1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
31 #include <asm/syscalls.h>
32 #include <linux/uaccess.h>
33 #include <asm/mwait.h>
34 #include <asm/fpu/internal.h>
35 #include <asm/debugreg.h>
37 #include <asm/tlbflush.h>
40 #include <asm/switch_to.h>
42 #include <asm/prctl.h>
43 #include <asm/spec-ctrl.h>
44 #include <asm/io_bitmap.h>
45 #include <asm/proto.h>
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
56 __visible
DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct
, cpu_tss_rw
) = {
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
64 .sp0
= (1UL << (BITS_PER_LONG
-1)) + 1,
67 * .sp1 is cpu_current_top_of_stack. The init task never
68 * runs user code, but cpu_current_top_of_stack should still
69 * be well defined before the first context switch.
71 .sp1
= TOP_OF_INIT_STACK
,
77 .io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
,
80 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw
);
82 DEFINE_PER_CPU(bool, __tss_limit_invalid
);
83 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid
);
86 * this gets called so that we can store lazy state into memory and copy the
87 * current task into the new thread.
89 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
91 memcpy(dst
, src
, arch_task_struct_size
);
93 dst
->thread
.vm86
= NULL
;
96 return fpu__copy(dst
, src
);
100 * Free current thread data structures etc..
102 void exit_thread(struct task_struct
*tsk
)
104 struct thread_struct
*t
= &tsk
->thread
;
105 struct fpu
*fpu
= &t
->fpu
;
107 if (test_thread_flag(TIF_IO_BITMAP
))
115 static int set_new_tls(struct task_struct
*p
, unsigned long tls
)
117 struct user_desc __user
*utls
= (struct user_desc __user
*)tls
;
119 if (in_ia32_syscall())
120 return do_set_thread_area(p
, -1, utls
, 0);
122 return do_set_thread_area_64(p
, ARCH_SET_FS
, tls
);
125 int copy_thread_tls(unsigned long clone_flags
, unsigned long sp
,
126 unsigned long arg
, struct task_struct
*p
, unsigned long tls
)
128 struct inactive_task_frame
*frame
;
129 struct fork_frame
*fork_frame
;
130 struct pt_regs
*childregs
;
133 childregs
= task_pt_regs(p
);
134 fork_frame
= container_of(childregs
, struct fork_frame
, regs
);
135 frame
= &fork_frame
->frame
;
138 frame
->ret_addr
= (unsigned long) ret_from_fork
;
139 p
->thread
.sp
= (unsigned long) fork_frame
;
140 p
->thread
.io_bitmap
= NULL
;
141 memset(p
->thread
.ptrace_bps
, 0, sizeof(p
->thread
.ptrace_bps
));
144 savesegment(gs
, p
->thread
.gsindex
);
145 p
->thread
.gsbase
= p
->thread
.gsindex
? 0 : current
->thread
.gsbase
;
146 savesegment(fs
, p
->thread
.fsindex
);
147 p
->thread
.fsbase
= p
->thread
.fsindex
? 0 : current
->thread
.fsbase
;
148 savesegment(es
, p
->thread
.es
);
149 savesegment(ds
, p
->thread
.ds
);
151 p
->thread
.sp0
= (unsigned long) (childregs
+ 1);
153 * Clear all status flags including IF and set fixed bit. 64bit
154 * does not have this initialization as the frame does not contain
155 * flags. The flags consistency (especially vs. AC) is there
156 * ensured via objtool, which lacks 32bit support.
158 frame
->flags
= X86_EFLAGS_FIXED
;
161 /* Kernel thread ? */
162 if (unlikely(p
->flags
& PF_KTHREAD
)) {
163 memset(childregs
, 0, sizeof(struct pt_regs
));
164 kthread_frame_init(frame
, sp
, arg
);
169 *childregs
= *current_pt_regs();
175 task_user_gs(p
) = get_user_gs(current_pt_regs());
178 /* Set a new TLS for the child thread? */
179 if (clone_flags
& CLONE_SETTLS
)
180 ret
= set_new_tls(p
, tls
);
182 if (!ret
&& unlikely(test_tsk_thread_flag(current
, TIF_IO_BITMAP
)))
188 void flush_thread(void)
190 struct task_struct
*tsk
= current
;
192 flush_ptrace_hw_breakpoint(tsk
);
193 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
195 fpu__clear(&tsk
->thread
.fpu
);
198 void disable_TSC(void)
201 if (!test_and_set_thread_flag(TIF_NOTSC
))
203 * Must flip the CPU state synchronously with
204 * TIF_NOTSC in the current running context.
206 cr4_set_bits(X86_CR4_TSD
);
210 static void enable_TSC(void)
213 if (test_and_clear_thread_flag(TIF_NOTSC
))
215 * Must flip the CPU state synchronously with
216 * TIF_NOTSC in the current running context.
218 cr4_clear_bits(X86_CR4_TSD
);
222 int get_tsc_mode(unsigned long adr
)
226 if (test_thread_flag(TIF_NOTSC
))
227 val
= PR_TSC_SIGSEGV
;
231 return put_user(val
, (unsigned int __user
*)adr
);
234 int set_tsc_mode(unsigned int val
)
236 if (val
== PR_TSC_SIGSEGV
)
238 else if (val
== PR_TSC_ENABLE
)
246 DEFINE_PER_CPU(u64
, msr_misc_features_shadow
);
248 static void set_cpuid_faulting(bool on
)
252 msrval
= this_cpu_read(msr_misc_features_shadow
);
253 msrval
&= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT
;
254 msrval
|= (on
<< MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT
);
255 this_cpu_write(msr_misc_features_shadow
, msrval
);
256 wrmsrl(MSR_MISC_FEATURES_ENABLES
, msrval
);
259 static void disable_cpuid(void)
262 if (!test_and_set_thread_flag(TIF_NOCPUID
)) {
264 * Must flip the CPU state synchronously with
265 * TIF_NOCPUID in the current running context.
267 set_cpuid_faulting(true);
272 static void enable_cpuid(void)
275 if (test_and_clear_thread_flag(TIF_NOCPUID
)) {
277 * Must flip the CPU state synchronously with
278 * TIF_NOCPUID in the current running context.
280 set_cpuid_faulting(false);
285 static int get_cpuid_mode(void)
287 return !test_thread_flag(TIF_NOCPUID
);
290 static int set_cpuid_mode(struct task_struct
*task
, unsigned long cpuid_enabled
)
292 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT
))
304 * Called immediately after a successful exec.
306 void arch_setup_new_exec(void)
308 /* If cpuid was previously disabled for this task, re-enable it. */
309 if (test_thread_flag(TIF_NOCPUID
))
313 * Don't inherit TIF_SSBD across exec boundary when
314 * PR_SPEC_DISABLE_NOEXEC is used.
316 if (test_thread_flag(TIF_SSBD
) &&
317 task_spec_ssb_noexec(current
)) {
318 clear_thread_flag(TIF_SSBD
);
319 task_clear_spec_ssb_disable(current
);
320 task_clear_spec_ssb_noexec(current
);
321 speculation_ctrl_update(task_thread_info(current
)->flags
);
325 static inline void tss_invalidate_io_bitmap(struct tss_struct
*tss
)
328 * Invalidate the I/O bitmap by moving io_bitmap_base outside the
329 * TSS limit so any subsequent I/O access from user space will
332 * This is correct even when VMEXIT rewrites the TSS limit
333 * to 0x67 as the only requirement is that the base points
336 tss
->x86_tss
.io_bitmap_base
= IO_BITMAP_OFFSET_INVALID
;
339 static inline void switch_to_bitmap(unsigned long tifp
)
342 * Invalidate I/O bitmap if the previous task used it. This prevents
343 * any possible leakage of an active I/O bitmap.
345 * If the next task has an I/O bitmap it will handle it on exit to
348 if (tifp
& _TIF_IO_BITMAP
)
349 tss_invalidate_io_bitmap(this_cpu_ptr(&cpu_tss_rw
));
352 static void tss_copy_io_bitmap(struct tss_struct
*tss
, struct io_bitmap
*iobm
)
355 * Copy at least the byte range of the incoming tasks bitmap which
356 * covers the permitted I/O ports.
358 * If the previous task which used an I/O bitmap had more bits
359 * permitted, then the copy needs to cover those as well so they
362 memcpy(tss
->io_bitmap
.bitmap
, iobm
->bitmap
,
363 max(tss
->io_bitmap
.prev_max
, iobm
->max
));
366 * Store the new max and the sequence number of this bitmap
367 * and a pointer to the bitmap itself.
369 tss
->io_bitmap
.prev_max
= iobm
->max
;
370 tss
->io_bitmap
.prev_sequence
= iobm
->sequence
;
374 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376 void tss_update_io_bitmap(void)
378 struct tss_struct
*tss
= this_cpu_ptr(&cpu_tss_rw
);
379 u16
*base
= &tss
->x86_tss
.io_bitmap_base
;
381 if (test_thread_flag(TIF_IO_BITMAP
)) {
382 struct thread_struct
*t
= ¤t
->thread
;
384 if (IS_ENABLED(CONFIG_X86_IOPL_EMULATION
) &&
386 *base
= IO_BITMAP_OFFSET_VALID_ALL
;
388 struct io_bitmap
*iobm
= t
->io_bitmap
;
390 * Only copy bitmap data when the sequence number
391 * differs. The update time is accounted to the
394 if (tss
->io_bitmap
.prev_sequence
!= iobm
->sequence
)
395 tss_copy_io_bitmap(tss
, iobm
);
397 /* Enable the bitmap */
398 *base
= IO_BITMAP_OFFSET_VALID_MAP
;
401 * Make sure that the TSS limit is covering the io bitmap.
402 * It might have been cut down by a VMEXIT to 0x67 which
403 * would cause a subsequent I/O access from user space to
404 * trigger a #GP because tbe bitmap is outside the TSS
409 tss_invalidate_io_bitmap(tss
);
416 struct ssb_state
*shared_state
;
418 unsigned int disable_state
;
419 unsigned long local_state
;
424 static DEFINE_PER_CPU(struct ssb_state
, ssb_state
);
426 void speculative_store_bypass_ht_init(void)
428 struct ssb_state
*st
= this_cpu_ptr(&ssb_state
);
429 unsigned int this_cpu
= smp_processor_id();
435 * Shared state setup happens once on the first bringup
436 * of the CPU. It's not destroyed on CPU hotunplug.
438 if (st
->shared_state
)
441 raw_spin_lock_init(&st
->lock
);
444 * Go over HT siblings and check whether one of them has set up the
445 * shared state pointer already.
447 for_each_cpu(cpu
, topology_sibling_cpumask(this_cpu
)) {
451 if (!per_cpu(ssb_state
, cpu
).shared_state
)
454 /* Link it to the state of the sibling: */
455 st
->shared_state
= per_cpu(ssb_state
, cpu
).shared_state
;
460 * First HT sibling to come up on the core. Link shared state of
461 * the first HT sibling to itself. The siblings on the same core
462 * which come up later will see the shared state pointer and link
463 * themself to the state of this CPU.
465 st
->shared_state
= st
;
469 * Logic is: First HT sibling enables SSBD for both siblings in the core
470 * and last sibling to disable it, disables it for the whole core. This how
471 * MSR_SPEC_CTRL works in "hardware":
473 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
475 static __always_inline
void amd_set_core_ssb_state(unsigned long tifn
)
477 struct ssb_state
*st
= this_cpu_ptr(&ssb_state
);
478 u64 msr
= x86_amd_ls_cfg_base
;
480 if (!static_cpu_has(X86_FEATURE_ZEN
)) {
481 msr
|= ssbd_tif_to_amd_ls_cfg(tifn
);
482 wrmsrl(MSR_AMD64_LS_CFG
, msr
);
486 if (tifn
& _TIF_SSBD
) {
488 * Since this can race with prctl(), block reentry on the
491 if (__test_and_set_bit(LSTATE_SSB
, &st
->local_state
))
494 msr
|= x86_amd_ls_cfg_ssbd_mask
;
496 raw_spin_lock(&st
->shared_state
->lock
);
497 /* First sibling enables SSBD: */
498 if (!st
->shared_state
->disable_state
)
499 wrmsrl(MSR_AMD64_LS_CFG
, msr
);
500 st
->shared_state
->disable_state
++;
501 raw_spin_unlock(&st
->shared_state
->lock
);
503 if (!__test_and_clear_bit(LSTATE_SSB
, &st
->local_state
))
506 raw_spin_lock(&st
->shared_state
->lock
);
507 st
->shared_state
->disable_state
--;
508 if (!st
->shared_state
->disable_state
)
509 wrmsrl(MSR_AMD64_LS_CFG
, msr
);
510 raw_spin_unlock(&st
->shared_state
->lock
);
514 static __always_inline
void amd_set_core_ssb_state(unsigned long tifn
)
516 u64 msr
= x86_amd_ls_cfg_base
| ssbd_tif_to_amd_ls_cfg(tifn
);
518 wrmsrl(MSR_AMD64_LS_CFG
, msr
);
522 static __always_inline
void amd_set_ssb_virt_state(unsigned long tifn
)
525 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
526 * so ssbd_tif_to_spec_ctrl() just works.
528 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL
, ssbd_tif_to_spec_ctrl(tifn
));
532 * Update the MSRs managing speculation control, during context switch.
534 * tifp: Previous task's thread flags
535 * tifn: Next task's thread flags
537 static __always_inline
void __speculation_ctrl_update(unsigned long tifp
,
540 unsigned long tif_diff
= tifp
^ tifn
;
541 u64 msr
= x86_spec_ctrl_base
;
544 lockdep_assert_irqs_disabled();
547 * If TIF_SSBD is different, select the proper mitigation
548 * method. Note that if SSBD mitigation is disabled or permanentely
549 * enabled this branch can't be taken because nothing can set
552 if (tif_diff
& _TIF_SSBD
) {
553 if (static_cpu_has(X86_FEATURE_VIRT_SSBD
)) {
554 amd_set_ssb_virt_state(tifn
);
555 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD
)) {
556 amd_set_core_ssb_state(tifn
);
557 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD
) ||
558 static_cpu_has(X86_FEATURE_AMD_SSBD
)) {
559 msr
|= ssbd_tif_to_spec_ctrl(tifn
);
565 * Only evaluate TIF_SPEC_IB if conditional STIBP is enabled,
566 * otherwise avoid the MSR write.
568 if (IS_ENABLED(CONFIG_SMP
) &&
569 static_branch_unlikely(&switch_to_cond_stibp
)) {
570 updmsr
|= !!(tif_diff
& _TIF_SPEC_IB
);
571 msr
|= stibp_tif_to_spec_ctrl(tifn
);
575 wrmsrl(MSR_IA32_SPEC_CTRL
, msr
);
578 static unsigned long speculation_ctrl_update_tif(struct task_struct
*tsk
)
580 if (test_and_clear_tsk_thread_flag(tsk
, TIF_SPEC_FORCE_UPDATE
)) {
581 if (task_spec_ssb_disable(tsk
))
582 set_tsk_thread_flag(tsk
, TIF_SSBD
);
584 clear_tsk_thread_flag(tsk
, TIF_SSBD
);
586 if (task_spec_ib_disable(tsk
))
587 set_tsk_thread_flag(tsk
, TIF_SPEC_IB
);
589 clear_tsk_thread_flag(tsk
, TIF_SPEC_IB
);
591 /* Return the updated threadinfo flags*/
592 return task_thread_info(tsk
)->flags
;
595 void speculation_ctrl_update(unsigned long tif
)
599 /* Forced update. Make sure all relevant TIF flags are different */
600 local_irq_save(flags
);
601 __speculation_ctrl_update(~tif
, tif
);
602 local_irq_restore(flags
);
605 /* Called from seccomp/prctl update */
606 void speculation_ctrl_update_current(void)
609 speculation_ctrl_update(speculation_ctrl_update_tif(current
));
613 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
)
615 struct thread_struct
*prev
, *next
;
616 unsigned long tifp
, tifn
;
618 prev
= &prev_p
->thread
;
619 next
= &next_p
->thread
;
621 tifn
= READ_ONCE(task_thread_info(next_p
)->flags
);
622 tifp
= READ_ONCE(task_thread_info(prev_p
)->flags
);
624 switch_to_bitmap(tifp
);
626 propagate_user_return_notify(prev_p
, next_p
);
628 if ((tifp
& _TIF_BLOCKSTEP
|| tifn
& _TIF_BLOCKSTEP
) &&
629 arch_has_block_step()) {
630 unsigned long debugctl
, msk
;
632 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
633 debugctl
&= ~DEBUGCTLMSR_BTF
;
634 msk
= tifn
& _TIF_BLOCKSTEP
;
635 debugctl
|= (msk
>> TIF_BLOCKSTEP
) << DEBUGCTLMSR_BTF_SHIFT
;
636 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
639 if ((tifp
^ tifn
) & _TIF_NOTSC
)
640 cr4_toggle_bits_irqsoff(X86_CR4_TSD
);
642 if ((tifp
^ tifn
) & _TIF_NOCPUID
)
643 set_cpuid_faulting(!!(tifn
& _TIF_NOCPUID
));
645 if (likely(!((tifp
| tifn
) & _TIF_SPEC_FORCE_UPDATE
))) {
646 __speculation_ctrl_update(tifp
, tifn
);
648 speculation_ctrl_update_tif(prev_p
);
649 tifn
= speculation_ctrl_update_tif(next_p
);
651 /* Enforce MSR update to ensure consistent state */
652 __speculation_ctrl_update(~tifn
, tifn
);
657 * Idle related variables and functions
659 unsigned long boot_option_idle_override
= IDLE_NO_OVERRIDE
;
660 EXPORT_SYMBOL(boot_option_idle_override
);
662 static void (*x86_idle
)(void);
665 static inline void play_dead(void)
671 void arch_cpu_idle_enter(void)
673 tsc_verify_tsc_adjust(false);
677 void arch_cpu_idle_dead(void)
683 * Called from the generic idle code.
685 void arch_cpu_idle(void)
691 * We use this if we don't have any better idle routine..
693 void __cpuidle
default_idle(void)
695 trace_cpu_idle_rcuidle(1, smp_processor_id());
697 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
699 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
700 EXPORT_SYMBOL(default_idle
);
704 bool xen_set_default_idle(void)
706 bool ret
= !!x86_idle
;
708 x86_idle
= default_idle
;
714 void stop_this_cpu(void *dummy
)
720 set_cpu_online(smp_processor_id(), false);
721 disable_local_APIC();
722 mcheck_cpu_clear(this_cpu_ptr(&cpu_info
));
725 * Use wbinvd on processors that support SME. This provides support
726 * for performing a successful kexec when going from SME inactive
727 * to SME active (or vice-versa). The cache must be cleared so that
728 * if there are entries with the same physical address, both with and
729 * without the encryption bit, they don't race each other when flushed
730 * and potentially end up with the wrong entry being committed to
733 if (boot_cpu_has(X86_FEATURE_SME
))
737 * Use native_halt() so that memory contents don't change
738 * (stack usage and variables) after possibly issuing the
739 * native_wbinvd() above.
746 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
747 * states (local apic timer and TSC stop).
749 static void amd_e400_idle(void)
752 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
753 * gets set after static_cpu_has() places have been converted via
756 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E
)) {
761 tick_broadcast_enter();
766 * The switch back from broadcast mode needs to be called with
767 * interrupts disabled.
770 tick_broadcast_exit();
775 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
776 * We can't rely on cpuidle installing MWAIT, because it will not load
777 * on systems that support only C1 -- so the boot default must be MWAIT.
779 * Some AMD machines are the opposite, they depend on using HALT.
781 * So for default C1, which is used during boot until cpuidle loads,
782 * use MWAIT-C1 on Intel HW that has it, else use HALT.
784 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86
*c
)
786 if (c
->x86_vendor
!= X86_VENDOR_INTEL
)
789 if (!cpu_has(c
, X86_FEATURE_MWAIT
) || boot_cpu_has_bug(X86_BUG_MONITOR
))
796 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
797 * with interrupts enabled and no flags, which is backwards compatible with the
798 * original MWAIT implementation.
800 static __cpuidle
void mwait_idle(void)
802 if (!current_set_polling_and_test()) {
803 trace_cpu_idle_rcuidle(1, smp_processor_id());
804 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR
)) {
806 clflush((void *)¤t_thread_info()->flags
);
810 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
815 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT
, smp_processor_id());
819 __current_clr_polling();
822 void select_idle_routine(const struct cpuinfo_x86
*c
)
825 if (boot_option_idle_override
== IDLE_POLL
&& smp_num_siblings
> 1)
826 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
828 if (x86_idle
|| boot_option_idle_override
== IDLE_POLL
)
831 if (boot_cpu_has_bug(X86_BUG_AMD_E400
)) {
832 pr_info("using AMD E400 aware idle routine\n");
833 x86_idle
= amd_e400_idle
;
834 } else if (prefer_mwait_c1_over_halt(c
)) {
835 pr_info("using mwait in idle threads\n");
836 x86_idle
= mwait_idle
;
838 x86_idle
= default_idle
;
841 void amd_e400_c1e_apic_setup(void)
843 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E
)) {
844 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
846 tick_broadcast_force();
851 void __init
arch_post_acpi_subsys_init(void)
855 if (!boot_cpu_has_bug(X86_BUG_AMD_E400
))
859 * AMD E400 detection needs to happen after ACPI has been enabled. If
860 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
861 * MSR_K8_INT_PENDING_MSG.
863 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
864 if (!(lo
& K8_INTP_C1E_ACTIVE_MASK
))
867 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E
);
869 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
870 mark_tsc_unstable("TSC halt in AMD C1E");
871 pr_info("System has AMD C1E enabled\n");
874 static int __init
idle_setup(char *str
)
879 if (!strcmp(str
, "poll")) {
880 pr_info("using polling idle threads\n");
881 boot_option_idle_override
= IDLE_POLL
;
882 cpu_idle_poll_ctrl(true);
883 } else if (!strcmp(str
, "halt")) {
885 * When the boot option of idle=halt is added, halt is
886 * forced to be used for CPU idle. In such case CPU C2/C3
887 * won't be used again.
888 * To continue to load the CPU idle driver, don't touch
889 * the boot_option_idle_override.
891 x86_idle
= default_idle
;
892 boot_option_idle_override
= IDLE_HALT
;
893 } else if (!strcmp(str
, "nomwait")) {
895 * If the boot option of "idle=nomwait" is added,
896 * it means that mwait will be disabled for CPU C2/C3
897 * states. In such case it won't touch the variable
898 * of boot_option_idle_override.
900 boot_option_idle_override
= IDLE_NOMWAIT
;
906 early_param("idle", idle_setup
);
908 unsigned long arch_align_stack(unsigned long sp
)
910 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
911 sp
-= get_random_int() % 8192;
915 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
917 return randomize_page(mm
->brk
, 0x02000000);
921 * Called from fs/proc with a reference on @p to find the function
922 * which called into schedule(). This needs to be done carefully
923 * because the task might wake up and we might look at a stack
926 unsigned long get_wchan(struct task_struct
*p
)
928 unsigned long start
, bottom
, top
, sp
, fp
, ip
, ret
= 0;
931 if (p
== current
|| p
->state
== TASK_RUNNING
)
934 if (!try_get_task_stack(p
))
937 start
= (unsigned long)task_stack_page(p
);
942 * Layout of the stack page:
944 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
946 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
948 * ----------- bottom = start
950 * The tasks stack pointer points at the location where the
951 * framepointer is stored. The data on the stack is:
952 * ... IP FP ... IP FP
954 * We need to read FP and IP, so we need to adjust the upper
955 * bound by another unsigned long.
957 top
= start
+ THREAD_SIZE
- TOP_OF_KERNEL_STACK_PADDING
;
958 top
-= 2 * sizeof(unsigned long);
961 sp
= READ_ONCE(p
->thread
.sp
);
962 if (sp
< bottom
|| sp
> top
)
965 fp
= READ_ONCE_NOCHECK(((struct inactive_task_frame
*)sp
)->bp
);
967 if (fp
< bottom
|| fp
> top
)
969 ip
= READ_ONCE_NOCHECK(*(unsigned long *)(fp
+ sizeof(unsigned long)));
970 if (!in_sched_functions(ip
)) {
974 fp
= READ_ONCE_NOCHECK(*(unsigned long *)fp
);
975 } while (count
++ < 16 && p
->state
!= TASK_RUNNING
);
982 long do_arch_prctl_common(struct task_struct
*task
, int option
,
983 unsigned long cpuid_enabled
)
987 return get_cpuid_mode();
989 return set_cpuid_mode(task
, cpuid_enabled
);