arch/x86/kernel/smp.c

   1 /*
   2  *      Intel SMP support routines.
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   5  *      (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   6  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
   7  *
   8  *      i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
   9  *
  10  *      This code is released under the GNU General Public License version 2 or
  11  *      later.
  12  */
  13
  14 #include <linux/init.h>
  15
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/export.h>
  20 #include <linux/kernel_stat.h>
  21 #include <linux/mc146818rtc.h>
  22 #include <linux/cache.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/cpu.h>
  25 #include <linux/gfp.h>
  26
  27 #include <asm/mtrr.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/proto.h>
  31 #include <asm/apic.h>
  32 #include <asm/nmi.h>
  33 #include <asm/mce.h>
  34 #include <asm/trace/irq_vectors.h>
  35 #include <asm/kexec.h>
  36 #include <asm/virtext.h>
  37
  38 /*
  39  *      Some notes on x86 processor bugs affecting SMP operation:
  40  *
  41  *      Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
  42  *      The Linux implications for SMP are handled as follows:
  43  *
  44  *      Pentium III / [Xeon]
  45  *              None of the E1AP-E3AP errata are visible to the user.
  46  *
  47  *      E1AP.   see PII A1AP
  48  *      E2AP.   see PII A2AP
  49  *      E3AP.   see PII A3AP
  50  *
  51  *      Pentium II / [Xeon]
  52  *              None of the A1AP-A3AP errata are visible to the user.
  53  *
  54  *      A1AP.   see PPro 1AP
  55  *      A2AP.   see PPro 2AP
  56  *      A3AP.   see PPro 7AP
  57  *
  58  *      Pentium Pro
  59  *              None of 1AP-9AP errata are visible to the normal user,
  60  *      except occasional delivery of 'spurious interrupt' as trap #15.
  61  *      This is very rare and a non-problem.
  62  *
  63  *      1AP.    Linux maps APIC as non-cacheable
  64  *      2AP.    worked around in hardware
  65  *      3AP.    fixed in C0 and above steppings microcode update.
  66  *              Linux does not use excessive STARTUP_IPIs.
  67  *      4AP.    worked around in hardware
  68  *      5AP.    symmetric IO mode (normal Linux operation) not affected.
  69  *              'noapic' mode has vector 0xf filled out properly.
  70  *      6AP.    'noapic' mode might be affected - fixed in later steppings
  71  *      7AP.    We do not assume writes to the LVT deassering IRQs
  72  *      8AP.    We do not enable low power mode (deep sleep) during MP bootup
  73  *      9AP.    We do not use mixed mode
  74  *
  75  *      Pentium
  76  *              There is a marginal case where REP MOVS on 100MHz SMP
  77  *      machines with B stepping processors can fail. XXX should provide
  78  *      an L1cache=Writethrough or L1cache=off option.
  79  *
  80  *              B stepping CPUs may hang. There are hardware work arounds
  81  *      for this. We warn about it in case your board doesn't have the work
  82  *      arounds. Basically that's so I can tell anyone with a B stepping
  83  *      CPU and SMP problems "tough".
  84  *
  85  *      Specific items [From Pentium Processor Specification Update]
  86  *
  87  *      1AP.    Linux doesn't use remote read
  88  *      2AP.    Linux doesn't trust APIC errors
  89  *      3AP.    We work around this
  90  *      4AP.    Linux never generated 3 interrupts of the same priority
  91  *              to cause a lost local interrupt.
  92  *      5AP.    Remote read is never used
  93  *      6AP.    not affected - worked around in hardware
  94  *      7AP.    not affected - worked around in hardware
  95  *      8AP.    worked around in hardware - we get explicit CS errors if not
  96  *      9AP.    only 'noapic' mode affected. Might generate spurious
  97  *              interrupts, we log only the first one and count the
  98  *              rest silently.
  99  *      10AP.   not affected - worked around in hardware
 100  *      11AP.   Linux reads the APIC between writes to avoid this, as per
 101  *              the documentation. Make sure you preserve this as it affects
 102  *              the C stepping chips too.
 103  *      12AP.   not affected - worked around in hardware
 104  *      13AP.   not affected - worked around in hardware
 105  *      14AP.   we always deassert INIT during bootup
 106  *      15AP.   not affected - worked around in hardware
 107  *      16AP.   not affected - worked around in hardware
 108  *      17AP.   not affected - worked around in hardware
 109  *      18AP.   not affected - worked around in hardware
 110  *      19AP.   not affected - worked around in BIOS
 111  *
 112  *      If this sounds worrying believe me these bugs are either ___RARE___,
 113  *      or are signal timing bugs worked around in hardware and there's
 114  *      about nothing of note with C stepping upwards.
 115  */
 116
 117 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
 118 static bool smp_no_nmi_ipi = false;
 119
 120 /*
 121  * this function sends a 'reschedule' IPI to another CPU.
 122  * it goes straight through and wastes no time serializing
 123  * anything. Worst case is that we lose a reschedule ...
 124  */
 125 static void native_smp_send_reschedule(int cpu)
 126 {
 127         if (unlikely(cpu_is_offline(cpu))) {
 128                 WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu);
 129                 return;
 130         }
 131         apic->send_IPI(cpu, RESCHEDULE_VECTOR);
 132 }
 133
 134 void native_send_call_func_single_ipi(int cpu)
 135 {
 136         apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR);
 137 }
 138
 139 void native_send_call_func_ipi(const struct cpumask *mask)
 140 {
 141         cpumask_var_t allbutself;
 142
 143         if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
 144                 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
 145                 return;
 146         }
 147
 148         cpumask_copy(allbutself, cpu_online_mask);
 149         cpumask_clear_cpu(smp_processor_id(), allbutself);
 150
 151         if (cpumask_equal(mask, allbutself) &&
 152             cpumask_equal(cpu_online_mask, cpu_callout_mask))
 153                 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
 154         else
 155                 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
 156
 157         free_cpumask_var(allbutself);
 158 }
 159
 160 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
 161 {
 162         /* We are registered on stopping cpu too, avoid spurious NMI */
 163         if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
 164                 return NMI_HANDLED;
 165
 166         cpu_emergency_vmxoff();
 167         stop_this_cpu(NULL);
 168
 169         return NMI_HANDLED;
 170 }
 171
 172 /*
 173  * this function calls the 'stop' function on all other CPUs in the system.
 174  */
 175
 176 asmlinkage __visible void smp_reboot_interrupt(void)
 177 {
 178         ipi_entering_ack_irq();
 179         cpu_emergency_vmxoff();
 180         stop_this_cpu(NULL);
 181         irq_exit();
 182 }
 183
 184 static void native_stop_other_cpus(int wait)
 185 {
 186         unsigned long flags;
 187         unsigned long timeout;
 188
 189         if (reboot_force)
 190                 return;
 191
 192         /*
 193          * Use an own vector here because smp_call_function
 194          * does lots of things not suitable in a panic situation.
 195          */
 196
 197         /*
 198          * We start by using the REBOOT_VECTOR irq.
 199          * The irq is treated as a sync point to allow critical
 200          * regions of code on other cpus to release their spin locks
 201          * and re-enable irqs.  Jumping straight to an NMI might
 202          * accidentally cause deadlocks with further shutdown/panic
 203          * code.  By syncing, we give the cpus up to one second to
 204          * finish their work before we force them off with the NMI.
 205          */
 206         if (num_online_cpus() > 1) {
 207                 /* did someone beat us here? */
 208                 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
 209                         return;
 210
 211                 /* sync above data before sending IRQ */
 212                 wmb();
 213
 214                 apic->send_IPI_allbutself(REBOOT_VECTOR);
 215
 216                 /*
 217                  * Don't wait longer than a second if the caller
 218                  * didn't ask us to wait.
 219                  */
 220                 timeout = USEC_PER_SEC;
 221                 while (num_online_cpus() > 1 && (wait || timeout--))
 222                         udelay(1);
 223         }
 224
 225         /* if the REBOOT_VECTOR didn't work, try with the NMI */
 226         if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi))  {
 227                 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
 228                                          NMI_FLAG_FIRST, "smp_stop"))
 229                         /* Note: we ignore failures here */
 230                         /* Hope the REBOOT_IRQ is good enough */
 231                         goto finish;
 232
 233                 /* sync above data before sending IRQ */
 234                 wmb();
 235
 236                 pr_emerg("Shutting down cpus with NMI\n");
 237
 238                 apic->send_IPI_allbutself(NMI_VECTOR);
 239
 240                 /*
 241                  * Don't wait longer than a 10 ms if the caller
 242                  * didn't ask us to wait.
 243                  */
 244                 timeout = USEC_PER_MSEC * 10;
 245                 while (num_online_cpus() > 1 && (wait || timeout--))
 246                         udelay(1);
 247         }
 248
 249 finish:
 250         local_irq_save(flags);
 251         disable_local_APIC();
 252         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 253         local_irq_restore(flags);
 254 }
 255
 256 /*
 257  * Reschedule call back.
 258  */
 259 static inline void __smp_reschedule_interrupt(void)
 260 {
 261         inc_irq_stat(irq_resched_count);
 262         scheduler_ipi();
 263 }
 264
 265 __visible void __irq_entry smp_reschedule_interrupt(struct pt_regs *regs)
 266 {
 267         ack_APIC_irq();
 268         __smp_reschedule_interrupt();
 269         /*
 270          * KVM uses this interrupt to force a cpu out of guest mode
 271          */
 272 }
 273
 274 __visible void __irq_entry smp_trace_reschedule_interrupt(struct pt_regs *regs)
 275 {
 276         /*
 277          * Need to call irq_enter() before calling the trace point.
 278          * __smp_reschedule_interrupt() calls irq_enter/exit() too (in
 279          * scheduler_ipi(). This is OK, since those functions are allowed
 280          * to nest.
 281          */
 282         ipi_entering_ack_irq();
 283         trace_reschedule_entry(RESCHEDULE_VECTOR);
 284         __smp_reschedule_interrupt();
 285         trace_reschedule_exit(RESCHEDULE_VECTOR);
 286         exiting_irq();
 287         /*
 288          * KVM uses this interrupt to force a cpu out of guest mode
 289          */
 290 }
 291
 292 static inline void __smp_call_function_interrupt(void)
 293 {
 294         generic_smp_call_function_interrupt();
 295         inc_irq_stat(irq_call_count);
 296 }
 297
 298 __visible void __irq_entry smp_call_function_interrupt(struct pt_regs *regs)
 299 {
 300         ipi_entering_ack_irq();
 301         __smp_call_function_interrupt();
 302         exiting_irq();
 303 }
 304
 305 __visible void __irq_entry
 306 smp_trace_call_function_interrupt(struct pt_regs *regs)
 307 {
 308         ipi_entering_ack_irq();
 309         trace_call_function_entry(CALL_FUNCTION_VECTOR);
 310         __smp_call_function_interrupt();
 311         trace_call_function_exit(CALL_FUNCTION_VECTOR);
 312         exiting_irq();
 313 }
 314
 315 static inline void __smp_call_function_single_interrupt(void)
 316 {
 317         generic_smp_call_function_single_interrupt();
 318         inc_irq_stat(irq_call_count);
 319 }
 320
 321 __visible void __irq_entry
 322 smp_call_function_single_interrupt(struct pt_regs *regs)
 323 {
 324         ipi_entering_ack_irq();
 325         __smp_call_function_single_interrupt();
 326         exiting_irq();
 327 }
 328
 329 __visible void __irq_entry
 330 smp_trace_call_function_single_interrupt(struct pt_regs *regs)
 331 {
 332         ipi_entering_ack_irq();
 333         trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
 334         __smp_call_function_single_interrupt();
 335         trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
 336         exiting_irq();
 337 }
 338
 339 static int __init nonmi_ipi_setup(char *str)
 340 {
 341         smp_no_nmi_ipi = true;
 342         return 1;
 343 }
 344
 345 __setup("nonmi_ipi", nonmi_ipi_setup);
 346
 347 struct smp_ops smp_ops = {
 348         .smp_prepare_boot_cpu   = native_smp_prepare_boot_cpu,
 349         .smp_prepare_cpus       = native_smp_prepare_cpus,
 350         .smp_cpus_done          = native_smp_cpus_done,
 351
 352         .stop_other_cpus        = native_stop_other_cpus,
 353 #if defined(CONFIG_KEXEC_CORE)
 354         .crash_stop_other_cpus  = kdump_nmi_shootdown_cpus,
 355 #endif
 356         .smp_send_reschedule    = native_smp_send_reschedule,
 357
 358         .cpu_up                 = native_cpu_up,
 359         .cpu_die                = native_cpu_die,
 360         .cpu_disable            = native_cpu_disable,
 361         .play_dead              = native_play_dead,
 362
 363         .send_call_func_ipi     = native_send_call_func_ipi,
 364         .send_call_func_single_ipi = native_send_call_func_single_ipi,
 365 };
 366 EXPORT_SYMBOL_GPL(smp_ops);