2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* Number of siblings per CPU package */
82 int smp_num_siblings
= 1;
83 EXPORT_SYMBOL(smp_num_siblings
);
85 /* Last level cache ID of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
88 /* representing HT siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
92 /* representing HT and core siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
94 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
100 EXPORT_PER_CPU_SYMBOL(cpu_info
);
102 /* Logical package management. We might want to allocate that dynamically */
103 static int *physical_to_logical_pkg __read_mostly
;
104 static unsigned long *physical_package_map __read_mostly
;;
105 static unsigned int max_physical_pkg_id __read_mostly
;
106 unsigned int __max_logical_packages __read_mostly
;
107 EXPORT_SYMBOL(__max_logical_packages
);
108 static unsigned int logical_packages __read_mostly
;
110 /* Maximum number of SMT threads on any online core */
111 int __max_smt_threads __read_mostly
;
113 /* Flag to indicate if a complete sched domain rebuild is required */
114 bool x86_topology_update
;
116 int arch_update_cpu_topology(void)
118 int retval
= x86_topology_update
;
120 x86_topology_update
= false;
124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
128 spin_lock_irqsave(&rtc_lock
, flags
);
129 CMOS_WRITE(0xa, 0xf);
130 spin_unlock_irqrestore(&rtc_lock
, flags
);
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
141 static inline void smpboot_restore_warm_reset_vector(void)
146 * Install writable page 0 entry to set BIOS data area.
151 * Paranoid: Set warm reset code and vector here back
154 spin_lock_irqsave(&rtc_lock
, flags
);
156 spin_unlock_irqrestore(&rtc_lock
, flags
);
158 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
162 * Report back to the Boot Processor during boot time or to the caller processor
165 static void smp_callin(void)
170 * If waken up by an INIT in an 82489DX configuration
171 * cpu_callout_mask guarantees we don't get here before
172 * an INIT_deassert IPI reaches our local APIC, so it is
173 * now safe to touch our local APIC.
175 cpuid
= smp_processor_id();
178 * (This works even if the APIC is not enabled.)
180 phys_id
= read_apic_id();
183 * the boot CPU has finished the init stage and is spinning
184 * on callin_map until we finish. We are free to set up this
185 * CPU, first the APIC. (this is probably redundant on most
191 * Save our processor parameters. Note: this information
192 * is needed for clock calibration.
194 smp_store_cpu_info(cpuid
);
198 * Update loops_per_jiffy in cpu_data. Previous call to
199 * smp_store_cpu_info() stored a value that is close but not as
200 * accurate as the value just calculated.
203 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
204 pr_debug("Stack at about %p\n", &cpuid
);
207 * This must be done before setting cpu_online_mask
208 * or calling notify_cpu_starting.
210 set_cpu_sibling_map(raw_smp_processor_id());
213 notify_cpu_starting(cpuid
);
216 * Allow the master to continue.
218 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
221 static int cpu0_logical_apicid
;
222 static int enable_start_cpu0
;
224 * Activate a secondary processor.
226 static void notrace
start_secondary(void *unused
)
229 * Don't put *anything* except direct CPU state initialization
230 * before cpu_init(), SMP booting is too fragile that we want to
231 * limit the things done here to the most necessary things.
233 if (boot_cpu_has(X86_FEATURE_PCID
))
234 __write_cr4(__read_cr4() | X86_CR4_PCIDE
);
236 x86_cpuinit
.early_percpu_clock_init();
240 enable_start_cpu0
= 0;
243 /* switch away from the initial page table */
244 load_cr3(swapper_pg_dir
);
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the BP:
253 check_tsc_sync_target();
256 * Lock vector_lock and initialize the vectors on this cpu
257 * before setting the cpu online. We must set it online with
258 * vector_lock held to prevent a concurrent setup/teardown
259 * from seeing a half valid vector space.
262 setup_vector_irq(smp_processor_id());
263 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform
.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit
.setup_percpu_clockev();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
281 * topology_update_package_map - Update the physical to logical package map
282 * @pkg: The physical package id as retrieved via CPUID
283 * @cpu: The cpu for which this is updated
285 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
289 /* Called from early boot ? */
290 if (!physical_package_map
)
293 if (pkg
>= max_physical_pkg_id
)
296 /* Set the logical package id */
297 if (test_and_set_bit(pkg
, physical_package_map
))
300 if (logical_packages
>= __max_logical_packages
) {
301 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
302 logical_packages
, cpu
, __max_logical_packages
);
306 new = logical_packages
++;
308 pr_info("CPU %u Converting physical %u to logical package %u\n",
311 physical_to_logical_pkg
[pkg
] = new;
314 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
319 * topology_phys_to_logical_pkg - Map a physical package id to a logical
321 * Returns logical package id or -1 if not found
323 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
325 if (phys_pkg
>= max_physical_pkg_id
)
327 return physical_to_logical_pkg
[phys_pkg
];
329 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
331 static void __init
smp_init_package_map(struct cpuinfo_x86
*c
, unsigned int cpu
)
337 * Today neither Intel nor AMD support heterogenous systems. That
338 * might change in the future....
340 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
341 * computation, this won't actually work since some Intel BIOSes
342 * report inconsistent HT data when they disable HT.
344 * In particular, they reduce the APIC-IDs to only include the cores,
345 * but leave the CPUID topology to say there are (2) siblings.
346 * This means we don't know how many threads there will be until
347 * after the APIC enumeration.
349 * By not including this we'll sometimes over-estimate the number of
350 * logical packages by the amount of !present siblings, but this is
351 * still better than MAX_LOCAL_APIC.
353 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
354 * on the command line leading to a similar issue as the HT disable
355 * problem because the hyperthreads are usually enumerated after the
358 ncpus
= boot_cpu_data
.x86_max_cores
;
360 pr_warn("x86_max_cores == zero !?!?");
364 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
365 logical_packages
= 0;
368 * Possibly larger than what we need as the number of apic ids per
369 * package can be smaller than the actual used apic ids.
371 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
372 size
= max_physical_pkg_id
* sizeof(unsigned int);
373 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
374 memset(physical_to_logical_pkg
, 0xff, size
);
375 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
376 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
378 pr_info("Max logical packages: %u\n", __max_logical_packages
);
380 topology_update_package_map(c
->phys_proc_id
, cpu
);
383 void __init
smp_store_boot_cpu_info(void)
385 int id
= 0; /* CPU 0 */
386 struct cpuinfo_x86
*c
= &cpu_data(id
);
390 smp_init_package_map(c
, id
);
394 * The bootstrap kernel entry code has set these up. Save them for
397 void smp_store_cpu_info(int id
)
399 struct cpuinfo_x86
*c
= &cpu_data(id
);
404 * During boot time, CPU0 has this setup already. Save the info when
405 * bringing up AP or offlined CPU0.
407 identify_secondary_cpu(c
);
411 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
413 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
415 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
419 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
421 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
423 return !WARN_ONCE(!topology_same_node(c
, o
),
424 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
425 "[node: %d != %d]. Ignoring dependency.\n",
426 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
429 #define link_mask(mfunc, c1, c2) \
431 cpumask_set_cpu((c1), mfunc(c2)); \
432 cpumask_set_cpu((c2), mfunc(c1)); \
435 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
437 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
438 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
440 if (c
->phys_proc_id
== o
->phys_proc_id
&&
441 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
442 if (c
->cpu_core_id
== o
->cpu_core_id
)
443 return topology_sane(c
, o
, "smt");
445 if ((c
->cu_id
!= 0xff) &&
446 (o
->cu_id
!= 0xff) &&
447 (c
->cu_id
== o
->cu_id
))
448 return topology_sane(c
, o
, "smt");
451 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
452 c
->cpu_core_id
== o
->cpu_core_id
) {
453 return topology_sane(c
, o
, "smt");
459 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
461 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
463 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
464 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
465 return topology_sane(c
, o
, "llc");
471 * Unlike the other levels, we do not enforce keeping a
472 * multicore group inside a NUMA node. If this happens, we will
473 * discard the MC level of the topology later.
475 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
477 if (c
->phys_proc_id
== o
->phys_proc_id
)
482 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
483 static inline int x86_sched_itmt_flags(void)
485 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
488 #ifdef CONFIG_SCHED_MC
489 static int x86_core_flags(void)
491 return cpu_core_flags() | x86_sched_itmt_flags();
494 #ifdef CONFIG_SCHED_SMT
495 static int x86_smt_flags(void)
497 return cpu_smt_flags() | x86_sched_itmt_flags();
502 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
503 #ifdef CONFIG_SCHED_SMT
504 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
506 #ifdef CONFIG_SCHED_MC
507 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
512 static struct sched_domain_topology_level x86_topology
[] = {
513 #ifdef CONFIG_SCHED_SMT
514 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
516 #ifdef CONFIG_SCHED_MC
517 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
519 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
524 * Set if a package/die has multiple NUMA nodes inside.
525 * AMD Magny-Cours and Intel Cluster-on-Die have this.
527 static bool x86_has_numa_in_package
;
529 void set_cpu_sibling_map(int cpu
)
531 bool has_smt
= smp_num_siblings
> 1;
532 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
533 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
534 struct cpuinfo_x86
*o
;
537 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
540 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
541 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
542 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
547 for_each_cpu(i
, cpu_sibling_setup_mask
) {
550 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
551 link_mask(topology_sibling_cpumask
, cpu
, i
);
553 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
554 link_mask(cpu_llc_shared_mask
, cpu
, i
);
559 * This needs a separate iteration over the cpus because we rely on all
560 * topology_sibling_cpumask links to be set-up.
562 for_each_cpu(i
, cpu_sibling_setup_mask
) {
565 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
566 link_mask(topology_core_cpumask
, cpu
, i
);
569 * Does this new cpu bringup a new core?
572 topology_sibling_cpumask(cpu
)) == 1) {
574 * for each core in package, increment
575 * the booted_cores for this new cpu
578 topology_sibling_cpumask(i
)) == i
)
581 * increment the core count for all
582 * the other cpus in this package
585 cpu_data(i
).booted_cores
++;
586 } else if (i
!= cpu
&& !c
->booted_cores
)
587 c
->booted_cores
= cpu_data(i
).booted_cores
;
589 if (match_die(c
, o
) && !topology_same_node(c
, o
))
590 x86_has_numa_in_package
= true;
593 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
594 if (threads
> __max_smt_threads
)
595 __max_smt_threads
= threads
;
598 /* maps the cpu to the sched domain representing multi-core */
599 const struct cpumask
*cpu_coregroup_mask(int cpu
)
601 return cpu_llc_shared_mask(cpu
);
604 static void impress_friends(void)
607 unsigned long bogosum
= 0;
609 * Allow the user to impress friends.
611 pr_debug("Before bogomips\n");
612 for_each_possible_cpu(cpu
)
613 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
614 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
615 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
618 (bogosum
/(5000/HZ
))%100);
620 pr_debug("Before bogocount - setting activated=1\n");
623 void __inquire_remote_apic(int apicid
)
625 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
626 const char * const names
[] = { "ID", "VERSION", "SPIV" };
630 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
632 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
633 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
638 status
= safe_apic_wait_icr_idle();
640 pr_cont("a previous APIC delivery may have failed\n");
642 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
647 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
648 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
651 case APIC_ICR_RR_VALID
:
652 status
= apic_read(APIC_RRR
);
653 pr_cont("%08x\n", status
);
662 * The Multiprocessor Specification 1.4 (1997) example code suggests
663 * that there should be a 10ms delay between the BSP asserting INIT
664 * and de-asserting INIT, when starting a remote processor.
665 * But that slows boot and resume on modern processors, which include
666 * many cores and don't require that delay.
668 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
669 * Modern processor families are quirked to remove the delay entirely.
671 #define UDELAY_10MS_DEFAULT 10000
673 static unsigned int init_udelay
= UINT_MAX
;
675 static int __init
cpu_init_udelay(char *str
)
677 get_option(&str
, &init_udelay
);
681 early_param("cpu_init_udelay", cpu_init_udelay
);
683 static void __init
smp_quirk_init_udelay(void)
685 /* if cmdline changed it from default, leave it alone */
686 if (init_udelay
!= UINT_MAX
)
689 /* if modern processor, use no delay */
690 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
691 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
695 /* else, use legacy delay */
696 init_udelay
= UDELAY_10MS_DEFAULT
;
700 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
701 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
702 * won't ... remember to clear down the APIC, etc later.
705 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
707 unsigned long send_status
, accept_status
= 0;
711 /* Boot on the stack */
712 /* Kick the second */
713 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
715 pr_debug("Waiting for send to finish...\n");
716 send_status
= safe_apic_wait_icr_idle();
719 * Give the other CPU some time to accept the IPI.
722 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
723 maxlvt
= lapic_get_maxlvt();
724 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
725 apic_write(APIC_ESR
, 0);
726 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
728 pr_debug("NMI sent\n");
731 pr_err("APIC never delivered???\n");
733 pr_err("APIC delivery error (%lx)\n", accept_status
);
735 return (send_status
| accept_status
);
739 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
741 unsigned long send_status
= 0, accept_status
= 0;
742 int maxlvt
, num_starts
, j
;
744 maxlvt
= lapic_get_maxlvt();
747 * Be paranoid about clearing APIC errors.
749 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
750 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
751 apic_write(APIC_ESR
, 0);
755 pr_debug("Asserting INIT\n");
758 * Turn INIT on target chip
763 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
766 pr_debug("Waiting for send to finish...\n");
767 send_status
= safe_apic_wait_icr_idle();
771 pr_debug("Deasserting INIT\n");
775 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
777 pr_debug("Waiting for send to finish...\n");
778 send_status
= safe_apic_wait_icr_idle();
783 * Should we send STARTUP IPIs ?
785 * Determine this based on the APIC version.
786 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
788 if (APIC_INTEGRATED(boot_cpu_apic_version
))
794 * Run STARTUP IPI loop.
796 pr_debug("#startup loops: %d\n", num_starts
);
798 for (j
= 1; j
<= num_starts
; j
++) {
799 pr_debug("Sending STARTUP #%d\n", j
);
800 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
801 apic_write(APIC_ESR
, 0);
803 pr_debug("After apic_write\n");
810 /* Boot on the stack */
811 /* Kick the second */
812 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
816 * Give the other CPU some time to accept the IPI.
818 if (init_udelay
== 0)
823 pr_debug("Startup point 1\n");
825 pr_debug("Waiting for send to finish...\n");
826 send_status
= safe_apic_wait_icr_idle();
829 * Give the other CPU some time to accept the IPI.
831 if (init_udelay
== 0)
836 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
837 apic_write(APIC_ESR
, 0);
838 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
839 if (send_status
|| accept_status
)
842 pr_debug("After Startup\n");
845 pr_err("APIC never delivered???\n");
847 pr_err("APIC delivery error (%lx)\n", accept_status
);
849 return (send_status
| accept_status
);
852 /* reduce the number of lines printed when booting a large cpu count system */
853 static void announce_cpu(int cpu
, int apicid
)
855 static int current_node
= -1;
856 int node
= early_cpu_to_node(cpu
);
857 static int width
, node_width
;
860 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
863 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
866 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
868 if (system_state
< SYSTEM_RUNNING
) {
869 if (node
!= current_node
) {
870 if (current_node
> (-1))
874 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
875 node_width
- num_digits(node
), " ", node
);
878 /* Add padding for the BSP */
880 pr_cont("%*s", width
+ 1, " ");
882 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
885 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
889 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
893 cpu
= smp_processor_id();
894 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
901 * Wake up AP by INIT, INIT, STARTUP sequence.
903 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
904 * boot-strap code which is not a desired behavior for waking up BSP. To
905 * void the boot-strap code, wake up CPU0 by NMI instead.
907 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
908 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
909 * We'll change this code in the future to wake up hard offlined CPU0 if
910 * real platform and request are available.
913 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
914 int *cpu0_nmi_registered
)
922 * Wake up AP by INIT, INIT, STARTUP sequence.
925 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
930 * Wake up BSP by nmi.
932 * Register a NMI handler to help wake up CPU0.
934 boot_error
= register_nmi_handler(NMI_LOCAL
,
935 wakeup_cpu0_nmi
, 0, "wake_cpu0");
938 enable_start_cpu0
= 1;
939 *cpu0_nmi_registered
= 1;
940 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
941 id
= cpu0_logical_apicid
;
944 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
953 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
955 /* Just in case we booted with a single CPU. */
956 alternatives_enable_smp();
958 per_cpu(current_task
, cpu
) = idle
;
961 /* Stack for startup_32 can be just as for start_secondary onwards */
963 per_cpu(cpu_current_top_of_stack
, cpu
) =
964 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
966 initial_gs
= per_cpu_offset(cpu
);
971 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
972 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
973 * Returns zero if CPU booted OK, else error code from
974 * ->wakeup_secondary_cpu.
976 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
977 int *cpu0_nmi_registered
)
979 volatile u32
*trampoline_status
=
980 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
981 /* start_ip had better be page-aligned! */
982 unsigned long start_ip
= real_mode_header
->trampoline_start
;
984 unsigned long boot_error
= 0;
985 unsigned long timeout
;
987 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
988 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
989 initial_code
= (unsigned long)start_secondary
;
990 initial_stack
= idle
->thread
.sp
;
993 * Enable the espfix hack for this CPU
995 #ifdef CONFIG_X86_ESPFIX64
999 /* So we see what's up */
1000 announce_cpu(cpu
, apicid
);
1003 * This grunge runs the startup process for
1004 * the targeted processor.
1007 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1009 pr_debug("Setting warm reset code and vector.\n");
1011 smpboot_setup_warm_reset_vector(start_ip
);
1013 * Be paranoid about clearing APIC errors.
1015 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1016 apic_write(APIC_ESR
, 0);
1017 apic_read(APIC_ESR
);
1022 * AP might wait on cpu_callout_mask in cpu_init() with
1023 * cpu_initialized_mask set if previous attempt to online
1024 * it timed-out. Clear cpu_initialized_mask so that after
1025 * INIT/SIPI it could start with a clean state.
1027 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1031 * Wake up a CPU in difference cases:
1032 * - Use the method in the APIC driver if it's defined
1034 * - Use an INIT boot APIC message for APs or NMI for BSP.
1036 if (apic
->wakeup_secondary_cpu
)
1037 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1039 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1040 cpu0_nmi_registered
);
1044 * Wait 10s total for first sign of life from AP
1047 timeout
= jiffies
+ 10*HZ
;
1048 while (time_before(jiffies
, timeout
)) {
1049 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1051 * Tell AP to proceed with initialization
1053 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1063 * Wait till AP completes initial initialization
1065 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1067 * Allow other tasks to run while we wait for the
1068 * AP to come online. This also gives a chance
1069 * for the MTRR work(triggered by the AP coming online)
1070 * to be completed in the stop machine context.
1076 /* mark "stuck" area as not stuck */
1077 *trampoline_status
= 0;
1079 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1081 * Cleanup possible dangling ends...
1083 smpboot_restore_warm_reset_vector();
1089 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1091 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1092 int cpu0_nmi_registered
= 0;
1093 unsigned long flags
;
1096 WARN_ON(irqs_disabled());
1098 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1100 if (apicid
== BAD_APICID
||
1101 !physid_isset(apicid
, phys_cpu_present_map
) ||
1102 !apic
->apic_id_valid(apicid
)) {
1103 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1108 * Already booted CPU?
1110 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1111 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1116 * Save current MTRR state in case it was changed since early boot
1117 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1121 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1122 err
= cpu_check_up_prepare(cpu
);
1123 if (err
&& err
!= -EBUSY
)
1126 /* the FPU context is blank, nobody can own it */
1127 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1129 common_cpu_up(cpu
, tidle
);
1131 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1133 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1139 * Check TSC synchronization with the AP (keep irqs disabled
1142 local_irq_save(flags
);
1143 check_tsc_sync_source(cpu
);
1144 local_irq_restore(flags
);
1146 while (!cpu_online(cpu
)) {
1148 touch_nmi_watchdog();
1153 * Clean up the nmi handler. Do this after the callin and callout sync
1154 * to avoid impact of possible long unregister time.
1156 if (cpu0_nmi_registered
)
1157 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1163 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1165 void arch_disable_smp_support(void)
1167 disable_ioapic_support();
1171 * Fall back to non SMP mode after errors.
1173 * RED-PEN audit/test this more. I bet there is more state messed up here.
1175 static __init
void disable_smp(void)
1177 pr_info("SMP disabled\n");
1179 disable_ioapic_support();
1181 init_cpu_present(cpumask_of(0));
1182 init_cpu_possible(cpumask_of(0));
1184 if (smp_found_config
)
1185 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1187 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1188 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1189 cpumask_set_cpu(0, topology_core_cpumask(0));
1200 * Various sanity checks.
1202 static int __init
smp_sanity_check(unsigned max_cpus
)
1206 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1207 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1211 pr_warn("More than 8 CPUs detected - skipping them\n"
1212 "Use CONFIG_X86_BIGSMP\n");
1215 for_each_present_cpu(cpu
) {
1217 set_cpu_present(cpu
, false);
1222 for_each_possible_cpu(cpu
) {
1224 set_cpu_possible(cpu
, false);
1232 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1233 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1234 hard_smp_processor_id());
1236 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1240 * If we couldn't find an SMP configuration at boot time,
1241 * get out of here now!
1243 if (!smp_found_config
&& !acpi_lapic
) {
1245 pr_notice("SMP motherboard not detected\n");
1246 return SMP_NO_CONFIG
;
1250 * Should not be necessary because the MP table should list the boot
1251 * CPU too, but we do it for the sake of robustness anyway.
1253 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1254 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1255 boot_cpu_physical_apicid
);
1256 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1261 * If we couldn't find a local APIC, then get out of here now!
1263 if (APIC_INTEGRATED(boot_cpu_apic_version
) &&
1264 !boot_cpu_has(X86_FEATURE_APIC
)) {
1265 if (!disable_apic
) {
1266 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1267 boot_cpu_physical_apicid
);
1268 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1274 * If SMP should be disabled, then really disable it!
1277 pr_info("SMP mode deactivated\n");
1278 return SMP_FORCE_UP
;
1284 static void __init
smp_cpu_index_default(void)
1287 struct cpuinfo_x86
*c
;
1289 for_each_possible_cpu(i
) {
1291 /* mark all to hotplug */
1292 c
->cpu_index
= nr_cpu_ids
;
1297 * Prepare for SMP bootup. The MP table or ACPI has been read
1298 * earlier. Just do some sanity checking here and enable APIC mode.
1300 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1304 smp_cpu_index_default();
1307 * Setup boot CPU information
1309 smp_store_boot_cpu_info(); /* Final full version of the data */
1310 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1313 for_each_possible_cpu(i
) {
1314 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1315 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1316 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1320 * Set 'default' x86 topology, this matches default_topology() in that
1321 * it has NUMA nodes as a topology level. See also
1322 * native_smp_cpus_done().
1324 * Must be done before set_cpus_sibling_map() is ran.
1326 set_sched_topology(x86_topology
);
1328 set_cpu_sibling_map(0);
1330 switch (smp_sanity_check(max_cpus
)) {
1333 if (APIC_init_uniprocessor())
1334 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1341 apic_bsp_setup(false);
1347 if (read_apic_id() != boot_cpu_physical_apicid
) {
1348 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1349 read_apic_id(), boot_cpu_physical_apicid
);
1350 /* Or can we switch back to PIC here? */
1353 default_setup_apic_routing();
1354 cpu0_logical_apicid
= apic_bsp_setup(false);
1357 print_cpu_info(&cpu_data(0));
1361 set_mtrr_aps_delayed_init();
1363 smp_quirk_init_udelay();
1366 void arch_enable_nonboot_cpus_begin(void)
1368 set_mtrr_aps_delayed_init();
1371 void arch_enable_nonboot_cpus_end(void)
1377 * Early setup to make printk work.
1379 void __init
native_smp_prepare_boot_cpu(void)
1381 int me
= smp_processor_id();
1382 switch_to_new_gdt(me
);
1383 /* already set me in cpu_online_mask in boot_cpu_init() */
1384 cpumask_set_cpu(me
, cpu_callout_mask
);
1385 cpu_set_state_online(me
);
1388 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1390 pr_debug("Boot done\n");
1392 if (x86_has_numa_in_package
)
1393 set_sched_topology(x86_numa_in_package_topology
);
1397 setup_ioapic_dest();
1401 static int __initdata setup_possible_cpus
= -1;
1402 static int __init
_setup_possible_cpus(char *str
)
1404 get_option(&str
, &setup_possible_cpus
);
1407 early_param("possible_cpus", _setup_possible_cpus
);
1411 * cpu_possible_mask should be static, it cannot change as cpu's
1412 * are onlined, or offlined. The reason is per-cpu data-structures
1413 * are allocated by some modules at init time, and dont expect to
1414 * do this dynamically on cpu arrival/departure.
1415 * cpu_present_mask on the other hand can change dynamically.
1416 * In case when cpu_hotplug is not compiled, then we resort to current
1417 * behaviour, which is cpu_possible == cpu_present.
1420 * Three ways to find out the number of additional hotplug CPUs:
1421 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1422 * - The user can overwrite it with possible_cpus=NUM
1423 * - Otherwise don't reserve additional CPUs.
1424 * We do this because additional CPUs waste a lot of memory.
1427 __init
void prefill_possible_map(void)
1431 /* No boot processor was found in mptable or ACPI MADT */
1432 if (!num_processors
) {
1433 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1434 int apicid
= boot_cpu_physical_apicid
;
1435 int cpu
= hard_smp_processor_id();
1437 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1439 /* Make sure boot cpu is enumerated */
1440 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1441 apic
->apic_id_valid(apicid
))
1442 generic_processor_info(apicid
, boot_cpu_apic_version
);
1445 if (!num_processors
)
1449 i
= setup_max_cpus
?: 1;
1450 if (setup_possible_cpus
== -1) {
1451 possible
= num_processors
;
1452 #ifdef CONFIG_HOTPLUG_CPU
1454 possible
+= disabled_cpus
;
1460 possible
= setup_possible_cpus
;
1462 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1464 /* nr_cpu_ids could be reduced via nr_cpus= */
1465 if (possible
> nr_cpu_ids
) {
1466 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1467 possible
, nr_cpu_ids
);
1468 possible
= nr_cpu_ids
;
1471 #ifdef CONFIG_HOTPLUG_CPU
1472 if (!setup_max_cpus
)
1475 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1476 possible
, setup_max_cpus
);
1480 nr_cpu_ids
= possible
;
1482 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1483 possible
, max_t(int, possible
- num_processors
, 0));
1485 reset_cpu_possible_mask();
1487 for (i
= 0; i
< possible
; i
++)
1488 set_cpu_possible(i
, true);
1491 #ifdef CONFIG_HOTPLUG_CPU
1493 /* Recompute SMT state for all CPUs on offline */
1494 static void recompute_smt_state(void)
1496 int max_threads
, cpu
;
1499 for_each_online_cpu (cpu
) {
1500 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1502 if (threads
> max_threads
)
1503 max_threads
= threads
;
1505 __max_smt_threads
= max_threads
;
1508 static void remove_siblinginfo(int cpu
)
1511 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1513 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1514 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1516 * last thread sibling in this cpu core going down
1518 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1519 cpu_data(sibling
).booted_cores
--;
1522 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1523 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1524 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1525 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1526 cpumask_clear(cpu_llc_shared_mask(cpu
));
1527 cpumask_clear(topology_sibling_cpumask(cpu
));
1528 cpumask_clear(topology_core_cpumask(cpu
));
1529 c
->phys_proc_id
= 0;
1531 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1532 recompute_smt_state();
1535 static void remove_cpu_from_maps(int cpu
)
1537 set_cpu_online(cpu
, false);
1538 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1539 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1540 /* was set by cpu_init() */
1541 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1542 numa_remove_cpu(cpu
);
1545 void cpu_disable_common(void)
1547 int cpu
= smp_processor_id();
1549 remove_siblinginfo(cpu
);
1551 /* It's now safe to remove this processor from the online map */
1553 remove_cpu_from_maps(cpu
);
1554 unlock_vector_lock();
1558 int native_cpu_disable(void)
1562 ret
= check_irq_vectors_for_cpu_disable();
1567 cpu_disable_common();
1572 int common_cpu_die(unsigned int cpu
)
1576 /* We don't do anything here: idle task is faking death itself. */
1578 /* They ack this in play_dead() by setting CPU_DEAD */
1579 if (cpu_wait_death(cpu
, 5)) {
1580 if (system_state
== SYSTEM_RUNNING
)
1581 pr_info("CPU %u is now offline\n", cpu
);
1583 pr_err("CPU %u didn't die...\n", cpu
);
1590 void native_cpu_die(unsigned int cpu
)
1592 common_cpu_die(cpu
);
1595 void play_dead_common(void)
1600 (void)cpu_report_death();
1603 * With physical CPU hotplug, we should halt the cpu
1605 local_irq_disable();
1608 static bool wakeup_cpu0(void)
1610 if (smp_processor_id() == 0 && enable_start_cpu0
)
1617 * We need to flush the caches before going to sleep, lest we have
1618 * dirty data in our caches when we come back up.
1620 static inline void mwait_play_dead(void)
1622 unsigned int eax
, ebx
, ecx
, edx
;
1623 unsigned int highest_cstate
= 0;
1624 unsigned int highest_subcstate
= 0;
1628 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1630 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1632 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1635 eax
= CPUID_MWAIT_LEAF
;
1637 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1640 * eax will be 0 if EDX enumeration is not valid.
1641 * Initialized below to cstate, sub_cstate value when EDX is valid.
1643 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1646 edx
>>= MWAIT_SUBSTATE_SIZE
;
1647 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1648 if (edx
& MWAIT_SUBSTATE_MASK
) {
1650 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1653 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1654 (highest_subcstate
- 1);
1658 * This should be a memory location in a cache line which is
1659 * unlikely to be touched by other processors. The actual
1660 * content is immaterial as it is not actually modified in any way.
1662 mwait_ptr
= ¤t_thread_info()->flags
;
1668 * The CLFLUSH is a workaround for erratum AAI65 for
1669 * the Xeon 7400 series. It's not clear it is actually
1670 * needed, but it should be harmless in either case.
1671 * The WBINVD is insufficient due to the spurious-wakeup
1672 * case where we return around the loop.
1677 __monitor(mwait_ptr
, 0, 0);
1681 * If NMI wants to wake up CPU0, start CPU0.
1688 void hlt_play_dead(void)
1690 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1696 * If NMI wants to wake up CPU0, start CPU0.
1703 void native_play_dead(void)
1706 tboot_shutdown(TB_SHUTDOWN_WFS
);
1708 mwait_play_dead(); /* Only returns on failure */
1709 if (cpuidle_play_dead())
1713 #else /* ... !CONFIG_HOTPLUG_CPU */
1714 int native_cpu_disable(void)
1719 void native_cpu_die(unsigned int cpu
)
1721 /* We said "no" in __cpu_disable */
1725 void native_play_dead(void)