2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings
= 1;
81 EXPORT_SYMBOL(smp_num_siblings
);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
98 EXPORT_PER_CPU_SYMBOL(cpu_info
);
100 atomic_t init_deasserted
;
102 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
106 spin_lock_irqsave(&rtc_lock
, flags
);
107 CMOS_WRITE(0xa, 0xf);
108 spin_unlock_irqrestore(&rtc_lock
, flags
);
111 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
114 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
119 static inline void smpboot_restore_warm_reset_vector(void)
124 * Install writable page 0 entry to set BIOS data area.
129 * Paranoid: Set warm reset code and vector here back
132 spin_lock_irqsave(&rtc_lock
, flags
);
134 spin_unlock_irqrestore(&rtc_lock
, flags
);
136 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
140 * Report back to the Boot Processor during boot time or to the caller processor
143 static void smp_callin(void)
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
153 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
155 cpuid
= smp_processor_id();
156 if (apic
->wait_for_init_deassert
&& cpuid
)
157 while (!atomic_read(&init_deasserted
))
161 * (This works even if the APIC is not enabled.)
163 phys_id
= read_apic_id();
166 * the boot CPU has finished the init stage and is spinning
167 * on callin_map until we finish. We are free to set up this
168 * CPU, first the APIC. (this is probably redundant on most
174 * Need to setup vector mappings before we enable interrupts.
176 setup_vector_irq(smp_processor_id());
179 * Save our processor parameters. Note: this information
180 * is needed for clock calibration.
182 smp_store_cpu_info(cpuid
);
186 * Update loops_per_jiffy in cpu_data. Previous call to
187 * smp_store_cpu_info() stored a value that is close but not as
188 * accurate as the value just calculated.
191 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
192 pr_debug("Stack at about %p\n", &cpuid
);
195 * This must be done before setting cpu_online_mask
196 * or calling notify_cpu_starting.
198 set_cpu_sibling_map(raw_smp_processor_id());
201 notify_cpu_starting(cpuid
);
204 * Allow the master to continue.
206 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
209 static int cpu0_logical_apicid
;
210 static int enable_start_cpu0
;
212 * Activate a secondary processor.
214 static void notrace
start_secondary(void *unused
)
217 * Don't put *anything* before cpu_init(), SMP booting is too
218 * fragile that we want to limit the things done here to the
219 * most necessary things.
222 x86_cpuinit
.early_percpu_clock_init();
226 enable_start_cpu0
= 0;
229 /* switch away from the initial page table */
230 load_cr3(swapper_pg_dir
);
234 /* otherwise gcc will move up smp_processor_id before the cpu_init */
237 * Check TSC synchronization with the BP:
239 check_tsc_sync_target();
242 * Enable the espfix hack for this CPU
244 #ifdef CONFIG_X86_ESPFIX64
249 * We need to hold vector_lock so there the set of online cpus
250 * does not change while we are assigning vectors to cpus. Holding
251 * this lock ensures we don't half assign or remove an irq from a cpu.
254 set_cpu_online(smp_processor_id(), true);
255 unlock_vector_lock();
256 cpu_set_state_online(smp_processor_id());
257 x86_platform
.nmi_init();
259 /* enable local interrupts */
262 /* to prevent fake stack check failure in clock setup */
263 boot_init_stack_canary();
265 x86_cpuinit
.setup_percpu_clockev();
268 cpu_startup_entry(CPUHP_ONLINE
);
271 void __init
smp_store_boot_cpu_info(void)
273 int id
= 0; /* CPU 0 */
274 struct cpuinfo_x86
*c
= &cpu_data(id
);
281 * The bootstrap kernel entry code has set these up. Save them for
284 void smp_store_cpu_info(int id
)
286 struct cpuinfo_x86
*c
= &cpu_data(id
);
291 * During boot time, CPU0 has this setup already. Save the info when
292 * bringing up AP or offlined CPU0.
294 identify_secondary_cpu(c
);
298 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
300 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
302 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
306 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
308 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
310 return !WARN_ONCE(!topology_same_node(c
, o
),
311 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
312 "[node: %d != %d]. Ignoring dependency.\n",
313 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
316 #define link_mask(_m, c1, c2) \
318 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
319 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
322 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
324 if (cpu_has_topoext
) {
325 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
327 if (c
->phys_proc_id
== o
->phys_proc_id
&&
328 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
329 c
->compute_unit_id
== o
->compute_unit_id
)
330 return topology_sane(c
, o
, "smt");
332 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
333 c
->cpu_core_id
== o
->cpu_core_id
) {
334 return topology_sane(c
, o
, "smt");
340 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
342 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
344 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
345 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
346 return topology_sane(c
, o
, "llc");
352 * Unlike the other levels, we do not enforce keeping a
353 * multicore group inside a NUMA node. If this happens, we will
354 * discard the MC level of the topology later.
356 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
358 if (c
->phys_proc_id
== o
->phys_proc_id
)
363 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
364 #ifdef CONFIG_SCHED_SMT
365 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
367 #ifdef CONFIG_SCHED_MC
368 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
373 * set_sched_topology() sets the topology internal to a CPU. The
374 * NUMA topologies are layered on top of it to build the full
377 * If NUMA nodes are observed to occur within a CPU package, this
378 * function should be called. It forces the sched domain code to
379 * only use the SMT level for the CPU portion of the topology.
380 * This essentially falls back to relying on NUMA information
381 * from the SRAT table to describe the entire system topology
382 * (except for hyperthreads).
384 static void primarily_use_numa_for_topology(void)
386 set_sched_topology(numa_inside_package_topology
);
389 void set_cpu_sibling_map(int cpu
)
391 bool has_smt
= smp_num_siblings
> 1;
392 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
393 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
394 struct cpuinfo_x86
*o
;
397 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
400 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
401 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
402 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
407 for_each_cpu(i
, cpu_sibling_setup_mask
) {
410 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
411 link_mask(sibling
, cpu
, i
);
413 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
414 link_mask(llc_shared
, cpu
, i
);
419 * This needs a separate iteration over the cpus because we rely on all
420 * cpu_sibling_mask links to be set-up.
422 for_each_cpu(i
, cpu_sibling_setup_mask
) {
425 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
426 link_mask(core
, cpu
, i
);
429 * Does this new cpu bringup a new core?
431 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
433 * for each core in package, increment
434 * the booted_cores for this new cpu
436 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
439 * increment the core count for all
440 * the other cpus in this package
443 cpu_data(i
).booted_cores
++;
444 } else if (i
!= cpu
&& !c
->booted_cores
)
445 c
->booted_cores
= cpu_data(i
).booted_cores
;
447 if (match_die(c
, o
) && !topology_same_node(c
, o
))
448 primarily_use_numa_for_topology();
452 /* maps the cpu to the sched domain representing multi-core */
453 const struct cpumask
*cpu_coregroup_mask(int cpu
)
455 return cpu_llc_shared_mask(cpu
);
458 static void impress_friends(void)
461 unsigned long bogosum
= 0;
463 * Allow the user to impress friends.
465 pr_debug("Before bogomips\n");
466 for_each_possible_cpu(cpu
)
467 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
468 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
469 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
472 (bogosum
/(5000/HZ
))%100);
474 pr_debug("Before bogocount - setting activated=1\n");
477 void __inquire_remote_apic(int apicid
)
479 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
480 const char * const names
[] = { "ID", "VERSION", "SPIV" };
484 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
486 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
487 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
492 status
= safe_apic_wait_icr_idle();
494 pr_cont("a previous APIC delivery may have failed\n");
496 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
501 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
502 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
505 case APIC_ICR_RR_VALID
:
506 status
= apic_read(APIC_RRR
);
507 pr_cont("%08x\n", status
);
516 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
517 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
518 * won't ... remember to clear down the APIC, etc later.
521 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
523 unsigned long send_status
, accept_status
= 0;
527 /* Boot on the stack */
528 /* Kick the second */
529 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
531 pr_debug("Waiting for send to finish...\n");
532 send_status
= safe_apic_wait_icr_idle();
535 * Give the other CPU some time to accept the IPI.
538 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
539 maxlvt
= lapic_get_maxlvt();
540 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
541 apic_write(APIC_ESR
, 0);
542 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
544 pr_debug("NMI sent\n");
547 pr_err("APIC never delivered???\n");
549 pr_err("APIC delivery error (%lx)\n", accept_status
);
551 return (send_status
| accept_status
);
555 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
557 unsigned long send_status
, accept_status
= 0;
558 int maxlvt
, num_starts
, j
;
560 maxlvt
= lapic_get_maxlvt();
563 * Be paranoid about clearing APIC errors.
565 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
566 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
567 apic_write(APIC_ESR
, 0);
571 pr_debug("Asserting INIT\n");
574 * Turn INIT on target chip
579 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
582 pr_debug("Waiting for send to finish...\n");
583 send_status
= safe_apic_wait_icr_idle();
587 pr_debug("Deasserting INIT\n");
591 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
593 pr_debug("Waiting for send to finish...\n");
594 send_status
= safe_apic_wait_icr_idle();
597 atomic_set(&init_deasserted
, 1);
600 * Should we send STARTUP IPIs ?
602 * Determine this based on the APIC version.
603 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
605 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
611 * Paravirt / VMI wants a startup IPI hook here to set up the
612 * target processor state.
614 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
618 * Run STARTUP IPI loop.
620 pr_debug("#startup loops: %d\n", num_starts
);
622 for (j
= 1; j
<= num_starts
; j
++) {
623 pr_debug("Sending STARTUP #%d\n", j
);
624 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
625 apic_write(APIC_ESR
, 0);
627 pr_debug("After apic_write\n");
634 /* Boot on the stack */
635 /* Kick the second */
636 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
640 * Give the other CPU some time to accept the IPI.
644 pr_debug("Startup point 1\n");
646 pr_debug("Waiting for send to finish...\n");
647 send_status
= safe_apic_wait_icr_idle();
650 * Give the other CPU some time to accept the IPI.
653 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
654 apic_write(APIC_ESR
, 0);
655 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
656 if (send_status
|| accept_status
)
659 pr_debug("After Startup\n");
662 pr_err("APIC never delivered???\n");
664 pr_err("APIC delivery error (%lx)\n", accept_status
);
666 return (send_status
| accept_status
);
669 void smp_announce(void)
671 int num_nodes
= num_online_nodes();
673 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
674 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
677 /* reduce the number of lines printed when booting a large cpu count system */
678 static void announce_cpu(int cpu
, int apicid
)
680 static int current_node
= -1;
681 int node
= early_cpu_to_node(cpu
);
682 static int width
, node_width
;
685 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
688 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
691 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
693 if (system_state
== SYSTEM_BOOTING
) {
694 if (node
!= current_node
) {
695 if (current_node
> (-1))
699 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
700 node_width
- num_digits(node
), " ", node
);
703 /* Add padding for the BSP */
705 pr_cont("%*s", width
+ 1, " ");
707 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
710 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
714 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
718 cpu
= smp_processor_id();
719 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
726 * Wake up AP by INIT, INIT, STARTUP sequence.
728 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
729 * boot-strap code which is not a desired behavior for waking up BSP. To
730 * void the boot-strap code, wake up CPU0 by NMI instead.
732 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
733 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
734 * We'll change this code in the future to wake up hard offlined CPU0 if
735 * real platform and request are available.
738 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
739 int *cpu0_nmi_registered
)
747 * Wake up AP by INIT, INIT, STARTUP sequence.
750 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
755 * Wake up BSP by nmi.
757 * Register a NMI handler to help wake up CPU0.
759 boot_error
= register_nmi_handler(NMI_LOCAL
,
760 wakeup_cpu0_nmi
, 0, "wake_cpu0");
763 enable_start_cpu0
= 1;
764 *cpu0_nmi_registered
= 1;
765 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
766 id
= cpu0_logical_apicid
;
769 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
778 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
780 /* Just in case we booted with a single CPU. */
781 alternatives_enable_smp();
783 per_cpu(current_task
, cpu
) = idle
;
786 /* Stack for startup_32 can be just as for start_secondary onwards */
788 per_cpu(cpu_current_top_of_stack
, cpu
) =
789 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
791 clear_tsk_thread_flag(idle
, TIF_FORK
);
792 initial_gs
= per_cpu_offset(cpu
);
794 per_cpu(kernel_stack
, cpu
) =
795 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
799 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
800 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
801 * Returns zero if CPU booted OK, else error code from
802 * ->wakeup_secondary_cpu.
804 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
806 volatile u32
*trampoline_status
=
807 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
808 /* start_ip had better be page-aligned! */
809 unsigned long start_ip
= real_mode_header
->trampoline_start
;
811 unsigned long boot_error
= 0;
812 int cpu0_nmi_registered
= 0;
813 unsigned long timeout
;
815 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
816 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
818 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
819 initial_code
= (unsigned long)start_secondary
;
820 stack_start
= idle
->thread
.sp
;
822 /* So we see what's up */
823 announce_cpu(cpu
, apicid
);
826 * This grunge runs the startup process for
827 * the targeted processor.
830 atomic_set(&init_deasserted
, 0);
832 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
834 pr_debug("Setting warm reset code and vector.\n");
836 smpboot_setup_warm_reset_vector(start_ip
);
838 * Be paranoid about clearing APIC errors.
840 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
841 apic_write(APIC_ESR
, 0);
847 * AP might wait on cpu_callout_mask in cpu_init() with
848 * cpu_initialized_mask set if previous attempt to online
849 * it timed-out. Clear cpu_initialized_mask so that after
850 * INIT/SIPI it could start with a clean state.
852 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
856 * Wake up a CPU in difference cases:
857 * - Use the method in the APIC driver if it's defined
859 * - Use an INIT boot APIC message for APs or NMI for BSP.
861 if (apic
->wakeup_secondary_cpu
)
862 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
864 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
865 &cpu0_nmi_registered
);
869 * Wait 10s total for a response from AP
872 timeout
= jiffies
+ 10*HZ
;
873 while (time_before(jiffies
, timeout
)) {
874 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
876 * Tell AP to proceed with initialization
878 cpumask_set_cpu(cpu
, cpu_callout_mask
);
889 * Wait till AP completes initial initialization
891 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
893 * Allow other tasks to run while we wait for the
894 * AP to come online. This also gives a chance
895 * for the MTRR work(triggered by the AP coming online)
896 * to be completed in the stop machine context.
903 /* mark "stuck" area as not stuck */
904 *trampoline_status
= 0;
906 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
908 * Cleanup possible dangling ends...
910 smpboot_restore_warm_reset_vector();
913 * Clean up the nmi handler. Do this after the callin and callout sync
914 * to avoid impact of possible long unregister time.
916 if (cpu0_nmi_registered
)
917 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
922 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
924 int apicid
= apic
->cpu_present_to_apicid(cpu
);
928 WARN_ON(irqs_disabled());
930 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
932 if (apicid
== BAD_APICID
||
933 !physid_isset(apicid
, phys_cpu_present_map
) ||
934 !apic
->apic_id_valid(apicid
)) {
935 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
940 * Already booted CPU?
942 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
943 pr_debug("do_boot_cpu %d Already started\n", cpu
);
948 * Save current MTRR state in case it was changed since early boot
949 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
953 /* x86 CPUs take themselves offline, so delayed offline is OK. */
954 err
= cpu_check_up_prepare(cpu
);
955 if (err
&& err
!= -EBUSY
)
958 /* the FPU context is blank, nobody can own it */
959 __cpu_disable_lazy_restore(cpu
);
961 common_cpu_up(cpu
, tidle
);
963 err
= do_boot_cpu(apicid
, cpu
, tidle
);
965 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
970 * Check TSC synchronization with the AP (keep irqs disabled
973 local_irq_save(flags
);
974 check_tsc_sync_source(cpu
);
975 local_irq_restore(flags
);
977 while (!cpu_online(cpu
)) {
979 touch_nmi_watchdog();
986 * arch_disable_smp_support() - disables SMP support for x86 at runtime
988 void arch_disable_smp_support(void)
990 disable_ioapic_support();
994 * Fall back to non SMP mode after errors.
996 * RED-PEN audit/test this more. I bet there is more state messed up here.
998 static __init
void disable_smp(void)
1000 pr_info("SMP disabled\n");
1002 disable_ioapic_support();
1004 init_cpu_present(cpumask_of(0));
1005 init_cpu_possible(cpumask_of(0));
1007 if (smp_found_config
)
1008 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1010 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1011 cpumask_set_cpu(0, cpu_sibling_mask(0));
1012 cpumask_set_cpu(0, cpu_core_mask(0));
1023 * Various sanity checks.
1025 static int __init
smp_sanity_check(unsigned max_cpus
)
1029 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1030 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1034 pr_warn("More than 8 CPUs detected - skipping them\n"
1035 "Use CONFIG_X86_BIGSMP\n");
1038 for_each_present_cpu(cpu
) {
1040 set_cpu_present(cpu
, false);
1045 for_each_possible_cpu(cpu
) {
1047 set_cpu_possible(cpu
, false);
1055 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1056 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1057 hard_smp_processor_id());
1059 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1063 * If we couldn't find an SMP configuration at boot time,
1064 * get out of here now!
1066 if (!smp_found_config
&& !acpi_lapic
) {
1068 pr_notice("SMP motherboard not detected\n");
1069 return SMP_NO_CONFIG
;
1073 * Should not be necessary because the MP table should list the boot
1074 * CPU too, but we do it for the sake of robustness anyway.
1076 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1077 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1078 boot_cpu_physical_apicid
);
1079 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1084 * If we couldn't find a local APIC, then get out of here now!
1086 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1088 if (!disable_apic
) {
1089 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1090 boot_cpu_physical_apicid
);
1091 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1097 * If SMP should be disabled, then really disable it!
1100 pr_info("SMP mode deactivated\n");
1101 return SMP_FORCE_UP
;
1107 static void __init
smp_cpu_index_default(void)
1110 struct cpuinfo_x86
*c
;
1112 for_each_possible_cpu(i
) {
1114 /* mark all to hotplug */
1115 c
->cpu_index
= nr_cpu_ids
;
1120 * Prepare for SMP bootup. The MP table or ACPI has been read
1121 * earlier. Just do some sanity checking here and enable APIC mode.
1123 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1127 smp_cpu_index_default();
1130 * Setup boot CPU information
1132 smp_store_boot_cpu_info(); /* Final full version of the data */
1133 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1136 current_thread_info()->cpu
= 0; /* needed? */
1137 for_each_possible_cpu(i
) {
1138 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1139 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1140 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1142 set_cpu_sibling_map(0);
1144 switch (smp_sanity_check(max_cpus
)) {
1147 if (APIC_init_uniprocessor())
1148 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1155 apic_bsp_setup(false);
1161 default_setup_apic_routing();
1163 if (read_apic_id() != boot_cpu_physical_apicid
) {
1164 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1165 read_apic_id(), boot_cpu_physical_apicid
);
1166 /* Or can we switch back to PIC here? */
1169 cpu0_logical_apicid
= apic_bsp_setup(false);
1171 pr_info("CPU%d: ", 0);
1172 print_cpu_info(&cpu_data(0));
1177 set_mtrr_aps_delayed_init();
1180 void arch_enable_nonboot_cpus_begin(void)
1182 set_mtrr_aps_delayed_init();
1185 void arch_enable_nonboot_cpus_end(void)
1191 * Early setup to make printk work.
1193 void __init
native_smp_prepare_boot_cpu(void)
1195 int me
= smp_processor_id();
1196 switch_to_new_gdt(me
);
1197 /* already set me in cpu_online_mask in boot_cpu_init() */
1198 cpumask_set_cpu(me
, cpu_callout_mask
);
1199 cpu_set_state_online(me
);
1202 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1204 pr_debug("Boot done\n");
1208 setup_ioapic_dest();
1212 static int __initdata setup_possible_cpus
= -1;
1213 static int __init
_setup_possible_cpus(char *str
)
1215 get_option(&str
, &setup_possible_cpus
);
1218 early_param("possible_cpus", _setup_possible_cpus
);
1222 * cpu_possible_mask should be static, it cannot change as cpu's
1223 * are onlined, or offlined. The reason is per-cpu data-structures
1224 * are allocated by some modules at init time, and dont expect to
1225 * do this dynamically on cpu arrival/departure.
1226 * cpu_present_mask on the other hand can change dynamically.
1227 * In case when cpu_hotplug is not compiled, then we resort to current
1228 * behaviour, which is cpu_possible == cpu_present.
1231 * Three ways to find out the number of additional hotplug CPUs:
1232 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1233 * - The user can overwrite it with possible_cpus=NUM
1234 * - Otherwise don't reserve additional CPUs.
1235 * We do this because additional CPUs waste a lot of memory.
1238 __init
void prefill_possible_map(void)
1242 /* no processor from mptable or madt */
1243 if (!num_processors
)
1246 i
= setup_max_cpus
?: 1;
1247 if (setup_possible_cpus
== -1) {
1248 possible
= num_processors
;
1249 #ifdef CONFIG_HOTPLUG_CPU
1251 possible
+= disabled_cpus
;
1257 possible
= setup_possible_cpus
;
1259 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1261 /* nr_cpu_ids could be reduced via nr_cpus= */
1262 if (possible
> nr_cpu_ids
) {
1263 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1264 possible
, nr_cpu_ids
);
1265 possible
= nr_cpu_ids
;
1268 #ifdef CONFIG_HOTPLUG_CPU
1269 if (!setup_max_cpus
)
1272 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1273 possible
, setup_max_cpus
);
1277 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1278 possible
, max_t(int, possible
- num_processors
, 0));
1280 for (i
= 0; i
< possible
; i
++)
1281 set_cpu_possible(i
, true);
1282 for (; i
< NR_CPUS
; i
++)
1283 set_cpu_possible(i
, false);
1285 nr_cpu_ids
= possible
;
1288 #ifdef CONFIG_HOTPLUG_CPU
1290 static void remove_siblinginfo(int cpu
)
1293 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1295 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1296 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1298 * last thread sibling in this cpu core going down
1300 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1301 cpu_data(sibling
).booted_cores
--;
1304 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1305 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1306 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1307 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1308 cpumask_clear(cpu_llc_shared_mask(cpu
));
1309 cpumask_clear(cpu_sibling_mask(cpu
));
1310 cpumask_clear(cpu_core_mask(cpu
));
1311 c
->phys_proc_id
= 0;
1313 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1316 static void __ref
remove_cpu_from_maps(int cpu
)
1318 set_cpu_online(cpu
, false);
1319 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1320 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1321 /* was set by cpu_init() */
1322 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1323 numa_remove_cpu(cpu
);
1326 void cpu_disable_common(void)
1328 int cpu
= smp_processor_id();
1330 remove_siblinginfo(cpu
);
1332 /* It's now safe to remove this processor from the online map */
1334 remove_cpu_from_maps(cpu
);
1335 unlock_vector_lock();
1339 int native_cpu_disable(void)
1343 ret
= check_irq_vectors_for_cpu_disable();
1348 cpu_disable_common();
1353 int common_cpu_die(unsigned int cpu
)
1357 /* We don't do anything here: idle task is faking death itself. */
1359 /* They ack this in play_dead() by setting CPU_DEAD */
1360 if (cpu_wait_death(cpu
, 5)) {
1361 if (system_state
== SYSTEM_RUNNING
)
1362 pr_info("CPU %u is now offline\n", cpu
);
1364 pr_err("CPU %u didn't die...\n", cpu
);
1371 void native_cpu_die(unsigned int cpu
)
1373 common_cpu_die(cpu
);
1376 void play_dead_common(void)
1379 reset_lazy_tlbstate();
1380 amd_e400_remove_cpu(raw_smp_processor_id());
1383 (void)cpu_report_death();
1386 * With physical CPU hotplug, we should halt the cpu
1388 local_irq_disable();
1391 static bool wakeup_cpu0(void)
1393 if (smp_processor_id() == 0 && enable_start_cpu0
)
1400 * We need to flush the caches before going to sleep, lest we have
1401 * dirty data in our caches when we come back up.
1403 static inline void mwait_play_dead(void)
1405 unsigned int eax
, ebx
, ecx
, edx
;
1406 unsigned int highest_cstate
= 0;
1407 unsigned int highest_subcstate
= 0;
1411 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1413 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1415 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1418 eax
= CPUID_MWAIT_LEAF
;
1420 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1423 * eax will be 0 if EDX enumeration is not valid.
1424 * Initialized below to cstate, sub_cstate value when EDX is valid.
1426 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1429 edx
>>= MWAIT_SUBSTATE_SIZE
;
1430 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1431 if (edx
& MWAIT_SUBSTATE_MASK
) {
1433 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1436 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1437 (highest_subcstate
- 1);
1441 * This should be a memory location in a cache line which is
1442 * unlikely to be touched by other processors. The actual
1443 * content is immaterial as it is not actually modified in any way.
1445 mwait_ptr
= ¤t_thread_info()->flags
;
1451 * The CLFLUSH is a workaround for erratum AAI65 for
1452 * the Xeon 7400 series. It's not clear it is actually
1453 * needed, but it should be harmless in either case.
1454 * The WBINVD is insufficient due to the spurious-wakeup
1455 * case where we return around the loop.
1460 __monitor(mwait_ptr
, 0, 0);
1464 * If NMI wants to wake up CPU0, start CPU0.
1471 static inline void hlt_play_dead(void)
1473 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1479 * If NMI wants to wake up CPU0, start CPU0.
1486 void native_play_dead(void)
1489 tboot_shutdown(TB_SHUTDOWN_WFS
);
1491 mwait_play_dead(); /* Only returns on failure */
1492 if (cpuidle_play_dead())
1496 #else /* ... !CONFIG_HOTPLUG_CPU */
1497 int native_cpu_disable(void)
1502 void native_cpu_die(unsigned int cpu
)
1504 /* We said "no" in __cpu_disable */
1508 void native_play_dead(void)