2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/setup.h>
72 #include <asm/uv/uv.h>
73 #include <linux/mc146818rtc.h>
75 #include <asm/smpboot_hooks.h>
76 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 /* State of each CPU */
81 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
83 #ifdef CONFIG_HOTPLUG_CPU
85 * We need this for trampoline_base protection from concurrent accesses when
86 * off- and onlining cores wildly.
88 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
90 void cpu_hotplug_driver_lock(void)
92 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
95 void cpu_hotplug_driver_unlock(void)
97 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
100 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
101 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
104 /* Number of siblings per CPU package */
105 int smp_num_siblings
= 1;
106 EXPORT_SYMBOL(smp_num_siblings
);
108 /* Last level cache ID of each logical CPU */
109 DEFINE_PER_CPU(u16
, cpu_llc_id
) = BAD_APICID
;
111 /* representing HT siblings of each logical CPU */
112 DEFINE_PER_CPU(cpumask_var_t
, cpu_sibling_map
);
113 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
115 /* representing HT and core siblings of each logical CPU */
116 DEFINE_PER_CPU(cpumask_var_t
, cpu_core_map
);
117 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
119 DEFINE_PER_CPU(cpumask_var_t
, cpu_llc_shared_map
);
121 /* Per CPU bogomips and other parameters */
122 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
123 EXPORT_PER_CPU_SYMBOL(cpu_info
);
125 atomic_t init_deasserted
;
128 * Report back to the Boot Processor.
131 static void __cpuinit
smp_callin(void)
134 unsigned long timeout
;
137 * If waken up by an INIT in an 82489DX configuration
138 * we may get here before an INIT-deassert IPI reaches
139 * our local APIC. We have to wait for the IPI or we'll
140 * lock up on an APIC access.
142 if (apic
->wait_for_init_deassert
)
143 apic
->wait_for_init_deassert(&init_deasserted
);
146 * (This works even if the APIC is not enabled.)
148 phys_id
= read_apic_id();
149 cpuid
= smp_processor_id();
150 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
151 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
154 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
157 * STARTUP IPIs are fragile beasts as they might sometimes
158 * trigger some glue motherboard logic. Complete APIC bus
159 * silence for 1 second, this overestimates the time the
160 * boot CPU is spending to send the up to 2 STARTUP IPIs
161 * by a factor of two. This should be enough.
165 * Waiting 2s total for startup (udelay is not yet working)
167 timeout
= jiffies
+ 2*HZ
;
168 while (time_before(jiffies
, timeout
)) {
170 * Has the boot CPU finished it's STARTUP sequence?
172 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
177 if (!time_before(jiffies
, timeout
)) {
178 panic("%s: CPU%d started up but did not get a callout!\n",
183 * the boot CPU has finished the init stage and is spinning
184 * on callin_map until we finish. We are free to set up this
185 * CPU, first the APIC. (this is probably redundant on most
189 pr_debug("CALLIN, before setup_local_APIC()\n");
190 if (apic
->smp_callin_clear_local_apic
)
191 apic
->smp_callin_clear_local_apic();
193 end_local_APIC_setup();
196 * Need to setup vector mappings before we enable interrupts.
198 setup_vector_irq(smp_processor_id());
201 * Save our processor parameters. Note: this information
202 * is needed for clock calibration.
204 smp_store_cpu_info(cpuid
);
208 * Update loops_per_jiffy in cpu_data. Previous call to
209 * smp_store_cpu_info() stored a value that is close but not as
210 * accurate as the value just calculated.
213 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
214 pr_debug("Stack at about %p\n", &cpuid
);
217 * This must be done before setting cpu_online_mask
218 * or calling notify_cpu_starting.
220 set_cpu_sibling_map(raw_smp_processor_id());
223 notify_cpu_starting(cpuid
);
226 * Allow the master to continue.
228 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
232 * Activate a secondary processor.
234 notrace
static void __cpuinit
start_secondary(void *unused
)
237 * Don't put *anything* before cpu_init(), SMP booting is too
238 * fragile that we want to limit the things done here to the
239 * most necessary things.
242 x86_cpuinit
.early_percpu_clock_init();
247 /* switch away from the initial page table */
248 load_cr3(swapper_pg_dir
);
252 /* otherwise gcc will move up smp_processor_id before the cpu_init */
255 * Check TSC synchronization with the BP:
257 check_tsc_sync_target();
260 * We need to hold call_lock, so there is no inconsistency
261 * between the time smp_call_function() determines number of
262 * IPI recipients, and the time when the determination is made
263 * for which cpus receive the IPI. Holding this
264 * lock helps us to not include this cpu in a currently in progress
265 * smp_call_function().
267 * We need to hold vector_lock so there the set of online cpus
268 * does not change while we are assigning vectors to cpus. Holding
269 * this lock ensures we don't half assign or remove an irq from a cpu.
273 set_cpu_online(smp_processor_id(), true);
274 unlock_vector_lock();
276 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
277 x86_platform
.nmi_init();
279 /* enable local interrupts */
282 /* to prevent fake stack check failure in clock setup */
283 boot_init_stack_canary();
285 x86_cpuinit
.setup_percpu_clockev();
292 * The bootstrap kernel entry code has set these up. Save them for
296 void __cpuinit
smp_store_cpu_info(int id
)
298 struct cpuinfo_x86
*c
= &cpu_data(id
);
303 identify_secondary_cpu(c
);
306 static bool __cpuinit
307 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
309 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
311 return !WARN_ONCE(cpu_to_node(cpu1
) != cpu_to_node(cpu2
),
312 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
313 "[node: %d != %d]. Ignoring dependency.\n",
314 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
317 #define link_mask(_m, c1, c2) \
319 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
320 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
323 static bool __cpuinit
match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
325 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
326 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
328 if (c
->phys_proc_id
== o
->phys_proc_id
&&
329 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
330 c
->compute_unit_id
== o
->compute_unit_id
)
331 return topology_sane(c
, o
, "smt");
333 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
334 c
->cpu_core_id
== o
->cpu_core_id
) {
335 return topology_sane(c
, o
, "smt");
341 static bool __cpuinit
match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
343 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
345 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
346 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
347 return topology_sane(c
, o
, "llc");
352 static bool __cpuinit
match_mc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
354 if (c
->phys_proc_id
== o
->phys_proc_id
)
355 return topology_sane(c
, o
, "mc");
360 void __cpuinit
set_cpu_sibling_map(int cpu
)
362 bool has_mc
= boot_cpu_data
.x86_max_cores
> 1;
363 bool has_smt
= smp_num_siblings
> 1;
364 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
365 struct cpuinfo_x86
*o
;
368 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
370 if (!has_smt
&& !has_mc
) {
371 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
372 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
373 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
378 for_each_cpu(i
, cpu_sibling_setup_mask
) {
381 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
382 link_mask(sibling
, cpu
, i
);
384 if ((i
== cpu
) || (has_mc
&& match_llc(c
, o
)))
385 link_mask(llc_shared
, cpu
, i
);
387 if ((i
== cpu
) || (has_mc
&& match_mc(c
, o
))) {
388 link_mask(core
, cpu
, i
);
391 * Does this new cpu bringup a new core?
393 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
395 * for each core in package, increment
396 * the booted_cores for this new cpu
398 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
401 * increment the core count for all
402 * the other cpus in this package
405 cpu_data(i
).booted_cores
++;
406 } else if (i
!= cpu
&& !c
->booted_cores
)
407 c
->booted_cores
= cpu_data(i
).booted_cores
;
412 /* maps the cpu to the sched domain representing multi-core */
413 const struct cpumask
*cpu_coregroup_mask(int cpu
)
415 return cpu_llc_shared_mask(cpu
);
418 static void impress_friends(void)
421 unsigned long bogosum
= 0;
423 * Allow the user to impress friends.
425 pr_debug("Before bogomips\n");
426 for_each_possible_cpu(cpu
)
427 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
428 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
429 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
432 (bogosum
/(5000/HZ
))%100);
434 pr_debug("Before bogocount - setting activated=1\n");
437 void __inquire_remote_apic(int apicid
)
439 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
440 const char * const names
[] = { "ID", "VERSION", "SPIV" };
444 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
446 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
447 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
452 status
= safe_apic_wait_icr_idle();
454 pr_cont("a previous APIC delivery may have failed\n");
456 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
461 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
462 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
465 case APIC_ICR_RR_VALID
:
466 status
= apic_read(APIC_RRR
);
467 pr_cont("%08x\n", status
);
476 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
477 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
478 * won't ... remember to clear down the APIC, etc later.
481 wakeup_secondary_cpu_via_nmi(int logical_apicid
, unsigned long start_eip
)
483 unsigned long send_status
, accept_status
= 0;
487 /* Boot on the stack */
488 /* Kick the second */
489 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, logical_apicid
);
491 pr_debug("Waiting for send to finish...\n");
492 send_status
= safe_apic_wait_icr_idle();
495 * Give the other CPU some time to accept the IPI.
498 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
499 maxlvt
= lapic_get_maxlvt();
500 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
501 apic_write(APIC_ESR
, 0);
502 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
504 pr_debug("NMI sent\n");
507 pr_err("APIC never delivered???\n");
509 pr_err("APIC delivery error (%lx)\n", accept_status
);
511 return (send_status
| accept_status
);
515 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
517 unsigned long send_status
, accept_status
= 0;
518 int maxlvt
, num_starts
, j
;
520 maxlvt
= lapic_get_maxlvt();
523 * Be paranoid about clearing APIC errors.
525 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
526 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
527 apic_write(APIC_ESR
, 0);
531 pr_debug("Asserting INIT\n");
534 * Turn INIT on target chip
539 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
542 pr_debug("Waiting for send to finish...\n");
543 send_status
= safe_apic_wait_icr_idle();
547 pr_debug("Deasserting INIT\n");
551 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
553 pr_debug("Waiting for send to finish...\n");
554 send_status
= safe_apic_wait_icr_idle();
557 atomic_set(&init_deasserted
, 1);
560 * Should we send STARTUP IPIs ?
562 * Determine this based on the APIC version.
563 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
565 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
571 * Paravirt / VMI wants a startup IPI hook here to set up the
572 * target processor state.
574 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
578 * Run STARTUP IPI loop.
580 pr_debug("#startup loops: %d\n", num_starts
);
582 for (j
= 1; j
<= num_starts
; j
++) {
583 pr_debug("Sending STARTUP #%d\n", j
);
584 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
585 apic_write(APIC_ESR
, 0);
587 pr_debug("After apic_write\n");
594 /* Boot on the stack */
595 /* Kick the second */
596 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
600 * Give the other CPU some time to accept the IPI.
604 pr_debug("Startup point 1\n");
606 pr_debug("Waiting for send to finish...\n");
607 send_status
= safe_apic_wait_icr_idle();
610 * Give the other CPU some time to accept the IPI.
613 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
614 apic_write(APIC_ESR
, 0);
615 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
616 if (send_status
|| accept_status
)
619 pr_debug("After Startup\n");
622 pr_err("APIC never delivered???\n");
624 pr_err("APIC delivery error (%lx)\n", accept_status
);
626 return (send_status
| accept_status
);
629 /* reduce the number of lines printed when booting a large cpu count system */
630 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
632 static int current_node
= -1;
633 int node
= early_cpu_to_node(cpu
);
635 if (system_state
== SYSTEM_BOOTING
) {
636 if (node
!= current_node
) {
637 if (current_node
> (-1))
640 pr_info("Booting Node %3d, Processors ", node
);
642 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " OK\n" : "");
645 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
650 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
651 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
652 * Returns zero if CPU booted OK, else error code from
653 * ->wakeup_secondary_cpu.
655 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
657 volatile u32
*trampoline_status
=
658 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
659 /* start_ip had better be page-aligned! */
660 unsigned long start_ip
= real_mode_header
->trampoline_start
;
662 unsigned long boot_error
= 0;
665 alternatives_smp_switch(1);
667 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
668 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
669 per_cpu(current_task
, cpu
) = idle
;
672 /* Stack for startup_32 can be just as for start_secondary onwards */
675 clear_tsk_thread_flag(idle
, TIF_FORK
);
676 initial_gs
= per_cpu_offset(cpu
);
677 per_cpu(kernel_stack
, cpu
) =
678 (unsigned long)task_stack_page(idle
) -
679 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
681 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
682 initial_code
= (unsigned long)start_secondary
;
683 stack_start
= idle
->thread
.sp
;
685 /* So we see what's up */
686 announce_cpu(cpu
, apicid
);
689 * This grunge runs the startup process for
690 * the targeted processor.
693 atomic_set(&init_deasserted
, 0);
695 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
697 pr_debug("Setting warm reset code and vector.\n");
699 smpboot_setup_warm_reset_vector(start_ip
);
701 * Be paranoid about clearing APIC errors.
703 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
704 apic_write(APIC_ESR
, 0);
710 * Kick the secondary CPU. Use the method in the APIC driver
711 * if it's defined - or use an INIT boot APIC message otherwise:
713 if (apic
->wakeup_secondary_cpu
)
714 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
716 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
720 * allow APs to start initializing.
722 pr_debug("Before Callout %d\n", cpu
);
723 cpumask_set_cpu(cpu
, cpu_callout_mask
);
724 pr_debug("After Callout %d\n", cpu
);
727 * Wait 5s total for a response
729 for (timeout
= 0; timeout
< 50000; timeout
++) {
730 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
731 break; /* It has booted */
734 * Allow other tasks to run while we wait for the
735 * AP to come online. This also gives a chance
736 * for the MTRR work(triggered by the AP coming online)
737 * to be completed in the stop machine context.
742 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
743 print_cpu_msr(&cpu_data(cpu
));
744 pr_debug("CPU%d: has booted.\n", cpu
);
747 if (*trampoline_status
== 0xA5A5A5A5)
748 /* trampoline started but...? */
749 pr_err("CPU%d: Stuck ??\n", cpu
);
751 /* trampoline code not run */
752 pr_err("CPU%d: Not responding\n", cpu
);
753 if (apic
->inquire_remote_apic
)
754 apic
->inquire_remote_apic(apicid
);
759 /* Try to put things back the way they were before ... */
760 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
762 /* was set by do_boot_cpu() */
763 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
765 /* was set by cpu_init() */
766 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
768 set_cpu_present(cpu
, false);
769 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
772 /* mark "stuck" area as not stuck */
773 *trampoline_status
= 0;
775 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
777 * Cleanup possible dangling ends...
779 smpboot_restore_warm_reset_vector();
784 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
786 int apicid
= apic
->cpu_present_to_apicid(cpu
);
790 WARN_ON(irqs_disabled());
792 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
794 if (apicid
== BAD_APICID
|| apicid
== boot_cpu_physical_apicid
||
795 !physid_isset(apicid
, phys_cpu_present_map
) ||
796 !apic
->apic_id_valid(apicid
)) {
797 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
802 * Already booted CPU?
804 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
805 pr_debug("do_boot_cpu %d Already started\n", cpu
);
810 * Save current MTRR state in case it was changed since early boot
811 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
815 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
817 err
= do_boot_cpu(apicid
, cpu
, tidle
);
819 pr_debug("do_boot_cpu failed %d\n", err
);
824 * Check TSC synchronization with the AP (keep irqs disabled
827 local_irq_save(flags
);
828 check_tsc_sync_source(cpu
);
829 local_irq_restore(flags
);
831 while (!cpu_online(cpu
)) {
833 touch_nmi_watchdog();
840 * arch_disable_smp_support() - disables SMP support for x86 at runtime
842 void arch_disable_smp_support(void)
844 disable_ioapic_support();
848 * Fall back to non SMP mode after errors.
850 * RED-PEN audit/test this more. I bet there is more state messed up here.
852 static __init
void disable_smp(void)
854 init_cpu_present(cpumask_of(0));
855 init_cpu_possible(cpumask_of(0));
856 smpboot_clear_io_apic_irqs();
858 if (smp_found_config
)
859 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
861 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
862 cpumask_set_cpu(0, cpu_sibling_mask(0));
863 cpumask_set_cpu(0, cpu_core_mask(0));
867 * Various sanity checks.
869 static int __init
smp_sanity_check(unsigned max_cpus
)
873 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
874 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
878 pr_warn("More than 8 CPUs detected - skipping them\n"
879 "Use CONFIG_X86_BIGSMP\n");
882 for_each_present_cpu(cpu
) {
884 set_cpu_present(cpu
, false);
889 for_each_possible_cpu(cpu
) {
891 set_cpu_possible(cpu
, false);
899 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
900 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
901 hard_smp_processor_id());
903 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
907 * If we couldn't find an SMP configuration at boot time,
908 * get out of here now!
910 if (!smp_found_config
&& !acpi_lapic
) {
912 pr_notice("SMP motherboard not detected\n");
914 if (APIC_init_uniprocessor())
915 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
920 * Should not be necessary because the MP table should list the boot
921 * CPU too, but we do it for the sake of robustness anyway.
923 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
924 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
925 boot_cpu_physical_apicid
);
926 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
931 * If we couldn't find a local APIC, then get out of here now!
933 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
936 pr_err("BIOS bug, local APIC #%d not detected!...\n",
937 boot_cpu_physical_apicid
);
938 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
940 smpboot_clear_io_apic();
941 disable_ioapic_support();
948 * If SMP should be disabled, then really disable it!
951 pr_info("SMP mode deactivated\n");
952 smpboot_clear_io_apic();
956 bsp_end_local_APIC_setup();
963 static void __init
smp_cpu_index_default(void)
966 struct cpuinfo_x86
*c
;
968 for_each_possible_cpu(i
) {
970 /* mark all to hotplug */
971 c
->cpu_index
= nr_cpu_ids
;
976 * Prepare for SMP bootup. The MP table or ACPI has been read
977 * earlier. Just do some sanity checking here and enable APIC mode.
979 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
984 smp_cpu_index_default();
987 * Setup boot CPU information
989 smp_store_cpu_info(0); /* Final full version of the data */
990 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
993 current_thread_info()->cpu
= 0; /* needed? */
994 for_each_possible_cpu(i
) {
995 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
996 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
997 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
999 set_cpu_sibling_map(0);
1002 if (smp_sanity_check(max_cpus
) < 0) {
1003 pr_info("SMP disabled\n");
1008 default_setup_apic_routing();
1011 if (read_apic_id() != boot_cpu_physical_apicid
) {
1012 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1013 read_apic_id(), boot_cpu_physical_apicid
);
1014 /* Or can we switch back to PIC here? */
1021 * Switch from PIC to APIC mode.
1026 * Enable IO APIC before setting up error vector
1028 if (!skip_ioapic_setup
&& nr_ioapics
)
1031 bsp_end_local_APIC_setup();
1033 if (apic
->setup_portio_remap
)
1034 apic
->setup_portio_remap();
1036 smpboot_setup_io_apic();
1038 * Set up local APIC timer on boot CPU.
1041 pr_info("CPU%d: ", 0);
1042 print_cpu_info(&cpu_data(0));
1043 x86_init
.timers
.setup_percpu_clockev();
1048 set_mtrr_aps_delayed_init();
1053 void arch_disable_nonboot_cpus_begin(void)
1056 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1057 * In the suspend path, we will be back in the SMP mode shortly anyways.
1059 skip_smp_alternatives
= true;
1062 void arch_disable_nonboot_cpus_end(void)
1064 skip_smp_alternatives
= false;
1067 void arch_enable_nonboot_cpus_begin(void)
1069 set_mtrr_aps_delayed_init();
1072 void arch_enable_nonboot_cpus_end(void)
1078 * Early setup to make printk work.
1080 void __init
native_smp_prepare_boot_cpu(void)
1082 int me
= smp_processor_id();
1083 switch_to_new_gdt(me
);
1084 /* already set me in cpu_online_mask in boot_cpu_init() */
1085 cpumask_set_cpu(me
, cpu_callout_mask
);
1086 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1089 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1091 pr_debug("Boot done\n");
1095 #ifdef CONFIG_X86_IO_APIC
1096 setup_ioapic_dest();
1101 static int __initdata setup_possible_cpus
= -1;
1102 static int __init
_setup_possible_cpus(char *str
)
1104 get_option(&str
, &setup_possible_cpus
);
1107 early_param("possible_cpus", _setup_possible_cpus
);
1111 * cpu_possible_mask should be static, it cannot change as cpu's
1112 * are onlined, or offlined. The reason is per-cpu data-structures
1113 * are allocated by some modules at init time, and dont expect to
1114 * do this dynamically on cpu arrival/departure.
1115 * cpu_present_mask on the other hand can change dynamically.
1116 * In case when cpu_hotplug is not compiled, then we resort to current
1117 * behaviour, which is cpu_possible == cpu_present.
1120 * Three ways to find out the number of additional hotplug CPUs:
1121 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1122 * - The user can overwrite it with possible_cpus=NUM
1123 * - Otherwise don't reserve additional CPUs.
1124 * We do this because additional CPUs waste a lot of memory.
1127 __init
void prefill_possible_map(void)
1131 /* no processor from mptable or madt */
1132 if (!num_processors
)
1135 i
= setup_max_cpus
?: 1;
1136 if (setup_possible_cpus
== -1) {
1137 possible
= num_processors
;
1138 #ifdef CONFIG_HOTPLUG_CPU
1140 possible
+= disabled_cpus
;
1146 possible
= setup_possible_cpus
;
1148 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1150 /* nr_cpu_ids could be reduced via nr_cpus= */
1151 if (possible
> nr_cpu_ids
) {
1152 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1153 possible
, nr_cpu_ids
);
1154 possible
= nr_cpu_ids
;
1157 #ifdef CONFIG_HOTPLUG_CPU
1158 if (!setup_max_cpus
)
1161 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1162 possible
, setup_max_cpus
);
1166 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1167 possible
, max_t(int, possible
- num_processors
, 0));
1169 for (i
= 0; i
< possible
; i
++)
1170 set_cpu_possible(i
, true);
1171 for (; i
< NR_CPUS
; i
++)
1172 set_cpu_possible(i
, false);
1174 nr_cpu_ids
= possible
;
1177 #ifdef CONFIG_HOTPLUG_CPU
1179 static void remove_siblinginfo(int cpu
)
1182 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1184 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1185 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1187 * last thread sibling in this cpu core going down
1189 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1190 cpu_data(sibling
).booted_cores
--;
1193 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1194 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1195 cpumask_clear(cpu_sibling_mask(cpu
));
1196 cpumask_clear(cpu_core_mask(cpu
));
1197 c
->phys_proc_id
= 0;
1199 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1202 static void __ref
remove_cpu_from_maps(int cpu
)
1204 set_cpu_online(cpu
, false);
1205 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1206 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1207 /* was set by cpu_init() */
1208 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1209 numa_remove_cpu(cpu
);
1212 void cpu_disable_common(void)
1214 int cpu
= smp_processor_id();
1216 remove_siblinginfo(cpu
);
1218 /* It's now safe to remove this processor from the online map */
1220 remove_cpu_from_maps(cpu
);
1221 unlock_vector_lock();
1225 int native_cpu_disable(void)
1227 int cpu
= smp_processor_id();
1230 * Perhaps use cpufreq to drop frequency, but that could go
1231 * into generic code.
1233 * We won't take down the boot processor on i386 due to some
1234 * interrupts only being able to be serviced by the BSP.
1235 * Especially so if we're not using an IOAPIC -zwane
1242 cpu_disable_common();
1246 void native_cpu_die(unsigned int cpu
)
1248 /* We don't do anything here: idle task is faking death itself. */
1251 for (i
= 0; i
< 10; i
++) {
1252 /* They ack this in play_dead by setting CPU_DEAD */
1253 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1254 if (system_state
== SYSTEM_RUNNING
)
1255 pr_info("CPU %u is now offline\n", cpu
);
1257 if (1 == num_online_cpus())
1258 alternatives_smp_switch(0);
1263 pr_err("CPU %u didn't die...\n", cpu
);
1266 void play_dead_common(void)
1269 reset_lazy_tlbstate();
1270 amd_e400_remove_cpu(raw_smp_processor_id());
1274 __this_cpu_write(cpu_state
, CPU_DEAD
);
1277 * With physical CPU hotplug, we should halt the cpu
1279 local_irq_disable();
1283 * We need to flush the caches before going to sleep, lest we have
1284 * dirty data in our caches when we come back up.
1286 static inline void mwait_play_dead(void)
1288 unsigned int eax
, ebx
, ecx
, edx
;
1289 unsigned int highest_cstate
= 0;
1290 unsigned int highest_subcstate
= 0;
1293 struct cpuinfo_x86
*c
= __this_cpu_ptr(&cpu_info
);
1295 if (!(this_cpu_has(X86_FEATURE_MWAIT
) && mwait_usable(c
)))
1297 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1299 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1302 eax
= CPUID_MWAIT_LEAF
;
1304 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1307 * eax will be 0 if EDX enumeration is not valid.
1308 * Initialized below to cstate, sub_cstate value when EDX is valid.
1310 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1313 edx
>>= MWAIT_SUBSTATE_SIZE
;
1314 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1315 if (edx
& MWAIT_SUBSTATE_MASK
) {
1317 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1320 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1321 (highest_subcstate
- 1);
1325 * This should be a memory location in a cache line which is
1326 * unlikely to be touched by other processors. The actual
1327 * content is immaterial as it is not actually modified in any way.
1329 mwait_ptr
= ¤t_thread_info()->flags
;
1335 * The CLFLUSH is a workaround for erratum AAI65 for
1336 * the Xeon 7400 series. It's not clear it is actually
1337 * needed, but it should be harmless in either case.
1338 * The WBINVD is insufficient due to the spurious-wakeup
1339 * case where we return around the loop.
1342 __monitor(mwait_ptr
, 0, 0);
1348 static inline void hlt_play_dead(void)
1350 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1358 void native_play_dead(void)
1361 tboot_shutdown(TB_SHUTDOWN_WFS
);
1363 mwait_play_dead(); /* Only returns on failure */
1364 if (cpuidle_play_dead())
1368 #else /* ... !CONFIG_HOTPLUG_CPU */
1369 int native_cpu_disable(void)
1374 void native_cpu_die(unsigned int cpu
)
1376 /* We said "no" in __cpu_disable */
1380 void native_play_dead(void)