2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/microcode.h>
82 /* Number of siblings per CPU package */
83 int smp_num_siblings
= 1;
84 EXPORT_SYMBOL(smp_num_siblings
);
86 /* Last level cache ID of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
89 /* representing HT siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
93 /* representing HT and core siblings of each logical CPU */
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
95 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
99 /* Per CPU bogomips and other parameters */
100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
101 EXPORT_PER_CPU_SYMBOL(cpu_info
);
103 /* Logical package management. We might want to allocate that dynamically */
104 static int *physical_to_logical_pkg __read_mostly
;
105 static unsigned long *physical_package_map __read_mostly
;;
106 static unsigned int max_physical_pkg_id __read_mostly
;
107 unsigned int __max_logical_packages __read_mostly
;
108 EXPORT_SYMBOL(__max_logical_packages
);
109 static unsigned int logical_packages __read_mostly
;
111 /* Maximum number of SMT threads on any online core */
112 int __max_smt_threads __read_mostly
;
114 /* Flag to indicate if a complete sched domain rebuild is required */
115 bool x86_topology_update
;
117 int arch_update_cpu_topology(void)
119 int retval
= x86_topology_update
;
121 x86_topology_update
= false;
125 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
129 spin_lock_irqsave(&rtc_lock
, flags
);
130 CMOS_WRITE(0xa, 0xf);
131 spin_unlock_irqrestore(&rtc_lock
, flags
);
132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
138 static inline void smpboot_restore_warm_reset_vector(void)
143 * Paranoid: Set warm reset code and vector here back
146 spin_lock_irqsave(&rtc_lock
, flags
);
148 spin_unlock_irqrestore(&rtc_lock
, flags
);
150 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
154 * Report back to the Boot Processor during boot time or to the caller processor
157 static void smp_callin(void)
162 * If waken up by an INIT in an 82489DX configuration
163 * cpu_callout_mask guarantees we don't get here before
164 * an INIT_deassert IPI reaches our local APIC, so it is
165 * now safe to touch our local APIC.
167 cpuid
= smp_processor_id();
170 * (This works even if the APIC is not enabled.)
172 phys_id
= read_apic_id();
175 * the boot CPU has finished the init stage and is spinning
176 * on callin_map until we finish. We are free to set up this
177 * CPU, first the APIC. (this is probably redundant on most
183 * Save our processor parameters. Note: this information
184 * is needed for clock calibration.
186 smp_store_cpu_info(cpuid
);
189 * The topology information must be up to date before
190 * calibrate_delay() and notify_cpu_starting().
192 set_cpu_sibling_map(raw_smp_processor_id());
196 * Update loops_per_jiffy in cpu_data. Previous call to
197 * smp_store_cpu_info() stored a value that is close but not as
198 * accurate as the value just calculated.
201 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
202 pr_debug("Stack at about %p\n", &cpuid
);
206 notify_cpu_starting(cpuid
);
209 * Allow the master to continue.
211 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
214 static int cpu0_logical_apicid
;
215 static int enable_start_cpu0
;
217 * Activate a secondary processor.
219 static void notrace
start_secondary(void *unused
)
222 * Don't put *anything* except direct CPU state initialization
223 * before cpu_init(), SMP booting is too fragile that we want to
224 * limit the things done here to the most necessary things.
226 if (IS_ENABLED(CONFIG_X86_64
) && boot_cpu_has(X86_FEATURE_PCID
))
227 __write_cr4(__read_cr4() | X86_CR4_PCIDE
);
229 x86_cpuinit
.early_percpu_clock_init();
233 enable_start_cpu0
= 0;
236 /* switch away from the initial page table */
237 load_cr3(swapper_pg_dir
);
241 /* otherwise gcc will move up smp_processor_id before the cpu_init */
244 * Check TSC synchronization with the BP:
246 check_tsc_sync_target();
249 * Lock vector_lock and initialize the vectors on this cpu
250 * before setting the cpu online. We must set it online with
251 * vector_lock held to prevent a concurrent setup/teardown
252 * from seeing a half valid vector space.
255 setup_vector_irq(smp_processor_id());
256 set_cpu_online(smp_processor_id(), true);
257 unlock_vector_lock();
258 cpu_set_state_online(smp_processor_id());
259 x86_platform
.nmi_init();
261 /* enable local interrupts */
264 /* to prevent fake stack check failure in clock setup */
265 boot_init_stack_canary();
267 x86_cpuinit
.setup_percpu_clockev();
270 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
274 * topology_update_package_map - Update the physical to logical package map
275 * @pkg: The physical package id as retrieved via CPUID
276 * @cpu: The cpu for which this is updated
278 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
282 /* Called from early boot ? */
283 if (!physical_package_map
)
286 if (pkg
>= max_physical_pkg_id
)
289 /* Set the logical package id */
290 if (test_and_set_bit(pkg
, physical_package_map
))
293 if (logical_packages
>= __max_logical_packages
) {
294 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
295 logical_packages
, cpu
, __max_logical_packages
);
299 new = logical_packages
++;
301 pr_info("CPU %u Converting physical %u to logical package %u\n",
304 physical_to_logical_pkg
[pkg
] = new;
307 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
312 * topology_phys_to_logical_pkg - Map a physical package id to a logical
314 * Returns logical package id or -1 if not found
316 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
318 if (phys_pkg
>= max_physical_pkg_id
)
320 return physical_to_logical_pkg
[phys_pkg
];
322 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
324 static void __init
smp_init_package_map(struct cpuinfo_x86
*c
, unsigned int cpu
)
330 * Today neither Intel nor AMD support heterogenous systems. That
331 * might change in the future....
333 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
334 * computation, this won't actually work since some Intel BIOSes
335 * report inconsistent HT data when they disable HT.
337 * In particular, they reduce the APIC-IDs to only include the cores,
338 * but leave the CPUID topology to say there are (2) siblings.
339 * This means we don't know how many threads there will be until
340 * after the APIC enumeration.
342 * By not including this we'll sometimes over-estimate the number of
343 * logical packages by the amount of !present siblings, but this is
344 * still better than MAX_LOCAL_APIC.
346 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
347 * on the command line leading to a similar issue as the HT disable
348 * problem because the hyperthreads are usually enumerated after the
351 ncpus
= boot_cpu_data
.x86_max_cores
;
353 pr_warn("x86_max_cores == zero !?!?");
357 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
358 logical_packages
= 0;
361 * Possibly larger than what we need as the number of apic ids per
362 * package can be smaller than the actual used apic ids.
364 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
365 size
= max_physical_pkg_id
* sizeof(unsigned int);
366 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
367 memset(physical_to_logical_pkg
, 0xff, size
);
368 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
369 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
371 pr_info("Max logical packages: %u\n", __max_logical_packages
);
373 topology_update_package_map(c
->phys_proc_id
, cpu
);
376 void __init
smp_store_boot_cpu_info(void)
378 int id
= 0; /* CPU 0 */
379 struct cpuinfo_x86
*c
= &cpu_data(id
);
383 smp_init_package_map(c
, id
);
387 * The bootstrap kernel entry code has set these up. Save them for
390 void smp_store_cpu_info(int id
)
392 struct cpuinfo_x86
*c
= &cpu_data(id
);
397 * During boot time, CPU0 has this setup already. Save the info when
398 * bringing up AP or offlined CPU0.
400 identify_secondary_cpu(c
);
404 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
406 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
408 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
412 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
414 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
416 return !WARN_ONCE(!topology_same_node(c
, o
),
417 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
418 "[node: %d != %d]. Ignoring dependency.\n",
419 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
422 #define link_mask(mfunc, c1, c2) \
424 cpumask_set_cpu((c1), mfunc(c2)); \
425 cpumask_set_cpu((c2), mfunc(c1)); \
428 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
430 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
431 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
433 if (c
->phys_proc_id
== o
->phys_proc_id
&&
434 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
435 if (c
->cpu_core_id
== o
->cpu_core_id
)
436 return topology_sane(c
, o
, "smt");
438 if ((c
->cu_id
!= 0xff) &&
439 (o
->cu_id
!= 0xff) &&
440 (c
->cu_id
== o
->cu_id
))
441 return topology_sane(c
, o
, "smt");
444 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
445 c
->cpu_core_id
== o
->cpu_core_id
) {
446 return topology_sane(c
, o
, "smt");
452 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
454 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
456 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
457 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
458 return topology_sane(c
, o
, "llc");
464 * Unlike the other levels, we do not enforce keeping a
465 * multicore group inside a NUMA node. If this happens, we will
466 * discard the MC level of the topology later.
468 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
470 if (c
->phys_proc_id
== o
->phys_proc_id
)
475 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
476 static inline int x86_sched_itmt_flags(void)
478 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
481 #ifdef CONFIG_SCHED_MC
482 static int x86_core_flags(void)
484 return cpu_core_flags() | x86_sched_itmt_flags();
487 #ifdef CONFIG_SCHED_SMT
488 static int x86_smt_flags(void)
490 return cpu_smt_flags() | x86_sched_itmt_flags();
495 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
496 #ifdef CONFIG_SCHED_SMT
497 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
499 #ifdef CONFIG_SCHED_MC
500 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
505 static struct sched_domain_topology_level x86_topology
[] = {
506 #ifdef CONFIG_SCHED_SMT
507 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
509 #ifdef CONFIG_SCHED_MC
510 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
512 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
517 * Set if a package/die has multiple NUMA nodes inside.
518 * AMD Magny-Cours and Intel Cluster-on-Die have this.
520 static bool x86_has_numa_in_package
;
522 void set_cpu_sibling_map(int cpu
)
524 bool has_smt
= smp_num_siblings
> 1;
525 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
526 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
527 struct cpuinfo_x86
*o
;
530 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
533 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
534 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
535 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
540 for_each_cpu(i
, cpu_sibling_setup_mask
) {
543 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
544 link_mask(topology_sibling_cpumask
, cpu
, i
);
546 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
547 link_mask(cpu_llc_shared_mask
, cpu
, i
);
552 * This needs a separate iteration over the cpus because we rely on all
553 * topology_sibling_cpumask links to be set-up.
555 for_each_cpu(i
, cpu_sibling_setup_mask
) {
558 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
559 link_mask(topology_core_cpumask
, cpu
, i
);
562 * Does this new cpu bringup a new core?
565 topology_sibling_cpumask(cpu
)) == 1) {
567 * for each core in package, increment
568 * the booted_cores for this new cpu
571 topology_sibling_cpumask(i
)) == i
)
574 * increment the core count for all
575 * the other cpus in this package
578 cpu_data(i
).booted_cores
++;
579 } else if (i
!= cpu
&& !c
->booted_cores
)
580 c
->booted_cores
= cpu_data(i
).booted_cores
;
582 if (match_die(c
, o
) && !topology_same_node(c
, o
))
583 x86_has_numa_in_package
= true;
586 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
587 if (threads
> __max_smt_threads
)
588 __max_smt_threads
= threads
;
591 /* maps the cpu to the sched domain representing multi-core */
592 const struct cpumask
*cpu_coregroup_mask(int cpu
)
594 return cpu_llc_shared_mask(cpu
);
597 static void impress_friends(void)
600 unsigned long bogosum
= 0;
602 * Allow the user to impress friends.
604 pr_debug("Before bogomips\n");
605 for_each_possible_cpu(cpu
)
606 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
607 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
608 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
611 (bogosum
/(5000/HZ
))%100);
613 pr_debug("Before bogocount - setting activated=1\n");
616 void __inquire_remote_apic(int apicid
)
618 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
619 const char * const names
[] = { "ID", "VERSION", "SPIV" };
623 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
625 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
626 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
631 status
= safe_apic_wait_icr_idle();
633 pr_cont("a previous APIC delivery may have failed\n");
635 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
640 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
641 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
644 case APIC_ICR_RR_VALID
:
645 status
= apic_read(APIC_RRR
);
646 pr_cont("%08x\n", status
);
655 * The Multiprocessor Specification 1.4 (1997) example code suggests
656 * that there should be a 10ms delay between the BSP asserting INIT
657 * and de-asserting INIT, when starting a remote processor.
658 * But that slows boot and resume on modern processors, which include
659 * many cores and don't require that delay.
661 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
662 * Modern processor families are quirked to remove the delay entirely.
664 #define UDELAY_10MS_DEFAULT 10000
666 static unsigned int init_udelay
= UINT_MAX
;
668 static int __init
cpu_init_udelay(char *str
)
670 get_option(&str
, &init_udelay
);
674 early_param("cpu_init_udelay", cpu_init_udelay
);
676 static void __init
smp_quirk_init_udelay(void)
678 /* if cmdline changed it from default, leave it alone */
679 if (init_udelay
!= UINT_MAX
)
682 /* if modern processor, use no delay */
683 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
684 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
688 /* else, use legacy delay */
689 init_udelay
= UDELAY_10MS_DEFAULT
;
693 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
694 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
695 * won't ... remember to clear down the APIC, etc later.
698 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
700 unsigned long send_status
, accept_status
= 0;
704 /* Boot on the stack */
705 /* Kick the second */
706 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
708 pr_debug("Waiting for send to finish...\n");
709 send_status
= safe_apic_wait_icr_idle();
712 * Give the other CPU some time to accept the IPI.
715 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
716 maxlvt
= lapic_get_maxlvt();
717 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
718 apic_write(APIC_ESR
, 0);
719 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
721 pr_debug("NMI sent\n");
724 pr_err("APIC never delivered???\n");
726 pr_err("APIC delivery error (%lx)\n", accept_status
);
728 return (send_status
| accept_status
);
732 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
734 unsigned long send_status
= 0, accept_status
= 0;
735 int maxlvt
, num_starts
, j
;
737 maxlvt
= lapic_get_maxlvt();
740 * Be paranoid about clearing APIC errors.
742 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
743 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
744 apic_write(APIC_ESR
, 0);
748 pr_debug("Asserting INIT\n");
751 * Turn INIT on target chip
756 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
759 pr_debug("Waiting for send to finish...\n");
760 send_status
= safe_apic_wait_icr_idle();
764 pr_debug("Deasserting INIT\n");
768 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
770 pr_debug("Waiting for send to finish...\n");
771 send_status
= safe_apic_wait_icr_idle();
776 * Should we send STARTUP IPIs ?
778 * Determine this based on the APIC version.
779 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
781 if (APIC_INTEGRATED(boot_cpu_apic_version
))
787 * Run STARTUP IPI loop.
789 pr_debug("#startup loops: %d\n", num_starts
);
791 for (j
= 1; j
<= num_starts
; j
++) {
792 pr_debug("Sending STARTUP #%d\n", j
);
793 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
794 apic_write(APIC_ESR
, 0);
796 pr_debug("After apic_write\n");
803 /* Boot on the stack */
804 /* Kick the second */
805 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
809 * Give the other CPU some time to accept the IPI.
811 if (init_udelay
== 0)
816 pr_debug("Startup point 1\n");
818 pr_debug("Waiting for send to finish...\n");
819 send_status
= safe_apic_wait_icr_idle();
822 * Give the other CPU some time to accept the IPI.
824 if (init_udelay
== 0)
829 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
830 apic_write(APIC_ESR
, 0);
831 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
832 if (send_status
|| accept_status
)
835 pr_debug("After Startup\n");
838 pr_err("APIC never delivered???\n");
840 pr_err("APIC delivery error (%lx)\n", accept_status
);
842 return (send_status
| accept_status
);
845 /* reduce the number of lines printed when booting a large cpu count system */
846 static void announce_cpu(int cpu
, int apicid
)
848 static int current_node
= -1;
849 int node
= early_cpu_to_node(cpu
);
850 static int width
, node_width
;
853 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
856 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
859 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
861 if (system_state
< SYSTEM_RUNNING
) {
862 if (node
!= current_node
) {
863 if (current_node
> (-1))
867 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
868 node_width
- num_digits(node
), " ", node
);
871 /* Add padding for the BSP */
873 pr_cont("%*s", width
+ 1, " ");
875 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
878 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
882 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
886 cpu
= smp_processor_id();
887 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
894 * Wake up AP by INIT, INIT, STARTUP sequence.
896 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
897 * boot-strap code which is not a desired behavior for waking up BSP. To
898 * void the boot-strap code, wake up CPU0 by NMI instead.
900 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
901 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
902 * We'll change this code in the future to wake up hard offlined CPU0 if
903 * real platform and request are available.
906 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
907 int *cpu0_nmi_registered
)
915 * Wake up AP by INIT, INIT, STARTUP sequence.
918 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
923 * Wake up BSP by nmi.
925 * Register a NMI handler to help wake up CPU0.
927 boot_error
= register_nmi_handler(NMI_LOCAL
,
928 wakeup_cpu0_nmi
, 0, "wake_cpu0");
931 enable_start_cpu0
= 1;
932 *cpu0_nmi_registered
= 1;
933 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
934 id
= cpu0_logical_apicid
;
937 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
946 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
948 /* Just in case we booted with a single CPU. */
949 alternatives_enable_smp();
951 per_cpu(current_task
, cpu
) = idle
;
954 /* Stack for startup_32 can be just as for start_secondary onwards */
956 per_cpu(cpu_current_top_of_stack
, cpu
) = task_top_of_stack(idle
);
958 initial_gs
= per_cpu_offset(cpu
);
963 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
964 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
965 * Returns zero if CPU booted OK, else error code from
966 * ->wakeup_secondary_cpu.
968 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
969 int *cpu0_nmi_registered
)
971 volatile u32
*trampoline_status
=
972 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
973 /* start_ip had better be page-aligned! */
974 unsigned long start_ip
= real_mode_header
->trampoline_start
;
976 unsigned long boot_error
= 0;
977 unsigned long timeout
;
979 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
980 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
981 initial_code
= (unsigned long)start_secondary
;
982 initial_stack
= idle
->thread
.sp
;
984 /* Enable the espfix hack for this CPU */
987 /* So we see what's up */
988 announce_cpu(cpu
, apicid
);
991 * This grunge runs the startup process for
992 * the targeted processor.
995 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
997 pr_debug("Setting warm reset code and vector.\n");
999 smpboot_setup_warm_reset_vector(start_ip
);
1001 * Be paranoid about clearing APIC errors.
1003 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1004 apic_write(APIC_ESR
, 0);
1005 apic_read(APIC_ESR
);
1010 * AP might wait on cpu_callout_mask in cpu_init() with
1011 * cpu_initialized_mask set if previous attempt to online
1012 * it timed-out. Clear cpu_initialized_mask so that after
1013 * INIT/SIPI it could start with a clean state.
1015 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1019 * Wake up a CPU in difference cases:
1020 * - Use the method in the APIC driver if it's defined
1022 * - Use an INIT boot APIC message for APs or NMI for BSP.
1024 if (apic
->wakeup_secondary_cpu
)
1025 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1027 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1028 cpu0_nmi_registered
);
1032 * Wait 10s total for first sign of life from AP
1035 timeout
= jiffies
+ 10*HZ
;
1036 while (time_before(jiffies
, timeout
)) {
1037 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1039 * Tell AP to proceed with initialization
1041 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1051 * Wait till AP completes initial initialization
1053 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1055 * Allow other tasks to run while we wait for the
1056 * AP to come online. This also gives a chance
1057 * for the MTRR work(triggered by the AP coming online)
1058 * to be completed in the stop machine context.
1064 /* mark "stuck" area as not stuck */
1065 *trampoline_status
= 0;
1067 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1069 * Cleanup possible dangling ends...
1071 smpboot_restore_warm_reset_vector();
1077 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1079 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1080 int cpu0_nmi_registered
= 0;
1081 unsigned long flags
;
1084 WARN_ON(irqs_disabled());
1086 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1088 if (apicid
== BAD_APICID
||
1089 !physid_isset(apicid
, phys_cpu_present_map
) ||
1090 !apic
->apic_id_valid(apicid
)) {
1091 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1096 * Already booted CPU?
1098 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1099 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1104 * Save current MTRR state in case it was changed since early boot
1105 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1109 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1110 err
= cpu_check_up_prepare(cpu
);
1111 if (err
&& err
!= -EBUSY
)
1114 /* the FPU context is blank, nobody can own it */
1115 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1117 common_cpu_up(cpu
, tidle
);
1119 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1121 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1127 * Check TSC synchronization with the AP (keep irqs disabled
1130 local_irq_save(flags
);
1131 check_tsc_sync_source(cpu
);
1132 local_irq_restore(flags
);
1134 while (!cpu_online(cpu
)) {
1136 touch_nmi_watchdog();
1141 * Clean up the nmi handler. Do this after the callin and callout sync
1142 * to avoid impact of possible long unregister time.
1144 if (cpu0_nmi_registered
)
1145 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1151 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1153 void arch_disable_smp_support(void)
1155 disable_ioapic_support();
1159 * Fall back to non SMP mode after errors.
1161 * RED-PEN audit/test this more. I bet there is more state messed up here.
1163 static __init
void disable_smp(void)
1165 pr_info("SMP disabled\n");
1167 disable_ioapic_support();
1169 init_cpu_present(cpumask_of(0));
1170 init_cpu_possible(cpumask_of(0));
1172 if (smp_found_config
)
1173 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1175 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1176 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1177 cpumask_set_cpu(0, topology_core_cpumask(0));
1188 * Various sanity checks.
1190 static int __init
smp_sanity_check(unsigned max_cpus
)
1194 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1195 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1199 pr_warn("More than 8 CPUs detected - skipping them\n"
1200 "Use CONFIG_X86_BIGSMP\n");
1203 for_each_present_cpu(cpu
) {
1205 set_cpu_present(cpu
, false);
1210 for_each_possible_cpu(cpu
) {
1212 set_cpu_possible(cpu
, false);
1220 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1221 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1222 hard_smp_processor_id());
1224 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1228 * If we couldn't find an SMP configuration at boot time,
1229 * get out of here now!
1231 if (!smp_found_config
&& !acpi_lapic
) {
1233 pr_notice("SMP motherboard not detected\n");
1234 return SMP_NO_CONFIG
;
1238 * Should not be necessary because the MP table should list the boot
1239 * CPU too, but we do it for the sake of robustness anyway.
1241 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1242 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1243 boot_cpu_physical_apicid
);
1244 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1249 * If we couldn't find a local APIC, then get out of here now!
1251 if (APIC_INTEGRATED(boot_cpu_apic_version
) &&
1252 !boot_cpu_has(X86_FEATURE_APIC
)) {
1253 if (!disable_apic
) {
1254 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1255 boot_cpu_physical_apicid
);
1256 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1262 * If SMP should be disabled, then really disable it!
1265 pr_info("SMP mode deactivated\n");
1266 return SMP_FORCE_UP
;
1272 static void __init
smp_cpu_index_default(void)
1275 struct cpuinfo_x86
*c
;
1277 for_each_possible_cpu(i
) {
1279 /* mark all to hotplug */
1280 c
->cpu_index
= nr_cpu_ids
;
1285 * Prepare for SMP bootup. The MP table or ACPI has been read
1286 * earlier. Just do some sanity checking here and enable APIC mode.
1288 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1292 smp_cpu_index_default();
1295 * Setup boot CPU information
1297 smp_store_boot_cpu_info(); /* Final full version of the data */
1298 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1301 for_each_possible_cpu(i
) {
1302 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1303 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1304 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1308 * Set 'default' x86 topology, this matches default_topology() in that
1309 * it has NUMA nodes as a topology level. See also
1310 * native_smp_cpus_done().
1312 * Must be done before set_cpus_sibling_map() is ran.
1314 set_sched_topology(x86_topology
);
1316 set_cpu_sibling_map(0);
1318 switch (smp_sanity_check(max_cpus
)) {
1321 if (APIC_init_uniprocessor())
1322 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1329 apic_bsp_setup(false);
1335 if (read_apic_id() != boot_cpu_physical_apicid
) {
1336 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1337 read_apic_id(), boot_cpu_physical_apicid
);
1338 /* Or can we switch back to PIC here? */
1341 default_setup_apic_routing();
1342 cpu0_logical_apicid
= apic_bsp_setup(false);
1345 print_cpu_info(&cpu_data(0));
1349 set_mtrr_aps_delayed_init();
1351 smp_quirk_init_udelay();
1354 void arch_enable_nonboot_cpus_begin(void)
1356 set_mtrr_aps_delayed_init();
1359 void arch_enable_nonboot_cpus_end(void)
1365 * Early setup to make printk work.
1367 void __init
native_smp_prepare_boot_cpu(void)
1369 int me
= smp_processor_id();
1370 switch_to_new_gdt(me
);
1371 /* already set me in cpu_online_mask in boot_cpu_init() */
1372 cpumask_set_cpu(me
, cpu_callout_mask
);
1373 cpu_set_state_online(me
);
1376 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1378 pr_debug("Boot done\n");
1380 if (x86_has_numa_in_package
)
1381 set_sched_topology(x86_numa_in_package_topology
);
1385 setup_ioapic_dest();
1389 static int __initdata setup_possible_cpus
= -1;
1390 static int __init
_setup_possible_cpus(char *str
)
1392 get_option(&str
, &setup_possible_cpus
);
1395 early_param("possible_cpus", _setup_possible_cpus
);
1399 * cpu_possible_mask should be static, it cannot change as cpu's
1400 * are onlined, or offlined. The reason is per-cpu data-structures
1401 * are allocated by some modules at init time, and dont expect to
1402 * do this dynamically on cpu arrival/departure.
1403 * cpu_present_mask on the other hand can change dynamically.
1404 * In case when cpu_hotplug is not compiled, then we resort to current
1405 * behaviour, which is cpu_possible == cpu_present.
1408 * Three ways to find out the number of additional hotplug CPUs:
1409 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1410 * - The user can overwrite it with possible_cpus=NUM
1411 * - Otherwise don't reserve additional CPUs.
1412 * We do this because additional CPUs waste a lot of memory.
1415 __init
void prefill_possible_map(void)
1419 /* No boot processor was found in mptable or ACPI MADT */
1420 if (!num_processors
) {
1421 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1422 int apicid
= boot_cpu_physical_apicid
;
1423 int cpu
= hard_smp_processor_id();
1425 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1427 /* Make sure boot cpu is enumerated */
1428 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1429 apic
->apic_id_valid(apicid
))
1430 generic_processor_info(apicid
, boot_cpu_apic_version
);
1433 if (!num_processors
)
1437 i
= setup_max_cpus
?: 1;
1438 if (setup_possible_cpus
== -1) {
1439 possible
= num_processors
;
1440 #ifdef CONFIG_HOTPLUG_CPU
1442 possible
+= disabled_cpus
;
1448 possible
= setup_possible_cpus
;
1450 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1452 /* nr_cpu_ids could be reduced via nr_cpus= */
1453 if (possible
> nr_cpu_ids
) {
1454 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1455 possible
, nr_cpu_ids
);
1456 possible
= nr_cpu_ids
;
1459 #ifdef CONFIG_HOTPLUG_CPU
1460 if (!setup_max_cpus
)
1463 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1464 possible
, setup_max_cpus
);
1468 nr_cpu_ids
= possible
;
1470 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1471 possible
, max_t(int, possible
- num_processors
, 0));
1473 reset_cpu_possible_mask();
1475 for (i
= 0; i
< possible
; i
++)
1476 set_cpu_possible(i
, true);
1479 #ifdef CONFIG_HOTPLUG_CPU
1481 /* Recompute SMT state for all CPUs on offline */
1482 static void recompute_smt_state(void)
1484 int max_threads
, cpu
;
1487 for_each_online_cpu (cpu
) {
1488 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1490 if (threads
> max_threads
)
1491 max_threads
= threads
;
1493 __max_smt_threads
= max_threads
;
1496 static void remove_siblinginfo(int cpu
)
1499 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1501 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1502 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1504 * last thread sibling in this cpu core going down
1506 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1507 cpu_data(sibling
).booted_cores
--;
1510 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1511 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1512 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1513 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1514 cpumask_clear(cpu_llc_shared_mask(cpu
));
1515 cpumask_clear(topology_sibling_cpumask(cpu
));
1516 cpumask_clear(topology_core_cpumask(cpu
));
1517 c
->phys_proc_id
= 0;
1519 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1520 recompute_smt_state();
1523 static void remove_cpu_from_maps(int cpu
)
1525 set_cpu_online(cpu
, false);
1526 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1527 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1528 /* was set by cpu_init() */
1529 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1530 numa_remove_cpu(cpu
);
1533 void cpu_disable_common(void)
1535 int cpu
= smp_processor_id();
1537 remove_siblinginfo(cpu
);
1539 /* It's now safe to remove this processor from the online map */
1541 remove_cpu_from_maps(cpu
);
1542 unlock_vector_lock();
1546 int native_cpu_disable(void)
1550 ret
= check_irq_vectors_for_cpu_disable();
1555 cpu_disable_common();
1560 int common_cpu_die(unsigned int cpu
)
1564 /* We don't do anything here: idle task is faking death itself. */
1566 /* They ack this in play_dead() by setting CPU_DEAD */
1567 if (cpu_wait_death(cpu
, 5)) {
1568 if (system_state
== SYSTEM_RUNNING
)
1569 pr_info("CPU %u is now offline\n", cpu
);
1571 pr_err("CPU %u didn't die...\n", cpu
);
1578 void native_cpu_die(unsigned int cpu
)
1580 common_cpu_die(cpu
);
1583 void play_dead_common(void)
1588 (void)cpu_report_death();
1591 * With physical CPU hotplug, we should halt the cpu
1593 local_irq_disable();
1596 static bool wakeup_cpu0(void)
1598 if (smp_processor_id() == 0 && enable_start_cpu0
)
1605 * We need to flush the caches before going to sleep, lest we have
1606 * dirty data in our caches when we come back up.
1608 static inline void mwait_play_dead(void)
1610 unsigned int eax
, ebx
, ecx
, edx
;
1611 unsigned int highest_cstate
= 0;
1612 unsigned int highest_subcstate
= 0;
1616 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1618 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1620 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1623 eax
= CPUID_MWAIT_LEAF
;
1625 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1628 * eax will be 0 if EDX enumeration is not valid.
1629 * Initialized below to cstate, sub_cstate value when EDX is valid.
1631 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1634 edx
>>= MWAIT_SUBSTATE_SIZE
;
1635 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1636 if (edx
& MWAIT_SUBSTATE_MASK
) {
1638 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1641 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1642 (highest_subcstate
- 1);
1646 * This should be a memory location in a cache line which is
1647 * unlikely to be touched by other processors. The actual
1648 * content is immaterial as it is not actually modified in any way.
1650 mwait_ptr
= ¤t_thread_info()->flags
;
1656 * The CLFLUSH is a workaround for erratum AAI65 for
1657 * the Xeon 7400 series. It's not clear it is actually
1658 * needed, but it should be harmless in either case.
1659 * The WBINVD is insufficient due to the spurious-wakeup
1660 * case where we return around the loop.
1665 __monitor(mwait_ptr
, 0, 0);
1669 * If NMI wants to wake up CPU0, start CPU0.
1676 void hlt_play_dead(void)
1678 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1684 * If NMI wants to wake up CPU0, start CPU0.
1691 void native_play_dead(void)
1694 tboot_shutdown(TB_SHUTDOWN_WFS
);
1697 native_wrmsrl(MSR_IA32_SPEC_CTRL
, 0);
1699 mwait_play_dead(); /* Only returns on failure */
1700 if (cpuidle_play_dead())
1704 native_wrmsrl(MSR_IA32_SPEC_CTRL
, FEATURE_ENABLE_IBRS
);
1707 #else /* ... !CONFIG_HOTPLUG_CPU */
1708 int native_cpu_disable(void)
1713 void native_cpu_die(unsigned int cpu
)
1715 /* We said "no" in __cpu_disable */
1719 void native_play_dead(void)