2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/trampoline.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 /* State of each CPU */
77 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
79 #ifdef CONFIG_HOTPLUG_CPU
81 * We need this for trampoline_base protection from concurrent accesses when
82 * off- and onlining cores wildly.
84 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
86 void cpu_hotplug_driver_lock(void)
88 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
91 void cpu_hotplug_driver_unlock(void)
93 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
96 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
97 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
100 /* Number of siblings per CPU package */
101 int smp_num_siblings
= 1;
102 EXPORT_SYMBOL(smp_num_siblings
);
104 /* Last level cache ID of each logical CPU */
105 DEFINE_PER_CPU(u16
, cpu_llc_id
) = BAD_APICID
;
107 /* representing HT siblings of each logical CPU */
108 DEFINE_PER_CPU(cpumask_var_t
, cpu_sibling_map
);
109 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
111 /* representing HT and core siblings of each logical CPU */
112 DEFINE_PER_CPU(cpumask_var_t
, cpu_core_map
);
113 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
115 DEFINE_PER_CPU(cpumask_var_t
, cpu_llc_shared_map
);
117 /* Per CPU bogomips and other parameters */
118 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
119 EXPORT_PER_CPU_SYMBOL(cpu_info
);
121 atomic_t init_deasserted
;
124 * Report back to the Boot Processor.
127 static void __cpuinit
smp_callin(void)
130 unsigned long timeout
;
133 * If waken up by an INIT in an 82489DX configuration
134 * we may get here before an INIT-deassert IPI reaches
135 * our local APIC. We have to wait for the IPI or we'll
136 * lock up on an APIC access.
138 if (apic
->wait_for_init_deassert
)
139 apic
->wait_for_init_deassert(&init_deasserted
);
142 * (This works even if the APIC is not enabled.)
144 phys_id
= read_apic_id();
145 cpuid
= smp_processor_id();
146 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
147 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
150 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
153 * STARTUP IPIs are fragile beasts as they might sometimes
154 * trigger some glue motherboard logic. Complete APIC bus
155 * silence for 1 second, this overestimates the time the
156 * boot CPU is spending to send the up to 2 STARTUP IPIs
157 * by a factor of two. This should be enough.
161 * Waiting 2s total for startup (udelay is not yet working)
163 timeout
= jiffies
+ 2*HZ
;
164 while (time_before(jiffies
, timeout
)) {
166 * Has the boot CPU finished it's STARTUP sequence?
168 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
173 if (!time_before(jiffies
, timeout
)) {
174 panic("%s: CPU%d started up but did not get a callout!\n",
179 * the boot CPU has finished the init stage and is spinning
180 * on callin_map until we finish. We are free to set up this
181 * CPU, first the APIC. (this is probably redundant on most
185 pr_debug("CALLIN, before setup_local_APIC().\n");
186 if (apic
->smp_callin_clear_local_apic
)
187 apic
->smp_callin_clear_local_apic();
189 end_local_APIC_setup();
192 * Need to setup vector mappings before we enable interrupts.
194 setup_vector_irq(smp_processor_id());
197 * Save our processor parameters. Note: this information
198 * is needed for clock calibration.
200 smp_store_cpu_info(cpuid
);
204 * Update loops_per_jiffy in cpu_data. Previous call to
205 * smp_store_cpu_info() stored a value that is close but not as
206 * accurate as the value just calculated.
209 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
210 pr_debug("Stack at about %p\n", &cpuid
);
213 * This must be done before setting cpu_online_mask
214 * or calling notify_cpu_starting.
216 set_cpu_sibling_map(raw_smp_processor_id());
219 notify_cpu_starting(cpuid
);
222 * Allow the master to continue.
224 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
228 * Activate a secondary processor.
230 notrace
static void __cpuinit
start_secondary(void *unused
)
233 * Don't put *anything* before cpu_init(), SMP booting is too
234 * fragile that we want to limit the things done here to the
235 * most necessary things.
238 x86_cpuinit
.early_percpu_clock_init();
243 /* switch away from the initial page table */
244 load_cr3(swapper_pg_dir
);
248 /* otherwise gcc will move up smp_processor_id before the cpu_init */
251 * Check TSC synchronization with the BP:
253 check_tsc_sync_target();
256 * We need to hold call_lock, so there is no inconsistency
257 * between the time smp_call_function() determines number of
258 * IPI recipients, and the time when the determination is made
259 * for which cpus receive the IPI. Holding this
260 * lock helps us to not include this cpu in a currently in progress
261 * smp_call_function().
263 * We need to hold vector_lock so there the set of online cpus
264 * does not change while we are assigning vectors to cpus. Holding
265 * this lock ensures we don't half assign or remove an irq from a cpu.
269 set_cpu_online(smp_processor_id(), true);
270 unlock_vector_lock();
272 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
273 x86_platform
.nmi_init();
275 /* enable local interrupts */
278 /* to prevent fake stack check failure in clock setup */
279 boot_init_stack_canary();
281 x86_cpuinit
.setup_percpu_clockev();
288 * The bootstrap kernel entry code has set these up. Save them for
292 void __cpuinit
smp_store_cpu_info(int id
)
294 struct cpuinfo_x86
*c
= &cpu_data(id
);
299 identify_secondary_cpu(c
);
302 static void __cpuinit
link_thread_siblings(int cpu1
, int cpu2
)
304 cpumask_set_cpu(cpu1
, cpu_sibling_mask(cpu2
));
305 cpumask_set_cpu(cpu2
, cpu_sibling_mask(cpu1
));
306 cpumask_set_cpu(cpu1
, cpu_core_mask(cpu2
));
307 cpumask_set_cpu(cpu2
, cpu_core_mask(cpu1
));
308 cpumask_set_cpu(cpu1
, cpu_llc_shared_mask(cpu2
));
309 cpumask_set_cpu(cpu2
, cpu_llc_shared_mask(cpu1
));
313 void __cpuinit
set_cpu_sibling_map(int cpu
)
316 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
318 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
320 if (smp_num_siblings
> 1) {
321 for_each_cpu(i
, cpu_sibling_setup_mask
) {
322 struct cpuinfo_x86
*o
= &cpu_data(i
);
324 if (cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
325 if (c
->phys_proc_id
== o
->phys_proc_id
&&
326 per_cpu(cpu_llc_id
, cpu
) == per_cpu(cpu_llc_id
, i
) &&
327 c
->compute_unit_id
== o
->compute_unit_id
)
328 link_thread_siblings(cpu
, i
);
329 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
330 c
->cpu_core_id
== o
->cpu_core_id
) {
331 link_thread_siblings(cpu
, i
);
335 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
338 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
340 if (__this_cpu_read(cpu_info
.x86_max_cores
) == 1) {
341 cpumask_copy(cpu_core_mask(cpu
), cpu_sibling_mask(cpu
));
346 for_each_cpu(i
, cpu_sibling_setup_mask
) {
347 if (per_cpu(cpu_llc_id
, cpu
) != BAD_APICID
&&
348 per_cpu(cpu_llc_id
, cpu
) == per_cpu(cpu_llc_id
, i
)) {
349 cpumask_set_cpu(i
, cpu_llc_shared_mask(cpu
));
350 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(i
));
352 if (c
->phys_proc_id
== cpu_data(i
).phys_proc_id
) {
353 cpumask_set_cpu(i
, cpu_core_mask(cpu
));
354 cpumask_set_cpu(cpu
, cpu_core_mask(i
));
356 * Does this new cpu bringup a new core?
358 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
360 * for each core in package, increment
361 * the booted_cores for this new cpu
363 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
366 * increment the core count for all
367 * the other cpus in this package
370 cpu_data(i
).booted_cores
++;
371 } else if (i
!= cpu
&& !c
->booted_cores
)
372 c
->booted_cores
= cpu_data(i
).booted_cores
;
377 /* maps the cpu to the sched domain representing multi-core */
378 const struct cpumask
*cpu_coregroup_mask(int cpu
)
380 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
382 * For perf, we return last level cache shared map.
383 * And for power savings, we return cpu_core_map
385 if ((sched_mc_power_savings
|| sched_smt_power_savings
) &&
386 !(cpu_has(c
, X86_FEATURE_AMD_DCM
)))
387 return cpu_core_mask(cpu
);
389 return cpu_llc_shared_mask(cpu
);
392 static void impress_friends(void)
395 unsigned long bogosum
= 0;
397 * Allow the user to impress friends.
399 pr_debug("Before bogomips.\n");
400 for_each_possible_cpu(cpu
)
401 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
402 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
404 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
407 (bogosum
/(5000/HZ
))%100);
409 pr_debug("Before bogocount - setting activated=1.\n");
412 void __inquire_remote_apic(int apicid
)
414 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
415 const char * const names
[] = { "ID", "VERSION", "SPIV" };
419 printk(KERN_INFO
"Inquiring remote APIC 0x%x...\n", apicid
);
421 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
422 printk(KERN_INFO
"... APIC 0x%x %s: ", apicid
, names
[i
]);
427 status
= safe_apic_wait_icr_idle();
430 "a previous APIC delivery may have failed\n");
432 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
437 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
438 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
441 case APIC_ICR_RR_VALID
:
442 status
= apic_read(APIC_RRR
);
443 printk(KERN_CONT
"%08x\n", status
);
446 printk(KERN_CONT
"failed\n");
452 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
453 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
454 * won't ... remember to clear down the APIC, etc later.
457 wakeup_secondary_cpu_via_nmi(int logical_apicid
, unsigned long start_eip
)
459 unsigned long send_status
, accept_status
= 0;
463 /* Boot on the stack */
464 /* Kick the second */
465 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, logical_apicid
);
467 pr_debug("Waiting for send to finish...\n");
468 send_status
= safe_apic_wait_icr_idle();
471 * Give the other CPU some time to accept the IPI.
474 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
475 maxlvt
= lapic_get_maxlvt();
476 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
477 apic_write(APIC_ESR
, 0);
478 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
480 pr_debug("NMI sent.\n");
483 printk(KERN_ERR
"APIC never delivered???\n");
485 printk(KERN_ERR
"APIC delivery error (%lx).\n", accept_status
);
487 return (send_status
| accept_status
);
491 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
493 unsigned long send_status
, accept_status
= 0;
494 int maxlvt
, num_starts
, j
;
496 maxlvt
= lapic_get_maxlvt();
499 * Be paranoid about clearing APIC errors.
501 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
502 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR
, 0);
507 pr_debug("Asserting INIT.\n");
510 * Turn INIT on target chip
515 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
518 pr_debug("Waiting for send to finish...\n");
519 send_status
= safe_apic_wait_icr_idle();
523 pr_debug("Deasserting INIT.\n");
527 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
529 pr_debug("Waiting for send to finish...\n");
530 send_status
= safe_apic_wait_icr_idle();
533 atomic_set(&init_deasserted
, 1);
536 * Should we send STARTUP IPIs ?
538 * Determine this based on the APIC version.
539 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
541 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
547 * Paravirt / VMI wants a startup IPI hook here to set up the
548 * target processor state.
550 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
554 * Run STARTUP IPI loop.
556 pr_debug("#startup loops: %d.\n", num_starts
);
558 for (j
= 1; j
<= num_starts
; j
++) {
559 pr_debug("Sending STARTUP #%d.\n", j
);
560 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
561 apic_write(APIC_ESR
, 0);
563 pr_debug("After apic_write.\n");
570 /* Boot on the stack */
571 /* Kick the second */
572 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
576 * Give the other CPU some time to accept the IPI.
580 pr_debug("Startup point 1.\n");
582 pr_debug("Waiting for send to finish...\n");
583 send_status
= safe_apic_wait_icr_idle();
586 * Give the other CPU some time to accept the IPI.
589 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
590 apic_write(APIC_ESR
, 0);
591 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
592 if (send_status
|| accept_status
)
595 pr_debug("After Startup.\n");
598 printk(KERN_ERR
"APIC never delivered???\n");
600 printk(KERN_ERR
"APIC delivery error (%lx).\n", accept_status
);
602 return (send_status
| accept_status
);
605 /* reduce the number of lines printed when booting a large cpu count system */
606 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
608 static int current_node
= -1;
609 int node
= early_cpu_to_node(cpu
);
611 if (system_state
== SYSTEM_BOOTING
) {
612 if (node
!= current_node
) {
613 if (current_node
> (-1))
616 pr_info("Booting Node %3d, Processors ", node
);
618 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " Ok.\n" : "");
621 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
626 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
627 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
628 * Returns zero if CPU booted OK, else error code from
629 * ->wakeup_secondary_cpu.
631 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
633 unsigned long boot_error
= 0;
634 unsigned long start_ip
;
637 alternatives_smp_switch(1);
639 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
640 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
641 per_cpu(current_task
, cpu
) = idle
;
644 /* Stack for startup_32 can be just as for start_secondary onwards */
647 clear_tsk_thread_flag(idle
, TIF_FORK
);
648 initial_gs
= per_cpu_offset(cpu
);
649 per_cpu(kernel_stack
, cpu
) =
650 (unsigned long)task_stack_page(idle
) -
651 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
653 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
654 initial_code
= (unsigned long)start_secondary
;
655 stack_start
= idle
->thread
.sp
;
657 /* start_ip had better be page-aligned! */
658 start_ip
= trampoline_address();
660 /* So we see what's up */
661 announce_cpu(cpu
, apicid
);
664 * This grunge runs the startup process for
665 * the targeted processor.
668 atomic_set(&init_deasserted
, 0);
670 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
672 pr_debug("Setting warm reset code and vector.\n");
674 smpboot_setup_warm_reset_vector(start_ip
);
676 * Be paranoid about clearing APIC errors.
678 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
679 apic_write(APIC_ESR
, 0);
685 * Kick the secondary CPU. Use the method in the APIC driver
686 * if it's defined - or use an INIT boot APIC message otherwise:
688 if (apic
->wakeup_secondary_cpu
)
689 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
691 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
695 * allow APs to start initializing.
697 pr_debug("Before Callout %d.\n", cpu
);
698 cpumask_set_cpu(cpu
, cpu_callout_mask
);
699 pr_debug("After Callout %d.\n", cpu
);
702 * Wait 5s total for a response
704 for (timeout
= 0; timeout
< 50000; timeout
++) {
705 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
706 break; /* It has booted */
709 * Allow other tasks to run while we wait for the
710 * AP to come online. This also gives a chance
711 * for the MTRR work(triggered by the AP coming online)
712 * to be completed in the stop machine context.
717 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
718 print_cpu_msr(&cpu_data(cpu
));
719 pr_debug("CPU%d: has booted.\n", cpu
);
722 if (*(volatile u32
*)TRAMPOLINE_SYM(trampoline_status
)
724 /* trampoline started but...? */
725 pr_err("CPU%d: Stuck ??\n", cpu
);
727 /* trampoline code not run */
728 pr_err("CPU%d: Not responding.\n", cpu
);
729 if (apic
->inquire_remote_apic
)
730 apic
->inquire_remote_apic(apicid
);
735 /* Try to put things back the way they were before ... */
736 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
738 /* was set by do_boot_cpu() */
739 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
741 /* was set by cpu_init() */
742 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
744 set_cpu_present(cpu
, false);
745 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
748 /* mark "stuck" area as not stuck */
749 *(volatile u32
*)TRAMPOLINE_SYM(trampoline_status
) = 0;
751 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
753 * Cleanup possible dangling ends...
755 smpboot_restore_warm_reset_vector();
760 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
762 int apicid
= apic
->cpu_present_to_apicid(cpu
);
766 WARN_ON(irqs_disabled());
768 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
770 if (apicid
== BAD_APICID
|| apicid
== boot_cpu_physical_apicid
||
771 !physid_isset(apicid
, phys_cpu_present_map
) ||
772 !apic
->apic_id_valid(apicid
)) {
773 printk(KERN_ERR
"%s: bad cpu %d\n", __func__
, cpu
);
778 * Already booted CPU?
780 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
781 pr_debug("do_boot_cpu %d Already started\n", cpu
);
786 * Save current MTRR state in case it was changed since early boot
787 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
791 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
793 err
= do_boot_cpu(apicid
, cpu
, tidle
);
795 pr_debug("do_boot_cpu failed %d\n", err
);
800 * Check TSC synchronization with the AP (keep irqs disabled
803 local_irq_save(flags
);
804 check_tsc_sync_source(cpu
);
805 local_irq_restore(flags
);
807 while (!cpu_online(cpu
)) {
809 touch_nmi_watchdog();
816 * arch_disable_smp_support() - disables SMP support for x86 at runtime
818 void arch_disable_smp_support(void)
820 disable_ioapic_support();
824 * Fall back to non SMP mode after errors.
826 * RED-PEN audit/test this more. I bet there is more state messed up here.
828 static __init
void disable_smp(void)
830 init_cpu_present(cpumask_of(0));
831 init_cpu_possible(cpumask_of(0));
832 smpboot_clear_io_apic_irqs();
834 if (smp_found_config
)
835 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
837 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
838 cpumask_set_cpu(0, cpu_sibling_mask(0));
839 cpumask_set_cpu(0, cpu_core_mask(0));
843 * Various sanity checks.
845 static int __init
smp_sanity_check(unsigned max_cpus
)
849 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
850 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
855 "More than 8 CPUs detected - skipping them.\n"
856 "Use CONFIG_X86_BIGSMP.\n");
859 for_each_present_cpu(cpu
) {
861 set_cpu_present(cpu
, false);
866 for_each_possible_cpu(cpu
) {
868 set_cpu_possible(cpu
, false);
876 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
878 "weird, boot CPU (#%d) not listed by the BIOS.\n",
879 hard_smp_processor_id());
881 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
885 * If we couldn't find an SMP configuration at boot time,
886 * get out of here now!
888 if (!smp_found_config
&& !acpi_lapic
) {
890 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
892 if (APIC_init_uniprocessor())
893 printk(KERN_NOTICE
"Local APIC not detected."
894 " Using dummy APIC emulation.\n");
899 * Should not be necessary because the MP table should list the boot
900 * CPU too, but we do it for the sake of robustness anyway.
902 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
904 "weird, boot CPU (#%d) not listed by the BIOS.\n",
905 boot_cpu_physical_apicid
);
906 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
911 * If we couldn't find a local APIC, then get out of here now!
913 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
916 pr_err("BIOS bug, local APIC #%d not detected!...\n",
917 boot_cpu_physical_apicid
);
918 pr_err("... forcing use of dummy APIC emulation."
919 "(tell your hw vendor)\n");
921 smpboot_clear_io_apic();
922 disable_ioapic_support();
929 * If SMP should be disabled, then really disable it!
932 printk(KERN_INFO
"SMP mode deactivated.\n");
933 smpboot_clear_io_apic();
937 bsp_end_local_APIC_setup();
944 static void __init
smp_cpu_index_default(void)
947 struct cpuinfo_x86
*c
;
949 for_each_possible_cpu(i
) {
951 /* mark all to hotplug */
952 c
->cpu_index
= nr_cpu_ids
;
957 * Prepare for SMP bootup. The MP table or ACPI has been read
958 * earlier. Just do some sanity checking here and enable APIC mode.
960 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
965 smp_cpu_index_default();
968 * Setup boot CPU information
970 smp_store_cpu_info(0); /* Final full version of the data */
971 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
974 current_thread_info()->cpu
= 0; /* needed? */
975 for_each_possible_cpu(i
) {
976 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
977 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
978 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
980 set_cpu_sibling_map(0);
983 if (smp_sanity_check(max_cpus
) < 0) {
984 printk(KERN_INFO
"SMP disabled\n");
989 default_setup_apic_routing();
992 if (read_apic_id() != boot_cpu_physical_apicid
) {
993 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
994 read_apic_id(), boot_cpu_physical_apicid
);
995 /* Or can we switch back to PIC here? */
1002 * Switch from PIC to APIC mode.
1007 * Enable IO APIC before setting up error vector
1009 if (!skip_ioapic_setup
&& nr_ioapics
)
1012 bsp_end_local_APIC_setup();
1014 if (apic
->setup_portio_remap
)
1015 apic
->setup_portio_remap();
1017 smpboot_setup_io_apic();
1019 * Set up local APIC timer on boot CPU.
1022 printk(KERN_INFO
"CPU%d: ", 0);
1023 print_cpu_info(&cpu_data(0));
1024 x86_init
.timers
.setup_percpu_clockev();
1029 set_mtrr_aps_delayed_init();
1034 void arch_disable_nonboot_cpus_begin(void)
1037 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1038 * In the suspend path, we will be back in the SMP mode shortly anyways.
1040 skip_smp_alternatives
= true;
1043 void arch_disable_nonboot_cpus_end(void)
1045 skip_smp_alternatives
= false;
1048 void arch_enable_nonboot_cpus_begin(void)
1050 set_mtrr_aps_delayed_init();
1053 void arch_enable_nonboot_cpus_end(void)
1059 * Early setup to make printk work.
1061 void __init
native_smp_prepare_boot_cpu(void)
1063 int me
= smp_processor_id();
1064 switch_to_new_gdt(me
);
1065 /* already set me in cpu_online_mask in boot_cpu_init() */
1066 cpumask_set_cpu(me
, cpu_callout_mask
);
1067 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1070 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1072 pr_debug("Boot done.\n");
1076 #ifdef CONFIG_X86_IO_APIC
1077 setup_ioapic_dest();
1082 static int __initdata setup_possible_cpus
= -1;
1083 static int __init
_setup_possible_cpus(char *str
)
1085 get_option(&str
, &setup_possible_cpus
);
1088 early_param("possible_cpus", _setup_possible_cpus
);
1092 * cpu_possible_mask should be static, it cannot change as cpu's
1093 * are onlined, or offlined. The reason is per-cpu data-structures
1094 * are allocated by some modules at init time, and dont expect to
1095 * do this dynamically on cpu arrival/departure.
1096 * cpu_present_mask on the other hand can change dynamically.
1097 * In case when cpu_hotplug is not compiled, then we resort to current
1098 * behaviour, which is cpu_possible == cpu_present.
1101 * Three ways to find out the number of additional hotplug CPUs:
1102 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1103 * - The user can overwrite it with possible_cpus=NUM
1104 * - Otherwise don't reserve additional CPUs.
1105 * We do this because additional CPUs waste a lot of memory.
1108 __init
void prefill_possible_map(void)
1112 /* no processor from mptable or madt */
1113 if (!num_processors
)
1116 i
= setup_max_cpus
?: 1;
1117 if (setup_possible_cpus
== -1) {
1118 possible
= num_processors
;
1119 #ifdef CONFIG_HOTPLUG_CPU
1121 possible
+= disabled_cpus
;
1127 possible
= setup_possible_cpus
;
1129 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1131 /* nr_cpu_ids could be reduced via nr_cpus= */
1132 if (possible
> nr_cpu_ids
) {
1134 "%d Processors exceeds NR_CPUS limit of %d\n",
1135 possible
, nr_cpu_ids
);
1136 possible
= nr_cpu_ids
;
1139 #ifdef CONFIG_HOTPLUG_CPU
1140 if (!setup_max_cpus
)
1144 "%d Processors exceeds max_cpus limit of %u\n",
1145 possible
, setup_max_cpus
);
1149 printk(KERN_INFO
"SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1150 possible
, max_t(int, possible
- num_processors
, 0));
1152 for (i
= 0; i
< possible
; i
++)
1153 set_cpu_possible(i
, true);
1154 for (; i
< NR_CPUS
; i
++)
1155 set_cpu_possible(i
, false);
1157 nr_cpu_ids
= possible
;
1160 #ifdef CONFIG_HOTPLUG_CPU
1162 static void remove_siblinginfo(int cpu
)
1165 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1167 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1168 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1170 * last thread sibling in this cpu core going down
1172 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1173 cpu_data(sibling
).booted_cores
--;
1176 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1177 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1178 cpumask_clear(cpu_sibling_mask(cpu
));
1179 cpumask_clear(cpu_core_mask(cpu
));
1180 c
->phys_proc_id
= 0;
1182 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1185 static void __ref
remove_cpu_from_maps(int cpu
)
1187 set_cpu_online(cpu
, false);
1188 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1189 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1190 /* was set by cpu_init() */
1191 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1192 numa_remove_cpu(cpu
);
1195 void cpu_disable_common(void)
1197 int cpu
= smp_processor_id();
1199 remove_siblinginfo(cpu
);
1201 /* It's now safe to remove this processor from the online map */
1203 remove_cpu_from_maps(cpu
);
1204 unlock_vector_lock();
1208 int native_cpu_disable(void)
1210 int cpu
= smp_processor_id();
1213 * Perhaps use cpufreq to drop frequency, but that could go
1214 * into generic code.
1216 * We won't take down the boot processor on i386 due to some
1217 * interrupts only being able to be serviced by the BSP.
1218 * Especially so if we're not using an IOAPIC -zwane
1225 cpu_disable_common();
1229 void native_cpu_die(unsigned int cpu
)
1231 /* We don't do anything here: idle task is faking death itself. */
1234 for (i
= 0; i
< 10; i
++) {
1235 /* They ack this in play_dead by setting CPU_DEAD */
1236 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1237 if (system_state
== SYSTEM_RUNNING
)
1238 pr_info("CPU %u is now offline\n", cpu
);
1240 if (1 == num_online_cpus())
1241 alternatives_smp_switch(0);
1246 pr_err("CPU %u didn't die...\n", cpu
);
1249 void play_dead_common(void)
1252 reset_lazy_tlbstate();
1253 amd_e400_remove_cpu(raw_smp_processor_id());
1257 __this_cpu_write(cpu_state
, CPU_DEAD
);
1260 * With physical CPU hotplug, we should halt the cpu
1262 local_irq_disable();
1266 * We need to flush the caches before going to sleep, lest we have
1267 * dirty data in our caches when we come back up.
1269 static inline void mwait_play_dead(void)
1271 unsigned int eax
, ebx
, ecx
, edx
;
1272 unsigned int highest_cstate
= 0;
1273 unsigned int highest_subcstate
= 0;
1276 struct cpuinfo_x86
*c
= __this_cpu_ptr(&cpu_info
);
1278 if (!(this_cpu_has(X86_FEATURE_MWAIT
) && mwait_usable(c
)))
1280 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1282 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1285 eax
= CPUID_MWAIT_LEAF
;
1287 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1290 * eax will be 0 if EDX enumeration is not valid.
1291 * Initialized below to cstate, sub_cstate value when EDX is valid.
1293 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1296 edx
>>= MWAIT_SUBSTATE_SIZE
;
1297 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1298 if (edx
& MWAIT_SUBSTATE_MASK
) {
1300 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1303 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1304 (highest_subcstate
- 1);
1308 * This should be a memory location in a cache line which is
1309 * unlikely to be touched by other processors. The actual
1310 * content is immaterial as it is not actually modified in any way.
1312 mwait_ptr
= ¤t_thread_info()->flags
;
1318 * The CLFLUSH is a workaround for erratum AAI65 for
1319 * the Xeon 7400 series. It's not clear it is actually
1320 * needed, but it should be harmless in either case.
1321 * The WBINVD is insufficient due to the spurious-wakeup
1322 * case where we return around the loop.
1325 __monitor(mwait_ptr
, 0, 0);
1331 static inline void hlt_play_dead(void)
1333 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1341 void native_play_dead(void)
1344 tboot_shutdown(TB_SHUTDOWN_WFS
);
1346 mwait_play_dead(); /* Only returns on failure */
1347 if (cpuidle_play_dead())
1351 #else /* ... !CONFIG_HOTPLUG_CPU */
1352 int native_cpu_disable(void)
1357 void native_cpu_die(unsigned int cpu
)
1359 /* We said "no" in __cpu_disable */
1363 void native_play_dead(void)