2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
80 #include <asm/spec-ctrl.h>
81 #include <asm/microcode.h>
82 #include <asm/spec-ctrl.h>
84 /* Number of siblings per CPU package */
85 int smp_num_siblings
= 1;
86 EXPORT_SYMBOL(smp_num_siblings
);
88 /* Last level cache ID of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
101 /* Per CPU bogomips and other parameters */
102 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
103 EXPORT_PER_CPU_SYMBOL(cpu_info
);
105 /* Logical package management. We might want to allocate that dynamically */
106 static int *physical_to_logical_pkg __read_mostly
;
107 static unsigned long *physical_package_map __read_mostly
;;
108 static unsigned int max_physical_pkg_id __read_mostly
;
109 unsigned int __max_logical_packages __read_mostly
;
110 EXPORT_SYMBOL(__max_logical_packages
);
111 static unsigned int logical_packages __read_mostly
;
113 /* Maximum number of SMT threads on any online core */
114 int __max_smt_threads __read_mostly
;
116 /* Flag to indicate if a complete sched domain rebuild is required */
117 bool x86_topology_update
;
119 int arch_update_cpu_topology(void)
121 int retval
= x86_topology_update
;
123 x86_topology_update
= false;
127 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
131 spin_lock_irqsave(&rtc_lock
, flags
);
132 CMOS_WRITE(0xa, 0xf);
133 spin_unlock_irqrestore(&rtc_lock
, flags
);
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
140 static inline void smpboot_restore_warm_reset_vector(void)
145 * Paranoid: Set warm reset code and vector here back
148 spin_lock_irqsave(&rtc_lock
, flags
);
150 spin_unlock_irqrestore(&rtc_lock
, flags
);
152 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
156 * Report back to the Boot Processor during boot time or to the caller processor
159 static void smp_callin(void)
164 * If waken up by an INIT in an 82489DX configuration
165 * cpu_callout_mask guarantees we don't get here before
166 * an INIT_deassert IPI reaches our local APIC, so it is
167 * now safe to touch our local APIC.
169 cpuid
= smp_processor_id();
172 * (This works even if the APIC is not enabled.)
174 phys_id
= read_apic_id();
177 * the boot CPU has finished the init stage and is spinning
178 * on callin_map until we finish. We are free to set up this
179 * CPU, first the APIC. (this is probably redundant on most
185 * Save our processor parameters. Note: this information
186 * is needed for clock calibration.
188 smp_store_cpu_info(cpuid
);
191 * The topology information must be up to date before
192 * calibrate_delay() and notify_cpu_starting().
194 set_cpu_sibling_map(raw_smp_processor_id());
198 * Update loops_per_jiffy in cpu_data. Previous call to
199 * smp_store_cpu_info() stored a value that is close but not as
200 * accurate as the value just calculated.
203 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
204 pr_debug("Stack at about %p\n", &cpuid
);
208 notify_cpu_starting(cpuid
);
211 * Allow the master to continue.
213 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
216 static int cpu0_logical_apicid
;
217 static int enable_start_cpu0
;
219 * Activate a secondary processor.
221 static void notrace
start_secondary(void *unused
)
224 * Don't put *anything* except direct CPU state initialization
225 * before cpu_init(), SMP booting is too fragile that we want to
226 * limit the things done here to the most necessary things.
228 if (IS_ENABLED(CONFIG_X86_64
) && boot_cpu_has(X86_FEATURE_PCID
))
229 __write_cr4(__read_cr4() | X86_CR4_PCIDE
);
231 x86_cpuinit
.early_percpu_clock_init();
235 enable_start_cpu0
= 0;
238 /* switch away from the initial page table */
239 load_cr3(swapper_pg_dir
);
243 /* otherwise gcc will move up smp_processor_id before the cpu_init */
246 * Check TSC synchronization with the BP:
248 check_tsc_sync_target();
250 speculative_store_bypass_ht_init();
253 * Lock vector_lock and initialize the vectors on this cpu
254 * before setting the cpu online. We must set it online with
255 * vector_lock held to prevent a concurrent setup/teardown
256 * from seeing a half valid vector space.
259 setup_vector_irq(smp_processor_id());
260 set_cpu_online(smp_processor_id(), true);
261 unlock_vector_lock();
262 cpu_set_state_online(smp_processor_id());
263 x86_platform
.nmi_init();
265 /* enable local interrupts */
268 /* to prevent fake stack check failure in clock setup */
269 boot_init_stack_canary();
271 x86_cpuinit
.setup_percpu_clockev();
274 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
278 * topology_update_package_map - Update the physical to logical package map
279 * @pkg: The physical package id as retrieved via CPUID
280 * @cpu: The cpu for which this is updated
282 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
286 /* Called from early boot ? */
287 if (!physical_package_map
)
290 if (pkg
>= max_physical_pkg_id
)
293 /* Set the logical package id */
294 if (test_and_set_bit(pkg
, physical_package_map
))
297 if (logical_packages
>= __max_logical_packages
) {
298 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
299 logical_packages
, cpu
, __max_logical_packages
);
303 new = logical_packages
++;
305 pr_info("CPU %u Converting physical %u to logical package %u\n",
308 physical_to_logical_pkg
[pkg
] = new;
311 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
316 * topology_phys_to_logical_pkg - Map a physical package id to a logical
318 * Returns logical package id or -1 if not found
320 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
322 if (phys_pkg
>= max_physical_pkg_id
)
324 return physical_to_logical_pkg
[phys_pkg
];
326 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
328 static void __init
smp_init_package_map(struct cpuinfo_x86
*c
, unsigned int cpu
)
334 * Today neither Intel nor AMD support heterogenous systems. That
335 * might change in the future....
337 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
338 * computation, this won't actually work since some Intel BIOSes
339 * report inconsistent HT data when they disable HT.
341 * In particular, they reduce the APIC-IDs to only include the cores,
342 * but leave the CPUID topology to say there are (2) siblings.
343 * This means we don't know how many threads there will be until
344 * after the APIC enumeration.
346 * By not including this we'll sometimes over-estimate the number of
347 * logical packages by the amount of !present siblings, but this is
348 * still better than MAX_LOCAL_APIC.
350 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
351 * on the command line leading to a similar issue as the HT disable
352 * problem because the hyperthreads are usually enumerated after the
355 ncpus
= boot_cpu_data
.x86_max_cores
;
357 pr_warn("x86_max_cores == zero !?!?");
361 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
362 logical_packages
= 0;
365 * Possibly larger than what we need as the number of apic ids per
366 * package can be smaller than the actual used apic ids.
368 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
369 size
= max_physical_pkg_id
* sizeof(unsigned int);
370 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
371 memset(physical_to_logical_pkg
, 0xff, size
);
372 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
373 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
375 pr_info("Max logical packages: %u\n", __max_logical_packages
);
377 topology_update_package_map(c
->phys_proc_id
, cpu
);
380 void __init
smp_store_boot_cpu_info(void)
382 int id
= 0; /* CPU 0 */
383 struct cpuinfo_x86
*c
= &cpu_data(id
);
387 smp_init_package_map(c
, id
);
391 * The bootstrap kernel entry code has set these up. Save them for
394 void smp_store_cpu_info(int id
)
396 struct cpuinfo_x86
*c
= &cpu_data(id
);
401 * During boot time, CPU0 has this setup already. Save the info when
402 * bringing up AP or offlined CPU0.
404 identify_secondary_cpu(c
);
408 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
410 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
412 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
416 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
418 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
420 return !WARN_ONCE(!topology_same_node(c
, o
),
421 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
422 "[node: %d != %d]. Ignoring dependency.\n",
423 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
426 #define link_mask(mfunc, c1, c2) \
428 cpumask_set_cpu((c1), mfunc(c2)); \
429 cpumask_set_cpu((c2), mfunc(c1)); \
432 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
434 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
435 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
437 if (c
->phys_proc_id
== o
->phys_proc_id
&&
438 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
439 if (c
->cpu_core_id
== o
->cpu_core_id
)
440 return topology_sane(c
, o
, "smt");
442 if ((c
->cu_id
!= 0xff) &&
443 (o
->cu_id
!= 0xff) &&
444 (c
->cu_id
== o
->cu_id
))
445 return topology_sane(c
, o
, "smt");
448 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
449 c
->cpu_core_id
== o
->cpu_core_id
) {
450 return topology_sane(c
, o
, "smt");
456 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
458 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
460 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
461 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
462 return topology_sane(c
, o
, "llc");
468 * Unlike the other levels, we do not enforce keeping a
469 * multicore group inside a NUMA node. If this happens, we will
470 * discard the MC level of the topology later.
472 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
474 if (c
->phys_proc_id
== o
->phys_proc_id
)
479 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
480 static inline int x86_sched_itmt_flags(void)
482 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
485 #ifdef CONFIG_SCHED_MC
486 static int x86_core_flags(void)
488 return cpu_core_flags() | x86_sched_itmt_flags();
491 #ifdef CONFIG_SCHED_SMT
492 static int x86_smt_flags(void)
494 return cpu_smt_flags() | x86_sched_itmt_flags();
499 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
500 #ifdef CONFIG_SCHED_SMT
501 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
503 #ifdef CONFIG_SCHED_MC
504 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
509 static struct sched_domain_topology_level x86_topology
[] = {
510 #ifdef CONFIG_SCHED_SMT
511 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
513 #ifdef CONFIG_SCHED_MC
514 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
516 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
521 * Set if a package/die has multiple NUMA nodes inside.
522 * AMD Magny-Cours and Intel Cluster-on-Die have this.
524 static bool x86_has_numa_in_package
;
526 void set_cpu_sibling_map(int cpu
)
528 bool has_smt
= smp_num_siblings
> 1;
529 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
530 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
531 struct cpuinfo_x86
*o
;
534 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
537 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
538 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
539 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
544 for_each_cpu(i
, cpu_sibling_setup_mask
) {
547 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
548 link_mask(topology_sibling_cpumask
, cpu
, i
);
550 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
551 link_mask(cpu_llc_shared_mask
, cpu
, i
);
556 * This needs a separate iteration over the cpus because we rely on all
557 * topology_sibling_cpumask links to be set-up.
559 for_each_cpu(i
, cpu_sibling_setup_mask
) {
562 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
563 link_mask(topology_core_cpumask
, cpu
, i
);
566 * Does this new cpu bringup a new core?
569 topology_sibling_cpumask(cpu
)) == 1) {
571 * for each core in package, increment
572 * the booted_cores for this new cpu
575 topology_sibling_cpumask(i
)) == i
)
578 * increment the core count for all
579 * the other cpus in this package
582 cpu_data(i
).booted_cores
++;
583 } else if (i
!= cpu
&& !c
->booted_cores
)
584 c
->booted_cores
= cpu_data(i
).booted_cores
;
586 if (match_die(c
, o
) && !topology_same_node(c
, o
))
587 x86_has_numa_in_package
= true;
590 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
591 if (threads
> __max_smt_threads
)
592 __max_smt_threads
= threads
;
595 /* maps the cpu to the sched domain representing multi-core */
596 const struct cpumask
*cpu_coregroup_mask(int cpu
)
598 return cpu_llc_shared_mask(cpu
);
601 static void impress_friends(void)
604 unsigned long bogosum
= 0;
606 * Allow the user to impress friends.
608 pr_debug("Before bogomips\n");
609 for_each_possible_cpu(cpu
)
610 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
611 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
612 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
615 (bogosum
/(5000/HZ
))%100);
617 pr_debug("Before bogocount - setting activated=1\n");
620 void __inquire_remote_apic(int apicid
)
622 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
623 const char * const names
[] = { "ID", "VERSION", "SPIV" };
627 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
629 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
630 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
635 status
= safe_apic_wait_icr_idle();
637 pr_cont("a previous APIC delivery may have failed\n");
639 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
644 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
645 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
648 case APIC_ICR_RR_VALID
:
649 status
= apic_read(APIC_RRR
);
650 pr_cont("%08x\n", status
);
659 * The Multiprocessor Specification 1.4 (1997) example code suggests
660 * that there should be a 10ms delay between the BSP asserting INIT
661 * and de-asserting INIT, when starting a remote processor.
662 * But that slows boot and resume on modern processors, which include
663 * many cores and don't require that delay.
665 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
666 * Modern processor families are quirked to remove the delay entirely.
668 #define UDELAY_10MS_DEFAULT 10000
670 static unsigned int init_udelay
= UINT_MAX
;
672 static int __init
cpu_init_udelay(char *str
)
674 get_option(&str
, &init_udelay
);
678 early_param("cpu_init_udelay", cpu_init_udelay
);
680 static void __init
smp_quirk_init_udelay(void)
682 /* if cmdline changed it from default, leave it alone */
683 if (init_udelay
!= UINT_MAX
)
686 /* if modern processor, use no delay */
687 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
688 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
692 /* else, use legacy delay */
693 init_udelay
= UDELAY_10MS_DEFAULT
;
697 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
698 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
699 * won't ... remember to clear down the APIC, etc later.
702 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
704 unsigned long send_status
, accept_status
= 0;
708 /* Boot on the stack */
709 /* Kick the second */
710 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
712 pr_debug("Waiting for send to finish...\n");
713 send_status
= safe_apic_wait_icr_idle();
716 * Give the other CPU some time to accept the IPI.
719 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
720 maxlvt
= lapic_get_maxlvt();
721 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
722 apic_write(APIC_ESR
, 0);
723 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
725 pr_debug("NMI sent\n");
728 pr_err("APIC never delivered???\n");
730 pr_err("APIC delivery error (%lx)\n", accept_status
);
732 return (send_status
| accept_status
);
736 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
738 unsigned long send_status
= 0, accept_status
= 0;
739 int maxlvt
, num_starts
, j
;
741 maxlvt
= lapic_get_maxlvt();
744 * Be paranoid about clearing APIC errors.
746 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
747 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
748 apic_write(APIC_ESR
, 0);
752 pr_debug("Asserting INIT\n");
755 * Turn INIT on target chip
760 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
763 pr_debug("Waiting for send to finish...\n");
764 send_status
= safe_apic_wait_icr_idle();
768 pr_debug("Deasserting INIT\n");
772 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
774 pr_debug("Waiting for send to finish...\n");
775 send_status
= safe_apic_wait_icr_idle();
780 * Should we send STARTUP IPIs ?
782 * Determine this based on the APIC version.
783 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
785 if (APIC_INTEGRATED(boot_cpu_apic_version
))
791 * Run STARTUP IPI loop.
793 pr_debug("#startup loops: %d\n", num_starts
);
795 for (j
= 1; j
<= num_starts
; j
++) {
796 pr_debug("Sending STARTUP #%d\n", j
);
797 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
798 apic_write(APIC_ESR
, 0);
800 pr_debug("After apic_write\n");
807 /* Boot on the stack */
808 /* Kick the second */
809 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
813 * Give the other CPU some time to accept the IPI.
815 if (init_udelay
== 0)
820 pr_debug("Startup point 1\n");
822 pr_debug("Waiting for send to finish...\n");
823 send_status
= safe_apic_wait_icr_idle();
826 * Give the other CPU some time to accept the IPI.
828 if (init_udelay
== 0)
833 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
834 apic_write(APIC_ESR
, 0);
835 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
836 if (send_status
|| accept_status
)
839 pr_debug("After Startup\n");
842 pr_err("APIC never delivered???\n");
844 pr_err("APIC delivery error (%lx)\n", accept_status
);
846 return (send_status
| accept_status
);
849 /* reduce the number of lines printed when booting a large cpu count system */
850 static void announce_cpu(int cpu
, int apicid
)
852 static int current_node
= -1;
853 int node
= early_cpu_to_node(cpu
);
854 static int width
, node_width
;
857 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
860 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
863 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
865 if (system_state
< SYSTEM_RUNNING
) {
866 if (node
!= current_node
) {
867 if (current_node
> (-1))
871 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
872 node_width
- num_digits(node
), " ", node
);
875 /* Add padding for the BSP */
877 pr_cont("%*s", width
+ 1, " ");
879 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
882 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
886 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
890 cpu
= smp_processor_id();
891 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
898 * Wake up AP by INIT, INIT, STARTUP sequence.
900 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
901 * boot-strap code which is not a desired behavior for waking up BSP. To
902 * void the boot-strap code, wake up CPU0 by NMI instead.
904 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
905 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
906 * We'll change this code in the future to wake up hard offlined CPU0 if
907 * real platform and request are available.
910 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
911 int *cpu0_nmi_registered
)
919 * Wake up AP by INIT, INIT, STARTUP sequence.
922 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
927 * Wake up BSP by nmi.
929 * Register a NMI handler to help wake up CPU0.
931 boot_error
= register_nmi_handler(NMI_LOCAL
,
932 wakeup_cpu0_nmi
, 0, "wake_cpu0");
935 enable_start_cpu0
= 1;
936 *cpu0_nmi_registered
= 1;
937 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
938 id
= cpu0_logical_apicid
;
941 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
950 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
952 /* Just in case we booted with a single CPU. */
953 alternatives_enable_smp();
955 per_cpu(current_task
, cpu
) = idle
;
958 /* Stack for startup_32 can be just as for start_secondary onwards */
960 per_cpu(cpu_current_top_of_stack
, cpu
) = task_top_of_stack(idle
);
962 initial_gs
= per_cpu_offset(cpu
);
967 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
968 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
969 * Returns zero if CPU booted OK, else error code from
970 * ->wakeup_secondary_cpu.
972 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
973 int *cpu0_nmi_registered
)
975 volatile u32
*trampoline_status
=
976 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
977 /* start_ip had better be page-aligned! */
978 unsigned long start_ip
= real_mode_header
->trampoline_start
;
980 unsigned long boot_error
= 0;
981 unsigned long timeout
;
983 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
984 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
985 initial_code
= (unsigned long)start_secondary
;
986 initial_stack
= idle
->thread
.sp
;
988 /* Enable the espfix hack for this CPU */
991 /* So we see what's up */
992 announce_cpu(cpu
, apicid
);
995 * This grunge runs the startup process for
996 * the targeted processor.
999 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1001 pr_debug("Setting warm reset code and vector.\n");
1003 smpboot_setup_warm_reset_vector(start_ip
);
1005 * Be paranoid about clearing APIC errors.
1007 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1008 apic_write(APIC_ESR
, 0);
1009 apic_read(APIC_ESR
);
1014 * AP might wait on cpu_callout_mask in cpu_init() with
1015 * cpu_initialized_mask set if previous attempt to online
1016 * it timed-out. Clear cpu_initialized_mask so that after
1017 * INIT/SIPI it could start with a clean state.
1019 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1023 * Wake up a CPU in difference cases:
1024 * - Use the method in the APIC driver if it's defined
1026 * - Use an INIT boot APIC message for APs or NMI for BSP.
1028 if (apic
->wakeup_secondary_cpu
)
1029 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1031 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1032 cpu0_nmi_registered
);
1036 * Wait 10s total for first sign of life from AP
1039 timeout
= jiffies
+ 10*HZ
;
1040 while (time_before(jiffies
, timeout
)) {
1041 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1043 * Tell AP to proceed with initialization
1045 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1055 * Wait till AP completes initial initialization
1057 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1059 * Allow other tasks to run while we wait for the
1060 * AP to come online. This also gives a chance
1061 * for the MTRR work(triggered by the AP coming online)
1062 * to be completed in the stop machine context.
1068 /* mark "stuck" area as not stuck */
1069 *trampoline_status
= 0;
1071 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1073 * Cleanup possible dangling ends...
1075 smpboot_restore_warm_reset_vector();
1081 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1083 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1084 int cpu0_nmi_registered
= 0;
1085 unsigned long flags
;
1088 WARN_ON(irqs_disabled());
1090 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1092 if (apicid
== BAD_APICID
||
1093 !physid_isset(apicid
, phys_cpu_present_map
) ||
1094 !apic
->apic_id_valid(apicid
)) {
1095 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1100 * Already booted CPU?
1102 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1103 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1108 * Save current MTRR state in case it was changed since early boot
1109 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1113 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1114 err
= cpu_check_up_prepare(cpu
);
1115 if (err
&& err
!= -EBUSY
)
1118 /* the FPU context is blank, nobody can own it */
1119 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1121 common_cpu_up(cpu
, tidle
);
1123 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1125 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1131 * Check TSC synchronization with the AP (keep irqs disabled
1134 local_irq_save(flags
);
1135 check_tsc_sync_source(cpu
);
1136 local_irq_restore(flags
);
1138 while (!cpu_online(cpu
)) {
1140 touch_nmi_watchdog();
1145 * Clean up the nmi handler. Do this after the callin and callout sync
1146 * to avoid impact of possible long unregister time.
1148 if (cpu0_nmi_registered
)
1149 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1155 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1157 void arch_disable_smp_support(void)
1159 disable_ioapic_support();
1163 * Fall back to non SMP mode after errors.
1165 * RED-PEN audit/test this more. I bet there is more state messed up here.
1167 static __init
void disable_smp(void)
1169 pr_info("SMP disabled\n");
1171 disable_ioapic_support();
1173 init_cpu_present(cpumask_of(0));
1174 init_cpu_possible(cpumask_of(0));
1176 if (smp_found_config
)
1177 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1179 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1180 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1181 cpumask_set_cpu(0, topology_core_cpumask(0));
1192 * Various sanity checks.
1194 static int __init
smp_sanity_check(unsigned max_cpus
)
1198 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1199 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1203 pr_warn("More than 8 CPUs detected - skipping them\n"
1204 "Use CONFIG_X86_BIGSMP\n");
1207 for_each_present_cpu(cpu
) {
1209 set_cpu_present(cpu
, false);
1214 for_each_possible_cpu(cpu
) {
1216 set_cpu_possible(cpu
, false);
1224 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1225 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1226 hard_smp_processor_id());
1228 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1232 * If we couldn't find an SMP configuration at boot time,
1233 * get out of here now!
1235 if (!smp_found_config
&& !acpi_lapic
) {
1237 pr_notice("SMP motherboard not detected\n");
1238 return SMP_NO_CONFIG
;
1242 * Should not be necessary because the MP table should list the boot
1243 * CPU too, but we do it for the sake of robustness anyway.
1245 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1246 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1247 boot_cpu_physical_apicid
);
1248 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1253 * If we couldn't find a local APIC, then get out of here now!
1255 if (APIC_INTEGRATED(boot_cpu_apic_version
) &&
1256 !boot_cpu_has(X86_FEATURE_APIC
)) {
1257 if (!disable_apic
) {
1258 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1259 boot_cpu_physical_apicid
);
1260 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1266 * If SMP should be disabled, then really disable it!
1269 pr_info("SMP mode deactivated\n");
1270 return SMP_FORCE_UP
;
1276 static void __init
smp_cpu_index_default(void)
1279 struct cpuinfo_x86
*c
;
1281 for_each_possible_cpu(i
) {
1283 /* mark all to hotplug */
1284 c
->cpu_index
= nr_cpu_ids
;
1289 * Prepare for SMP bootup. The MP table or ACPI has been read
1290 * earlier. Just do some sanity checking here and enable APIC mode.
1292 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1296 smp_cpu_index_default();
1299 * Setup boot CPU information
1301 smp_store_boot_cpu_info(); /* Final full version of the data */
1302 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1305 for_each_possible_cpu(i
) {
1306 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1307 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1308 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1312 * Set 'default' x86 topology, this matches default_topology() in that
1313 * it has NUMA nodes as a topology level. See also
1314 * native_smp_cpus_done().
1316 * Must be done before set_cpus_sibling_map() is ran.
1318 set_sched_topology(x86_topology
);
1320 set_cpu_sibling_map(0);
1322 switch (smp_sanity_check(max_cpus
)) {
1325 if (APIC_init_uniprocessor())
1326 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1333 apic_bsp_setup(false);
1339 if (read_apic_id() != boot_cpu_physical_apicid
) {
1340 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1341 read_apic_id(), boot_cpu_physical_apicid
);
1342 /* Or can we switch back to PIC here? */
1345 default_setup_apic_routing();
1346 cpu0_logical_apicid
= apic_bsp_setup(false);
1349 print_cpu_info(&cpu_data(0));
1353 set_mtrr_aps_delayed_init();
1355 smp_quirk_init_udelay();
1357 speculative_store_bypass_ht_init();
1360 void arch_enable_nonboot_cpus_begin(void)
1362 set_mtrr_aps_delayed_init();
1365 void arch_enable_nonboot_cpus_end(void)
1371 * Early setup to make printk work.
1373 void __init
native_smp_prepare_boot_cpu(void)
1375 int me
= smp_processor_id();
1376 switch_to_new_gdt(me
);
1377 /* already set me in cpu_online_mask in boot_cpu_init() */
1378 cpumask_set_cpu(me
, cpu_callout_mask
);
1379 cpu_set_state_online(me
);
1382 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1384 pr_debug("Boot done\n");
1386 if (x86_has_numa_in_package
)
1387 set_sched_topology(x86_numa_in_package_topology
);
1391 setup_ioapic_dest();
1395 static int __initdata setup_possible_cpus
= -1;
1396 static int __init
_setup_possible_cpus(char *str
)
1398 get_option(&str
, &setup_possible_cpus
);
1401 early_param("possible_cpus", _setup_possible_cpus
);
1405 * cpu_possible_mask should be static, it cannot change as cpu's
1406 * are onlined, or offlined. The reason is per-cpu data-structures
1407 * are allocated by some modules at init time, and dont expect to
1408 * do this dynamically on cpu arrival/departure.
1409 * cpu_present_mask on the other hand can change dynamically.
1410 * In case when cpu_hotplug is not compiled, then we resort to current
1411 * behaviour, which is cpu_possible == cpu_present.
1414 * Three ways to find out the number of additional hotplug CPUs:
1415 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1416 * - The user can overwrite it with possible_cpus=NUM
1417 * - Otherwise don't reserve additional CPUs.
1418 * We do this because additional CPUs waste a lot of memory.
1421 __init
void prefill_possible_map(void)
1425 /* No boot processor was found in mptable or ACPI MADT */
1426 if (!num_processors
) {
1427 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1428 int apicid
= boot_cpu_physical_apicid
;
1429 int cpu
= hard_smp_processor_id();
1431 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1433 /* Make sure boot cpu is enumerated */
1434 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1435 apic
->apic_id_valid(apicid
))
1436 generic_processor_info(apicid
, boot_cpu_apic_version
);
1439 if (!num_processors
)
1443 i
= setup_max_cpus
?: 1;
1444 if (setup_possible_cpus
== -1) {
1445 possible
= num_processors
;
1446 #ifdef CONFIG_HOTPLUG_CPU
1448 possible
+= disabled_cpus
;
1454 possible
= setup_possible_cpus
;
1456 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1458 /* nr_cpu_ids could be reduced via nr_cpus= */
1459 if (possible
> nr_cpu_ids
) {
1460 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1461 possible
, nr_cpu_ids
);
1462 possible
= nr_cpu_ids
;
1465 #ifdef CONFIG_HOTPLUG_CPU
1466 if (!setup_max_cpus
)
1469 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1470 possible
, setup_max_cpus
);
1474 nr_cpu_ids
= possible
;
1476 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1477 possible
, max_t(int, possible
- num_processors
, 0));
1479 reset_cpu_possible_mask();
1481 for (i
= 0; i
< possible
; i
++)
1482 set_cpu_possible(i
, true);
1485 #ifdef CONFIG_HOTPLUG_CPU
1487 /* Recompute SMT state for all CPUs on offline */
1488 static void recompute_smt_state(void)
1490 int max_threads
, cpu
;
1493 for_each_online_cpu (cpu
) {
1494 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1496 if (threads
> max_threads
)
1497 max_threads
= threads
;
1499 __max_smt_threads
= max_threads
;
1502 static void remove_siblinginfo(int cpu
)
1505 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1507 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1508 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1510 * last thread sibling in this cpu core going down
1512 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1513 cpu_data(sibling
).booted_cores
--;
1516 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1517 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1518 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1519 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1520 cpumask_clear(cpu_llc_shared_mask(cpu
));
1521 cpumask_clear(topology_sibling_cpumask(cpu
));
1522 cpumask_clear(topology_core_cpumask(cpu
));
1523 c
->phys_proc_id
= 0;
1525 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1526 recompute_smt_state();
1529 static void remove_cpu_from_maps(int cpu
)
1531 set_cpu_online(cpu
, false);
1532 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1533 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1534 /* was set by cpu_init() */
1535 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1536 numa_remove_cpu(cpu
);
1539 void cpu_disable_common(void)
1541 int cpu
= smp_processor_id();
1543 remove_siblinginfo(cpu
);
1545 /* It's now safe to remove this processor from the online map */
1547 remove_cpu_from_maps(cpu
);
1548 unlock_vector_lock();
1552 int native_cpu_disable(void)
1556 ret
= check_irq_vectors_for_cpu_disable();
1561 cpu_disable_common();
1566 int common_cpu_die(unsigned int cpu
)
1570 /* We don't do anything here: idle task is faking death itself. */
1572 /* They ack this in play_dead() by setting CPU_DEAD */
1573 if (cpu_wait_death(cpu
, 5)) {
1574 if (system_state
== SYSTEM_RUNNING
)
1575 pr_info("CPU %u is now offline\n", cpu
);
1577 pr_err("CPU %u didn't die...\n", cpu
);
1584 void native_cpu_die(unsigned int cpu
)
1586 common_cpu_die(cpu
);
1589 void play_dead_common(void)
1594 (void)cpu_report_death();
1597 * With physical CPU hotplug, we should halt the cpu
1599 local_irq_disable();
1602 static bool wakeup_cpu0(void)
1604 if (smp_processor_id() == 0 && enable_start_cpu0
)
1611 * We need to flush the caches before going to sleep, lest we have
1612 * dirty data in our caches when we come back up.
1614 static inline void mwait_play_dead(void)
1616 unsigned int eax
, ebx
, ecx
, edx
;
1617 unsigned int highest_cstate
= 0;
1618 unsigned int highest_subcstate
= 0;
1622 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1624 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1626 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1629 eax
= CPUID_MWAIT_LEAF
;
1631 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1634 * eax will be 0 if EDX enumeration is not valid.
1635 * Initialized below to cstate, sub_cstate value when EDX is valid.
1637 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1640 edx
>>= MWAIT_SUBSTATE_SIZE
;
1641 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1642 if (edx
& MWAIT_SUBSTATE_MASK
) {
1644 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1647 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1648 (highest_subcstate
- 1);
1652 * This should be a memory location in a cache line which is
1653 * unlikely to be touched by other processors. The actual
1654 * content is immaterial as it is not actually modified in any way.
1656 mwait_ptr
= ¤t_thread_info()->flags
;
1662 * The CLFLUSH is a workaround for erratum AAI65 for
1663 * the Xeon 7400 series. It's not clear it is actually
1664 * needed, but it should be harmless in either case.
1665 * The WBINVD is insufficient due to the spurious-wakeup
1666 * case where we return around the loop.
1671 __monitor(mwait_ptr
, 0, 0);
1675 * If NMI wants to wake up CPU0, start CPU0.
1682 void hlt_play_dead(void)
1684 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1690 * If NMI wants to wake up CPU0, start CPU0.
1697 void native_play_dead(void)
1700 tboot_shutdown(TB_SHUTDOWN_WFS
);
1703 native_wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
1705 mwait_play_dead(); /* Only returns on failure */
1706 if (cpuidle_play_dead())
1710 native_wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
| SPEC_CTRL_IBRS
);
1713 #else /* ... !CONFIG_HOTPLUG_CPU */
1714 int native_cpu_disable(void)
1719 void native_cpu_die(unsigned int cpu
)
1721 /* We said "no" in __cpu_disable */
1725 void native_play_dead(void)