2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
64 #include <asm/realmode.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
70 #include <asm/mwait.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* Number of siblings per CPU package */
82 int smp_num_siblings
= 1;
83 EXPORT_SYMBOL(smp_num_siblings
);
85 /* Last level cache ID of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
88 /* representing HT siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
92 /* representing HT and core siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
94 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
100 EXPORT_PER_CPU_SYMBOL(cpu_info
);
102 /* Logical package management. We might want to allocate that dynamically */
103 static int *physical_to_logical_pkg __read_mostly
;
104 static unsigned long *physical_package_map __read_mostly
;;
105 static unsigned int max_physical_pkg_id __read_mostly
;
106 unsigned int __max_logical_packages __read_mostly
;
107 EXPORT_SYMBOL(__max_logical_packages
);
108 static unsigned int logical_packages __read_mostly
;
110 /* Maximum number of SMT threads on any online core */
111 int __max_smt_threads __read_mostly
;
113 /* Flag to indicate if a complete sched domain rebuild is required */
114 bool x86_topology_update
;
116 int arch_update_cpu_topology(void)
118 int retval
= x86_topology_update
;
120 x86_topology_update
= false;
124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
128 spin_lock_irqsave(&rtc_lock
, flags
);
129 CMOS_WRITE(0xa, 0xf);
130 spin_unlock_irqrestore(&rtc_lock
, flags
);
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
141 static inline void smpboot_restore_warm_reset_vector(void)
146 * Install writable page 0 entry to set BIOS data area.
151 * Paranoid: Set warm reset code and vector here back
154 spin_lock_irqsave(&rtc_lock
, flags
);
156 spin_unlock_irqrestore(&rtc_lock
, flags
);
158 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
162 * Report back to the Boot Processor during boot time or to the caller processor
165 static void smp_callin(void)
170 * If waken up by an INIT in an 82489DX configuration
171 * cpu_callout_mask guarantees we don't get here before
172 * an INIT_deassert IPI reaches our local APIC, so it is
173 * now safe to touch our local APIC.
175 cpuid
= smp_processor_id();
178 * (This works even if the APIC is not enabled.)
180 phys_id
= read_apic_id();
183 * the boot CPU has finished the init stage and is spinning
184 * on callin_map until we finish. We are free to set up this
185 * CPU, first the APIC. (this is probably redundant on most
191 * Save our processor parameters. Note: this information
192 * is needed for clock calibration.
194 smp_store_cpu_info(cpuid
);
198 * Update loops_per_jiffy in cpu_data. Previous call to
199 * smp_store_cpu_info() stored a value that is close but not as
200 * accurate as the value just calculated.
203 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
204 pr_debug("Stack at about %p\n", &cpuid
);
207 * This must be done before setting cpu_online_mask
208 * or calling notify_cpu_starting.
210 set_cpu_sibling_map(raw_smp_processor_id());
213 notify_cpu_starting(cpuid
);
216 * Allow the master to continue.
218 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
221 static int cpu0_logical_apicid
;
222 static int enable_start_cpu0
;
224 * Activate a secondary processor.
226 static void notrace
start_secondary(void *unused
)
229 * Don't put *anything* before cpu_init(), SMP booting is too
230 * fragile that we want to limit the things done here to the
231 * most necessary things.
234 x86_cpuinit
.early_percpu_clock_init();
238 enable_start_cpu0
= 0;
241 /* switch away from the initial page table */
242 load_cr3(swapper_pg_dir
);
246 /* otherwise gcc will move up smp_processor_id before the cpu_init */
249 * Check TSC synchronization with the BP:
251 check_tsc_sync_target();
254 * Lock vector_lock and initialize the vectors on this cpu
255 * before setting the cpu online. We must set it online with
256 * vector_lock held to prevent a concurrent setup/teardown
257 * from seeing a half valid vector space.
260 setup_vector_irq(smp_processor_id());
261 set_cpu_online(smp_processor_id(), true);
262 unlock_vector_lock();
263 cpu_set_state_online(smp_processor_id());
264 x86_platform
.nmi_init();
266 /* enable local interrupts */
269 /* to prevent fake stack check failure in clock setup */
270 boot_init_stack_canary();
272 x86_cpuinit
.setup_percpu_clockev();
275 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
279 * topology_update_package_map - Update the physical to logical package map
280 * @pkg: The physical package id as retrieved via CPUID
281 * @cpu: The cpu for which this is updated
283 int topology_update_package_map(unsigned int pkg
, unsigned int cpu
)
287 /* Called from early boot ? */
288 if (!physical_package_map
)
291 if (pkg
>= max_physical_pkg_id
)
294 /* Set the logical package id */
295 if (test_and_set_bit(pkg
, physical_package_map
))
298 if (logical_packages
>= __max_logical_packages
) {
299 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
300 logical_packages
, cpu
, __max_logical_packages
);
304 new = logical_packages
++;
306 pr_info("CPU %u Converting physical %u to logical package %u\n",
309 physical_to_logical_pkg
[pkg
] = new;
312 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
317 * topology_phys_to_logical_pkg - Map a physical package id to a logical
319 * Returns logical package id or -1 if not found
321 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
323 if (phys_pkg
>= max_physical_pkg_id
)
325 return physical_to_logical_pkg
[phys_pkg
];
327 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
329 static void __init
smp_init_package_map(struct cpuinfo_x86
*c
, unsigned int cpu
)
335 * Today neither Intel nor AMD support heterogenous systems. That
336 * might change in the future....
338 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
339 * computation, this won't actually work since some Intel BIOSes
340 * report inconsistent HT data when they disable HT.
342 * In particular, they reduce the APIC-IDs to only include the cores,
343 * but leave the CPUID topology to say there are (2) siblings.
344 * This means we don't know how many threads there will be until
345 * after the APIC enumeration.
347 * By not including this we'll sometimes over-estimate the number of
348 * logical packages by the amount of !present siblings, but this is
349 * still better than MAX_LOCAL_APIC.
351 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
352 * on the command line leading to a similar issue as the HT disable
353 * problem because the hyperthreads are usually enumerated after the
356 ncpus
= boot_cpu_data
.x86_max_cores
;
358 pr_warn("x86_max_cores == zero !?!?");
362 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
363 logical_packages
= 0;
366 * Possibly larger than what we need as the number of apic ids per
367 * package can be smaller than the actual used apic ids.
369 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
370 size
= max_physical_pkg_id
* sizeof(unsigned int);
371 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
372 memset(physical_to_logical_pkg
, 0xff, size
);
373 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
374 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
376 pr_info("Max logical packages: %u\n", __max_logical_packages
);
378 topology_update_package_map(c
->phys_proc_id
, cpu
);
381 void __init
smp_store_boot_cpu_info(void)
383 int id
= 0; /* CPU 0 */
384 struct cpuinfo_x86
*c
= &cpu_data(id
);
388 smp_init_package_map(c
, id
);
392 * The bootstrap kernel entry code has set these up. Save them for
395 void smp_store_cpu_info(int id
)
397 struct cpuinfo_x86
*c
= &cpu_data(id
);
402 * During boot time, CPU0 has this setup already. Save the info when
403 * bringing up AP or offlined CPU0.
405 identify_secondary_cpu(c
);
409 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
411 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
413 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
417 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
419 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
421 return !WARN_ONCE(!topology_same_node(c
, o
),
422 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
423 "[node: %d != %d]. Ignoring dependency.\n",
424 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
427 #define link_mask(mfunc, c1, c2) \
429 cpumask_set_cpu((c1), mfunc(c2)); \
430 cpumask_set_cpu((c2), mfunc(c1)); \
433 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
435 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
436 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
438 if (c
->phys_proc_id
== o
->phys_proc_id
&&
439 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
)) {
440 if (c
->cpu_core_id
== o
->cpu_core_id
)
441 return topology_sane(c
, o
, "smt");
443 if ((c
->cu_id
!= 0xff) &&
444 (o
->cu_id
!= 0xff) &&
445 (c
->cu_id
== o
->cu_id
))
446 return topology_sane(c
, o
, "smt");
449 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
450 c
->cpu_core_id
== o
->cpu_core_id
) {
451 return topology_sane(c
, o
, "smt");
457 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
459 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
461 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
462 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
463 return topology_sane(c
, o
, "llc");
469 * Unlike the other levels, we do not enforce keeping a
470 * multicore group inside a NUMA node. If this happens, we will
471 * discard the MC level of the topology later.
473 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
475 if (c
->phys_proc_id
== o
->phys_proc_id
)
480 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
481 static inline int x86_sched_itmt_flags(void)
483 return sysctl_sched_itmt_enabled
? SD_ASYM_PACKING
: 0;
486 #ifdef CONFIG_SCHED_MC
487 static int x86_core_flags(void)
489 return cpu_core_flags() | x86_sched_itmt_flags();
492 #ifdef CONFIG_SCHED_SMT
493 static int x86_smt_flags(void)
495 return cpu_smt_flags() | x86_sched_itmt_flags();
500 static struct sched_domain_topology_level x86_numa_in_package_topology
[] = {
501 #ifdef CONFIG_SCHED_SMT
502 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
504 #ifdef CONFIG_SCHED_MC
505 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
510 static struct sched_domain_topology_level x86_topology
[] = {
511 #ifdef CONFIG_SCHED_SMT
512 { cpu_smt_mask
, x86_smt_flags
, SD_INIT_NAME(SMT
) },
514 #ifdef CONFIG_SCHED_MC
515 { cpu_coregroup_mask
, x86_core_flags
, SD_INIT_NAME(MC
) },
517 { cpu_cpu_mask
, SD_INIT_NAME(DIE
) },
522 * Set if a package/die has multiple NUMA nodes inside.
523 * AMD Magny-Cours and Intel Cluster-on-Die have this.
525 static bool x86_has_numa_in_package
;
527 void set_cpu_sibling_map(int cpu
)
529 bool has_smt
= smp_num_siblings
> 1;
530 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
531 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
532 struct cpuinfo_x86
*o
;
535 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
538 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
539 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
540 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
545 for_each_cpu(i
, cpu_sibling_setup_mask
) {
548 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
549 link_mask(topology_sibling_cpumask
, cpu
, i
);
551 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
552 link_mask(cpu_llc_shared_mask
, cpu
, i
);
557 * This needs a separate iteration over the cpus because we rely on all
558 * topology_sibling_cpumask links to be set-up.
560 for_each_cpu(i
, cpu_sibling_setup_mask
) {
563 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
564 link_mask(topology_core_cpumask
, cpu
, i
);
567 * Does this new cpu bringup a new core?
570 topology_sibling_cpumask(cpu
)) == 1) {
572 * for each core in package, increment
573 * the booted_cores for this new cpu
576 topology_sibling_cpumask(i
)) == i
)
579 * increment the core count for all
580 * the other cpus in this package
583 cpu_data(i
).booted_cores
++;
584 } else if (i
!= cpu
&& !c
->booted_cores
)
585 c
->booted_cores
= cpu_data(i
).booted_cores
;
587 if (match_die(c
, o
) && !topology_same_node(c
, o
))
588 x86_has_numa_in_package
= true;
591 threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
592 if (threads
> __max_smt_threads
)
593 __max_smt_threads
= threads
;
596 /* maps the cpu to the sched domain representing multi-core */
597 const struct cpumask
*cpu_coregroup_mask(int cpu
)
599 return cpu_llc_shared_mask(cpu
);
602 static void impress_friends(void)
605 unsigned long bogosum
= 0;
607 * Allow the user to impress friends.
609 pr_debug("Before bogomips\n");
610 for_each_possible_cpu(cpu
)
611 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
612 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
613 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
616 (bogosum
/(5000/HZ
))%100);
618 pr_debug("Before bogocount - setting activated=1\n");
621 void __inquire_remote_apic(int apicid
)
623 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
624 const char * const names
[] = { "ID", "VERSION", "SPIV" };
628 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
630 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
631 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
636 status
= safe_apic_wait_icr_idle();
638 pr_cont("a previous APIC delivery may have failed\n");
640 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
645 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
646 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
649 case APIC_ICR_RR_VALID
:
650 status
= apic_read(APIC_RRR
);
651 pr_cont("%08x\n", status
);
660 * The Multiprocessor Specification 1.4 (1997) example code suggests
661 * that there should be a 10ms delay between the BSP asserting INIT
662 * and de-asserting INIT, when starting a remote processor.
663 * But that slows boot and resume on modern processors, which include
664 * many cores and don't require that delay.
666 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
667 * Modern processor families are quirked to remove the delay entirely.
669 #define UDELAY_10MS_DEFAULT 10000
671 static unsigned int init_udelay
= UINT_MAX
;
673 static int __init
cpu_init_udelay(char *str
)
675 get_option(&str
, &init_udelay
);
679 early_param("cpu_init_udelay", cpu_init_udelay
);
681 static void __init
smp_quirk_init_udelay(void)
683 /* if cmdline changed it from default, leave it alone */
684 if (init_udelay
!= UINT_MAX
)
687 /* if modern processor, use no delay */
688 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
689 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
693 /* else, use legacy delay */
694 init_udelay
= UDELAY_10MS_DEFAULT
;
698 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
699 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
700 * won't ... remember to clear down the APIC, etc later.
703 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
705 unsigned long send_status
, accept_status
= 0;
709 /* Boot on the stack */
710 /* Kick the second */
711 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
713 pr_debug("Waiting for send to finish...\n");
714 send_status
= safe_apic_wait_icr_idle();
717 * Give the other CPU some time to accept the IPI.
720 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
721 maxlvt
= lapic_get_maxlvt();
722 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
723 apic_write(APIC_ESR
, 0);
724 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
726 pr_debug("NMI sent\n");
729 pr_err("APIC never delivered???\n");
731 pr_err("APIC delivery error (%lx)\n", accept_status
);
733 return (send_status
| accept_status
);
737 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
739 unsigned long send_status
= 0, accept_status
= 0;
740 int maxlvt
, num_starts
, j
;
742 maxlvt
= lapic_get_maxlvt();
745 * Be paranoid about clearing APIC errors.
747 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
748 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
749 apic_write(APIC_ESR
, 0);
753 pr_debug("Asserting INIT\n");
756 * Turn INIT on target chip
761 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
764 pr_debug("Waiting for send to finish...\n");
765 send_status
= safe_apic_wait_icr_idle();
769 pr_debug("Deasserting INIT\n");
773 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
775 pr_debug("Waiting for send to finish...\n");
776 send_status
= safe_apic_wait_icr_idle();
781 * Should we send STARTUP IPIs ?
783 * Determine this based on the APIC version.
784 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
786 if (APIC_INTEGRATED(boot_cpu_apic_version
))
792 * Run STARTUP IPI loop.
794 pr_debug("#startup loops: %d\n", num_starts
);
796 for (j
= 1; j
<= num_starts
; j
++) {
797 pr_debug("Sending STARTUP #%d\n", j
);
798 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
799 apic_write(APIC_ESR
, 0);
801 pr_debug("After apic_write\n");
808 /* Boot on the stack */
809 /* Kick the second */
810 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
814 * Give the other CPU some time to accept the IPI.
816 if (init_udelay
== 0)
821 pr_debug("Startup point 1\n");
823 pr_debug("Waiting for send to finish...\n");
824 send_status
= safe_apic_wait_icr_idle();
827 * Give the other CPU some time to accept the IPI.
829 if (init_udelay
== 0)
834 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
835 apic_write(APIC_ESR
, 0);
836 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
837 if (send_status
|| accept_status
)
840 pr_debug("After Startup\n");
843 pr_err("APIC never delivered???\n");
845 pr_err("APIC delivery error (%lx)\n", accept_status
);
847 return (send_status
| accept_status
);
850 /* reduce the number of lines printed when booting a large cpu count system */
851 static void announce_cpu(int cpu
, int apicid
)
853 static int current_node
= -1;
854 int node
= early_cpu_to_node(cpu
);
855 static int width
, node_width
;
858 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
861 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
864 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
866 if (system_state
< SYSTEM_RUNNING
) {
867 if (node
!= current_node
) {
868 if (current_node
> (-1))
872 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
873 node_width
- num_digits(node
), " ", node
);
876 /* Add padding for the BSP */
878 pr_cont("%*s", width
+ 1, " ");
880 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
883 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
887 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
891 cpu
= smp_processor_id();
892 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
899 * Wake up AP by INIT, INIT, STARTUP sequence.
901 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
902 * boot-strap code which is not a desired behavior for waking up BSP. To
903 * void the boot-strap code, wake up CPU0 by NMI instead.
905 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
906 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
907 * We'll change this code in the future to wake up hard offlined CPU0 if
908 * real platform and request are available.
911 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
912 int *cpu0_nmi_registered
)
920 * Wake up AP by INIT, INIT, STARTUP sequence.
923 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
928 * Wake up BSP by nmi.
930 * Register a NMI handler to help wake up CPU0.
932 boot_error
= register_nmi_handler(NMI_LOCAL
,
933 wakeup_cpu0_nmi
, 0, "wake_cpu0");
936 enable_start_cpu0
= 1;
937 *cpu0_nmi_registered
= 1;
938 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
939 id
= cpu0_logical_apicid
;
942 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
951 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
953 /* Just in case we booted with a single CPU. */
954 alternatives_enable_smp();
956 per_cpu(current_task
, cpu
) = idle
;
959 /* Stack for startup_32 can be just as for start_secondary onwards */
961 per_cpu(cpu_current_top_of_stack
, cpu
) =
962 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
964 initial_gs
= per_cpu_offset(cpu
);
969 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
970 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
971 * Returns zero if CPU booted OK, else error code from
972 * ->wakeup_secondary_cpu.
974 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
,
975 int *cpu0_nmi_registered
)
977 volatile u32
*trampoline_status
=
978 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
979 /* start_ip had better be page-aligned! */
980 unsigned long start_ip
= real_mode_header
->trampoline_start
;
982 unsigned long boot_error
= 0;
983 unsigned long timeout
;
985 idle
->thread
.sp
= (unsigned long)task_pt_regs(idle
);
986 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_rw(cpu
);
987 initial_code
= (unsigned long)start_secondary
;
988 initial_stack
= idle
->thread
.sp
;
991 * Enable the espfix hack for this CPU
993 #ifdef CONFIG_X86_ESPFIX64
997 /* So we see what's up */
998 announce_cpu(cpu
, apicid
);
1001 * This grunge runs the startup process for
1002 * the targeted processor.
1005 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1007 pr_debug("Setting warm reset code and vector.\n");
1009 smpboot_setup_warm_reset_vector(start_ip
);
1011 * Be paranoid about clearing APIC errors.
1013 if (APIC_INTEGRATED(boot_cpu_apic_version
)) {
1014 apic_write(APIC_ESR
, 0);
1015 apic_read(APIC_ESR
);
1020 * AP might wait on cpu_callout_mask in cpu_init() with
1021 * cpu_initialized_mask set if previous attempt to online
1022 * it timed-out. Clear cpu_initialized_mask so that after
1023 * INIT/SIPI it could start with a clean state.
1025 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1029 * Wake up a CPU in difference cases:
1030 * - Use the method in the APIC driver if it's defined
1032 * - Use an INIT boot APIC message for APs or NMI for BSP.
1034 if (apic
->wakeup_secondary_cpu
)
1035 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1037 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1038 cpu0_nmi_registered
);
1042 * Wait 10s total for first sign of life from AP
1045 timeout
= jiffies
+ 10*HZ
;
1046 while (time_before(jiffies
, timeout
)) {
1047 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1049 * Tell AP to proceed with initialization
1051 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1061 * Wait till AP completes initial initialization
1063 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1065 * Allow other tasks to run while we wait for the
1066 * AP to come online. This also gives a chance
1067 * for the MTRR work(triggered by the AP coming online)
1068 * to be completed in the stop machine context.
1074 /* mark "stuck" area as not stuck */
1075 *trampoline_status
= 0;
1077 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1079 * Cleanup possible dangling ends...
1081 smpboot_restore_warm_reset_vector();
1087 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1089 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1090 int cpu0_nmi_registered
= 0;
1091 unsigned long flags
;
1094 WARN_ON(irqs_disabled());
1096 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1098 if (apicid
== BAD_APICID
||
1099 !physid_isset(apicid
, phys_cpu_present_map
) ||
1100 !apic
->apic_id_valid(apicid
)) {
1101 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1106 * Already booted CPU?
1108 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1109 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1114 * Save current MTRR state in case it was changed since early boot
1115 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1119 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1120 err
= cpu_check_up_prepare(cpu
);
1121 if (err
&& err
!= -EBUSY
)
1124 /* the FPU context is blank, nobody can own it */
1125 per_cpu(fpu_fpregs_owner_ctx
, cpu
) = NULL
;
1127 common_cpu_up(cpu
, tidle
);
1129 err
= do_boot_cpu(apicid
, cpu
, tidle
, &cpu0_nmi_registered
);
1131 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1137 * Check TSC synchronization with the AP (keep irqs disabled
1140 local_irq_save(flags
);
1141 check_tsc_sync_source(cpu
);
1142 local_irq_restore(flags
);
1144 while (!cpu_online(cpu
)) {
1146 touch_nmi_watchdog();
1151 * Clean up the nmi handler. Do this after the callin and callout sync
1152 * to avoid impact of possible long unregister time.
1154 if (cpu0_nmi_registered
)
1155 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1161 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1163 void arch_disable_smp_support(void)
1165 disable_ioapic_support();
1169 * Fall back to non SMP mode after errors.
1171 * RED-PEN audit/test this more. I bet there is more state messed up here.
1173 static __init
void disable_smp(void)
1175 pr_info("SMP disabled\n");
1177 disable_ioapic_support();
1179 init_cpu_present(cpumask_of(0));
1180 init_cpu_possible(cpumask_of(0));
1182 if (smp_found_config
)
1183 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1185 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1186 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1187 cpumask_set_cpu(0, topology_core_cpumask(0));
1198 * Various sanity checks.
1200 static int __init
smp_sanity_check(unsigned max_cpus
)
1204 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1205 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1209 pr_warn("More than 8 CPUs detected - skipping them\n"
1210 "Use CONFIG_X86_BIGSMP\n");
1213 for_each_present_cpu(cpu
) {
1215 set_cpu_present(cpu
, false);
1220 for_each_possible_cpu(cpu
) {
1222 set_cpu_possible(cpu
, false);
1230 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1231 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1232 hard_smp_processor_id());
1234 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1238 * If we couldn't find an SMP configuration at boot time,
1239 * get out of here now!
1241 if (!smp_found_config
&& !acpi_lapic
) {
1243 pr_notice("SMP motherboard not detected\n");
1244 return SMP_NO_CONFIG
;
1248 * Should not be necessary because the MP table should list the boot
1249 * CPU too, but we do it for the sake of robustness anyway.
1251 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1252 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1253 boot_cpu_physical_apicid
);
1254 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1259 * If we couldn't find a local APIC, then get out of here now!
1261 if (APIC_INTEGRATED(boot_cpu_apic_version
) &&
1262 !boot_cpu_has(X86_FEATURE_APIC
)) {
1263 if (!disable_apic
) {
1264 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1265 boot_cpu_physical_apicid
);
1266 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1272 * If SMP should be disabled, then really disable it!
1275 pr_info("SMP mode deactivated\n");
1276 return SMP_FORCE_UP
;
1282 static void __init
smp_cpu_index_default(void)
1285 struct cpuinfo_x86
*c
;
1287 for_each_possible_cpu(i
) {
1289 /* mark all to hotplug */
1290 c
->cpu_index
= nr_cpu_ids
;
1295 * Prepare for SMP bootup. The MP table or ACPI has been read
1296 * earlier. Just do some sanity checking here and enable APIC mode.
1298 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1302 smp_cpu_index_default();
1305 * Setup boot CPU information
1307 smp_store_boot_cpu_info(); /* Final full version of the data */
1308 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1311 for_each_possible_cpu(i
) {
1312 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1313 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1314 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1318 * Set 'default' x86 topology, this matches default_topology() in that
1319 * it has NUMA nodes as a topology level. See also
1320 * native_smp_cpus_done().
1322 * Must be done before set_cpus_sibling_map() is ran.
1324 set_sched_topology(x86_topology
);
1326 set_cpu_sibling_map(0);
1328 switch (smp_sanity_check(max_cpus
)) {
1331 if (APIC_init_uniprocessor())
1332 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1339 apic_bsp_setup(false);
1345 if (read_apic_id() != boot_cpu_physical_apicid
) {
1346 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1347 read_apic_id(), boot_cpu_physical_apicid
);
1348 /* Or can we switch back to PIC here? */
1351 default_setup_apic_routing();
1352 cpu0_logical_apicid
= apic_bsp_setup(false);
1355 print_cpu_info(&cpu_data(0));
1359 set_mtrr_aps_delayed_init();
1361 smp_quirk_init_udelay();
1364 void arch_enable_nonboot_cpus_begin(void)
1366 set_mtrr_aps_delayed_init();
1369 void arch_enable_nonboot_cpus_end(void)
1375 * Early setup to make printk work.
1377 void __init
native_smp_prepare_boot_cpu(void)
1379 int me
= smp_processor_id();
1380 switch_to_new_gdt(me
);
1381 /* already set me in cpu_online_mask in boot_cpu_init() */
1382 cpumask_set_cpu(me
, cpu_callout_mask
);
1383 cpu_set_state_online(me
);
1386 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1388 pr_debug("Boot done\n");
1390 if (x86_has_numa_in_package
)
1391 set_sched_topology(x86_numa_in_package_topology
);
1395 setup_ioapic_dest();
1399 static int __initdata setup_possible_cpus
= -1;
1400 static int __init
_setup_possible_cpus(char *str
)
1402 get_option(&str
, &setup_possible_cpus
);
1405 early_param("possible_cpus", _setup_possible_cpus
);
1409 * cpu_possible_mask should be static, it cannot change as cpu's
1410 * are onlined, or offlined. The reason is per-cpu data-structures
1411 * are allocated by some modules at init time, and dont expect to
1412 * do this dynamically on cpu arrival/departure.
1413 * cpu_present_mask on the other hand can change dynamically.
1414 * In case when cpu_hotplug is not compiled, then we resort to current
1415 * behaviour, which is cpu_possible == cpu_present.
1418 * Three ways to find out the number of additional hotplug CPUs:
1419 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1420 * - The user can overwrite it with possible_cpus=NUM
1421 * - Otherwise don't reserve additional CPUs.
1422 * We do this because additional CPUs waste a lot of memory.
1425 __init
void prefill_possible_map(void)
1429 /* No boot processor was found in mptable or ACPI MADT */
1430 if (!num_processors
) {
1431 if (boot_cpu_has(X86_FEATURE_APIC
)) {
1432 int apicid
= boot_cpu_physical_apicid
;
1433 int cpu
= hard_smp_processor_id();
1435 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu
);
1437 /* Make sure boot cpu is enumerated */
1438 if (apic
->cpu_present_to_apicid(0) == BAD_APICID
&&
1439 apic
->apic_id_valid(apicid
))
1440 generic_processor_info(apicid
, boot_cpu_apic_version
);
1443 if (!num_processors
)
1447 i
= setup_max_cpus
?: 1;
1448 if (setup_possible_cpus
== -1) {
1449 possible
= num_processors
;
1450 #ifdef CONFIG_HOTPLUG_CPU
1452 possible
+= disabled_cpus
;
1458 possible
= setup_possible_cpus
;
1460 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1462 /* nr_cpu_ids could be reduced via nr_cpus= */
1463 if (possible
> nr_cpu_ids
) {
1464 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1465 possible
, nr_cpu_ids
);
1466 possible
= nr_cpu_ids
;
1469 #ifdef CONFIG_HOTPLUG_CPU
1470 if (!setup_max_cpus
)
1473 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1474 possible
, setup_max_cpus
);
1478 nr_cpu_ids
= possible
;
1480 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1481 possible
, max_t(int, possible
- num_processors
, 0));
1483 reset_cpu_possible_mask();
1485 for (i
= 0; i
< possible
; i
++)
1486 set_cpu_possible(i
, true);
1489 #ifdef CONFIG_HOTPLUG_CPU
1491 /* Recompute SMT state for all CPUs on offline */
1492 static void recompute_smt_state(void)
1494 int max_threads
, cpu
;
1497 for_each_online_cpu (cpu
) {
1498 int threads
= cpumask_weight(topology_sibling_cpumask(cpu
));
1500 if (threads
> max_threads
)
1501 max_threads
= threads
;
1503 __max_smt_threads
= max_threads
;
1506 static void remove_siblinginfo(int cpu
)
1509 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1511 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1512 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1514 * last thread sibling in this cpu core going down
1516 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1517 cpu_data(sibling
).booted_cores
--;
1520 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1521 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1522 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1523 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1524 cpumask_clear(cpu_llc_shared_mask(cpu
));
1525 cpumask_clear(topology_sibling_cpumask(cpu
));
1526 cpumask_clear(topology_core_cpumask(cpu
));
1527 c
->phys_proc_id
= 0;
1529 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1530 recompute_smt_state();
1533 static void remove_cpu_from_maps(int cpu
)
1535 set_cpu_online(cpu
, false);
1536 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1537 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1538 /* was set by cpu_init() */
1539 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1540 numa_remove_cpu(cpu
);
1543 void cpu_disable_common(void)
1545 int cpu
= smp_processor_id();
1547 remove_siblinginfo(cpu
);
1549 /* It's now safe to remove this processor from the online map */
1551 remove_cpu_from_maps(cpu
);
1552 unlock_vector_lock();
1556 int native_cpu_disable(void)
1560 ret
= check_irq_vectors_for_cpu_disable();
1565 cpu_disable_common();
1570 int common_cpu_die(unsigned int cpu
)
1574 /* We don't do anything here: idle task is faking death itself. */
1576 /* They ack this in play_dead() by setting CPU_DEAD */
1577 if (cpu_wait_death(cpu
, 5)) {
1578 if (system_state
== SYSTEM_RUNNING
)
1579 pr_info("CPU %u is now offline\n", cpu
);
1581 pr_err("CPU %u didn't die...\n", cpu
);
1588 void native_cpu_die(unsigned int cpu
)
1590 common_cpu_die(cpu
);
1593 void play_dead_common(void)
1598 (void)cpu_report_death();
1601 * With physical CPU hotplug, we should halt the cpu
1603 local_irq_disable();
1606 static bool wakeup_cpu0(void)
1608 if (smp_processor_id() == 0 && enable_start_cpu0
)
1615 * We need to flush the caches before going to sleep, lest we have
1616 * dirty data in our caches when we come back up.
1618 static inline void mwait_play_dead(void)
1620 unsigned int eax
, ebx
, ecx
, edx
;
1621 unsigned int highest_cstate
= 0;
1622 unsigned int highest_subcstate
= 0;
1626 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1628 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1630 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1633 eax
= CPUID_MWAIT_LEAF
;
1635 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1638 * eax will be 0 if EDX enumeration is not valid.
1639 * Initialized below to cstate, sub_cstate value when EDX is valid.
1641 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1644 edx
>>= MWAIT_SUBSTATE_SIZE
;
1645 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1646 if (edx
& MWAIT_SUBSTATE_MASK
) {
1648 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1651 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1652 (highest_subcstate
- 1);
1656 * This should be a memory location in a cache line which is
1657 * unlikely to be touched by other processors. The actual
1658 * content is immaterial as it is not actually modified in any way.
1660 mwait_ptr
= ¤t_thread_info()->flags
;
1666 * The CLFLUSH is a workaround for erratum AAI65 for
1667 * the Xeon 7400 series. It's not clear it is actually
1668 * needed, but it should be harmless in either case.
1669 * The WBINVD is insufficient due to the spurious-wakeup
1670 * case where we return around the loop.
1675 __monitor(mwait_ptr
, 0, 0);
1679 * If NMI wants to wake up CPU0, start CPU0.
1686 void hlt_play_dead(void)
1688 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1694 * If NMI wants to wake up CPU0, start CPU0.
1701 void native_play_dead(void)
1704 tboot_shutdown(TB_SHUTDOWN_WFS
);
1706 mwait_play_dead(); /* Only returns on failure */
1707 if (cpuidle_play_dead())
1711 #else /* ... !CONFIG_HOTPLUG_CPU */
1712 int native_cpu_disable(void)
1717 void native_cpu_die(unsigned int cpu
)
1719 /* We said "no" in __cpu_disable */
1723 void native_play_dead(void)