2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/smpboot_hooks.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* State of each CPU */
82 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
84 /* Number of siblings per CPU package */
85 int smp_num_siblings
= 1;
86 EXPORT_SYMBOL(smp_num_siblings
);
88 /* Last level cache ID of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
101 /* Per CPU bogomips and other parameters */
102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
103 EXPORT_PER_CPU_SYMBOL(cpu_info
);
105 static DEFINE_PER_CPU(struct completion
, die_complete
);
107 atomic_t init_deasserted
;
110 * Report back to the Boot Processor during boot time or to the caller processor
113 static void smp_callin(void)
118 * If waken up by an INIT in an 82489DX configuration
119 * we may get here before an INIT-deassert IPI reaches
120 * our local APIC. We have to wait for the IPI or we'll
121 * lock up on an APIC access.
123 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
125 cpuid
= smp_processor_id();
126 if (apic
->wait_for_init_deassert
&& cpuid
)
127 while (!atomic_read(&init_deasserted
))
131 * (This works even if the APIC is not enabled.)
133 phys_id
= read_apic_id();
136 * the boot CPU has finished the init stage and is spinning
137 * on callin_map until we finish. We are free to set up this
138 * CPU, first the APIC. (this is probably redundant on most
142 end_local_APIC_setup();
145 * Need to setup vector mappings before we enable interrupts.
147 setup_vector_irq(smp_processor_id());
150 * Save our processor parameters. Note: this information
151 * is needed for clock calibration.
153 smp_store_cpu_info(cpuid
);
157 * Update loops_per_jiffy in cpu_data. Previous call to
158 * smp_store_cpu_info() stored a value that is close but not as
159 * accurate as the value just calculated.
162 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
163 pr_debug("Stack at about %p\n", &cpuid
);
166 * This must be done before setting cpu_online_mask
167 * or calling notify_cpu_starting.
169 set_cpu_sibling_map(raw_smp_processor_id());
172 notify_cpu_starting(cpuid
);
175 * Allow the master to continue.
177 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
180 static int cpu0_logical_apicid
;
181 static int enable_start_cpu0
;
183 * Activate a secondary processor.
185 static void notrace
start_secondary(void *unused
)
188 * Don't put *anything* before cpu_init(), SMP booting is too
189 * fragile that we want to limit the things done here to the
190 * most necessary things.
193 x86_cpuinit
.early_percpu_clock_init();
197 enable_start_cpu0
= 0;
200 /* switch away from the initial page table */
201 load_cr3(swapper_pg_dir
);
205 /* otherwise gcc will move up smp_processor_id before the cpu_init */
208 * Check TSC synchronization with the BP:
210 check_tsc_sync_target();
213 * Enable the espfix hack for this CPU
215 #ifdef CONFIG_X86_ESPFIX64
220 * We need to hold vector_lock so there the set of online cpus
221 * does not change while we are assigning vectors to cpus. Holding
222 * this lock ensures we don't half assign or remove an irq from a cpu.
225 set_cpu_online(smp_processor_id(), true);
226 unlock_vector_lock();
227 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
228 x86_platform
.nmi_init();
230 /* enable local interrupts */
233 /* to prevent fake stack check failure in clock setup */
234 boot_init_stack_canary();
236 x86_cpuinit
.setup_percpu_clockev();
239 cpu_startup_entry(CPUHP_ONLINE
);
242 void __init
smp_store_boot_cpu_info(void)
244 int id
= 0; /* CPU 0 */
245 struct cpuinfo_x86
*c
= &cpu_data(id
);
252 * The bootstrap kernel entry code has set these up. Save them for
255 void smp_store_cpu_info(int id
)
257 struct cpuinfo_x86
*c
= &cpu_data(id
);
262 * During boot time, CPU0 has this setup already. Save the info when
263 * bringing up AP or offlined CPU0.
265 identify_secondary_cpu(c
);
269 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
271 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
273 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
277 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
279 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
281 return !WARN_ONCE(!topology_same_node(c
, o
),
282 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
283 "[node: %d != %d]. Ignoring dependency.\n",
284 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
287 #define link_mask(_m, c1, c2) \
289 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
290 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
293 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
295 if (cpu_has_topoext
) {
296 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
298 if (c
->phys_proc_id
== o
->phys_proc_id
&&
299 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
300 c
->compute_unit_id
== o
->compute_unit_id
)
301 return topology_sane(c
, o
, "smt");
303 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
304 c
->cpu_core_id
== o
->cpu_core_id
) {
305 return topology_sane(c
, o
, "smt");
311 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
313 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
315 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
316 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
317 return topology_sane(c
, o
, "llc");
323 * Unlike the other levels, we do not enforce keeping a
324 * multicore group inside a NUMA node. If this happens, we will
325 * discard the MC level of the topology later.
327 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
329 if (c
->phys_proc_id
== o
->phys_proc_id
)
334 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
335 #ifdef CONFIG_SCHED_SMT
336 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
338 #ifdef CONFIG_SCHED_MC
339 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
344 * set_sched_topology() sets the topology internal to a CPU. The
345 * NUMA topologies are layered on top of it to build the full
348 * If NUMA nodes are observed to occur within a CPU package, this
349 * function should be called. It forces the sched domain code to
350 * only use the SMT level for the CPU portion of the topology.
351 * This essentially falls back to relying on NUMA information
352 * from the SRAT table to describe the entire system topology
353 * (except for hyperthreads).
355 static void primarily_use_numa_for_topology(void)
357 set_sched_topology(numa_inside_package_topology
);
360 void set_cpu_sibling_map(int cpu
)
362 bool has_smt
= smp_num_siblings
> 1;
363 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
364 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
365 struct cpuinfo_x86
*o
;
368 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
371 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
372 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
373 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
378 for_each_cpu(i
, cpu_sibling_setup_mask
) {
381 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
382 link_mask(sibling
, cpu
, i
);
384 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
385 link_mask(llc_shared
, cpu
, i
);
390 * This needs a separate iteration over the cpus because we rely on all
391 * cpu_sibling_mask links to be set-up.
393 for_each_cpu(i
, cpu_sibling_setup_mask
) {
396 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
397 link_mask(core
, cpu
, i
);
400 * Does this new cpu bringup a new core?
402 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
404 * for each core in package, increment
405 * the booted_cores for this new cpu
407 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
410 * increment the core count for all
411 * the other cpus in this package
414 cpu_data(i
).booted_cores
++;
415 } else if (i
!= cpu
&& !c
->booted_cores
)
416 c
->booted_cores
= cpu_data(i
).booted_cores
;
418 if (match_die(c
, o
) && !topology_same_node(c
, o
))
419 primarily_use_numa_for_topology();
423 /* maps the cpu to the sched domain representing multi-core */
424 const struct cpumask
*cpu_coregroup_mask(int cpu
)
426 return cpu_llc_shared_mask(cpu
);
429 static void impress_friends(void)
432 unsigned long bogosum
= 0;
434 * Allow the user to impress friends.
436 pr_debug("Before bogomips\n");
437 for_each_possible_cpu(cpu
)
438 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
439 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
440 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
443 (bogosum
/(5000/HZ
))%100);
445 pr_debug("Before bogocount - setting activated=1\n");
448 void __inquire_remote_apic(int apicid
)
450 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
451 const char * const names
[] = { "ID", "VERSION", "SPIV" };
455 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
457 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
458 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
463 status
= safe_apic_wait_icr_idle();
465 pr_cont("a previous APIC delivery may have failed\n");
467 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
472 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
473 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
476 case APIC_ICR_RR_VALID
:
477 status
= apic_read(APIC_RRR
);
478 pr_cont("%08x\n", status
);
487 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
488 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
489 * won't ... remember to clear down the APIC, etc later.
492 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
494 unsigned long send_status
, accept_status
= 0;
498 /* Boot on the stack */
499 /* Kick the second */
500 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
502 pr_debug("Waiting for send to finish...\n");
503 send_status
= safe_apic_wait_icr_idle();
506 * Give the other CPU some time to accept the IPI.
509 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
510 maxlvt
= lapic_get_maxlvt();
511 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
512 apic_write(APIC_ESR
, 0);
513 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
515 pr_debug("NMI sent\n");
518 pr_err("APIC never delivered???\n");
520 pr_err("APIC delivery error (%lx)\n", accept_status
);
522 return (send_status
| accept_status
);
526 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
528 unsigned long send_status
, accept_status
= 0;
529 int maxlvt
, num_starts
, j
;
531 maxlvt
= lapic_get_maxlvt();
534 * Be paranoid about clearing APIC errors.
536 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
537 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
538 apic_write(APIC_ESR
, 0);
542 pr_debug("Asserting INIT\n");
545 * Turn INIT on target chip
550 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
553 pr_debug("Waiting for send to finish...\n");
554 send_status
= safe_apic_wait_icr_idle();
558 pr_debug("Deasserting INIT\n");
562 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
564 pr_debug("Waiting for send to finish...\n");
565 send_status
= safe_apic_wait_icr_idle();
568 atomic_set(&init_deasserted
, 1);
571 * Should we send STARTUP IPIs ?
573 * Determine this based on the APIC version.
574 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
576 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
582 * Paravirt / VMI wants a startup IPI hook here to set up the
583 * target processor state.
585 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
589 * Run STARTUP IPI loop.
591 pr_debug("#startup loops: %d\n", num_starts
);
593 for (j
= 1; j
<= num_starts
; j
++) {
594 pr_debug("Sending STARTUP #%d\n", j
);
595 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
596 apic_write(APIC_ESR
, 0);
598 pr_debug("After apic_write\n");
605 /* Boot on the stack */
606 /* Kick the second */
607 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
611 * Give the other CPU some time to accept the IPI.
615 pr_debug("Startup point 1\n");
617 pr_debug("Waiting for send to finish...\n");
618 send_status
= safe_apic_wait_icr_idle();
621 * Give the other CPU some time to accept the IPI.
624 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
625 apic_write(APIC_ESR
, 0);
626 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
627 if (send_status
|| accept_status
)
630 pr_debug("After Startup\n");
633 pr_err("APIC never delivered???\n");
635 pr_err("APIC delivery error (%lx)\n", accept_status
);
637 return (send_status
| accept_status
);
640 void smp_announce(void)
642 int num_nodes
= num_online_nodes();
644 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
645 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
648 /* reduce the number of lines printed when booting a large cpu count system */
649 static void announce_cpu(int cpu
, int apicid
)
651 static int current_node
= -1;
652 int node
= early_cpu_to_node(cpu
);
653 static int width
, node_width
;
656 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
659 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
662 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
664 if (system_state
== SYSTEM_BOOTING
) {
665 if (node
!= current_node
) {
666 if (current_node
> (-1))
670 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
671 node_width
- num_digits(node
), " ", node
);
674 /* Add padding for the BSP */
676 pr_cont("%*s", width
+ 1, " ");
678 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
681 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
685 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
689 cpu
= smp_processor_id();
690 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
697 * Wake up AP by INIT, INIT, STARTUP sequence.
699 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
700 * boot-strap code which is not a desired behavior for waking up BSP. To
701 * void the boot-strap code, wake up CPU0 by NMI instead.
703 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
704 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
705 * We'll change this code in the future to wake up hard offlined CPU0 if
706 * real platform and request are available.
709 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
710 int *cpu0_nmi_registered
)
718 * Wake up AP by INIT, INIT, STARTUP sequence.
721 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
726 * Wake up BSP by nmi.
728 * Register a NMI handler to help wake up CPU0.
730 boot_error
= register_nmi_handler(NMI_LOCAL
,
731 wakeup_cpu0_nmi
, 0, "wake_cpu0");
734 enable_start_cpu0
= 1;
735 *cpu0_nmi_registered
= 1;
736 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
737 id
= cpu0_logical_apicid
;
740 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
750 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
751 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
752 * Returns zero if CPU booted OK, else error code from
753 * ->wakeup_secondary_cpu.
755 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
757 volatile u32
*trampoline_status
=
758 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
759 /* start_ip had better be page-aligned! */
760 unsigned long start_ip
= real_mode_header
->trampoline_start
;
762 unsigned long boot_error
= 0;
763 int cpu0_nmi_registered
= 0;
764 unsigned long timeout
;
766 /* Just in case we booted with a single CPU. */
767 alternatives_enable_smp();
769 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
770 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
771 per_cpu(current_task
, cpu
) = idle
;
774 /* Stack for startup_32 can be just as for start_secondary onwards */
777 clear_tsk_thread_flag(idle
, TIF_FORK
);
778 initial_gs
= per_cpu_offset(cpu
);
780 per_cpu(kernel_stack
, cpu
) =
781 (unsigned long)task_stack_page(idle
) -
782 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
783 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
784 initial_code
= (unsigned long)start_secondary
;
785 stack_start
= idle
->thread
.sp
;
787 /* So we see what's up */
788 announce_cpu(cpu
, apicid
);
791 * This grunge runs the startup process for
792 * the targeted processor.
795 atomic_set(&init_deasserted
, 0);
797 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
799 pr_debug("Setting warm reset code and vector.\n");
801 smpboot_setup_warm_reset_vector(start_ip
);
803 * Be paranoid about clearing APIC errors.
805 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
806 apic_write(APIC_ESR
, 0);
812 * AP might wait on cpu_callout_mask in cpu_init() with
813 * cpu_initialized_mask set if previous attempt to online
814 * it timed-out. Clear cpu_initialized_mask so that after
815 * INIT/SIPI it could start with a clean state.
817 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
821 * Wake up a CPU in difference cases:
822 * - Use the method in the APIC driver if it's defined
824 * - Use an INIT boot APIC message for APs or NMI for BSP.
826 if (apic
->wakeup_secondary_cpu
)
827 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
829 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
830 &cpu0_nmi_registered
);
834 * Wait 10s total for a response from AP
837 timeout
= jiffies
+ 10*HZ
;
838 while (time_before(jiffies
, timeout
)) {
839 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
841 * Tell AP to proceed with initialization
843 cpumask_set_cpu(cpu
, cpu_callout_mask
);
854 * Wait till AP completes initial initialization
856 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
858 * Allow other tasks to run while we wait for the
859 * AP to come online. This also gives a chance
860 * for the MTRR work(triggered by the AP coming online)
861 * to be completed in the stop machine context.
868 /* mark "stuck" area as not stuck */
869 *trampoline_status
= 0;
871 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
873 * Cleanup possible dangling ends...
875 smpboot_restore_warm_reset_vector();
878 * Clean up the nmi handler. Do this after the callin and callout sync
879 * to avoid impact of possible long unregister time.
881 if (cpu0_nmi_registered
)
882 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
887 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
889 int apicid
= apic
->cpu_present_to_apicid(cpu
);
893 WARN_ON(irqs_disabled());
895 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
897 if (apicid
== BAD_APICID
||
898 !physid_isset(apicid
, phys_cpu_present_map
) ||
899 !apic
->apic_id_valid(apicid
)) {
900 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
905 * Already booted CPU?
907 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
908 pr_debug("do_boot_cpu %d Already started\n", cpu
);
913 * Save current MTRR state in case it was changed since early boot
914 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
918 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
920 /* the FPU context is blank, nobody can own it */
921 __cpu_disable_lazy_restore(cpu
);
923 err
= do_boot_cpu(apicid
, cpu
, tidle
);
925 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
930 * Check TSC synchronization with the AP (keep irqs disabled
933 local_irq_save(flags
);
934 check_tsc_sync_source(cpu
);
935 local_irq_restore(flags
);
937 while (!cpu_online(cpu
)) {
939 touch_nmi_watchdog();
946 * arch_disable_smp_support() - disables SMP support for x86 at runtime
948 void arch_disable_smp_support(void)
950 disable_ioapic_support();
954 * Fall back to non SMP mode after errors.
956 * RED-PEN audit/test this more. I bet there is more state messed up here.
958 static __init
void disable_smp(void)
960 init_cpu_present(cpumask_of(0));
961 init_cpu_possible(cpumask_of(0));
962 smpboot_clear_io_apic_irqs();
964 if (smp_found_config
)
965 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
967 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
968 cpumask_set_cpu(0, cpu_sibling_mask(0));
969 cpumask_set_cpu(0, cpu_core_mask(0));
973 * Various sanity checks.
975 static int __init
smp_sanity_check(unsigned max_cpus
)
979 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
980 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
984 pr_warn("More than 8 CPUs detected - skipping them\n"
985 "Use CONFIG_X86_BIGSMP\n");
988 for_each_present_cpu(cpu
) {
990 set_cpu_present(cpu
, false);
995 for_each_possible_cpu(cpu
) {
997 set_cpu_possible(cpu
, false);
1005 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1006 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1007 hard_smp_processor_id());
1009 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1013 * If we couldn't find an SMP configuration at boot time,
1014 * get out of here now!
1016 if (!smp_found_config
&& !acpi_lapic
) {
1018 pr_notice("SMP motherboard not detected\n");
1020 if (APIC_init_uniprocessor())
1021 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1026 * Should not be necessary because the MP table should list the boot
1027 * CPU too, but we do it for the sake of robustness anyway.
1029 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1030 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1031 boot_cpu_physical_apicid
);
1032 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1037 * If we couldn't find a local APIC, then get out of here now!
1039 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1041 if (!disable_apic
) {
1042 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1043 boot_cpu_physical_apicid
);
1044 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1046 smpboot_clear_io_apic();
1047 disable_ioapic_support();
1051 verify_local_APIC();
1054 * If SMP should be disabled, then really disable it!
1057 pr_info("SMP mode deactivated\n");
1058 smpboot_clear_io_apic();
1062 bsp_end_local_APIC_setup();
1069 static void __init
smp_cpu_index_default(void)
1072 struct cpuinfo_x86
*c
;
1074 for_each_possible_cpu(i
) {
1076 /* mark all to hotplug */
1077 c
->cpu_index
= nr_cpu_ids
;
1082 * Prepare for SMP bootup. The MP table or ACPI has been read
1083 * earlier. Just do some sanity checking here and enable APIC mode.
1085 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1090 smp_cpu_index_default();
1093 * Setup boot CPU information
1095 smp_store_boot_cpu_info(); /* Final full version of the data */
1096 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1099 current_thread_info()->cpu
= 0; /* needed? */
1100 for_each_possible_cpu(i
) {
1101 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1102 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1103 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1105 set_cpu_sibling_map(0);
1108 if (smp_sanity_check(max_cpus
) < 0) {
1109 pr_info("SMP disabled\n");
1114 default_setup_apic_routing();
1117 if (read_apic_id() != boot_cpu_physical_apicid
) {
1118 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1119 read_apic_id(), boot_cpu_physical_apicid
);
1120 /* Or can we switch back to PIC here? */
1127 * Switch from PIC to APIC mode.
1132 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1134 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1137 * Enable IO APIC before setting up error vector
1139 if (!skip_ioapic_setup
&& nr_ioapics
)
1142 bsp_end_local_APIC_setup();
1143 smpboot_setup_io_apic();
1145 * Set up local APIC timer on boot CPU.
1148 pr_info("CPU%d: ", 0);
1149 print_cpu_info(&cpu_data(0));
1150 x86_init
.timers
.setup_percpu_clockev();
1155 set_mtrr_aps_delayed_init();
1160 void arch_enable_nonboot_cpus_begin(void)
1162 set_mtrr_aps_delayed_init();
1165 void arch_enable_nonboot_cpus_end(void)
1171 * Early setup to make printk work.
1173 void __init
native_smp_prepare_boot_cpu(void)
1175 int me
= smp_processor_id();
1176 switch_to_new_gdt(me
);
1177 /* already set me in cpu_online_mask in boot_cpu_init() */
1178 cpumask_set_cpu(me
, cpu_callout_mask
);
1179 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1182 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1184 pr_debug("Boot done\n");
1188 #ifdef CONFIG_X86_IO_APIC
1189 setup_ioapic_dest();
1194 static int __initdata setup_possible_cpus
= -1;
1195 static int __init
_setup_possible_cpus(char *str
)
1197 get_option(&str
, &setup_possible_cpus
);
1200 early_param("possible_cpus", _setup_possible_cpus
);
1204 * cpu_possible_mask should be static, it cannot change as cpu's
1205 * are onlined, or offlined. The reason is per-cpu data-structures
1206 * are allocated by some modules at init time, and dont expect to
1207 * do this dynamically on cpu arrival/departure.
1208 * cpu_present_mask on the other hand can change dynamically.
1209 * In case when cpu_hotplug is not compiled, then we resort to current
1210 * behaviour, which is cpu_possible == cpu_present.
1213 * Three ways to find out the number of additional hotplug CPUs:
1214 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1215 * - The user can overwrite it with possible_cpus=NUM
1216 * - Otherwise don't reserve additional CPUs.
1217 * We do this because additional CPUs waste a lot of memory.
1220 __init
void prefill_possible_map(void)
1224 /* no processor from mptable or madt */
1225 if (!num_processors
)
1228 i
= setup_max_cpus
?: 1;
1229 if (setup_possible_cpus
== -1) {
1230 possible
= num_processors
;
1231 #ifdef CONFIG_HOTPLUG_CPU
1233 possible
+= disabled_cpus
;
1239 possible
= setup_possible_cpus
;
1241 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1243 /* nr_cpu_ids could be reduced via nr_cpus= */
1244 if (possible
> nr_cpu_ids
) {
1245 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1246 possible
, nr_cpu_ids
);
1247 possible
= nr_cpu_ids
;
1250 #ifdef CONFIG_HOTPLUG_CPU
1251 if (!setup_max_cpus
)
1254 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1255 possible
, setup_max_cpus
);
1259 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1260 possible
, max_t(int, possible
- num_processors
, 0));
1262 for (i
= 0; i
< possible
; i
++)
1263 set_cpu_possible(i
, true);
1264 for (; i
< NR_CPUS
; i
++)
1265 set_cpu_possible(i
, false);
1267 nr_cpu_ids
= possible
;
1270 #ifdef CONFIG_HOTPLUG_CPU
1272 static void remove_siblinginfo(int cpu
)
1275 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1277 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1278 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1280 * last thread sibling in this cpu core going down
1282 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1283 cpu_data(sibling
).booted_cores
--;
1286 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1287 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1288 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1289 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1290 cpumask_clear(cpu_llc_shared_mask(cpu
));
1291 cpumask_clear(cpu_sibling_mask(cpu
));
1292 cpumask_clear(cpu_core_mask(cpu
));
1293 c
->phys_proc_id
= 0;
1295 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1298 static void __ref
remove_cpu_from_maps(int cpu
)
1300 set_cpu_online(cpu
, false);
1301 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1302 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1303 /* was set by cpu_init() */
1304 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1305 numa_remove_cpu(cpu
);
1308 void cpu_disable_common(void)
1310 int cpu
= smp_processor_id();
1312 remove_siblinginfo(cpu
);
1314 /* It's now safe to remove this processor from the online map */
1316 remove_cpu_from_maps(cpu
);
1317 unlock_vector_lock();
1321 int native_cpu_disable(void)
1325 ret
= check_irq_vectors_for_cpu_disable();
1330 init_completion(&per_cpu(die_complete
, smp_processor_id()));
1331 cpu_disable_common();
1336 void native_cpu_die(unsigned int cpu
)
1338 /* We don't do anything here: idle task is faking death itself. */
1339 wait_for_completion_timeout(&per_cpu(die_complete
, cpu
), HZ
);
1341 /* They ack this in play_dead() by setting CPU_DEAD */
1342 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1343 if (system_state
== SYSTEM_RUNNING
)
1344 pr_info("CPU %u is now offline\n", cpu
);
1346 pr_err("CPU %u didn't die...\n", cpu
);
1350 void play_dead_common(void)
1353 reset_lazy_tlbstate();
1354 amd_e400_remove_cpu(raw_smp_processor_id());
1358 __this_cpu_write(cpu_state
, CPU_DEAD
);
1359 complete(&per_cpu(die_complete
, smp_processor_id()));
1362 * With physical CPU hotplug, we should halt the cpu
1364 local_irq_disable();
1367 static bool wakeup_cpu0(void)
1369 if (smp_processor_id() == 0 && enable_start_cpu0
)
1376 * We need to flush the caches before going to sleep, lest we have
1377 * dirty data in our caches when we come back up.
1379 static inline void mwait_play_dead(void)
1381 unsigned int eax
, ebx
, ecx
, edx
;
1382 unsigned int highest_cstate
= 0;
1383 unsigned int highest_subcstate
= 0;
1387 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1389 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1391 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1394 eax
= CPUID_MWAIT_LEAF
;
1396 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1399 * eax will be 0 if EDX enumeration is not valid.
1400 * Initialized below to cstate, sub_cstate value when EDX is valid.
1402 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1405 edx
>>= MWAIT_SUBSTATE_SIZE
;
1406 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1407 if (edx
& MWAIT_SUBSTATE_MASK
) {
1409 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1412 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1413 (highest_subcstate
- 1);
1417 * This should be a memory location in a cache line which is
1418 * unlikely to be touched by other processors. The actual
1419 * content is immaterial as it is not actually modified in any way.
1421 mwait_ptr
= ¤t_thread_info()->flags
;
1427 * The CLFLUSH is a workaround for erratum AAI65 for
1428 * the Xeon 7400 series. It's not clear it is actually
1429 * needed, but it should be harmless in either case.
1430 * The WBINVD is insufficient due to the spurious-wakeup
1431 * case where we return around the loop.
1436 __monitor(mwait_ptr
, 0, 0);
1440 * If NMI wants to wake up CPU0, start CPU0.
1447 static inline void hlt_play_dead(void)
1449 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1455 * If NMI wants to wake up CPU0, start CPU0.
1462 void native_play_dead(void)
1465 tboot_shutdown(TB_SHUTDOWN_WFS
);
1467 mwait_play_dead(); /* Only returns on failure */
1468 if (cpuidle_play_dead())
1472 #else /* ... !CONFIG_HOTPLUG_CPU */
1473 int native_cpu_disable(void)
1478 void native_cpu_die(unsigned int cpu
)
1480 /* We said "no" in __cpu_disable */
1484 void native_play_dead(void)