2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
77 #include <asm/realmode.h>
80 /* Number of siblings per CPU package */
81 int smp_num_siblings
= 1;
82 EXPORT_SYMBOL(smp_num_siblings
);
84 /* Last level cache ID of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
87 /* representing HT siblings of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
91 /* representing HT and core siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
93 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
97 /* Per CPU bogomips and other parameters */
98 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
99 EXPORT_PER_CPU_SYMBOL(cpu_info
);
101 atomic_t init_deasserted
;
103 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
107 spin_lock_irqsave(&rtc_lock
, flags
);
108 CMOS_WRITE(0xa, 0xf);
109 spin_unlock_irqrestore(&rtc_lock
, flags
);
112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
115 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
120 static inline void smpboot_restore_warm_reset_vector(void)
125 * Install writable page 0 entry to set BIOS data area.
130 * Paranoid: Set warm reset code and vector here back
133 spin_lock_irqsave(&rtc_lock
, flags
);
135 spin_unlock_irqrestore(&rtc_lock
, flags
);
137 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
141 * Report back to the Boot Processor during boot time or to the caller processor
144 static void smp_callin(void)
149 * If waken up by an INIT in an 82489DX configuration
150 * we may get here before an INIT-deassert IPI reaches
151 * our local APIC. We have to wait for the IPI or we'll
152 * lock up on an APIC access.
154 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
156 cpuid
= smp_processor_id();
157 if (apic
->wait_for_init_deassert
&& cpuid
)
158 while (!atomic_read(&init_deasserted
))
162 * (This works even if the APIC is not enabled.)
164 phys_id
= read_apic_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Need to setup vector mappings before we enable interrupts.
177 setup_vector_irq(smp_processor_id());
180 * Save our processor parameters. Note: this information
181 * is needed for clock calibration.
183 smp_store_cpu_info(cpuid
);
187 * Update loops_per_jiffy in cpu_data. Previous call to
188 * smp_store_cpu_info() stored a value that is close but not as
189 * accurate as the value just calculated.
192 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
193 pr_debug("Stack at about %p\n", &cpuid
);
196 * This must be done before setting cpu_online_mask
197 * or calling notify_cpu_starting.
199 set_cpu_sibling_map(raw_smp_processor_id());
202 notify_cpu_starting(cpuid
);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
210 static int cpu0_logical_apicid
;
211 static int enable_start_cpu0
;
213 * Activate a secondary processor.
215 static void notrace
start_secondary(void *unused
)
218 * Don't put *anything* before cpu_init(), SMP booting is too
219 * fragile that we want to limit the things done here to the
220 * most necessary things.
223 x86_cpuinit
.early_percpu_clock_init();
227 enable_start_cpu0
= 0;
230 /* switch away from the initial page table */
231 load_cr3(swapper_pg_dir
);
235 /* otherwise gcc will move up smp_processor_id before the cpu_init */
238 * Check TSC synchronization with the BP:
240 check_tsc_sync_target();
243 * Enable the espfix hack for this CPU
245 #ifdef CONFIG_X86_ESPFIX64
250 * We need to hold vector_lock so there the set of online cpus
251 * does not change while we are assigning vectors to cpus. Holding
252 * this lock ensures we don't half assign or remove an irq from a cpu.
255 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 cpu_set_state_online(smp_processor_id());
258 x86_platform
.nmi_init();
260 /* enable local interrupts */
263 /* to prevent fake stack check failure in clock setup */
264 boot_init_stack_canary();
266 x86_cpuinit
.setup_percpu_clockev();
269 cpu_startup_entry(CPUHP_ONLINE
);
272 void __init
smp_store_boot_cpu_info(void)
274 int id
= 0; /* CPU 0 */
275 struct cpuinfo_x86
*c
= &cpu_data(id
);
282 * The bootstrap kernel entry code has set these up. Save them for
285 void smp_store_cpu_info(int id
)
287 struct cpuinfo_x86
*c
= &cpu_data(id
);
292 * During boot time, CPU0 has this setup already. Save the info when
293 * bringing up AP or offlined CPU0.
295 identify_secondary_cpu(c
);
299 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
301 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
303 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
307 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
309 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
311 return !WARN_ONCE(!topology_same_node(c
, o
),
312 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
313 "[node: %d != %d]. Ignoring dependency.\n",
314 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
317 #define link_mask(_m, c1, c2) \
319 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
320 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
323 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
325 if (cpu_has_topoext
) {
326 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
328 if (c
->phys_proc_id
== o
->phys_proc_id
&&
329 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
330 c
->compute_unit_id
== o
->compute_unit_id
)
331 return topology_sane(c
, o
, "smt");
333 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
334 c
->cpu_core_id
== o
->cpu_core_id
) {
335 return topology_sane(c
, o
, "smt");
341 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
343 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
345 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
346 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
347 return topology_sane(c
, o
, "llc");
353 * Unlike the other levels, we do not enforce keeping a
354 * multicore group inside a NUMA node. If this happens, we will
355 * discard the MC level of the topology later.
357 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
359 if (c
->phys_proc_id
== o
->phys_proc_id
)
364 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
365 #ifdef CONFIG_SCHED_SMT
366 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
368 #ifdef CONFIG_SCHED_MC
369 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
374 * set_sched_topology() sets the topology internal to a CPU. The
375 * NUMA topologies are layered on top of it to build the full
378 * If NUMA nodes are observed to occur within a CPU package, this
379 * function should be called. It forces the sched domain code to
380 * only use the SMT level for the CPU portion of the topology.
381 * This essentially falls back to relying on NUMA information
382 * from the SRAT table to describe the entire system topology
383 * (except for hyperthreads).
385 static void primarily_use_numa_for_topology(void)
387 set_sched_topology(numa_inside_package_topology
);
390 void set_cpu_sibling_map(int cpu
)
392 bool has_smt
= smp_num_siblings
> 1;
393 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
394 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
395 struct cpuinfo_x86
*o
;
398 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
401 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
402 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
403 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
408 for_each_cpu(i
, cpu_sibling_setup_mask
) {
411 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
412 link_mask(sibling
, cpu
, i
);
414 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
415 link_mask(llc_shared
, cpu
, i
);
420 * This needs a separate iteration over the cpus because we rely on all
421 * cpu_sibling_mask links to be set-up.
423 for_each_cpu(i
, cpu_sibling_setup_mask
) {
426 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
427 link_mask(core
, cpu
, i
);
430 * Does this new cpu bringup a new core?
432 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
434 * for each core in package, increment
435 * the booted_cores for this new cpu
437 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
440 * increment the core count for all
441 * the other cpus in this package
444 cpu_data(i
).booted_cores
++;
445 } else if (i
!= cpu
&& !c
->booted_cores
)
446 c
->booted_cores
= cpu_data(i
).booted_cores
;
448 if (match_die(c
, o
) && !topology_same_node(c
, o
))
449 primarily_use_numa_for_topology();
453 /* maps the cpu to the sched domain representing multi-core */
454 const struct cpumask
*cpu_coregroup_mask(int cpu
)
456 return cpu_llc_shared_mask(cpu
);
459 static void impress_friends(void)
462 unsigned long bogosum
= 0;
464 * Allow the user to impress friends.
466 pr_debug("Before bogomips\n");
467 for_each_possible_cpu(cpu
)
468 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
469 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
470 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
473 (bogosum
/(5000/HZ
))%100);
475 pr_debug("Before bogocount - setting activated=1\n");
478 void __inquire_remote_apic(int apicid
)
480 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
481 const char * const names
[] = { "ID", "VERSION", "SPIV" };
485 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
487 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
488 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
493 status
= safe_apic_wait_icr_idle();
495 pr_cont("a previous APIC delivery may have failed\n");
497 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
502 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
503 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
506 case APIC_ICR_RR_VALID
:
507 status
= apic_read(APIC_RRR
);
508 pr_cont("%08x\n", status
);
517 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
518 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
519 * won't ... remember to clear down the APIC, etc later.
522 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
524 unsigned long send_status
, accept_status
= 0;
528 /* Boot on the stack */
529 /* Kick the second */
530 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
532 pr_debug("Waiting for send to finish...\n");
533 send_status
= safe_apic_wait_icr_idle();
536 * Give the other CPU some time to accept the IPI.
539 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
540 maxlvt
= lapic_get_maxlvt();
541 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
542 apic_write(APIC_ESR
, 0);
543 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
545 pr_debug("NMI sent\n");
548 pr_err("APIC never delivered???\n");
550 pr_err("APIC delivery error (%lx)\n", accept_status
);
552 return (send_status
| accept_status
);
556 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
558 unsigned long send_status
= 0, accept_status
= 0;
559 int maxlvt
, num_starts
, j
;
561 maxlvt
= lapic_get_maxlvt();
564 * Be paranoid about clearing APIC errors.
566 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
567 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
568 apic_write(APIC_ESR
, 0);
572 pr_debug("Asserting INIT\n");
575 * Turn INIT on target chip
580 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
583 if (!cpu_has_x2apic
) {
584 pr_debug("Waiting for send to finish...\n");
585 send_status
= safe_apic_wait_icr_idle();
589 pr_debug("Deasserting INIT\n");
593 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
595 pr_debug("Waiting for send to finish...\n");
596 send_status
= safe_apic_wait_icr_idle();
599 atomic_set(&init_deasserted
, 1);
600 } else if (tboot_enabled()) {
602 * With tboot AP is actually spinning in a mini-guest before
603 * receiving INIT. Upon receiving INIT ipi, AP need time to
604 * VMExit, update VMCS to tracking SIPIs and VMResume.
606 * While AP is in root mode handling the INIT the CPU will drop
613 * Should we send STARTUP IPIs ?
615 * Determine this based on the APIC version.
616 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
618 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
624 * Paravirt / VMI wants a startup IPI hook here to set up the
625 * target processor state.
627 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
631 * Run STARTUP IPI loop.
633 pr_debug("#startup loops: %d\n", num_starts
);
635 for (j
= 1; j
<= num_starts
; j
++) {
636 pr_debug("Sending STARTUP #%d\n", j
);
637 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
638 apic_write(APIC_ESR
, 0);
640 pr_debug("After apic_write\n");
647 /* Boot on the stack */
648 /* Kick the second */
649 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
652 if (!cpu_has_x2apic
) {
654 * Give the other CPU some time to accept the IPI.
658 pr_debug("Startup point 1\n");
660 pr_debug("Waiting for send to finish...\n");
661 send_status
= safe_apic_wait_icr_idle();
664 * Give the other CPU some time to accept the IPI.
669 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
670 apic_write(APIC_ESR
, 0);
671 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
672 if (send_status
|| accept_status
)
675 pr_debug("After Startup\n");
678 pr_err("APIC never delivered???\n");
680 pr_err("APIC delivery error (%lx)\n", accept_status
);
682 return (send_status
| accept_status
);
685 void smp_announce(void)
687 int num_nodes
= num_online_nodes();
689 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
690 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
693 /* reduce the number of lines printed when booting a large cpu count system */
694 static void announce_cpu(int cpu
, int apicid
)
696 static int current_node
= -1;
697 int node
= early_cpu_to_node(cpu
);
698 static int width
, node_width
;
701 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
704 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
707 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
709 if (system_state
== SYSTEM_BOOTING
) {
710 if (node
!= current_node
) {
711 if (current_node
> (-1))
715 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
716 node_width
- num_digits(node
), " ", node
);
719 /* Add padding for the BSP */
721 pr_cont("%*s", width
+ 1, " ");
723 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
726 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
730 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
734 cpu
= smp_processor_id();
735 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
742 * Wake up AP by INIT, INIT, STARTUP sequence.
744 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
745 * boot-strap code which is not a desired behavior for waking up BSP. To
746 * void the boot-strap code, wake up CPU0 by NMI instead.
748 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
749 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
750 * We'll change this code in the future to wake up hard offlined CPU0 if
751 * real platform and request are available.
754 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
755 int *cpu0_nmi_registered
)
763 * Wake up AP by INIT, INIT, STARTUP sequence.
766 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
771 * Wake up BSP by nmi.
773 * Register a NMI handler to help wake up CPU0.
775 boot_error
= register_nmi_handler(NMI_LOCAL
,
776 wakeup_cpu0_nmi
, 0, "wake_cpu0");
779 enable_start_cpu0
= 1;
780 *cpu0_nmi_registered
= 1;
781 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
782 id
= cpu0_logical_apicid
;
785 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
794 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
796 /* Just in case we booted with a single CPU. */
797 alternatives_enable_smp();
799 per_cpu(current_task
, cpu
) = idle
;
802 /* Stack for startup_32 can be just as for start_secondary onwards */
804 per_cpu(cpu_current_top_of_stack
, cpu
) =
805 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
807 clear_tsk_thread_flag(idle
, TIF_FORK
);
808 initial_gs
= per_cpu_offset(cpu
);
810 per_cpu(kernel_stack
, cpu
) =
811 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
815 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
816 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
817 * Returns zero if CPU booted OK, else error code from
818 * ->wakeup_secondary_cpu.
820 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
822 volatile u32
*trampoline_status
=
823 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
824 /* start_ip had better be page-aligned! */
825 unsigned long start_ip
= real_mode_header
->trampoline_start
;
827 unsigned long boot_error
= 0;
828 int cpu0_nmi_registered
= 0;
829 unsigned long timeout
;
831 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
832 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
834 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
835 initial_code
= (unsigned long)start_secondary
;
836 stack_start
= idle
->thread
.sp
;
838 /* So we see what's up */
839 announce_cpu(cpu
, apicid
);
842 * This grunge runs the startup process for
843 * the targeted processor.
846 atomic_set(&init_deasserted
, 0);
848 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
850 pr_debug("Setting warm reset code and vector.\n");
852 smpboot_setup_warm_reset_vector(start_ip
);
854 * Be paranoid about clearing APIC errors.
856 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
857 apic_write(APIC_ESR
, 0);
863 * AP might wait on cpu_callout_mask in cpu_init() with
864 * cpu_initialized_mask set if previous attempt to online
865 * it timed-out. Clear cpu_initialized_mask so that after
866 * INIT/SIPI it could start with a clean state.
868 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
872 * Wake up a CPU in difference cases:
873 * - Use the method in the APIC driver if it's defined
875 * - Use an INIT boot APIC message for APs or NMI for BSP.
877 if (apic
->wakeup_secondary_cpu
)
878 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
880 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
881 &cpu0_nmi_registered
);
885 * Wait 10s total for a response from AP
888 timeout
= jiffies
+ 10*HZ
;
889 while (time_before(jiffies
, timeout
)) {
890 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
892 * Tell AP to proceed with initialization
894 cpumask_set_cpu(cpu
, cpu_callout_mask
);
905 * Wait till AP completes initial initialization
907 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
909 * Allow other tasks to run while we wait for the
910 * AP to come online. This also gives a chance
911 * for the MTRR work(triggered by the AP coming online)
912 * to be completed in the stop machine context.
919 /* mark "stuck" area as not stuck */
920 *trampoline_status
= 0;
922 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
924 * Cleanup possible dangling ends...
926 smpboot_restore_warm_reset_vector();
929 * Clean up the nmi handler. Do this after the callin and callout sync
930 * to avoid impact of possible long unregister time.
932 if (cpu0_nmi_registered
)
933 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
938 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
940 int apicid
= apic
->cpu_present_to_apicid(cpu
);
944 WARN_ON(irqs_disabled());
946 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
948 if (apicid
== BAD_APICID
||
949 !physid_isset(apicid
, phys_cpu_present_map
) ||
950 !apic
->apic_id_valid(apicid
)) {
951 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
956 * Already booted CPU?
958 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
959 pr_debug("do_boot_cpu %d Already started\n", cpu
);
964 * Save current MTRR state in case it was changed since early boot
965 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
969 /* x86 CPUs take themselves offline, so delayed offline is OK. */
970 err
= cpu_check_up_prepare(cpu
);
971 if (err
&& err
!= -EBUSY
)
974 /* the FPU context is blank, nobody can own it */
975 __cpu_disable_lazy_restore(cpu
);
977 common_cpu_up(cpu
, tidle
);
979 err
= do_boot_cpu(apicid
, cpu
, tidle
);
981 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
986 * Check TSC synchronization with the AP (keep irqs disabled
989 local_irq_save(flags
);
990 check_tsc_sync_source(cpu
);
991 local_irq_restore(flags
);
993 while (!cpu_online(cpu
)) {
995 touch_nmi_watchdog();
1002 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1004 void arch_disable_smp_support(void)
1006 disable_ioapic_support();
1010 * Fall back to non SMP mode after errors.
1012 * RED-PEN audit/test this more. I bet there is more state messed up here.
1014 static __init
void disable_smp(void)
1016 pr_info("SMP disabled\n");
1018 disable_ioapic_support();
1020 init_cpu_present(cpumask_of(0));
1021 init_cpu_possible(cpumask_of(0));
1023 if (smp_found_config
)
1024 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1026 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1027 cpumask_set_cpu(0, cpu_sibling_mask(0));
1028 cpumask_set_cpu(0, cpu_core_mask(0));
1039 * Various sanity checks.
1041 static int __init
smp_sanity_check(unsigned max_cpus
)
1045 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1046 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1050 pr_warn("More than 8 CPUs detected - skipping them\n"
1051 "Use CONFIG_X86_BIGSMP\n");
1054 for_each_present_cpu(cpu
) {
1056 set_cpu_present(cpu
, false);
1061 for_each_possible_cpu(cpu
) {
1063 set_cpu_possible(cpu
, false);
1071 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1072 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1073 hard_smp_processor_id());
1075 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1079 * If we couldn't find an SMP configuration at boot time,
1080 * get out of here now!
1082 if (!smp_found_config
&& !acpi_lapic
) {
1084 pr_notice("SMP motherboard not detected\n");
1085 return SMP_NO_CONFIG
;
1089 * Should not be necessary because the MP table should list the boot
1090 * CPU too, but we do it for the sake of robustness anyway.
1092 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1093 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1094 boot_cpu_physical_apicid
);
1095 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1100 * If we couldn't find a local APIC, then get out of here now!
1102 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1104 if (!disable_apic
) {
1105 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1106 boot_cpu_physical_apicid
);
1107 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1113 * If SMP should be disabled, then really disable it!
1116 pr_info("SMP mode deactivated\n");
1117 return SMP_FORCE_UP
;
1123 static void __init
smp_cpu_index_default(void)
1126 struct cpuinfo_x86
*c
;
1128 for_each_possible_cpu(i
) {
1130 /* mark all to hotplug */
1131 c
->cpu_index
= nr_cpu_ids
;
1136 * Prepare for SMP bootup. The MP table or ACPI has been read
1137 * earlier. Just do some sanity checking here and enable APIC mode.
1139 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1143 smp_cpu_index_default();
1146 * Setup boot CPU information
1148 smp_store_boot_cpu_info(); /* Final full version of the data */
1149 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1152 current_thread_info()->cpu
= 0; /* needed? */
1153 for_each_possible_cpu(i
) {
1154 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1155 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1156 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1158 set_cpu_sibling_map(0);
1160 switch (smp_sanity_check(max_cpus
)) {
1163 if (APIC_init_uniprocessor())
1164 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1171 apic_bsp_setup(false);
1177 default_setup_apic_routing();
1179 if (read_apic_id() != boot_cpu_physical_apicid
) {
1180 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1181 read_apic_id(), boot_cpu_physical_apicid
);
1182 /* Or can we switch back to PIC here? */
1185 cpu0_logical_apicid
= apic_bsp_setup(false);
1187 pr_info("CPU%d: ", 0);
1188 print_cpu_info(&cpu_data(0));
1193 set_mtrr_aps_delayed_init();
1196 void arch_enable_nonboot_cpus_begin(void)
1198 set_mtrr_aps_delayed_init();
1201 void arch_enable_nonboot_cpus_end(void)
1207 * Early setup to make printk work.
1209 void __init
native_smp_prepare_boot_cpu(void)
1211 int me
= smp_processor_id();
1212 switch_to_new_gdt(me
);
1213 /* already set me in cpu_online_mask in boot_cpu_init() */
1214 cpumask_set_cpu(me
, cpu_callout_mask
);
1215 cpu_set_state_online(me
);
1218 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1220 pr_debug("Boot done\n");
1224 setup_ioapic_dest();
1228 static int __initdata setup_possible_cpus
= -1;
1229 static int __init
_setup_possible_cpus(char *str
)
1231 get_option(&str
, &setup_possible_cpus
);
1234 early_param("possible_cpus", _setup_possible_cpus
);
1238 * cpu_possible_mask should be static, it cannot change as cpu's
1239 * are onlined, or offlined. The reason is per-cpu data-structures
1240 * are allocated by some modules at init time, and dont expect to
1241 * do this dynamically on cpu arrival/departure.
1242 * cpu_present_mask on the other hand can change dynamically.
1243 * In case when cpu_hotplug is not compiled, then we resort to current
1244 * behaviour, which is cpu_possible == cpu_present.
1247 * Three ways to find out the number of additional hotplug CPUs:
1248 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1249 * - The user can overwrite it with possible_cpus=NUM
1250 * - Otherwise don't reserve additional CPUs.
1251 * We do this because additional CPUs waste a lot of memory.
1254 __init
void prefill_possible_map(void)
1258 /* no processor from mptable or madt */
1259 if (!num_processors
)
1262 i
= setup_max_cpus
?: 1;
1263 if (setup_possible_cpus
== -1) {
1264 possible
= num_processors
;
1265 #ifdef CONFIG_HOTPLUG_CPU
1267 possible
+= disabled_cpus
;
1273 possible
= setup_possible_cpus
;
1275 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1277 /* nr_cpu_ids could be reduced via nr_cpus= */
1278 if (possible
> nr_cpu_ids
) {
1279 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1280 possible
, nr_cpu_ids
);
1281 possible
= nr_cpu_ids
;
1284 #ifdef CONFIG_HOTPLUG_CPU
1285 if (!setup_max_cpus
)
1288 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1289 possible
, setup_max_cpus
);
1293 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1294 possible
, max_t(int, possible
- num_processors
, 0));
1296 for (i
= 0; i
< possible
; i
++)
1297 set_cpu_possible(i
, true);
1298 for (; i
< NR_CPUS
; i
++)
1299 set_cpu_possible(i
, false);
1301 nr_cpu_ids
= possible
;
1304 #ifdef CONFIG_HOTPLUG_CPU
1306 static void remove_siblinginfo(int cpu
)
1309 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1311 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1312 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1314 * last thread sibling in this cpu core going down
1316 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1317 cpu_data(sibling
).booted_cores
--;
1320 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1321 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1322 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1323 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1324 cpumask_clear(cpu_llc_shared_mask(cpu
));
1325 cpumask_clear(cpu_sibling_mask(cpu
));
1326 cpumask_clear(cpu_core_mask(cpu
));
1327 c
->phys_proc_id
= 0;
1329 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1332 static void __ref
remove_cpu_from_maps(int cpu
)
1334 set_cpu_online(cpu
, false);
1335 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1336 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1337 /* was set by cpu_init() */
1338 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1339 numa_remove_cpu(cpu
);
1342 void cpu_disable_common(void)
1344 int cpu
= smp_processor_id();
1346 remove_siblinginfo(cpu
);
1348 /* It's now safe to remove this processor from the online map */
1350 remove_cpu_from_maps(cpu
);
1351 unlock_vector_lock();
1355 int native_cpu_disable(void)
1359 ret
= check_irq_vectors_for_cpu_disable();
1364 cpu_disable_common();
1369 int common_cpu_die(unsigned int cpu
)
1373 /* We don't do anything here: idle task is faking death itself. */
1375 /* They ack this in play_dead() by setting CPU_DEAD */
1376 if (cpu_wait_death(cpu
, 5)) {
1377 if (system_state
== SYSTEM_RUNNING
)
1378 pr_info("CPU %u is now offline\n", cpu
);
1380 pr_err("CPU %u didn't die...\n", cpu
);
1387 void native_cpu_die(unsigned int cpu
)
1389 common_cpu_die(cpu
);
1392 void play_dead_common(void)
1395 reset_lazy_tlbstate();
1396 amd_e400_remove_cpu(raw_smp_processor_id());
1399 (void)cpu_report_death();
1402 * With physical CPU hotplug, we should halt the cpu
1404 local_irq_disable();
1407 static bool wakeup_cpu0(void)
1409 if (smp_processor_id() == 0 && enable_start_cpu0
)
1416 * We need to flush the caches before going to sleep, lest we have
1417 * dirty data in our caches when we come back up.
1419 static inline void mwait_play_dead(void)
1421 unsigned int eax
, ebx
, ecx
, edx
;
1422 unsigned int highest_cstate
= 0;
1423 unsigned int highest_subcstate
= 0;
1427 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1429 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1431 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1434 eax
= CPUID_MWAIT_LEAF
;
1436 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1439 * eax will be 0 if EDX enumeration is not valid.
1440 * Initialized below to cstate, sub_cstate value when EDX is valid.
1442 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1445 edx
>>= MWAIT_SUBSTATE_SIZE
;
1446 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1447 if (edx
& MWAIT_SUBSTATE_MASK
) {
1449 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1452 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1453 (highest_subcstate
- 1);
1457 * This should be a memory location in a cache line which is
1458 * unlikely to be touched by other processors. The actual
1459 * content is immaterial as it is not actually modified in any way.
1461 mwait_ptr
= ¤t_thread_info()->flags
;
1467 * The CLFLUSH is a workaround for erratum AAI65 for
1468 * the Xeon 7400 series. It's not clear it is actually
1469 * needed, but it should be harmless in either case.
1470 * The WBINVD is insufficient due to the spurious-wakeup
1471 * case where we return around the loop.
1476 __monitor(mwait_ptr
, 0, 0);
1480 * If NMI wants to wake up CPU0, start CPU0.
1487 static inline void hlt_play_dead(void)
1489 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1495 * If NMI wants to wake up CPU0, start CPU0.
1502 void native_play_dead(void)
1505 tboot_shutdown(TB_SHUTDOWN_WFS
);
1507 mwait_play_dead(); /* Only returns on failure */
1508 if (cpuidle_play_dead())
1512 #else /* ... !CONFIG_HOTPLUG_CPU */
1513 int native_cpu_disable(void)
1518 void native_cpu_die(unsigned int cpu
)
1520 /* We said "no" in __cpu_disable */
1524 void native_play_dead(void)