1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/sched/clock.h>
6 #include <linux/init.h>
7 #include <linux/export.h>
8 #include <linux/timer.h>
9 #include <linux/acpi_pmtmr.h>
10 #include <linux/cpufreq.h>
11 #include <linux/delay.h>
12 #include <linux/clocksource.h>
13 #include <linux/percpu.h>
14 #include <linux/timex.h>
15 #include <linux/static_key.h>
18 #include <asm/timer.h>
19 #include <asm/vgtod.h>
21 #include <asm/delay.h>
22 #include <asm/hypervisor.h>
24 #include <asm/x86_init.h>
25 #include <asm/geode.h>
27 #include <asm/intel-family.h>
29 unsigned int __read_mostly cpu_khz
; /* TSC clocks / usec, not used here */
30 EXPORT_SYMBOL(cpu_khz
);
32 unsigned int __read_mostly tsc_khz
;
33 EXPORT_SYMBOL(tsc_khz
);
36 * TSC can be unstable due to cpufreq or due to unsynced TSCs
38 static int __read_mostly tsc_unstable
;
40 /* native_sched_clock() is called before tsc_init(), so
41 we must start with the TSC soft disabled to prevent
42 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
43 static int __read_mostly tsc_disabled
= -1;
45 static DEFINE_STATIC_KEY_FALSE(__use_tsc
);
47 int tsc_clocksource_reliable
;
49 static u32 art_to_tsc_numerator
;
50 static u32 art_to_tsc_denominator
;
51 static u64 art_to_tsc_offset
;
52 struct clocksource
*art_related_clocksource
;
55 struct cyc2ns_data data
[2]; /* 0 + 2*16 = 32 */
56 seqcount_t seq
; /* 32 + 4 = 36 */
58 }; /* fits one cacheline */
60 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns
, cyc2ns
);
62 void cyc2ns_read_begin(struct cyc2ns_data
*data
)
66 preempt_disable_notrace();
69 seq
= this_cpu_read(cyc2ns
.seq
.sequence
);
72 data
->cyc2ns_offset
= this_cpu_read(cyc2ns
.data
[idx
].cyc2ns_offset
);
73 data
->cyc2ns_mul
= this_cpu_read(cyc2ns
.data
[idx
].cyc2ns_mul
);
74 data
->cyc2ns_shift
= this_cpu_read(cyc2ns
.data
[idx
].cyc2ns_shift
);
76 } while (unlikely(seq
!= this_cpu_read(cyc2ns
.seq
.sequence
)));
79 void cyc2ns_read_end(void)
81 preempt_enable_notrace();
85 * Accelerators for sched_clock()
86 * convert from cycles(64bits) => nanoseconds (64bits)
88 * ns = cycles / (freq / ns_per_sec)
89 * ns = cycles * (ns_per_sec / freq)
90 * ns = cycles * (10^9 / (cpu_khz * 10^3))
91 * ns = cycles * (10^6 / cpu_khz)
93 * Then we use scaling math (suggested by george@mvista.com) to get:
94 * ns = cycles * (10^6 * SC / cpu_khz) / SC
95 * ns = cycles * cyc2ns_scale / SC
97 * And since SC is a constant power of two, we can convert the div
98 * into a shift. The larger SC is, the more accurate the conversion, but
99 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
100 * (64-bit result) can be used.
102 * We can use khz divisor instead of mhz to keep a better precision.
103 * (mathieu.desnoyers@polymtl.ca)
105 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
108 static void cyc2ns_data_init(struct cyc2ns_data
*data
)
110 data
->cyc2ns_mul
= 0;
111 data
->cyc2ns_shift
= 0;
112 data
->cyc2ns_offset
= 0;
115 static void __init
cyc2ns_init(int cpu
)
117 struct cyc2ns
*c2n
= &per_cpu(cyc2ns
, cpu
);
119 cyc2ns_data_init(&c2n
->data
[0]);
120 cyc2ns_data_init(&c2n
->data
[1]);
122 seqcount_init(&c2n
->seq
);
125 static inline unsigned long long cycles_2_ns(unsigned long long cyc
)
127 struct cyc2ns_data data
;
128 unsigned long long ns
;
130 cyc2ns_read_begin(&data
);
132 ns
= data
.cyc2ns_offset
;
133 ns
+= mul_u64_u32_shr(cyc
, data
.cyc2ns_mul
, data
.cyc2ns_shift
);
140 static void set_cyc2ns_scale(unsigned long khz
, int cpu
, unsigned long long tsc_now
)
142 unsigned long long ns_now
;
143 struct cyc2ns_data data
;
147 local_irq_save(flags
);
148 sched_clock_idle_sleep_event();
153 ns_now
= cycles_2_ns(tsc_now
);
156 * Compute a new multiplier as per the above comment and ensure our
157 * time function is continuous; see the comment near struct
160 clocks_calc_mult_shift(&data
.cyc2ns_mul
, &data
.cyc2ns_shift
, khz
,
164 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
165 * not expected to be greater than 31 due to the original published
166 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
167 * value) - refer perf_event_mmap_page documentation in perf_event.h.
169 if (data
.cyc2ns_shift
== 32) {
170 data
.cyc2ns_shift
= 31;
171 data
.cyc2ns_mul
>>= 1;
174 data
.cyc2ns_offset
= ns_now
-
175 mul_u64_u32_shr(tsc_now
, data
.cyc2ns_mul
, data
.cyc2ns_shift
);
177 c2n
= per_cpu_ptr(&cyc2ns
, cpu
);
179 raw_write_seqcount_latch(&c2n
->seq
);
181 raw_write_seqcount_latch(&c2n
->seq
);
185 sched_clock_idle_wakeup_event();
186 local_irq_restore(flags
);
190 * Scheduler clock - returns current time in nanosec units.
192 u64
native_sched_clock(void)
194 if (static_branch_likely(&__use_tsc
)) {
195 u64 tsc_now
= rdtsc();
197 /* return the value in ns */
198 return cycles_2_ns(tsc_now
);
202 * Fall back to jiffies if there's no TSC available:
203 * ( But note that we still use it if the TSC is marked
204 * unstable. We do this because unlike Time Of Day,
205 * the scheduler clock tolerates small errors and it's
206 * very important for it to be as fast as the platform
210 /* No locking but a rare wrong value is not a big deal: */
211 return (jiffies_64
- INITIAL_JIFFIES
) * (1000000000 / HZ
);
215 * Generate a sched_clock if you already have a TSC value.
217 u64
native_sched_clock_from_tsc(u64 tsc
)
219 return cycles_2_ns(tsc
);
222 /* We need to define a real function for sched_clock, to override the
223 weak default version */
224 #ifdef CONFIG_PARAVIRT
225 unsigned long long sched_clock(void)
227 return paravirt_sched_clock();
230 bool using_native_sched_clock(void)
232 return pv_time_ops
.sched_clock
== native_sched_clock
;
236 sched_clock(void) __attribute__((alias("native_sched_clock")));
238 bool using_native_sched_clock(void) { return true; }
241 int check_tsc_unstable(void)
245 EXPORT_SYMBOL_GPL(check_tsc_unstable
);
247 #ifdef CONFIG_X86_TSC
248 int __init
notsc_setup(char *str
)
250 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
256 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
259 int __init
notsc_setup(char *str
)
261 setup_clear_cpu_cap(X86_FEATURE_TSC
);
266 __setup("notsc", notsc_setup
);
268 static int no_sched_irq_time
;
270 static int __init
tsc_setup(char *str
)
272 if (!strcmp(str
, "reliable"))
273 tsc_clocksource_reliable
= 1;
274 if (!strncmp(str
, "noirqtime", 9))
275 no_sched_irq_time
= 1;
276 if (!strcmp(str
, "unstable"))
277 mark_tsc_unstable("boot parameter");
281 __setup("tsc=", tsc_setup
);
283 #define MAX_RETRIES 5
284 #define SMI_TRESHOLD 50000
287 * Read TSC and the reference counters. Take care of SMI disturbance
289 static u64
tsc_read_refs(u64
*p
, int hpet
)
294 for (i
= 0; i
< MAX_RETRIES
; i
++) {
297 *p
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
299 *p
= acpi_pm_read_early();
301 if ((t2
- t1
) < SMI_TRESHOLD
)
308 * Calculate the TSC frequency from HPET reference
310 static unsigned long calc_hpet_ref(u64 deltatsc
, u64 hpet1
, u64 hpet2
)
315 hpet2
+= 0x100000000ULL
;
317 tmp
= ((u64
)hpet2
* hpet_readl(HPET_PERIOD
));
318 do_div(tmp
, 1000000);
319 deltatsc
= div64_u64(deltatsc
, tmp
);
321 return (unsigned long) deltatsc
;
325 * Calculate the TSC frequency from PMTimer reference
327 static unsigned long calc_pmtimer_ref(u64 deltatsc
, u64 pm1
, u64 pm2
)
335 pm2
+= (u64
)ACPI_PM_OVRRUN
;
337 tmp
= pm2
* 1000000000LL;
338 do_div(tmp
, PMTMR_TICKS_PER_SEC
);
339 do_div(deltatsc
, tmp
);
341 return (unsigned long) deltatsc
;
345 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
346 #define CAL_PIT_LOOPS 1000
349 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
350 #define CAL2_PIT_LOOPS 5000
354 * Try to calibrate the TSC against the Programmable
355 * Interrupt Timer and return the frequency of the TSC
358 * Return ULONG_MAX on failure to calibrate.
360 static unsigned long pit_calibrate_tsc(u32 latch
, unsigned long ms
, int loopmin
)
362 u64 tsc
, t1
, t2
, delta
;
363 unsigned long tscmin
, tscmax
;
366 /* Set the Gate high, disable speaker */
367 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
370 * Setup CTC channel 2* for mode 0, (interrupt on terminal
371 * count mode), binary count. Set the latch register to 50ms
372 * (LSB then MSB) to begin countdown.
375 outb(latch
& 0xff, 0x42);
376 outb(latch
>> 8, 0x42);
378 tsc
= t1
= t2
= get_cycles();
383 while ((inb(0x61) & 0x20) == 0) {
387 if ((unsigned long) delta
< tscmin
)
388 tscmin
= (unsigned int) delta
;
389 if ((unsigned long) delta
> tscmax
)
390 tscmax
= (unsigned int) delta
;
397 * If we were not able to read the PIT more than loopmin
398 * times, then we have been hit by a massive SMI
400 * If the maximum is 10 times larger than the minimum,
401 * then we got hit by an SMI as well.
403 if (pitcnt
< loopmin
|| tscmax
> 10 * tscmin
)
406 /* Calculate the PIT value */
413 * This reads the current MSB of the PIT counter, and
414 * checks if we are running on sufficiently fast and
415 * non-virtualized hardware.
417 * Our expectations are:
419 * - the PIT is running at roughly 1.19MHz
421 * - each IO is going to take about 1us on real hardware,
422 * but we allow it to be much faster (by a factor of 10) or
423 * _slightly_ slower (ie we allow up to a 2us read+counter
424 * update - anything else implies a unacceptably slow CPU
425 * or PIT for the fast calibration to work.
427 * - with 256 PIT ticks to read the value, we have 214us to
428 * see the same MSB (and overhead like doing a single TSC
429 * read per MSB value etc).
431 * - We're doing 2 reads per loop (LSB, MSB), and we expect
432 * them each to take about a microsecond on real hardware.
433 * So we expect a count value of around 100. But we'll be
434 * generous, and accept anything over 50.
436 * - if the PIT is stuck, and we see *many* more reads, we
437 * return early (and the next caller of pit_expect_msb()
438 * then consider it a failure when they don't see the
439 * next expected value).
441 * These expectations mean that we know that we have seen the
442 * transition from one expected value to another with a fairly
443 * high accuracy, and we didn't miss any events. We can thus
444 * use the TSC value at the transitions to calculate a pretty
445 * good value for the TSC frequencty.
447 static inline int pit_verify_msb(unsigned char val
)
451 return inb(0x42) == val
;
454 static inline int pit_expect_msb(unsigned char val
, u64
*tscp
, unsigned long *deltap
)
457 u64 tsc
= 0, prev_tsc
= 0;
459 for (count
= 0; count
< 50000; count
++) {
460 if (!pit_verify_msb(val
))
465 *deltap
= get_cycles() - prev_tsc
;
469 * We require _some_ success, but the quality control
470 * will be based on the error terms on the TSC values.
476 * How many MSB values do we want to see? We aim for
477 * a maximum error rate of 500ppm (in practice the
478 * real error is much smaller), but refuse to spend
479 * more than 50ms on it.
481 #define MAX_QUICK_PIT_MS 50
482 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
484 static unsigned long quick_pit_calibrate(void)
488 unsigned long d1
, d2
;
490 /* Set the Gate high, disable speaker */
491 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
494 * Counter 2, mode 0 (one-shot), binary count
496 * NOTE! Mode 2 decrements by two (and then the
497 * output is flipped each time, giving the same
498 * final output frequency as a decrement-by-one),
499 * so mode 0 is much better when looking at the
504 /* Start at 0xffff */
509 * The PIT starts counting at the next edge, so we
510 * need to delay for a microsecond. The easiest way
511 * to do that is to just read back the 16-bit counter
516 if (pit_expect_msb(0xff, &tsc
, &d1
)) {
517 for (i
= 1; i
<= MAX_QUICK_PIT_ITERATIONS
; i
++) {
518 if (!pit_expect_msb(0xff-i
, &delta
, &d2
))
524 * Extrapolate the error and fail fast if the error will
525 * never be below 500 ppm.
528 d1
+ d2
>= (delta
* MAX_QUICK_PIT_ITERATIONS
) >> 11)
532 * Iterate until the error is less than 500 ppm
534 if (d1
+d2
>= delta
>> 11)
538 * Check the PIT one more time to verify that
539 * all TSC reads were stable wrt the PIT.
541 * This also guarantees serialization of the
542 * last cycle read ('d2') in pit_expect_msb.
544 if (!pit_verify_msb(0xfe - i
))
549 pr_info("Fast TSC calibration failed\n");
554 * Ok, if we get here, then we've seen the
555 * MSB of the PIT decrement 'i' times, and the
556 * error has shrunk to less than 500 ppm.
558 * As a result, we can depend on there not being
559 * any odd delays anywhere, and the TSC reads are
560 * reliable (within the error).
562 * kHz = ticks / time-in-seconds / 1000;
563 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
564 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
566 delta
*= PIT_TICK_RATE
;
567 do_div(delta
, i
*256*1000);
568 pr_info("Fast TSC calibration using PIT\n");
573 * native_calibrate_tsc
574 * Determine TSC frequency via CPUID, else return 0.
576 unsigned long native_calibrate_tsc(void)
578 unsigned int eax_denominator
, ebx_numerator
, ecx_hz
, edx
;
579 unsigned int crystal_khz
;
581 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
584 if (boot_cpu_data
.cpuid_level
< 0x15)
587 eax_denominator
= ebx_numerator
= ecx_hz
= edx
= 0;
589 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
590 cpuid(0x15, &eax_denominator
, &ebx_numerator
, &ecx_hz
, &edx
);
592 if (ebx_numerator
== 0 || eax_denominator
== 0)
595 crystal_khz
= ecx_hz
/ 1000;
597 if (crystal_khz
== 0) {
598 switch (boot_cpu_data
.x86_model
) {
599 case INTEL_FAM6_SKYLAKE_MOBILE
:
600 case INTEL_FAM6_SKYLAKE_DESKTOP
:
601 case INTEL_FAM6_KABYLAKE_MOBILE
:
602 case INTEL_FAM6_KABYLAKE_DESKTOP
:
603 crystal_khz
= 24000; /* 24.0 MHz */
605 case INTEL_FAM6_ATOM_DENVERTON
:
606 crystal_khz
= 25000; /* 25.0 MHz */
608 case INTEL_FAM6_ATOM_GOLDMONT
:
609 crystal_khz
= 19200; /* 19.2 MHz */
614 if (crystal_khz
== 0)
617 * TSC frequency determined by CPUID is a "hardware reported"
618 * frequency and is the most accurate one so far we have. This
619 * is considered a known frequency.
621 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ
);
624 * For Atom SoCs TSC is the only reliable clocksource.
625 * Mark TSC reliable so no watchdog on it.
627 if (boot_cpu_data
.x86_model
== INTEL_FAM6_ATOM_GOLDMONT
)
628 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE
);
630 return crystal_khz
* ebx_numerator
/ eax_denominator
;
633 static unsigned long cpu_khz_from_cpuid(void)
635 unsigned int eax_base_mhz
, ebx_max_mhz
, ecx_bus_mhz
, edx
;
637 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
640 if (boot_cpu_data
.cpuid_level
< 0x16)
643 eax_base_mhz
= ebx_max_mhz
= ecx_bus_mhz
= edx
= 0;
645 cpuid(0x16, &eax_base_mhz
, &ebx_max_mhz
, &ecx_bus_mhz
, &edx
);
647 return eax_base_mhz
* 1000;
651 * native_calibrate_cpu - calibrate the cpu on boot
653 unsigned long native_calibrate_cpu(void)
655 u64 tsc1
, tsc2
, delta
, ref1
, ref2
;
656 unsigned long tsc_pit_min
= ULONG_MAX
, tsc_ref_min
= ULONG_MAX
;
657 unsigned long flags
, latch
, ms
, fast_calibrate
;
658 int hpet
= is_hpet_enabled(), i
, loopmin
;
660 fast_calibrate
= cpu_khz_from_cpuid();
662 return fast_calibrate
;
664 fast_calibrate
= cpu_khz_from_msr();
666 return fast_calibrate
;
668 local_irq_save(flags
);
669 fast_calibrate
= quick_pit_calibrate();
670 local_irq_restore(flags
);
672 return fast_calibrate
;
675 * Run 5 calibration loops to get the lowest frequency value
676 * (the best estimate). We use two different calibration modes
679 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
680 * load a timeout of 50ms. We read the time right after we
681 * started the timer and wait until the PIT count down reaches
682 * zero. In each wait loop iteration we read the TSC and check
683 * the delta to the previous read. We keep track of the min
684 * and max values of that delta. The delta is mostly defined
685 * by the IO time of the PIT access, so we can detect when a
686 * SMI/SMM disturbance happened between the two reads. If the
687 * maximum time is significantly larger than the minimum time,
688 * then we discard the result and have another try.
690 * 2) Reference counter. If available we use the HPET or the
691 * PMTIMER as a reference to check the sanity of that value.
692 * We use separate TSC readouts and check inside of the
693 * reference read for a SMI/SMM disturbance. We dicard
694 * disturbed values here as well. We do that around the PIT
695 * calibration delay loop as we have to wait for a certain
696 * amount of time anyway.
699 /* Preset PIT loop values */
702 loopmin
= CAL_PIT_LOOPS
;
704 for (i
= 0; i
< 3; i
++) {
705 unsigned long tsc_pit_khz
;
708 * Read the start value and the reference count of
709 * hpet/pmtimer when available. Then do the PIT
710 * calibration, which will take at least 50ms, and
711 * read the end value.
713 local_irq_save(flags
);
714 tsc1
= tsc_read_refs(&ref1
, hpet
);
715 tsc_pit_khz
= pit_calibrate_tsc(latch
, ms
, loopmin
);
716 tsc2
= tsc_read_refs(&ref2
, hpet
);
717 local_irq_restore(flags
);
719 /* Pick the lowest PIT TSC calibration so far */
720 tsc_pit_min
= min(tsc_pit_min
, tsc_pit_khz
);
722 /* hpet or pmtimer available ? */
726 /* Check, whether the sampling was disturbed by an SMI */
727 if (tsc1
== ULLONG_MAX
|| tsc2
== ULLONG_MAX
)
730 tsc2
= (tsc2
- tsc1
) * 1000000LL;
732 tsc2
= calc_hpet_ref(tsc2
, ref1
, ref2
);
734 tsc2
= calc_pmtimer_ref(tsc2
, ref1
, ref2
);
736 tsc_ref_min
= min(tsc_ref_min
, (unsigned long) tsc2
);
738 /* Check the reference deviation */
739 delta
= ((u64
) tsc_pit_min
) * 100;
740 do_div(delta
, tsc_ref_min
);
743 * If both calibration results are inside a 10% window
744 * then we can be sure, that the calibration
745 * succeeded. We break out of the loop right away. We
746 * use the reference value, as it is more precise.
748 if (delta
>= 90 && delta
<= 110) {
749 pr_info("PIT calibration matches %s. %d loops\n",
750 hpet
? "HPET" : "PMTIMER", i
+ 1);
755 * Check whether PIT failed more than once. This
756 * happens in virtualized environments. We need to
757 * give the virtual PC a slightly longer timeframe for
758 * the HPET/PMTIMER to make the result precise.
760 if (i
== 1 && tsc_pit_min
== ULONG_MAX
) {
763 loopmin
= CAL2_PIT_LOOPS
;
768 * Now check the results.
770 if (tsc_pit_min
== ULONG_MAX
) {
771 /* PIT gave no useful value */
772 pr_warn("Unable to calibrate against PIT\n");
774 /* We don't have an alternative source, disable TSC */
775 if (!hpet
&& !ref1
&& !ref2
) {
776 pr_notice("No reference (HPET/PMTIMER) available\n");
780 /* The alternative source failed as well, disable TSC */
781 if (tsc_ref_min
== ULONG_MAX
) {
782 pr_warn("HPET/PMTIMER calibration failed\n");
786 /* Use the alternative source */
787 pr_info("using %s reference calibration\n",
788 hpet
? "HPET" : "PMTIMER");
793 /* We don't have an alternative source, use the PIT calibration value */
794 if (!hpet
&& !ref1
&& !ref2
) {
795 pr_info("Using PIT calibration value\n");
799 /* The alternative source failed, use the PIT calibration value */
800 if (tsc_ref_min
== ULONG_MAX
) {
801 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
806 * The calibration values differ too much. In doubt, we use
807 * the PIT value as we know that there are PMTIMERs around
808 * running at double speed. At least we let the user know:
810 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
811 hpet
? "HPET" : "PMTIMER", tsc_pit_min
, tsc_ref_min
);
812 pr_info("Using PIT calibration value\n");
816 void recalibrate_cpu_khz(void)
819 unsigned long cpu_khz_old
= cpu_khz
;
821 if (!boot_cpu_has(X86_FEATURE_TSC
))
824 cpu_khz
= x86_platform
.calibrate_cpu();
825 tsc_khz
= x86_platform
.calibrate_tsc();
828 else if (abs(cpu_khz
- tsc_khz
) * 10 > tsc_khz
)
830 cpu_data(0).loops_per_jiffy
= cpufreq_scale(cpu_data(0).loops_per_jiffy
,
831 cpu_khz_old
, cpu_khz
);
835 EXPORT_SYMBOL(recalibrate_cpu_khz
);
838 static unsigned long long cyc2ns_suspend
;
840 void tsc_save_sched_clock_state(void)
842 if (!sched_clock_stable())
845 cyc2ns_suspend
= sched_clock();
849 * Even on processors with invariant TSC, TSC gets reset in some the
850 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
851 * arbitrary value (still sync'd across cpu's) during resume from such sleep
852 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
853 * that sched_clock() continues from the point where it was left off during
856 void tsc_restore_sched_clock_state(void)
858 unsigned long long offset
;
862 if (!sched_clock_stable())
865 local_irq_save(flags
);
868 * We're coming out of suspend, there's no concurrency yet; don't
869 * bother being nice about the RCU stuff, just write to both
873 this_cpu_write(cyc2ns
.data
[0].cyc2ns_offset
, 0);
874 this_cpu_write(cyc2ns
.data
[1].cyc2ns_offset
, 0);
876 offset
= cyc2ns_suspend
- sched_clock();
878 for_each_possible_cpu(cpu
) {
879 per_cpu(cyc2ns
.data
[0].cyc2ns_offset
, cpu
) = offset
;
880 per_cpu(cyc2ns
.data
[1].cyc2ns_offset
, cpu
) = offset
;
883 local_irq_restore(flags
);
886 #ifdef CONFIG_CPU_FREQ
887 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
890 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
891 * not that important because current Opteron setups do not support
892 * scaling on SMP anyroads.
894 * Should fix up last_tsc too. Currently gettimeofday in the
895 * first tick after the change will be slightly wrong.
898 static unsigned int ref_freq
;
899 static unsigned long loops_per_jiffy_ref
;
900 static unsigned long tsc_khz_ref
;
902 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
905 struct cpufreq_freqs
*freq
= data
;
908 lpj
= &boot_cpu_data
.loops_per_jiffy
;
910 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
911 lpj
= &cpu_data(freq
->cpu
).loops_per_jiffy
;
915 ref_freq
= freq
->old
;
916 loops_per_jiffy_ref
= *lpj
;
917 tsc_khz_ref
= tsc_khz
;
919 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
920 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new)) {
921 *lpj
= cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
923 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
924 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
925 mark_tsc_unstable("cpufreq changes");
927 set_cyc2ns_scale(tsc_khz
, freq
->cpu
, rdtsc());
933 static struct notifier_block time_cpufreq_notifier_block
= {
934 .notifier_call
= time_cpufreq_notifier
937 static int __init
cpufreq_register_tsc_scaling(void)
939 if (!boot_cpu_has(X86_FEATURE_TSC
))
941 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
943 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
944 CPUFREQ_TRANSITION_NOTIFIER
);
948 core_initcall(cpufreq_register_tsc_scaling
);
950 #endif /* CONFIG_CPU_FREQ */
952 #define ART_CPUID_LEAF (0x15)
953 #define ART_MIN_DENOMINATOR (1)
957 * If ART is present detect the numerator:denominator to convert to TSC
959 static void __init
detect_art(void)
961 unsigned int unused
[2];
963 if (boot_cpu_data
.cpuid_level
< ART_CPUID_LEAF
)
967 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
968 * and the TSC counter resets must not occur asynchronously.
970 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
) ||
971 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC
) ||
972 !boot_cpu_has(X86_FEATURE_TSC_ADJUST
) ||
976 cpuid(ART_CPUID_LEAF
, &art_to_tsc_denominator
,
977 &art_to_tsc_numerator
, unused
, unused
+1);
979 if (art_to_tsc_denominator
< ART_MIN_DENOMINATOR
)
982 rdmsrl(MSR_IA32_TSC_ADJUST
, art_to_tsc_offset
);
984 /* Make this sticky over multiple CPU init calls */
985 setup_force_cpu_cap(X86_FEATURE_ART
);
989 /* clocksource code */
991 static struct clocksource clocksource_tsc
;
993 static void tsc_resume(struct clocksource
*cs
)
995 tsc_verify_tsc_adjust(true);
999 * We used to compare the TSC to the cycle_last value in the clocksource
1000 * structure to avoid a nasty time-warp. This can be observed in a
1001 * very small window right after one CPU updated cycle_last under
1002 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1003 * is smaller than the cycle_last reference value due to a TSC which
1004 * is slighty behind. This delta is nowhere else observable, but in
1005 * that case it results in a forward time jump in the range of hours
1006 * due to the unsigned delta calculation of the time keeping core
1007 * code, which is necessary to support wrapping clocksources like pm
1010 * This sanity check is now done in the core timekeeping code.
1011 * checking the result of read_tsc() - cycle_last for being negative.
1012 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1014 static u64
read_tsc(struct clocksource
*cs
)
1016 return (u64
)rdtsc_ordered();
1019 static void tsc_cs_mark_unstable(struct clocksource
*cs
)
1025 if (using_native_sched_clock())
1026 clear_sched_clock_stable();
1027 disable_sched_clock_irqtime();
1028 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1031 static void tsc_cs_tick_stable(struct clocksource
*cs
)
1036 if (using_native_sched_clock())
1037 sched_clock_tick_stable();
1041 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1043 static struct clocksource clocksource_tsc
= {
1047 .mask
= CLOCKSOURCE_MASK(64),
1048 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
1049 CLOCK_SOURCE_MUST_VERIFY
,
1050 .archdata
= { .vclock_mode
= VCLOCK_TSC
},
1051 .resume
= tsc_resume
,
1052 .mark_unstable
= tsc_cs_mark_unstable
,
1053 .tick_stable
= tsc_cs_tick_stable
,
1056 void mark_tsc_unstable(char *reason
)
1062 if (using_native_sched_clock())
1063 clear_sched_clock_stable();
1064 disable_sched_clock_irqtime();
1065 pr_info("Marking TSC unstable due to %s\n", reason
);
1066 /* Change only the rating, when not registered */
1067 if (clocksource_tsc
.mult
) {
1068 clocksource_mark_unstable(&clocksource_tsc
);
1070 clocksource_tsc
.flags
|= CLOCK_SOURCE_UNSTABLE
;
1071 clocksource_tsc
.rating
= 0;
1075 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
1077 static void __init
check_system_tsc_reliable(void)
1079 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1080 if (is_geode_lx()) {
1081 /* RTSC counts during suspend */
1082 #define RTSC_SUSP 0x100
1083 unsigned long res_low
, res_high
;
1085 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0
, &res_low
, &res_high
);
1086 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1087 if (res_low
& RTSC_SUSP
)
1088 tsc_clocksource_reliable
= 1;
1091 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE
))
1092 tsc_clocksource_reliable
= 1;
1096 * Make an educated guess if the TSC is trustworthy and synchronized
1099 int unsynchronized_tsc(void)
1101 if (!boot_cpu_has(X86_FEATURE_TSC
) || tsc_unstable
)
1105 if (apic_is_clustered_box())
1109 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
1112 if (tsc_clocksource_reliable
)
1115 * Intel systems are normally all synchronized.
1116 * Exceptions must mark TSC as unstable:
1118 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
) {
1119 /* assume multi socket systems are not synchronized: */
1120 if (num_possible_cpus() > 1)
1128 * Convert ART to TSC given numerator/denominator found in detect_art()
1130 struct system_counterval_t
convert_art_to_tsc(u64 art
)
1134 rem
= do_div(art
, art_to_tsc_denominator
);
1136 res
= art
* art_to_tsc_numerator
;
1137 tmp
= rem
* art_to_tsc_numerator
;
1139 do_div(tmp
, art_to_tsc_denominator
);
1140 res
+= tmp
+ art_to_tsc_offset
;
1142 return (struct system_counterval_t
) {.cs
= art_related_clocksource
,
1145 EXPORT_SYMBOL(convert_art_to_tsc
);
1147 static void tsc_refine_calibration_work(struct work_struct
*work
);
1148 static DECLARE_DELAYED_WORK(tsc_irqwork
, tsc_refine_calibration_work
);
1150 * tsc_refine_calibration_work - Further refine tsc freq calibration
1153 * This functions uses delayed work over a period of a
1154 * second to further refine the TSC freq value. Since this is
1155 * timer based, instead of loop based, we don't block the boot
1156 * process while this longer calibration is done.
1158 * If there are any calibration anomalies (too many SMIs, etc),
1159 * or the refined calibration is off by 1% of the fast early
1160 * calibration, we throw out the new calibration and use the
1161 * early calibration.
1163 static void tsc_refine_calibration_work(struct work_struct
*work
)
1165 static u64 tsc_start
= -1, ref_start
;
1167 u64 tsc_stop
, ref_stop
, delta
;
1171 /* Don't bother refining TSC on unstable systems */
1172 if (check_tsc_unstable())
1176 * Since the work is started early in boot, we may be
1177 * delayed the first time we expire. So set the workqueue
1178 * again once we know timers are working.
1180 if (tsc_start
== -1) {
1182 * Only set hpet once, to avoid mixing hardware
1183 * if the hpet becomes enabled later.
1185 hpet
= is_hpet_enabled();
1186 schedule_delayed_work(&tsc_irqwork
, HZ
);
1187 tsc_start
= tsc_read_refs(&ref_start
, hpet
);
1191 tsc_stop
= tsc_read_refs(&ref_stop
, hpet
);
1193 /* hpet or pmtimer available ? */
1194 if (ref_start
== ref_stop
)
1197 /* Check, whether the sampling was disturbed by an SMI */
1198 if (tsc_start
== ULLONG_MAX
|| tsc_stop
== ULLONG_MAX
)
1201 delta
= tsc_stop
- tsc_start
;
1204 freq
= calc_hpet_ref(delta
, ref_start
, ref_stop
);
1206 freq
= calc_pmtimer_ref(delta
, ref_start
, ref_stop
);
1208 /* Make sure we're within 1% */
1209 if (abs(tsc_khz
- freq
) > tsc_khz
/100)
1213 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1214 (unsigned long)tsc_khz
/ 1000,
1215 (unsigned long)tsc_khz
% 1000);
1217 /* Inform the TSC deadline clockevent devices about the recalibration */
1218 lapic_update_tsc_freq();
1220 /* Update the sched_clock() rate to match the clocksource one */
1221 for_each_possible_cpu(cpu
)
1222 set_cyc2ns_scale(tsc_khz
, cpu
, tsc_stop
);
1225 if (boot_cpu_has(X86_FEATURE_ART
))
1226 art_related_clocksource
= &clocksource_tsc
;
1227 clocksource_register_khz(&clocksource_tsc
, tsc_khz
);
1231 static int __init
init_tsc_clocksource(void)
1233 if (!boot_cpu_has(X86_FEATURE_TSC
) || tsc_disabled
> 0 || !tsc_khz
)
1236 if (tsc_clocksource_reliable
)
1237 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_MUST_VERIFY
;
1238 /* lower the rating if we already know its unstable: */
1239 if (check_tsc_unstable()) {
1240 clocksource_tsc
.rating
= 0;
1241 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_IS_CONTINUOUS
;
1244 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3
))
1245 clocksource_tsc
.flags
|= CLOCK_SOURCE_SUSPEND_NONSTOP
;
1248 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1249 * the refined calibration and directly register it as a clocksource.
1251 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ
)) {
1252 if (boot_cpu_has(X86_FEATURE_ART
))
1253 art_related_clocksource
= &clocksource_tsc
;
1254 clocksource_register_khz(&clocksource_tsc
, tsc_khz
);
1258 schedule_delayed_work(&tsc_irqwork
, 0);
1262 * We use device_initcall here, to ensure we run after the hpet
1263 * is fully initialized, which may occur at fs_initcall time.
1265 device_initcall(init_tsc_clocksource
);
1267 void __init
tsc_early_delay_calibrate(void)
1271 if (!boot_cpu_has(X86_FEATURE_TSC
))
1274 cpu_khz
= x86_platform
.calibrate_cpu();
1275 tsc_khz
= x86_platform
.calibrate_tsc();
1277 tsc_khz
= tsc_khz
? : cpu_khz
;
1281 lpj
= tsc_khz
* 1000;
1283 loops_per_jiffy
= lpj
;
1286 void __init
tsc_init(void)
1291 if (!boot_cpu_has(X86_FEATURE_TSC
)) {
1292 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
1296 cpu_khz
= x86_platform
.calibrate_cpu();
1297 tsc_khz
= x86_platform
.calibrate_tsc();
1300 * Trust non-zero tsc_khz as authorative,
1301 * and use it to sanity check cpu_khz,
1302 * which will be off if system timer is off.
1306 else if (abs(cpu_khz
- tsc_khz
) * 10 > tsc_khz
)
1310 mark_tsc_unstable("could not calculate TSC khz");
1311 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER
);
1315 pr_info("Detected %lu.%03lu MHz processor\n",
1316 (unsigned long)cpu_khz
/ 1000,
1317 (unsigned long)cpu_khz
% 1000);
1319 if (cpu_khz
!= tsc_khz
) {
1320 pr_info("Detected %lu.%03lu MHz TSC",
1321 (unsigned long)tsc_khz
/ 1000,
1322 (unsigned long)tsc_khz
% 1000);
1325 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1326 tsc_store_and_check_tsc_adjust(true);
1329 * Secondary CPUs do not run through tsc_init(), so set up
1330 * all the scale factors for all CPUs, assuming the same
1331 * speed as the bootup CPU. (cpufreq notifiers will fix this
1332 * up if their speed diverges)
1335 for_each_possible_cpu(cpu
) {
1337 set_cyc2ns_scale(tsc_khz
, cpu
, cyc
);
1340 if (tsc_disabled
> 0)
1343 /* now allow native_sched_clock() to use rdtsc */
1346 static_branch_enable(&__use_tsc
);
1348 if (!no_sched_irq_time
)
1349 enable_sched_clock_irqtime();
1351 lpj
= ((u64
)tsc_khz
* 1000);
1357 check_system_tsc_reliable();
1359 if (unsynchronized_tsc())
1360 mark_tsc_unstable("TSCs unsynchronized");
1367 * If we have a constant TSC and are using the TSC for the delay loop,
1368 * we can skip clock calibration if another cpu in the same socket has already
1369 * been calibrated. This assumes that CONSTANT_TSC applies to all
1370 * cpus in the socket - this should be a safe assumption.
1372 unsigned long calibrate_delay_is_known(void)
1374 int sibling
, cpu
= smp_processor_id();
1375 int constant_tsc
= cpu_has(&cpu_data(cpu
), X86_FEATURE_CONSTANT_TSC
);
1376 const struct cpumask
*mask
= topology_core_cpumask(cpu
);
1378 if (tsc_disabled
|| !constant_tsc
|| !mask
)
1381 sibling
= cpumask_any_but(mask
, cpu
);
1382 if (sibling
< nr_cpu_ids
)
1383 return cpu_data(sibling
).loops_per_jiffy
;