arch/x86/kernel/tsc_msr.c

   1 /*
   2  * tsc_msr.c - TSC frequency enumeration via MSR
   3  *
   4  * Copyright (C) 2013 Intel Corporation
   5  * Author: Bin Gao <bin.gao@intel.com>
   6  *
   7  * This file is released under the GPLv2.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <asm/processor.h>
  12 #include <asm/setup.h>
  13 #include <asm/apic.h>
  14 #include <asm/param.h>
  15 #include <asm/tsc.h>
  16
  17 #define MAX_NUM_FREQS   9
  18
  19 /*
  20  * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  21  * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  22  * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  23  * so we need manually differentiate SoC families. This is what the
  24  * field msr_plat does.
  25  */
  26 struct freq_desc {
  27         u8 x86_family;  /* CPU family */
  28         u8 x86_model;   /* model */
  29         u8 msr_plat;    /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  30         u32 freqs[MAX_NUM_FREQS];
  31 };
  32
  33 static struct freq_desc freq_desc_tables[] = {
  34         /* PNW */
  35         { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
  36         /* CLV+ */
  37         { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
  38         /* TNG - Intel Atom processor Z3400 series */
  39         { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
  40         /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
  41         { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
  42         /* ANN - Intel Atom processor Z3500 series */
  43         { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
  44         /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
  45         { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
  46                         80000, 93300, 90000, 88900, 87500 } },
  47 };
  48
  49 static int match_cpu(u8 family, u8 model)
  50 {
  51         int i;
  52
  53         for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  54                 if ((family == freq_desc_tables[i].x86_family) &&
  55                         (model == freq_desc_tables[i].x86_model))
  56                         return i;
  57         }
  58
  59         return -1;
  60 }
  61
  62 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  63 #define id_to_freq(cpu_index, freq_id) \
  64         (freq_desc_tables[cpu_index].freqs[freq_id])
  65
  66 /*
  67  * MSR-based CPU/TSC frequency discovery for certain CPUs.
  68  *
  69  * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
  70  * Return processor base frequency in KHz, or 0 on failure.
  71  */
  72 unsigned long cpu_khz_from_msr(void)
  73 {
  74         u32 lo, hi, ratio, freq_id, freq;
  75         unsigned long res;
  76         int cpu_index;
  77
  78         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  79                 return 0;
  80
  81         cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
  82         if (cpu_index < 0)
  83                 return 0;
  84
  85         if (freq_desc_tables[cpu_index].msr_plat) {
  86                 rdmsr(MSR_PLATFORM_INFO, lo, hi);
  87                 ratio = (lo >> 8) & 0xff;
  88         } else {
  89                 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  90                 ratio = (hi >> 8) & 0x1f;
  91         }
  92
  93         /* Get FSB FREQ ID */
  94         rdmsr(MSR_FSB_FREQ, lo, hi);
  95         freq_id = lo & 0x7;
  96         freq = id_to_freq(cpu_index, freq_id);
  97
  98         /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  99         res = freq * ratio;
 100
 101 #ifdef CONFIG_X86_LOCAL_APIC
 102         lapic_timer_frequency = (freq * 1000) / HZ;
 103 #endif
 104
 105         /*
 106          * TSC frequency determined by MSR is always considered "known"
 107          * because it is reported by HW.
 108          * Another fact is that on MSR capable platforms, PIT/HPET is
 109          * generally not available so calibration won't work at all.
 110          */
 111         setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
 112
 113         /*
 114          * Unfortunately there is no way for hardware to tell whether the
 115          * TSC is reliable.  We were told by silicon design team that TSC
 116          * on Atom SoCs are always "reliable". TSC is also the only
 117          * reliable clocksource on these SoCs (HPET is either not present
 118          * or not functional) so mark TSC reliable which removes the
 119          * requirement for a watchdog clocksource.
 120          */
 121         setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 122
 123         return res;
 124 }