1 // SPDX-License-Identifier: GPL-2.0
3 * check TSC synchronization.
5 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
7 * We check whether all boot CPUs have their TSC's synchronized,
8 * print a warning if not and turn off the TSC clock-source.
10 * The warp-check is point-to-point between two CPUs, the CPU
11 * initiating the bootup is the 'source CPU', the freshly booting
12 * CPU is the 'target CPU'.
14 * Only two CPUs may participate - they can enter in any order.
15 * ( The serial nature of the boot logic and the CPU hotplug lock
16 * protects against more than 2 CPUs entering this code. )
18 #include <linux/topology.h>
19 #include <linux/spinlock.h>
20 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/nmi.h>
28 unsigned long nextcheck
;
32 static DEFINE_PER_CPU(struct tsc_adjust
, tsc_adjust
);
33 static struct timer_list tsc_sync_check_timer
;
36 * TSC's on different sockets may be reset asynchronously.
37 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
39 bool __read_mostly tsc_async_resets
;
41 void mark_tsc_async_resets(char *reason
)
45 tsc_async_resets
= true;
46 pr_info("tsc: Marking TSC async resets true due to %s\n", reason
);
49 void tsc_verify_tsc_adjust(bool resume
)
51 struct tsc_adjust
*adj
= this_cpu_ptr(&tsc_adjust
);
54 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST
))
57 /* Skip unnecessary error messages if TSC already unstable */
58 if (check_tsc_unstable())
61 /* Rate limit the MSR check */
62 if (!resume
&& time_before(jiffies
, adj
->nextcheck
))
65 adj
->nextcheck
= jiffies
+ HZ
;
67 rdmsrl(MSR_IA32_TSC_ADJUST
, curval
);
68 if (adj
->adjusted
== curval
)
71 /* Restore the original value */
72 wrmsrl(MSR_IA32_TSC_ADJUST
, adj
->adjusted
);
74 if (!adj
->warned
|| resume
) {
75 pr_warn(FW_BUG
"TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
76 smp_processor_id(), adj
->adjusted
, curval
);
82 * Normally the tsc_sync will be checked every time system enters idle
83 * state, but there is still caveat that a system won't enter idle,
84 * either because it's too busy or configured purposely to not enter
87 * So setup a periodic timer (every 10 minutes) to make sure the check
91 #define SYNC_CHECK_INTERVAL (HZ * 600)
93 static void tsc_sync_check_timer_fn(struct timer_list
*unused
)
97 tsc_verify_tsc_adjust(false);
99 /* Run the check for all onlined CPUs in turn */
100 next_cpu
= cpumask_next(raw_smp_processor_id(), cpu_online_mask
);
101 if (next_cpu
>= nr_cpu_ids
)
102 next_cpu
= cpumask_first(cpu_online_mask
);
104 tsc_sync_check_timer
.expires
+= SYNC_CHECK_INTERVAL
;
105 add_timer_on(&tsc_sync_check_timer
, next_cpu
);
108 static int __init
start_sync_check_timer(void)
110 if (!cpu_feature_enabled(X86_FEATURE_TSC_ADJUST
) || tsc_clocksource_reliable
)
113 timer_setup(&tsc_sync_check_timer
, tsc_sync_check_timer_fn
, 0);
114 tsc_sync_check_timer
.expires
= jiffies
+ SYNC_CHECK_INTERVAL
;
115 add_timer(&tsc_sync_check_timer
);
119 late_initcall(start_sync_check_timer
);
121 static void tsc_sanitize_first_cpu(struct tsc_adjust
*cur
, s64 bootval
,
122 unsigned int cpu
, bool bootcpu
)
125 * First online CPU in a package stores the boot value in the
126 * adjustment value. This value might change later via the sync
127 * mechanism. If that fails we still can yell about boot values not
130 * On the boot cpu we just force set the ADJUST value to 0 if it's
131 * non zero. We don't do that on non boot cpus because physical
132 * hotplug should have set the ADJUST register to a value > 0 so
133 * the TSC is in sync with the already running cpus.
135 * Also don't force the ADJUST value to zero if that is a valid value
136 * for socket 0 as determined by the system arch. This is required
137 * when multiple sockets are reset asynchronously with each other
138 * and socket 0 may not have an TSC ADJUST value of 0.
140 if (bootcpu
&& bootval
!= 0) {
141 if (likely(!tsc_async_resets
)) {
142 pr_warn(FW_BUG
"TSC ADJUST: CPU%u: %lld force to 0\n",
144 wrmsrl(MSR_IA32_TSC_ADJUST
, 0);
147 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
151 cur
->adjusted
= bootval
;
155 bool __init
tsc_store_and_check_tsc_adjust(bool bootcpu
)
157 struct tsc_adjust
*cur
= this_cpu_ptr(&tsc_adjust
);
160 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST
))
163 /* Skip unnecessary error messages if TSC already unstable */
164 if (check_tsc_unstable())
167 rdmsrl(MSR_IA32_TSC_ADJUST
, bootval
);
168 cur
->bootval
= bootval
;
169 cur
->nextcheck
= jiffies
+ HZ
;
170 tsc_sanitize_first_cpu(cur
, bootval
, smp_processor_id(), bootcpu
);
174 #else /* !CONFIG_SMP */
177 * Store and check the TSC ADJUST MSR if available
179 bool tsc_store_and_check_tsc_adjust(bool bootcpu
)
181 struct tsc_adjust
*ref
, *cur
= this_cpu_ptr(&tsc_adjust
);
182 unsigned int refcpu
, cpu
= smp_processor_id();
183 struct cpumask
*mask
;
186 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST
))
189 rdmsrl(MSR_IA32_TSC_ADJUST
, bootval
);
190 cur
->bootval
= bootval
;
191 cur
->nextcheck
= jiffies
+ HZ
;
195 * If a non-zero TSC value for socket 0 may be valid then the default
196 * adjusted value cannot assumed to be zero either.
198 if (tsc_async_resets
)
199 cur
->adjusted
= bootval
;
202 * Check whether this CPU is the first in a package to come up. In
203 * this case do not check the boot value against another package
204 * because the new package might have been physically hotplugged,
205 * where TSC_ADJUST is expected to be different. When called on the
206 * boot CPU topology_core_cpumask() might not be available yet.
208 mask
= topology_core_cpumask(cpu
);
209 refcpu
= mask
? cpumask_any_but(mask
, cpu
) : nr_cpu_ids
;
211 if (refcpu
>= nr_cpu_ids
) {
212 tsc_sanitize_first_cpu(cur
, bootval
, smp_processor_id(),
217 ref
= per_cpu_ptr(&tsc_adjust
, refcpu
);
219 * Compare the boot value and complain if it differs in the
222 if (bootval
!= ref
->bootval
)
223 printk_once(FW_BUG
"TSC ADJUST differs within socket(s), fixing all errors\n");
226 * The TSC_ADJUST values in a package must be the same. If the boot
227 * value on this newly upcoming CPU differs from the adjustment
228 * value of the already online CPU in this package, set it to that
231 if (bootval
!= ref
->adjusted
) {
232 cur
->adjusted
= ref
->adjusted
;
233 wrmsrl(MSR_IA32_TSC_ADJUST
, ref
->adjusted
);
236 * We have the TSCs forced to be in sync on this package. Skip sync
243 * Entry/exit counters that make sure that both CPUs
244 * run the measurement code at once:
246 static atomic_t start_count
;
247 static atomic_t stop_count
;
248 static atomic_t skip_test
;
249 static atomic_t test_runs
;
252 * We use a raw spinlock in this exceptional case, because
253 * we want to have the fastest, inlined, non-debug version
254 * of a critical section, to be able to prove TSC time-warps:
256 static arch_spinlock_t sync_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
258 static cycles_t last_tsc
;
259 static cycles_t max_warp
;
261 static int random_warps
;
264 * TSC-warp measurement loop running on both CPUs. This is not called
265 * if there is no TSC.
267 static cycles_t
check_tsc_warp(unsigned int timeout
)
269 cycles_t start
, now
, prev
, end
, cur_max_warp
= 0;
270 int i
, cur_warps
= 0;
272 start
= rdtsc_ordered();
274 * The measurement runs for 'timeout' msecs:
276 end
= start
+ (cycles_t
) tsc_khz
* timeout
;
280 * We take the global lock, measure TSC, save the
281 * previous TSC that was measured (possibly on
282 * another CPU) and update the previous TSC timestamp.
284 arch_spin_lock(&sync_lock
);
286 now
= rdtsc_ordered();
288 arch_spin_unlock(&sync_lock
);
291 * Be nice every now and then (and also check whether
292 * measurement is done [we also insert a 10 million
293 * loops safety exit, so we dont lock up in case the
294 * TSC readout is totally broken]):
296 if (unlikely(!(i
& 7))) {
297 if (now
> end
|| i
> 10000000)
300 touch_nmi_watchdog();
303 * Outside the critical section we can now see whether
304 * we saw a time-warp of the TSC going backwards:
306 if (unlikely(prev
> now
)) {
307 arch_spin_lock(&sync_lock
);
308 max_warp
= max(max_warp
, prev
- now
);
309 cur_max_warp
= max_warp
;
311 * Check whether this bounces back and forth. Only
312 * one CPU should observe time going backwards.
314 if (cur_warps
!= nr_warps
)
317 cur_warps
= nr_warps
;
318 arch_spin_unlock(&sync_lock
);
322 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
323 now
-start
, end
-start
);
328 * If the target CPU coming online doesn't have any of its core-siblings
329 * online, a timeout of 20msec will be used for the TSC-warp measurement
330 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
331 * information about this socket already (and this information grows as we
332 * have more and more logical-siblings in that socket).
334 * Ideally we should be able to skip the TSC sync check on the other
335 * core-siblings, if the first logical CPU in a socket passed the sync test.
336 * But as the TSC is per-logical CPU and can potentially be modified wrongly
337 * by the bios, TSC sync test for smaller duration should be able
338 * to catch such errors. Also this will catch the condition where all the
339 * cores in the socket don't get reset at the same time.
341 static inline unsigned int loop_timeout(int cpu
)
343 return (cpumask_weight(topology_core_cpumask(cpu
)) > 1) ? 2 : 20;
347 * Source CPU calls into this - it waits for the freshly booted
348 * target CPU to arrive and then starts the measurement:
350 void check_tsc_sync_source(int cpu
)
355 * No need to check if we already know that the TSC is not
356 * synchronized or if we have no TSC.
358 if (unsynchronized_tsc())
362 * Set the maximum number of test runs to
363 * 1 if the CPU does not provide the TSC_ADJUST MSR
364 * 3 if the MSR is available, so the target can try to adjust
366 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST
))
367 atomic_set(&test_runs
, 1);
369 atomic_set(&test_runs
, 3);
372 * Wait for the target to start or to skip the test:
374 while (atomic_read(&start_count
) != cpus
- 1) {
375 if (atomic_read(&skip_test
) > 0) {
376 atomic_set(&skip_test
, 0);
383 * Trigger the target to continue into the measurement too:
385 atomic_inc(&start_count
);
387 check_tsc_warp(loop_timeout(cpu
));
389 while (atomic_read(&stop_count
) != cpus
-1)
393 * If the test was successful set the number of runs to zero and
394 * stop. If not, decrement the number of runs an check if we can
395 * retry. In case of random warps no retry is attempted.
398 atomic_set(&test_runs
, 0);
400 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
401 smp_processor_id(), cpu
);
403 } else if (atomic_dec_and_test(&test_runs
) || random_warps
) {
404 /* Force it to 0 if random warps brought us here */
405 atomic_set(&test_runs
, 0);
407 pr_warn("TSC synchronization [CPU#%d -> CPU#%d]:\n",
408 smp_processor_id(), cpu
);
409 pr_warn("Measured %Ld cycles TSC warp between CPUs, "
410 "turning off TSC clock.\n", max_warp
);
412 pr_warn("TSC warped randomly between CPUs\n");
413 mark_tsc_unstable("check_tsc_sync_source failed");
417 * Reset it - just in case we boot another CPU later:
419 atomic_set(&start_count
, 0);
426 * Let the target continue with the bootup:
428 atomic_inc(&stop_count
);
431 * Retry, if there is a chance to do so.
433 if (atomic_read(&test_runs
) > 0)
438 * Freshly booted CPUs call into this:
440 void check_tsc_sync_target(void)
442 struct tsc_adjust
*cur
= this_cpu_ptr(&tsc_adjust
);
443 unsigned int cpu
= smp_processor_id();
444 cycles_t cur_max_warp
, gbl_max_warp
;
447 /* Also aborts if there is no TSC. */
448 if (unsynchronized_tsc())
452 * Store, verify and sanitize the TSC adjust register. If
453 * successful skip the test.
455 * The test is also skipped when the TSC is marked reliable. This
456 * is true for SoCs which have no fallback clocksource. On these
457 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
458 * register might have been wreckaged by the BIOS..
460 if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable
) {
461 atomic_inc(&skip_test
);
467 * Register this CPU's participation and wait for the
468 * source CPU to start the measurement:
470 atomic_inc(&start_count
);
471 while (atomic_read(&start_count
) != cpus
)
474 cur_max_warp
= check_tsc_warp(loop_timeout(cpu
));
477 * Store the maximum observed warp value for a potential retry:
479 gbl_max_warp
= max_warp
;
484 atomic_inc(&stop_count
);
487 * Wait for the source CPU to print stuff:
489 while (atomic_read(&stop_count
) != cpus
)
493 * Reset it for the next sync test:
495 atomic_set(&stop_count
, 0);
498 * Check the number of remaining test runs. If not zero, the test
499 * failed and a retry with adjusted TSC is possible. If zero the
500 * test was either successful or failed terminally.
502 if (!atomic_read(&test_runs
))
506 * If the warp value of this CPU is 0, then the other CPU
507 * observed time going backwards so this TSC was ahead and
508 * needs to move backwards.
511 cur_max_warp
= -gbl_max_warp
;
514 * Add the result to the previous adjustment value.
516 * The adjustment value is slightly off by the overhead of the
517 * sync mechanism (observed values are ~200 TSC cycles), but this
518 * really depends on CPU, node distance and frequency. So
519 * compensating for this is hard to get right. Experiments show
520 * that the warp is not longer detectable when the observed warp
521 * value is used. In the worst case the adjustment needs to go
522 * through a 3rd run for fine tuning.
524 cur
->adjusted
+= cur_max_warp
;
526 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
527 cpu
, cur_max_warp
, cur
->adjusted
);
529 wrmsrl(MSR_IA32_TSC_ADJUST
, cur
->adjusted
);
534 #endif /* CONFIG_SMP */