arch/x86/kernel/uv_time.c

   1 /*
   2  * SGI RTC clock/timer routines.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  *  Copyright (c) 2009 Silicon Graphics, Inc.  All Rights Reserved.
  19  *  Copyright (c) Dimitri Sivanich
  20  */
  21 #include <linux/clockchips.h>
  22
  23 #include <asm/uv/uv_mmrs.h>
  24 #include <asm/uv/uv_hub.h>
  25 #include <asm/uv/bios.h>
  26 #include <asm/uv/uv.h>
  27 #include <asm/apic.h>
  28 #include <asm/cpu.h>
  29
  30 #define RTC_NAME                "sgi_rtc"
  31
  32 static cycle_t uv_read_rtc(struct clocksource *cs);
  33 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
  34 static void uv_rtc_timer_setup(enum clock_event_mode,
  35                                 struct clock_event_device *);
  36
  37 static struct clocksource clocksource_uv = {
  38         .name           = RTC_NAME,
  39         .rating         = 400,
  40         .read           = uv_read_rtc,
  41         .mask           = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
  42         .shift          = 10,
  43         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  44 };
  45
  46 static struct clock_event_device clock_event_device_uv = {
  47         .name           = RTC_NAME,
  48         .features       = CLOCK_EVT_FEAT_ONESHOT,
  49         .shift          = 20,
  50         .rating         = 400,
  51         .irq            = -1,
  52         .set_next_event = uv_rtc_next_event,
  53         .set_mode       = uv_rtc_timer_setup,
  54         .event_handler  = NULL,
  55 };
  56
  57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
  58
  59 /* There is one of these allocated per node */
  60 struct uv_rtc_timer_head {
  61         spinlock_t      lock;
  62         /* next cpu waiting for timer, local node relative: */
  63         int             next_cpu;
  64         /* number of cpus on this node: */
  65         int             ncpus;
  66         struct {
  67                 int     lcpu;           /* systemwide logical cpu number */
  68                 u64     expires;        /* next timer expiration for this cpu */
  69         } cpu[1];
  70 };
  71
  72 /*
  73  * Access to uv_rtc_timer_head via blade id.
  74  */
  75 static struct uv_rtc_timer_head         **blade_info __read_mostly;
  76
  77 static int                              uv_rtc_evt_enable;
  78
  79 /*
  80  * Hardware interface routines
  81  */
  82
  83 /* Send IPIs to another node */
  84 static void uv_rtc_send_IPI(int cpu)
  85 {
  86         unsigned long apicid, val;
  87         int pnode;
  88
  89         apicid = cpu_physical_id(cpu);
  90         pnode = uv_apicid_to_pnode(apicid);
  91         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  92               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  93               (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
  94
  95         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  96 }
  97
  98 /* Check for an RTC interrupt pending */
  99 static int uv_intr_pending(int pnode)
 100 {
 101         return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
 102                 UVH_EVENT_OCCURRED0_RTC1_MASK;
 103 }
 104
 105 /* Setup interrupt and return non-zero if early expiration occurred. */
 106 static int uv_setup_intr(int cpu, u64 expires)
 107 {
 108         u64 val;
 109         int pnode = uv_cpu_to_pnode(cpu);
 110
 111         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 112                 UVH_RTC1_INT_CONFIG_M_MASK);
 113         uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
 114
 115         uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
 116                 UVH_EVENT_OCCURRED0_RTC1_MASK);
 117
 118         val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
 119                 ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
 120
 121         /* Set configuration */
 122         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
 123         /* Initialize comparator value */
 124         uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
 125
 126         if (uv_read_rtc(NULL) <= expires)
 127                 return 0;
 128
 129         return !uv_intr_pending(pnode);
 130 }
 131
 132 /*
 133  * Per-cpu timer tracking routines
 134  */
 135
 136 static __init void uv_rtc_deallocate_timers(void)
 137 {
 138         int bid;
 139
 140         for_each_possible_blade(bid) {
 141                 kfree(blade_info[bid]);
 142         }
 143         kfree(blade_info);
 144 }
 145
 146 /* Allocate per-node list of cpu timer expiration times. */
 147 static __init int uv_rtc_allocate_timers(void)
 148 {
 149         int cpu;
 150
 151         blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
 152         if (!blade_info)
 153                 return -ENOMEM;
 154         memset(blade_info, 0, uv_possible_blades * sizeof(void *));
 155
 156         for_each_present_cpu(cpu) {
 157                 int nid = cpu_to_node(cpu);
 158                 int bid = uv_cpu_to_blade_id(cpu);
 159                 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 160                 struct uv_rtc_timer_head *head = blade_info[bid];
 161
 162                 if (!head) {
 163                         head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
 164                                 (uv_blade_nr_possible_cpus(bid) *
 165                                         2 * sizeof(u64)),
 166                                 GFP_KERNEL, nid);
 167                         if (!head) {
 168                                 uv_rtc_deallocate_timers();
 169                                 return -ENOMEM;
 170                         }
 171                         spin_lock_init(&head->lock);
 172                         head->ncpus = uv_blade_nr_possible_cpus(bid);
 173                         head->next_cpu = -1;
 174                         blade_info[bid] = head;
 175                 }
 176
 177                 head->cpu[bcpu].lcpu = cpu;
 178                 head->cpu[bcpu].expires = ULLONG_MAX;
 179         }
 180
 181         return 0;
 182 }
 183
 184 /* Find and set the next expiring timer.  */
 185 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
 186 {
 187         u64 lowest = ULLONG_MAX;
 188         int c, bcpu = -1;
 189
 190         head->next_cpu = -1;
 191         for (c = 0; c < head->ncpus; c++) {
 192                 u64 exp = head->cpu[c].expires;
 193                 if (exp < lowest) {
 194                         bcpu = c;
 195                         lowest = exp;
 196                 }
 197         }
 198         if (bcpu >= 0) {
 199                 head->next_cpu = bcpu;
 200                 c = head->cpu[bcpu].lcpu;
 201                 if (uv_setup_intr(c, lowest))
 202                         /* If we didn't set it up in time, trigger */
 203                         uv_rtc_send_IPI(c);
 204         } else {
 205                 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 206                         UVH_RTC1_INT_CONFIG_M_MASK);
 207         }
 208 }
 209
 210 /*
 211  * Set expiration time for current cpu.
 212  *
 213  * Returns 1 if we missed the expiration time.
 214  */
 215 static int uv_rtc_set_timer(int cpu, u64 expires)
 216 {
 217         int pnode = uv_cpu_to_pnode(cpu);
 218         int bid = uv_cpu_to_blade_id(cpu);
 219         struct uv_rtc_timer_head *head = blade_info[bid];
 220         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 221         u64 *t = &head->cpu[bcpu].expires;
 222         unsigned long flags;
 223         int next_cpu;
 224
 225         spin_lock_irqsave(&head->lock, flags);
 226
 227         next_cpu = head->next_cpu;
 228         *t = expires;
 229
 230         /* Will this one be next to go off? */
 231         if (next_cpu < 0 || bcpu == next_cpu ||
 232                         expires < head->cpu[next_cpu].expires) {
 233                 head->next_cpu = bcpu;
 234                 if (uv_setup_intr(cpu, expires)) {
 235                         *t = ULLONG_MAX;
 236                         uv_rtc_find_next_timer(head, pnode);
 237                         spin_unlock_irqrestore(&head->lock, flags);
 238                         return -ETIME;
 239                 }
 240         }
 241
 242         spin_unlock_irqrestore(&head->lock, flags);
 243         return 0;
 244 }
 245
 246 /*
 247  * Unset expiration time for current cpu.
 248  *
 249  * Returns 1 if this timer was pending.
 250  */
 251 static int uv_rtc_unset_timer(int cpu, int force)
 252 {
 253         int pnode = uv_cpu_to_pnode(cpu);
 254         int bid = uv_cpu_to_blade_id(cpu);
 255         struct uv_rtc_timer_head *head = blade_info[bid];
 256         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 257         u64 *t = &head->cpu[bcpu].expires;
 258         unsigned long flags;
 259         int rc = 0;
 260
 261         spin_lock_irqsave(&head->lock, flags);
 262
 263         if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
 264                 rc = 1;
 265
 266         if (rc) {
 267                 *t = ULLONG_MAX;
 268                 /* Was the hardware setup for this timer? */
 269                 if (head->next_cpu == bcpu)
 270                         uv_rtc_find_next_timer(head, pnode);
 271         }
 272
 273         spin_unlock_irqrestore(&head->lock, flags);
 274
 275         return rc;
 276 }
 277
 278
 279 /*
 280  * Kernel interface routines.
 281  */
 282
 283 /*
 284  * Read the RTC.
 285  */
 286 static cycle_t uv_read_rtc(struct clocksource *cs)
 287 {
 288         return (cycle_t)uv_read_local_mmr(UVH_RTC);
 289 }
 290
 291 /*
 292  * Program the next event, relative to now
 293  */
 294 static int uv_rtc_next_event(unsigned long delta,
 295                              struct clock_event_device *ced)
 296 {
 297         int ced_cpu = cpumask_first(ced->cpumask);
 298
 299         return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
 300 }
 301
 302 /*
 303  * Setup the RTC timer in oneshot mode
 304  */
 305 static void uv_rtc_timer_setup(enum clock_event_mode mode,
 306                                struct clock_event_device *evt)
 307 {
 308         int ced_cpu = cpumask_first(evt->cpumask);
 309
 310         switch (mode) {
 311         case CLOCK_EVT_MODE_PERIODIC:
 312         case CLOCK_EVT_MODE_ONESHOT:
 313         case CLOCK_EVT_MODE_RESUME:
 314                 /* Nothing to do here yet */
 315                 break;
 316         case CLOCK_EVT_MODE_UNUSED:
 317         case CLOCK_EVT_MODE_SHUTDOWN:
 318                 uv_rtc_unset_timer(ced_cpu, 1);
 319                 break;
 320         }
 321 }
 322
 323 static void uv_rtc_interrupt(void)
 324 {
 325         int cpu = smp_processor_id();
 326         struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
 327
 328         if (!ced || !ced->event_handler)
 329                 return;
 330
 331         if (uv_rtc_unset_timer(cpu, 0) != 1)
 332                 return;
 333
 334         ced->event_handler(ced);
 335 }
 336
 337 static int __init uv_enable_evt_rtc(char *str)
 338 {
 339         uv_rtc_evt_enable = 1;
 340
 341         return 1;
 342 }
 343 __setup("uvrtcevt", uv_enable_evt_rtc);
 344
 345 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
 346 {
 347         struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
 348
 349         *ced = clock_event_device_uv;
 350         ced->cpumask = cpumask_of(smp_processor_id());
 351         clockevents_register_device(ced);
 352 }
 353
 354 static __init int uv_rtc_setup_clock(void)
 355 {
 356         int rc;
 357
 358         if (!is_uv_system())
 359                 return -ENODEV;
 360
 361         clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
 362                                 clocksource_uv.shift);
 363
 364         /* If single blade, prefer tsc */
 365         if (uv_num_possible_blades() == 1)
 366                 clocksource_uv.rating = 250;
 367
 368         rc = clocksource_register(&clocksource_uv);
 369         if (rc)
 370                 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
 371         else
 372                 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
 373                         sn_rtc_cycles_per_second/(unsigned long)1E6);
 374
 375         if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
 376                 return rc;
 377
 378         /* Setup and register clockevents */
 379         rc = uv_rtc_allocate_timers();
 380         if (rc)
 381                 goto error;
 382
 383         x86_platform_ipi_callback = uv_rtc_interrupt;
 384
 385         clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
 386                                 NSEC_PER_SEC, clock_event_device_uv.shift);
 387
 388         clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
 389                                                 sn_rtc_cycles_per_second;
 390
 391         clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
 392                                 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
 393
 394         rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
 395         if (rc) {
 396                 x86_platform_ipi_callback = NULL;
 397                 uv_rtc_deallocate_timers();
 398                 goto error;
 399         }
 400
 401         printk(KERN_INFO "UV RTC clockevents registered\n");
 402
 403         return 0;
 404
 405 error:
 406         clocksource_unregister(&clocksource_uv);
 407         printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
 408
 409         return rc;
 410 }
 411 arch_initcall(uv_rtc_setup_clock);