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KVM: x86 emulator: emulate LAHF
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27
28 #include "x86.h"
29 #include "tss.h"
30
31 /*
32 * Operand types
33 */
34 #define OpNone 0ull
35 #define OpImplicit 1ull /* No generic decode */
36 #define OpReg 2ull /* Register */
37 #define OpMem 3ull /* Memory */
38 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39 #define OpDI 5ull /* ES:DI/EDI/RDI */
40 #define OpMem64 6ull /* Memory, 64-bit */
41 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42 #define OpDX 8ull /* DX register */
43 #define OpCL 9ull /* CL register (for shifts) */
44 #define OpImmByte 10ull /* 8-bit sign extended immediate */
45 #define OpOne 11ull /* Implied 1 */
46 #define OpImm 12ull /* Sign extended immediate */
47 #define OpMem16 13ull /* Memory operand (16-bit). */
48 #define OpMem32 14ull /* Memory operand (32-bit). */
49 #define OpImmU 15ull /* Immediate operand, zero extended */
50 #define OpSI 16ull /* SI/ESI/RSI */
51 #define OpImmFAddr 17ull /* Immediate far address */
52 #define OpMemFAddr 18ull /* Far address in memory */
53 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
54 #define OpES 20ull /* ES */
55 #define OpCS 21ull /* CS */
56 #define OpSS 22ull /* SS */
57 #define OpDS 23ull /* DS */
58 #define OpFS 24ull /* FS */
59 #define OpGS 25ull /* GS */
60 #define OpMem8 26ull /* 8-bit zero extended memory operand */
61
62 #define OpBits 5 /* Width of operand field */
63 #define OpMask ((1ull << OpBits) - 1)
64
65 /*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74 /* Operand sizes: 8-bit operands or specified/overridden size. */
75 #define ByteOp (1<<0) /* 8-bit operands. */
76 /* Destination operand type. */
77 #define DstShift 1
78 #define ImplicitOps (OpImplicit << DstShift)
79 #define DstReg (OpReg << DstShift)
80 #define DstMem (OpMem << DstShift)
81 #define DstAcc (OpAcc << DstShift)
82 #define DstDI (OpDI << DstShift)
83 #define DstMem64 (OpMem64 << DstShift)
84 #define DstImmUByte (OpImmUByte << DstShift)
85 #define DstDX (OpDX << DstShift)
86 #define DstMask (OpMask << DstShift)
87 /* Source operand type. */
88 #define SrcShift 6
89 #define SrcNone (OpNone << SrcShift)
90 #define SrcReg (OpReg << SrcShift)
91 #define SrcMem (OpMem << SrcShift)
92 #define SrcMem16 (OpMem16 << SrcShift)
93 #define SrcMem32 (OpMem32 << SrcShift)
94 #define SrcImm (OpImm << SrcShift)
95 #define SrcImmByte (OpImmByte << SrcShift)
96 #define SrcOne (OpOne << SrcShift)
97 #define SrcImmUByte (OpImmUByte << SrcShift)
98 #define SrcImmU (OpImmU << SrcShift)
99 #define SrcSI (OpSI << SrcShift)
100 #define SrcImmFAddr (OpImmFAddr << SrcShift)
101 #define SrcMemFAddr (OpMemFAddr << SrcShift)
102 #define SrcAcc (OpAcc << SrcShift)
103 #define SrcImmU16 (OpImmU16 << SrcShift)
104 #define SrcDX (OpDX << SrcShift)
105 #define SrcMem8 (OpMem8 << SrcShift)
106 #define SrcMask (OpMask << SrcShift)
107 #define BitOp (1<<11)
108 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
109 #define String (1<<13) /* String instruction (rep capable) */
110 #define Stack (1<<14) /* Stack instruction (push/pop) */
111 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116 #define Sse (1<<18) /* SSE Vector instruction */
117 /* Generic ModRM decode. */
118 #define ModRM (1<<19)
119 /* Destination is only written; never read. */
120 #define Mov (1<<20)
121 /* Misc flags */
122 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
123 #define VendorSpecific (1<<22) /* Vendor specific instruction */
124 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
125 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
126 #define Undefined (1<<25) /* No Such Instruction */
127 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
128 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
129 #define No64 (1<<28)
130 #define PageTable (1 << 29) /* instruction used to write page table */
131 /* Source 2 operand type */
132 #define Src2Shift (30)
133 #define Src2None (OpNone << Src2Shift)
134 #define Src2CL (OpCL << Src2Shift)
135 #define Src2ImmByte (OpImmByte << Src2Shift)
136 #define Src2One (OpOne << Src2Shift)
137 #define Src2Imm (OpImm << Src2Shift)
138 #define Src2ES (OpES << Src2Shift)
139 #define Src2CS (OpCS << Src2Shift)
140 #define Src2SS (OpSS << Src2Shift)
141 #define Src2DS (OpDS << Src2Shift)
142 #define Src2FS (OpFS << Src2Shift)
143 #define Src2GS (OpGS << Src2Shift)
144 #define Src2Mask (OpMask << Src2Shift)
145 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
146 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
149
150 #define X2(x...) x, x
151 #define X3(x...) X2(x), x
152 #define X4(x...) X2(x), X2(x)
153 #define X5(x...) X4(x), x
154 #define X6(x...) X4(x), X2(x)
155 #define X7(x...) X4(x), X3(x)
156 #define X8(x...) X4(x), X4(x)
157 #define X16(x...) X8(x), X8(x)
158
159 struct opcode {
160 u64 flags : 56;
161 u64 intercept : 8;
162 union {
163 int (*execute)(struct x86_emulate_ctxt *ctxt);
164 struct opcode *group;
165 struct group_dual *gdual;
166 struct gprefix *gprefix;
167 } u;
168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
169 };
170
171 struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
174 };
175
176 struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181 };
182
183 /* EFLAGS bit definitions. */
184 #define EFLG_ID (1<<21)
185 #define EFLG_VIP (1<<20)
186 #define EFLG_VIF (1<<19)
187 #define EFLG_AC (1<<18)
188 #define EFLG_VM (1<<17)
189 #define EFLG_RF (1<<16)
190 #define EFLG_IOPL (3<<12)
191 #define EFLG_NT (1<<14)
192 #define EFLG_OF (1<<11)
193 #define EFLG_DF (1<<10)
194 #define EFLG_IF (1<<9)
195 #define EFLG_TF (1<<8)
196 #define EFLG_SF (1<<7)
197 #define EFLG_ZF (1<<6)
198 #define EFLG_AF (1<<4)
199 #define EFLG_PF (1<<2)
200 #define EFLG_CF (1<<0)
201
202 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203 #define EFLG_RESERVED_ONE_MASK 2
204
205 /*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
212 #if defined(CONFIG_X86_64)
213 #define _LO32 "k" /* force 32-bit operand */
214 #define _STK "%%rsp" /* stack pointer */
215 #elif defined(__i386__)
216 #define _LO32 "" /* force 32-bit operand */
217 #define _STK "%%esp" /* stack pointer */
218 #endif
219
220 /*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226 /* Before executing instruction: restore necessary bits in EFLAGS. */
227 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
242
243 /* After executing instruction: write-back necessary bits in EFLAGS. */
244 #define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
251 #ifdef CONFIG_X86_64
252 #define ON64(x) x
253 #else
254 #define ON64(x)
255 #endif
256
257 #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
265 "=&r" (_tmp) \
266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
267 } while (0)
268
269
270 /* Raw emulation: instruction has two explicit operands. */
271 #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
272 do { \
273 unsigned long _tmp; \
274 \
275 switch ((ctxt)->dst.bytes) { \
276 case 2: \
277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
278 break; \
279 case 4: \
280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
281 break; \
282 case 8: \
283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
284 break; \
285 } \
286 } while (0)
287
288 #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
289 do { \
290 unsigned long _tmp; \
291 switch ((ctxt)->dst.bytes) { \
292 case 1: \
293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
294 break; \
295 default: \
296 __emulate_2op_nobyte(ctxt, _op, \
297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302 /* Source operand is byte-sized and may be restricted to just %cl. */
303 #define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
305
306 /* Source operand is byte, word, long or quad sized. */
307 #define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
309
310 /* Source operand is word, long or quad sized. */
311 #define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
313
314 /* Instruction has three operands and one operand is stored in ECX register */
315 #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
316 do { \
317 unsigned long _tmp; \
318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
333 } while (0)
334
335 #define emulate_2op_cl(ctxt, _op) \
336 do { \
337 switch ((ctxt)->dst.bytes) { \
338 case 2: \
339 __emulate_2op_cl(ctxt, _op, "w", u16); \
340 break; \
341 case 4: \
342 __emulate_2op_cl(ctxt, _op, "l", u32); \
343 break; \
344 case 8: \
345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
346 break; \
347 } \
348 } while (0)
349
350 #define __emulate_1op(ctxt, _op, _suffix) \
351 do { \
352 unsigned long _tmp; \
353 \
354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363 /* Instruction has only one explicit operand (no source operand). */
364 #define emulate_1op(ctxt, _op) \
365 do { \
366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
371 } \
372 } while (0)
373
374 #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
375 do { \
376 unsigned long _tmp; \
377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
395 } while (0)
396
397 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
398 #define emulate_1op_rax_rdx(ctxt, _op, _ex) \
399 do { \
400 switch((ctxt)->src.bytes) { \
401 case 1: \
402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
403 break; \
404 case 2: \
405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
406 break; \
407 case 4: \
408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
409 break; \
410 case 8: ON64( \
411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
412 break; \
413 } \
414 } while (0)
415
416 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419 {
420 struct x86_instruction_info info = {
421 .intercept = intercept,
422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
430 .next_rip = ctxt->eip,
431 };
432
433 return ctxt->ops->intercept(ctxt, &info, stage);
434 }
435
436 static void assign_masked(ulong *dest, ulong src, ulong mask)
437 {
438 *dest = (*dest & ~mask) | (src & mask);
439 }
440
441 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
442 {
443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
444 }
445
446 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447 {
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455 }
456
457 /* Access/update address held in a register, based on addressing mode. */
458 static inline unsigned long
459 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
460 {
461 if (ctxt->ad_bytes == sizeof(unsigned long))
462 return reg;
463 else
464 return reg & ad_mask(ctxt);
465 }
466
467 static inline unsigned long
468 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
469 {
470 return address_mask(ctxt, reg);
471 }
472
473 static inline void
474 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
475 {
476 if (ctxt->ad_bytes == sizeof(unsigned long))
477 *reg += inc;
478 else
479 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
480 }
481
482 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
483 {
484 register_address_increment(ctxt, &ctxt->_eip, rel);
485 }
486
487 static u32 desc_limit_scaled(struct desc_struct *desc)
488 {
489 u32 limit = get_desc_limit(desc);
490
491 return desc->g ? (limit << 12) | 0xfff : limit;
492 }
493
494 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
495 {
496 ctxt->has_seg_override = true;
497 ctxt->seg_override = seg;
498 }
499
500 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
501 {
502 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
503 return 0;
504
505 return ctxt->ops->get_cached_segment_base(ctxt, seg);
506 }
507
508 static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
509 {
510 if (!ctxt->has_seg_override)
511 return 0;
512
513 return ctxt->seg_override;
514 }
515
516 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
517 u32 error, bool valid)
518 {
519 ctxt->exception.vector = vec;
520 ctxt->exception.error_code = error;
521 ctxt->exception.error_code_valid = valid;
522 return X86EMUL_PROPAGATE_FAULT;
523 }
524
525 static int emulate_db(struct x86_emulate_ctxt *ctxt)
526 {
527 return emulate_exception(ctxt, DB_VECTOR, 0, false);
528 }
529
530 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
531 {
532 return emulate_exception(ctxt, GP_VECTOR, err, true);
533 }
534
535 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
536 {
537 return emulate_exception(ctxt, SS_VECTOR, err, true);
538 }
539
540 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
541 {
542 return emulate_exception(ctxt, UD_VECTOR, 0, false);
543 }
544
545 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
546 {
547 return emulate_exception(ctxt, TS_VECTOR, err, true);
548 }
549
550 static int emulate_de(struct x86_emulate_ctxt *ctxt)
551 {
552 return emulate_exception(ctxt, DE_VECTOR, 0, false);
553 }
554
555 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
556 {
557 return emulate_exception(ctxt, NM_VECTOR, 0, false);
558 }
559
560 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
561 {
562 u16 selector;
563 struct desc_struct desc;
564
565 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
566 return selector;
567 }
568
569 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
570 unsigned seg)
571 {
572 u16 dummy;
573 u32 base3;
574 struct desc_struct desc;
575
576 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
577 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
578 }
579
580 /*
581 * x86 defines three classes of vector instructions: explicitly
582 * aligned, explicitly unaligned, and the rest, which change behaviour
583 * depending on whether they're AVX encoded or not.
584 *
585 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
586 * subject to the same check.
587 */
588 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
589 {
590 if (likely(size < 16))
591 return false;
592
593 if (ctxt->d & Aligned)
594 return true;
595 else if (ctxt->d & Unaligned)
596 return false;
597 else if (ctxt->d & Avx)
598 return false;
599 else
600 return true;
601 }
602
603 static int __linearize(struct x86_emulate_ctxt *ctxt,
604 struct segmented_address addr,
605 unsigned size, bool write, bool fetch,
606 ulong *linear)
607 {
608 struct desc_struct desc;
609 bool usable;
610 ulong la;
611 u32 lim;
612 u16 sel;
613 unsigned cpl, rpl;
614
615 la = seg_base(ctxt, addr.seg) + addr.ea;
616 switch (ctxt->mode) {
617 case X86EMUL_MODE_REAL:
618 break;
619 case X86EMUL_MODE_PROT64:
620 if (((signed long)la << 16) >> 16 != la)
621 return emulate_gp(ctxt, 0);
622 break;
623 default:
624 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
625 addr.seg);
626 if (!usable)
627 goto bad;
628 /* code segment or read-only data segment */
629 if (((desc.type & 8) || !(desc.type & 2)) && write)
630 goto bad;
631 /* unreadable code segment */
632 if (!fetch && (desc.type & 8) && !(desc.type & 2))
633 goto bad;
634 lim = desc_limit_scaled(&desc);
635 if ((desc.type & 8) || !(desc.type & 4)) {
636 /* expand-up segment */
637 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
638 goto bad;
639 } else {
640 /* exapand-down segment */
641 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
642 goto bad;
643 lim = desc.d ? 0xffffffff : 0xffff;
644 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
645 goto bad;
646 }
647 cpl = ctxt->ops->cpl(ctxt);
648 rpl = sel & 3;
649 cpl = max(cpl, rpl);
650 if (!(desc.type & 8)) {
651 /* data segment */
652 if (cpl > desc.dpl)
653 goto bad;
654 } else if ((desc.type & 8) && !(desc.type & 4)) {
655 /* nonconforming code segment */
656 if (cpl != desc.dpl)
657 goto bad;
658 } else if ((desc.type & 8) && (desc.type & 4)) {
659 /* conforming code segment */
660 if (cpl < desc.dpl)
661 goto bad;
662 }
663 break;
664 }
665 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
666 la &= (u32)-1;
667 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
668 return emulate_gp(ctxt, 0);
669 *linear = la;
670 return X86EMUL_CONTINUE;
671 bad:
672 if (addr.seg == VCPU_SREG_SS)
673 return emulate_ss(ctxt, addr.seg);
674 else
675 return emulate_gp(ctxt, addr.seg);
676 }
677
678 static int linearize(struct x86_emulate_ctxt *ctxt,
679 struct segmented_address addr,
680 unsigned size, bool write,
681 ulong *linear)
682 {
683 return __linearize(ctxt, addr, size, write, false, linear);
684 }
685
686
687 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
688 struct segmented_address addr,
689 void *data,
690 unsigned size)
691 {
692 int rc;
693 ulong linear;
694
695 rc = linearize(ctxt, addr, size, false, &linear);
696 if (rc != X86EMUL_CONTINUE)
697 return rc;
698 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
699 }
700
701 /*
702 * Fetch the next byte of the instruction being emulated which is pointed to
703 * by ctxt->_eip, then increment ctxt->_eip.
704 *
705 * Also prefetch the remaining bytes of the instruction without crossing page
706 * boundary if they are not in fetch_cache yet.
707 */
708 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
709 {
710 struct fetch_cache *fc = &ctxt->fetch;
711 int rc;
712 int size, cur_size;
713
714 if (ctxt->_eip == fc->end) {
715 unsigned long linear;
716 struct segmented_address addr = { .seg = VCPU_SREG_CS,
717 .ea = ctxt->_eip };
718 cur_size = fc->end - fc->start;
719 size = min(15UL - cur_size,
720 PAGE_SIZE - offset_in_page(ctxt->_eip));
721 rc = __linearize(ctxt, addr, size, false, true, &linear);
722 if (unlikely(rc != X86EMUL_CONTINUE))
723 return rc;
724 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
725 size, &ctxt->exception);
726 if (unlikely(rc != X86EMUL_CONTINUE))
727 return rc;
728 fc->end += size;
729 }
730 *dest = fc->data[ctxt->_eip - fc->start];
731 ctxt->_eip++;
732 return X86EMUL_CONTINUE;
733 }
734
735 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
736 void *dest, unsigned size)
737 {
738 int rc;
739
740 /* x86 instructions are limited to 15 bytes. */
741 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
742 return X86EMUL_UNHANDLEABLE;
743 while (size--) {
744 rc = do_insn_fetch_byte(ctxt, dest++);
745 if (rc != X86EMUL_CONTINUE)
746 return rc;
747 }
748 return X86EMUL_CONTINUE;
749 }
750
751 /* Fetch next part of the instruction being emulated. */
752 #define insn_fetch(_type, _ctxt) \
753 ({ unsigned long _x; \
754 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
755 if (rc != X86EMUL_CONTINUE) \
756 goto done; \
757 (_type)_x; \
758 })
759
760 #define insn_fetch_arr(_arr, _size, _ctxt) \
761 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
762 if (rc != X86EMUL_CONTINUE) \
763 goto done; \
764 })
765
766 /*
767 * Given the 'reg' portion of a ModRM byte, and a register block, return a
768 * pointer into the block that addresses the relevant register.
769 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
770 */
771 static void *decode_register(u8 modrm_reg, unsigned long *regs,
772 int highbyte_regs)
773 {
774 void *p;
775
776 p = &regs[modrm_reg];
777 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
778 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
779 return p;
780 }
781
782 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
783 struct segmented_address addr,
784 u16 *size, unsigned long *address, int op_bytes)
785 {
786 int rc;
787
788 if (op_bytes == 2)
789 op_bytes = 3;
790 *address = 0;
791 rc = segmented_read_std(ctxt, addr, size, 2);
792 if (rc != X86EMUL_CONTINUE)
793 return rc;
794 addr.ea += 2;
795 rc = segmented_read_std(ctxt, addr, address, op_bytes);
796 return rc;
797 }
798
799 static int test_cc(unsigned int condition, unsigned int flags)
800 {
801 int rc = 0;
802
803 switch ((condition & 15) >> 1) {
804 case 0: /* o */
805 rc |= (flags & EFLG_OF);
806 break;
807 case 1: /* b/c/nae */
808 rc |= (flags & EFLG_CF);
809 break;
810 case 2: /* z/e */
811 rc |= (flags & EFLG_ZF);
812 break;
813 case 3: /* be/na */
814 rc |= (flags & (EFLG_CF|EFLG_ZF));
815 break;
816 case 4: /* s */
817 rc |= (flags & EFLG_SF);
818 break;
819 case 5: /* p/pe */
820 rc |= (flags & EFLG_PF);
821 break;
822 case 7: /* le/ng */
823 rc |= (flags & EFLG_ZF);
824 /* fall through */
825 case 6: /* l/nge */
826 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
827 break;
828 }
829
830 /* Odd condition identifiers (lsb == 1) have inverted sense. */
831 return (!!rc ^ (condition & 1));
832 }
833
834 static void fetch_register_operand(struct operand *op)
835 {
836 switch (op->bytes) {
837 case 1:
838 op->val = *(u8 *)op->addr.reg;
839 break;
840 case 2:
841 op->val = *(u16 *)op->addr.reg;
842 break;
843 case 4:
844 op->val = *(u32 *)op->addr.reg;
845 break;
846 case 8:
847 op->val = *(u64 *)op->addr.reg;
848 break;
849 }
850 }
851
852 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
853 {
854 ctxt->ops->get_fpu(ctxt);
855 switch (reg) {
856 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
857 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
858 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
859 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
860 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
861 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
862 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
863 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
864 #ifdef CONFIG_X86_64
865 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
866 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
867 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
868 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
869 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
870 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
871 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
872 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
873 #endif
874 default: BUG();
875 }
876 ctxt->ops->put_fpu(ctxt);
877 }
878
879 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
880 int reg)
881 {
882 ctxt->ops->get_fpu(ctxt);
883 switch (reg) {
884 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
885 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
886 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
887 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
888 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
889 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
890 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
891 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
892 #ifdef CONFIG_X86_64
893 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
894 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
895 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
896 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
897 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
898 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
899 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
900 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
901 #endif
902 default: BUG();
903 }
904 ctxt->ops->put_fpu(ctxt);
905 }
906
907 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
908 {
909 ctxt->ops->get_fpu(ctxt);
910 switch (reg) {
911 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
912 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
913 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
914 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
915 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
916 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
917 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
918 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
919 default: BUG();
920 }
921 ctxt->ops->put_fpu(ctxt);
922 }
923
924 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
925 {
926 ctxt->ops->get_fpu(ctxt);
927 switch (reg) {
928 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
929 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
930 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
931 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
932 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
933 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
934 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
935 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
936 default: BUG();
937 }
938 ctxt->ops->put_fpu(ctxt);
939 }
940
941 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
942 struct operand *op)
943 {
944 unsigned reg = ctxt->modrm_reg;
945 int highbyte_regs = ctxt->rex_prefix == 0;
946
947 if (!(ctxt->d & ModRM))
948 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
949
950 if (ctxt->d & Sse) {
951 op->type = OP_XMM;
952 op->bytes = 16;
953 op->addr.xmm = reg;
954 read_sse_reg(ctxt, &op->vec_val, reg);
955 return;
956 }
957 if (ctxt->d & Mmx) {
958 reg &= 7;
959 op->type = OP_MM;
960 op->bytes = 8;
961 op->addr.mm = reg;
962 return;
963 }
964
965 op->type = OP_REG;
966 if (ctxt->d & ByteOp) {
967 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
968 op->bytes = 1;
969 } else {
970 op->addr.reg = decode_register(reg, ctxt->regs, 0);
971 op->bytes = ctxt->op_bytes;
972 }
973 fetch_register_operand(op);
974 op->orig_val = op->val;
975 }
976
977 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
978 {
979 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
980 ctxt->modrm_seg = VCPU_SREG_SS;
981 }
982
983 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
984 struct operand *op)
985 {
986 u8 sib;
987 int index_reg = 0, base_reg = 0, scale;
988 int rc = X86EMUL_CONTINUE;
989 ulong modrm_ea = 0;
990
991 if (ctxt->rex_prefix) {
992 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
993 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
994 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
995 }
996
997 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
998 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
999 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1000 ctxt->modrm_seg = VCPU_SREG_DS;
1001
1002 if (ctxt->modrm_mod == 3) {
1003 op->type = OP_REG;
1004 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1005 op->addr.reg = decode_register(ctxt->modrm_rm,
1006 ctxt->regs, ctxt->d & ByteOp);
1007 if (ctxt->d & Sse) {
1008 op->type = OP_XMM;
1009 op->bytes = 16;
1010 op->addr.xmm = ctxt->modrm_rm;
1011 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1012 return rc;
1013 }
1014 if (ctxt->d & Mmx) {
1015 op->type = OP_MM;
1016 op->bytes = 8;
1017 op->addr.xmm = ctxt->modrm_rm & 7;
1018 return rc;
1019 }
1020 fetch_register_operand(op);
1021 return rc;
1022 }
1023
1024 op->type = OP_MEM;
1025
1026 if (ctxt->ad_bytes == 2) {
1027 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1028 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1029 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1030 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1031
1032 /* 16-bit ModR/M decode. */
1033 switch (ctxt->modrm_mod) {
1034 case 0:
1035 if (ctxt->modrm_rm == 6)
1036 modrm_ea += insn_fetch(u16, ctxt);
1037 break;
1038 case 1:
1039 modrm_ea += insn_fetch(s8, ctxt);
1040 break;
1041 case 2:
1042 modrm_ea += insn_fetch(u16, ctxt);
1043 break;
1044 }
1045 switch (ctxt->modrm_rm) {
1046 case 0:
1047 modrm_ea += bx + si;
1048 break;
1049 case 1:
1050 modrm_ea += bx + di;
1051 break;
1052 case 2:
1053 modrm_ea += bp + si;
1054 break;
1055 case 3:
1056 modrm_ea += bp + di;
1057 break;
1058 case 4:
1059 modrm_ea += si;
1060 break;
1061 case 5:
1062 modrm_ea += di;
1063 break;
1064 case 6:
1065 if (ctxt->modrm_mod != 0)
1066 modrm_ea += bp;
1067 break;
1068 case 7:
1069 modrm_ea += bx;
1070 break;
1071 }
1072 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1073 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1074 ctxt->modrm_seg = VCPU_SREG_SS;
1075 modrm_ea = (u16)modrm_ea;
1076 } else {
1077 /* 32/64-bit ModR/M decode. */
1078 if ((ctxt->modrm_rm & 7) == 4) {
1079 sib = insn_fetch(u8, ctxt);
1080 index_reg |= (sib >> 3) & 7;
1081 base_reg |= sib & 7;
1082 scale = sib >> 6;
1083
1084 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1085 modrm_ea += insn_fetch(s32, ctxt);
1086 else {
1087 modrm_ea += ctxt->regs[base_reg];
1088 adjust_modrm_seg(ctxt, base_reg);
1089 }
1090 if (index_reg != 4)
1091 modrm_ea += ctxt->regs[index_reg] << scale;
1092 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1093 if (ctxt->mode == X86EMUL_MODE_PROT64)
1094 ctxt->rip_relative = 1;
1095 } else {
1096 base_reg = ctxt->modrm_rm;
1097 modrm_ea += ctxt->regs[base_reg];
1098 adjust_modrm_seg(ctxt, base_reg);
1099 }
1100 switch (ctxt->modrm_mod) {
1101 case 0:
1102 if (ctxt->modrm_rm == 5)
1103 modrm_ea += insn_fetch(s32, ctxt);
1104 break;
1105 case 1:
1106 modrm_ea += insn_fetch(s8, ctxt);
1107 break;
1108 case 2:
1109 modrm_ea += insn_fetch(s32, ctxt);
1110 break;
1111 }
1112 }
1113 op->addr.mem.ea = modrm_ea;
1114 done:
1115 return rc;
1116 }
1117
1118 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1119 struct operand *op)
1120 {
1121 int rc = X86EMUL_CONTINUE;
1122
1123 op->type = OP_MEM;
1124 switch (ctxt->ad_bytes) {
1125 case 2:
1126 op->addr.mem.ea = insn_fetch(u16, ctxt);
1127 break;
1128 case 4:
1129 op->addr.mem.ea = insn_fetch(u32, ctxt);
1130 break;
1131 case 8:
1132 op->addr.mem.ea = insn_fetch(u64, ctxt);
1133 break;
1134 }
1135 done:
1136 return rc;
1137 }
1138
1139 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1140 {
1141 long sv = 0, mask;
1142
1143 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1144 mask = ~(ctxt->dst.bytes * 8 - 1);
1145
1146 if (ctxt->src.bytes == 2)
1147 sv = (s16)ctxt->src.val & (s16)mask;
1148 else if (ctxt->src.bytes == 4)
1149 sv = (s32)ctxt->src.val & (s32)mask;
1150
1151 ctxt->dst.addr.mem.ea += (sv >> 3);
1152 }
1153
1154 /* only subword offset */
1155 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1156 }
1157
1158 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1159 unsigned long addr, void *dest, unsigned size)
1160 {
1161 int rc;
1162 struct read_cache *mc = &ctxt->mem_read;
1163
1164 while (size) {
1165 int n = min(size, 8u);
1166 size -= n;
1167 if (mc->pos < mc->end)
1168 goto read_cached;
1169
1170 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1171 &ctxt->exception);
1172 if (rc != X86EMUL_CONTINUE)
1173 return rc;
1174 mc->end += n;
1175
1176 read_cached:
1177 memcpy(dest, mc->data + mc->pos, n);
1178 mc->pos += n;
1179 dest += n;
1180 addr += n;
1181 }
1182 return X86EMUL_CONTINUE;
1183 }
1184
1185 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1186 struct segmented_address addr,
1187 void *data,
1188 unsigned size)
1189 {
1190 int rc;
1191 ulong linear;
1192
1193 rc = linearize(ctxt, addr, size, false, &linear);
1194 if (rc != X86EMUL_CONTINUE)
1195 return rc;
1196 return read_emulated(ctxt, linear, data, size);
1197 }
1198
1199 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1200 struct segmented_address addr,
1201 const void *data,
1202 unsigned size)
1203 {
1204 int rc;
1205 ulong linear;
1206
1207 rc = linearize(ctxt, addr, size, true, &linear);
1208 if (rc != X86EMUL_CONTINUE)
1209 return rc;
1210 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1211 &ctxt->exception);
1212 }
1213
1214 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1215 struct segmented_address addr,
1216 const void *orig_data, const void *data,
1217 unsigned size)
1218 {
1219 int rc;
1220 ulong linear;
1221
1222 rc = linearize(ctxt, addr, size, true, &linear);
1223 if (rc != X86EMUL_CONTINUE)
1224 return rc;
1225 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1226 size, &ctxt->exception);
1227 }
1228
1229 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1230 unsigned int size, unsigned short port,
1231 void *dest)
1232 {
1233 struct read_cache *rc = &ctxt->io_read;
1234
1235 if (rc->pos == rc->end) { /* refill pio read ahead */
1236 unsigned int in_page, n;
1237 unsigned int count = ctxt->rep_prefix ?
1238 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
1239 in_page = (ctxt->eflags & EFLG_DF) ?
1240 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1241 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
1242 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1243 count);
1244 if (n == 0)
1245 n = 1;
1246 rc->pos = rc->end = 0;
1247 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1248 return 0;
1249 rc->end = n * size;
1250 }
1251
1252 memcpy(dest, rc->data + rc->pos, size);
1253 rc->pos += size;
1254 return 1;
1255 }
1256
1257 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1258 u16 index, struct desc_struct *desc)
1259 {
1260 struct desc_ptr dt;
1261 ulong addr;
1262
1263 ctxt->ops->get_idt(ctxt, &dt);
1264
1265 if (dt.size < index * 8 + 7)
1266 return emulate_gp(ctxt, index << 3 | 0x2);
1267
1268 addr = dt.address + index * 8;
1269 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1270 &ctxt->exception);
1271 }
1272
1273 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1274 u16 selector, struct desc_ptr *dt)
1275 {
1276 struct x86_emulate_ops *ops = ctxt->ops;
1277
1278 if (selector & 1 << 2) {
1279 struct desc_struct desc;
1280 u16 sel;
1281
1282 memset (dt, 0, sizeof *dt);
1283 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1284 return;
1285
1286 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1287 dt->address = get_desc_base(&desc);
1288 } else
1289 ops->get_gdt(ctxt, dt);
1290 }
1291
1292 /* allowed just for 8 bytes segments */
1293 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1294 u16 selector, struct desc_struct *desc)
1295 {
1296 struct desc_ptr dt;
1297 u16 index = selector >> 3;
1298 ulong addr;
1299
1300 get_descriptor_table_ptr(ctxt, selector, &dt);
1301
1302 if (dt.size < index * 8 + 7)
1303 return emulate_gp(ctxt, selector & 0xfffc);
1304
1305 addr = dt.address + index * 8;
1306 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1307 &ctxt->exception);
1308 }
1309
1310 /* allowed just for 8 bytes segments */
1311 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1312 u16 selector, struct desc_struct *desc)
1313 {
1314 struct desc_ptr dt;
1315 u16 index = selector >> 3;
1316 ulong addr;
1317
1318 get_descriptor_table_ptr(ctxt, selector, &dt);
1319
1320 if (dt.size < index * 8 + 7)
1321 return emulate_gp(ctxt, selector & 0xfffc);
1322
1323 addr = dt.address + index * 8;
1324 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1325 &ctxt->exception);
1326 }
1327
1328 /* Does not support long mode */
1329 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1330 u16 selector, int seg)
1331 {
1332 struct desc_struct seg_desc;
1333 u8 dpl, rpl, cpl;
1334 unsigned err_vec = GP_VECTOR;
1335 u32 err_code = 0;
1336 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1337 int ret;
1338
1339 memset(&seg_desc, 0, sizeof seg_desc);
1340
1341 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1342 || ctxt->mode == X86EMUL_MODE_REAL) {
1343 /* set real mode segment descriptor */
1344 set_desc_base(&seg_desc, selector << 4);
1345 set_desc_limit(&seg_desc, 0xffff);
1346 seg_desc.type = 3;
1347 seg_desc.p = 1;
1348 seg_desc.s = 1;
1349 if (ctxt->mode == X86EMUL_MODE_VM86)
1350 seg_desc.dpl = 3;
1351 goto load;
1352 }
1353
1354 rpl = selector & 3;
1355 cpl = ctxt->ops->cpl(ctxt);
1356
1357 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1358 if ((seg == VCPU_SREG_CS
1359 || (seg == VCPU_SREG_SS
1360 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1361 || seg == VCPU_SREG_TR)
1362 && null_selector)
1363 goto exception;
1364
1365 /* TR should be in GDT only */
1366 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1367 goto exception;
1368
1369 if (null_selector) /* for NULL selector skip all following checks */
1370 goto load;
1371
1372 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
1373 if (ret != X86EMUL_CONTINUE)
1374 return ret;
1375
1376 err_code = selector & 0xfffc;
1377 err_vec = GP_VECTOR;
1378
1379 /* can't load system descriptor into segment selecor */
1380 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1381 goto exception;
1382
1383 if (!seg_desc.p) {
1384 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1385 goto exception;
1386 }
1387
1388 dpl = seg_desc.dpl;
1389
1390 switch (seg) {
1391 case VCPU_SREG_SS:
1392 /*
1393 * segment is not a writable data segment or segment
1394 * selector's RPL != CPL or segment selector's RPL != CPL
1395 */
1396 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1397 goto exception;
1398 break;
1399 case VCPU_SREG_CS:
1400 if (!(seg_desc.type & 8))
1401 goto exception;
1402
1403 if (seg_desc.type & 4) {
1404 /* conforming */
1405 if (dpl > cpl)
1406 goto exception;
1407 } else {
1408 /* nonconforming */
1409 if (rpl > cpl || dpl != cpl)
1410 goto exception;
1411 }
1412 /* CS(RPL) <- CPL */
1413 selector = (selector & 0xfffc) | cpl;
1414 break;
1415 case VCPU_SREG_TR:
1416 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1417 goto exception;
1418 break;
1419 case VCPU_SREG_LDTR:
1420 if (seg_desc.s || seg_desc.type != 2)
1421 goto exception;
1422 break;
1423 default: /* DS, ES, FS, or GS */
1424 /*
1425 * segment is not a data or readable code segment or
1426 * ((segment is a data or nonconforming code segment)
1427 * and (both RPL and CPL > DPL))
1428 */
1429 if ((seg_desc.type & 0xa) == 0x8 ||
1430 (((seg_desc.type & 0xc) != 0xc) &&
1431 (rpl > dpl && cpl > dpl)))
1432 goto exception;
1433 break;
1434 }
1435
1436 if (seg_desc.s) {
1437 /* mark segment as accessed */
1438 seg_desc.type |= 1;
1439 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1440 if (ret != X86EMUL_CONTINUE)
1441 return ret;
1442 }
1443 load:
1444 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1445 return X86EMUL_CONTINUE;
1446 exception:
1447 emulate_exception(ctxt, err_vec, err_code, true);
1448 return X86EMUL_PROPAGATE_FAULT;
1449 }
1450
1451 static void write_register_operand(struct operand *op)
1452 {
1453 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1454 switch (op->bytes) {
1455 case 1:
1456 *(u8 *)op->addr.reg = (u8)op->val;
1457 break;
1458 case 2:
1459 *(u16 *)op->addr.reg = (u16)op->val;
1460 break;
1461 case 4:
1462 *op->addr.reg = (u32)op->val;
1463 break; /* 64b: zero-extend */
1464 case 8:
1465 *op->addr.reg = op->val;
1466 break;
1467 }
1468 }
1469
1470 static int writeback(struct x86_emulate_ctxt *ctxt)
1471 {
1472 int rc;
1473
1474 switch (ctxt->dst.type) {
1475 case OP_REG:
1476 write_register_operand(&ctxt->dst);
1477 break;
1478 case OP_MEM:
1479 if (ctxt->lock_prefix)
1480 rc = segmented_cmpxchg(ctxt,
1481 ctxt->dst.addr.mem,
1482 &ctxt->dst.orig_val,
1483 &ctxt->dst.val,
1484 ctxt->dst.bytes);
1485 else
1486 rc = segmented_write(ctxt,
1487 ctxt->dst.addr.mem,
1488 &ctxt->dst.val,
1489 ctxt->dst.bytes);
1490 if (rc != X86EMUL_CONTINUE)
1491 return rc;
1492 break;
1493 case OP_XMM:
1494 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1495 break;
1496 case OP_MM:
1497 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1498 break;
1499 case OP_NONE:
1500 /* no writeback */
1501 break;
1502 default:
1503 break;
1504 }
1505 return X86EMUL_CONTINUE;
1506 }
1507
1508 static int em_push(struct x86_emulate_ctxt *ctxt)
1509 {
1510 struct segmented_address addr;
1511
1512 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1513 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1514 addr.seg = VCPU_SREG_SS;
1515
1516 /* Disable writeback. */
1517 ctxt->dst.type = OP_NONE;
1518 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
1519 }
1520
1521 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1522 void *dest, int len)
1523 {
1524 int rc;
1525 struct segmented_address addr;
1526
1527 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1528 addr.seg = VCPU_SREG_SS;
1529 rc = segmented_read(ctxt, addr, dest, len);
1530 if (rc != X86EMUL_CONTINUE)
1531 return rc;
1532
1533 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
1534 return rc;
1535 }
1536
1537 static int em_pop(struct x86_emulate_ctxt *ctxt)
1538 {
1539 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1540 }
1541
1542 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1543 void *dest, int len)
1544 {
1545 int rc;
1546 unsigned long val, change_mask;
1547 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1548 int cpl = ctxt->ops->cpl(ctxt);
1549
1550 rc = emulate_pop(ctxt, &val, len);
1551 if (rc != X86EMUL_CONTINUE)
1552 return rc;
1553
1554 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1555 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1556
1557 switch(ctxt->mode) {
1558 case X86EMUL_MODE_PROT64:
1559 case X86EMUL_MODE_PROT32:
1560 case X86EMUL_MODE_PROT16:
1561 if (cpl == 0)
1562 change_mask |= EFLG_IOPL;
1563 if (cpl <= iopl)
1564 change_mask |= EFLG_IF;
1565 break;
1566 case X86EMUL_MODE_VM86:
1567 if (iopl < 3)
1568 return emulate_gp(ctxt, 0);
1569 change_mask |= EFLG_IF;
1570 break;
1571 default: /* real mode */
1572 change_mask |= (EFLG_IOPL | EFLG_IF);
1573 break;
1574 }
1575
1576 *(unsigned long *)dest =
1577 (ctxt->eflags & ~change_mask) | (val & change_mask);
1578
1579 return rc;
1580 }
1581
1582 static int em_popf(struct x86_emulate_ctxt *ctxt)
1583 {
1584 ctxt->dst.type = OP_REG;
1585 ctxt->dst.addr.reg = &ctxt->eflags;
1586 ctxt->dst.bytes = ctxt->op_bytes;
1587 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1588 }
1589
1590 static int em_leave(struct x86_emulate_ctxt *ctxt)
1591 {
1592 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1593 stack_mask(ctxt));
1594 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1595 }
1596
1597 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1598 {
1599 int seg = ctxt->src2.val;
1600
1601 ctxt->src.val = get_segment_selector(ctxt, seg);
1602
1603 return em_push(ctxt);
1604 }
1605
1606 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1607 {
1608 int seg = ctxt->src2.val;
1609 unsigned long selector;
1610 int rc;
1611
1612 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1613 if (rc != X86EMUL_CONTINUE)
1614 return rc;
1615
1616 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1617 return rc;
1618 }
1619
1620 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1621 {
1622 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
1623 int rc = X86EMUL_CONTINUE;
1624 int reg = VCPU_REGS_RAX;
1625
1626 while (reg <= VCPU_REGS_RDI) {
1627 (reg == VCPU_REGS_RSP) ?
1628 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
1629
1630 rc = em_push(ctxt);
1631 if (rc != X86EMUL_CONTINUE)
1632 return rc;
1633
1634 ++reg;
1635 }
1636
1637 return rc;
1638 }
1639
1640 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1641 {
1642 ctxt->src.val = (unsigned long)ctxt->eflags;
1643 return em_push(ctxt);
1644 }
1645
1646 static int em_popa(struct x86_emulate_ctxt *ctxt)
1647 {
1648 int rc = X86EMUL_CONTINUE;
1649 int reg = VCPU_REGS_RDI;
1650
1651 while (reg >= VCPU_REGS_RAX) {
1652 if (reg == VCPU_REGS_RSP) {
1653 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1654 ctxt->op_bytes);
1655 --reg;
1656 }
1657
1658 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
1659 if (rc != X86EMUL_CONTINUE)
1660 break;
1661 --reg;
1662 }
1663 return rc;
1664 }
1665
1666 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1667 {
1668 struct x86_emulate_ops *ops = ctxt->ops;
1669 int rc;
1670 struct desc_ptr dt;
1671 gva_t cs_addr;
1672 gva_t eip_addr;
1673 u16 cs, eip;
1674
1675 /* TODO: Add limit checks */
1676 ctxt->src.val = ctxt->eflags;
1677 rc = em_push(ctxt);
1678 if (rc != X86EMUL_CONTINUE)
1679 return rc;
1680
1681 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1682
1683 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1684 rc = em_push(ctxt);
1685 if (rc != X86EMUL_CONTINUE)
1686 return rc;
1687
1688 ctxt->src.val = ctxt->_eip;
1689 rc = em_push(ctxt);
1690 if (rc != X86EMUL_CONTINUE)
1691 return rc;
1692
1693 ops->get_idt(ctxt, &dt);
1694
1695 eip_addr = dt.address + (irq << 2);
1696 cs_addr = dt.address + (irq << 2) + 2;
1697
1698 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1699 if (rc != X86EMUL_CONTINUE)
1700 return rc;
1701
1702 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1703 if (rc != X86EMUL_CONTINUE)
1704 return rc;
1705
1706 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1707 if (rc != X86EMUL_CONTINUE)
1708 return rc;
1709
1710 ctxt->_eip = eip;
1711
1712 return rc;
1713 }
1714
1715 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1716 {
1717 switch(ctxt->mode) {
1718 case X86EMUL_MODE_REAL:
1719 return emulate_int_real(ctxt, irq);
1720 case X86EMUL_MODE_VM86:
1721 case X86EMUL_MODE_PROT16:
1722 case X86EMUL_MODE_PROT32:
1723 case X86EMUL_MODE_PROT64:
1724 default:
1725 /* Protected mode interrupts unimplemented yet */
1726 return X86EMUL_UNHANDLEABLE;
1727 }
1728 }
1729
1730 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1731 {
1732 int rc = X86EMUL_CONTINUE;
1733 unsigned long temp_eip = 0;
1734 unsigned long temp_eflags = 0;
1735 unsigned long cs = 0;
1736 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1737 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1738 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1739 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1740
1741 /* TODO: Add stack limit check */
1742
1743 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1744
1745 if (rc != X86EMUL_CONTINUE)
1746 return rc;
1747
1748 if (temp_eip & ~0xffff)
1749 return emulate_gp(ctxt, 0);
1750
1751 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1752
1753 if (rc != X86EMUL_CONTINUE)
1754 return rc;
1755
1756 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1757
1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
1760
1761 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1762
1763 if (rc != X86EMUL_CONTINUE)
1764 return rc;
1765
1766 ctxt->_eip = temp_eip;
1767
1768
1769 if (ctxt->op_bytes == 4)
1770 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1771 else if (ctxt->op_bytes == 2) {
1772 ctxt->eflags &= ~0xffff;
1773 ctxt->eflags |= temp_eflags;
1774 }
1775
1776 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1777 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1778
1779 return rc;
1780 }
1781
1782 static int em_iret(struct x86_emulate_ctxt *ctxt)
1783 {
1784 switch(ctxt->mode) {
1785 case X86EMUL_MODE_REAL:
1786 return emulate_iret_real(ctxt);
1787 case X86EMUL_MODE_VM86:
1788 case X86EMUL_MODE_PROT16:
1789 case X86EMUL_MODE_PROT32:
1790 case X86EMUL_MODE_PROT64:
1791 default:
1792 /* iret from protected mode unimplemented yet */
1793 return X86EMUL_UNHANDLEABLE;
1794 }
1795 }
1796
1797 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1798 {
1799 int rc;
1800 unsigned short sel;
1801
1802 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1803
1804 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1805 if (rc != X86EMUL_CONTINUE)
1806 return rc;
1807
1808 ctxt->_eip = 0;
1809 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1810 return X86EMUL_CONTINUE;
1811 }
1812
1813 static int em_grp2(struct x86_emulate_ctxt *ctxt)
1814 {
1815 switch (ctxt->modrm_reg) {
1816 case 0: /* rol */
1817 emulate_2op_SrcB(ctxt, "rol");
1818 break;
1819 case 1: /* ror */
1820 emulate_2op_SrcB(ctxt, "ror");
1821 break;
1822 case 2: /* rcl */
1823 emulate_2op_SrcB(ctxt, "rcl");
1824 break;
1825 case 3: /* rcr */
1826 emulate_2op_SrcB(ctxt, "rcr");
1827 break;
1828 case 4: /* sal/shl */
1829 case 6: /* sal/shl */
1830 emulate_2op_SrcB(ctxt, "sal");
1831 break;
1832 case 5: /* shr */
1833 emulate_2op_SrcB(ctxt, "shr");
1834 break;
1835 case 7: /* sar */
1836 emulate_2op_SrcB(ctxt, "sar");
1837 break;
1838 }
1839 return X86EMUL_CONTINUE;
1840 }
1841
1842 static int em_not(struct x86_emulate_ctxt *ctxt)
1843 {
1844 ctxt->dst.val = ~ctxt->dst.val;
1845 return X86EMUL_CONTINUE;
1846 }
1847
1848 static int em_neg(struct x86_emulate_ctxt *ctxt)
1849 {
1850 emulate_1op(ctxt, "neg");
1851 return X86EMUL_CONTINUE;
1852 }
1853
1854 static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1855 {
1856 u8 ex = 0;
1857
1858 emulate_1op_rax_rdx(ctxt, "mul", ex);
1859 return X86EMUL_CONTINUE;
1860 }
1861
1862 static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1863 {
1864 u8 ex = 0;
1865
1866 emulate_1op_rax_rdx(ctxt, "imul", ex);
1867 return X86EMUL_CONTINUE;
1868 }
1869
1870 static int em_div_ex(struct x86_emulate_ctxt *ctxt)
1871 {
1872 u8 de = 0;
1873
1874 emulate_1op_rax_rdx(ctxt, "div", de);
1875 if (de)
1876 return emulate_de(ctxt);
1877 return X86EMUL_CONTINUE;
1878 }
1879
1880 static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1881 {
1882 u8 de = 0;
1883
1884 emulate_1op_rax_rdx(ctxt, "idiv", de);
1885 if (de)
1886 return emulate_de(ctxt);
1887 return X86EMUL_CONTINUE;
1888 }
1889
1890 static int em_grp45(struct x86_emulate_ctxt *ctxt)
1891 {
1892 int rc = X86EMUL_CONTINUE;
1893
1894 switch (ctxt->modrm_reg) {
1895 case 0: /* inc */
1896 emulate_1op(ctxt, "inc");
1897 break;
1898 case 1: /* dec */
1899 emulate_1op(ctxt, "dec");
1900 break;
1901 case 2: /* call near abs */ {
1902 long int old_eip;
1903 old_eip = ctxt->_eip;
1904 ctxt->_eip = ctxt->src.val;
1905 ctxt->src.val = old_eip;
1906 rc = em_push(ctxt);
1907 break;
1908 }
1909 case 4: /* jmp abs */
1910 ctxt->_eip = ctxt->src.val;
1911 break;
1912 case 5: /* jmp far */
1913 rc = em_jmp_far(ctxt);
1914 break;
1915 case 6: /* push */
1916 rc = em_push(ctxt);
1917 break;
1918 }
1919 return rc;
1920 }
1921
1922 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
1923 {
1924 u64 old = ctxt->dst.orig_val64;
1925
1926 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1927 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1928 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1929 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1930 ctxt->eflags &= ~EFLG_ZF;
1931 } else {
1932 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1933 (u32) ctxt->regs[VCPU_REGS_RBX];
1934
1935 ctxt->eflags |= EFLG_ZF;
1936 }
1937 return X86EMUL_CONTINUE;
1938 }
1939
1940 static int em_ret(struct x86_emulate_ctxt *ctxt)
1941 {
1942 ctxt->dst.type = OP_REG;
1943 ctxt->dst.addr.reg = &ctxt->_eip;
1944 ctxt->dst.bytes = ctxt->op_bytes;
1945 return em_pop(ctxt);
1946 }
1947
1948 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
1949 {
1950 int rc;
1951 unsigned long cs;
1952
1953 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1954 if (rc != X86EMUL_CONTINUE)
1955 return rc;
1956 if (ctxt->op_bytes == 4)
1957 ctxt->_eip = (u32)ctxt->_eip;
1958 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1959 if (rc != X86EMUL_CONTINUE)
1960 return rc;
1961 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1962 return rc;
1963 }
1964
1965 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1966 {
1967 /* Save real source value, then compare EAX against destination. */
1968 ctxt->src.orig_val = ctxt->src.val;
1969 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1970 emulate_2op_SrcV(ctxt, "cmp");
1971
1972 if (ctxt->eflags & EFLG_ZF) {
1973 /* Success: write back to memory. */
1974 ctxt->dst.val = ctxt->src.orig_val;
1975 } else {
1976 /* Failure: write the value we saw to EAX. */
1977 ctxt->dst.type = OP_REG;
1978 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1979 }
1980 return X86EMUL_CONTINUE;
1981 }
1982
1983 static int em_lseg(struct x86_emulate_ctxt *ctxt)
1984 {
1985 int seg = ctxt->src2.val;
1986 unsigned short sel;
1987 int rc;
1988
1989 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1990
1991 rc = load_segment_descriptor(ctxt, sel, seg);
1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
1994
1995 ctxt->dst.val = ctxt->src.val;
1996 return rc;
1997 }
1998
1999 static void
2000 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2001 struct desc_struct *cs, struct desc_struct *ss)
2002 {
2003 u16 selector;
2004
2005 memset(cs, 0, sizeof(struct desc_struct));
2006 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
2007 memset(ss, 0, sizeof(struct desc_struct));
2008
2009 cs->l = 0; /* will be adjusted later */
2010 set_desc_base(cs, 0); /* flat segment */
2011 cs->g = 1; /* 4kb granularity */
2012 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2013 cs->type = 0x0b; /* Read, Execute, Accessed */
2014 cs->s = 1;
2015 cs->dpl = 0; /* will be adjusted later */
2016 cs->p = 1;
2017 cs->d = 1;
2018
2019 set_desc_base(ss, 0); /* flat segment */
2020 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2021 ss->g = 1; /* 4kb granularity */
2022 ss->s = 1;
2023 ss->type = 0x03; /* Read/Write, Accessed */
2024 ss->d = 1; /* 32bit stack segment */
2025 ss->dpl = 0;
2026 ss->p = 1;
2027 }
2028
2029 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2030 {
2031 u32 eax, ebx, ecx, edx;
2032
2033 eax = ecx = 0;
2034 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2035 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2036 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2037 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2038 }
2039
2040 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2041 {
2042 struct x86_emulate_ops *ops = ctxt->ops;
2043 u32 eax, ebx, ecx, edx;
2044
2045 /*
2046 * syscall should always be enabled in longmode - so only become
2047 * vendor specific (cpuid) if other modes are active...
2048 */
2049 if (ctxt->mode == X86EMUL_MODE_PROT64)
2050 return true;
2051
2052 eax = 0x00000000;
2053 ecx = 0x00000000;
2054 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2055 /*
2056 * Intel ("GenuineIntel")
2057 * remark: Intel CPUs only support "syscall" in 64bit
2058 * longmode. Also an 64bit guest with a
2059 * 32bit compat-app running will #UD !! While this
2060 * behaviour can be fixed (by emulating) into AMD
2061 * response - CPUs of AMD can't behave like Intel.
2062 */
2063 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2064 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2065 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2066 return false;
2067
2068 /* AMD ("AuthenticAMD") */
2069 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2070 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2071 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2072 return true;
2073
2074 /* AMD ("AMDisbetter!") */
2075 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2076 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2077 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2078 return true;
2079
2080 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2081 return false;
2082 }
2083
2084 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2085 {
2086 struct x86_emulate_ops *ops = ctxt->ops;
2087 struct desc_struct cs, ss;
2088 u64 msr_data;
2089 u16 cs_sel, ss_sel;
2090 u64 efer = 0;
2091
2092 /* syscall is not available in real mode */
2093 if (ctxt->mode == X86EMUL_MODE_REAL ||
2094 ctxt->mode == X86EMUL_MODE_VM86)
2095 return emulate_ud(ctxt);
2096
2097 if (!(em_syscall_is_enabled(ctxt)))
2098 return emulate_ud(ctxt);
2099
2100 ops->get_msr(ctxt, MSR_EFER, &efer);
2101 setup_syscalls_segments(ctxt, &cs, &ss);
2102
2103 if (!(efer & EFER_SCE))
2104 return emulate_ud(ctxt);
2105
2106 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2107 msr_data >>= 32;
2108 cs_sel = (u16)(msr_data & 0xfffc);
2109 ss_sel = (u16)(msr_data + 8);
2110
2111 if (efer & EFER_LMA) {
2112 cs.d = 0;
2113 cs.l = 1;
2114 }
2115 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2116 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2117
2118 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
2119 if (efer & EFER_LMA) {
2120 #ifdef CONFIG_X86_64
2121 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2122
2123 ops->get_msr(ctxt,
2124 ctxt->mode == X86EMUL_MODE_PROT64 ?
2125 MSR_LSTAR : MSR_CSTAR, &msr_data);
2126 ctxt->_eip = msr_data;
2127
2128 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2129 ctxt->eflags &= ~(msr_data | EFLG_RF);
2130 #endif
2131 } else {
2132 /* legacy mode */
2133 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2134 ctxt->_eip = (u32)msr_data;
2135
2136 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2137 }
2138
2139 return X86EMUL_CONTINUE;
2140 }
2141
2142 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2143 {
2144 struct x86_emulate_ops *ops = ctxt->ops;
2145 struct desc_struct cs, ss;
2146 u64 msr_data;
2147 u16 cs_sel, ss_sel;
2148 u64 efer = 0;
2149
2150 ops->get_msr(ctxt, MSR_EFER, &efer);
2151 /* inject #GP if in real mode */
2152 if (ctxt->mode == X86EMUL_MODE_REAL)
2153 return emulate_gp(ctxt, 0);
2154
2155 /*
2156 * Not recognized on AMD in compat mode (but is recognized in legacy
2157 * mode).
2158 */
2159 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2160 && !vendor_intel(ctxt))
2161 return emulate_ud(ctxt);
2162
2163 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2164 * Therefore, we inject an #UD.
2165 */
2166 if (ctxt->mode == X86EMUL_MODE_PROT64)
2167 return emulate_ud(ctxt);
2168
2169 setup_syscalls_segments(ctxt, &cs, &ss);
2170
2171 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2172 switch (ctxt->mode) {
2173 case X86EMUL_MODE_PROT32:
2174 if ((msr_data & 0xfffc) == 0x0)
2175 return emulate_gp(ctxt, 0);
2176 break;
2177 case X86EMUL_MODE_PROT64:
2178 if (msr_data == 0x0)
2179 return emulate_gp(ctxt, 0);
2180 break;
2181 }
2182
2183 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2184 cs_sel = (u16)msr_data;
2185 cs_sel &= ~SELECTOR_RPL_MASK;
2186 ss_sel = cs_sel + 8;
2187 ss_sel &= ~SELECTOR_RPL_MASK;
2188 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2189 cs.d = 0;
2190 cs.l = 1;
2191 }
2192
2193 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2194 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2195
2196 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2197 ctxt->_eip = msr_data;
2198
2199 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2200 ctxt->regs[VCPU_REGS_RSP] = msr_data;
2201
2202 return X86EMUL_CONTINUE;
2203 }
2204
2205 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2206 {
2207 struct x86_emulate_ops *ops = ctxt->ops;
2208 struct desc_struct cs, ss;
2209 u64 msr_data;
2210 int usermode;
2211 u16 cs_sel = 0, ss_sel = 0;
2212
2213 /* inject #GP if in real mode or Virtual 8086 mode */
2214 if (ctxt->mode == X86EMUL_MODE_REAL ||
2215 ctxt->mode == X86EMUL_MODE_VM86)
2216 return emulate_gp(ctxt, 0);
2217
2218 setup_syscalls_segments(ctxt, &cs, &ss);
2219
2220 if ((ctxt->rex_prefix & 0x8) != 0x0)
2221 usermode = X86EMUL_MODE_PROT64;
2222 else
2223 usermode = X86EMUL_MODE_PROT32;
2224
2225 cs.dpl = 3;
2226 ss.dpl = 3;
2227 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2228 switch (usermode) {
2229 case X86EMUL_MODE_PROT32:
2230 cs_sel = (u16)(msr_data + 16);
2231 if ((msr_data & 0xfffc) == 0x0)
2232 return emulate_gp(ctxt, 0);
2233 ss_sel = (u16)(msr_data + 24);
2234 break;
2235 case X86EMUL_MODE_PROT64:
2236 cs_sel = (u16)(msr_data + 32);
2237 if (msr_data == 0x0)
2238 return emulate_gp(ctxt, 0);
2239 ss_sel = cs_sel + 8;
2240 cs.d = 0;
2241 cs.l = 1;
2242 break;
2243 }
2244 cs_sel |= SELECTOR_RPL_MASK;
2245 ss_sel |= SELECTOR_RPL_MASK;
2246
2247 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2248 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2249
2250 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2251 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
2252
2253 return X86EMUL_CONTINUE;
2254 }
2255
2256 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2257 {
2258 int iopl;
2259 if (ctxt->mode == X86EMUL_MODE_REAL)
2260 return false;
2261 if (ctxt->mode == X86EMUL_MODE_VM86)
2262 return true;
2263 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2264 return ctxt->ops->cpl(ctxt) > iopl;
2265 }
2266
2267 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2268 u16 port, u16 len)
2269 {
2270 struct x86_emulate_ops *ops = ctxt->ops;
2271 struct desc_struct tr_seg;
2272 u32 base3;
2273 int r;
2274 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2275 unsigned mask = (1 << len) - 1;
2276 unsigned long base;
2277
2278 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2279 if (!tr_seg.p)
2280 return false;
2281 if (desc_limit_scaled(&tr_seg) < 103)
2282 return false;
2283 base = get_desc_base(&tr_seg);
2284 #ifdef CONFIG_X86_64
2285 base |= ((u64)base3) << 32;
2286 #endif
2287 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2288 if (r != X86EMUL_CONTINUE)
2289 return false;
2290 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2291 return false;
2292 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2293 if (r != X86EMUL_CONTINUE)
2294 return false;
2295 if ((perm >> bit_idx) & mask)
2296 return false;
2297 return true;
2298 }
2299
2300 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2301 u16 port, u16 len)
2302 {
2303 if (ctxt->perm_ok)
2304 return true;
2305
2306 if (emulator_bad_iopl(ctxt))
2307 if (!emulator_io_port_access_allowed(ctxt, port, len))
2308 return false;
2309
2310 ctxt->perm_ok = true;
2311
2312 return true;
2313 }
2314
2315 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2316 struct tss_segment_16 *tss)
2317 {
2318 tss->ip = ctxt->_eip;
2319 tss->flag = ctxt->eflags;
2320 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2321 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2322 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2323 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2324 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2325 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2326 tss->si = ctxt->regs[VCPU_REGS_RSI];
2327 tss->di = ctxt->regs[VCPU_REGS_RDI];
2328
2329 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2330 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2331 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2332 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2333 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2334 }
2335
2336 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2337 struct tss_segment_16 *tss)
2338 {
2339 int ret;
2340
2341 ctxt->_eip = tss->ip;
2342 ctxt->eflags = tss->flag | 2;
2343 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2344 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2345 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2346 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2347 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2348 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2349 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2350 ctxt->regs[VCPU_REGS_RDI] = tss->di;
2351
2352 /*
2353 * SDM says that segment selectors are loaded before segment
2354 * descriptors
2355 */
2356 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2357 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2358 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2359 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2360 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2361
2362 /*
2363 * Now load segment descriptors. If fault happenes at this stage
2364 * it is handled in a context of new task
2365 */
2366 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2367 if (ret != X86EMUL_CONTINUE)
2368 return ret;
2369 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2370 if (ret != X86EMUL_CONTINUE)
2371 return ret;
2372 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2373 if (ret != X86EMUL_CONTINUE)
2374 return ret;
2375 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
2378 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2379 if (ret != X86EMUL_CONTINUE)
2380 return ret;
2381
2382 return X86EMUL_CONTINUE;
2383 }
2384
2385 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2386 u16 tss_selector, u16 old_tss_sel,
2387 ulong old_tss_base, struct desc_struct *new_desc)
2388 {
2389 struct x86_emulate_ops *ops = ctxt->ops;
2390 struct tss_segment_16 tss_seg;
2391 int ret;
2392 u32 new_tss_base = get_desc_base(new_desc);
2393
2394 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2395 &ctxt->exception);
2396 if (ret != X86EMUL_CONTINUE)
2397 /* FIXME: need to provide precise fault address */
2398 return ret;
2399
2400 save_state_to_tss16(ctxt, &tss_seg);
2401
2402 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2403 &ctxt->exception);
2404 if (ret != X86EMUL_CONTINUE)
2405 /* FIXME: need to provide precise fault address */
2406 return ret;
2407
2408 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2409 &ctxt->exception);
2410 if (ret != X86EMUL_CONTINUE)
2411 /* FIXME: need to provide precise fault address */
2412 return ret;
2413
2414 if (old_tss_sel != 0xffff) {
2415 tss_seg.prev_task_link = old_tss_sel;
2416
2417 ret = ops->write_std(ctxt, new_tss_base,
2418 &tss_seg.prev_task_link,
2419 sizeof tss_seg.prev_task_link,
2420 &ctxt->exception);
2421 if (ret != X86EMUL_CONTINUE)
2422 /* FIXME: need to provide precise fault address */
2423 return ret;
2424 }
2425
2426 return load_state_from_tss16(ctxt, &tss_seg);
2427 }
2428
2429 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2430 struct tss_segment_32 *tss)
2431 {
2432 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2433 tss->eip = ctxt->_eip;
2434 tss->eflags = ctxt->eflags;
2435 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2436 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2437 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2438 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2439 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2440 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2441 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2442 tss->edi = ctxt->regs[VCPU_REGS_RDI];
2443
2444 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2445 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2446 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2447 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2448 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2449 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2450 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2451 }
2452
2453 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2454 struct tss_segment_32 *tss)
2455 {
2456 int ret;
2457
2458 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2459 return emulate_gp(ctxt, 0);
2460 ctxt->_eip = tss->eip;
2461 ctxt->eflags = tss->eflags | 2;
2462
2463 /* General purpose registers */
2464 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2465 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2466 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2467 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2468 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2469 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2470 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2471 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
2472
2473 /*
2474 * SDM says that segment selectors are loaded before segment
2475 * descriptors
2476 */
2477 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2478 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2479 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2480 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2481 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2482 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2483 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2484
2485 /*
2486 * If we're switching between Protected Mode and VM86, we need to make
2487 * sure to update the mode before loading the segment descriptors so
2488 * that the selectors are interpreted correctly.
2489 *
2490 * Need to get rflags to the vcpu struct immediately because it
2491 * influences the CPL which is checked at least when loading the segment
2492 * descriptors and when pushing an error code to the new kernel stack.
2493 *
2494 * TODO Introduce a separate ctxt->ops->set_cpl callback
2495 */
2496 if (ctxt->eflags & X86_EFLAGS_VM)
2497 ctxt->mode = X86EMUL_MODE_VM86;
2498 else
2499 ctxt->mode = X86EMUL_MODE_PROT32;
2500
2501 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2502
2503 /*
2504 * Now load segment descriptors. If fault happenes at this stage
2505 * it is handled in a context of new task
2506 */
2507 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2508 if (ret != X86EMUL_CONTINUE)
2509 return ret;
2510 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2511 if (ret != X86EMUL_CONTINUE)
2512 return ret;
2513 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2514 if (ret != X86EMUL_CONTINUE)
2515 return ret;
2516 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2517 if (ret != X86EMUL_CONTINUE)
2518 return ret;
2519 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2520 if (ret != X86EMUL_CONTINUE)
2521 return ret;
2522 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2523 if (ret != X86EMUL_CONTINUE)
2524 return ret;
2525 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2526 if (ret != X86EMUL_CONTINUE)
2527 return ret;
2528
2529 return X86EMUL_CONTINUE;
2530 }
2531
2532 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2533 u16 tss_selector, u16 old_tss_sel,
2534 ulong old_tss_base, struct desc_struct *new_desc)
2535 {
2536 struct x86_emulate_ops *ops = ctxt->ops;
2537 struct tss_segment_32 tss_seg;
2538 int ret;
2539 u32 new_tss_base = get_desc_base(new_desc);
2540
2541 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2542 &ctxt->exception);
2543 if (ret != X86EMUL_CONTINUE)
2544 /* FIXME: need to provide precise fault address */
2545 return ret;
2546
2547 save_state_to_tss32(ctxt, &tss_seg);
2548
2549 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2550 &ctxt->exception);
2551 if (ret != X86EMUL_CONTINUE)
2552 /* FIXME: need to provide precise fault address */
2553 return ret;
2554
2555 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2556 &ctxt->exception);
2557 if (ret != X86EMUL_CONTINUE)
2558 /* FIXME: need to provide precise fault address */
2559 return ret;
2560
2561 if (old_tss_sel != 0xffff) {
2562 tss_seg.prev_task_link = old_tss_sel;
2563
2564 ret = ops->write_std(ctxt, new_tss_base,
2565 &tss_seg.prev_task_link,
2566 sizeof tss_seg.prev_task_link,
2567 &ctxt->exception);
2568 if (ret != X86EMUL_CONTINUE)
2569 /* FIXME: need to provide precise fault address */
2570 return ret;
2571 }
2572
2573 return load_state_from_tss32(ctxt, &tss_seg);
2574 }
2575
2576 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2577 u16 tss_selector, int idt_index, int reason,
2578 bool has_error_code, u32 error_code)
2579 {
2580 struct x86_emulate_ops *ops = ctxt->ops;
2581 struct desc_struct curr_tss_desc, next_tss_desc;
2582 int ret;
2583 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2584 ulong old_tss_base =
2585 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2586 u32 desc_limit;
2587
2588 /* FIXME: old_tss_base == ~0 ? */
2589
2590 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
2593 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2594 if (ret != X86EMUL_CONTINUE)
2595 return ret;
2596
2597 /* FIXME: check that next_tss_desc is tss */
2598
2599 /*
2600 * Check privileges. The three cases are task switch caused by...
2601 *
2602 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2603 * 2. Exception/IRQ/iret: No check is performed
2604 * 3. jmp/call to TSS: Check agains DPL of the TSS
2605 */
2606 if (reason == TASK_SWITCH_GATE) {
2607 if (idt_index != -1) {
2608 /* Software interrupts */
2609 struct desc_struct task_gate_desc;
2610 int dpl;
2611
2612 ret = read_interrupt_descriptor(ctxt, idt_index,
2613 &task_gate_desc);
2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
2616
2617 dpl = task_gate_desc.dpl;
2618 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2619 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2620 }
2621 } else if (reason != TASK_SWITCH_IRET) {
2622 int dpl = next_tss_desc.dpl;
2623 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2624 return emulate_gp(ctxt, tss_selector);
2625 }
2626
2627
2628 desc_limit = desc_limit_scaled(&next_tss_desc);
2629 if (!next_tss_desc.p ||
2630 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2631 desc_limit < 0x2b)) {
2632 emulate_ts(ctxt, tss_selector & 0xfffc);
2633 return X86EMUL_PROPAGATE_FAULT;
2634 }
2635
2636 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2637 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2638 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2639 }
2640
2641 if (reason == TASK_SWITCH_IRET)
2642 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2643
2644 /* set back link to prev task only if NT bit is set in eflags
2645 note that old_tss_sel is not used afetr this point */
2646 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2647 old_tss_sel = 0xffff;
2648
2649 if (next_tss_desc.type & 8)
2650 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2651 old_tss_base, &next_tss_desc);
2652 else
2653 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2654 old_tss_base, &next_tss_desc);
2655 if (ret != X86EMUL_CONTINUE)
2656 return ret;
2657
2658 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2659 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2660
2661 if (reason != TASK_SWITCH_IRET) {
2662 next_tss_desc.type |= (1 << 1); /* set busy flag */
2663 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2664 }
2665
2666 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2667 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2668
2669 if (has_error_code) {
2670 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2671 ctxt->lock_prefix = 0;
2672 ctxt->src.val = (unsigned long) error_code;
2673 ret = em_push(ctxt);
2674 }
2675
2676 return ret;
2677 }
2678
2679 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2680 u16 tss_selector, int idt_index, int reason,
2681 bool has_error_code, u32 error_code)
2682 {
2683 int rc;
2684
2685 ctxt->_eip = ctxt->eip;
2686 ctxt->dst.type = OP_NONE;
2687
2688 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2689 has_error_code, error_code);
2690
2691 if (rc == X86EMUL_CONTINUE)
2692 ctxt->eip = ctxt->_eip;
2693
2694 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2695 }
2696
2697 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2698 int reg, struct operand *op)
2699 {
2700 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2701
2702 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2703 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
2704 op->addr.mem.seg = seg;
2705 }
2706
2707 static int em_das(struct x86_emulate_ctxt *ctxt)
2708 {
2709 u8 al, old_al;
2710 bool af, cf, old_cf;
2711
2712 cf = ctxt->eflags & X86_EFLAGS_CF;
2713 al = ctxt->dst.val;
2714
2715 old_al = al;
2716 old_cf = cf;
2717 cf = false;
2718 af = ctxt->eflags & X86_EFLAGS_AF;
2719 if ((al & 0x0f) > 9 || af) {
2720 al -= 6;
2721 cf = old_cf | (al >= 250);
2722 af = true;
2723 } else {
2724 af = false;
2725 }
2726 if (old_al > 0x99 || old_cf) {
2727 al -= 0x60;
2728 cf = true;
2729 }
2730
2731 ctxt->dst.val = al;
2732 /* Set PF, ZF, SF */
2733 ctxt->src.type = OP_IMM;
2734 ctxt->src.val = 0;
2735 ctxt->src.bytes = 1;
2736 emulate_2op_SrcV(ctxt, "or");
2737 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2738 if (cf)
2739 ctxt->eflags |= X86_EFLAGS_CF;
2740 if (af)
2741 ctxt->eflags |= X86_EFLAGS_AF;
2742 return X86EMUL_CONTINUE;
2743 }
2744
2745 static int em_call(struct x86_emulate_ctxt *ctxt)
2746 {
2747 long rel = ctxt->src.val;
2748
2749 ctxt->src.val = (unsigned long)ctxt->_eip;
2750 jmp_rel(ctxt, rel);
2751 return em_push(ctxt);
2752 }
2753
2754 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2755 {
2756 u16 sel, old_cs;
2757 ulong old_eip;
2758 int rc;
2759
2760 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2761 old_eip = ctxt->_eip;
2762
2763 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2764 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2765 return X86EMUL_CONTINUE;
2766
2767 ctxt->_eip = 0;
2768 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2769
2770 ctxt->src.val = old_cs;
2771 rc = em_push(ctxt);
2772 if (rc != X86EMUL_CONTINUE)
2773 return rc;
2774
2775 ctxt->src.val = old_eip;
2776 return em_push(ctxt);
2777 }
2778
2779 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2780 {
2781 int rc;
2782
2783 ctxt->dst.type = OP_REG;
2784 ctxt->dst.addr.reg = &ctxt->_eip;
2785 ctxt->dst.bytes = ctxt->op_bytes;
2786 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2787 if (rc != X86EMUL_CONTINUE)
2788 return rc;
2789 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
2790 return X86EMUL_CONTINUE;
2791 }
2792
2793 static int em_add(struct x86_emulate_ctxt *ctxt)
2794 {
2795 emulate_2op_SrcV(ctxt, "add");
2796 return X86EMUL_CONTINUE;
2797 }
2798
2799 static int em_or(struct x86_emulate_ctxt *ctxt)
2800 {
2801 emulate_2op_SrcV(ctxt, "or");
2802 return X86EMUL_CONTINUE;
2803 }
2804
2805 static int em_adc(struct x86_emulate_ctxt *ctxt)
2806 {
2807 emulate_2op_SrcV(ctxt, "adc");
2808 return X86EMUL_CONTINUE;
2809 }
2810
2811 static int em_sbb(struct x86_emulate_ctxt *ctxt)
2812 {
2813 emulate_2op_SrcV(ctxt, "sbb");
2814 return X86EMUL_CONTINUE;
2815 }
2816
2817 static int em_and(struct x86_emulate_ctxt *ctxt)
2818 {
2819 emulate_2op_SrcV(ctxt, "and");
2820 return X86EMUL_CONTINUE;
2821 }
2822
2823 static int em_sub(struct x86_emulate_ctxt *ctxt)
2824 {
2825 emulate_2op_SrcV(ctxt, "sub");
2826 return X86EMUL_CONTINUE;
2827 }
2828
2829 static int em_xor(struct x86_emulate_ctxt *ctxt)
2830 {
2831 emulate_2op_SrcV(ctxt, "xor");
2832 return X86EMUL_CONTINUE;
2833 }
2834
2835 static int em_cmp(struct x86_emulate_ctxt *ctxt)
2836 {
2837 emulate_2op_SrcV(ctxt, "cmp");
2838 /* Disable writeback. */
2839 ctxt->dst.type = OP_NONE;
2840 return X86EMUL_CONTINUE;
2841 }
2842
2843 static int em_test(struct x86_emulate_ctxt *ctxt)
2844 {
2845 emulate_2op_SrcV(ctxt, "test");
2846 /* Disable writeback. */
2847 ctxt->dst.type = OP_NONE;
2848 return X86EMUL_CONTINUE;
2849 }
2850
2851 static int em_xchg(struct x86_emulate_ctxt *ctxt)
2852 {
2853 /* Write back the register source. */
2854 ctxt->src.val = ctxt->dst.val;
2855 write_register_operand(&ctxt->src);
2856
2857 /* Write back the memory destination with implicit LOCK prefix. */
2858 ctxt->dst.val = ctxt->src.orig_val;
2859 ctxt->lock_prefix = 1;
2860 return X86EMUL_CONTINUE;
2861 }
2862
2863 static int em_imul(struct x86_emulate_ctxt *ctxt)
2864 {
2865 emulate_2op_SrcV_nobyte(ctxt, "imul");
2866 return X86EMUL_CONTINUE;
2867 }
2868
2869 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2870 {
2871 ctxt->dst.val = ctxt->src2.val;
2872 return em_imul(ctxt);
2873 }
2874
2875 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2876 {
2877 ctxt->dst.type = OP_REG;
2878 ctxt->dst.bytes = ctxt->src.bytes;
2879 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2880 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2881
2882 return X86EMUL_CONTINUE;
2883 }
2884
2885 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2886 {
2887 u64 tsc = 0;
2888
2889 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2890 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2891 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
2892 return X86EMUL_CONTINUE;
2893 }
2894
2895 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2896 {
2897 u64 pmc;
2898
2899 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2900 return emulate_gp(ctxt, 0);
2901 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2902 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2903 return X86EMUL_CONTINUE;
2904 }
2905
2906 static int em_mov(struct x86_emulate_ctxt *ctxt)
2907 {
2908 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
2909 return X86EMUL_CONTINUE;
2910 }
2911
2912 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2913 {
2914 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2915 return emulate_gp(ctxt, 0);
2916
2917 /* Disable writeback. */
2918 ctxt->dst.type = OP_NONE;
2919 return X86EMUL_CONTINUE;
2920 }
2921
2922 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2923 {
2924 unsigned long val;
2925
2926 if (ctxt->mode == X86EMUL_MODE_PROT64)
2927 val = ctxt->src.val & ~0ULL;
2928 else
2929 val = ctxt->src.val & ~0U;
2930
2931 /* #UD condition is already handled. */
2932 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2933 return emulate_gp(ctxt, 0);
2934
2935 /* Disable writeback. */
2936 ctxt->dst.type = OP_NONE;
2937 return X86EMUL_CONTINUE;
2938 }
2939
2940 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2941 {
2942 u64 msr_data;
2943
2944 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2945 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2946 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2947 return emulate_gp(ctxt, 0);
2948
2949 return X86EMUL_CONTINUE;
2950 }
2951
2952 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2953 {
2954 u64 msr_data;
2955
2956 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2957 return emulate_gp(ctxt, 0);
2958
2959 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2960 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2961 return X86EMUL_CONTINUE;
2962 }
2963
2964 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2965 {
2966 if (ctxt->modrm_reg > VCPU_SREG_GS)
2967 return emulate_ud(ctxt);
2968
2969 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
2970 return X86EMUL_CONTINUE;
2971 }
2972
2973 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2974 {
2975 u16 sel = ctxt->src.val;
2976
2977 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
2978 return emulate_ud(ctxt);
2979
2980 if (ctxt->modrm_reg == VCPU_SREG_SS)
2981 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2982
2983 /* Disable writeback. */
2984 ctxt->dst.type = OP_NONE;
2985 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
2986 }
2987
2988 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2989 {
2990 int rc;
2991 ulong linear;
2992
2993 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
2994 if (rc == X86EMUL_CONTINUE)
2995 ctxt->ops->invlpg(ctxt, linear);
2996 /* Disable writeback. */
2997 ctxt->dst.type = OP_NONE;
2998 return X86EMUL_CONTINUE;
2999 }
3000
3001 static int em_clts(struct x86_emulate_ctxt *ctxt)
3002 {
3003 ulong cr0;
3004
3005 cr0 = ctxt->ops->get_cr(ctxt, 0);
3006 cr0 &= ~X86_CR0_TS;
3007 ctxt->ops->set_cr(ctxt, 0, cr0);
3008 return X86EMUL_CONTINUE;
3009 }
3010
3011 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3012 {
3013 int rc;
3014
3015 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3016 return X86EMUL_UNHANDLEABLE;
3017
3018 rc = ctxt->ops->fix_hypercall(ctxt);
3019 if (rc != X86EMUL_CONTINUE)
3020 return rc;
3021
3022 /* Let the processor re-execute the fixed hypercall */
3023 ctxt->_eip = ctxt->eip;
3024 /* Disable writeback. */
3025 ctxt->dst.type = OP_NONE;
3026 return X86EMUL_CONTINUE;
3027 }
3028
3029 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3030 void (*get)(struct x86_emulate_ctxt *ctxt,
3031 struct desc_ptr *ptr))
3032 {
3033 struct desc_ptr desc_ptr;
3034
3035 if (ctxt->mode == X86EMUL_MODE_PROT64)
3036 ctxt->op_bytes = 8;
3037 get(ctxt, &desc_ptr);
3038 if (ctxt->op_bytes == 2) {
3039 ctxt->op_bytes = 4;
3040 desc_ptr.address &= 0x00ffffff;
3041 }
3042 /* Disable writeback. */
3043 ctxt->dst.type = OP_NONE;
3044 return segmented_write(ctxt, ctxt->dst.addr.mem,
3045 &desc_ptr, 2 + ctxt->op_bytes);
3046 }
3047
3048 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3049 {
3050 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3051 }
3052
3053 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3054 {
3055 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3056 }
3057
3058 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3059 {
3060 struct desc_ptr desc_ptr;
3061 int rc;
3062
3063 if (ctxt->mode == X86EMUL_MODE_PROT64)
3064 ctxt->op_bytes = 8;
3065 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3066 &desc_ptr.size, &desc_ptr.address,
3067 ctxt->op_bytes);
3068 if (rc != X86EMUL_CONTINUE)
3069 return rc;
3070 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3071 /* Disable writeback. */
3072 ctxt->dst.type = OP_NONE;
3073 return X86EMUL_CONTINUE;
3074 }
3075
3076 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3077 {
3078 int rc;
3079
3080 rc = ctxt->ops->fix_hypercall(ctxt);
3081
3082 /* Disable writeback. */
3083 ctxt->dst.type = OP_NONE;
3084 return rc;
3085 }
3086
3087 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3088 {
3089 struct desc_ptr desc_ptr;
3090 int rc;
3091
3092 if (ctxt->mode == X86EMUL_MODE_PROT64)
3093 ctxt->op_bytes = 8;
3094 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3095 &desc_ptr.size, &desc_ptr.address,
3096 ctxt->op_bytes);
3097 if (rc != X86EMUL_CONTINUE)
3098 return rc;
3099 ctxt->ops->set_idt(ctxt, &desc_ptr);
3100 /* Disable writeback. */
3101 ctxt->dst.type = OP_NONE;
3102 return X86EMUL_CONTINUE;
3103 }
3104
3105 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3106 {
3107 ctxt->dst.bytes = 2;
3108 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3109 return X86EMUL_CONTINUE;
3110 }
3111
3112 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3113 {
3114 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3115 | (ctxt->src.val & 0x0f));
3116 ctxt->dst.type = OP_NONE;
3117 return X86EMUL_CONTINUE;
3118 }
3119
3120 static int em_loop(struct x86_emulate_ctxt *ctxt)
3121 {
3122 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3123 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3124 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3125 jmp_rel(ctxt, ctxt->src.val);
3126
3127 return X86EMUL_CONTINUE;
3128 }
3129
3130 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3131 {
3132 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3133 jmp_rel(ctxt, ctxt->src.val);
3134
3135 return X86EMUL_CONTINUE;
3136 }
3137
3138 static int em_in(struct x86_emulate_ctxt *ctxt)
3139 {
3140 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3141 &ctxt->dst.val))
3142 return X86EMUL_IO_NEEDED;
3143
3144 return X86EMUL_CONTINUE;
3145 }
3146
3147 static int em_out(struct x86_emulate_ctxt *ctxt)
3148 {
3149 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3150 &ctxt->src.val, 1);
3151 /* Disable writeback. */
3152 ctxt->dst.type = OP_NONE;
3153 return X86EMUL_CONTINUE;
3154 }
3155
3156 static int em_cli(struct x86_emulate_ctxt *ctxt)
3157 {
3158 if (emulator_bad_iopl(ctxt))
3159 return emulate_gp(ctxt, 0);
3160
3161 ctxt->eflags &= ~X86_EFLAGS_IF;
3162 return X86EMUL_CONTINUE;
3163 }
3164
3165 static int em_sti(struct x86_emulate_ctxt *ctxt)
3166 {
3167 if (emulator_bad_iopl(ctxt))
3168 return emulate_gp(ctxt, 0);
3169
3170 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3171 ctxt->eflags |= X86_EFLAGS_IF;
3172 return X86EMUL_CONTINUE;
3173 }
3174
3175 static int em_bt(struct x86_emulate_ctxt *ctxt)
3176 {
3177 /* Disable writeback. */
3178 ctxt->dst.type = OP_NONE;
3179 /* only subword offset */
3180 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3181
3182 emulate_2op_SrcV_nobyte(ctxt, "bt");
3183 return X86EMUL_CONTINUE;
3184 }
3185
3186 static int em_bts(struct x86_emulate_ctxt *ctxt)
3187 {
3188 emulate_2op_SrcV_nobyte(ctxt, "bts");
3189 return X86EMUL_CONTINUE;
3190 }
3191
3192 static int em_btr(struct x86_emulate_ctxt *ctxt)
3193 {
3194 emulate_2op_SrcV_nobyte(ctxt, "btr");
3195 return X86EMUL_CONTINUE;
3196 }
3197
3198 static int em_btc(struct x86_emulate_ctxt *ctxt)
3199 {
3200 emulate_2op_SrcV_nobyte(ctxt, "btc");
3201 return X86EMUL_CONTINUE;
3202 }
3203
3204 static int em_bsf(struct x86_emulate_ctxt *ctxt)
3205 {
3206 emulate_2op_SrcV_nobyte(ctxt, "bsf");
3207 return X86EMUL_CONTINUE;
3208 }
3209
3210 static int em_bsr(struct x86_emulate_ctxt *ctxt)
3211 {
3212 emulate_2op_SrcV_nobyte(ctxt, "bsr");
3213 return X86EMUL_CONTINUE;
3214 }
3215
3216 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3217 {
3218 u32 eax, ebx, ecx, edx;
3219
3220 eax = ctxt->regs[VCPU_REGS_RAX];
3221 ecx = ctxt->regs[VCPU_REGS_RCX];
3222 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3223 ctxt->regs[VCPU_REGS_RAX] = eax;
3224 ctxt->regs[VCPU_REGS_RBX] = ebx;
3225 ctxt->regs[VCPU_REGS_RCX] = ecx;
3226 ctxt->regs[VCPU_REGS_RDX] = edx;
3227 return X86EMUL_CONTINUE;
3228 }
3229
3230 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3231 {
3232 ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
3233 ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
3234 return X86EMUL_CONTINUE;
3235 }
3236
3237 static bool valid_cr(int nr)
3238 {
3239 switch (nr) {
3240 case 0:
3241 case 2 ... 4:
3242 case 8:
3243 return true;
3244 default:
3245 return false;
3246 }
3247 }
3248
3249 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3250 {
3251 if (!valid_cr(ctxt->modrm_reg))
3252 return emulate_ud(ctxt);
3253
3254 return X86EMUL_CONTINUE;
3255 }
3256
3257 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3258 {
3259 u64 new_val = ctxt->src.val64;
3260 int cr = ctxt->modrm_reg;
3261 u64 efer = 0;
3262
3263 static u64 cr_reserved_bits[] = {
3264 0xffffffff00000000ULL,
3265 0, 0, 0, /* CR3 checked later */
3266 CR4_RESERVED_BITS,
3267 0, 0, 0,
3268 CR8_RESERVED_BITS,
3269 };
3270
3271 if (!valid_cr(cr))
3272 return emulate_ud(ctxt);
3273
3274 if (new_val & cr_reserved_bits[cr])
3275 return emulate_gp(ctxt, 0);
3276
3277 switch (cr) {
3278 case 0: {
3279 u64 cr4;
3280 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3281 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3282 return emulate_gp(ctxt, 0);
3283
3284 cr4 = ctxt->ops->get_cr(ctxt, 4);
3285 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3286
3287 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3288 !(cr4 & X86_CR4_PAE))
3289 return emulate_gp(ctxt, 0);
3290
3291 break;
3292 }
3293 case 3: {
3294 u64 rsvd = 0;
3295
3296 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3297 if (efer & EFER_LMA)
3298 rsvd = CR3_L_MODE_RESERVED_BITS;
3299 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
3300 rsvd = CR3_PAE_RESERVED_BITS;
3301 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
3302 rsvd = CR3_NONPAE_RESERVED_BITS;
3303
3304 if (new_val & rsvd)
3305 return emulate_gp(ctxt, 0);
3306
3307 break;
3308 }
3309 case 4: {
3310 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3311
3312 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3313 return emulate_gp(ctxt, 0);
3314
3315 break;
3316 }
3317 }
3318
3319 return X86EMUL_CONTINUE;
3320 }
3321
3322 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3323 {
3324 unsigned long dr7;
3325
3326 ctxt->ops->get_dr(ctxt, 7, &dr7);
3327
3328 /* Check if DR7.Global_Enable is set */
3329 return dr7 & (1 << 13);
3330 }
3331
3332 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3333 {
3334 int dr = ctxt->modrm_reg;
3335 u64 cr4;
3336
3337 if (dr > 7)
3338 return emulate_ud(ctxt);
3339
3340 cr4 = ctxt->ops->get_cr(ctxt, 4);
3341 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3342 return emulate_ud(ctxt);
3343
3344 if (check_dr7_gd(ctxt))
3345 return emulate_db(ctxt);
3346
3347 return X86EMUL_CONTINUE;
3348 }
3349
3350 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3351 {
3352 u64 new_val = ctxt->src.val64;
3353 int dr = ctxt->modrm_reg;
3354
3355 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3356 return emulate_gp(ctxt, 0);
3357
3358 return check_dr_read(ctxt);
3359 }
3360
3361 static int check_svme(struct x86_emulate_ctxt *ctxt)
3362 {
3363 u64 efer;
3364
3365 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3366
3367 if (!(efer & EFER_SVME))
3368 return emulate_ud(ctxt);
3369
3370 return X86EMUL_CONTINUE;
3371 }
3372
3373 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3374 {
3375 u64 rax = ctxt->regs[VCPU_REGS_RAX];
3376
3377 /* Valid physical address? */
3378 if (rax & 0xffff000000000000ULL)
3379 return emulate_gp(ctxt, 0);
3380
3381 return check_svme(ctxt);
3382 }
3383
3384 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3385 {
3386 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3387
3388 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3389 return emulate_ud(ctxt);
3390
3391 return X86EMUL_CONTINUE;
3392 }
3393
3394 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3395 {
3396 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3397 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
3398
3399 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3400 (rcx > 3))
3401 return emulate_gp(ctxt, 0);
3402
3403 return X86EMUL_CONTINUE;
3404 }
3405
3406 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3407 {
3408 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3409 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3410 return emulate_gp(ctxt, 0);
3411
3412 return X86EMUL_CONTINUE;
3413 }
3414
3415 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3416 {
3417 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3418 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3419 return emulate_gp(ctxt, 0);
3420
3421 return X86EMUL_CONTINUE;
3422 }
3423
3424 #define D(_y) { .flags = (_y) }
3425 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
3426 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3427 .check_perm = (_p) }
3428 #define N D(0)
3429 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3430 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3431 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3432 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3433 #define II(_f, _e, _i) \
3434 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3435 #define IIP(_f, _e, _i, _p) \
3436 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3437 .check_perm = (_p) }
3438 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3439
3440 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3441 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3442 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3443 #define I2bvIP(_f, _e, _i, _p) \
3444 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3445
3446 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3447 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3448 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3449
3450 static struct opcode group7_rm1[] = {
3451 DI(SrcNone | Priv, monitor),
3452 DI(SrcNone | Priv, mwait),
3453 N, N, N, N, N, N,
3454 };
3455
3456 static struct opcode group7_rm3[] = {
3457 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3458 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3459 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3460 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3461 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3462 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3463 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3464 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3465 };
3466
3467 static struct opcode group7_rm7[] = {
3468 N,
3469 DIP(SrcNone, rdtscp, check_rdtsc),
3470 N, N, N, N, N, N,
3471 };
3472
3473 static struct opcode group1[] = {
3474 I(Lock, em_add),
3475 I(Lock | PageTable, em_or),
3476 I(Lock, em_adc),
3477 I(Lock, em_sbb),
3478 I(Lock | PageTable, em_and),
3479 I(Lock, em_sub),
3480 I(Lock, em_xor),
3481 I(0, em_cmp),
3482 };
3483
3484 static struct opcode group1A[] = {
3485 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3486 };
3487
3488 static struct opcode group3[] = {
3489 I(DstMem | SrcImm, em_test),
3490 I(DstMem | SrcImm, em_test),
3491 I(DstMem | SrcNone | Lock, em_not),
3492 I(DstMem | SrcNone | Lock, em_neg),
3493 I(SrcMem, em_mul_ex),
3494 I(SrcMem, em_imul_ex),
3495 I(SrcMem, em_div_ex),
3496 I(SrcMem, em_idiv_ex),
3497 };
3498
3499 static struct opcode group4[] = {
3500 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3501 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3502 N, N, N, N, N, N,
3503 };
3504
3505 static struct opcode group5[] = {
3506 I(DstMem | SrcNone | Lock, em_grp45),
3507 I(DstMem | SrcNone | Lock, em_grp45),
3508 I(SrcMem | Stack, em_grp45),
3509 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3510 I(SrcMem | Stack, em_grp45),
3511 I(SrcMemFAddr | ImplicitOps, em_grp45),
3512 I(SrcMem | Stack, em_grp45), N,
3513 };
3514
3515 static struct opcode group6[] = {
3516 DI(Prot, sldt),
3517 DI(Prot, str),
3518 DI(Prot | Priv, lldt),
3519 DI(Prot | Priv, ltr),
3520 N, N, N, N,
3521 };
3522
3523 static struct group_dual group7 = { {
3524 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3525 II(Mov | DstMem | Priv, em_sidt, sidt),
3526 II(SrcMem | Priv, em_lgdt, lgdt),
3527 II(SrcMem | Priv, em_lidt, lidt),
3528 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3529 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3530 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3531 }, {
3532 I(SrcNone | Priv | VendorSpecific, em_vmcall),
3533 EXT(0, group7_rm1),
3534 N, EXT(0, group7_rm3),
3535 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3536 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3537 EXT(0, group7_rm7),
3538 } };
3539
3540 static struct opcode group8[] = {
3541 N, N, N, N,
3542 I(DstMem | SrcImmByte, em_bt),
3543 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3544 I(DstMem | SrcImmByte | Lock, em_btr),
3545 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3546 };
3547
3548 static struct group_dual group9 = { {
3549 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3550 }, {
3551 N, N, N, N, N, N, N, N,
3552 } };
3553
3554 static struct opcode group11[] = {
3555 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3556 X7(D(Undefined)),
3557 };
3558
3559 static struct gprefix pfx_0f_6f_0f_7f = {
3560 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3561 };
3562
3563 static struct gprefix pfx_vmovntpx = {
3564 I(0, em_mov), N, N, N,
3565 };
3566
3567 static struct opcode opcode_table[256] = {
3568 /* 0x00 - 0x07 */
3569 I6ALU(Lock, em_add),
3570 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3571 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3572 /* 0x08 - 0x0F */
3573 I6ALU(Lock | PageTable, em_or),
3574 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3575 N,
3576 /* 0x10 - 0x17 */
3577 I6ALU(Lock, em_adc),
3578 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3579 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3580 /* 0x18 - 0x1F */
3581 I6ALU(Lock, em_sbb),
3582 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3583 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3584 /* 0x20 - 0x27 */
3585 I6ALU(Lock | PageTable, em_and), N, N,
3586 /* 0x28 - 0x2F */
3587 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3588 /* 0x30 - 0x37 */
3589 I6ALU(Lock, em_xor), N, N,
3590 /* 0x38 - 0x3F */
3591 I6ALU(0, em_cmp), N, N,
3592 /* 0x40 - 0x4F */
3593 X16(D(DstReg)),
3594 /* 0x50 - 0x57 */
3595 X8(I(SrcReg | Stack, em_push)),
3596 /* 0x58 - 0x5F */
3597 X8(I(DstReg | Stack, em_pop)),
3598 /* 0x60 - 0x67 */
3599 I(ImplicitOps | Stack | No64, em_pusha),
3600 I(ImplicitOps | Stack | No64, em_popa),
3601 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3602 N, N, N, N,
3603 /* 0x68 - 0x6F */
3604 I(SrcImm | Mov | Stack, em_push),
3605 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3606 I(SrcImmByte | Mov | Stack, em_push),
3607 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3608 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3609 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3610 /* 0x70 - 0x7F */
3611 X16(D(SrcImmByte)),
3612 /* 0x80 - 0x87 */
3613 G(ByteOp | DstMem | SrcImm, group1),
3614 G(DstMem | SrcImm, group1),
3615 G(ByteOp | DstMem | SrcImm | No64, group1),
3616 G(DstMem | SrcImmByte, group1),
3617 I2bv(DstMem | SrcReg | ModRM, em_test),
3618 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3619 /* 0x88 - 0x8F */
3620 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3621 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3622 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3623 D(ModRM | SrcMem | NoAccess | DstReg),
3624 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3625 G(0, group1A),
3626 /* 0x90 - 0x97 */
3627 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3628 /* 0x98 - 0x9F */
3629 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3630 I(SrcImmFAddr | No64, em_call_far), N,
3631 II(ImplicitOps | Stack, em_pushf, pushf),
3632 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
3633 /* 0xA0 - 0xA7 */
3634 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3635 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3636 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3637 I2bv(SrcSI | DstDI | String, em_cmp),
3638 /* 0xA8 - 0xAF */
3639 I2bv(DstAcc | SrcImm, em_test),
3640 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3641 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3642 I2bv(SrcAcc | DstDI | String, em_cmp),
3643 /* 0xB0 - 0xB7 */
3644 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3645 /* 0xB8 - 0xBF */
3646 X8(I(DstReg | SrcImm | Mov, em_mov)),
3647 /* 0xC0 - 0xC7 */
3648 D2bv(DstMem | SrcImmByte | ModRM),
3649 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3650 I(ImplicitOps | Stack, em_ret),
3651 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3652 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3653 G(ByteOp, group11), G(0, group11),
3654 /* 0xC8 - 0xCF */
3655 N, I(Stack, em_leave), N, I(ImplicitOps | Stack, em_ret_far),
3656 D(ImplicitOps), DI(SrcImmByte, intn),
3657 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3658 /* 0xD0 - 0xD7 */
3659 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3660 N, N, N, N,
3661 /* 0xD8 - 0xDF */
3662 N, N, N, N, N, N, N, N,
3663 /* 0xE0 - 0xE7 */
3664 X3(I(SrcImmByte, em_loop)),
3665 I(SrcImmByte, em_jcxz),
3666 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3667 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3668 /* 0xE8 - 0xEF */
3669 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
3670 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3671 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3672 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3673 /* 0xF0 - 0xF7 */
3674 N, DI(ImplicitOps, icebp), N, N,
3675 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3676 G(ByteOp, group3), G(0, group3),
3677 /* 0xF8 - 0xFF */
3678 D(ImplicitOps), D(ImplicitOps),
3679 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3680 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3681 };
3682
3683 static struct opcode twobyte_table[256] = {
3684 /* 0x00 - 0x0F */
3685 G(0, group6), GD(0, &group7), N, N,
3686 N, I(ImplicitOps | VendorSpecific, em_syscall),
3687 II(ImplicitOps | Priv, em_clts, clts), N,
3688 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3689 N, D(ImplicitOps | ModRM), N, N,
3690 /* 0x10 - 0x1F */
3691 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3692 /* 0x20 - 0x2F */
3693 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3694 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3695 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3696 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
3697 N, N, N, N,
3698 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3699 N, N, N, N,
3700 /* 0x30 - 0x3F */
3701 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
3702 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3703 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
3704 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
3705 I(ImplicitOps | VendorSpecific, em_sysenter),
3706 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3707 N, N,
3708 N, N, N, N, N, N, N, N,
3709 /* 0x40 - 0x4F */
3710 X16(D(DstReg | SrcMem | ModRM | Mov)),
3711 /* 0x50 - 0x5F */
3712 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3713 /* 0x60 - 0x6F */
3714 N, N, N, N,
3715 N, N, N, N,
3716 N, N, N, N,
3717 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3718 /* 0x70 - 0x7F */
3719 N, N, N, N,
3720 N, N, N, N,
3721 N, N, N, N,
3722 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3723 /* 0x80 - 0x8F */
3724 X16(D(SrcImm)),
3725 /* 0x90 - 0x9F */
3726 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3727 /* 0xA0 - 0xA7 */
3728 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
3729 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
3730 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3731 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3732 /* 0xA8 - 0xAF */
3733 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
3734 DI(ImplicitOps, rsm),
3735 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3736 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3737 D(DstMem | SrcReg | Src2CL | ModRM),
3738 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3739 /* 0xB0 - 0xB7 */
3740 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3741 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
3742 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
3743 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3744 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
3745 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3746 /* 0xB8 - 0xBF */
3747 N, N,
3748 G(BitOp, group8),
3749 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3750 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
3751 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3752 /* 0xC0 - 0xCF */
3753 D2bv(DstMem | SrcReg | ModRM | Lock),
3754 N, D(DstMem | SrcReg | ModRM | Mov),
3755 N, N, N, GD(0, &group9),
3756 N, N, N, N, N, N, N, N,
3757 /* 0xD0 - 0xDF */
3758 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3759 /* 0xE0 - 0xEF */
3760 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3761 /* 0xF0 - 0xFF */
3762 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3763 };
3764
3765 #undef D
3766 #undef N
3767 #undef G
3768 #undef GD
3769 #undef I
3770 #undef GP
3771 #undef EXT
3772
3773 #undef D2bv
3774 #undef D2bvIP
3775 #undef I2bv
3776 #undef I2bvIP
3777 #undef I6ALU
3778
3779 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3780 {
3781 unsigned size;
3782
3783 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3784 if (size == 8)
3785 size = 4;
3786 return size;
3787 }
3788
3789 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3790 unsigned size, bool sign_extension)
3791 {
3792 int rc = X86EMUL_CONTINUE;
3793
3794 op->type = OP_IMM;
3795 op->bytes = size;
3796 op->addr.mem.ea = ctxt->_eip;
3797 /* NB. Immediates are sign-extended as necessary. */
3798 switch (op->bytes) {
3799 case 1:
3800 op->val = insn_fetch(s8, ctxt);
3801 break;
3802 case 2:
3803 op->val = insn_fetch(s16, ctxt);
3804 break;
3805 case 4:
3806 op->val = insn_fetch(s32, ctxt);
3807 break;
3808 }
3809 if (!sign_extension) {
3810 switch (op->bytes) {
3811 case 1:
3812 op->val &= 0xff;
3813 break;
3814 case 2:
3815 op->val &= 0xffff;
3816 break;
3817 case 4:
3818 op->val &= 0xffffffff;
3819 break;
3820 }
3821 }
3822 done:
3823 return rc;
3824 }
3825
3826 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3827 unsigned d)
3828 {
3829 int rc = X86EMUL_CONTINUE;
3830
3831 switch (d) {
3832 case OpReg:
3833 decode_register_operand(ctxt, op);
3834 break;
3835 case OpImmUByte:
3836 rc = decode_imm(ctxt, op, 1, false);
3837 break;
3838 case OpMem:
3839 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3840 mem_common:
3841 *op = ctxt->memop;
3842 ctxt->memopp = op;
3843 if ((ctxt->d & BitOp) && op == &ctxt->dst)
3844 fetch_bit_operand(ctxt);
3845 op->orig_val = op->val;
3846 break;
3847 case OpMem64:
3848 ctxt->memop.bytes = 8;
3849 goto mem_common;
3850 case OpAcc:
3851 op->type = OP_REG;
3852 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3853 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3854 fetch_register_operand(op);
3855 op->orig_val = op->val;
3856 break;
3857 case OpDI:
3858 op->type = OP_MEM;
3859 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3860 op->addr.mem.ea =
3861 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3862 op->addr.mem.seg = VCPU_SREG_ES;
3863 op->val = 0;
3864 break;
3865 case OpDX:
3866 op->type = OP_REG;
3867 op->bytes = 2;
3868 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3869 fetch_register_operand(op);
3870 break;
3871 case OpCL:
3872 op->bytes = 1;
3873 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3874 break;
3875 case OpImmByte:
3876 rc = decode_imm(ctxt, op, 1, true);
3877 break;
3878 case OpOne:
3879 op->bytes = 1;
3880 op->val = 1;
3881 break;
3882 case OpImm:
3883 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3884 break;
3885 case OpMem8:
3886 ctxt->memop.bytes = 1;
3887 goto mem_common;
3888 case OpMem16:
3889 ctxt->memop.bytes = 2;
3890 goto mem_common;
3891 case OpMem32:
3892 ctxt->memop.bytes = 4;
3893 goto mem_common;
3894 case OpImmU16:
3895 rc = decode_imm(ctxt, op, 2, false);
3896 break;
3897 case OpImmU:
3898 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3899 break;
3900 case OpSI:
3901 op->type = OP_MEM;
3902 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3903 op->addr.mem.ea =
3904 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3905 op->addr.mem.seg = seg_override(ctxt);
3906 op->val = 0;
3907 break;
3908 case OpImmFAddr:
3909 op->type = OP_IMM;
3910 op->addr.mem.ea = ctxt->_eip;
3911 op->bytes = ctxt->op_bytes + 2;
3912 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3913 break;
3914 case OpMemFAddr:
3915 ctxt->memop.bytes = ctxt->op_bytes + 2;
3916 goto mem_common;
3917 case OpES:
3918 op->val = VCPU_SREG_ES;
3919 break;
3920 case OpCS:
3921 op->val = VCPU_SREG_CS;
3922 break;
3923 case OpSS:
3924 op->val = VCPU_SREG_SS;
3925 break;
3926 case OpDS:
3927 op->val = VCPU_SREG_DS;
3928 break;
3929 case OpFS:
3930 op->val = VCPU_SREG_FS;
3931 break;
3932 case OpGS:
3933 op->val = VCPU_SREG_GS;
3934 break;
3935 case OpImplicit:
3936 /* Special instructions do their own operand decoding. */
3937 default:
3938 op->type = OP_NONE; /* Disable writeback. */
3939 break;
3940 }
3941
3942 done:
3943 return rc;
3944 }
3945
3946 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3947 {
3948 int rc = X86EMUL_CONTINUE;
3949 int mode = ctxt->mode;
3950 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3951 bool op_prefix = false;
3952 struct opcode opcode;
3953
3954 ctxt->memop.type = OP_NONE;
3955 ctxt->memopp = NULL;
3956 ctxt->_eip = ctxt->eip;
3957 ctxt->fetch.start = ctxt->_eip;
3958 ctxt->fetch.end = ctxt->fetch.start + insn_len;
3959 if (insn_len > 0)
3960 memcpy(ctxt->fetch.data, insn, insn_len);
3961
3962 switch (mode) {
3963 case X86EMUL_MODE_REAL:
3964 case X86EMUL_MODE_VM86:
3965 case X86EMUL_MODE_PROT16:
3966 def_op_bytes = def_ad_bytes = 2;
3967 break;
3968 case X86EMUL_MODE_PROT32:
3969 def_op_bytes = def_ad_bytes = 4;
3970 break;
3971 #ifdef CONFIG_X86_64
3972 case X86EMUL_MODE_PROT64:
3973 def_op_bytes = 4;
3974 def_ad_bytes = 8;
3975 break;
3976 #endif
3977 default:
3978 return EMULATION_FAILED;
3979 }
3980
3981 ctxt->op_bytes = def_op_bytes;
3982 ctxt->ad_bytes = def_ad_bytes;
3983
3984 /* Legacy prefixes. */
3985 for (;;) {
3986 switch (ctxt->b = insn_fetch(u8, ctxt)) {
3987 case 0x66: /* operand-size override */
3988 op_prefix = true;
3989 /* switch between 2/4 bytes */
3990 ctxt->op_bytes = def_op_bytes ^ 6;
3991 break;
3992 case 0x67: /* address-size override */
3993 if (mode == X86EMUL_MODE_PROT64)
3994 /* switch between 4/8 bytes */
3995 ctxt->ad_bytes = def_ad_bytes ^ 12;
3996 else
3997 /* switch between 2/4 bytes */
3998 ctxt->ad_bytes = def_ad_bytes ^ 6;
3999 break;
4000 case 0x26: /* ES override */
4001 case 0x2e: /* CS override */
4002 case 0x36: /* SS override */
4003 case 0x3e: /* DS override */
4004 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
4005 break;
4006 case 0x64: /* FS override */
4007 case 0x65: /* GS override */
4008 set_seg_override(ctxt, ctxt->b & 7);
4009 break;
4010 case 0x40 ... 0x4f: /* REX */
4011 if (mode != X86EMUL_MODE_PROT64)
4012 goto done_prefixes;
4013 ctxt->rex_prefix = ctxt->b;
4014 continue;
4015 case 0xf0: /* LOCK */
4016 ctxt->lock_prefix = 1;
4017 break;
4018 case 0xf2: /* REPNE/REPNZ */
4019 case 0xf3: /* REP/REPE/REPZ */
4020 ctxt->rep_prefix = ctxt->b;
4021 break;
4022 default:
4023 goto done_prefixes;
4024 }
4025
4026 /* Any legacy prefix after a REX prefix nullifies its effect. */
4027
4028 ctxt->rex_prefix = 0;
4029 }
4030
4031 done_prefixes:
4032
4033 /* REX prefix. */
4034 if (ctxt->rex_prefix & 8)
4035 ctxt->op_bytes = 8; /* REX.W */
4036
4037 /* Opcode byte(s). */
4038 opcode = opcode_table[ctxt->b];
4039 /* Two-byte opcode? */
4040 if (ctxt->b == 0x0f) {
4041 ctxt->twobyte = 1;
4042 ctxt->b = insn_fetch(u8, ctxt);
4043 opcode = twobyte_table[ctxt->b];
4044 }
4045 ctxt->d = opcode.flags;
4046
4047 if (ctxt->d & ModRM)
4048 ctxt->modrm = insn_fetch(u8, ctxt);
4049
4050 while (ctxt->d & GroupMask) {
4051 switch (ctxt->d & GroupMask) {
4052 case Group:
4053 goffset = (ctxt->modrm >> 3) & 7;
4054 opcode = opcode.u.group[goffset];
4055 break;
4056 case GroupDual:
4057 goffset = (ctxt->modrm >> 3) & 7;
4058 if ((ctxt->modrm >> 6) == 3)
4059 opcode = opcode.u.gdual->mod3[goffset];
4060 else
4061 opcode = opcode.u.gdual->mod012[goffset];
4062 break;
4063 case RMExt:
4064 goffset = ctxt->modrm & 7;
4065 opcode = opcode.u.group[goffset];
4066 break;
4067 case Prefix:
4068 if (ctxt->rep_prefix && op_prefix)
4069 return EMULATION_FAILED;
4070 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4071 switch (simd_prefix) {
4072 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4073 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4074 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4075 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4076 }
4077 break;
4078 default:
4079 return EMULATION_FAILED;
4080 }
4081
4082 ctxt->d &= ~(u64)GroupMask;
4083 ctxt->d |= opcode.flags;
4084 }
4085
4086 ctxt->execute = opcode.u.execute;
4087 ctxt->check_perm = opcode.check_perm;
4088 ctxt->intercept = opcode.intercept;
4089
4090 /* Unrecognised? */
4091 if (ctxt->d == 0 || (ctxt->d & Undefined))
4092 return EMULATION_FAILED;
4093
4094 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
4095 return EMULATION_FAILED;
4096
4097 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4098 ctxt->op_bytes = 8;
4099
4100 if (ctxt->d & Op3264) {
4101 if (mode == X86EMUL_MODE_PROT64)
4102 ctxt->op_bytes = 8;
4103 else
4104 ctxt->op_bytes = 4;
4105 }
4106
4107 if (ctxt->d & Sse)
4108 ctxt->op_bytes = 16;
4109 else if (ctxt->d & Mmx)
4110 ctxt->op_bytes = 8;
4111
4112 /* ModRM and SIB bytes. */
4113 if (ctxt->d & ModRM) {
4114 rc = decode_modrm(ctxt, &ctxt->memop);
4115 if (!ctxt->has_seg_override)
4116 set_seg_override(ctxt, ctxt->modrm_seg);
4117 } else if (ctxt->d & MemAbs)
4118 rc = decode_abs(ctxt, &ctxt->memop);
4119 if (rc != X86EMUL_CONTINUE)
4120 goto done;
4121
4122 if (!ctxt->has_seg_override)
4123 set_seg_override(ctxt, VCPU_SREG_DS);
4124
4125 ctxt->memop.addr.mem.seg = seg_override(ctxt);
4126
4127 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4128 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
4129
4130 /*
4131 * Decode and fetch the source operand: register, memory
4132 * or immediate.
4133 */
4134 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4135 if (rc != X86EMUL_CONTINUE)
4136 goto done;
4137
4138 /*
4139 * Decode and fetch the second source operand: register, memory
4140 * or immediate.
4141 */
4142 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4143 if (rc != X86EMUL_CONTINUE)
4144 goto done;
4145
4146 /* Decode and fetch the destination operand: register or memory. */
4147 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4148
4149 done:
4150 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4151 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4152
4153 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4154 }
4155
4156 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4157 {
4158 return ctxt->d & PageTable;
4159 }
4160
4161 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4162 {
4163 /* The second termination condition only applies for REPE
4164 * and REPNE. Test if the repeat string operation prefix is
4165 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4166 * corresponding termination condition according to:
4167 * - if REPE/REPZ and ZF = 0 then done
4168 * - if REPNE/REPNZ and ZF = 1 then done
4169 */
4170 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4171 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4172 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4173 ((ctxt->eflags & EFLG_ZF) == 0))
4174 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4175 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4176 return true;
4177
4178 return false;
4179 }
4180
4181 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4182 {
4183 bool fault = false;
4184
4185 ctxt->ops->get_fpu(ctxt);
4186 asm volatile("1: fwait \n\t"
4187 "2: \n\t"
4188 ".pushsection .fixup,\"ax\" \n\t"
4189 "3: \n\t"
4190 "movb $1, %[fault] \n\t"
4191 "jmp 2b \n\t"
4192 ".popsection \n\t"
4193 _ASM_EXTABLE(1b, 3b)
4194 : [fault]"+qm"(fault));
4195 ctxt->ops->put_fpu(ctxt);
4196
4197 if (unlikely(fault))
4198 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4199
4200 return X86EMUL_CONTINUE;
4201 }
4202
4203 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4204 struct operand *op)
4205 {
4206 if (op->type == OP_MM)
4207 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4208 }
4209
4210 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4211 {
4212 struct x86_emulate_ops *ops = ctxt->ops;
4213 int rc = X86EMUL_CONTINUE;
4214 int saved_dst_type = ctxt->dst.type;
4215
4216 ctxt->mem_read.pos = 0;
4217
4218 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
4219 rc = emulate_ud(ctxt);
4220 goto done;
4221 }
4222
4223 /* LOCK prefix is allowed only with some instructions */
4224 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4225 rc = emulate_ud(ctxt);
4226 goto done;
4227 }
4228
4229 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4230 rc = emulate_ud(ctxt);
4231 goto done;
4232 }
4233
4234 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4235 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4236 rc = emulate_ud(ctxt);
4237 goto done;
4238 }
4239
4240 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4241 rc = emulate_nm(ctxt);
4242 goto done;
4243 }
4244
4245 if (ctxt->d & Mmx) {
4246 rc = flush_pending_x87_faults(ctxt);
4247 if (rc != X86EMUL_CONTINUE)
4248 goto done;
4249 /*
4250 * Now that we know the fpu is exception safe, we can fetch
4251 * operands from it.
4252 */
4253 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4254 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4255 if (!(ctxt->d & Mov))
4256 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4257 }
4258
4259 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4260 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4261 X86_ICPT_PRE_EXCEPT);
4262 if (rc != X86EMUL_CONTINUE)
4263 goto done;
4264 }
4265
4266 /* Privileged instruction can be executed only in CPL=0 */
4267 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4268 rc = emulate_gp(ctxt, 0);
4269 goto done;
4270 }
4271
4272 /* Instruction can only be executed in protected mode */
4273 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
4274 rc = emulate_ud(ctxt);
4275 goto done;
4276 }
4277
4278 /* Do instruction specific permission checks */
4279 if (ctxt->check_perm) {
4280 rc = ctxt->check_perm(ctxt);
4281 if (rc != X86EMUL_CONTINUE)
4282 goto done;
4283 }
4284
4285 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4286 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4287 X86_ICPT_POST_EXCEPT);
4288 if (rc != X86EMUL_CONTINUE)
4289 goto done;
4290 }
4291
4292 if (ctxt->rep_prefix && (ctxt->d & String)) {
4293 /* All REP prefixes have the same first termination condition */
4294 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4295 ctxt->eip = ctxt->_eip;
4296 goto done;
4297 }
4298 }
4299
4300 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4301 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4302 ctxt->src.valptr, ctxt->src.bytes);
4303 if (rc != X86EMUL_CONTINUE)
4304 goto done;
4305 ctxt->src.orig_val64 = ctxt->src.val64;
4306 }
4307
4308 if (ctxt->src2.type == OP_MEM) {
4309 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4310 &ctxt->src2.val, ctxt->src2.bytes);
4311 if (rc != X86EMUL_CONTINUE)
4312 goto done;
4313 }
4314
4315 if ((ctxt->d & DstMask) == ImplicitOps)
4316 goto special_insn;
4317
4318
4319 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4320 /* optimisation - avoid slow emulated read if Mov */
4321 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4322 &ctxt->dst.val, ctxt->dst.bytes);
4323 if (rc != X86EMUL_CONTINUE)
4324 goto done;
4325 }
4326 ctxt->dst.orig_val = ctxt->dst.val;
4327
4328 special_insn:
4329
4330 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4331 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4332 X86_ICPT_POST_MEMACCESS);
4333 if (rc != X86EMUL_CONTINUE)
4334 goto done;
4335 }
4336
4337 if (ctxt->execute) {
4338 rc = ctxt->execute(ctxt);
4339 if (rc != X86EMUL_CONTINUE)
4340 goto done;
4341 goto writeback;
4342 }
4343
4344 if (ctxt->twobyte)
4345 goto twobyte_insn;
4346
4347 switch (ctxt->b) {
4348 case 0x40 ... 0x47: /* inc r16/r32 */
4349 emulate_1op(ctxt, "inc");
4350 break;
4351 case 0x48 ... 0x4f: /* dec r16/r32 */
4352 emulate_1op(ctxt, "dec");
4353 break;
4354 case 0x63: /* movsxd */
4355 if (ctxt->mode != X86EMUL_MODE_PROT64)
4356 goto cannot_emulate;
4357 ctxt->dst.val = (s32) ctxt->src.val;
4358 break;
4359 case 0x70 ... 0x7f: /* jcc (short) */
4360 if (test_cc(ctxt->b, ctxt->eflags))
4361 jmp_rel(ctxt, ctxt->src.val);
4362 break;
4363 case 0x8d: /* lea r16/r32, m */
4364 ctxt->dst.val = ctxt->src.addr.mem.ea;
4365 break;
4366 case 0x90 ... 0x97: /* nop / xchg reg, rax */
4367 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
4368 break;
4369 rc = em_xchg(ctxt);
4370 break;
4371 case 0x98: /* cbw/cwde/cdqe */
4372 switch (ctxt->op_bytes) {
4373 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4374 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4375 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4376 }
4377 break;
4378 case 0xc0 ... 0xc1:
4379 rc = em_grp2(ctxt);
4380 break;
4381 case 0xcc: /* int3 */
4382 rc = emulate_int(ctxt, 3);
4383 break;
4384 case 0xcd: /* int n */
4385 rc = emulate_int(ctxt, ctxt->src.val);
4386 break;
4387 case 0xce: /* into */
4388 if (ctxt->eflags & EFLG_OF)
4389 rc = emulate_int(ctxt, 4);
4390 break;
4391 case 0xd0 ... 0xd1: /* Grp2 */
4392 rc = em_grp2(ctxt);
4393 break;
4394 case 0xd2 ... 0xd3: /* Grp2 */
4395 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
4396 rc = em_grp2(ctxt);
4397 break;
4398 case 0xe9: /* jmp rel */
4399 case 0xeb: /* jmp rel short */
4400 jmp_rel(ctxt, ctxt->src.val);
4401 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4402 break;
4403 case 0xf4: /* hlt */
4404 ctxt->ops->halt(ctxt);
4405 break;
4406 case 0xf5: /* cmc */
4407 /* complement carry flag from eflags reg */
4408 ctxt->eflags ^= EFLG_CF;
4409 break;
4410 case 0xf8: /* clc */
4411 ctxt->eflags &= ~EFLG_CF;
4412 break;
4413 case 0xf9: /* stc */
4414 ctxt->eflags |= EFLG_CF;
4415 break;
4416 case 0xfc: /* cld */
4417 ctxt->eflags &= ~EFLG_DF;
4418 break;
4419 case 0xfd: /* std */
4420 ctxt->eflags |= EFLG_DF;
4421 break;
4422 default:
4423 goto cannot_emulate;
4424 }
4425
4426 if (rc != X86EMUL_CONTINUE)
4427 goto done;
4428
4429 writeback:
4430 rc = writeback(ctxt);
4431 if (rc != X86EMUL_CONTINUE)
4432 goto done;
4433
4434 /*
4435 * restore dst type in case the decoding will be reused
4436 * (happens for string instruction )
4437 */
4438 ctxt->dst.type = saved_dst_type;
4439
4440 if ((ctxt->d & SrcMask) == SrcSI)
4441 string_addr_inc(ctxt, seg_override(ctxt),
4442 VCPU_REGS_RSI, &ctxt->src);
4443
4444 if ((ctxt->d & DstMask) == DstDI)
4445 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4446 &ctxt->dst);
4447
4448 if (ctxt->rep_prefix && (ctxt->d & String)) {
4449 struct read_cache *r = &ctxt->io_read;
4450 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
4451
4452 if (!string_insn_completed(ctxt)) {
4453 /*
4454 * Re-enter guest when pio read ahead buffer is empty
4455 * or, if it is not used, after each 1024 iteration.
4456 */
4457 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
4458 (r->end == 0 || r->end != r->pos)) {
4459 /*
4460 * Reset read cache. Usually happens before
4461 * decode, but since instruction is restarted
4462 * we have to do it here.
4463 */
4464 ctxt->mem_read.end = 0;
4465 return EMULATION_RESTART;
4466 }
4467 goto done; /* skip rip writeback */
4468 }
4469 }
4470
4471 ctxt->eip = ctxt->_eip;
4472
4473 done:
4474 if (rc == X86EMUL_PROPAGATE_FAULT)
4475 ctxt->have_exception = true;
4476 if (rc == X86EMUL_INTERCEPTED)
4477 return EMULATION_INTERCEPTED;
4478
4479 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4480
4481 twobyte_insn:
4482 switch (ctxt->b) {
4483 case 0x09: /* wbinvd */
4484 (ctxt->ops->wbinvd)(ctxt);
4485 break;
4486 case 0x08: /* invd */
4487 case 0x0d: /* GrpP (prefetch) */
4488 case 0x18: /* Grp16 (prefetch/nop) */
4489 break;
4490 case 0x20: /* mov cr, reg */
4491 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4492 break;
4493 case 0x21: /* mov from dr to reg */
4494 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
4495 break;
4496 case 0x40 ... 0x4f: /* cmov */
4497 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4498 if (!test_cc(ctxt->b, ctxt->eflags))
4499 ctxt->dst.type = OP_NONE; /* no writeback */
4500 break;
4501 case 0x80 ... 0x8f: /* jnz rel, etc*/
4502 if (test_cc(ctxt->b, ctxt->eflags))
4503 jmp_rel(ctxt, ctxt->src.val);
4504 break;
4505 case 0x90 ... 0x9f: /* setcc r/m8 */
4506 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4507 break;
4508 case 0xa4: /* shld imm8, r, r/m */
4509 case 0xa5: /* shld cl, r, r/m */
4510 emulate_2op_cl(ctxt, "shld");
4511 break;
4512 case 0xac: /* shrd imm8, r, r/m */
4513 case 0xad: /* shrd cl, r, r/m */
4514 emulate_2op_cl(ctxt, "shrd");
4515 break;
4516 case 0xae: /* clflush */
4517 break;
4518 case 0xb6 ... 0xb7: /* movzx */
4519 ctxt->dst.bytes = ctxt->op_bytes;
4520 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4521 : (u16) ctxt->src.val;
4522 break;
4523 case 0xbe ... 0xbf: /* movsx */
4524 ctxt->dst.bytes = ctxt->op_bytes;
4525 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4526 (s16) ctxt->src.val;
4527 break;
4528 case 0xc0 ... 0xc1: /* xadd */
4529 emulate_2op_SrcV(ctxt, "add");
4530 /* Write back the register source. */
4531 ctxt->src.val = ctxt->dst.orig_val;
4532 write_register_operand(&ctxt->src);
4533 break;
4534 case 0xc3: /* movnti */
4535 ctxt->dst.bytes = ctxt->op_bytes;
4536 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4537 (u64) ctxt->src.val;
4538 break;
4539 default:
4540 goto cannot_emulate;
4541 }
4542
4543 if (rc != X86EMUL_CONTINUE)
4544 goto done;
4545
4546 goto writeback;
4547
4548 cannot_emulate:
4549 return EMULATION_FAILED;
4550 }
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