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1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27 #include <linux/stringify.h>
28
29 #include "x86.h"
30 #include "tss.h"
31
32 /*
33 * Operand types
34 */
35 #define OpNone 0ull
36 #define OpImplicit 1ull /* No generic decode */
37 #define OpReg 2ull /* Register */
38 #define OpMem 3ull /* Memory */
39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40 #define OpDI 5ull /* ES:DI/EDI/RDI */
41 #define OpMem64 6ull /* Memory, 64-bit */
42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43 #define OpDX 8ull /* DX register */
44 #define OpCL 9ull /* CL register (for shifts) */
45 #define OpImmByte 10ull /* 8-bit sign extended immediate */
46 #define OpOne 11ull /* Implied 1 */
47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
48 #define OpMem16 13ull /* Memory operand (16-bit). */
49 #define OpMem32 14ull /* Memory operand (32-bit). */
50 #define OpImmU 15ull /* Immediate operand, zero extended */
51 #define OpSI 16ull /* SI/ESI/RSI */
52 #define OpImmFAddr 17ull /* Immediate far address */
53 #define OpMemFAddr 18ull /* Far address in memory */
54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
55 #define OpES 20ull /* ES */
56 #define OpCS 21ull /* CS */
57 #define OpSS 22ull /* SS */
58 #define OpDS 23ull /* DS */
59 #define OpFS 24ull /* FS */
60 #define OpGS 25ull /* GS */
61 #define OpMem8 26ull /* 8-bit zero extended memory operand */
62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
64 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
66
67 #define OpBits 5 /* Width of operand field */
68 #define OpMask ((1ull << OpBits) - 1)
69
70 /*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79 /* Operand sizes: 8-bit operands or specified/overridden size. */
80 #define ByteOp (1<<0) /* 8-bit operands. */
81 /* Destination operand type. */
82 #define DstShift 1
83 #define ImplicitOps (OpImplicit << DstShift)
84 #define DstReg (OpReg << DstShift)
85 #define DstMem (OpMem << DstShift)
86 #define DstAcc (OpAcc << DstShift)
87 #define DstDI (OpDI << DstShift)
88 #define DstMem64 (OpMem64 << DstShift)
89 #define DstImmUByte (OpImmUByte << DstShift)
90 #define DstDX (OpDX << DstShift)
91 #define DstAccLo (OpAccLo << DstShift)
92 #define DstMask (OpMask << DstShift)
93 /* Source operand type. */
94 #define SrcShift 6
95 #define SrcNone (OpNone << SrcShift)
96 #define SrcReg (OpReg << SrcShift)
97 #define SrcMem (OpMem << SrcShift)
98 #define SrcMem16 (OpMem16 << SrcShift)
99 #define SrcMem32 (OpMem32 << SrcShift)
100 #define SrcImm (OpImm << SrcShift)
101 #define SrcImmByte (OpImmByte << SrcShift)
102 #define SrcOne (OpOne << SrcShift)
103 #define SrcImmUByte (OpImmUByte << SrcShift)
104 #define SrcImmU (OpImmU << SrcShift)
105 #define SrcSI (OpSI << SrcShift)
106 #define SrcXLat (OpXLat << SrcShift)
107 #define SrcImmFAddr (OpImmFAddr << SrcShift)
108 #define SrcMemFAddr (OpMemFAddr << SrcShift)
109 #define SrcAcc (OpAcc << SrcShift)
110 #define SrcImmU16 (OpImmU16 << SrcShift)
111 #define SrcImm64 (OpImm64 << SrcShift)
112 #define SrcDX (OpDX << SrcShift)
113 #define SrcMem8 (OpMem8 << SrcShift)
114 #define SrcAccHi (OpAccHi << SrcShift)
115 #define SrcMask (OpMask << SrcShift)
116 #define BitOp (1<<11)
117 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
118 #define String (1<<13) /* String instruction (rep capable) */
119 #define Stack (1<<14) /* Stack instruction (push/pop) */
120 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
125 #define Escape (5<<15) /* Escape to coprocessor instruction */
126 #define Sse (1<<18) /* SSE Vector instruction */
127 /* Generic ModRM decode. */
128 #define ModRM (1<<19)
129 /* Destination is only written; never read. */
130 #define Mov (1<<20)
131 /* Misc flags */
132 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
133 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
134 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
135 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
136 #define Undefined (1<<25) /* No Such Instruction */
137 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
138 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
139 #define No64 (1<<28)
140 #define PageTable (1 << 29) /* instruction used to write page table */
141 #define NotImpl (1 << 30) /* instruction is not implemented */
142 /* Source 2 operand type */
143 #define Src2Shift (31)
144 #define Src2None (OpNone << Src2Shift)
145 #define Src2Mem (OpMem << Src2Shift)
146 #define Src2CL (OpCL << Src2Shift)
147 #define Src2ImmByte (OpImmByte << Src2Shift)
148 #define Src2One (OpOne << Src2Shift)
149 #define Src2Imm (OpImm << Src2Shift)
150 #define Src2ES (OpES << Src2Shift)
151 #define Src2CS (OpCS << Src2Shift)
152 #define Src2SS (OpSS << Src2Shift)
153 #define Src2DS (OpDS << Src2Shift)
154 #define Src2FS (OpFS << Src2Shift)
155 #define Src2GS (OpGS << Src2Shift)
156 #define Src2Mask (OpMask << Src2Shift)
157 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
158 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
161 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
162 #define NoWrite ((u64)1 << 45) /* No writeback */
163 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
164 #define NoMod ((u64)1 << 47) /* Mod field is ignored */
165 #define Intercept ((u64)1 << 48) /* Has valid intercept field */
166 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
167 #define NoBigReal ((u64)1 << 50) /* No big real mode */
168 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
169 #define NearBranch ((u64)1 << 52) /* Near branches */
170
171 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
172
173 #define X2(x...) x, x
174 #define X3(x...) X2(x), x
175 #define X4(x...) X2(x), X2(x)
176 #define X5(x...) X4(x), x
177 #define X6(x...) X4(x), X2(x)
178 #define X7(x...) X4(x), X3(x)
179 #define X8(x...) X4(x), X4(x)
180 #define X16(x...) X8(x), X8(x)
181
182 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
183 #define FASTOP_SIZE 8
184
185 /*
186 * fastop functions have a special calling convention:
187 *
188 * dst: rax (in/out)
189 * src: rdx (in/out)
190 * src2: rcx (in)
191 * flags: rflags (in/out)
192 * ex: rsi (in:fastop pointer, out:zero if exception)
193 *
194 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
195 * different operand sizes can be reached by calculation, rather than a jump
196 * table (which would be bigger than the code).
197 *
198 * fastop functions are declared as taking a never-defined fastop parameter,
199 * so they can't be called from C directly.
200 */
201
202 struct fastop;
203
204 struct opcode {
205 u64 flags : 56;
206 u64 intercept : 8;
207 union {
208 int (*execute)(struct x86_emulate_ctxt *ctxt);
209 const struct opcode *group;
210 const struct group_dual *gdual;
211 const struct gprefix *gprefix;
212 const struct escape *esc;
213 void (*fastop)(struct fastop *fake);
214 } u;
215 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
216 };
217
218 struct group_dual {
219 struct opcode mod012[8];
220 struct opcode mod3[8];
221 };
222
223 struct gprefix {
224 struct opcode pfx_no;
225 struct opcode pfx_66;
226 struct opcode pfx_f2;
227 struct opcode pfx_f3;
228 };
229
230 struct escape {
231 struct opcode op[8];
232 struct opcode high[64];
233 };
234
235 /* EFLAGS bit definitions. */
236 #define EFLG_ID (1<<21)
237 #define EFLG_VIP (1<<20)
238 #define EFLG_VIF (1<<19)
239 #define EFLG_AC (1<<18)
240 #define EFLG_VM (1<<17)
241 #define EFLG_RF (1<<16)
242 #define EFLG_IOPL (3<<12)
243 #define EFLG_NT (1<<14)
244 #define EFLG_OF (1<<11)
245 #define EFLG_DF (1<<10)
246 #define EFLG_IF (1<<9)
247 #define EFLG_TF (1<<8)
248 #define EFLG_SF (1<<7)
249 #define EFLG_ZF (1<<6)
250 #define EFLG_AF (1<<4)
251 #define EFLG_PF (1<<2)
252 #define EFLG_CF (1<<0)
253
254 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
255 #define EFLG_RESERVED_ONE_MASK 2
256
257 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
258 {
259 if (!(ctxt->regs_valid & (1 << nr))) {
260 ctxt->regs_valid |= 1 << nr;
261 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
262 }
263 return ctxt->_regs[nr];
264 }
265
266 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
267 {
268 ctxt->regs_valid |= 1 << nr;
269 ctxt->regs_dirty |= 1 << nr;
270 return &ctxt->_regs[nr];
271 }
272
273 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
274 {
275 reg_read(ctxt, nr);
276 return reg_write(ctxt, nr);
277 }
278
279 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
280 {
281 unsigned reg;
282
283 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
284 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
285 }
286
287 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
288 {
289 ctxt->regs_dirty = 0;
290 ctxt->regs_valid = 0;
291 }
292
293 /*
294 * These EFLAGS bits are restored from saved value during emulation, and
295 * any changes are written back to the saved value after emulation.
296 */
297 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
298
299 #ifdef CONFIG_X86_64
300 #define ON64(x) x
301 #else
302 #define ON64(x)
303 #endif
304
305 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
306
307 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
308 #define FOP_RET "ret \n\t"
309
310 #define FOP_START(op) \
311 extern void em_##op(struct fastop *fake); \
312 asm(".pushsection .text, \"ax\" \n\t" \
313 ".global em_" #op " \n\t" \
314 FOP_ALIGN \
315 "em_" #op ": \n\t"
316
317 #define FOP_END \
318 ".popsection")
319
320 #define FOPNOP() FOP_ALIGN FOP_RET
321
322 #define FOP1E(op, dst) \
323 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
324
325 #define FOP1EEX(op, dst) \
326 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
327
328 #define FASTOP1(op) \
329 FOP_START(op) \
330 FOP1E(op##b, al) \
331 FOP1E(op##w, ax) \
332 FOP1E(op##l, eax) \
333 ON64(FOP1E(op##q, rax)) \
334 FOP_END
335
336 /* 1-operand, using src2 (for MUL/DIV r/m) */
337 #define FASTOP1SRC2(op, name) \
338 FOP_START(name) \
339 FOP1E(op, cl) \
340 FOP1E(op, cx) \
341 FOP1E(op, ecx) \
342 ON64(FOP1E(op, rcx)) \
343 FOP_END
344
345 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
346 #define FASTOP1SRC2EX(op, name) \
347 FOP_START(name) \
348 FOP1EEX(op, cl) \
349 FOP1EEX(op, cx) \
350 FOP1EEX(op, ecx) \
351 ON64(FOP1EEX(op, rcx)) \
352 FOP_END
353
354 #define FOP2E(op, dst, src) \
355 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
356
357 #define FASTOP2(op) \
358 FOP_START(op) \
359 FOP2E(op##b, al, dl) \
360 FOP2E(op##w, ax, dx) \
361 FOP2E(op##l, eax, edx) \
362 ON64(FOP2E(op##q, rax, rdx)) \
363 FOP_END
364
365 /* 2 operand, word only */
366 #define FASTOP2W(op) \
367 FOP_START(op) \
368 FOPNOP() \
369 FOP2E(op##w, ax, dx) \
370 FOP2E(op##l, eax, edx) \
371 ON64(FOP2E(op##q, rax, rdx)) \
372 FOP_END
373
374 /* 2 operand, src is CL */
375 #define FASTOP2CL(op) \
376 FOP_START(op) \
377 FOP2E(op##b, al, cl) \
378 FOP2E(op##w, ax, cl) \
379 FOP2E(op##l, eax, cl) \
380 ON64(FOP2E(op##q, rax, cl)) \
381 FOP_END
382
383 #define FOP3E(op, dst, src, src2) \
384 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
385
386 /* 3-operand, word-only, src2=cl */
387 #define FASTOP3WCL(op) \
388 FOP_START(op) \
389 FOPNOP() \
390 FOP3E(op##w, ax, dx, cl) \
391 FOP3E(op##l, eax, edx, cl) \
392 ON64(FOP3E(op##q, rax, rdx, cl)) \
393 FOP_END
394
395 /* Special case for SETcc - 1 instruction per cc */
396 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
397
398 asm(".global kvm_fastop_exception \n"
399 "kvm_fastop_exception: xor %esi, %esi; ret");
400
401 FOP_START(setcc)
402 FOP_SETCC(seto)
403 FOP_SETCC(setno)
404 FOP_SETCC(setc)
405 FOP_SETCC(setnc)
406 FOP_SETCC(setz)
407 FOP_SETCC(setnz)
408 FOP_SETCC(setbe)
409 FOP_SETCC(setnbe)
410 FOP_SETCC(sets)
411 FOP_SETCC(setns)
412 FOP_SETCC(setp)
413 FOP_SETCC(setnp)
414 FOP_SETCC(setl)
415 FOP_SETCC(setnl)
416 FOP_SETCC(setle)
417 FOP_SETCC(setnle)
418 FOP_END;
419
420 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
421 FOP_END;
422
423 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
424 enum x86_intercept intercept,
425 enum x86_intercept_stage stage)
426 {
427 struct x86_instruction_info info = {
428 .intercept = intercept,
429 .rep_prefix = ctxt->rep_prefix,
430 .modrm_mod = ctxt->modrm_mod,
431 .modrm_reg = ctxt->modrm_reg,
432 .modrm_rm = ctxt->modrm_rm,
433 .src_val = ctxt->src.val64,
434 .dst_val = ctxt->dst.val64,
435 .src_bytes = ctxt->src.bytes,
436 .dst_bytes = ctxt->dst.bytes,
437 .ad_bytes = ctxt->ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
441 return ctxt->ops->intercept(ctxt, &info, stage);
442 }
443
444 static void assign_masked(ulong *dest, ulong src, ulong mask)
445 {
446 *dest = (*dest & ~mask) | (src & mask);
447 }
448
449 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
450 {
451 return (1UL << (ctxt->ad_bytes << 3)) - 1;
452 }
453
454 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
455 {
456 u16 sel;
457 struct desc_struct ss;
458
459 if (ctxt->mode == X86EMUL_MODE_PROT64)
460 return ~0UL;
461 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
462 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
463 }
464
465 static int stack_size(struct x86_emulate_ctxt *ctxt)
466 {
467 return (__fls(stack_mask(ctxt)) + 1) >> 3;
468 }
469
470 /* Access/update address held in a register, based on addressing mode. */
471 static inline unsigned long
472 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
473 {
474 if (ctxt->ad_bytes == sizeof(unsigned long))
475 return reg;
476 else
477 return reg & ad_mask(ctxt);
478 }
479
480 static inline unsigned long
481 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
482 {
483 return address_mask(ctxt, reg);
484 }
485
486 static void masked_increment(ulong *reg, ulong mask, int inc)
487 {
488 assign_masked(reg, *reg + inc, mask);
489 }
490
491 static inline void
492 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
493 {
494 ulong mask;
495
496 if (ctxt->ad_bytes == sizeof(unsigned long))
497 mask = ~0UL;
498 else
499 mask = ad_mask(ctxt);
500 masked_increment(reg, mask, inc);
501 }
502
503 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
504 {
505 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
506 }
507
508 static u32 desc_limit_scaled(struct desc_struct *desc)
509 {
510 u32 limit = get_desc_limit(desc);
511
512 return desc->g ? (limit << 12) | 0xfff : limit;
513 }
514
515 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
516 {
517 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
518 return 0;
519
520 return ctxt->ops->get_cached_segment_base(ctxt, seg);
521 }
522
523 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
524 u32 error, bool valid)
525 {
526 WARN_ON(vec > 0x1f);
527 ctxt->exception.vector = vec;
528 ctxt->exception.error_code = error;
529 ctxt->exception.error_code_valid = valid;
530 return X86EMUL_PROPAGATE_FAULT;
531 }
532
533 static int emulate_db(struct x86_emulate_ctxt *ctxt)
534 {
535 return emulate_exception(ctxt, DB_VECTOR, 0, false);
536 }
537
538 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
539 {
540 return emulate_exception(ctxt, GP_VECTOR, err, true);
541 }
542
543 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
544 {
545 return emulate_exception(ctxt, SS_VECTOR, err, true);
546 }
547
548 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
549 {
550 return emulate_exception(ctxt, UD_VECTOR, 0, false);
551 }
552
553 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
554 {
555 return emulate_exception(ctxt, TS_VECTOR, err, true);
556 }
557
558 static int emulate_de(struct x86_emulate_ctxt *ctxt)
559 {
560 return emulate_exception(ctxt, DE_VECTOR, 0, false);
561 }
562
563 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
564 {
565 return emulate_exception(ctxt, NM_VECTOR, 0, false);
566 }
567
568 static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
569 int cs_l)
570 {
571 switch (ctxt->op_bytes) {
572 case 2:
573 ctxt->_eip = (u16)dst;
574 break;
575 case 4:
576 ctxt->_eip = (u32)dst;
577 break;
578 #ifdef CONFIG_X86_64
579 case 8:
580 if ((cs_l && is_noncanonical_address(dst)) ||
581 (!cs_l && (dst >> 32) != 0))
582 return emulate_gp(ctxt, 0);
583 ctxt->_eip = dst;
584 break;
585 #endif
586 default:
587 WARN(1, "unsupported eip assignment size\n");
588 }
589 return X86EMUL_CONTINUE;
590 }
591
592 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
593 {
594 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
595 }
596
597 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
598 {
599 return assign_eip_near(ctxt, ctxt->_eip + rel);
600 }
601
602 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
603 {
604 u16 selector;
605 struct desc_struct desc;
606
607 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
608 return selector;
609 }
610
611 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
612 unsigned seg)
613 {
614 u16 dummy;
615 u32 base3;
616 struct desc_struct desc;
617
618 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
619 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
620 }
621
622 /*
623 * x86 defines three classes of vector instructions: explicitly
624 * aligned, explicitly unaligned, and the rest, which change behaviour
625 * depending on whether they're AVX encoded or not.
626 *
627 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
628 * subject to the same check.
629 */
630 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
631 {
632 if (likely(size < 16))
633 return false;
634
635 if (ctxt->d & Aligned)
636 return true;
637 else if (ctxt->d & Unaligned)
638 return false;
639 else if (ctxt->d & Avx)
640 return false;
641 else
642 return true;
643 }
644
645 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
646 struct segmented_address addr,
647 unsigned *max_size, unsigned size,
648 bool write, bool fetch,
649 ulong *linear)
650 {
651 struct desc_struct desc;
652 bool usable;
653 ulong la;
654 u32 lim;
655 u16 sel;
656 unsigned cpl;
657
658 la = seg_base(ctxt, addr.seg) + addr.ea;
659 *max_size = 0;
660 switch (ctxt->mode) {
661 case X86EMUL_MODE_PROT64:
662 if (is_noncanonical_address(la))
663 return emulate_gp(ctxt, 0);
664
665 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
666 if (size > *max_size)
667 goto bad;
668 break;
669 default:
670 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
671 addr.seg);
672 if (!usable)
673 goto bad;
674 /* code segment in protected mode or read-only data segment */
675 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
676 || !(desc.type & 2)) && write)
677 goto bad;
678 /* unreadable code segment */
679 if (!fetch && (desc.type & 8) && !(desc.type & 2))
680 goto bad;
681 lim = desc_limit_scaled(&desc);
682 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
683 (ctxt->d & NoBigReal)) {
684 /* la is between zero and 0xffff */
685 if (la > 0xffff)
686 goto bad;
687 *max_size = 0x10000 - la;
688 } else if ((desc.type & 8) || !(desc.type & 4)) {
689 /* expand-up segment */
690 if (addr.ea > lim)
691 goto bad;
692 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
693 } else {
694 /* expand-down segment */
695 if (addr.ea <= lim)
696 goto bad;
697 lim = desc.d ? 0xffffffff : 0xffff;
698 if (addr.ea > lim)
699 goto bad;
700 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
701 }
702 if (size > *max_size)
703 goto bad;
704 cpl = ctxt->ops->cpl(ctxt);
705 if (!(desc.type & 8)) {
706 /* data segment */
707 if (cpl > desc.dpl)
708 goto bad;
709 } else if ((desc.type & 8) && !(desc.type & 4)) {
710 /* nonconforming code segment */
711 if (cpl != desc.dpl)
712 goto bad;
713 } else if ((desc.type & 8) && (desc.type & 4)) {
714 /* conforming code segment */
715 if (cpl < desc.dpl)
716 goto bad;
717 }
718 break;
719 }
720 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
721 la &= (u32)-1;
722 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
723 return emulate_gp(ctxt, 0);
724 *linear = la;
725 return X86EMUL_CONTINUE;
726 bad:
727 if (addr.seg == VCPU_SREG_SS)
728 return emulate_ss(ctxt, 0);
729 else
730 return emulate_gp(ctxt, 0);
731 }
732
733 static int linearize(struct x86_emulate_ctxt *ctxt,
734 struct segmented_address addr,
735 unsigned size, bool write,
736 ulong *linear)
737 {
738 unsigned max_size;
739 return __linearize(ctxt, addr, &max_size, size, write, false, linear);
740 }
741
742
743 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
744 struct segmented_address addr,
745 void *data,
746 unsigned size)
747 {
748 int rc;
749 ulong linear;
750
751 rc = linearize(ctxt, addr, size, false, &linear);
752 if (rc != X86EMUL_CONTINUE)
753 return rc;
754 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
755 }
756
757 /*
758 * Prefetch the remaining bytes of the instruction without crossing page
759 * boundary if they are not in fetch_cache yet.
760 */
761 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
762 {
763 int rc;
764 unsigned size, max_size;
765 unsigned long linear;
766 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
767 struct segmented_address addr = { .seg = VCPU_SREG_CS,
768 .ea = ctxt->eip + cur_size };
769
770 /*
771 * We do not know exactly how many bytes will be needed, and
772 * __linearize is expensive, so fetch as much as possible. We
773 * just have to avoid going beyond the 15 byte limit, the end
774 * of the segment, or the end of the page.
775 *
776 * __linearize is called with size 0 so that it does not do any
777 * boundary check itself. Instead, we use max_size to check
778 * against op_size.
779 */
780 rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
781 if (unlikely(rc != X86EMUL_CONTINUE))
782 return rc;
783
784 size = min_t(unsigned, 15UL ^ cur_size, max_size);
785 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
786
787 /*
788 * One instruction can only straddle two pages,
789 * and one has been loaded at the beginning of
790 * x86_decode_insn. So, if not enough bytes
791 * still, we must have hit the 15-byte boundary.
792 */
793 if (unlikely(size < op_size))
794 return emulate_gp(ctxt, 0);
795
796 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
797 size, &ctxt->exception);
798 if (unlikely(rc != X86EMUL_CONTINUE))
799 return rc;
800 ctxt->fetch.end += size;
801 return X86EMUL_CONTINUE;
802 }
803
804 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
805 unsigned size)
806 {
807 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
808
809 if (unlikely(done_size < size))
810 return __do_insn_fetch_bytes(ctxt, size - done_size);
811 else
812 return X86EMUL_CONTINUE;
813 }
814
815 /* Fetch next part of the instruction being emulated. */
816 #define insn_fetch(_type, _ctxt) \
817 ({ _type _x; \
818 \
819 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
820 if (rc != X86EMUL_CONTINUE) \
821 goto done; \
822 ctxt->_eip += sizeof(_type); \
823 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
824 ctxt->fetch.ptr += sizeof(_type); \
825 _x; \
826 })
827
828 #define insn_fetch_arr(_arr, _size, _ctxt) \
829 ({ \
830 rc = do_insn_fetch_bytes(_ctxt, _size); \
831 if (rc != X86EMUL_CONTINUE) \
832 goto done; \
833 ctxt->_eip += (_size); \
834 memcpy(_arr, ctxt->fetch.ptr, _size); \
835 ctxt->fetch.ptr += (_size); \
836 })
837
838 /*
839 * Given the 'reg' portion of a ModRM byte, and a register block, return a
840 * pointer into the block that addresses the relevant register.
841 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
842 */
843 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
844 int byteop)
845 {
846 void *p;
847 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
848
849 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
850 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
851 else
852 p = reg_rmw(ctxt, modrm_reg);
853 return p;
854 }
855
856 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
857 struct segmented_address addr,
858 u16 *size, unsigned long *address, int op_bytes)
859 {
860 int rc;
861
862 if (op_bytes == 2)
863 op_bytes = 3;
864 *address = 0;
865 rc = segmented_read_std(ctxt, addr, size, 2);
866 if (rc != X86EMUL_CONTINUE)
867 return rc;
868 addr.ea += 2;
869 rc = segmented_read_std(ctxt, addr, address, op_bytes);
870 return rc;
871 }
872
873 FASTOP2(add);
874 FASTOP2(or);
875 FASTOP2(adc);
876 FASTOP2(sbb);
877 FASTOP2(and);
878 FASTOP2(sub);
879 FASTOP2(xor);
880 FASTOP2(cmp);
881 FASTOP2(test);
882
883 FASTOP1SRC2(mul, mul_ex);
884 FASTOP1SRC2(imul, imul_ex);
885 FASTOP1SRC2EX(div, div_ex);
886 FASTOP1SRC2EX(idiv, idiv_ex);
887
888 FASTOP3WCL(shld);
889 FASTOP3WCL(shrd);
890
891 FASTOP2W(imul);
892
893 FASTOP1(not);
894 FASTOP1(neg);
895 FASTOP1(inc);
896 FASTOP1(dec);
897
898 FASTOP2CL(rol);
899 FASTOP2CL(ror);
900 FASTOP2CL(rcl);
901 FASTOP2CL(rcr);
902 FASTOP2CL(shl);
903 FASTOP2CL(shr);
904 FASTOP2CL(sar);
905
906 FASTOP2W(bsf);
907 FASTOP2W(bsr);
908 FASTOP2W(bt);
909 FASTOP2W(bts);
910 FASTOP2W(btr);
911 FASTOP2W(btc);
912
913 FASTOP2(xadd);
914
915 static u8 test_cc(unsigned int condition, unsigned long flags)
916 {
917 u8 rc;
918 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
919
920 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
921 asm("push %[flags]; popf; call *%[fastop]"
922 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
923 return rc;
924 }
925
926 static void fetch_register_operand(struct operand *op)
927 {
928 switch (op->bytes) {
929 case 1:
930 op->val = *(u8 *)op->addr.reg;
931 break;
932 case 2:
933 op->val = *(u16 *)op->addr.reg;
934 break;
935 case 4:
936 op->val = *(u32 *)op->addr.reg;
937 break;
938 case 8:
939 op->val = *(u64 *)op->addr.reg;
940 break;
941 }
942 }
943
944 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
945 {
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
948 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
949 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
950 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
951 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
952 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
953 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
954 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
955 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
956 #ifdef CONFIG_X86_64
957 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
958 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
959 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
960 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
961 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
962 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
963 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
964 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
965 #endif
966 default: BUG();
967 }
968 ctxt->ops->put_fpu(ctxt);
969 }
970
971 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
972 int reg)
973 {
974 ctxt->ops->get_fpu(ctxt);
975 switch (reg) {
976 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
977 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
978 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
979 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
980 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
981 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
982 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
983 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
984 #ifdef CONFIG_X86_64
985 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
986 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
987 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
988 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
989 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
990 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
991 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
992 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
993 #endif
994 default: BUG();
995 }
996 ctxt->ops->put_fpu(ctxt);
997 }
998
999 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1000 {
1001 ctxt->ops->get_fpu(ctxt);
1002 switch (reg) {
1003 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1004 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1005 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1006 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1007 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1008 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1009 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1010 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1011 default: BUG();
1012 }
1013 ctxt->ops->put_fpu(ctxt);
1014 }
1015
1016 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1017 {
1018 ctxt->ops->get_fpu(ctxt);
1019 switch (reg) {
1020 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1021 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1022 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1023 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1024 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1025 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1026 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1027 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1028 default: BUG();
1029 }
1030 ctxt->ops->put_fpu(ctxt);
1031 }
1032
1033 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1034 {
1035 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1036 return emulate_nm(ctxt);
1037
1038 ctxt->ops->get_fpu(ctxt);
1039 asm volatile("fninit");
1040 ctxt->ops->put_fpu(ctxt);
1041 return X86EMUL_CONTINUE;
1042 }
1043
1044 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1045 {
1046 u16 fcw;
1047
1048 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1049 return emulate_nm(ctxt);
1050
1051 ctxt->ops->get_fpu(ctxt);
1052 asm volatile("fnstcw %0": "+m"(fcw));
1053 ctxt->ops->put_fpu(ctxt);
1054
1055 /* force 2 byte destination */
1056 ctxt->dst.bytes = 2;
1057 ctxt->dst.val = fcw;
1058
1059 return X86EMUL_CONTINUE;
1060 }
1061
1062 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1063 {
1064 u16 fsw;
1065
1066 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1067 return emulate_nm(ctxt);
1068
1069 ctxt->ops->get_fpu(ctxt);
1070 asm volatile("fnstsw %0": "+m"(fsw));
1071 ctxt->ops->put_fpu(ctxt);
1072
1073 /* force 2 byte destination */
1074 ctxt->dst.bytes = 2;
1075 ctxt->dst.val = fsw;
1076
1077 return X86EMUL_CONTINUE;
1078 }
1079
1080 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1081 struct operand *op)
1082 {
1083 unsigned reg = ctxt->modrm_reg;
1084
1085 if (!(ctxt->d & ModRM))
1086 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1087
1088 if (ctxt->d & Sse) {
1089 op->type = OP_XMM;
1090 op->bytes = 16;
1091 op->addr.xmm = reg;
1092 read_sse_reg(ctxt, &op->vec_val, reg);
1093 return;
1094 }
1095 if (ctxt->d & Mmx) {
1096 reg &= 7;
1097 op->type = OP_MM;
1098 op->bytes = 8;
1099 op->addr.mm = reg;
1100 return;
1101 }
1102
1103 op->type = OP_REG;
1104 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1105 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1106
1107 fetch_register_operand(op);
1108 op->orig_val = op->val;
1109 }
1110
1111 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1112 {
1113 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1114 ctxt->modrm_seg = VCPU_SREG_SS;
1115 }
1116
1117 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1118 struct operand *op)
1119 {
1120 u8 sib;
1121 int index_reg, base_reg, scale;
1122 int rc = X86EMUL_CONTINUE;
1123 ulong modrm_ea = 0;
1124
1125 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1126 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1127 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1128
1129 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1130 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1131 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1132 ctxt->modrm_seg = VCPU_SREG_DS;
1133
1134 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1135 op->type = OP_REG;
1136 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1137 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1138 ctxt->d & ByteOp);
1139 if (ctxt->d & Sse) {
1140 op->type = OP_XMM;
1141 op->bytes = 16;
1142 op->addr.xmm = ctxt->modrm_rm;
1143 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1144 return rc;
1145 }
1146 if (ctxt->d & Mmx) {
1147 op->type = OP_MM;
1148 op->bytes = 8;
1149 op->addr.mm = ctxt->modrm_rm & 7;
1150 return rc;
1151 }
1152 fetch_register_operand(op);
1153 return rc;
1154 }
1155
1156 op->type = OP_MEM;
1157
1158 if (ctxt->ad_bytes == 2) {
1159 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1160 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1161 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1162 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1163
1164 /* 16-bit ModR/M decode. */
1165 switch (ctxt->modrm_mod) {
1166 case 0:
1167 if (ctxt->modrm_rm == 6)
1168 modrm_ea += insn_fetch(u16, ctxt);
1169 break;
1170 case 1:
1171 modrm_ea += insn_fetch(s8, ctxt);
1172 break;
1173 case 2:
1174 modrm_ea += insn_fetch(u16, ctxt);
1175 break;
1176 }
1177 switch (ctxt->modrm_rm) {
1178 case 0:
1179 modrm_ea += bx + si;
1180 break;
1181 case 1:
1182 modrm_ea += bx + di;
1183 break;
1184 case 2:
1185 modrm_ea += bp + si;
1186 break;
1187 case 3:
1188 modrm_ea += bp + di;
1189 break;
1190 case 4:
1191 modrm_ea += si;
1192 break;
1193 case 5:
1194 modrm_ea += di;
1195 break;
1196 case 6:
1197 if (ctxt->modrm_mod != 0)
1198 modrm_ea += bp;
1199 break;
1200 case 7:
1201 modrm_ea += bx;
1202 break;
1203 }
1204 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1205 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1206 ctxt->modrm_seg = VCPU_SREG_SS;
1207 modrm_ea = (u16)modrm_ea;
1208 } else {
1209 /* 32/64-bit ModR/M decode. */
1210 if ((ctxt->modrm_rm & 7) == 4) {
1211 sib = insn_fetch(u8, ctxt);
1212 index_reg |= (sib >> 3) & 7;
1213 base_reg |= sib & 7;
1214 scale = sib >> 6;
1215
1216 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1217 modrm_ea += insn_fetch(s32, ctxt);
1218 else {
1219 modrm_ea += reg_read(ctxt, base_reg);
1220 adjust_modrm_seg(ctxt, base_reg);
1221 }
1222 if (index_reg != 4)
1223 modrm_ea += reg_read(ctxt, index_reg) << scale;
1224 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1225 if (ctxt->mode == X86EMUL_MODE_PROT64)
1226 ctxt->rip_relative = 1;
1227 } else {
1228 base_reg = ctxt->modrm_rm;
1229 modrm_ea += reg_read(ctxt, base_reg);
1230 adjust_modrm_seg(ctxt, base_reg);
1231 }
1232 switch (ctxt->modrm_mod) {
1233 case 0:
1234 if (ctxt->modrm_rm == 5)
1235 modrm_ea += insn_fetch(s32, ctxt);
1236 break;
1237 case 1:
1238 modrm_ea += insn_fetch(s8, ctxt);
1239 break;
1240 case 2:
1241 modrm_ea += insn_fetch(s32, ctxt);
1242 break;
1243 }
1244 }
1245 op->addr.mem.ea = modrm_ea;
1246 if (ctxt->ad_bytes != 8)
1247 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1248
1249 done:
1250 return rc;
1251 }
1252
1253 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1254 struct operand *op)
1255 {
1256 int rc = X86EMUL_CONTINUE;
1257
1258 op->type = OP_MEM;
1259 switch (ctxt->ad_bytes) {
1260 case 2:
1261 op->addr.mem.ea = insn_fetch(u16, ctxt);
1262 break;
1263 case 4:
1264 op->addr.mem.ea = insn_fetch(u32, ctxt);
1265 break;
1266 case 8:
1267 op->addr.mem.ea = insn_fetch(u64, ctxt);
1268 break;
1269 }
1270 done:
1271 return rc;
1272 }
1273
1274 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1275 {
1276 long sv = 0, mask;
1277
1278 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1279 mask = ~((long)ctxt->dst.bytes * 8 - 1);
1280
1281 if (ctxt->src.bytes == 2)
1282 sv = (s16)ctxt->src.val & (s16)mask;
1283 else if (ctxt->src.bytes == 4)
1284 sv = (s32)ctxt->src.val & (s32)mask;
1285 else
1286 sv = (s64)ctxt->src.val & (s64)mask;
1287
1288 ctxt->dst.addr.mem.ea += (sv >> 3);
1289 }
1290
1291 /* only subword offset */
1292 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1293 }
1294
1295 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1296 unsigned long addr, void *dest, unsigned size)
1297 {
1298 int rc;
1299 struct read_cache *mc = &ctxt->mem_read;
1300
1301 if (mc->pos < mc->end)
1302 goto read_cached;
1303
1304 WARN_ON((mc->end + size) >= sizeof(mc->data));
1305
1306 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1307 &ctxt->exception);
1308 if (rc != X86EMUL_CONTINUE)
1309 return rc;
1310
1311 mc->end += size;
1312
1313 read_cached:
1314 memcpy(dest, mc->data + mc->pos, size);
1315 mc->pos += size;
1316 return X86EMUL_CONTINUE;
1317 }
1318
1319 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1320 struct segmented_address addr,
1321 void *data,
1322 unsigned size)
1323 {
1324 int rc;
1325 ulong linear;
1326
1327 rc = linearize(ctxt, addr, size, false, &linear);
1328 if (rc != X86EMUL_CONTINUE)
1329 return rc;
1330 return read_emulated(ctxt, linear, data, size);
1331 }
1332
1333 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1334 struct segmented_address addr,
1335 const void *data,
1336 unsigned size)
1337 {
1338 int rc;
1339 ulong linear;
1340
1341 rc = linearize(ctxt, addr, size, true, &linear);
1342 if (rc != X86EMUL_CONTINUE)
1343 return rc;
1344 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1345 &ctxt->exception);
1346 }
1347
1348 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1349 struct segmented_address addr,
1350 const void *orig_data, const void *data,
1351 unsigned size)
1352 {
1353 int rc;
1354 ulong linear;
1355
1356 rc = linearize(ctxt, addr, size, true, &linear);
1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
1359 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1360 size, &ctxt->exception);
1361 }
1362
1363 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1364 unsigned int size, unsigned short port,
1365 void *dest)
1366 {
1367 struct read_cache *rc = &ctxt->io_read;
1368
1369 if (rc->pos == rc->end) { /* refill pio read ahead */
1370 unsigned int in_page, n;
1371 unsigned int count = ctxt->rep_prefix ?
1372 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1373 in_page = (ctxt->eflags & EFLG_DF) ?
1374 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1375 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1376 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1377 if (n == 0)
1378 n = 1;
1379 rc->pos = rc->end = 0;
1380 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1381 return 0;
1382 rc->end = n * size;
1383 }
1384
1385 if (ctxt->rep_prefix && (ctxt->d & String) &&
1386 !(ctxt->eflags & EFLG_DF)) {
1387 ctxt->dst.data = rc->data + rc->pos;
1388 ctxt->dst.type = OP_MEM_STR;
1389 ctxt->dst.count = (rc->end - rc->pos) / size;
1390 rc->pos = rc->end;
1391 } else {
1392 memcpy(dest, rc->data + rc->pos, size);
1393 rc->pos += size;
1394 }
1395 return 1;
1396 }
1397
1398 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1399 u16 index, struct desc_struct *desc)
1400 {
1401 struct desc_ptr dt;
1402 ulong addr;
1403
1404 ctxt->ops->get_idt(ctxt, &dt);
1405
1406 if (dt.size < index * 8 + 7)
1407 return emulate_gp(ctxt, index << 3 | 0x2);
1408
1409 addr = dt.address + index * 8;
1410 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1411 &ctxt->exception);
1412 }
1413
1414 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1415 u16 selector, struct desc_ptr *dt)
1416 {
1417 const struct x86_emulate_ops *ops = ctxt->ops;
1418 u32 base3 = 0;
1419
1420 if (selector & 1 << 2) {
1421 struct desc_struct desc;
1422 u16 sel;
1423
1424 memset (dt, 0, sizeof *dt);
1425 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1426 VCPU_SREG_LDTR))
1427 return;
1428
1429 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1430 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1431 } else
1432 ops->get_gdt(ctxt, dt);
1433 }
1434
1435 /* allowed just for 8 bytes segments */
1436 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1437 u16 selector, struct desc_struct *desc,
1438 ulong *desc_addr_p)
1439 {
1440 struct desc_ptr dt;
1441 u16 index = selector >> 3;
1442 ulong addr;
1443
1444 get_descriptor_table_ptr(ctxt, selector, &dt);
1445
1446 if (dt.size < index * 8 + 7)
1447 return emulate_gp(ctxt, selector & 0xfffc);
1448
1449 *desc_addr_p = addr = dt.address + index * 8;
1450 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1451 &ctxt->exception);
1452 }
1453
1454 /* allowed just for 8 bytes segments */
1455 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1456 u16 selector, struct desc_struct *desc)
1457 {
1458 struct desc_ptr dt;
1459 u16 index = selector >> 3;
1460 ulong addr;
1461
1462 get_descriptor_table_ptr(ctxt, selector, &dt);
1463
1464 if (dt.size < index * 8 + 7)
1465 return emulate_gp(ctxt, selector & 0xfffc);
1466
1467 addr = dt.address + index * 8;
1468 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1469 &ctxt->exception);
1470 }
1471
1472 /* Does not support long mode */
1473 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1474 u16 selector, int seg, u8 cpl,
1475 bool in_task_switch,
1476 struct desc_struct *desc)
1477 {
1478 struct desc_struct seg_desc, old_desc;
1479 u8 dpl, rpl;
1480 unsigned err_vec = GP_VECTOR;
1481 u32 err_code = 0;
1482 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1483 ulong desc_addr;
1484 int ret;
1485 u16 dummy;
1486 u32 base3 = 0;
1487
1488 memset(&seg_desc, 0, sizeof seg_desc);
1489
1490 if (ctxt->mode == X86EMUL_MODE_REAL) {
1491 /* set real mode segment descriptor (keep limit etc. for
1492 * unreal mode) */
1493 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1494 set_desc_base(&seg_desc, selector << 4);
1495 goto load;
1496 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1497 /* VM86 needs a clean new segment descriptor */
1498 set_desc_base(&seg_desc, selector << 4);
1499 set_desc_limit(&seg_desc, 0xffff);
1500 seg_desc.type = 3;
1501 seg_desc.p = 1;
1502 seg_desc.s = 1;
1503 seg_desc.dpl = 3;
1504 goto load;
1505 }
1506
1507 rpl = selector & 3;
1508
1509 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1510 if ((seg == VCPU_SREG_CS
1511 || (seg == VCPU_SREG_SS
1512 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1513 || seg == VCPU_SREG_TR)
1514 && null_selector)
1515 goto exception;
1516
1517 /* TR should be in GDT only */
1518 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1519 goto exception;
1520
1521 if (null_selector) /* for NULL selector skip all following checks */
1522 goto load;
1523
1524 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1525 if (ret != X86EMUL_CONTINUE)
1526 return ret;
1527
1528 err_code = selector & 0xfffc;
1529 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
1530
1531 /* can't load system descriptor into segment selector */
1532 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1533 goto exception;
1534
1535 if (!seg_desc.p) {
1536 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1537 goto exception;
1538 }
1539
1540 dpl = seg_desc.dpl;
1541
1542 switch (seg) {
1543 case VCPU_SREG_SS:
1544 /*
1545 * segment is not a writable data segment or segment
1546 * selector's RPL != CPL or segment selector's RPL != CPL
1547 */
1548 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1549 goto exception;
1550 break;
1551 case VCPU_SREG_CS:
1552 if (!(seg_desc.type & 8))
1553 goto exception;
1554
1555 if (seg_desc.type & 4) {
1556 /* conforming */
1557 if (dpl > cpl)
1558 goto exception;
1559 } else {
1560 /* nonconforming */
1561 if (rpl > cpl || dpl != cpl)
1562 goto exception;
1563 }
1564 /* in long-mode d/b must be clear if l is set */
1565 if (seg_desc.d && seg_desc.l) {
1566 u64 efer = 0;
1567
1568 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1569 if (efer & EFER_LMA)
1570 goto exception;
1571 }
1572
1573 /* CS(RPL) <- CPL */
1574 selector = (selector & 0xfffc) | cpl;
1575 break;
1576 case VCPU_SREG_TR:
1577 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1578 goto exception;
1579 old_desc = seg_desc;
1580 seg_desc.type |= 2; /* busy */
1581 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1582 sizeof(seg_desc), &ctxt->exception);
1583 if (ret != X86EMUL_CONTINUE)
1584 return ret;
1585 break;
1586 case VCPU_SREG_LDTR:
1587 if (seg_desc.s || seg_desc.type != 2)
1588 goto exception;
1589 break;
1590 default: /* DS, ES, FS, or GS */
1591 /*
1592 * segment is not a data or readable code segment or
1593 * ((segment is a data or nonconforming code segment)
1594 * and (both RPL and CPL > DPL))
1595 */
1596 if ((seg_desc.type & 0xa) == 0x8 ||
1597 (((seg_desc.type & 0xc) != 0xc) &&
1598 (rpl > dpl && cpl > dpl)))
1599 goto exception;
1600 break;
1601 }
1602
1603 if (seg_desc.s) {
1604 /* mark segment as accessed */
1605 seg_desc.type |= 1;
1606 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1607 if (ret != X86EMUL_CONTINUE)
1608 return ret;
1609 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1610 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1611 sizeof(base3), &ctxt->exception);
1612 if (ret != X86EMUL_CONTINUE)
1613 return ret;
1614 }
1615 load:
1616 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1617 if (desc)
1618 *desc = seg_desc;
1619 return X86EMUL_CONTINUE;
1620 exception:
1621 return emulate_exception(ctxt, err_vec, err_code, true);
1622 }
1623
1624 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1625 u16 selector, int seg)
1626 {
1627 u8 cpl = ctxt->ops->cpl(ctxt);
1628 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
1629 }
1630
1631 static void write_register_operand(struct operand *op)
1632 {
1633 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1634 switch (op->bytes) {
1635 case 1:
1636 *(u8 *)op->addr.reg = (u8)op->val;
1637 break;
1638 case 2:
1639 *(u16 *)op->addr.reg = (u16)op->val;
1640 break;
1641 case 4:
1642 *op->addr.reg = (u32)op->val;
1643 break; /* 64b: zero-extend */
1644 case 8:
1645 *op->addr.reg = op->val;
1646 break;
1647 }
1648 }
1649
1650 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1651 {
1652 switch (op->type) {
1653 case OP_REG:
1654 write_register_operand(op);
1655 break;
1656 case OP_MEM:
1657 if (ctxt->lock_prefix)
1658 return segmented_cmpxchg(ctxt,
1659 op->addr.mem,
1660 &op->orig_val,
1661 &op->val,
1662 op->bytes);
1663 else
1664 return segmented_write(ctxt,
1665 op->addr.mem,
1666 &op->val,
1667 op->bytes);
1668 break;
1669 case OP_MEM_STR:
1670 return segmented_write(ctxt,
1671 op->addr.mem,
1672 op->data,
1673 op->bytes * op->count);
1674 break;
1675 case OP_XMM:
1676 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1677 break;
1678 case OP_MM:
1679 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1680 break;
1681 case OP_NONE:
1682 /* no writeback */
1683 break;
1684 default:
1685 break;
1686 }
1687 return X86EMUL_CONTINUE;
1688 }
1689
1690 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1691 {
1692 struct segmented_address addr;
1693
1694 rsp_increment(ctxt, -bytes);
1695 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1696 addr.seg = VCPU_SREG_SS;
1697
1698 return segmented_write(ctxt, addr, data, bytes);
1699 }
1700
1701 static int em_push(struct x86_emulate_ctxt *ctxt)
1702 {
1703 /* Disable writeback. */
1704 ctxt->dst.type = OP_NONE;
1705 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1706 }
1707
1708 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1709 void *dest, int len)
1710 {
1711 int rc;
1712 struct segmented_address addr;
1713
1714 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1715 addr.seg = VCPU_SREG_SS;
1716 rc = segmented_read(ctxt, addr, dest, len);
1717 if (rc != X86EMUL_CONTINUE)
1718 return rc;
1719
1720 rsp_increment(ctxt, len);
1721 return rc;
1722 }
1723
1724 static int em_pop(struct x86_emulate_ctxt *ctxt)
1725 {
1726 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1727 }
1728
1729 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1730 void *dest, int len)
1731 {
1732 int rc;
1733 unsigned long val, change_mask;
1734 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1735 int cpl = ctxt->ops->cpl(ctxt);
1736
1737 rc = emulate_pop(ctxt, &val, len);
1738 if (rc != X86EMUL_CONTINUE)
1739 return rc;
1740
1741 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1742 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
1743
1744 switch(ctxt->mode) {
1745 case X86EMUL_MODE_PROT64:
1746 case X86EMUL_MODE_PROT32:
1747 case X86EMUL_MODE_PROT16:
1748 if (cpl == 0)
1749 change_mask |= EFLG_IOPL;
1750 if (cpl <= iopl)
1751 change_mask |= EFLG_IF;
1752 break;
1753 case X86EMUL_MODE_VM86:
1754 if (iopl < 3)
1755 return emulate_gp(ctxt, 0);
1756 change_mask |= EFLG_IF;
1757 break;
1758 default: /* real mode */
1759 change_mask |= (EFLG_IOPL | EFLG_IF);
1760 break;
1761 }
1762
1763 *(unsigned long *)dest =
1764 (ctxt->eflags & ~change_mask) | (val & change_mask);
1765
1766 return rc;
1767 }
1768
1769 static int em_popf(struct x86_emulate_ctxt *ctxt)
1770 {
1771 ctxt->dst.type = OP_REG;
1772 ctxt->dst.addr.reg = &ctxt->eflags;
1773 ctxt->dst.bytes = ctxt->op_bytes;
1774 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1775 }
1776
1777 static int em_enter(struct x86_emulate_ctxt *ctxt)
1778 {
1779 int rc;
1780 unsigned frame_size = ctxt->src.val;
1781 unsigned nesting_level = ctxt->src2.val & 31;
1782 ulong rbp;
1783
1784 if (nesting_level)
1785 return X86EMUL_UNHANDLEABLE;
1786
1787 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1788 rc = push(ctxt, &rbp, stack_size(ctxt));
1789 if (rc != X86EMUL_CONTINUE)
1790 return rc;
1791 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1792 stack_mask(ctxt));
1793 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1794 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1795 stack_mask(ctxt));
1796 return X86EMUL_CONTINUE;
1797 }
1798
1799 static int em_leave(struct x86_emulate_ctxt *ctxt)
1800 {
1801 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1802 stack_mask(ctxt));
1803 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1804 }
1805
1806 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1807 {
1808 int seg = ctxt->src2.val;
1809
1810 ctxt->src.val = get_segment_selector(ctxt, seg);
1811
1812 return em_push(ctxt);
1813 }
1814
1815 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1816 {
1817 int seg = ctxt->src2.val;
1818 unsigned long selector;
1819 int rc;
1820
1821 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1822 if (rc != X86EMUL_CONTINUE)
1823 return rc;
1824
1825 if (ctxt->modrm_reg == VCPU_SREG_SS)
1826 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1827
1828 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1829 return rc;
1830 }
1831
1832 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1833 {
1834 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1835 int rc = X86EMUL_CONTINUE;
1836 int reg = VCPU_REGS_RAX;
1837
1838 while (reg <= VCPU_REGS_RDI) {
1839 (reg == VCPU_REGS_RSP) ?
1840 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1841
1842 rc = em_push(ctxt);
1843 if (rc != X86EMUL_CONTINUE)
1844 return rc;
1845
1846 ++reg;
1847 }
1848
1849 return rc;
1850 }
1851
1852 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1853 {
1854 ctxt->src.val = (unsigned long)ctxt->eflags;
1855 return em_push(ctxt);
1856 }
1857
1858 static int em_popa(struct x86_emulate_ctxt *ctxt)
1859 {
1860 int rc = X86EMUL_CONTINUE;
1861 int reg = VCPU_REGS_RDI;
1862
1863 while (reg >= VCPU_REGS_RAX) {
1864 if (reg == VCPU_REGS_RSP) {
1865 rsp_increment(ctxt, ctxt->op_bytes);
1866 --reg;
1867 }
1868
1869 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1870 if (rc != X86EMUL_CONTINUE)
1871 break;
1872 --reg;
1873 }
1874 return rc;
1875 }
1876
1877 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1878 {
1879 const struct x86_emulate_ops *ops = ctxt->ops;
1880 int rc;
1881 struct desc_ptr dt;
1882 gva_t cs_addr;
1883 gva_t eip_addr;
1884 u16 cs, eip;
1885
1886 /* TODO: Add limit checks */
1887 ctxt->src.val = ctxt->eflags;
1888 rc = em_push(ctxt);
1889 if (rc != X86EMUL_CONTINUE)
1890 return rc;
1891
1892 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1893
1894 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1895 rc = em_push(ctxt);
1896 if (rc != X86EMUL_CONTINUE)
1897 return rc;
1898
1899 ctxt->src.val = ctxt->_eip;
1900 rc = em_push(ctxt);
1901 if (rc != X86EMUL_CONTINUE)
1902 return rc;
1903
1904 ops->get_idt(ctxt, &dt);
1905
1906 eip_addr = dt.address + (irq << 2);
1907 cs_addr = dt.address + (irq << 2) + 2;
1908
1909 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
1913 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
1916
1917 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1918 if (rc != X86EMUL_CONTINUE)
1919 return rc;
1920
1921 ctxt->_eip = eip;
1922
1923 return rc;
1924 }
1925
1926 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1927 {
1928 int rc;
1929
1930 invalidate_registers(ctxt);
1931 rc = __emulate_int_real(ctxt, irq);
1932 if (rc == X86EMUL_CONTINUE)
1933 writeback_registers(ctxt);
1934 return rc;
1935 }
1936
1937 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1938 {
1939 switch(ctxt->mode) {
1940 case X86EMUL_MODE_REAL:
1941 return __emulate_int_real(ctxt, irq);
1942 case X86EMUL_MODE_VM86:
1943 case X86EMUL_MODE_PROT16:
1944 case X86EMUL_MODE_PROT32:
1945 case X86EMUL_MODE_PROT64:
1946 default:
1947 /* Protected mode interrupts unimplemented yet */
1948 return X86EMUL_UNHANDLEABLE;
1949 }
1950 }
1951
1952 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1953 {
1954 int rc = X86EMUL_CONTINUE;
1955 unsigned long temp_eip = 0;
1956 unsigned long temp_eflags = 0;
1957 unsigned long cs = 0;
1958 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1959 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1960 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1961 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1962
1963 /* TODO: Add stack limit check */
1964
1965 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1966
1967 if (rc != X86EMUL_CONTINUE)
1968 return rc;
1969
1970 if (temp_eip & ~0xffff)
1971 return emulate_gp(ctxt, 0);
1972
1973 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1974
1975 if (rc != X86EMUL_CONTINUE)
1976 return rc;
1977
1978 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1979
1980 if (rc != X86EMUL_CONTINUE)
1981 return rc;
1982
1983 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1984
1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
1987
1988 ctxt->_eip = temp_eip;
1989
1990
1991 if (ctxt->op_bytes == 4)
1992 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1993 else if (ctxt->op_bytes == 2) {
1994 ctxt->eflags &= ~0xffff;
1995 ctxt->eflags |= temp_eflags;
1996 }
1997
1998 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1999 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2000
2001 return rc;
2002 }
2003
2004 static int em_iret(struct x86_emulate_ctxt *ctxt)
2005 {
2006 switch(ctxt->mode) {
2007 case X86EMUL_MODE_REAL:
2008 return emulate_iret_real(ctxt);
2009 case X86EMUL_MODE_VM86:
2010 case X86EMUL_MODE_PROT16:
2011 case X86EMUL_MODE_PROT32:
2012 case X86EMUL_MODE_PROT64:
2013 default:
2014 /* iret from protected mode unimplemented yet */
2015 return X86EMUL_UNHANDLEABLE;
2016 }
2017 }
2018
2019 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2020 {
2021 int rc;
2022 unsigned short sel, old_sel;
2023 struct desc_struct old_desc, new_desc;
2024 const struct x86_emulate_ops *ops = ctxt->ops;
2025 u8 cpl = ctxt->ops->cpl(ctxt);
2026
2027 /* Assignment of RIP may only fail in 64-bit mode */
2028 if (ctxt->mode == X86EMUL_MODE_PROT64)
2029 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2030 VCPU_SREG_CS);
2031
2032 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2033
2034 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2035 &new_desc);
2036 if (rc != X86EMUL_CONTINUE)
2037 return rc;
2038
2039 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2040 if (rc != X86EMUL_CONTINUE) {
2041 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2042 /* assigning eip failed; restore the old cs */
2043 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2044 return rc;
2045 }
2046 return rc;
2047 }
2048
2049 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2050 {
2051 return assign_eip_near(ctxt, ctxt->src.val);
2052 }
2053
2054 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2055 {
2056 int rc;
2057 long int old_eip;
2058
2059 old_eip = ctxt->_eip;
2060 rc = assign_eip_near(ctxt, ctxt->src.val);
2061 if (rc != X86EMUL_CONTINUE)
2062 return rc;
2063 ctxt->src.val = old_eip;
2064 rc = em_push(ctxt);
2065 return rc;
2066 }
2067
2068 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2069 {
2070 u64 old = ctxt->dst.orig_val64;
2071
2072 if (ctxt->dst.bytes == 16)
2073 return X86EMUL_UNHANDLEABLE;
2074
2075 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2076 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2077 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2078 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2079 ctxt->eflags &= ~EFLG_ZF;
2080 } else {
2081 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2082 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2083
2084 ctxt->eflags |= EFLG_ZF;
2085 }
2086 return X86EMUL_CONTINUE;
2087 }
2088
2089 static int em_ret(struct x86_emulate_ctxt *ctxt)
2090 {
2091 int rc;
2092 unsigned long eip;
2093
2094 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2095 if (rc != X86EMUL_CONTINUE)
2096 return rc;
2097
2098 return assign_eip_near(ctxt, eip);
2099 }
2100
2101 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2102 {
2103 int rc;
2104 unsigned long eip, cs;
2105 u16 old_cs;
2106 int cpl = ctxt->ops->cpl(ctxt);
2107 struct desc_struct old_desc, new_desc;
2108 const struct x86_emulate_ops *ops = ctxt->ops;
2109
2110 if (ctxt->mode == X86EMUL_MODE_PROT64)
2111 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2112 VCPU_SREG_CS);
2113
2114 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2115 if (rc != X86EMUL_CONTINUE)
2116 return rc;
2117 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2118 if (rc != X86EMUL_CONTINUE)
2119 return rc;
2120 /* Outer-privilege level return is not implemented */
2121 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2122 return X86EMUL_UNHANDLEABLE;
2123 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2124 &new_desc);
2125 if (rc != X86EMUL_CONTINUE)
2126 return rc;
2127 rc = assign_eip_far(ctxt, eip, new_desc.l);
2128 if (rc != X86EMUL_CONTINUE) {
2129 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2130 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2131 }
2132 return rc;
2133 }
2134
2135 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2136 {
2137 int rc;
2138
2139 rc = em_ret_far(ctxt);
2140 if (rc != X86EMUL_CONTINUE)
2141 return rc;
2142 rsp_increment(ctxt, ctxt->src.val);
2143 return X86EMUL_CONTINUE;
2144 }
2145
2146 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2147 {
2148 /* Save real source value, then compare EAX against destination. */
2149 ctxt->dst.orig_val = ctxt->dst.val;
2150 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2151 ctxt->src.orig_val = ctxt->src.val;
2152 ctxt->src.val = ctxt->dst.orig_val;
2153 fastop(ctxt, em_cmp);
2154
2155 if (ctxt->eflags & EFLG_ZF) {
2156 /* Success: write back to memory. */
2157 ctxt->dst.val = ctxt->src.orig_val;
2158 } else {
2159 /* Failure: write the value we saw to EAX. */
2160 ctxt->dst.type = OP_REG;
2161 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2162 ctxt->dst.val = ctxt->dst.orig_val;
2163 }
2164 return X86EMUL_CONTINUE;
2165 }
2166
2167 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2168 {
2169 int seg = ctxt->src2.val;
2170 unsigned short sel;
2171 int rc;
2172
2173 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2174
2175 rc = load_segment_descriptor(ctxt, sel, seg);
2176 if (rc != X86EMUL_CONTINUE)
2177 return rc;
2178
2179 ctxt->dst.val = ctxt->src.val;
2180 return rc;
2181 }
2182
2183 static void
2184 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2185 struct desc_struct *cs, struct desc_struct *ss)
2186 {
2187 cs->l = 0; /* will be adjusted later */
2188 set_desc_base(cs, 0); /* flat segment */
2189 cs->g = 1; /* 4kb granularity */
2190 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2191 cs->type = 0x0b; /* Read, Execute, Accessed */
2192 cs->s = 1;
2193 cs->dpl = 0; /* will be adjusted later */
2194 cs->p = 1;
2195 cs->d = 1;
2196 cs->avl = 0;
2197
2198 set_desc_base(ss, 0); /* flat segment */
2199 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2200 ss->g = 1; /* 4kb granularity */
2201 ss->s = 1;
2202 ss->type = 0x03; /* Read/Write, Accessed */
2203 ss->d = 1; /* 32bit stack segment */
2204 ss->dpl = 0;
2205 ss->p = 1;
2206 ss->l = 0;
2207 ss->avl = 0;
2208 }
2209
2210 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2211 {
2212 u32 eax, ebx, ecx, edx;
2213
2214 eax = ecx = 0;
2215 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2216 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2217 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2218 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2219 }
2220
2221 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2222 {
2223 const struct x86_emulate_ops *ops = ctxt->ops;
2224 u32 eax, ebx, ecx, edx;
2225
2226 /*
2227 * syscall should always be enabled in longmode - so only become
2228 * vendor specific (cpuid) if other modes are active...
2229 */
2230 if (ctxt->mode == X86EMUL_MODE_PROT64)
2231 return true;
2232
2233 eax = 0x00000000;
2234 ecx = 0x00000000;
2235 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2236 /*
2237 * Intel ("GenuineIntel")
2238 * remark: Intel CPUs only support "syscall" in 64bit
2239 * longmode. Also an 64bit guest with a
2240 * 32bit compat-app running will #UD !! While this
2241 * behaviour can be fixed (by emulating) into AMD
2242 * response - CPUs of AMD can't behave like Intel.
2243 */
2244 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2245 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2246 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2247 return false;
2248
2249 /* AMD ("AuthenticAMD") */
2250 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2251 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2252 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2253 return true;
2254
2255 /* AMD ("AMDisbetter!") */
2256 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2257 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2258 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2259 return true;
2260
2261 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2262 return false;
2263 }
2264
2265 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2266 {
2267 const struct x86_emulate_ops *ops = ctxt->ops;
2268 struct desc_struct cs, ss;
2269 u64 msr_data;
2270 u16 cs_sel, ss_sel;
2271 u64 efer = 0;
2272
2273 /* syscall is not available in real mode */
2274 if (ctxt->mode == X86EMUL_MODE_REAL ||
2275 ctxt->mode == X86EMUL_MODE_VM86)
2276 return emulate_ud(ctxt);
2277
2278 if (!(em_syscall_is_enabled(ctxt)))
2279 return emulate_ud(ctxt);
2280
2281 ops->get_msr(ctxt, MSR_EFER, &efer);
2282 setup_syscalls_segments(ctxt, &cs, &ss);
2283
2284 if (!(efer & EFER_SCE))
2285 return emulate_ud(ctxt);
2286
2287 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2288 msr_data >>= 32;
2289 cs_sel = (u16)(msr_data & 0xfffc);
2290 ss_sel = (u16)(msr_data + 8);
2291
2292 if (efer & EFER_LMA) {
2293 cs.d = 0;
2294 cs.l = 1;
2295 }
2296 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2297 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2298
2299 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2300 if (efer & EFER_LMA) {
2301 #ifdef CONFIG_X86_64
2302 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2303
2304 ops->get_msr(ctxt,
2305 ctxt->mode == X86EMUL_MODE_PROT64 ?
2306 MSR_LSTAR : MSR_CSTAR, &msr_data);
2307 ctxt->_eip = msr_data;
2308
2309 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2310 ctxt->eflags &= ~msr_data;
2311 #endif
2312 } else {
2313 /* legacy mode */
2314 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2315 ctxt->_eip = (u32)msr_data;
2316
2317 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2318 }
2319
2320 return X86EMUL_CONTINUE;
2321 }
2322
2323 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2324 {
2325 const struct x86_emulate_ops *ops = ctxt->ops;
2326 struct desc_struct cs, ss;
2327 u64 msr_data;
2328 u16 cs_sel, ss_sel;
2329 u64 efer = 0;
2330
2331 ops->get_msr(ctxt, MSR_EFER, &efer);
2332 /* inject #GP if in real mode */
2333 if (ctxt->mode == X86EMUL_MODE_REAL)
2334 return emulate_gp(ctxt, 0);
2335
2336 /*
2337 * Not recognized on AMD in compat mode (but is recognized in legacy
2338 * mode).
2339 */
2340 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2341 && !vendor_intel(ctxt))
2342 return emulate_ud(ctxt);
2343
2344 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2345 * Therefore, we inject an #UD.
2346 */
2347 if (ctxt->mode == X86EMUL_MODE_PROT64)
2348 return emulate_ud(ctxt);
2349
2350 setup_syscalls_segments(ctxt, &cs, &ss);
2351
2352 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2353 switch (ctxt->mode) {
2354 case X86EMUL_MODE_PROT32:
2355 if ((msr_data & 0xfffc) == 0x0)
2356 return emulate_gp(ctxt, 0);
2357 break;
2358 case X86EMUL_MODE_PROT64:
2359 if (msr_data == 0x0)
2360 return emulate_gp(ctxt, 0);
2361 break;
2362 default:
2363 break;
2364 }
2365
2366 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2367 cs_sel = (u16)msr_data;
2368 cs_sel &= ~SELECTOR_RPL_MASK;
2369 ss_sel = cs_sel + 8;
2370 ss_sel &= ~SELECTOR_RPL_MASK;
2371 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2372 cs.d = 0;
2373 cs.l = 1;
2374 }
2375
2376 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2377 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2378
2379 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2380 ctxt->_eip = msr_data;
2381
2382 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2383 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2384
2385 return X86EMUL_CONTINUE;
2386 }
2387
2388 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2389 {
2390 const struct x86_emulate_ops *ops = ctxt->ops;
2391 struct desc_struct cs, ss;
2392 u64 msr_data, rcx, rdx;
2393 int usermode;
2394 u16 cs_sel = 0, ss_sel = 0;
2395
2396 /* inject #GP if in real mode or Virtual 8086 mode */
2397 if (ctxt->mode == X86EMUL_MODE_REAL ||
2398 ctxt->mode == X86EMUL_MODE_VM86)
2399 return emulate_gp(ctxt, 0);
2400
2401 setup_syscalls_segments(ctxt, &cs, &ss);
2402
2403 if ((ctxt->rex_prefix & 0x8) != 0x0)
2404 usermode = X86EMUL_MODE_PROT64;
2405 else
2406 usermode = X86EMUL_MODE_PROT32;
2407
2408 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2409 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2410
2411 cs.dpl = 3;
2412 ss.dpl = 3;
2413 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2414 switch (usermode) {
2415 case X86EMUL_MODE_PROT32:
2416 cs_sel = (u16)(msr_data + 16);
2417 if ((msr_data & 0xfffc) == 0x0)
2418 return emulate_gp(ctxt, 0);
2419 ss_sel = (u16)(msr_data + 24);
2420 break;
2421 case X86EMUL_MODE_PROT64:
2422 cs_sel = (u16)(msr_data + 32);
2423 if (msr_data == 0x0)
2424 return emulate_gp(ctxt, 0);
2425 ss_sel = cs_sel + 8;
2426 cs.d = 0;
2427 cs.l = 1;
2428 if (is_noncanonical_address(rcx) ||
2429 is_noncanonical_address(rdx))
2430 return emulate_gp(ctxt, 0);
2431 break;
2432 }
2433 cs_sel |= SELECTOR_RPL_MASK;
2434 ss_sel |= SELECTOR_RPL_MASK;
2435
2436 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2437 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2438
2439 ctxt->_eip = rdx;
2440 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2441
2442 return X86EMUL_CONTINUE;
2443 }
2444
2445 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2446 {
2447 int iopl;
2448 if (ctxt->mode == X86EMUL_MODE_REAL)
2449 return false;
2450 if (ctxt->mode == X86EMUL_MODE_VM86)
2451 return true;
2452 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2453 return ctxt->ops->cpl(ctxt) > iopl;
2454 }
2455
2456 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2457 u16 port, u16 len)
2458 {
2459 const struct x86_emulate_ops *ops = ctxt->ops;
2460 struct desc_struct tr_seg;
2461 u32 base3;
2462 int r;
2463 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2464 unsigned mask = (1 << len) - 1;
2465 unsigned long base;
2466
2467 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2468 if (!tr_seg.p)
2469 return false;
2470 if (desc_limit_scaled(&tr_seg) < 103)
2471 return false;
2472 base = get_desc_base(&tr_seg);
2473 #ifdef CONFIG_X86_64
2474 base |= ((u64)base3) << 32;
2475 #endif
2476 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2477 if (r != X86EMUL_CONTINUE)
2478 return false;
2479 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2480 return false;
2481 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2482 if (r != X86EMUL_CONTINUE)
2483 return false;
2484 if ((perm >> bit_idx) & mask)
2485 return false;
2486 return true;
2487 }
2488
2489 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2490 u16 port, u16 len)
2491 {
2492 if (ctxt->perm_ok)
2493 return true;
2494
2495 if (emulator_bad_iopl(ctxt))
2496 if (!emulator_io_port_access_allowed(ctxt, port, len))
2497 return false;
2498
2499 ctxt->perm_ok = true;
2500
2501 return true;
2502 }
2503
2504 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2505 struct tss_segment_16 *tss)
2506 {
2507 tss->ip = ctxt->_eip;
2508 tss->flag = ctxt->eflags;
2509 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2510 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2511 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2512 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2513 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2514 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2515 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2516 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2517
2518 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2519 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2520 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2521 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2522 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2523 }
2524
2525 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2526 struct tss_segment_16 *tss)
2527 {
2528 int ret;
2529 u8 cpl;
2530
2531 ctxt->_eip = tss->ip;
2532 ctxt->eflags = tss->flag | 2;
2533 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2534 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2535 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2536 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2537 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2538 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2539 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2540 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2541
2542 /*
2543 * SDM says that segment selectors are loaded before segment
2544 * descriptors
2545 */
2546 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2547 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2548 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2549 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2550 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2551
2552 cpl = tss->cs & 3;
2553
2554 /*
2555 * Now load segment descriptors. If fault happens at this stage
2556 * it is handled in a context of new task
2557 */
2558 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2559 true, NULL);
2560 if (ret != X86EMUL_CONTINUE)
2561 return ret;
2562 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2563 true, NULL);
2564 if (ret != X86EMUL_CONTINUE)
2565 return ret;
2566 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2567 true, NULL);
2568 if (ret != X86EMUL_CONTINUE)
2569 return ret;
2570 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2571 true, NULL);
2572 if (ret != X86EMUL_CONTINUE)
2573 return ret;
2574 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2575 true, NULL);
2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
2578
2579 return X86EMUL_CONTINUE;
2580 }
2581
2582 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2583 u16 tss_selector, u16 old_tss_sel,
2584 ulong old_tss_base, struct desc_struct *new_desc)
2585 {
2586 const struct x86_emulate_ops *ops = ctxt->ops;
2587 struct tss_segment_16 tss_seg;
2588 int ret;
2589 u32 new_tss_base = get_desc_base(new_desc);
2590
2591 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2592 &ctxt->exception);
2593 if (ret != X86EMUL_CONTINUE)
2594 /* FIXME: need to provide precise fault address */
2595 return ret;
2596
2597 save_state_to_tss16(ctxt, &tss_seg);
2598
2599 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2600 &ctxt->exception);
2601 if (ret != X86EMUL_CONTINUE)
2602 /* FIXME: need to provide precise fault address */
2603 return ret;
2604
2605 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2606 &ctxt->exception);
2607 if (ret != X86EMUL_CONTINUE)
2608 /* FIXME: need to provide precise fault address */
2609 return ret;
2610
2611 if (old_tss_sel != 0xffff) {
2612 tss_seg.prev_task_link = old_tss_sel;
2613
2614 ret = ops->write_std(ctxt, new_tss_base,
2615 &tss_seg.prev_task_link,
2616 sizeof tss_seg.prev_task_link,
2617 &ctxt->exception);
2618 if (ret != X86EMUL_CONTINUE)
2619 /* FIXME: need to provide precise fault address */
2620 return ret;
2621 }
2622
2623 return load_state_from_tss16(ctxt, &tss_seg);
2624 }
2625
2626 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2627 struct tss_segment_32 *tss)
2628 {
2629 /* CR3 and ldt selector are not saved intentionally */
2630 tss->eip = ctxt->_eip;
2631 tss->eflags = ctxt->eflags;
2632 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2633 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2634 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2635 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2636 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2637 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2638 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2639 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2640
2641 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2642 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2643 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2644 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2645 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2646 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2647 }
2648
2649 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2650 struct tss_segment_32 *tss)
2651 {
2652 int ret;
2653 u8 cpl;
2654
2655 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2656 return emulate_gp(ctxt, 0);
2657 ctxt->_eip = tss->eip;
2658 ctxt->eflags = tss->eflags | 2;
2659
2660 /* General purpose registers */
2661 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2662 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2663 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2664 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2665 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2666 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2667 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2668 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2669
2670 /*
2671 * SDM says that segment selectors are loaded before segment
2672 * descriptors. This is important because CPL checks will
2673 * use CS.RPL.
2674 */
2675 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2676 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2677 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2678 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2679 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2680 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2681 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2682
2683 /*
2684 * If we're switching between Protected Mode and VM86, we need to make
2685 * sure to update the mode before loading the segment descriptors so
2686 * that the selectors are interpreted correctly.
2687 */
2688 if (ctxt->eflags & X86_EFLAGS_VM) {
2689 ctxt->mode = X86EMUL_MODE_VM86;
2690 cpl = 3;
2691 } else {
2692 ctxt->mode = X86EMUL_MODE_PROT32;
2693 cpl = tss->cs & 3;
2694 }
2695
2696 /*
2697 * Now load segment descriptors. If fault happenes at this stage
2698 * it is handled in a context of new task
2699 */
2700 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2701 cpl, true, NULL);
2702 if (ret != X86EMUL_CONTINUE)
2703 return ret;
2704 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2705 true, NULL);
2706 if (ret != X86EMUL_CONTINUE)
2707 return ret;
2708 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2709 true, NULL);
2710 if (ret != X86EMUL_CONTINUE)
2711 return ret;
2712 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2713 true, NULL);
2714 if (ret != X86EMUL_CONTINUE)
2715 return ret;
2716 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2717 true, NULL);
2718 if (ret != X86EMUL_CONTINUE)
2719 return ret;
2720 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2721 true, NULL);
2722 if (ret != X86EMUL_CONTINUE)
2723 return ret;
2724 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2725 true, NULL);
2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
2728
2729 return X86EMUL_CONTINUE;
2730 }
2731
2732 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2733 u16 tss_selector, u16 old_tss_sel,
2734 ulong old_tss_base, struct desc_struct *new_desc)
2735 {
2736 const struct x86_emulate_ops *ops = ctxt->ops;
2737 struct tss_segment_32 tss_seg;
2738 int ret;
2739 u32 new_tss_base = get_desc_base(new_desc);
2740 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2741 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2742
2743 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2744 &ctxt->exception);
2745 if (ret != X86EMUL_CONTINUE)
2746 /* FIXME: need to provide precise fault address */
2747 return ret;
2748
2749 save_state_to_tss32(ctxt, &tss_seg);
2750
2751 /* Only GP registers and segment selectors are saved */
2752 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2753 ldt_sel_offset - eip_offset, &ctxt->exception);
2754 if (ret != X86EMUL_CONTINUE)
2755 /* FIXME: need to provide precise fault address */
2756 return ret;
2757
2758 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2759 &ctxt->exception);
2760 if (ret != X86EMUL_CONTINUE)
2761 /* FIXME: need to provide precise fault address */
2762 return ret;
2763
2764 if (old_tss_sel != 0xffff) {
2765 tss_seg.prev_task_link = old_tss_sel;
2766
2767 ret = ops->write_std(ctxt, new_tss_base,
2768 &tss_seg.prev_task_link,
2769 sizeof tss_seg.prev_task_link,
2770 &ctxt->exception);
2771 if (ret != X86EMUL_CONTINUE)
2772 /* FIXME: need to provide precise fault address */
2773 return ret;
2774 }
2775
2776 return load_state_from_tss32(ctxt, &tss_seg);
2777 }
2778
2779 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2780 u16 tss_selector, int idt_index, int reason,
2781 bool has_error_code, u32 error_code)
2782 {
2783 const struct x86_emulate_ops *ops = ctxt->ops;
2784 struct desc_struct curr_tss_desc, next_tss_desc;
2785 int ret;
2786 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2787 ulong old_tss_base =
2788 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2789 u32 desc_limit;
2790 ulong desc_addr;
2791
2792 /* FIXME: old_tss_base == ~0 ? */
2793
2794 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2795 if (ret != X86EMUL_CONTINUE)
2796 return ret;
2797 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2798 if (ret != X86EMUL_CONTINUE)
2799 return ret;
2800
2801 /* FIXME: check that next_tss_desc is tss */
2802
2803 /*
2804 * Check privileges. The three cases are task switch caused by...
2805 *
2806 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2807 * 2. Exception/IRQ/iret: No check is performed
2808 * 3. jmp/call to TSS: Check against DPL of the TSS
2809 */
2810 if (reason == TASK_SWITCH_GATE) {
2811 if (idt_index != -1) {
2812 /* Software interrupts */
2813 struct desc_struct task_gate_desc;
2814 int dpl;
2815
2816 ret = read_interrupt_descriptor(ctxt, idt_index,
2817 &task_gate_desc);
2818 if (ret != X86EMUL_CONTINUE)
2819 return ret;
2820
2821 dpl = task_gate_desc.dpl;
2822 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2823 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2824 }
2825 } else if (reason != TASK_SWITCH_IRET) {
2826 int dpl = next_tss_desc.dpl;
2827 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2828 return emulate_gp(ctxt, tss_selector);
2829 }
2830
2831
2832 desc_limit = desc_limit_scaled(&next_tss_desc);
2833 if (!next_tss_desc.p ||
2834 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2835 desc_limit < 0x2b)) {
2836 return emulate_ts(ctxt, tss_selector & 0xfffc);
2837 }
2838
2839 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2840 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2841 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2842 }
2843
2844 if (reason == TASK_SWITCH_IRET)
2845 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2846
2847 /* set back link to prev task only if NT bit is set in eflags
2848 note that old_tss_sel is not used after this point */
2849 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2850 old_tss_sel = 0xffff;
2851
2852 if (next_tss_desc.type & 8)
2853 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2854 old_tss_base, &next_tss_desc);
2855 else
2856 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2857 old_tss_base, &next_tss_desc);
2858 if (ret != X86EMUL_CONTINUE)
2859 return ret;
2860
2861 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2862 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2863
2864 if (reason != TASK_SWITCH_IRET) {
2865 next_tss_desc.type |= (1 << 1); /* set busy flag */
2866 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2867 }
2868
2869 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2870 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2871
2872 if (has_error_code) {
2873 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2874 ctxt->lock_prefix = 0;
2875 ctxt->src.val = (unsigned long) error_code;
2876 ret = em_push(ctxt);
2877 }
2878
2879 return ret;
2880 }
2881
2882 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2883 u16 tss_selector, int idt_index, int reason,
2884 bool has_error_code, u32 error_code)
2885 {
2886 int rc;
2887
2888 invalidate_registers(ctxt);
2889 ctxt->_eip = ctxt->eip;
2890 ctxt->dst.type = OP_NONE;
2891
2892 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2893 has_error_code, error_code);
2894
2895 if (rc == X86EMUL_CONTINUE) {
2896 ctxt->eip = ctxt->_eip;
2897 writeback_registers(ctxt);
2898 }
2899
2900 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2901 }
2902
2903 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2904 struct operand *op)
2905 {
2906 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2907
2908 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2909 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2910 }
2911
2912 static int em_das(struct x86_emulate_ctxt *ctxt)
2913 {
2914 u8 al, old_al;
2915 bool af, cf, old_cf;
2916
2917 cf = ctxt->eflags & X86_EFLAGS_CF;
2918 al = ctxt->dst.val;
2919
2920 old_al = al;
2921 old_cf = cf;
2922 cf = false;
2923 af = ctxt->eflags & X86_EFLAGS_AF;
2924 if ((al & 0x0f) > 9 || af) {
2925 al -= 6;
2926 cf = old_cf | (al >= 250);
2927 af = true;
2928 } else {
2929 af = false;
2930 }
2931 if (old_al > 0x99 || old_cf) {
2932 al -= 0x60;
2933 cf = true;
2934 }
2935
2936 ctxt->dst.val = al;
2937 /* Set PF, ZF, SF */
2938 ctxt->src.type = OP_IMM;
2939 ctxt->src.val = 0;
2940 ctxt->src.bytes = 1;
2941 fastop(ctxt, em_or);
2942 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2943 if (cf)
2944 ctxt->eflags |= X86_EFLAGS_CF;
2945 if (af)
2946 ctxt->eflags |= X86_EFLAGS_AF;
2947 return X86EMUL_CONTINUE;
2948 }
2949
2950 static int em_aam(struct x86_emulate_ctxt *ctxt)
2951 {
2952 u8 al, ah;
2953
2954 if (ctxt->src.val == 0)
2955 return emulate_de(ctxt);
2956
2957 al = ctxt->dst.val & 0xff;
2958 ah = al / ctxt->src.val;
2959 al %= ctxt->src.val;
2960
2961 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2962
2963 /* Set PF, ZF, SF */
2964 ctxt->src.type = OP_IMM;
2965 ctxt->src.val = 0;
2966 ctxt->src.bytes = 1;
2967 fastop(ctxt, em_or);
2968
2969 return X86EMUL_CONTINUE;
2970 }
2971
2972 static int em_aad(struct x86_emulate_ctxt *ctxt)
2973 {
2974 u8 al = ctxt->dst.val & 0xff;
2975 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2976
2977 al = (al + (ah * ctxt->src.val)) & 0xff;
2978
2979 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2980
2981 /* Set PF, ZF, SF */
2982 ctxt->src.type = OP_IMM;
2983 ctxt->src.val = 0;
2984 ctxt->src.bytes = 1;
2985 fastop(ctxt, em_or);
2986
2987 return X86EMUL_CONTINUE;
2988 }
2989
2990 static int em_call(struct x86_emulate_ctxt *ctxt)
2991 {
2992 int rc;
2993 long rel = ctxt->src.val;
2994
2995 ctxt->src.val = (unsigned long)ctxt->_eip;
2996 rc = jmp_rel(ctxt, rel);
2997 if (rc != X86EMUL_CONTINUE)
2998 return rc;
2999 return em_push(ctxt);
3000 }
3001
3002 static int em_call_far(struct x86_emulate_ctxt *ctxt)
3003 {
3004 u16 sel, old_cs;
3005 ulong old_eip;
3006 int rc;
3007 struct desc_struct old_desc, new_desc;
3008 const struct x86_emulate_ops *ops = ctxt->ops;
3009 int cpl = ctxt->ops->cpl(ctxt);
3010
3011 old_eip = ctxt->_eip;
3012 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3013
3014 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3015 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3016 &new_desc);
3017 if (rc != X86EMUL_CONTINUE)
3018 return X86EMUL_CONTINUE;
3019
3020 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
3021 if (rc != X86EMUL_CONTINUE)
3022 goto fail;
3023
3024 ctxt->src.val = old_cs;
3025 rc = em_push(ctxt);
3026 if (rc != X86EMUL_CONTINUE)
3027 goto fail;
3028
3029 ctxt->src.val = old_eip;
3030 rc = em_push(ctxt);
3031 /* If we failed, we tainted the memory, but the very least we should
3032 restore cs */
3033 if (rc != X86EMUL_CONTINUE)
3034 goto fail;
3035 return rc;
3036 fail:
3037 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3038 return rc;
3039
3040 }
3041
3042 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3043 {
3044 int rc;
3045 unsigned long eip;
3046
3047 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3048 if (rc != X86EMUL_CONTINUE)
3049 return rc;
3050 rc = assign_eip_near(ctxt, eip);
3051 if (rc != X86EMUL_CONTINUE)
3052 return rc;
3053 rsp_increment(ctxt, ctxt->src.val);
3054 return X86EMUL_CONTINUE;
3055 }
3056
3057 static int em_xchg(struct x86_emulate_ctxt *ctxt)
3058 {
3059 /* Write back the register source. */
3060 ctxt->src.val = ctxt->dst.val;
3061 write_register_operand(&ctxt->src);
3062
3063 /* Write back the memory destination with implicit LOCK prefix. */
3064 ctxt->dst.val = ctxt->src.orig_val;
3065 ctxt->lock_prefix = 1;
3066 return X86EMUL_CONTINUE;
3067 }
3068
3069 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3070 {
3071 ctxt->dst.val = ctxt->src2.val;
3072 return fastop(ctxt, em_imul);
3073 }
3074
3075 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3076 {
3077 ctxt->dst.type = OP_REG;
3078 ctxt->dst.bytes = ctxt->src.bytes;
3079 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3080 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3081
3082 return X86EMUL_CONTINUE;
3083 }
3084
3085 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3086 {
3087 u64 tsc = 0;
3088
3089 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3090 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3091 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3092 return X86EMUL_CONTINUE;
3093 }
3094
3095 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3096 {
3097 u64 pmc;
3098
3099 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3100 return emulate_gp(ctxt, 0);
3101 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3102 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3103 return X86EMUL_CONTINUE;
3104 }
3105
3106 static int em_mov(struct x86_emulate_ctxt *ctxt)
3107 {
3108 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3109 return X86EMUL_CONTINUE;
3110 }
3111
3112 #define FFL(x) bit(X86_FEATURE_##x)
3113
3114 static int em_movbe(struct x86_emulate_ctxt *ctxt)
3115 {
3116 u32 ebx, ecx, edx, eax = 1;
3117 u16 tmp;
3118
3119 /*
3120 * Check MOVBE is set in the guest-visible CPUID leaf.
3121 */
3122 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3123 if (!(ecx & FFL(MOVBE)))
3124 return emulate_ud(ctxt);
3125
3126 switch (ctxt->op_bytes) {
3127 case 2:
3128 /*
3129 * From MOVBE definition: "...When the operand size is 16 bits,
3130 * the upper word of the destination register remains unchanged
3131 * ..."
3132 *
3133 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3134 * rules so we have to do the operation almost per hand.
3135 */
3136 tmp = (u16)ctxt->src.val;
3137 ctxt->dst.val &= ~0xffffUL;
3138 ctxt->dst.val |= (unsigned long)swab16(tmp);
3139 break;
3140 case 4:
3141 ctxt->dst.val = swab32((u32)ctxt->src.val);
3142 break;
3143 case 8:
3144 ctxt->dst.val = swab64(ctxt->src.val);
3145 break;
3146 default:
3147 BUG();
3148 }
3149 return X86EMUL_CONTINUE;
3150 }
3151
3152 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3153 {
3154 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3155 return emulate_gp(ctxt, 0);
3156
3157 /* Disable writeback. */
3158 ctxt->dst.type = OP_NONE;
3159 return X86EMUL_CONTINUE;
3160 }
3161
3162 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3163 {
3164 unsigned long val;
3165
3166 if (ctxt->mode == X86EMUL_MODE_PROT64)
3167 val = ctxt->src.val & ~0ULL;
3168 else
3169 val = ctxt->src.val & ~0U;
3170
3171 /* #UD condition is already handled. */
3172 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3173 return emulate_gp(ctxt, 0);
3174
3175 /* Disable writeback. */
3176 ctxt->dst.type = OP_NONE;
3177 return X86EMUL_CONTINUE;
3178 }
3179
3180 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3181 {
3182 u64 msr_data;
3183
3184 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3185 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3186 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3187 return emulate_gp(ctxt, 0);
3188
3189 return X86EMUL_CONTINUE;
3190 }
3191
3192 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3193 {
3194 u64 msr_data;
3195
3196 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3197 return emulate_gp(ctxt, 0);
3198
3199 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3200 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3201 return X86EMUL_CONTINUE;
3202 }
3203
3204 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3205 {
3206 if (ctxt->modrm_reg > VCPU_SREG_GS)
3207 return emulate_ud(ctxt);
3208
3209 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3210 return X86EMUL_CONTINUE;
3211 }
3212
3213 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3214 {
3215 u16 sel = ctxt->src.val;
3216
3217 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3218 return emulate_ud(ctxt);
3219
3220 if (ctxt->modrm_reg == VCPU_SREG_SS)
3221 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3222
3223 /* Disable writeback. */
3224 ctxt->dst.type = OP_NONE;
3225 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3226 }
3227
3228 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3229 {
3230 u16 sel = ctxt->src.val;
3231
3232 /* Disable writeback. */
3233 ctxt->dst.type = OP_NONE;
3234 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3235 }
3236
3237 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3238 {
3239 u16 sel = ctxt->src.val;
3240
3241 /* Disable writeback. */
3242 ctxt->dst.type = OP_NONE;
3243 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3244 }
3245
3246 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3247 {
3248 int rc;
3249 ulong linear;
3250
3251 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3252 if (rc == X86EMUL_CONTINUE)
3253 ctxt->ops->invlpg(ctxt, linear);
3254 /* Disable writeback. */
3255 ctxt->dst.type = OP_NONE;
3256 return X86EMUL_CONTINUE;
3257 }
3258
3259 static int em_clts(struct x86_emulate_ctxt *ctxt)
3260 {
3261 ulong cr0;
3262
3263 cr0 = ctxt->ops->get_cr(ctxt, 0);
3264 cr0 &= ~X86_CR0_TS;
3265 ctxt->ops->set_cr(ctxt, 0, cr0);
3266 return X86EMUL_CONTINUE;
3267 }
3268
3269 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3270 {
3271 int rc = ctxt->ops->fix_hypercall(ctxt);
3272
3273 if (rc != X86EMUL_CONTINUE)
3274 return rc;
3275
3276 /* Let the processor re-execute the fixed hypercall */
3277 ctxt->_eip = ctxt->eip;
3278 /* Disable writeback. */
3279 ctxt->dst.type = OP_NONE;
3280 return X86EMUL_CONTINUE;
3281 }
3282
3283 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3284 void (*get)(struct x86_emulate_ctxt *ctxt,
3285 struct desc_ptr *ptr))
3286 {
3287 struct desc_ptr desc_ptr;
3288
3289 if (ctxt->mode == X86EMUL_MODE_PROT64)
3290 ctxt->op_bytes = 8;
3291 get(ctxt, &desc_ptr);
3292 if (ctxt->op_bytes == 2) {
3293 ctxt->op_bytes = 4;
3294 desc_ptr.address &= 0x00ffffff;
3295 }
3296 /* Disable writeback. */
3297 ctxt->dst.type = OP_NONE;
3298 return segmented_write(ctxt, ctxt->dst.addr.mem,
3299 &desc_ptr, 2 + ctxt->op_bytes);
3300 }
3301
3302 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3303 {
3304 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3305 }
3306
3307 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3308 {
3309 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3310 }
3311
3312 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3313 {
3314 struct desc_ptr desc_ptr;
3315 int rc;
3316
3317 if (ctxt->mode == X86EMUL_MODE_PROT64)
3318 ctxt->op_bytes = 8;
3319 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3320 &desc_ptr.size, &desc_ptr.address,
3321 ctxt->op_bytes);
3322 if (rc != X86EMUL_CONTINUE)
3323 return rc;
3324 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3325 /* Disable writeback. */
3326 ctxt->dst.type = OP_NONE;
3327 return X86EMUL_CONTINUE;
3328 }
3329
3330 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3331 {
3332 int rc;
3333
3334 rc = ctxt->ops->fix_hypercall(ctxt);
3335
3336 /* Disable writeback. */
3337 ctxt->dst.type = OP_NONE;
3338 return rc;
3339 }
3340
3341 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3342 {
3343 struct desc_ptr desc_ptr;
3344 int rc;
3345
3346 if (ctxt->mode == X86EMUL_MODE_PROT64)
3347 ctxt->op_bytes = 8;
3348 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3349 &desc_ptr.size, &desc_ptr.address,
3350 ctxt->op_bytes);
3351 if (rc != X86EMUL_CONTINUE)
3352 return rc;
3353 ctxt->ops->set_idt(ctxt, &desc_ptr);
3354 /* Disable writeback. */
3355 ctxt->dst.type = OP_NONE;
3356 return X86EMUL_CONTINUE;
3357 }
3358
3359 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3360 {
3361 if (ctxt->dst.type == OP_MEM)
3362 ctxt->dst.bytes = 2;
3363 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3364 return X86EMUL_CONTINUE;
3365 }
3366
3367 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3368 {
3369 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3370 | (ctxt->src.val & 0x0f));
3371 ctxt->dst.type = OP_NONE;
3372 return X86EMUL_CONTINUE;
3373 }
3374
3375 static int em_loop(struct x86_emulate_ctxt *ctxt)
3376 {
3377 int rc = X86EMUL_CONTINUE;
3378
3379 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3380 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3381 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3382 rc = jmp_rel(ctxt, ctxt->src.val);
3383
3384 return rc;
3385 }
3386
3387 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3388 {
3389 int rc = X86EMUL_CONTINUE;
3390
3391 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3392 rc = jmp_rel(ctxt, ctxt->src.val);
3393
3394 return rc;
3395 }
3396
3397 static int em_in(struct x86_emulate_ctxt *ctxt)
3398 {
3399 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3400 &ctxt->dst.val))
3401 return X86EMUL_IO_NEEDED;
3402
3403 return X86EMUL_CONTINUE;
3404 }
3405
3406 static int em_out(struct x86_emulate_ctxt *ctxt)
3407 {
3408 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3409 &ctxt->src.val, 1);
3410 /* Disable writeback. */
3411 ctxt->dst.type = OP_NONE;
3412 return X86EMUL_CONTINUE;
3413 }
3414
3415 static int em_cli(struct x86_emulate_ctxt *ctxt)
3416 {
3417 if (emulator_bad_iopl(ctxt))
3418 return emulate_gp(ctxt, 0);
3419
3420 ctxt->eflags &= ~X86_EFLAGS_IF;
3421 return X86EMUL_CONTINUE;
3422 }
3423
3424 static int em_sti(struct x86_emulate_ctxt *ctxt)
3425 {
3426 if (emulator_bad_iopl(ctxt))
3427 return emulate_gp(ctxt, 0);
3428
3429 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3430 ctxt->eflags |= X86_EFLAGS_IF;
3431 return X86EMUL_CONTINUE;
3432 }
3433
3434 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3435 {
3436 u32 eax, ebx, ecx, edx;
3437
3438 eax = reg_read(ctxt, VCPU_REGS_RAX);
3439 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3440 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3441 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3442 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3443 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3444 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3445 return X86EMUL_CONTINUE;
3446 }
3447
3448 static int em_sahf(struct x86_emulate_ctxt *ctxt)
3449 {
3450 u32 flags;
3451
3452 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3453 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3454
3455 ctxt->eflags &= ~0xffUL;
3456 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3457 return X86EMUL_CONTINUE;
3458 }
3459
3460 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3461 {
3462 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3463 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3464 return X86EMUL_CONTINUE;
3465 }
3466
3467 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3468 {
3469 switch (ctxt->op_bytes) {
3470 #ifdef CONFIG_X86_64
3471 case 8:
3472 asm("bswap %0" : "+r"(ctxt->dst.val));
3473 break;
3474 #endif
3475 default:
3476 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3477 break;
3478 }
3479 return X86EMUL_CONTINUE;
3480 }
3481
3482 static int em_clflush(struct x86_emulate_ctxt *ctxt)
3483 {
3484 /* emulating clflush regardless of cpuid */
3485 return X86EMUL_CONTINUE;
3486 }
3487
3488 static bool valid_cr(int nr)
3489 {
3490 switch (nr) {
3491 case 0:
3492 case 2 ... 4:
3493 case 8:
3494 return true;
3495 default:
3496 return false;
3497 }
3498 }
3499
3500 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3501 {
3502 if (!valid_cr(ctxt->modrm_reg))
3503 return emulate_ud(ctxt);
3504
3505 return X86EMUL_CONTINUE;
3506 }
3507
3508 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3509 {
3510 u64 new_val = ctxt->src.val64;
3511 int cr = ctxt->modrm_reg;
3512 u64 efer = 0;
3513
3514 static u64 cr_reserved_bits[] = {
3515 0xffffffff00000000ULL,
3516 0, 0, 0, /* CR3 checked later */
3517 CR4_RESERVED_BITS,
3518 0, 0, 0,
3519 CR8_RESERVED_BITS,
3520 };
3521
3522 if (!valid_cr(cr))
3523 return emulate_ud(ctxt);
3524
3525 if (new_val & cr_reserved_bits[cr])
3526 return emulate_gp(ctxt, 0);
3527
3528 switch (cr) {
3529 case 0: {
3530 u64 cr4;
3531 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3532 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3533 return emulate_gp(ctxt, 0);
3534
3535 cr4 = ctxt->ops->get_cr(ctxt, 4);
3536 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3537
3538 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3539 !(cr4 & X86_CR4_PAE))
3540 return emulate_gp(ctxt, 0);
3541
3542 break;
3543 }
3544 case 3: {
3545 u64 rsvd = 0;
3546
3547 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3548 if (efer & EFER_LMA)
3549 rsvd = CR3_L_MODE_RESERVED_BITS;
3550
3551 if (new_val & rsvd)
3552 return emulate_gp(ctxt, 0);
3553
3554 break;
3555 }
3556 case 4: {
3557 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3558
3559 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3560 return emulate_gp(ctxt, 0);
3561
3562 break;
3563 }
3564 }
3565
3566 return X86EMUL_CONTINUE;
3567 }
3568
3569 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3570 {
3571 unsigned long dr7;
3572
3573 ctxt->ops->get_dr(ctxt, 7, &dr7);
3574
3575 /* Check if DR7.Global_Enable is set */
3576 return dr7 & (1 << 13);
3577 }
3578
3579 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3580 {
3581 int dr = ctxt->modrm_reg;
3582 u64 cr4;
3583
3584 if (dr > 7)
3585 return emulate_ud(ctxt);
3586
3587 cr4 = ctxt->ops->get_cr(ctxt, 4);
3588 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3589 return emulate_ud(ctxt);
3590
3591 if (check_dr7_gd(ctxt))
3592 return emulate_db(ctxt);
3593
3594 return X86EMUL_CONTINUE;
3595 }
3596
3597 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3598 {
3599 u64 new_val = ctxt->src.val64;
3600 int dr = ctxt->modrm_reg;
3601
3602 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3603 return emulate_gp(ctxt, 0);
3604
3605 return check_dr_read(ctxt);
3606 }
3607
3608 static int check_svme(struct x86_emulate_ctxt *ctxt)
3609 {
3610 u64 efer;
3611
3612 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3613
3614 if (!(efer & EFER_SVME))
3615 return emulate_ud(ctxt);
3616
3617 return X86EMUL_CONTINUE;
3618 }
3619
3620 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3621 {
3622 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3623
3624 /* Valid physical address? */
3625 if (rax & 0xffff000000000000ULL)
3626 return emulate_gp(ctxt, 0);
3627
3628 return check_svme(ctxt);
3629 }
3630
3631 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3632 {
3633 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3634
3635 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3636 return emulate_ud(ctxt);
3637
3638 return X86EMUL_CONTINUE;
3639 }
3640
3641 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3642 {
3643 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3644 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3645
3646 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3647 ctxt->ops->check_pmc(ctxt, rcx))
3648 return emulate_gp(ctxt, 0);
3649
3650 return X86EMUL_CONTINUE;
3651 }
3652
3653 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3654 {
3655 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3656 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3657 return emulate_gp(ctxt, 0);
3658
3659 return X86EMUL_CONTINUE;
3660 }
3661
3662 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3663 {
3664 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3665 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3666 return emulate_gp(ctxt, 0);
3667
3668 return X86EMUL_CONTINUE;
3669 }
3670
3671 #define D(_y) { .flags = (_y) }
3672 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3673 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3674 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3675 #define N D(NotImpl)
3676 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3677 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3678 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3679 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3680 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3681 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3682 #define II(_f, _e, _i) \
3683 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3684 #define IIP(_f, _e, _i, _p) \
3685 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3686 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3687 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3688
3689 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3690 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3691 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3692 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3693 #define I2bvIP(_f, _e, _i, _p) \
3694 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3695
3696 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3697 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3698 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3699
3700 static const struct opcode group7_rm0[] = {
3701 N,
3702 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3703 N, N, N, N, N, N,
3704 };
3705
3706 static const struct opcode group7_rm1[] = {
3707 DI(SrcNone | Priv, monitor),
3708 DI(SrcNone | Priv, mwait),
3709 N, N, N, N, N, N,
3710 };
3711
3712 static const struct opcode group7_rm3[] = {
3713 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3714 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
3715 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3716 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3717 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3718 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3719 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3720 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3721 };
3722
3723 static const struct opcode group7_rm7[] = {
3724 N,
3725 DIP(SrcNone, rdtscp, check_rdtsc),
3726 N, N, N, N, N, N,
3727 };
3728
3729 static const struct opcode group1[] = {
3730 F(Lock, em_add),
3731 F(Lock | PageTable, em_or),
3732 F(Lock, em_adc),
3733 F(Lock, em_sbb),
3734 F(Lock | PageTable, em_and),
3735 F(Lock, em_sub),
3736 F(Lock, em_xor),
3737 F(NoWrite, em_cmp),
3738 };
3739
3740 static const struct opcode group1A[] = {
3741 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3742 };
3743
3744 static const struct opcode group2[] = {
3745 F(DstMem | ModRM, em_rol),
3746 F(DstMem | ModRM, em_ror),
3747 F(DstMem | ModRM, em_rcl),
3748 F(DstMem | ModRM, em_rcr),
3749 F(DstMem | ModRM, em_shl),
3750 F(DstMem | ModRM, em_shr),
3751 F(DstMem | ModRM, em_shl),
3752 F(DstMem | ModRM, em_sar),
3753 };
3754
3755 static const struct opcode group3[] = {
3756 F(DstMem | SrcImm | NoWrite, em_test),
3757 F(DstMem | SrcImm | NoWrite, em_test),
3758 F(DstMem | SrcNone | Lock, em_not),
3759 F(DstMem | SrcNone | Lock, em_neg),
3760 F(DstXacc | Src2Mem, em_mul_ex),
3761 F(DstXacc | Src2Mem, em_imul_ex),
3762 F(DstXacc | Src2Mem, em_div_ex),
3763 F(DstXacc | Src2Mem, em_idiv_ex),
3764 };
3765
3766 static const struct opcode group4[] = {
3767 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3768 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3769 N, N, N, N, N, N,
3770 };
3771
3772 static const struct opcode group5[] = {
3773 F(DstMem | SrcNone | Lock, em_inc),
3774 F(DstMem | SrcNone | Lock, em_dec),
3775 I(SrcMem | NearBranch, em_call_near_abs),
3776 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3777 I(SrcMem | NearBranch, em_jmp_abs),
3778 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3779 I(SrcMem | Stack, em_push), D(Undefined),
3780 };
3781
3782 static const struct opcode group6[] = {
3783 DI(Prot, sldt),
3784 DI(Prot, str),
3785 II(Prot | Priv | SrcMem16, em_lldt, lldt),
3786 II(Prot | Priv | SrcMem16, em_ltr, ltr),
3787 N, N, N, N,
3788 };
3789
3790 static const struct group_dual group7 = { {
3791 II(Mov | DstMem, em_sgdt, sgdt),
3792 II(Mov | DstMem, em_sidt, sidt),
3793 II(SrcMem | Priv, em_lgdt, lgdt),
3794 II(SrcMem | Priv, em_lidt, lidt),
3795 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3796 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3797 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3798 }, {
3799 EXT(0, group7_rm0),
3800 EXT(0, group7_rm1),
3801 N, EXT(0, group7_rm3),
3802 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3803 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3804 EXT(0, group7_rm7),
3805 } };
3806
3807 static const struct opcode group8[] = {
3808 N, N, N, N,
3809 F(DstMem | SrcImmByte | NoWrite, em_bt),
3810 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3811 F(DstMem | SrcImmByte | Lock, em_btr),
3812 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3813 };
3814
3815 static const struct group_dual group9 = { {
3816 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3817 }, {
3818 N, N, N, N, N, N, N, N,
3819 } };
3820
3821 static const struct opcode group11[] = {
3822 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3823 X7(D(Undefined)),
3824 };
3825
3826 static const struct gprefix pfx_0f_ae_7 = {
3827 I(SrcMem | ByteOp, em_clflush), N, N, N,
3828 };
3829
3830 static const struct group_dual group15 = { {
3831 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3832 }, {
3833 N, N, N, N, N, N, N, N,
3834 } };
3835
3836 static const struct gprefix pfx_0f_6f_0f_7f = {
3837 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3838 };
3839
3840 static const struct gprefix pfx_0f_2b = {
3841 I(0, em_mov), I(0, em_mov), N, N,
3842 };
3843
3844 static const struct gprefix pfx_0f_28_0f_29 = {
3845 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
3846 };
3847
3848 static const struct gprefix pfx_0f_e7 = {
3849 N, I(Sse, em_mov), N, N,
3850 };
3851
3852 static const struct escape escape_d9 = { {
3853 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3854 }, {
3855 /* 0xC0 - 0xC7 */
3856 N, N, N, N, N, N, N, N,
3857 /* 0xC8 - 0xCF */
3858 N, N, N, N, N, N, N, N,
3859 /* 0xD0 - 0xC7 */
3860 N, N, N, N, N, N, N, N,
3861 /* 0xD8 - 0xDF */
3862 N, N, N, N, N, N, N, N,
3863 /* 0xE0 - 0xE7 */
3864 N, N, N, N, N, N, N, N,
3865 /* 0xE8 - 0xEF */
3866 N, N, N, N, N, N, N, N,
3867 /* 0xF0 - 0xF7 */
3868 N, N, N, N, N, N, N, N,
3869 /* 0xF8 - 0xFF */
3870 N, N, N, N, N, N, N, N,
3871 } };
3872
3873 static const struct escape escape_db = { {
3874 N, N, N, N, N, N, N, N,
3875 }, {
3876 /* 0xC0 - 0xC7 */
3877 N, N, N, N, N, N, N, N,
3878 /* 0xC8 - 0xCF */
3879 N, N, N, N, N, N, N, N,
3880 /* 0xD0 - 0xC7 */
3881 N, N, N, N, N, N, N, N,
3882 /* 0xD8 - 0xDF */
3883 N, N, N, N, N, N, N, N,
3884 /* 0xE0 - 0xE7 */
3885 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3886 /* 0xE8 - 0xEF */
3887 N, N, N, N, N, N, N, N,
3888 /* 0xF0 - 0xF7 */
3889 N, N, N, N, N, N, N, N,
3890 /* 0xF8 - 0xFF */
3891 N, N, N, N, N, N, N, N,
3892 } };
3893
3894 static const struct escape escape_dd = { {
3895 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3896 }, {
3897 /* 0xC0 - 0xC7 */
3898 N, N, N, N, N, N, N, N,
3899 /* 0xC8 - 0xCF */
3900 N, N, N, N, N, N, N, N,
3901 /* 0xD0 - 0xC7 */
3902 N, N, N, N, N, N, N, N,
3903 /* 0xD8 - 0xDF */
3904 N, N, N, N, N, N, N, N,
3905 /* 0xE0 - 0xE7 */
3906 N, N, N, N, N, N, N, N,
3907 /* 0xE8 - 0xEF */
3908 N, N, N, N, N, N, N, N,
3909 /* 0xF0 - 0xF7 */
3910 N, N, N, N, N, N, N, N,
3911 /* 0xF8 - 0xFF */
3912 N, N, N, N, N, N, N, N,
3913 } };
3914
3915 static const struct opcode opcode_table[256] = {
3916 /* 0x00 - 0x07 */
3917 F6ALU(Lock, em_add),
3918 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3919 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3920 /* 0x08 - 0x0F */
3921 F6ALU(Lock | PageTable, em_or),
3922 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3923 N,
3924 /* 0x10 - 0x17 */
3925 F6ALU(Lock, em_adc),
3926 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3927 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3928 /* 0x18 - 0x1F */
3929 F6ALU(Lock, em_sbb),
3930 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3931 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3932 /* 0x20 - 0x27 */
3933 F6ALU(Lock | PageTable, em_and), N, N,
3934 /* 0x28 - 0x2F */
3935 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3936 /* 0x30 - 0x37 */
3937 F6ALU(Lock, em_xor), N, N,
3938 /* 0x38 - 0x3F */
3939 F6ALU(NoWrite, em_cmp), N, N,
3940 /* 0x40 - 0x4F */
3941 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3942 /* 0x50 - 0x57 */
3943 X8(I(SrcReg | Stack, em_push)),
3944 /* 0x58 - 0x5F */
3945 X8(I(DstReg | Stack, em_pop)),
3946 /* 0x60 - 0x67 */
3947 I(ImplicitOps | Stack | No64, em_pusha),
3948 I(ImplicitOps | Stack | No64, em_popa),
3949 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3950 N, N, N, N,
3951 /* 0x68 - 0x6F */
3952 I(SrcImm | Mov | Stack, em_push),
3953 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3954 I(SrcImmByte | Mov | Stack, em_push),
3955 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3956 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3957 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3958 /* 0x70 - 0x7F */
3959 X16(D(SrcImmByte | NearBranch)),
3960 /* 0x80 - 0x87 */
3961 G(ByteOp | DstMem | SrcImm, group1),
3962 G(DstMem | SrcImm, group1),
3963 G(ByteOp | DstMem | SrcImm | No64, group1),
3964 G(DstMem | SrcImmByte, group1),
3965 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3966 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3967 /* 0x88 - 0x8F */
3968 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3969 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3970 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3971 D(ModRM | SrcMem | NoAccess | DstReg),
3972 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3973 G(0, group1A),
3974 /* 0x90 - 0x97 */
3975 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3976 /* 0x98 - 0x9F */
3977 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3978 I(SrcImmFAddr | No64, em_call_far), N,
3979 II(ImplicitOps | Stack, em_pushf, pushf),
3980 II(ImplicitOps | Stack, em_popf, popf),
3981 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
3982 /* 0xA0 - 0xA7 */
3983 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3984 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3985 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3986 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3987 /* 0xA8 - 0xAF */
3988 F2bv(DstAcc | SrcImm | NoWrite, em_test),
3989 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3990 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3991 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3992 /* 0xB0 - 0xB7 */
3993 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3994 /* 0xB8 - 0xBF */
3995 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3996 /* 0xC0 - 0xC7 */
3997 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3998 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
3999 I(ImplicitOps | NearBranch, em_ret),
4000 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4001 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4002 G(ByteOp, group11), G(0, group11),
4003 /* 0xC8 - 0xCF */
4004 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4005 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4006 I(ImplicitOps | Stack, em_ret_far),
4007 D(ImplicitOps), DI(SrcImmByte, intn),
4008 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4009 /* 0xD0 - 0xD7 */
4010 G(Src2One | ByteOp, group2), G(Src2One, group2),
4011 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4012 I(DstAcc | SrcImmUByte | No64, em_aam),
4013 I(DstAcc | SrcImmUByte | No64, em_aad),
4014 F(DstAcc | ByteOp | No64, em_salc),
4015 I(DstAcc | SrcXLat | ByteOp, em_mov),
4016 /* 0xD8 - 0xDF */
4017 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4018 /* 0xE0 - 0xE7 */
4019 X3(I(SrcImmByte | NearBranch, em_loop)),
4020 I(SrcImmByte | NearBranch, em_jcxz),
4021 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4022 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4023 /* 0xE8 - 0xEF */
4024 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4025 I(SrcImmFAddr | No64, em_jmp_far),
4026 D(SrcImmByte | ImplicitOps | NearBranch),
4027 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4028 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4029 /* 0xF0 - 0xF7 */
4030 N, DI(ImplicitOps, icebp), N, N,
4031 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4032 G(ByteOp, group3), G(0, group3),
4033 /* 0xF8 - 0xFF */
4034 D(ImplicitOps), D(ImplicitOps),
4035 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4036 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4037 };
4038
4039 static const struct opcode twobyte_table[256] = {
4040 /* 0x00 - 0x0F */
4041 G(0, group6), GD(0, &group7), N, N,
4042 N, I(ImplicitOps | EmulateOnUD, em_syscall),
4043 II(ImplicitOps | Priv, em_clts, clts), N,
4044 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4045 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4046 /* 0x10 - 0x1F */
4047 N, N, N, N, N, N, N, N,
4048 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4049 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4050 /* 0x20 - 0x2F */
4051 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4052 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4053 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4054 check_cr_write),
4055 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4056 check_dr_write),
4057 N, N, N, N,
4058 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4059 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4060 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4061 N, N, N, N,
4062 /* 0x30 - 0x3F */
4063 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4064 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4065 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4066 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4067 I(ImplicitOps | EmulateOnUD, em_sysenter),
4068 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4069 N, N,
4070 N, N, N, N, N, N, N, N,
4071 /* 0x40 - 0x4F */
4072 X16(D(DstReg | SrcMem | ModRM)),
4073 /* 0x50 - 0x5F */
4074 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4075 /* 0x60 - 0x6F */
4076 N, N, N, N,
4077 N, N, N, N,
4078 N, N, N, N,
4079 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4080 /* 0x70 - 0x7F */
4081 N, N, N, N,
4082 N, N, N, N,
4083 N, N, N, N,
4084 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4085 /* 0x80 - 0x8F */
4086 X16(D(SrcImm | NearBranch)),
4087 /* 0x90 - 0x9F */
4088 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4089 /* 0xA0 - 0xA7 */
4090 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4091 II(ImplicitOps, em_cpuid, cpuid),
4092 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4093 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4094 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4095 /* 0xA8 - 0xAF */
4096 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4097 DI(ImplicitOps, rsm),
4098 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4099 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4100 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4101 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4102 /* 0xB0 - 0xB7 */
4103 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
4104 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4105 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4106 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4107 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4108 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4109 /* 0xB8 - 0xBF */
4110 N, N,
4111 G(BitOp, group8),
4112 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4113 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
4114 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4115 /* 0xC0 - 0xC7 */
4116 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4117 N, D(DstMem | SrcReg | ModRM | Mov),
4118 N, N, N, GD(0, &group9),
4119 /* 0xC8 - 0xCF */
4120 X8(I(DstReg, em_bswap)),
4121 /* 0xD0 - 0xDF */
4122 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4123 /* 0xE0 - 0xEF */
4124 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4125 N, N, N, N, N, N, N, N,
4126 /* 0xF0 - 0xFF */
4127 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4128 };
4129
4130 static const struct gprefix three_byte_0f_38_f0 = {
4131 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
4132 };
4133
4134 static const struct gprefix three_byte_0f_38_f1 = {
4135 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
4136 };
4137
4138 /*
4139 * Insns below are selected by the prefix which indexed by the third opcode
4140 * byte.
4141 */
4142 static const struct opcode opcode_map_0f_38[256] = {
4143 /* 0x00 - 0x7f */
4144 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4145 /* 0x80 - 0xef */
4146 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4147 /* 0xf0 - 0xf1 */
4148 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4149 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4150 /* 0xf2 - 0xff */
4151 N, N, X4(N), X8(N)
4152 };
4153
4154 #undef D
4155 #undef N
4156 #undef G
4157 #undef GD
4158 #undef I
4159 #undef GP
4160 #undef EXT
4161
4162 #undef D2bv
4163 #undef D2bvIP
4164 #undef I2bv
4165 #undef I2bvIP
4166 #undef I6ALU
4167
4168 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4169 {
4170 unsigned size;
4171
4172 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4173 if (size == 8)
4174 size = 4;
4175 return size;
4176 }
4177
4178 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4179 unsigned size, bool sign_extension)
4180 {
4181 int rc = X86EMUL_CONTINUE;
4182
4183 op->type = OP_IMM;
4184 op->bytes = size;
4185 op->addr.mem.ea = ctxt->_eip;
4186 /* NB. Immediates are sign-extended as necessary. */
4187 switch (op->bytes) {
4188 case 1:
4189 op->val = insn_fetch(s8, ctxt);
4190 break;
4191 case 2:
4192 op->val = insn_fetch(s16, ctxt);
4193 break;
4194 case 4:
4195 op->val = insn_fetch(s32, ctxt);
4196 break;
4197 case 8:
4198 op->val = insn_fetch(s64, ctxt);
4199 break;
4200 }
4201 if (!sign_extension) {
4202 switch (op->bytes) {
4203 case 1:
4204 op->val &= 0xff;
4205 break;
4206 case 2:
4207 op->val &= 0xffff;
4208 break;
4209 case 4:
4210 op->val &= 0xffffffff;
4211 break;
4212 }
4213 }
4214 done:
4215 return rc;
4216 }
4217
4218 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4219 unsigned d)
4220 {
4221 int rc = X86EMUL_CONTINUE;
4222
4223 switch (d) {
4224 case OpReg:
4225 decode_register_operand(ctxt, op);
4226 break;
4227 case OpImmUByte:
4228 rc = decode_imm(ctxt, op, 1, false);
4229 break;
4230 case OpMem:
4231 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4232 mem_common:
4233 *op = ctxt->memop;
4234 ctxt->memopp = op;
4235 if (ctxt->d & BitOp)
4236 fetch_bit_operand(ctxt);
4237 op->orig_val = op->val;
4238 break;
4239 case OpMem64:
4240 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4241 goto mem_common;
4242 case OpAcc:
4243 op->type = OP_REG;
4244 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4245 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4246 fetch_register_operand(op);
4247 op->orig_val = op->val;
4248 break;
4249 case OpAccLo:
4250 op->type = OP_REG;
4251 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4252 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4253 fetch_register_operand(op);
4254 op->orig_val = op->val;
4255 break;
4256 case OpAccHi:
4257 if (ctxt->d & ByteOp) {
4258 op->type = OP_NONE;
4259 break;
4260 }
4261 op->type = OP_REG;
4262 op->bytes = ctxt->op_bytes;
4263 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4264 fetch_register_operand(op);
4265 op->orig_val = op->val;
4266 break;
4267 case OpDI:
4268 op->type = OP_MEM;
4269 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4270 op->addr.mem.ea =
4271 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4272 op->addr.mem.seg = VCPU_SREG_ES;
4273 op->val = 0;
4274 op->count = 1;
4275 break;
4276 case OpDX:
4277 op->type = OP_REG;
4278 op->bytes = 2;
4279 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4280 fetch_register_operand(op);
4281 break;
4282 case OpCL:
4283 op->bytes = 1;
4284 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4285 break;
4286 case OpImmByte:
4287 rc = decode_imm(ctxt, op, 1, true);
4288 break;
4289 case OpOne:
4290 op->bytes = 1;
4291 op->val = 1;
4292 break;
4293 case OpImm:
4294 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4295 break;
4296 case OpImm64:
4297 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4298 break;
4299 case OpMem8:
4300 ctxt->memop.bytes = 1;
4301 if (ctxt->memop.type == OP_REG) {
4302 ctxt->memop.addr.reg = decode_register(ctxt,
4303 ctxt->modrm_rm, true);
4304 fetch_register_operand(&ctxt->memop);
4305 }
4306 goto mem_common;
4307 case OpMem16:
4308 ctxt->memop.bytes = 2;
4309 goto mem_common;
4310 case OpMem32:
4311 ctxt->memop.bytes = 4;
4312 goto mem_common;
4313 case OpImmU16:
4314 rc = decode_imm(ctxt, op, 2, false);
4315 break;
4316 case OpImmU:
4317 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4318 break;
4319 case OpSI:
4320 op->type = OP_MEM;
4321 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4322 op->addr.mem.ea =
4323 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
4324 op->addr.mem.seg = ctxt->seg_override;
4325 op->val = 0;
4326 op->count = 1;
4327 break;
4328 case OpXLat:
4329 op->type = OP_MEM;
4330 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4331 op->addr.mem.ea =
4332 register_address(ctxt,
4333 reg_read(ctxt, VCPU_REGS_RBX) +
4334 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4335 op->addr.mem.seg = ctxt->seg_override;
4336 op->val = 0;
4337 break;
4338 case OpImmFAddr:
4339 op->type = OP_IMM;
4340 op->addr.mem.ea = ctxt->_eip;
4341 op->bytes = ctxt->op_bytes + 2;
4342 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4343 break;
4344 case OpMemFAddr:
4345 ctxt->memop.bytes = ctxt->op_bytes + 2;
4346 goto mem_common;
4347 case OpES:
4348 op->val = VCPU_SREG_ES;
4349 break;
4350 case OpCS:
4351 op->val = VCPU_SREG_CS;
4352 break;
4353 case OpSS:
4354 op->val = VCPU_SREG_SS;
4355 break;
4356 case OpDS:
4357 op->val = VCPU_SREG_DS;
4358 break;
4359 case OpFS:
4360 op->val = VCPU_SREG_FS;
4361 break;
4362 case OpGS:
4363 op->val = VCPU_SREG_GS;
4364 break;
4365 case OpImplicit:
4366 /* Special instructions do their own operand decoding. */
4367 default:
4368 op->type = OP_NONE; /* Disable writeback. */
4369 break;
4370 }
4371
4372 done:
4373 return rc;
4374 }
4375
4376 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4377 {
4378 int rc = X86EMUL_CONTINUE;
4379 int mode = ctxt->mode;
4380 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4381 bool op_prefix = false;
4382 bool has_seg_override = false;
4383 struct opcode opcode;
4384
4385 ctxt->memop.type = OP_NONE;
4386 ctxt->memopp = NULL;
4387 ctxt->_eip = ctxt->eip;
4388 ctxt->fetch.ptr = ctxt->fetch.data;
4389 ctxt->fetch.end = ctxt->fetch.data + insn_len;
4390 ctxt->opcode_len = 1;
4391 if (insn_len > 0)
4392 memcpy(ctxt->fetch.data, insn, insn_len);
4393 else {
4394 rc = __do_insn_fetch_bytes(ctxt, 1);
4395 if (rc != X86EMUL_CONTINUE)
4396 return rc;
4397 }
4398
4399 switch (mode) {
4400 case X86EMUL_MODE_REAL:
4401 case X86EMUL_MODE_VM86:
4402 case X86EMUL_MODE_PROT16:
4403 def_op_bytes = def_ad_bytes = 2;
4404 break;
4405 case X86EMUL_MODE_PROT32:
4406 def_op_bytes = def_ad_bytes = 4;
4407 break;
4408 #ifdef CONFIG_X86_64
4409 case X86EMUL_MODE_PROT64:
4410 def_op_bytes = 4;
4411 def_ad_bytes = 8;
4412 break;
4413 #endif
4414 default:
4415 return EMULATION_FAILED;
4416 }
4417
4418 ctxt->op_bytes = def_op_bytes;
4419 ctxt->ad_bytes = def_ad_bytes;
4420
4421 /* Legacy prefixes. */
4422 for (;;) {
4423 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4424 case 0x66: /* operand-size override */
4425 op_prefix = true;
4426 /* switch between 2/4 bytes */
4427 ctxt->op_bytes = def_op_bytes ^ 6;
4428 break;
4429 case 0x67: /* address-size override */
4430 if (mode == X86EMUL_MODE_PROT64)
4431 /* switch between 4/8 bytes */
4432 ctxt->ad_bytes = def_ad_bytes ^ 12;
4433 else
4434 /* switch between 2/4 bytes */
4435 ctxt->ad_bytes = def_ad_bytes ^ 6;
4436 break;
4437 case 0x26: /* ES override */
4438 case 0x2e: /* CS override */
4439 case 0x36: /* SS override */
4440 case 0x3e: /* DS override */
4441 has_seg_override = true;
4442 ctxt->seg_override = (ctxt->b >> 3) & 3;
4443 break;
4444 case 0x64: /* FS override */
4445 case 0x65: /* GS override */
4446 has_seg_override = true;
4447 ctxt->seg_override = ctxt->b & 7;
4448 break;
4449 case 0x40 ... 0x4f: /* REX */
4450 if (mode != X86EMUL_MODE_PROT64)
4451 goto done_prefixes;
4452 ctxt->rex_prefix = ctxt->b;
4453 continue;
4454 case 0xf0: /* LOCK */
4455 ctxt->lock_prefix = 1;
4456 break;
4457 case 0xf2: /* REPNE/REPNZ */
4458 case 0xf3: /* REP/REPE/REPZ */
4459 ctxt->rep_prefix = ctxt->b;
4460 break;
4461 default:
4462 goto done_prefixes;
4463 }
4464
4465 /* Any legacy prefix after a REX prefix nullifies its effect. */
4466
4467 ctxt->rex_prefix = 0;
4468 }
4469
4470 done_prefixes:
4471
4472 /* REX prefix. */
4473 if (ctxt->rex_prefix & 8)
4474 ctxt->op_bytes = 8; /* REX.W */
4475
4476 /* Opcode byte(s). */
4477 opcode = opcode_table[ctxt->b];
4478 /* Two-byte opcode? */
4479 if (ctxt->b == 0x0f) {
4480 ctxt->opcode_len = 2;
4481 ctxt->b = insn_fetch(u8, ctxt);
4482 opcode = twobyte_table[ctxt->b];
4483
4484 /* 0F_38 opcode map */
4485 if (ctxt->b == 0x38) {
4486 ctxt->opcode_len = 3;
4487 ctxt->b = insn_fetch(u8, ctxt);
4488 opcode = opcode_map_0f_38[ctxt->b];
4489 }
4490 }
4491 ctxt->d = opcode.flags;
4492
4493 if (ctxt->d & ModRM)
4494 ctxt->modrm = insn_fetch(u8, ctxt);
4495
4496 /* vex-prefix instructions are not implemented */
4497 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4498 (mode == X86EMUL_MODE_PROT64 ||
4499 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4500 ctxt->d = NotImpl;
4501 }
4502
4503 while (ctxt->d & GroupMask) {
4504 switch (ctxt->d & GroupMask) {
4505 case Group:
4506 goffset = (ctxt->modrm >> 3) & 7;
4507 opcode = opcode.u.group[goffset];
4508 break;
4509 case GroupDual:
4510 goffset = (ctxt->modrm >> 3) & 7;
4511 if ((ctxt->modrm >> 6) == 3)
4512 opcode = opcode.u.gdual->mod3[goffset];
4513 else
4514 opcode = opcode.u.gdual->mod012[goffset];
4515 break;
4516 case RMExt:
4517 goffset = ctxt->modrm & 7;
4518 opcode = opcode.u.group[goffset];
4519 break;
4520 case Prefix:
4521 if (ctxt->rep_prefix && op_prefix)
4522 return EMULATION_FAILED;
4523 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4524 switch (simd_prefix) {
4525 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4526 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4527 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4528 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4529 }
4530 break;
4531 case Escape:
4532 if (ctxt->modrm > 0xbf)
4533 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4534 else
4535 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4536 break;
4537 default:
4538 return EMULATION_FAILED;
4539 }
4540
4541 ctxt->d &= ~(u64)GroupMask;
4542 ctxt->d |= opcode.flags;
4543 }
4544
4545 /* Unrecognised? */
4546 if (ctxt->d == 0)
4547 return EMULATION_FAILED;
4548
4549 ctxt->execute = opcode.u.execute;
4550
4551 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4552 return EMULATION_FAILED;
4553
4554 if (unlikely(ctxt->d &
4555 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch))) {
4556 /*
4557 * These are copied unconditionally here, and checked unconditionally
4558 * in x86_emulate_insn.
4559 */
4560 ctxt->check_perm = opcode.check_perm;
4561 ctxt->intercept = opcode.intercept;
4562
4563 if (ctxt->d & NotImpl)
4564 return EMULATION_FAILED;
4565
4566 if (mode == X86EMUL_MODE_PROT64) {
4567 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4568 ctxt->op_bytes = 8;
4569 else if (ctxt->d & NearBranch)
4570 ctxt->op_bytes = 8;
4571 }
4572
4573 if (ctxt->d & Op3264) {
4574 if (mode == X86EMUL_MODE_PROT64)
4575 ctxt->op_bytes = 8;
4576 else
4577 ctxt->op_bytes = 4;
4578 }
4579
4580 if (ctxt->d & Sse)
4581 ctxt->op_bytes = 16;
4582 else if (ctxt->d & Mmx)
4583 ctxt->op_bytes = 8;
4584 }
4585
4586 /* ModRM and SIB bytes. */
4587 if (ctxt->d & ModRM) {
4588 rc = decode_modrm(ctxt, &ctxt->memop);
4589 if (!has_seg_override) {
4590 has_seg_override = true;
4591 ctxt->seg_override = ctxt->modrm_seg;
4592 }
4593 } else if (ctxt->d & MemAbs)
4594 rc = decode_abs(ctxt, &ctxt->memop);
4595 if (rc != X86EMUL_CONTINUE)
4596 goto done;
4597
4598 if (!has_seg_override)
4599 ctxt->seg_override = VCPU_SREG_DS;
4600
4601 ctxt->memop.addr.mem.seg = ctxt->seg_override;
4602
4603 /*
4604 * Decode and fetch the source operand: register, memory
4605 * or immediate.
4606 */
4607 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4608 if (rc != X86EMUL_CONTINUE)
4609 goto done;
4610
4611 /*
4612 * Decode and fetch the second source operand: register, memory
4613 * or immediate.
4614 */
4615 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4616 if (rc != X86EMUL_CONTINUE)
4617 goto done;
4618
4619 /* Decode and fetch the destination operand: register or memory. */
4620 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4621
4622 if (ctxt->rip_relative)
4623 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4624
4625 done:
4626 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4627 }
4628
4629 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4630 {
4631 return ctxt->d & PageTable;
4632 }
4633
4634 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4635 {
4636 /* The second termination condition only applies for REPE
4637 * and REPNE. Test if the repeat string operation prefix is
4638 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4639 * corresponding termination condition according to:
4640 * - if REPE/REPZ and ZF = 0 then done
4641 * - if REPNE/REPNZ and ZF = 1 then done
4642 */
4643 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4644 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4645 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4646 ((ctxt->eflags & EFLG_ZF) == 0))
4647 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4648 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4649 return true;
4650
4651 return false;
4652 }
4653
4654 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4655 {
4656 bool fault = false;
4657
4658 ctxt->ops->get_fpu(ctxt);
4659 asm volatile("1: fwait \n\t"
4660 "2: \n\t"
4661 ".pushsection .fixup,\"ax\" \n\t"
4662 "3: \n\t"
4663 "movb $1, %[fault] \n\t"
4664 "jmp 2b \n\t"
4665 ".popsection \n\t"
4666 _ASM_EXTABLE(1b, 3b)
4667 : [fault]"+qm"(fault));
4668 ctxt->ops->put_fpu(ctxt);
4669
4670 if (unlikely(fault))
4671 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4672
4673 return X86EMUL_CONTINUE;
4674 }
4675
4676 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4677 struct operand *op)
4678 {
4679 if (op->type == OP_MM)
4680 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4681 }
4682
4683 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4684 {
4685 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4686 if (!(ctxt->d & ByteOp))
4687 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4688 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4689 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4690 [fastop]"+S"(fop)
4691 : "c"(ctxt->src2.val));
4692 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4693 if (!fop) /* exception is returned in fop variable */
4694 return emulate_de(ctxt);
4695 return X86EMUL_CONTINUE;
4696 }
4697
4698 void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4699 {
4700 memset(&ctxt->rip_relative, 0,
4701 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
4702
4703 ctxt->io_read.pos = 0;
4704 ctxt->io_read.end = 0;
4705 ctxt->mem_read.end = 0;
4706 }
4707
4708 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4709 {
4710 const struct x86_emulate_ops *ops = ctxt->ops;
4711 int rc = X86EMUL_CONTINUE;
4712 int saved_dst_type = ctxt->dst.type;
4713
4714 ctxt->mem_read.pos = 0;
4715
4716 /* LOCK prefix is allowed only with some instructions */
4717 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4718 rc = emulate_ud(ctxt);
4719 goto done;
4720 }
4721
4722 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4723 rc = emulate_ud(ctxt);
4724 goto done;
4725 }
4726
4727 if (unlikely(ctxt->d &
4728 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4729 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4730 (ctxt->d & Undefined)) {
4731 rc = emulate_ud(ctxt);
4732 goto done;
4733 }
4734
4735 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4736 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4737 rc = emulate_ud(ctxt);
4738 goto done;
4739 }
4740
4741 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4742 rc = emulate_nm(ctxt);
4743 goto done;
4744 }
4745
4746 if (ctxt->d & Mmx) {
4747 rc = flush_pending_x87_faults(ctxt);
4748 if (rc != X86EMUL_CONTINUE)
4749 goto done;
4750 /*
4751 * Now that we know the fpu is exception safe, we can fetch
4752 * operands from it.
4753 */
4754 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4755 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4756 if (!(ctxt->d & Mov))
4757 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4758 }
4759
4760 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4761 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4762 X86_ICPT_PRE_EXCEPT);
4763 if (rc != X86EMUL_CONTINUE)
4764 goto done;
4765 }
4766
4767 /* Privileged instruction can be executed only in CPL=0 */
4768 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4769 if (ctxt->d & PrivUD)
4770 rc = emulate_ud(ctxt);
4771 else
4772 rc = emulate_gp(ctxt, 0);
4773 goto done;
4774 }
4775
4776 /* Instruction can only be executed in protected mode */
4777 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4778 rc = emulate_ud(ctxt);
4779 goto done;
4780 }
4781
4782 /* Do instruction specific permission checks */
4783 if (ctxt->d & CheckPerm) {
4784 rc = ctxt->check_perm(ctxt);
4785 if (rc != X86EMUL_CONTINUE)
4786 goto done;
4787 }
4788
4789 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4790 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4791 X86_ICPT_POST_EXCEPT);
4792 if (rc != X86EMUL_CONTINUE)
4793 goto done;
4794 }
4795
4796 if (ctxt->rep_prefix && (ctxt->d & String)) {
4797 /* All REP prefixes have the same first termination condition */
4798 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4799 ctxt->eip = ctxt->_eip;
4800 ctxt->eflags &= ~EFLG_RF;
4801 goto done;
4802 }
4803 }
4804 }
4805
4806 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4807 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4808 ctxt->src.valptr, ctxt->src.bytes);
4809 if (rc != X86EMUL_CONTINUE)
4810 goto done;
4811 ctxt->src.orig_val64 = ctxt->src.val64;
4812 }
4813
4814 if (ctxt->src2.type == OP_MEM) {
4815 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4816 &ctxt->src2.val, ctxt->src2.bytes);
4817 if (rc != X86EMUL_CONTINUE)
4818 goto done;
4819 }
4820
4821 if ((ctxt->d & DstMask) == ImplicitOps)
4822 goto special_insn;
4823
4824
4825 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4826 /* optimisation - avoid slow emulated read if Mov */
4827 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4828 &ctxt->dst.val, ctxt->dst.bytes);
4829 if (rc != X86EMUL_CONTINUE)
4830 goto done;
4831 }
4832 ctxt->dst.orig_val = ctxt->dst.val;
4833
4834 special_insn:
4835
4836 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4837 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4838 X86_ICPT_POST_MEMACCESS);
4839 if (rc != X86EMUL_CONTINUE)
4840 goto done;
4841 }
4842
4843 if (ctxt->rep_prefix && (ctxt->d & String))
4844 ctxt->eflags |= EFLG_RF;
4845 else
4846 ctxt->eflags &= ~EFLG_RF;
4847
4848 if (ctxt->execute) {
4849 if (ctxt->d & Fastop) {
4850 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4851 rc = fastop(ctxt, fop);
4852 if (rc != X86EMUL_CONTINUE)
4853 goto done;
4854 goto writeback;
4855 }
4856 rc = ctxt->execute(ctxt);
4857 if (rc != X86EMUL_CONTINUE)
4858 goto done;
4859 goto writeback;
4860 }
4861
4862 if (ctxt->opcode_len == 2)
4863 goto twobyte_insn;
4864 else if (ctxt->opcode_len == 3)
4865 goto threebyte_insn;
4866
4867 switch (ctxt->b) {
4868 case 0x63: /* movsxd */
4869 if (ctxt->mode != X86EMUL_MODE_PROT64)
4870 goto cannot_emulate;
4871 ctxt->dst.val = (s32) ctxt->src.val;
4872 break;
4873 case 0x70 ... 0x7f: /* jcc (short) */
4874 if (test_cc(ctxt->b, ctxt->eflags))
4875 rc = jmp_rel(ctxt, ctxt->src.val);
4876 break;
4877 case 0x8d: /* lea r16/r32, m */
4878 ctxt->dst.val = ctxt->src.addr.mem.ea;
4879 break;
4880 case 0x90 ... 0x97: /* nop / xchg reg, rax */
4881 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4882 ctxt->dst.type = OP_NONE;
4883 else
4884 rc = em_xchg(ctxt);
4885 break;
4886 case 0x98: /* cbw/cwde/cdqe */
4887 switch (ctxt->op_bytes) {
4888 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4889 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4890 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4891 }
4892 break;
4893 case 0xcc: /* int3 */
4894 rc = emulate_int(ctxt, 3);
4895 break;
4896 case 0xcd: /* int n */
4897 rc = emulate_int(ctxt, ctxt->src.val);
4898 break;
4899 case 0xce: /* into */
4900 if (ctxt->eflags & EFLG_OF)
4901 rc = emulate_int(ctxt, 4);
4902 break;
4903 case 0xe9: /* jmp rel */
4904 case 0xeb: /* jmp rel short */
4905 rc = jmp_rel(ctxt, ctxt->src.val);
4906 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4907 break;
4908 case 0xf4: /* hlt */
4909 ctxt->ops->halt(ctxt);
4910 break;
4911 case 0xf5: /* cmc */
4912 /* complement carry flag from eflags reg */
4913 ctxt->eflags ^= EFLG_CF;
4914 break;
4915 case 0xf8: /* clc */
4916 ctxt->eflags &= ~EFLG_CF;
4917 break;
4918 case 0xf9: /* stc */
4919 ctxt->eflags |= EFLG_CF;
4920 break;
4921 case 0xfc: /* cld */
4922 ctxt->eflags &= ~EFLG_DF;
4923 break;
4924 case 0xfd: /* std */
4925 ctxt->eflags |= EFLG_DF;
4926 break;
4927 default:
4928 goto cannot_emulate;
4929 }
4930
4931 if (rc != X86EMUL_CONTINUE)
4932 goto done;
4933
4934 writeback:
4935 if (ctxt->d & SrcWrite) {
4936 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4937 rc = writeback(ctxt, &ctxt->src);
4938 if (rc != X86EMUL_CONTINUE)
4939 goto done;
4940 }
4941 if (!(ctxt->d & NoWrite)) {
4942 rc = writeback(ctxt, &ctxt->dst);
4943 if (rc != X86EMUL_CONTINUE)
4944 goto done;
4945 }
4946
4947 /*
4948 * restore dst type in case the decoding will be reused
4949 * (happens for string instruction )
4950 */
4951 ctxt->dst.type = saved_dst_type;
4952
4953 if ((ctxt->d & SrcMask) == SrcSI)
4954 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4955
4956 if ((ctxt->d & DstMask) == DstDI)
4957 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4958
4959 if (ctxt->rep_prefix && (ctxt->d & String)) {
4960 unsigned int count;
4961 struct read_cache *r = &ctxt->io_read;
4962 if ((ctxt->d & SrcMask) == SrcSI)
4963 count = ctxt->src.count;
4964 else
4965 count = ctxt->dst.count;
4966 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4967 -count);
4968
4969 if (!string_insn_completed(ctxt)) {
4970 /*
4971 * Re-enter guest when pio read ahead buffer is empty
4972 * or, if it is not used, after each 1024 iteration.
4973 */
4974 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4975 (r->end == 0 || r->end != r->pos)) {
4976 /*
4977 * Reset read cache. Usually happens before
4978 * decode, but since instruction is restarted
4979 * we have to do it here.
4980 */
4981 ctxt->mem_read.end = 0;
4982 writeback_registers(ctxt);
4983 return EMULATION_RESTART;
4984 }
4985 goto done; /* skip rip writeback */
4986 }
4987 ctxt->eflags &= ~EFLG_RF;
4988 }
4989
4990 ctxt->eip = ctxt->_eip;
4991
4992 done:
4993 if (rc == X86EMUL_PROPAGATE_FAULT) {
4994 WARN_ON(ctxt->exception.vector > 0x1f);
4995 ctxt->have_exception = true;
4996 }
4997 if (rc == X86EMUL_INTERCEPTED)
4998 return EMULATION_INTERCEPTED;
4999
5000 if (rc == X86EMUL_CONTINUE)
5001 writeback_registers(ctxt);
5002
5003 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5004
5005 twobyte_insn:
5006 switch (ctxt->b) {
5007 case 0x09: /* wbinvd */
5008 (ctxt->ops->wbinvd)(ctxt);
5009 break;
5010 case 0x08: /* invd */
5011 case 0x0d: /* GrpP (prefetch) */
5012 case 0x18: /* Grp16 (prefetch/nop) */
5013 case 0x1f: /* nop */
5014 break;
5015 case 0x20: /* mov cr, reg */
5016 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5017 break;
5018 case 0x21: /* mov from dr to reg */
5019 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
5020 break;
5021 case 0x40 ... 0x4f: /* cmov */
5022 if (test_cc(ctxt->b, ctxt->eflags))
5023 ctxt->dst.val = ctxt->src.val;
5024 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5025 ctxt->op_bytes != 4)
5026 ctxt->dst.type = OP_NONE; /* no writeback */
5027 break;
5028 case 0x80 ... 0x8f: /* jnz rel, etc*/
5029 if (test_cc(ctxt->b, ctxt->eflags))
5030 rc = jmp_rel(ctxt, ctxt->src.val);
5031 break;
5032 case 0x90 ... 0x9f: /* setcc r/m8 */
5033 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5034 break;
5035 case 0xb6 ... 0xb7: /* movzx */
5036 ctxt->dst.bytes = ctxt->op_bytes;
5037 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5038 : (u16) ctxt->src.val;
5039 break;
5040 case 0xbe ... 0xbf: /* movsx */
5041 ctxt->dst.bytes = ctxt->op_bytes;
5042 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5043 (s16) ctxt->src.val;
5044 break;
5045 case 0xc3: /* movnti */
5046 ctxt->dst.bytes = ctxt->op_bytes;
5047 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
5048 (u32) ctxt->src.val;
5049 break;
5050 default:
5051 goto cannot_emulate;
5052 }
5053
5054 threebyte_insn:
5055
5056 if (rc != X86EMUL_CONTINUE)
5057 goto done;
5058
5059 goto writeback;
5060
5061 cannot_emulate:
5062 return EMULATION_FAILED;
5063 }
5064
5065 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5066 {
5067 invalidate_registers(ctxt);
5068 }
5069
5070 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5071 {
5072 writeback_registers(ctxt);
5073 }
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