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KVM: x86 emulator: check io permissions only once for string pio
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #ifndef __KERNEL__
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #else
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
32 #endif
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
35
36 #include "x86.h"
37 #include "tss.h"
38
39 /*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstMask (7<<1)
58 /* Source operand type. */
59 #define SrcNone (0<<4) /* No source operand. */
60 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcMask (0xf<<4)
75 /* Generic ModRM decode. */
76 #define ModRM (1<<8)
77 /* Destination is only written; never read. */
78 #define Mov (1<<9)
79 #define BitOp (1<<10)
80 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
81 #define String (1<<12) /* String instruction (rep capable) */
82 #define Stack (1<<13) /* Stack instruction (push/pop) */
83 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
85 /* Misc flags */
86 #define Undefined (1<<25) /* No Such Instruction */
87 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
88 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89 #define No64 (1<<28)
90 /* Source 2 operand type */
91 #define Src2None (0<<29)
92 #define Src2CL (1<<29)
93 #define Src2ImmByte (2<<29)
94 #define Src2One (3<<29)
95 #define Src2Mask (7<<29)
96
97 #define X2(x...) x, x
98 #define X3(x...) X2(x), x
99 #define X4(x...) X2(x), X2(x)
100 #define X5(x...) X4(x), x
101 #define X6(x...) X4(x), X2(x)
102 #define X7(x...) X4(x), X3(x)
103 #define X8(x...) X4(x), X4(x)
104 #define X16(x...) X8(x), X8(x)
105
106 struct opcode {
107 u32 flags;
108 union {
109 int (*execute)(struct x86_emulate_ctxt *ctxt);
110 struct opcode *group;
111 struct group_dual *gdual;
112 } u;
113 };
114
115 struct group_dual {
116 struct opcode mod012[8];
117 struct opcode mod3[8];
118 };
119
120 /* EFLAGS bit definitions. */
121 #define EFLG_ID (1<<21)
122 #define EFLG_VIP (1<<20)
123 #define EFLG_VIF (1<<19)
124 #define EFLG_AC (1<<18)
125 #define EFLG_VM (1<<17)
126 #define EFLG_RF (1<<16)
127 #define EFLG_IOPL (3<<12)
128 #define EFLG_NT (1<<14)
129 #define EFLG_OF (1<<11)
130 #define EFLG_DF (1<<10)
131 #define EFLG_IF (1<<9)
132 #define EFLG_TF (1<<8)
133 #define EFLG_SF (1<<7)
134 #define EFLG_ZF (1<<6)
135 #define EFLG_AF (1<<4)
136 #define EFLG_PF (1<<2)
137 #define EFLG_CF (1<<0)
138
139 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
140 #define EFLG_RESERVED_ONE_MASK 2
141
142 /*
143 * Instruction emulation:
144 * Most instructions are emulated directly via a fragment of inline assembly
145 * code. This allows us to save/restore EFLAGS and thus very easily pick up
146 * any modified flags.
147 */
148
149 #if defined(CONFIG_X86_64)
150 #define _LO32 "k" /* force 32-bit operand */
151 #define _STK "%%rsp" /* stack pointer */
152 #elif defined(__i386__)
153 #define _LO32 "" /* force 32-bit operand */
154 #define _STK "%%esp" /* stack pointer */
155 #endif
156
157 /*
158 * These EFLAGS bits are restored from saved value during emulation, and
159 * any changes are written back to the saved value after emulation.
160 */
161 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
162
163 /* Before executing instruction: restore necessary bits in EFLAGS. */
164 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
165 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
166 "movl %"_sav",%"_LO32 _tmp"; " \
167 "push %"_tmp"; " \
168 "push %"_tmp"; " \
169 "movl %"_msk",%"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "pushf; " \
172 "notl %"_LO32 _tmp"; " \
173 "andl %"_LO32 _tmp",("_STK"); " \
174 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
175 "pop %"_tmp"; " \
176 "orl %"_LO32 _tmp",("_STK"); " \
177 "popf; " \
178 "pop %"_sav"; "
179
180 /* After executing instruction: write-back necessary bits in EFLAGS. */
181 #define _POST_EFLAGS(_sav, _msk, _tmp) \
182 /* _sav |= EFLAGS & _msk; */ \
183 "pushf; " \
184 "pop %"_tmp"; " \
185 "andl %"_msk",%"_LO32 _tmp"; " \
186 "orl %"_LO32 _tmp",%"_sav"; "
187
188 #ifdef CONFIG_X86_64
189 #define ON64(x) x
190 #else
191 #define ON64(x)
192 #endif
193
194 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
195 do { \
196 __asm__ __volatile__ ( \
197 _PRE_EFLAGS("0", "4", "2") \
198 _op _suffix " %"_x"3,%1; " \
199 _POST_EFLAGS("0", "4", "2") \
200 : "=m" (_eflags), "=m" ((_dst).val), \
201 "=&r" (_tmp) \
202 : _y ((_src).val), "i" (EFLAGS_MASK)); \
203 } while (0)
204
205
206 /* Raw emulation: instruction has two explicit operands. */
207 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
208 do { \
209 unsigned long _tmp; \
210 \
211 switch ((_dst).bytes) { \
212 case 2: \
213 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
214 break; \
215 case 4: \
216 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
217 break; \
218 case 8: \
219 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
220 break; \
221 } \
222 } while (0)
223
224 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
225 do { \
226 unsigned long _tmp; \
227 switch ((_dst).bytes) { \
228 case 1: \
229 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
230 break; \
231 default: \
232 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
233 _wx, _wy, _lx, _ly, _qx, _qy); \
234 break; \
235 } \
236 } while (0)
237
238 /* Source operand is byte-sized and may be restricted to just %cl. */
239 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
240 __emulate_2op(_op, _src, _dst, _eflags, \
241 "b", "c", "b", "c", "b", "c", "b", "c")
242
243 /* Source operand is byte, word, long or quad sized. */
244 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
245 __emulate_2op(_op, _src, _dst, _eflags, \
246 "b", "q", "w", "r", _LO32, "r", "", "r")
247
248 /* Source operand is word, long or quad sized. */
249 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
250 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
251 "w", "r", _LO32, "r", "", "r")
252
253 /* Instruction has three operands and one operand is stored in ECX register */
254 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
255 do { \
256 unsigned long _tmp; \
257 _type _clv = (_cl).val; \
258 _type _srcv = (_src).val; \
259 _type _dstv = (_dst).val; \
260 \
261 __asm__ __volatile__ ( \
262 _PRE_EFLAGS("0", "5", "2") \
263 _op _suffix " %4,%1 \n" \
264 _POST_EFLAGS("0", "5", "2") \
265 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
266 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
267 ); \
268 \
269 (_cl).val = (unsigned long) _clv; \
270 (_src).val = (unsigned long) _srcv; \
271 (_dst).val = (unsigned long) _dstv; \
272 } while (0)
273
274 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
275 do { \
276 switch ((_dst).bytes) { \
277 case 2: \
278 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
279 "w", unsigned short); \
280 break; \
281 case 4: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "l", unsigned int); \
284 break; \
285 case 8: \
286 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "q", unsigned long)); \
288 break; \
289 } \
290 } while (0)
291
292 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
293 do { \
294 unsigned long _tmp; \
295 \
296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0", "3", "2") \
298 _op _suffix " %1; " \
299 _POST_EFLAGS("0", "3", "2") \
300 : "=m" (_eflags), "+m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : "i" (EFLAGS_MASK)); \
303 } while (0)
304
305 /* Instruction has only one explicit operand (no source operand). */
306 #define emulate_1op(_op, _dst, _eflags) \
307 do { \
308 switch ((_dst).bytes) { \
309 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
310 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
311 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
312 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
313 } \
314 } while (0)
315
316 /* Fetch next part of the instruction being emulated. */
317 #define insn_fetch(_type, _size, _eip) \
318 ({ unsigned long _x; \
319 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
320 if (rc != X86EMUL_CONTINUE) \
321 goto done; \
322 (_eip) += (_size); \
323 (_type)_x; \
324 })
325
326 #define insn_fetch_arr(_arr, _size, _eip) \
327 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
328 if (rc != X86EMUL_CONTINUE) \
329 goto done; \
330 (_eip) += (_size); \
331 })
332
333 static inline unsigned long ad_mask(struct decode_cache *c)
334 {
335 return (1UL << (c->ad_bytes << 3)) - 1;
336 }
337
338 /* Access/update address held in a register, based on addressing mode. */
339 static inline unsigned long
340 address_mask(struct decode_cache *c, unsigned long reg)
341 {
342 if (c->ad_bytes == sizeof(unsigned long))
343 return reg;
344 else
345 return reg & ad_mask(c);
346 }
347
348 static inline unsigned long
349 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
350 {
351 return base + address_mask(c, reg);
352 }
353
354 static inline void
355 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
356 {
357 if (c->ad_bytes == sizeof(unsigned long))
358 *reg += inc;
359 else
360 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
361 }
362
363 static inline void jmp_rel(struct decode_cache *c, int rel)
364 {
365 register_address_increment(c, &c->eip, rel);
366 }
367
368 static void set_seg_override(struct decode_cache *c, int seg)
369 {
370 c->has_seg_override = true;
371 c->seg_override = seg;
372 }
373
374 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
375 struct x86_emulate_ops *ops, int seg)
376 {
377 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
378 return 0;
379
380 return ops->get_cached_segment_base(seg, ctxt->vcpu);
381 }
382
383 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
384 struct x86_emulate_ops *ops,
385 struct decode_cache *c)
386 {
387 if (!c->has_seg_override)
388 return 0;
389
390 return seg_base(ctxt, ops, c->seg_override);
391 }
392
393 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
394 struct x86_emulate_ops *ops)
395 {
396 return seg_base(ctxt, ops, VCPU_SREG_ES);
397 }
398
399 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
400 struct x86_emulate_ops *ops)
401 {
402 return seg_base(ctxt, ops, VCPU_SREG_SS);
403 }
404
405 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
406 u32 error, bool valid)
407 {
408 ctxt->exception = vec;
409 ctxt->error_code = error;
410 ctxt->error_code_valid = valid;
411 ctxt->restart = false;
412 }
413
414 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
415 {
416 emulate_exception(ctxt, GP_VECTOR, err, true);
417 }
418
419 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
420 int err)
421 {
422 ctxt->cr2 = addr;
423 emulate_exception(ctxt, PF_VECTOR, err, true);
424 }
425
426 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
427 {
428 emulate_exception(ctxt, UD_VECTOR, 0, false);
429 }
430
431 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
432 {
433 emulate_exception(ctxt, TS_VECTOR, err, true);
434 }
435
436 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
437 struct x86_emulate_ops *ops,
438 unsigned long eip, u8 *dest)
439 {
440 struct fetch_cache *fc = &ctxt->decode.fetch;
441 int rc;
442 int size, cur_size;
443
444 if (eip == fc->end) {
445 cur_size = fc->end - fc->start;
446 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
447 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
448 size, ctxt->vcpu, NULL);
449 if (rc != X86EMUL_CONTINUE)
450 return rc;
451 fc->end += size;
452 }
453 *dest = fc->data[eip - fc->start];
454 return X86EMUL_CONTINUE;
455 }
456
457 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
458 struct x86_emulate_ops *ops,
459 unsigned long eip, void *dest, unsigned size)
460 {
461 int rc;
462
463 /* x86 instructions are limited to 15 bytes. */
464 if (eip + size - ctxt->eip > 15)
465 return X86EMUL_UNHANDLEABLE;
466 while (size--) {
467 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
468 if (rc != X86EMUL_CONTINUE)
469 return rc;
470 }
471 return X86EMUL_CONTINUE;
472 }
473
474 /*
475 * Given the 'reg' portion of a ModRM byte, and a register block, return a
476 * pointer into the block that addresses the relevant register.
477 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
478 */
479 static void *decode_register(u8 modrm_reg, unsigned long *regs,
480 int highbyte_regs)
481 {
482 void *p;
483
484 p = &regs[modrm_reg];
485 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
486 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
487 return p;
488 }
489
490 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
491 struct x86_emulate_ops *ops,
492 void *ptr,
493 u16 *size, unsigned long *address, int op_bytes)
494 {
495 int rc;
496
497 if (op_bytes == 2)
498 op_bytes = 3;
499 *address = 0;
500 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
501 ctxt->vcpu, NULL);
502 if (rc != X86EMUL_CONTINUE)
503 return rc;
504 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
505 ctxt->vcpu, NULL);
506 return rc;
507 }
508
509 static int test_cc(unsigned int condition, unsigned int flags)
510 {
511 int rc = 0;
512
513 switch ((condition & 15) >> 1) {
514 case 0: /* o */
515 rc |= (flags & EFLG_OF);
516 break;
517 case 1: /* b/c/nae */
518 rc |= (flags & EFLG_CF);
519 break;
520 case 2: /* z/e */
521 rc |= (flags & EFLG_ZF);
522 break;
523 case 3: /* be/na */
524 rc |= (flags & (EFLG_CF|EFLG_ZF));
525 break;
526 case 4: /* s */
527 rc |= (flags & EFLG_SF);
528 break;
529 case 5: /* p/pe */
530 rc |= (flags & EFLG_PF);
531 break;
532 case 7: /* le/ng */
533 rc |= (flags & EFLG_ZF);
534 /* fall through */
535 case 6: /* l/nge */
536 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
537 break;
538 }
539
540 /* Odd condition identifiers (lsb == 1) have inverted sense. */
541 return (!!rc ^ (condition & 1));
542 }
543
544 static void decode_register_operand(struct operand *op,
545 struct decode_cache *c,
546 int inhibit_bytereg)
547 {
548 unsigned reg = c->modrm_reg;
549 int highbyte_regs = c->rex_prefix == 0;
550
551 if (!(c->d & ModRM))
552 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
553 op->type = OP_REG;
554 if ((c->d & ByteOp) && !inhibit_bytereg) {
555 op->ptr = decode_register(reg, c->regs, highbyte_regs);
556 op->val = *(u8 *)op->ptr;
557 op->bytes = 1;
558 } else {
559 op->ptr = decode_register(reg, c->regs, 0);
560 op->bytes = c->op_bytes;
561 switch (op->bytes) {
562 case 2:
563 op->val = *(u16 *)op->ptr;
564 break;
565 case 4:
566 op->val = *(u32 *)op->ptr;
567 break;
568 case 8:
569 op->val = *(u64 *) op->ptr;
570 break;
571 }
572 }
573 op->orig_val = op->val;
574 }
575
576 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
577 struct x86_emulate_ops *ops)
578 {
579 struct decode_cache *c = &ctxt->decode;
580 u8 sib;
581 int index_reg = 0, base_reg = 0, scale;
582 int rc = X86EMUL_CONTINUE;
583
584 if (c->rex_prefix) {
585 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
586 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
587 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
588 }
589
590 c->modrm = insn_fetch(u8, 1, c->eip);
591 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
592 c->modrm_reg |= (c->modrm & 0x38) >> 3;
593 c->modrm_rm |= (c->modrm & 0x07);
594 c->modrm_ea = 0;
595 c->use_modrm_ea = 1;
596
597 if (c->modrm_mod == 3) {
598 c->modrm_ptr = decode_register(c->modrm_rm,
599 c->regs, c->d & ByteOp);
600 c->modrm_val = *(unsigned long *)c->modrm_ptr;
601 return rc;
602 }
603
604 if (c->ad_bytes == 2) {
605 unsigned bx = c->regs[VCPU_REGS_RBX];
606 unsigned bp = c->regs[VCPU_REGS_RBP];
607 unsigned si = c->regs[VCPU_REGS_RSI];
608 unsigned di = c->regs[VCPU_REGS_RDI];
609
610 /* 16-bit ModR/M decode. */
611 switch (c->modrm_mod) {
612 case 0:
613 if (c->modrm_rm == 6)
614 c->modrm_ea += insn_fetch(u16, 2, c->eip);
615 break;
616 case 1:
617 c->modrm_ea += insn_fetch(s8, 1, c->eip);
618 break;
619 case 2:
620 c->modrm_ea += insn_fetch(u16, 2, c->eip);
621 break;
622 }
623 switch (c->modrm_rm) {
624 case 0:
625 c->modrm_ea += bx + si;
626 break;
627 case 1:
628 c->modrm_ea += bx + di;
629 break;
630 case 2:
631 c->modrm_ea += bp + si;
632 break;
633 case 3:
634 c->modrm_ea += bp + di;
635 break;
636 case 4:
637 c->modrm_ea += si;
638 break;
639 case 5:
640 c->modrm_ea += di;
641 break;
642 case 6:
643 if (c->modrm_mod != 0)
644 c->modrm_ea += bp;
645 break;
646 case 7:
647 c->modrm_ea += bx;
648 break;
649 }
650 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
651 (c->modrm_rm == 6 && c->modrm_mod != 0))
652 if (!c->has_seg_override)
653 set_seg_override(c, VCPU_SREG_SS);
654 c->modrm_ea = (u16)c->modrm_ea;
655 } else {
656 /* 32/64-bit ModR/M decode. */
657 if ((c->modrm_rm & 7) == 4) {
658 sib = insn_fetch(u8, 1, c->eip);
659 index_reg |= (sib >> 3) & 7;
660 base_reg |= sib & 7;
661 scale = sib >> 6;
662
663 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
664 c->modrm_ea += insn_fetch(s32, 4, c->eip);
665 else
666 c->modrm_ea += c->regs[base_reg];
667 if (index_reg != 4)
668 c->modrm_ea += c->regs[index_reg] << scale;
669 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
670 if (ctxt->mode == X86EMUL_MODE_PROT64)
671 c->rip_relative = 1;
672 } else
673 c->modrm_ea += c->regs[c->modrm_rm];
674 switch (c->modrm_mod) {
675 case 0:
676 if (c->modrm_rm == 5)
677 c->modrm_ea += insn_fetch(s32, 4, c->eip);
678 break;
679 case 1:
680 c->modrm_ea += insn_fetch(s8, 1, c->eip);
681 break;
682 case 2:
683 c->modrm_ea += insn_fetch(s32, 4, c->eip);
684 break;
685 }
686 }
687 done:
688 return rc;
689 }
690
691 static int decode_abs(struct x86_emulate_ctxt *ctxt,
692 struct x86_emulate_ops *ops)
693 {
694 struct decode_cache *c = &ctxt->decode;
695 int rc = X86EMUL_CONTINUE;
696
697 switch (c->ad_bytes) {
698 case 2:
699 c->modrm_ea = insn_fetch(u16, 2, c->eip);
700 break;
701 case 4:
702 c->modrm_ea = insn_fetch(u32, 4, c->eip);
703 break;
704 case 8:
705 c->modrm_ea = insn_fetch(u64, 8, c->eip);
706 break;
707 }
708 done:
709 return rc;
710 }
711
712 static int read_emulated(struct x86_emulate_ctxt *ctxt,
713 struct x86_emulate_ops *ops,
714 unsigned long addr, void *dest, unsigned size)
715 {
716 int rc;
717 struct read_cache *mc = &ctxt->decode.mem_read;
718 u32 err;
719
720 while (size) {
721 int n = min(size, 8u);
722 size -= n;
723 if (mc->pos < mc->end)
724 goto read_cached;
725
726 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
727 ctxt->vcpu);
728 if (rc == X86EMUL_PROPAGATE_FAULT)
729 emulate_pf(ctxt, addr, err);
730 if (rc != X86EMUL_CONTINUE)
731 return rc;
732 mc->end += n;
733
734 read_cached:
735 memcpy(dest, mc->data + mc->pos, n);
736 mc->pos += n;
737 dest += n;
738 addr += n;
739 }
740 return X86EMUL_CONTINUE;
741 }
742
743 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
744 struct x86_emulate_ops *ops,
745 unsigned int size, unsigned short port,
746 void *dest)
747 {
748 struct read_cache *rc = &ctxt->decode.io_read;
749
750 if (rc->pos == rc->end) { /* refill pio read ahead */
751 struct decode_cache *c = &ctxt->decode;
752 unsigned int in_page, n;
753 unsigned int count = c->rep_prefix ?
754 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
755 in_page = (ctxt->eflags & EFLG_DF) ?
756 offset_in_page(c->regs[VCPU_REGS_RDI]) :
757 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
758 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
759 count);
760 if (n == 0)
761 n = 1;
762 rc->pos = rc->end = 0;
763 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
764 return 0;
765 rc->end = n * size;
766 }
767
768 memcpy(dest, rc->data + rc->pos, size);
769 rc->pos += size;
770 return 1;
771 }
772
773 static u32 desc_limit_scaled(struct desc_struct *desc)
774 {
775 u32 limit = get_desc_limit(desc);
776
777 return desc->g ? (limit << 12) | 0xfff : limit;
778 }
779
780 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
781 struct x86_emulate_ops *ops,
782 u16 selector, struct desc_ptr *dt)
783 {
784 if (selector & 1 << 2) {
785 struct desc_struct desc;
786 memset (dt, 0, sizeof *dt);
787 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
788 return;
789
790 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
791 dt->address = get_desc_base(&desc);
792 } else
793 ops->get_gdt(dt, ctxt->vcpu);
794 }
795
796 /* allowed just for 8 bytes segments */
797 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
798 struct x86_emulate_ops *ops,
799 u16 selector, struct desc_struct *desc)
800 {
801 struct desc_ptr dt;
802 u16 index = selector >> 3;
803 int ret;
804 u32 err;
805 ulong addr;
806
807 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
808
809 if (dt.size < index * 8 + 7) {
810 emulate_gp(ctxt, selector & 0xfffc);
811 return X86EMUL_PROPAGATE_FAULT;
812 }
813 addr = dt.address + index * 8;
814 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
815 if (ret == X86EMUL_PROPAGATE_FAULT)
816 emulate_pf(ctxt, addr, err);
817
818 return ret;
819 }
820
821 /* allowed just for 8 bytes segments */
822 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
823 struct x86_emulate_ops *ops,
824 u16 selector, struct desc_struct *desc)
825 {
826 struct desc_ptr dt;
827 u16 index = selector >> 3;
828 u32 err;
829 ulong addr;
830 int ret;
831
832 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
833
834 if (dt.size < index * 8 + 7) {
835 emulate_gp(ctxt, selector & 0xfffc);
836 return X86EMUL_PROPAGATE_FAULT;
837 }
838
839 addr = dt.address + index * 8;
840 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
841 if (ret == X86EMUL_PROPAGATE_FAULT)
842 emulate_pf(ctxt, addr, err);
843
844 return ret;
845 }
846
847 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
848 struct x86_emulate_ops *ops,
849 u16 selector, int seg)
850 {
851 struct desc_struct seg_desc;
852 u8 dpl, rpl, cpl;
853 unsigned err_vec = GP_VECTOR;
854 u32 err_code = 0;
855 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
856 int ret;
857
858 memset(&seg_desc, 0, sizeof seg_desc);
859
860 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
861 || ctxt->mode == X86EMUL_MODE_REAL) {
862 /* set real mode segment descriptor */
863 set_desc_base(&seg_desc, selector << 4);
864 set_desc_limit(&seg_desc, 0xffff);
865 seg_desc.type = 3;
866 seg_desc.p = 1;
867 seg_desc.s = 1;
868 goto load;
869 }
870
871 /* NULL selector is not valid for TR, CS and SS */
872 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
873 && null_selector)
874 goto exception;
875
876 /* TR should be in GDT only */
877 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
878 goto exception;
879
880 if (null_selector) /* for NULL selector skip all following checks */
881 goto load;
882
883 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
884 if (ret != X86EMUL_CONTINUE)
885 return ret;
886
887 err_code = selector & 0xfffc;
888 err_vec = GP_VECTOR;
889
890 /* can't load system descriptor into segment selecor */
891 if (seg <= VCPU_SREG_GS && !seg_desc.s)
892 goto exception;
893
894 if (!seg_desc.p) {
895 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
896 goto exception;
897 }
898
899 rpl = selector & 3;
900 dpl = seg_desc.dpl;
901 cpl = ops->cpl(ctxt->vcpu);
902
903 switch (seg) {
904 case VCPU_SREG_SS:
905 /*
906 * segment is not a writable data segment or segment
907 * selector's RPL != CPL or segment selector's RPL != CPL
908 */
909 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
910 goto exception;
911 break;
912 case VCPU_SREG_CS:
913 if (!(seg_desc.type & 8))
914 goto exception;
915
916 if (seg_desc.type & 4) {
917 /* conforming */
918 if (dpl > cpl)
919 goto exception;
920 } else {
921 /* nonconforming */
922 if (rpl > cpl || dpl != cpl)
923 goto exception;
924 }
925 /* CS(RPL) <- CPL */
926 selector = (selector & 0xfffc) | cpl;
927 break;
928 case VCPU_SREG_TR:
929 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
930 goto exception;
931 break;
932 case VCPU_SREG_LDTR:
933 if (seg_desc.s || seg_desc.type != 2)
934 goto exception;
935 break;
936 default: /* DS, ES, FS, or GS */
937 /*
938 * segment is not a data or readable code segment or
939 * ((segment is a data or nonconforming code segment)
940 * and (both RPL and CPL > DPL))
941 */
942 if ((seg_desc.type & 0xa) == 0x8 ||
943 (((seg_desc.type & 0xc) != 0xc) &&
944 (rpl > dpl && cpl > dpl)))
945 goto exception;
946 break;
947 }
948
949 if (seg_desc.s) {
950 /* mark segment as accessed */
951 seg_desc.type |= 1;
952 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
953 if (ret != X86EMUL_CONTINUE)
954 return ret;
955 }
956 load:
957 ops->set_segment_selector(selector, seg, ctxt->vcpu);
958 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
959 return X86EMUL_CONTINUE;
960 exception:
961 emulate_exception(ctxt, err_vec, err_code, true);
962 return X86EMUL_PROPAGATE_FAULT;
963 }
964
965 static inline int writeback(struct x86_emulate_ctxt *ctxt,
966 struct x86_emulate_ops *ops)
967 {
968 int rc;
969 struct decode_cache *c = &ctxt->decode;
970 u32 err;
971
972 switch (c->dst.type) {
973 case OP_REG:
974 /* The 4-byte case *is* correct:
975 * in 64-bit mode we zero-extend.
976 */
977 switch (c->dst.bytes) {
978 case 1:
979 *(u8 *)c->dst.ptr = (u8)c->dst.val;
980 break;
981 case 2:
982 *(u16 *)c->dst.ptr = (u16)c->dst.val;
983 break;
984 case 4:
985 *c->dst.ptr = (u32)c->dst.val;
986 break; /* 64b: zero-ext */
987 case 8:
988 *c->dst.ptr = c->dst.val;
989 break;
990 }
991 break;
992 case OP_MEM:
993 if (c->lock_prefix)
994 rc = ops->cmpxchg_emulated(
995 (unsigned long)c->dst.ptr,
996 &c->dst.orig_val,
997 &c->dst.val,
998 c->dst.bytes,
999 &err,
1000 ctxt->vcpu);
1001 else
1002 rc = ops->write_emulated(
1003 (unsigned long)c->dst.ptr,
1004 &c->dst.val,
1005 c->dst.bytes,
1006 &err,
1007 ctxt->vcpu);
1008 if (rc == X86EMUL_PROPAGATE_FAULT)
1009 emulate_pf(ctxt,
1010 (unsigned long)c->dst.ptr, err);
1011 if (rc != X86EMUL_CONTINUE)
1012 return rc;
1013 break;
1014 case OP_NONE:
1015 /* no writeback */
1016 break;
1017 default:
1018 break;
1019 }
1020 return X86EMUL_CONTINUE;
1021 }
1022
1023 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1024 struct x86_emulate_ops *ops)
1025 {
1026 struct decode_cache *c = &ctxt->decode;
1027
1028 c->dst.type = OP_MEM;
1029 c->dst.bytes = c->op_bytes;
1030 c->dst.val = c->src.val;
1031 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1032 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
1033 c->regs[VCPU_REGS_RSP]);
1034 }
1035
1036 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 void *dest, int len)
1039 {
1040 struct decode_cache *c = &ctxt->decode;
1041 int rc;
1042
1043 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1044 c->regs[VCPU_REGS_RSP]),
1045 dest, len);
1046 if (rc != X86EMUL_CONTINUE)
1047 return rc;
1048
1049 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1050 return rc;
1051 }
1052
1053 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1054 struct x86_emulate_ops *ops,
1055 void *dest, int len)
1056 {
1057 int rc;
1058 unsigned long val, change_mask;
1059 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1060 int cpl = ops->cpl(ctxt->vcpu);
1061
1062 rc = emulate_pop(ctxt, ops, &val, len);
1063 if (rc != X86EMUL_CONTINUE)
1064 return rc;
1065
1066 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1067 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1068
1069 switch(ctxt->mode) {
1070 case X86EMUL_MODE_PROT64:
1071 case X86EMUL_MODE_PROT32:
1072 case X86EMUL_MODE_PROT16:
1073 if (cpl == 0)
1074 change_mask |= EFLG_IOPL;
1075 if (cpl <= iopl)
1076 change_mask |= EFLG_IF;
1077 break;
1078 case X86EMUL_MODE_VM86:
1079 if (iopl < 3) {
1080 emulate_gp(ctxt, 0);
1081 return X86EMUL_PROPAGATE_FAULT;
1082 }
1083 change_mask |= EFLG_IF;
1084 break;
1085 default: /* real mode */
1086 change_mask |= (EFLG_IOPL | EFLG_IF);
1087 break;
1088 }
1089
1090 *(unsigned long *)dest =
1091 (ctxt->eflags & ~change_mask) | (val & change_mask);
1092
1093 return rc;
1094 }
1095
1096 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1097 struct x86_emulate_ops *ops, int seg)
1098 {
1099 struct decode_cache *c = &ctxt->decode;
1100
1101 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1102
1103 emulate_push(ctxt, ops);
1104 }
1105
1106 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1107 struct x86_emulate_ops *ops, int seg)
1108 {
1109 struct decode_cache *c = &ctxt->decode;
1110 unsigned long selector;
1111 int rc;
1112
1113 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1114 if (rc != X86EMUL_CONTINUE)
1115 return rc;
1116
1117 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1118 return rc;
1119 }
1120
1121 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1122 struct x86_emulate_ops *ops)
1123 {
1124 struct decode_cache *c = &ctxt->decode;
1125 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1126 int rc = X86EMUL_CONTINUE;
1127 int reg = VCPU_REGS_RAX;
1128
1129 while (reg <= VCPU_REGS_RDI) {
1130 (reg == VCPU_REGS_RSP) ?
1131 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1132
1133 emulate_push(ctxt, ops);
1134
1135 rc = writeback(ctxt, ops);
1136 if (rc != X86EMUL_CONTINUE)
1137 return rc;
1138
1139 ++reg;
1140 }
1141
1142 /* Disable writeback. */
1143 c->dst.type = OP_NONE;
1144
1145 return rc;
1146 }
1147
1148 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1149 struct x86_emulate_ops *ops)
1150 {
1151 struct decode_cache *c = &ctxt->decode;
1152 int rc = X86EMUL_CONTINUE;
1153 int reg = VCPU_REGS_RDI;
1154
1155 while (reg >= VCPU_REGS_RAX) {
1156 if (reg == VCPU_REGS_RSP) {
1157 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1158 c->op_bytes);
1159 --reg;
1160 }
1161
1162 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1163 if (rc != X86EMUL_CONTINUE)
1164 break;
1165 --reg;
1166 }
1167 return rc;
1168 }
1169
1170 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1171 struct x86_emulate_ops *ops)
1172 {
1173 struct decode_cache *c = &ctxt->decode;
1174 int rc = X86EMUL_CONTINUE;
1175 unsigned long temp_eip = 0;
1176 unsigned long temp_eflags = 0;
1177 unsigned long cs = 0;
1178 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1179 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1180 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1181 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1182
1183 /* TODO: Add stack limit check */
1184
1185 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1186
1187 if (rc != X86EMUL_CONTINUE)
1188 return rc;
1189
1190 if (temp_eip & ~0xffff) {
1191 emulate_gp(ctxt, 0);
1192 return X86EMUL_PROPAGATE_FAULT;
1193 }
1194
1195 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1196
1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
1199
1200 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1201
1202 if (rc != X86EMUL_CONTINUE)
1203 return rc;
1204
1205 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1206
1207 if (rc != X86EMUL_CONTINUE)
1208 return rc;
1209
1210 c->eip = temp_eip;
1211
1212
1213 if (c->op_bytes == 4)
1214 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1215 else if (c->op_bytes == 2) {
1216 ctxt->eflags &= ~0xffff;
1217 ctxt->eflags |= temp_eflags;
1218 }
1219
1220 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1221 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1222
1223 return rc;
1224 }
1225
1226 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1227 struct x86_emulate_ops* ops)
1228 {
1229 switch(ctxt->mode) {
1230 case X86EMUL_MODE_REAL:
1231 return emulate_iret_real(ctxt, ops);
1232 case X86EMUL_MODE_VM86:
1233 case X86EMUL_MODE_PROT16:
1234 case X86EMUL_MODE_PROT32:
1235 case X86EMUL_MODE_PROT64:
1236 default:
1237 /* iret from protected mode unimplemented yet */
1238 return X86EMUL_UNHANDLEABLE;
1239 }
1240 }
1241
1242 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1243 struct x86_emulate_ops *ops)
1244 {
1245 struct decode_cache *c = &ctxt->decode;
1246
1247 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1248 }
1249
1250 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1251 {
1252 struct decode_cache *c = &ctxt->decode;
1253 switch (c->modrm_reg) {
1254 case 0: /* rol */
1255 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1256 break;
1257 case 1: /* ror */
1258 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1259 break;
1260 case 2: /* rcl */
1261 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1262 break;
1263 case 3: /* rcr */
1264 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1265 break;
1266 case 4: /* sal/shl */
1267 case 6: /* sal/shl */
1268 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1269 break;
1270 case 5: /* shr */
1271 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1272 break;
1273 case 7: /* sar */
1274 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1275 break;
1276 }
1277 }
1278
1279 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1280 struct x86_emulate_ops *ops)
1281 {
1282 struct decode_cache *c = &ctxt->decode;
1283
1284 switch (c->modrm_reg) {
1285 case 0 ... 1: /* test */
1286 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1287 break;
1288 case 2: /* not */
1289 c->dst.val = ~c->dst.val;
1290 break;
1291 case 3: /* neg */
1292 emulate_1op("neg", c->dst, ctxt->eflags);
1293 break;
1294 default:
1295 return 0;
1296 }
1297 return 1;
1298 }
1299
1300 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1301 struct x86_emulate_ops *ops)
1302 {
1303 struct decode_cache *c = &ctxt->decode;
1304
1305 switch (c->modrm_reg) {
1306 case 0: /* inc */
1307 emulate_1op("inc", c->dst, ctxt->eflags);
1308 break;
1309 case 1: /* dec */
1310 emulate_1op("dec", c->dst, ctxt->eflags);
1311 break;
1312 case 2: /* call near abs */ {
1313 long int old_eip;
1314 old_eip = c->eip;
1315 c->eip = c->src.val;
1316 c->src.val = old_eip;
1317 emulate_push(ctxt, ops);
1318 break;
1319 }
1320 case 4: /* jmp abs */
1321 c->eip = c->src.val;
1322 break;
1323 case 6: /* push */
1324 emulate_push(ctxt, ops);
1325 break;
1326 }
1327 return X86EMUL_CONTINUE;
1328 }
1329
1330 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1331 struct x86_emulate_ops *ops)
1332 {
1333 struct decode_cache *c = &ctxt->decode;
1334 u64 old = c->dst.orig_val64;
1335
1336 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1337 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1338 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1339 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1340 ctxt->eflags &= ~EFLG_ZF;
1341 } else {
1342 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1343 (u32) c->regs[VCPU_REGS_RBX];
1344
1345 ctxt->eflags |= EFLG_ZF;
1346 }
1347 return X86EMUL_CONTINUE;
1348 }
1349
1350 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1351 struct x86_emulate_ops *ops)
1352 {
1353 struct decode_cache *c = &ctxt->decode;
1354 int rc;
1355 unsigned long cs;
1356
1357 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1358 if (rc != X86EMUL_CONTINUE)
1359 return rc;
1360 if (c->op_bytes == 4)
1361 c->eip = (u32)c->eip;
1362 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1363 if (rc != X86EMUL_CONTINUE)
1364 return rc;
1365 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1366 return rc;
1367 }
1368
1369 static inline void
1370 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1371 struct x86_emulate_ops *ops, struct desc_struct *cs,
1372 struct desc_struct *ss)
1373 {
1374 memset(cs, 0, sizeof(struct desc_struct));
1375 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1376 memset(ss, 0, sizeof(struct desc_struct));
1377
1378 cs->l = 0; /* will be adjusted later */
1379 set_desc_base(cs, 0); /* flat segment */
1380 cs->g = 1; /* 4kb granularity */
1381 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1382 cs->type = 0x0b; /* Read, Execute, Accessed */
1383 cs->s = 1;
1384 cs->dpl = 0; /* will be adjusted later */
1385 cs->p = 1;
1386 cs->d = 1;
1387
1388 set_desc_base(ss, 0); /* flat segment */
1389 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1390 ss->g = 1; /* 4kb granularity */
1391 ss->s = 1;
1392 ss->type = 0x03; /* Read/Write, Accessed */
1393 ss->d = 1; /* 32bit stack segment */
1394 ss->dpl = 0;
1395 ss->p = 1;
1396 }
1397
1398 static int
1399 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1400 {
1401 struct decode_cache *c = &ctxt->decode;
1402 struct desc_struct cs, ss;
1403 u64 msr_data;
1404 u16 cs_sel, ss_sel;
1405
1406 /* syscall is not available in real mode */
1407 if (ctxt->mode == X86EMUL_MODE_REAL ||
1408 ctxt->mode == X86EMUL_MODE_VM86) {
1409 emulate_ud(ctxt);
1410 return X86EMUL_PROPAGATE_FAULT;
1411 }
1412
1413 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1414
1415 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1416 msr_data >>= 32;
1417 cs_sel = (u16)(msr_data & 0xfffc);
1418 ss_sel = (u16)(msr_data + 8);
1419
1420 if (is_long_mode(ctxt->vcpu)) {
1421 cs.d = 0;
1422 cs.l = 1;
1423 }
1424 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1425 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1426 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1427 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1428
1429 c->regs[VCPU_REGS_RCX] = c->eip;
1430 if (is_long_mode(ctxt->vcpu)) {
1431 #ifdef CONFIG_X86_64
1432 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1433
1434 ops->get_msr(ctxt->vcpu,
1435 ctxt->mode == X86EMUL_MODE_PROT64 ?
1436 MSR_LSTAR : MSR_CSTAR, &msr_data);
1437 c->eip = msr_data;
1438
1439 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1440 ctxt->eflags &= ~(msr_data | EFLG_RF);
1441 #endif
1442 } else {
1443 /* legacy mode */
1444 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1445 c->eip = (u32)msr_data;
1446
1447 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1448 }
1449
1450 return X86EMUL_CONTINUE;
1451 }
1452
1453 static int
1454 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1455 {
1456 struct decode_cache *c = &ctxt->decode;
1457 struct desc_struct cs, ss;
1458 u64 msr_data;
1459 u16 cs_sel, ss_sel;
1460
1461 /* inject #GP if in real mode */
1462 if (ctxt->mode == X86EMUL_MODE_REAL) {
1463 emulate_gp(ctxt, 0);
1464 return X86EMUL_PROPAGATE_FAULT;
1465 }
1466
1467 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1468 * Therefore, we inject an #UD.
1469 */
1470 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1471 emulate_ud(ctxt);
1472 return X86EMUL_PROPAGATE_FAULT;
1473 }
1474
1475 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1476
1477 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1478 switch (ctxt->mode) {
1479 case X86EMUL_MODE_PROT32:
1480 if ((msr_data & 0xfffc) == 0x0) {
1481 emulate_gp(ctxt, 0);
1482 return X86EMUL_PROPAGATE_FAULT;
1483 }
1484 break;
1485 case X86EMUL_MODE_PROT64:
1486 if (msr_data == 0x0) {
1487 emulate_gp(ctxt, 0);
1488 return X86EMUL_PROPAGATE_FAULT;
1489 }
1490 break;
1491 }
1492
1493 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1494 cs_sel = (u16)msr_data;
1495 cs_sel &= ~SELECTOR_RPL_MASK;
1496 ss_sel = cs_sel + 8;
1497 ss_sel &= ~SELECTOR_RPL_MASK;
1498 if (ctxt->mode == X86EMUL_MODE_PROT64
1499 || is_long_mode(ctxt->vcpu)) {
1500 cs.d = 0;
1501 cs.l = 1;
1502 }
1503
1504 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1505 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1506 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1507 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1508
1509 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1510 c->eip = msr_data;
1511
1512 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1513 c->regs[VCPU_REGS_RSP] = msr_data;
1514
1515 return X86EMUL_CONTINUE;
1516 }
1517
1518 static int
1519 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1520 {
1521 struct decode_cache *c = &ctxt->decode;
1522 struct desc_struct cs, ss;
1523 u64 msr_data;
1524 int usermode;
1525 u16 cs_sel, ss_sel;
1526
1527 /* inject #GP if in real mode or Virtual 8086 mode */
1528 if (ctxt->mode == X86EMUL_MODE_REAL ||
1529 ctxt->mode == X86EMUL_MODE_VM86) {
1530 emulate_gp(ctxt, 0);
1531 return X86EMUL_PROPAGATE_FAULT;
1532 }
1533
1534 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1535
1536 if ((c->rex_prefix & 0x8) != 0x0)
1537 usermode = X86EMUL_MODE_PROT64;
1538 else
1539 usermode = X86EMUL_MODE_PROT32;
1540
1541 cs.dpl = 3;
1542 ss.dpl = 3;
1543 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1544 switch (usermode) {
1545 case X86EMUL_MODE_PROT32:
1546 cs_sel = (u16)(msr_data + 16);
1547 if ((msr_data & 0xfffc) == 0x0) {
1548 emulate_gp(ctxt, 0);
1549 return X86EMUL_PROPAGATE_FAULT;
1550 }
1551 ss_sel = (u16)(msr_data + 24);
1552 break;
1553 case X86EMUL_MODE_PROT64:
1554 cs_sel = (u16)(msr_data + 32);
1555 if (msr_data == 0x0) {
1556 emulate_gp(ctxt, 0);
1557 return X86EMUL_PROPAGATE_FAULT;
1558 }
1559 ss_sel = cs_sel + 8;
1560 cs.d = 0;
1561 cs.l = 1;
1562 break;
1563 }
1564 cs_sel |= SELECTOR_RPL_MASK;
1565 ss_sel |= SELECTOR_RPL_MASK;
1566
1567 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1568 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1569 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1570 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1571
1572 c->eip = c->regs[VCPU_REGS_RDX];
1573 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1574
1575 return X86EMUL_CONTINUE;
1576 }
1577
1578 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1579 struct x86_emulate_ops *ops)
1580 {
1581 int iopl;
1582 if (ctxt->mode == X86EMUL_MODE_REAL)
1583 return false;
1584 if (ctxt->mode == X86EMUL_MODE_VM86)
1585 return true;
1586 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1587 return ops->cpl(ctxt->vcpu) > iopl;
1588 }
1589
1590 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1591 struct x86_emulate_ops *ops,
1592 u16 port, u16 len)
1593 {
1594 struct desc_struct tr_seg;
1595 int r;
1596 u16 io_bitmap_ptr;
1597 u8 perm, bit_idx = port & 0x7;
1598 unsigned mask = (1 << len) - 1;
1599
1600 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1601 if (!tr_seg.p)
1602 return false;
1603 if (desc_limit_scaled(&tr_seg) < 103)
1604 return false;
1605 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1606 ctxt->vcpu, NULL);
1607 if (r != X86EMUL_CONTINUE)
1608 return false;
1609 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1610 return false;
1611 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1612 &perm, 1, ctxt->vcpu, NULL);
1613 if (r != X86EMUL_CONTINUE)
1614 return false;
1615 if ((perm >> bit_idx) & mask)
1616 return false;
1617 return true;
1618 }
1619
1620 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1621 struct x86_emulate_ops *ops,
1622 u16 port, u16 len)
1623 {
1624 if (ctxt->perm_ok)
1625 return true;
1626
1627 if (emulator_bad_iopl(ctxt, ops))
1628 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1629 return false;
1630
1631 ctxt->perm_ok = true;
1632
1633 return true;
1634 }
1635
1636 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1637 struct x86_emulate_ops *ops,
1638 struct tss_segment_16 *tss)
1639 {
1640 struct decode_cache *c = &ctxt->decode;
1641
1642 tss->ip = c->eip;
1643 tss->flag = ctxt->eflags;
1644 tss->ax = c->regs[VCPU_REGS_RAX];
1645 tss->cx = c->regs[VCPU_REGS_RCX];
1646 tss->dx = c->regs[VCPU_REGS_RDX];
1647 tss->bx = c->regs[VCPU_REGS_RBX];
1648 tss->sp = c->regs[VCPU_REGS_RSP];
1649 tss->bp = c->regs[VCPU_REGS_RBP];
1650 tss->si = c->regs[VCPU_REGS_RSI];
1651 tss->di = c->regs[VCPU_REGS_RDI];
1652
1653 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1654 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1655 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1656 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1657 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1658 }
1659
1660 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1661 struct x86_emulate_ops *ops,
1662 struct tss_segment_16 *tss)
1663 {
1664 struct decode_cache *c = &ctxt->decode;
1665 int ret;
1666
1667 c->eip = tss->ip;
1668 ctxt->eflags = tss->flag | 2;
1669 c->regs[VCPU_REGS_RAX] = tss->ax;
1670 c->regs[VCPU_REGS_RCX] = tss->cx;
1671 c->regs[VCPU_REGS_RDX] = tss->dx;
1672 c->regs[VCPU_REGS_RBX] = tss->bx;
1673 c->regs[VCPU_REGS_RSP] = tss->sp;
1674 c->regs[VCPU_REGS_RBP] = tss->bp;
1675 c->regs[VCPU_REGS_RSI] = tss->si;
1676 c->regs[VCPU_REGS_RDI] = tss->di;
1677
1678 /*
1679 * SDM says that segment selectors are loaded before segment
1680 * descriptors
1681 */
1682 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1683 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1684 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1685 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1686 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1687
1688 /*
1689 * Now load segment descriptors. If fault happenes at this stage
1690 * it is handled in a context of new task
1691 */
1692 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1693 if (ret != X86EMUL_CONTINUE)
1694 return ret;
1695 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1696 if (ret != X86EMUL_CONTINUE)
1697 return ret;
1698 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1699 if (ret != X86EMUL_CONTINUE)
1700 return ret;
1701 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1702 if (ret != X86EMUL_CONTINUE)
1703 return ret;
1704 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1705 if (ret != X86EMUL_CONTINUE)
1706 return ret;
1707
1708 return X86EMUL_CONTINUE;
1709 }
1710
1711 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1712 struct x86_emulate_ops *ops,
1713 u16 tss_selector, u16 old_tss_sel,
1714 ulong old_tss_base, struct desc_struct *new_desc)
1715 {
1716 struct tss_segment_16 tss_seg;
1717 int ret;
1718 u32 err, new_tss_base = get_desc_base(new_desc);
1719
1720 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1721 &err);
1722 if (ret == X86EMUL_PROPAGATE_FAULT) {
1723 /* FIXME: need to provide precise fault address */
1724 emulate_pf(ctxt, old_tss_base, err);
1725 return ret;
1726 }
1727
1728 save_state_to_tss16(ctxt, ops, &tss_seg);
1729
1730 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1731 &err);
1732 if (ret == X86EMUL_PROPAGATE_FAULT) {
1733 /* FIXME: need to provide precise fault address */
1734 emulate_pf(ctxt, old_tss_base, err);
1735 return ret;
1736 }
1737
1738 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1739 &err);
1740 if (ret == X86EMUL_PROPAGATE_FAULT) {
1741 /* FIXME: need to provide precise fault address */
1742 emulate_pf(ctxt, new_tss_base, err);
1743 return ret;
1744 }
1745
1746 if (old_tss_sel != 0xffff) {
1747 tss_seg.prev_task_link = old_tss_sel;
1748
1749 ret = ops->write_std(new_tss_base,
1750 &tss_seg.prev_task_link,
1751 sizeof tss_seg.prev_task_link,
1752 ctxt->vcpu, &err);
1753 if (ret == X86EMUL_PROPAGATE_FAULT) {
1754 /* FIXME: need to provide precise fault address */
1755 emulate_pf(ctxt, new_tss_base, err);
1756 return ret;
1757 }
1758 }
1759
1760 return load_state_from_tss16(ctxt, ops, &tss_seg);
1761 }
1762
1763 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1764 struct x86_emulate_ops *ops,
1765 struct tss_segment_32 *tss)
1766 {
1767 struct decode_cache *c = &ctxt->decode;
1768
1769 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1770 tss->eip = c->eip;
1771 tss->eflags = ctxt->eflags;
1772 tss->eax = c->regs[VCPU_REGS_RAX];
1773 tss->ecx = c->regs[VCPU_REGS_RCX];
1774 tss->edx = c->regs[VCPU_REGS_RDX];
1775 tss->ebx = c->regs[VCPU_REGS_RBX];
1776 tss->esp = c->regs[VCPU_REGS_RSP];
1777 tss->ebp = c->regs[VCPU_REGS_RBP];
1778 tss->esi = c->regs[VCPU_REGS_RSI];
1779 tss->edi = c->regs[VCPU_REGS_RDI];
1780
1781 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1782 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1783 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1784 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1785 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1786 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1787 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1788 }
1789
1790 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1791 struct x86_emulate_ops *ops,
1792 struct tss_segment_32 *tss)
1793 {
1794 struct decode_cache *c = &ctxt->decode;
1795 int ret;
1796
1797 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1798 emulate_gp(ctxt, 0);
1799 return X86EMUL_PROPAGATE_FAULT;
1800 }
1801 c->eip = tss->eip;
1802 ctxt->eflags = tss->eflags | 2;
1803 c->regs[VCPU_REGS_RAX] = tss->eax;
1804 c->regs[VCPU_REGS_RCX] = tss->ecx;
1805 c->regs[VCPU_REGS_RDX] = tss->edx;
1806 c->regs[VCPU_REGS_RBX] = tss->ebx;
1807 c->regs[VCPU_REGS_RSP] = tss->esp;
1808 c->regs[VCPU_REGS_RBP] = tss->ebp;
1809 c->regs[VCPU_REGS_RSI] = tss->esi;
1810 c->regs[VCPU_REGS_RDI] = tss->edi;
1811
1812 /*
1813 * SDM says that segment selectors are loaded before segment
1814 * descriptors
1815 */
1816 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1817 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1818 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1819 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1820 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1821 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1822 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1823
1824 /*
1825 * Now load segment descriptors. If fault happenes at this stage
1826 * it is handled in a context of new task
1827 */
1828 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1829 if (ret != X86EMUL_CONTINUE)
1830 return ret;
1831 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1832 if (ret != X86EMUL_CONTINUE)
1833 return ret;
1834 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1835 if (ret != X86EMUL_CONTINUE)
1836 return ret;
1837 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1838 if (ret != X86EMUL_CONTINUE)
1839 return ret;
1840 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1841 if (ret != X86EMUL_CONTINUE)
1842 return ret;
1843 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1844 if (ret != X86EMUL_CONTINUE)
1845 return ret;
1846 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1847 if (ret != X86EMUL_CONTINUE)
1848 return ret;
1849
1850 return X86EMUL_CONTINUE;
1851 }
1852
1853 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
1854 struct x86_emulate_ops *ops,
1855 u16 tss_selector, u16 old_tss_sel,
1856 ulong old_tss_base, struct desc_struct *new_desc)
1857 {
1858 struct tss_segment_32 tss_seg;
1859 int ret;
1860 u32 err, new_tss_base = get_desc_base(new_desc);
1861
1862 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1863 &err);
1864 if (ret == X86EMUL_PROPAGATE_FAULT) {
1865 /* FIXME: need to provide precise fault address */
1866 emulate_pf(ctxt, old_tss_base, err);
1867 return ret;
1868 }
1869
1870 save_state_to_tss32(ctxt, ops, &tss_seg);
1871
1872 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1873 &err);
1874 if (ret == X86EMUL_PROPAGATE_FAULT) {
1875 /* FIXME: need to provide precise fault address */
1876 emulate_pf(ctxt, old_tss_base, err);
1877 return ret;
1878 }
1879
1880 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1881 &err);
1882 if (ret == X86EMUL_PROPAGATE_FAULT) {
1883 /* FIXME: need to provide precise fault address */
1884 emulate_pf(ctxt, new_tss_base, err);
1885 return ret;
1886 }
1887
1888 if (old_tss_sel != 0xffff) {
1889 tss_seg.prev_task_link = old_tss_sel;
1890
1891 ret = ops->write_std(new_tss_base,
1892 &tss_seg.prev_task_link,
1893 sizeof tss_seg.prev_task_link,
1894 ctxt->vcpu, &err);
1895 if (ret == X86EMUL_PROPAGATE_FAULT) {
1896 /* FIXME: need to provide precise fault address */
1897 emulate_pf(ctxt, new_tss_base, err);
1898 return ret;
1899 }
1900 }
1901
1902 return load_state_from_tss32(ctxt, ops, &tss_seg);
1903 }
1904
1905 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
1906 struct x86_emulate_ops *ops,
1907 u16 tss_selector, int reason,
1908 bool has_error_code, u32 error_code)
1909 {
1910 struct desc_struct curr_tss_desc, next_tss_desc;
1911 int ret;
1912 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
1913 ulong old_tss_base =
1914 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
1915 u32 desc_limit;
1916
1917 /* FIXME: old_tss_base == ~0 ? */
1918
1919 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
1920 if (ret != X86EMUL_CONTINUE)
1921 return ret;
1922 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
1923 if (ret != X86EMUL_CONTINUE)
1924 return ret;
1925
1926 /* FIXME: check that next_tss_desc is tss */
1927
1928 if (reason != TASK_SWITCH_IRET) {
1929 if ((tss_selector & 3) > next_tss_desc.dpl ||
1930 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
1931 emulate_gp(ctxt, 0);
1932 return X86EMUL_PROPAGATE_FAULT;
1933 }
1934 }
1935
1936 desc_limit = desc_limit_scaled(&next_tss_desc);
1937 if (!next_tss_desc.p ||
1938 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
1939 desc_limit < 0x2b)) {
1940 emulate_ts(ctxt, tss_selector & 0xfffc);
1941 return X86EMUL_PROPAGATE_FAULT;
1942 }
1943
1944 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
1945 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
1946 write_segment_descriptor(ctxt, ops, old_tss_sel,
1947 &curr_tss_desc);
1948 }
1949
1950 if (reason == TASK_SWITCH_IRET)
1951 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
1952
1953 /* set back link to prev task only if NT bit is set in eflags
1954 note that old_tss_sel is not used afetr this point */
1955 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
1956 old_tss_sel = 0xffff;
1957
1958 if (next_tss_desc.type & 8)
1959 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
1960 old_tss_base, &next_tss_desc);
1961 else
1962 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
1963 old_tss_base, &next_tss_desc);
1964 if (ret != X86EMUL_CONTINUE)
1965 return ret;
1966
1967 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
1968 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
1969
1970 if (reason != TASK_SWITCH_IRET) {
1971 next_tss_desc.type |= (1 << 1); /* set busy flag */
1972 write_segment_descriptor(ctxt, ops, tss_selector,
1973 &next_tss_desc);
1974 }
1975
1976 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
1977 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
1978 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
1979
1980 if (has_error_code) {
1981 struct decode_cache *c = &ctxt->decode;
1982
1983 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
1984 c->lock_prefix = 0;
1985 c->src.val = (unsigned long) error_code;
1986 emulate_push(ctxt, ops);
1987 }
1988
1989 return ret;
1990 }
1991
1992 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
1993 u16 tss_selector, int reason,
1994 bool has_error_code, u32 error_code)
1995 {
1996 struct x86_emulate_ops *ops = ctxt->ops;
1997 struct decode_cache *c = &ctxt->decode;
1998 int rc;
1999
2000 c->eip = ctxt->eip;
2001 c->dst.type = OP_NONE;
2002
2003 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2004 has_error_code, error_code);
2005
2006 if (rc == X86EMUL_CONTINUE) {
2007 rc = writeback(ctxt, ops);
2008 if (rc == X86EMUL_CONTINUE)
2009 ctxt->eip = c->eip;
2010 }
2011
2012 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2013 }
2014
2015 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2016 int reg, struct operand *op)
2017 {
2018 struct decode_cache *c = &ctxt->decode;
2019 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2020
2021 register_address_increment(c, &c->regs[reg], df * op->bytes);
2022 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
2023 }
2024
2025 static int em_push(struct x86_emulate_ctxt *ctxt)
2026 {
2027 emulate_push(ctxt, ctxt->ops);
2028 return X86EMUL_CONTINUE;
2029 }
2030
2031 #define D(_y) { .flags = (_y) }
2032 #define N D(0)
2033 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2034 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2035 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2036
2037 static struct opcode group1[] = {
2038 X7(D(Lock)), N
2039 };
2040
2041 static struct opcode group1A[] = {
2042 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2043 };
2044
2045 static struct opcode group3[] = {
2046 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2047 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2048 X4(D(Undefined)),
2049 };
2050
2051 static struct opcode group4[] = {
2052 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2053 N, N, N, N, N, N,
2054 };
2055
2056 static struct opcode group5[] = {
2057 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2058 D(SrcMem | ModRM | Stack), N,
2059 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2060 D(SrcMem | ModRM | Stack), N,
2061 };
2062
2063 static struct group_dual group7 = { {
2064 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2065 D(SrcNone | ModRM | DstMem | Mov), N,
2066 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2067 }, {
2068 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2069 D(SrcNone | ModRM | DstMem | Mov), N,
2070 D(SrcMem16 | ModRM | Mov | Priv), N,
2071 } };
2072
2073 static struct opcode group8[] = {
2074 N, N, N, N,
2075 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2076 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2077 };
2078
2079 static struct group_dual group9 = { {
2080 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2081 }, {
2082 N, N, N, N, N, N, N, N,
2083 } };
2084
2085 static struct opcode opcode_table[256] = {
2086 /* 0x00 - 0x07 */
2087 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2088 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2089 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2090 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2091 /* 0x08 - 0x0F */
2092 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2093 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2094 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2095 D(ImplicitOps | Stack | No64), N,
2096 /* 0x10 - 0x17 */
2097 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2098 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2099 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2100 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2101 /* 0x18 - 0x1F */
2102 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2103 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2104 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2105 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2106 /* 0x20 - 0x27 */
2107 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2108 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2109 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2110 /* 0x28 - 0x2F */
2111 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2112 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2113 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2114 /* 0x30 - 0x37 */
2115 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2116 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2117 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2118 /* 0x38 - 0x3F */
2119 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2120 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2121 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2122 N, N,
2123 /* 0x40 - 0x4F */
2124 X16(D(DstReg)),
2125 /* 0x50 - 0x57 */
2126 X8(I(SrcReg | Stack, em_push)),
2127 /* 0x58 - 0x5F */
2128 X8(D(DstReg | Stack)),
2129 /* 0x60 - 0x67 */
2130 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2131 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2132 N, N, N, N,
2133 /* 0x68 - 0x6F */
2134 I(SrcImm | Mov | Stack, em_push), N,
2135 I(SrcImmByte | Mov | Stack, em_push), N,
2136 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2137 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2138 /* 0x70 - 0x7F */
2139 X16(D(SrcImmByte)),
2140 /* 0x80 - 0x87 */
2141 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2142 G(DstMem | SrcImm | ModRM | Group, group1),
2143 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2144 G(DstMem | SrcImmByte | ModRM | Group, group1),
2145 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2146 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2147 /* 0x88 - 0x8F */
2148 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2149 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2150 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
2151 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2152 /* 0x90 - 0x97 */
2153 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
2154 /* 0x98 - 0x9F */
2155 N, N, D(SrcImmFAddr | No64), N,
2156 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2157 /* 0xA0 - 0xA7 */
2158 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2159 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2160 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2161 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2162 /* 0xA8 - 0xAF */
2163 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
2164 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2165 D(ByteOp | DstDI | String), D(DstDI | String),
2166 /* 0xB0 - 0xB7 */
2167 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2168 /* 0xB8 - 0xBF */
2169 X8(D(DstReg | SrcImm | Mov)),
2170 /* 0xC0 - 0xC7 */
2171 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2172 N, D(ImplicitOps | Stack), N, N,
2173 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2174 /* 0xC8 - 0xCF */
2175 N, N, N, D(ImplicitOps | Stack),
2176 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2177 /* 0xD0 - 0xD7 */
2178 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2179 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2180 N, N, N, N,
2181 /* 0xD8 - 0xDF */
2182 N, N, N, N, N, N, N, N,
2183 /* 0xE0 - 0xE7 */
2184 N, N, N, N,
2185 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2186 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2187 /* 0xE8 - 0xEF */
2188 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2189 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2190 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2191 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2192 /* 0xF0 - 0xF7 */
2193 N, N, N, N,
2194 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2195 /* 0xF8 - 0xFF */
2196 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
2197 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2198 };
2199
2200 static struct opcode twobyte_table[256] = {
2201 /* 0x00 - 0x0F */
2202 N, GD(0, &group7), N, N,
2203 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2204 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2205 N, D(ImplicitOps | ModRM), N, N,
2206 /* 0x10 - 0x1F */
2207 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2208 /* 0x20 - 0x2F */
2209 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2210 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2211 N, N, N, N,
2212 N, N, N, N, N, N, N, N,
2213 /* 0x30 - 0x3F */
2214 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2215 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2216 N, N, N, N, N, N, N, N,
2217 /* 0x40 - 0x4F */
2218 X16(D(DstReg | SrcMem | ModRM | Mov)),
2219 /* 0x50 - 0x5F */
2220 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2221 /* 0x60 - 0x6F */
2222 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2223 /* 0x70 - 0x7F */
2224 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2225 /* 0x80 - 0x8F */
2226 X16(D(SrcImm)),
2227 /* 0x90 - 0x9F */
2228 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2229 /* 0xA0 - 0xA7 */
2230 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2231 N, D(DstMem | SrcReg | ModRM | BitOp),
2232 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2233 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2234 /* 0xA8 - 0xAF */
2235 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2236 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2237 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2238 D(DstMem | SrcReg | Src2CL | ModRM),
2239 D(ModRM), N,
2240 /* 0xB0 - 0xB7 */
2241 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2242 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2243 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2244 D(DstReg | SrcMem16 | ModRM | Mov),
2245 /* 0xB8 - 0xBF */
2246 N, N,
2247 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2248 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2249 D(DstReg | SrcMem16 | ModRM | Mov),
2250 /* 0xC0 - 0xCF */
2251 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
2252 N, N, N, GD(0, &group9),
2253 N, N, N, N, N, N, N, N,
2254 /* 0xD0 - 0xDF */
2255 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2256 /* 0xE0 - 0xEF */
2257 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2258 /* 0xF0 - 0xFF */
2259 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2260 };
2261
2262 #undef D
2263 #undef N
2264 #undef G
2265 #undef GD
2266 #undef I
2267
2268 int
2269 x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2270 {
2271 struct x86_emulate_ops *ops = ctxt->ops;
2272 struct decode_cache *c = &ctxt->decode;
2273 int rc = X86EMUL_CONTINUE;
2274 int mode = ctxt->mode;
2275 int def_op_bytes, def_ad_bytes, dual, goffset;
2276 struct opcode opcode, *g_mod012, *g_mod3;
2277
2278 /* we cannot decode insn before we complete previous rep insn */
2279 WARN_ON(ctxt->restart);
2280
2281 c->eip = ctxt->eip;
2282 c->fetch.start = c->fetch.end = c->eip;
2283 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2284
2285 switch (mode) {
2286 case X86EMUL_MODE_REAL:
2287 case X86EMUL_MODE_VM86:
2288 case X86EMUL_MODE_PROT16:
2289 def_op_bytes = def_ad_bytes = 2;
2290 break;
2291 case X86EMUL_MODE_PROT32:
2292 def_op_bytes = def_ad_bytes = 4;
2293 break;
2294 #ifdef CONFIG_X86_64
2295 case X86EMUL_MODE_PROT64:
2296 def_op_bytes = 4;
2297 def_ad_bytes = 8;
2298 break;
2299 #endif
2300 default:
2301 return -1;
2302 }
2303
2304 c->op_bytes = def_op_bytes;
2305 c->ad_bytes = def_ad_bytes;
2306
2307 /* Legacy prefixes. */
2308 for (;;) {
2309 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2310 case 0x66: /* operand-size override */
2311 /* switch between 2/4 bytes */
2312 c->op_bytes = def_op_bytes ^ 6;
2313 break;
2314 case 0x67: /* address-size override */
2315 if (mode == X86EMUL_MODE_PROT64)
2316 /* switch between 4/8 bytes */
2317 c->ad_bytes = def_ad_bytes ^ 12;
2318 else
2319 /* switch between 2/4 bytes */
2320 c->ad_bytes = def_ad_bytes ^ 6;
2321 break;
2322 case 0x26: /* ES override */
2323 case 0x2e: /* CS override */
2324 case 0x36: /* SS override */
2325 case 0x3e: /* DS override */
2326 set_seg_override(c, (c->b >> 3) & 3);
2327 break;
2328 case 0x64: /* FS override */
2329 case 0x65: /* GS override */
2330 set_seg_override(c, c->b & 7);
2331 break;
2332 case 0x40 ... 0x4f: /* REX */
2333 if (mode != X86EMUL_MODE_PROT64)
2334 goto done_prefixes;
2335 c->rex_prefix = c->b;
2336 continue;
2337 case 0xf0: /* LOCK */
2338 c->lock_prefix = 1;
2339 break;
2340 case 0xf2: /* REPNE/REPNZ */
2341 c->rep_prefix = REPNE_PREFIX;
2342 break;
2343 case 0xf3: /* REP/REPE/REPZ */
2344 c->rep_prefix = REPE_PREFIX;
2345 break;
2346 default:
2347 goto done_prefixes;
2348 }
2349
2350 /* Any legacy prefix after a REX prefix nullifies its effect. */
2351
2352 c->rex_prefix = 0;
2353 }
2354
2355 done_prefixes:
2356
2357 /* REX prefix. */
2358 if (c->rex_prefix)
2359 if (c->rex_prefix & 8)
2360 c->op_bytes = 8; /* REX.W */
2361
2362 /* Opcode byte(s). */
2363 opcode = opcode_table[c->b];
2364 if (opcode.flags == 0) {
2365 /* Two-byte opcode? */
2366 if (c->b == 0x0f) {
2367 c->twobyte = 1;
2368 c->b = insn_fetch(u8, 1, c->eip);
2369 opcode = twobyte_table[c->b];
2370 }
2371 }
2372 c->d = opcode.flags;
2373
2374 if (c->d & Group) {
2375 dual = c->d & GroupDual;
2376 c->modrm = insn_fetch(u8, 1, c->eip);
2377 --c->eip;
2378
2379 if (c->d & GroupDual) {
2380 g_mod012 = opcode.u.gdual->mod012;
2381 g_mod3 = opcode.u.gdual->mod3;
2382 } else
2383 g_mod012 = g_mod3 = opcode.u.group;
2384
2385 c->d &= ~(Group | GroupDual);
2386
2387 goffset = (c->modrm >> 3) & 7;
2388
2389 if ((c->modrm >> 6) == 3)
2390 opcode = g_mod3[goffset];
2391 else
2392 opcode = g_mod012[goffset];
2393 c->d |= opcode.flags;
2394 }
2395
2396 c->execute = opcode.u.execute;
2397
2398 /* Unrecognised? */
2399 if (c->d == 0 || (c->d & Undefined)) {
2400 DPRINTF("Cannot emulate %02x\n", c->b);
2401 return -1;
2402 }
2403
2404 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2405 c->op_bytes = 8;
2406
2407 /* ModRM and SIB bytes. */
2408 if (c->d & ModRM)
2409 rc = decode_modrm(ctxt, ops);
2410 else if (c->d & MemAbs)
2411 rc = decode_abs(ctxt, ops);
2412 if (rc != X86EMUL_CONTINUE)
2413 goto done;
2414
2415 if (!c->has_seg_override)
2416 set_seg_override(c, VCPU_SREG_DS);
2417
2418 if (!(!c->twobyte && c->b == 0x8d))
2419 c->modrm_ea += seg_override_base(ctxt, ops, c);
2420
2421 if (c->ad_bytes != 8)
2422 c->modrm_ea = (u32)c->modrm_ea;
2423
2424 if (c->rip_relative)
2425 c->modrm_ea += c->eip;
2426
2427 /*
2428 * Decode and fetch the source operand: register, memory
2429 * or immediate.
2430 */
2431 switch (c->d & SrcMask) {
2432 case SrcNone:
2433 break;
2434 case SrcReg:
2435 decode_register_operand(&c->src, c, 0);
2436 break;
2437 case SrcMem16:
2438 c->src.bytes = 2;
2439 goto srcmem_common;
2440 case SrcMem32:
2441 c->src.bytes = 4;
2442 goto srcmem_common;
2443 case SrcMem:
2444 c->src.bytes = (c->d & ByteOp) ? 1 :
2445 c->op_bytes;
2446 /* Don't fetch the address for invlpg: it could be unmapped. */
2447 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
2448 break;
2449 srcmem_common:
2450 /*
2451 * For instructions with a ModR/M byte, switch to register
2452 * access if Mod = 3.
2453 */
2454 if ((c->d & ModRM) && c->modrm_mod == 3) {
2455 c->src.type = OP_REG;
2456 c->src.val = c->modrm_val;
2457 c->src.ptr = c->modrm_ptr;
2458 break;
2459 }
2460 c->src.type = OP_MEM;
2461 c->src.ptr = (unsigned long *)c->modrm_ea;
2462 c->src.val = 0;
2463 break;
2464 case SrcImm:
2465 case SrcImmU:
2466 c->src.type = OP_IMM;
2467 c->src.ptr = (unsigned long *)c->eip;
2468 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2469 if (c->src.bytes == 8)
2470 c->src.bytes = 4;
2471 /* NB. Immediates are sign-extended as necessary. */
2472 switch (c->src.bytes) {
2473 case 1:
2474 c->src.val = insn_fetch(s8, 1, c->eip);
2475 break;
2476 case 2:
2477 c->src.val = insn_fetch(s16, 2, c->eip);
2478 break;
2479 case 4:
2480 c->src.val = insn_fetch(s32, 4, c->eip);
2481 break;
2482 }
2483 if ((c->d & SrcMask) == SrcImmU) {
2484 switch (c->src.bytes) {
2485 case 1:
2486 c->src.val &= 0xff;
2487 break;
2488 case 2:
2489 c->src.val &= 0xffff;
2490 break;
2491 case 4:
2492 c->src.val &= 0xffffffff;
2493 break;
2494 }
2495 }
2496 break;
2497 case SrcImmByte:
2498 case SrcImmUByte:
2499 c->src.type = OP_IMM;
2500 c->src.ptr = (unsigned long *)c->eip;
2501 c->src.bytes = 1;
2502 if ((c->d & SrcMask) == SrcImmByte)
2503 c->src.val = insn_fetch(s8, 1, c->eip);
2504 else
2505 c->src.val = insn_fetch(u8, 1, c->eip);
2506 break;
2507 case SrcAcc:
2508 c->src.type = OP_REG;
2509 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2510 c->src.ptr = &c->regs[VCPU_REGS_RAX];
2511 switch (c->src.bytes) {
2512 case 1:
2513 c->src.val = *(u8 *)c->src.ptr;
2514 break;
2515 case 2:
2516 c->src.val = *(u16 *)c->src.ptr;
2517 break;
2518 case 4:
2519 c->src.val = *(u32 *)c->src.ptr;
2520 break;
2521 case 8:
2522 c->src.val = *(u64 *)c->src.ptr;
2523 break;
2524 }
2525 break;
2526 case SrcOne:
2527 c->src.bytes = 1;
2528 c->src.val = 1;
2529 break;
2530 case SrcSI:
2531 c->src.type = OP_MEM;
2532 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2533 c->src.ptr = (unsigned long *)
2534 register_address(c, seg_override_base(ctxt, ops, c),
2535 c->regs[VCPU_REGS_RSI]);
2536 c->src.val = 0;
2537 break;
2538 case SrcImmFAddr:
2539 c->src.type = OP_IMM;
2540 c->src.ptr = (unsigned long *)c->eip;
2541 c->src.bytes = c->op_bytes + 2;
2542 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2543 break;
2544 case SrcMemFAddr:
2545 c->src.type = OP_MEM;
2546 c->src.ptr = (unsigned long *)c->modrm_ea;
2547 c->src.bytes = c->op_bytes + 2;
2548 break;
2549 }
2550
2551 /*
2552 * Decode and fetch the second source operand: register, memory
2553 * or immediate.
2554 */
2555 switch (c->d & Src2Mask) {
2556 case Src2None:
2557 break;
2558 case Src2CL:
2559 c->src2.bytes = 1;
2560 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2561 break;
2562 case Src2ImmByte:
2563 c->src2.type = OP_IMM;
2564 c->src2.ptr = (unsigned long *)c->eip;
2565 c->src2.bytes = 1;
2566 c->src2.val = insn_fetch(u8, 1, c->eip);
2567 break;
2568 case Src2One:
2569 c->src2.bytes = 1;
2570 c->src2.val = 1;
2571 break;
2572 }
2573
2574 /* Decode and fetch the destination operand: register or memory. */
2575 switch (c->d & DstMask) {
2576 case ImplicitOps:
2577 /* Special instructions do their own operand decoding. */
2578 return 0;
2579 case DstReg:
2580 decode_register_operand(&c->dst, c,
2581 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2582 break;
2583 case DstMem:
2584 case DstMem64:
2585 if ((c->d & ModRM) && c->modrm_mod == 3) {
2586 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2587 c->dst.type = OP_REG;
2588 c->dst.val = c->dst.orig_val = c->modrm_val;
2589 c->dst.ptr = c->modrm_ptr;
2590 break;
2591 }
2592 c->dst.type = OP_MEM;
2593 c->dst.ptr = (unsigned long *)c->modrm_ea;
2594 if ((c->d & DstMask) == DstMem64)
2595 c->dst.bytes = 8;
2596 else
2597 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2598 c->dst.val = 0;
2599 if (c->d & BitOp) {
2600 unsigned long mask = ~(c->dst.bytes * 8 - 1);
2601
2602 c->dst.ptr = (void *)c->dst.ptr +
2603 (c->src.val & mask) / 8;
2604 }
2605 break;
2606 case DstAcc:
2607 c->dst.type = OP_REG;
2608 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2609 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
2610 switch (c->dst.bytes) {
2611 case 1:
2612 c->dst.val = *(u8 *)c->dst.ptr;
2613 break;
2614 case 2:
2615 c->dst.val = *(u16 *)c->dst.ptr;
2616 break;
2617 case 4:
2618 c->dst.val = *(u32 *)c->dst.ptr;
2619 break;
2620 case 8:
2621 c->dst.val = *(u64 *)c->dst.ptr;
2622 break;
2623 }
2624 c->dst.orig_val = c->dst.val;
2625 break;
2626 case DstDI:
2627 c->dst.type = OP_MEM;
2628 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2629 c->dst.ptr = (unsigned long *)
2630 register_address(c, es_base(ctxt, ops),
2631 c->regs[VCPU_REGS_RDI]);
2632 c->dst.val = 0;
2633 break;
2634 }
2635
2636 done:
2637 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2638 }
2639
2640 int
2641 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2642 {
2643 struct x86_emulate_ops *ops = ctxt->ops;
2644 u64 msr_data;
2645 struct decode_cache *c = &ctxt->decode;
2646 int rc = X86EMUL_CONTINUE;
2647 int saved_dst_type = c->dst.type;
2648
2649 ctxt->decode.mem_read.pos = 0;
2650
2651 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2652 emulate_ud(ctxt);
2653 goto done;
2654 }
2655
2656 /* LOCK prefix is allowed only with some instructions */
2657 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2658 emulate_ud(ctxt);
2659 goto done;
2660 }
2661
2662 /* Privileged instruction can be executed only in CPL=0 */
2663 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2664 emulate_gp(ctxt, 0);
2665 goto done;
2666 }
2667
2668 if (c->rep_prefix && (c->d & String)) {
2669 ctxt->restart = true;
2670 /* All REP prefixes have the same first termination condition */
2671 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2672 string_done:
2673 ctxt->restart = false;
2674 ctxt->eip = c->eip;
2675 goto done;
2676 }
2677 /* The second termination condition only applies for REPE
2678 * and REPNE. Test if the repeat string operation prefix is
2679 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2680 * corresponding termination condition according to:
2681 * - if REPE/REPZ and ZF = 0 then done
2682 * - if REPNE/REPNZ and ZF = 1 then done
2683 */
2684 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2685 (c->b == 0xae) || (c->b == 0xaf)) {
2686 if ((c->rep_prefix == REPE_PREFIX) &&
2687 ((ctxt->eflags & EFLG_ZF) == 0))
2688 goto string_done;
2689 if ((c->rep_prefix == REPNE_PREFIX) &&
2690 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2691 goto string_done;
2692 }
2693 c->eip = ctxt->eip;
2694 }
2695
2696 if (c->src.type == OP_MEM) {
2697 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
2698 c->src.valptr, c->src.bytes);
2699 if (rc != X86EMUL_CONTINUE)
2700 goto done;
2701 c->src.orig_val64 = c->src.val64;
2702 }
2703
2704 if (c->src2.type == OP_MEM) {
2705 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2706 &c->src2.val, c->src2.bytes);
2707 if (rc != X86EMUL_CONTINUE)
2708 goto done;
2709 }
2710
2711 if ((c->d & DstMask) == ImplicitOps)
2712 goto special_insn;
2713
2714
2715 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2716 /* optimisation - avoid slow emulated read if Mov */
2717 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2718 &c->dst.val, c->dst.bytes);
2719 if (rc != X86EMUL_CONTINUE)
2720 goto done;
2721 }
2722 c->dst.orig_val = c->dst.val;
2723
2724 special_insn:
2725
2726 if (c->execute) {
2727 rc = c->execute(ctxt);
2728 if (rc != X86EMUL_CONTINUE)
2729 goto done;
2730 goto writeback;
2731 }
2732
2733 if (c->twobyte)
2734 goto twobyte_insn;
2735
2736 switch (c->b) {
2737 case 0x00 ... 0x05:
2738 add: /* add */
2739 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2740 break;
2741 case 0x06: /* push es */
2742 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
2743 break;
2744 case 0x07: /* pop es */
2745 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2746 if (rc != X86EMUL_CONTINUE)
2747 goto done;
2748 break;
2749 case 0x08 ... 0x0d:
2750 or: /* or */
2751 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2752 break;
2753 case 0x0e: /* push cs */
2754 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
2755 break;
2756 case 0x10 ... 0x15:
2757 adc: /* adc */
2758 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2759 break;
2760 case 0x16: /* push ss */
2761 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
2762 break;
2763 case 0x17: /* pop ss */
2764 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2765 if (rc != X86EMUL_CONTINUE)
2766 goto done;
2767 break;
2768 case 0x18 ... 0x1d:
2769 sbb: /* sbb */
2770 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2771 break;
2772 case 0x1e: /* push ds */
2773 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
2774 break;
2775 case 0x1f: /* pop ds */
2776 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2777 if (rc != X86EMUL_CONTINUE)
2778 goto done;
2779 break;
2780 case 0x20 ... 0x25:
2781 and: /* and */
2782 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2783 break;
2784 case 0x28 ... 0x2d:
2785 sub: /* sub */
2786 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2787 break;
2788 case 0x30 ... 0x35:
2789 xor: /* xor */
2790 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2791 break;
2792 case 0x38 ... 0x3d:
2793 cmp: /* cmp */
2794 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2795 break;
2796 case 0x40 ... 0x47: /* inc r16/r32 */
2797 emulate_1op("inc", c->dst, ctxt->eflags);
2798 break;
2799 case 0x48 ... 0x4f: /* dec r16/r32 */
2800 emulate_1op("dec", c->dst, ctxt->eflags);
2801 break;
2802 case 0x58 ... 0x5f: /* pop reg */
2803 pop_instruction:
2804 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2805 if (rc != X86EMUL_CONTINUE)
2806 goto done;
2807 break;
2808 case 0x60: /* pusha */
2809 rc = emulate_pusha(ctxt, ops);
2810 if (rc != X86EMUL_CONTINUE)
2811 goto done;
2812 break;
2813 case 0x61: /* popa */
2814 rc = emulate_popa(ctxt, ops);
2815 if (rc != X86EMUL_CONTINUE)
2816 goto done;
2817 break;
2818 case 0x63: /* movsxd */
2819 if (ctxt->mode != X86EMUL_MODE_PROT64)
2820 goto cannot_emulate;
2821 c->dst.val = (s32) c->src.val;
2822 break;
2823 case 0x6c: /* insb */
2824 case 0x6d: /* insw/insd */
2825 c->dst.bytes = min(c->dst.bytes, 4u);
2826 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2827 c->dst.bytes)) {
2828 emulate_gp(ctxt, 0);
2829 goto done;
2830 }
2831 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2832 c->regs[VCPU_REGS_RDX], &c->dst.val))
2833 goto done; /* IO is needed, skip writeback */
2834 break;
2835 case 0x6e: /* outsb */
2836 case 0x6f: /* outsw/outsd */
2837 c->src.bytes = min(c->src.bytes, 4u);
2838 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2839 c->src.bytes)) {
2840 emulate_gp(ctxt, 0);
2841 goto done;
2842 }
2843 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2844 &c->src.val, 1, ctxt->vcpu);
2845
2846 c->dst.type = OP_NONE; /* nothing to writeback */
2847 break;
2848 case 0x70 ... 0x7f: /* jcc (short) */
2849 if (test_cc(c->b, ctxt->eflags))
2850 jmp_rel(c, c->src.val);
2851 break;
2852 case 0x80 ... 0x83: /* Grp1 */
2853 switch (c->modrm_reg) {
2854 case 0:
2855 goto add;
2856 case 1:
2857 goto or;
2858 case 2:
2859 goto adc;
2860 case 3:
2861 goto sbb;
2862 case 4:
2863 goto and;
2864 case 5:
2865 goto sub;
2866 case 6:
2867 goto xor;
2868 case 7:
2869 goto cmp;
2870 }
2871 break;
2872 case 0x84 ... 0x85:
2873 test:
2874 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2875 break;
2876 case 0x86 ... 0x87: /* xchg */
2877 xchg:
2878 /* Write back the register source. */
2879 switch (c->dst.bytes) {
2880 case 1:
2881 *(u8 *) c->src.ptr = (u8) c->dst.val;
2882 break;
2883 case 2:
2884 *(u16 *) c->src.ptr = (u16) c->dst.val;
2885 break;
2886 case 4:
2887 *c->src.ptr = (u32) c->dst.val;
2888 break; /* 64b reg: zero-extend */
2889 case 8:
2890 *c->src.ptr = c->dst.val;
2891 break;
2892 }
2893 /*
2894 * Write back the memory destination with implicit LOCK
2895 * prefix.
2896 */
2897 c->dst.val = c->src.val;
2898 c->lock_prefix = 1;
2899 break;
2900 case 0x88 ... 0x8b: /* mov */
2901 goto mov;
2902 case 0x8c: /* mov r/m, sreg */
2903 if (c->modrm_reg > VCPU_SREG_GS) {
2904 emulate_ud(ctxt);
2905 goto done;
2906 }
2907 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
2908 break;
2909 case 0x8d: /* lea r16/r32, m */
2910 c->dst.val = c->modrm_ea;
2911 break;
2912 case 0x8e: { /* mov seg, r/m16 */
2913 uint16_t sel;
2914
2915 sel = c->src.val;
2916
2917 if (c->modrm_reg == VCPU_SREG_CS ||
2918 c->modrm_reg > VCPU_SREG_GS) {
2919 emulate_ud(ctxt);
2920 goto done;
2921 }
2922
2923 if (c->modrm_reg == VCPU_SREG_SS)
2924 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2925
2926 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
2927
2928 c->dst.type = OP_NONE; /* Disable writeback. */
2929 break;
2930 }
2931 case 0x8f: /* pop (sole member of Grp1a) */
2932 rc = emulate_grp1a(ctxt, ops);
2933 if (rc != X86EMUL_CONTINUE)
2934 goto done;
2935 break;
2936 case 0x90: /* nop / xchg r8,rax */
2937 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2938 c->dst.type = OP_NONE; /* nop */
2939 break;
2940 }
2941 case 0x91 ... 0x97: /* xchg reg,rax */
2942 c->src.type = OP_REG;
2943 c->src.bytes = c->op_bytes;
2944 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2945 c->src.val = *(c->src.ptr);
2946 goto xchg;
2947 case 0x9c: /* pushf */
2948 c->src.val = (unsigned long) ctxt->eflags;
2949 emulate_push(ctxt, ops);
2950 break;
2951 case 0x9d: /* popf */
2952 c->dst.type = OP_REG;
2953 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2954 c->dst.bytes = c->op_bytes;
2955 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2956 if (rc != X86EMUL_CONTINUE)
2957 goto done;
2958 break;
2959 case 0xa0 ... 0xa3: /* mov */
2960 case 0xa4 ... 0xa5: /* movs */
2961 goto mov;
2962 case 0xa6 ... 0xa7: /* cmps */
2963 c->dst.type = OP_NONE; /* Disable writeback. */
2964 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2965 goto cmp;
2966 case 0xa8 ... 0xa9: /* test ax, imm */
2967 goto test;
2968 case 0xaa ... 0xab: /* stos */
2969 c->dst.val = c->regs[VCPU_REGS_RAX];
2970 break;
2971 case 0xac ... 0xad: /* lods */
2972 goto mov;
2973 case 0xae ... 0xaf: /* scas */
2974 DPRINTF("Urk! I don't handle SCAS.\n");
2975 goto cannot_emulate;
2976 case 0xb0 ... 0xbf: /* mov r, imm */
2977 goto mov;
2978 case 0xc0 ... 0xc1:
2979 emulate_grp2(ctxt);
2980 break;
2981 case 0xc3: /* ret */
2982 c->dst.type = OP_REG;
2983 c->dst.ptr = &c->eip;
2984 c->dst.bytes = c->op_bytes;
2985 goto pop_instruction;
2986 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2987 mov:
2988 c->dst.val = c->src.val;
2989 break;
2990 case 0xcb: /* ret far */
2991 rc = emulate_ret_far(ctxt, ops);
2992 if (rc != X86EMUL_CONTINUE)
2993 goto done;
2994 break;
2995 case 0xcf: /* iret */
2996 rc = emulate_iret(ctxt, ops);
2997
2998 if (rc != X86EMUL_CONTINUE)
2999 goto done;
3000 break;
3001 case 0xd0 ... 0xd1: /* Grp2 */
3002 c->src.val = 1;
3003 emulate_grp2(ctxt);
3004 break;
3005 case 0xd2 ... 0xd3: /* Grp2 */
3006 c->src.val = c->regs[VCPU_REGS_RCX];
3007 emulate_grp2(ctxt);
3008 break;
3009 case 0xe4: /* inb */
3010 case 0xe5: /* in */
3011 goto do_io_in;
3012 case 0xe6: /* outb */
3013 case 0xe7: /* out */
3014 goto do_io_out;
3015 case 0xe8: /* call (near) */ {
3016 long int rel = c->src.val;
3017 c->src.val = (unsigned long) c->eip;
3018 jmp_rel(c, rel);
3019 emulate_push(ctxt, ops);
3020 break;
3021 }
3022 case 0xe9: /* jmp rel */
3023 goto jmp;
3024 case 0xea: { /* jmp far */
3025 unsigned short sel;
3026 jump_far:
3027 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3028
3029 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3030 goto done;
3031
3032 c->eip = 0;
3033 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3034 break;
3035 }
3036 case 0xeb:
3037 jmp: /* jmp rel short */
3038 jmp_rel(c, c->src.val);
3039 c->dst.type = OP_NONE; /* Disable writeback. */
3040 break;
3041 case 0xec: /* in al,dx */
3042 case 0xed: /* in (e/r)ax,dx */
3043 c->src.val = c->regs[VCPU_REGS_RDX];
3044 do_io_in:
3045 c->dst.bytes = min(c->dst.bytes, 4u);
3046 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3047 emulate_gp(ctxt, 0);
3048 goto done;
3049 }
3050 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3051 &c->dst.val))
3052 goto done; /* IO is needed */
3053 break;
3054 case 0xee: /* out dx,al */
3055 case 0xef: /* out dx,(e/r)ax */
3056 c->src.val = c->regs[VCPU_REGS_RDX];
3057 do_io_out:
3058 c->dst.bytes = min(c->dst.bytes, 4u);
3059 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3060 emulate_gp(ctxt, 0);
3061 goto done;
3062 }
3063 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3064 ctxt->vcpu);
3065 c->dst.type = OP_NONE; /* Disable writeback. */
3066 break;
3067 case 0xf4: /* hlt */
3068 ctxt->vcpu->arch.halt_request = 1;
3069 break;
3070 case 0xf5: /* cmc */
3071 /* complement carry flag from eflags reg */
3072 ctxt->eflags ^= EFLG_CF;
3073 c->dst.type = OP_NONE; /* Disable writeback. */
3074 break;
3075 case 0xf6 ... 0xf7: /* Grp3 */
3076 if (!emulate_grp3(ctxt, ops))
3077 goto cannot_emulate;
3078 break;
3079 case 0xf8: /* clc */
3080 ctxt->eflags &= ~EFLG_CF;
3081 c->dst.type = OP_NONE; /* Disable writeback. */
3082 break;
3083 case 0xfa: /* cli */
3084 if (emulator_bad_iopl(ctxt, ops)) {
3085 emulate_gp(ctxt, 0);
3086 goto done;
3087 } else {
3088 ctxt->eflags &= ~X86_EFLAGS_IF;
3089 c->dst.type = OP_NONE; /* Disable writeback. */
3090 }
3091 break;
3092 case 0xfb: /* sti */
3093 if (emulator_bad_iopl(ctxt, ops)) {
3094 emulate_gp(ctxt, 0);
3095 goto done;
3096 } else {
3097 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3098 ctxt->eflags |= X86_EFLAGS_IF;
3099 c->dst.type = OP_NONE; /* Disable writeback. */
3100 }
3101 break;
3102 case 0xfc: /* cld */
3103 ctxt->eflags &= ~EFLG_DF;
3104 c->dst.type = OP_NONE; /* Disable writeback. */
3105 break;
3106 case 0xfd: /* std */
3107 ctxt->eflags |= EFLG_DF;
3108 c->dst.type = OP_NONE; /* Disable writeback. */
3109 break;
3110 case 0xfe: /* Grp4 */
3111 grp45:
3112 rc = emulate_grp45(ctxt, ops);
3113 if (rc != X86EMUL_CONTINUE)
3114 goto done;
3115 break;
3116 case 0xff: /* Grp5 */
3117 if (c->modrm_reg == 5)
3118 goto jump_far;
3119 goto grp45;
3120 default:
3121 goto cannot_emulate;
3122 }
3123
3124 writeback:
3125 rc = writeback(ctxt, ops);
3126 if (rc != X86EMUL_CONTINUE)
3127 goto done;
3128
3129 /*
3130 * restore dst type in case the decoding will be reused
3131 * (happens for string instruction )
3132 */
3133 c->dst.type = saved_dst_type;
3134
3135 if ((c->d & SrcMask) == SrcSI)
3136 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3137 VCPU_REGS_RSI, &c->src);
3138
3139 if ((c->d & DstMask) == DstDI)
3140 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3141 &c->dst);
3142
3143 if (c->rep_prefix && (c->d & String)) {
3144 struct read_cache *rc = &ctxt->decode.io_read;
3145 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3146 /*
3147 * Re-enter guest when pio read ahead buffer is empty or,
3148 * if it is not used, after each 1024 iteration.
3149 */
3150 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3151 (rc->end != 0 && rc->end == rc->pos))
3152 ctxt->restart = false;
3153 }
3154 /*
3155 * reset read cache here in case string instruction is restared
3156 * without decoding
3157 */
3158 ctxt->decode.mem_read.end = 0;
3159 ctxt->eip = c->eip;
3160
3161 done:
3162 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3163
3164 twobyte_insn:
3165 switch (c->b) {
3166 case 0x01: /* lgdt, lidt, lmsw */
3167 switch (c->modrm_reg) {
3168 u16 size;
3169 unsigned long address;
3170
3171 case 0: /* vmcall */
3172 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3173 goto cannot_emulate;
3174
3175 rc = kvm_fix_hypercall(ctxt->vcpu);
3176 if (rc != X86EMUL_CONTINUE)
3177 goto done;
3178
3179 /* Let the processor re-execute the fixed hypercall */
3180 c->eip = ctxt->eip;
3181 /* Disable writeback. */
3182 c->dst.type = OP_NONE;
3183 break;
3184 case 2: /* lgdt */
3185 rc = read_descriptor(ctxt, ops, c->src.ptr,
3186 &size, &address, c->op_bytes);
3187 if (rc != X86EMUL_CONTINUE)
3188 goto done;
3189 realmode_lgdt(ctxt->vcpu, size, address);
3190 /* Disable writeback. */
3191 c->dst.type = OP_NONE;
3192 break;
3193 case 3: /* lidt/vmmcall */
3194 if (c->modrm_mod == 3) {
3195 switch (c->modrm_rm) {
3196 case 1:
3197 rc = kvm_fix_hypercall(ctxt->vcpu);
3198 if (rc != X86EMUL_CONTINUE)
3199 goto done;
3200 break;
3201 default:
3202 goto cannot_emulate;
3203 }
3204 } else {
3205 rc = read_descriptor(ctxt, ops, c->src.ptr,
3206 &size, &address,
3207 c->op_bytes);
3208 if (rc != X86EMUL_CONTINUE)
3209 goto done;
3210 realmode_lidt(ctxt->vcpu, size, address);
3211 }
3212 /* Disable writeback. */
3213 c->dst.type = OP_NONE;
3214 break;
3215 case 4: /* smsw */
3216 c->dst.bytes = 2;
3217 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3218 break;
3219 case 6: /* lmsw */
3220 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3221 (c->src.val & 0x0f), ctxt->vcpu);
3222 c->dst.type = OP_NONE;
3223 break;
3224 case 5: /* not defined */
3225 emulate_ud(ctxt);
3226 goto done;
3227 case 7: /* invlpg*/
3228 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
3229 /* Disable writeback. */
3230 c->dst.type = OP_NONE;
3231 break;
3232 default:
3233 goto cannot_emulate;
3234 }
3235 break;
3236 case 0x05: /* syscall */
3237 rc = emulate_syscall(ctxt, ops);
3238 if (rc != X86EMUL_CONTINUE)
3239 goto done;
3240 else
3241 goto writeback;
3242 break;
3243 case 0x06:
3244 emulate_clts(ctxt->vcpu);
3245 c->dst.type = OP_NONE;
3246 break;
3247 case 0x09: /* wbinvd */
3248 kvm_emulate_wbinvd(ctxt->vcpu);
3249 c->dst.type = OP_NONE;
3250 break;
3251 case 0x08: /* invd */
3252 case 0x0d: /* GrpP (prefetch) */
3253 case 0x18: /* Grp16 (prefetch/nop) */
3254 c->dst.type = OP_NONE;
3255 break;
3256 case 0x20: /* mov cr, reg */
3257 switch (c->modrm_reg) {
3258 case 1:
3259 case 5 ... 7:
3260 case 9 ... 15:
3261 emulate_ud(ctxt);
3262 goto done;
3263 }
3264 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3265 c->dst.type = OP_NONE; /* no writeback */
3266 break;
3267 case 0x21: /* mov from dr to reg */
3268 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3269 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3270 emulate_ud(ctxt);
3271 goto done;
3272 }
3273 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
3274 c->dst.type = OP_NONE; /* no writeback */
3275 break;
3276 case 0x22: /* mov reg, cr */
3277 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
3278 emulate_gp(ctxt, 0);
3279 goto done;
3280 }
3281 c->dst.type = OP_NONE;
3282 break;
3283 case 0x23: /* mov from reg to dr */
3284 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3285 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3286 emulate_ud(ctxt);
3287 goto done;
3288 }
3289
3290 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3291 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3292 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3293 /* #UD condition is already handled by the code above */
3294 emulate_gp(ctxt, 0);
3295 goto done;
3296 }
3297
3298 c->dst.type = OP_NONE; /* no writeback */
3299 break;
3300 case 0x30:
3301 /* wrmsr */
3302 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3303 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3304 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3305 emulate_gp(ctxt, 0);
3306 goto done;
3307 }
3308 rc = X86EMUL_CONTINUE;
3309 c->dst.type = OP_NONE;
3310 break;
3311 case 0x32:
3312 /* rdmsr */
3313 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3314 emulate_gp(ctxt, 0);
3315 goto done;
3316 } else {
3317 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3318 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3319 }
3320 rc = X86EMUL_CONTINUE;
3321 c->dst.type = OP_NONE;
3322 break;
3323 case 0x34: /* sysenter */
3324 rc = emulate_sysenter(ctxt, ops);
3325 if (rc != X86EMUL_CONTINUE)
3326 goto done;
3327 else
3328 goto writeback;
3329 break;
3330 case 0x35: /* sysexit */
3331 rc = emulate_sysexit(ctxt, ops);
3332 if (rc != X86EMUL_CONTINUE)
3333 goto done;
3334 else
3335 goto writeback;
3336 break;
3337 case 0x40 ... 0x4f: /* cmov */
3338 c->dst.val = c->dst.orig_val = c->src.val;
3339 if (!test_cc(c->b, ctxt->eflags))
3340 c->dst.type = OP_NONE; /* no writeback */
3341 break;
3342 case 0x80 ... 0x8f: /* jnz rel, etc*/
3343 if (test_cc(c->b, ctxt->eflags))
3344 jmp_rel(c, c->src.val);
3345 c->dst.type = OP_NONE;
3346 break;
3347 case 0xa0: /* push fs */
3348 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3349 break;
3350 case 0xa1: /* pop fs */
3351 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3352 if (rc != X86EMUL_CONTINUE)
3353 goto done;
3354 break;
3355 case 0xa3:
3356 bt: /* bt */
3357 c->dst.type = OP_NONE;
3358 /* only subword offset */
3359 c->src.val &= (c->dst.bytes << 3) - 1;
3360 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3361 break;
3362 case 0xa4: /* shld imm8, r, r/m */
3363 case 0xa5: /* shld cl, r, r/m */
3364 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3365 break;
3366 case 0xa8: /* push gs */
3367 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3368 break;
3369 case 0xa9: /* pop gs */
3370 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3371 if (rc != X86EMUL_CONTINUE)
3372 goto done;
3373 break;
3374 case 0xab:
3375 bts: /* bts */
3376 /* only subword offset */
3377 c->src.val &= (c->dst.bytes << 3) - 1;
3378 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3379 break;
3380 case 0xac: /* shrd imm8, r, r/m */
3381 case 0xad: /* shrd cl, r, r/m */
3382 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3383 break;
3384 case 0xae: /* clflush */
3385 break;
3386 case 0xb0 ... 0xb1: /* cmpxchg */
3387 /*
3388 * Save real source value, then compare EAX against
3389 * destination.
3390 */
3391 c->src.orig_val = c->src.val;
3392 c->src.val = c->regs[VCPU_REGS_RAX];
3393 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3394 if (ctxt->eflags & EFLG_ZF) {
3395 /* Success: write back to memory. */
3396 c->dst.val = c->src.orig_val;
3397 } else {
3398 /* Failure: write the value we saw to EAX. */
3399 c->dst.type = OP_REG;
3400 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3401 }
3402 break;
3403 case 0xb3:
3404 btr: /* btr */
3405 /* only subword offset */
3406 c->src.val &= (c->dst.bytes << 3) - 1;
3407 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3408 break;
3409 case 0xb6 ... 0xb7: /* movzx */
3410 c->dst.bytes = c->op_bytes;
3411 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3412 : (u16) c->src.val;
3413 break;
3414 case 0xba: /* Grp8 */
3415 switch (c->modrm_reg & 3) {
3416 case 0:
3417 goto bt;
3418 case 1:
3419 goto bts;
3420 case 2:
3421 goto btr;
3422 case 3:
3423 goto btc;
3424 }
3425 break;
3426 case 0xbb:
3427 btc: /* btc */
3428 /* only subword offset */
3429 c->src.val &= (c->dst.bytes << 3) - 1;
3430 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3431 break;
3432 case 0xbe ... 0xbf: /* movsx */
3433 c->dst.bytes = c->op_bytes;
3434 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3435 (s16) c->src.val;
3436 break;
3437 case 0xc3: /* movnti */
3438 c->dst.bytes = c->op_bytes;
3439 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3440 (u64) c->src.val;
3441 break;
3442 case 0xc7: /* Grp9 (cmpxchg8b) */
3443 rc = emulate_grp9(ctxt, ops);
3444 if (rc != X86EMUL_CONTINUE)
3445 goto done;
3446 break;
3447 default:
3448 goto cannot_emulate;
3449 }
3450 goto writeback;
3451
3452 cannot_emulate:
3453 DPRINTF("Cannot emulate %02x\n", c->b);
3454 return -1;
3455 }
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