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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / lapic.c
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
40 #include "irq.h"
41 #include "trace.h"
42 #include "x86.h"
43 #include "cpuid.h"
44 #include "hyperv.h"
45
46 #ifndef CONFIG_X86_64
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #else
49 #define mod_64(x, y) ((x) % (y))
50 #endif
51
52 #define PRId64 "d"
53 #define PRIx64 "llx"
54 #define PRIu64 "u"
55 #define PRIo64 "o"
56
57 #define APIC_BUS_CYCLE_NS 1
58
59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60 #define apic_debug(fmt, arg...)
61
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
71
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
74
75 static inline int apic_test_vector(int vec, void *bitmap)
76 {
77 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 }
79
80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
81 {
82 struct kvm_lapic *apic = vcpu->arch.apic;
83
84 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
85 apic_test_vector(vector, apic->regs + APIC_IRR);
86 }
87
88 static inline void apic_clear_vector(int vec, void *bitmap)
89 {
90 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 }
92
93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
94 {
95 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 }
97
98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
99 {
100 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 }
102
103 struct static_key_deferred apic_hw_disabled __read_mostly;
104 struct static_key_deferred apic_sw_disabled __read_mostly;
105
106 static inline int apic_enabled(struct kvm_lapic *apic)
107 {
108 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
109 }
110
111 #define LVT_MASK \
112 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
113
114 #define LINT_MASK \
115 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
116 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
117
118 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
119 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
120 switch (map->mode) {
121 case KVM_APIC_MODE_X2APIC: {
122 u32 offset = (dest_id >> 16) * 16;
123 u32 max_apic_id = map->max_apic_id;
124
125 if (offset <= max_apic_id) {
126 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
127
128 *cluster = &map->phys_map[offset];
129 *mask = dest_id & (0xffff >> (16 - cluster_size));
130 } else {
131 *mask = 0;
132 }
133
134 return true;
135 }
136 case KVM_APIC_MODE_XAPIC_FLAT:
137 *cluster = map->xapic_flat_map;
138 *mask = dest_id & 0xff;
139 return true;
140 case KVM_APIC_MODE_XAPIC_CLUSTER:
141 *cluster = map->xapic_cluster_map[dest_id >> 4];
142 *mask = dest_id & 0xf;
143 return true;
144 default:
145 /* Not optimized. */
146 return false;
147 }
148 }
149
150 static void recalculate_apic_map(struct kvm *kvm)
151 {
152 struct kvm_apic_map *new, *old = NULL;
153 struct kvm_vcpu *vcpu;
154 int i;
155 u32 max_id = 255;
156
157 mutex_lock(&kvm->arch.apic_map_lock);
158
159 kvm_for_each_vcpu(i, vcpu, kvm)
160 if (kvm_apic_present(vcpu))
161 max_id = max(max_id, kvm_apic_id(vcpu->arch.apic));
162
163 new = kzalloc(sizeof(struct kvm_apic_map) +
164 sizeof(struct kvm_lapic *) * (max_id + 1), GFP_KERNEL);
165
166 if (!new)
167 goto out;
168
169 new->max_apic_id = max_id;
170
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 struct kvm_lapic **cluster;
174 u16 mask;
175 u32 ldr, aid;
176
177 if (!kvm_apic_present(vcpu))
178 continue;
179
180 aid = kvm_apic_id(apic);
181 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
182
183 if (aid <= new->max_apic_id)
184 new->phys_map[aid] = apic;
185
186 if (apic_x2apic_mode(apic)) {
187 new->mode |= KVM_APIC_MODE_X2APIC;
188 } else if (ldr) {
189 ldr = GET_APIC_LOGICAL_ID(ldr);
190 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
191 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
192 else
193 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
194 }
195
196 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
197 continue;
198
199 if (mask)
200 cluster[ffs(mask) - 1] = apic;
201 }
202 out:
203 old = rcu_dereference_protected(kvm->arch.apic_map,
204 lockdep_is_held(&kvm->arch.apic_map_lock));
205 rcu_assign_pointer(kvm->arch.apic_map, new);
206 mutex_unlock(&kvm->arch.apic_map_lock);
207
208 if (old)
209 kfree_rcu(old, rcu);
210
211 kvm_make_scan_ioapic_request(kvm);
212 }
213
214 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
215 {
216 bool enabled = val & APIC_SPIV_APIC_ENABLED;
217
218 kvm_lapic_set_reg(apic, APIC_SPIV, val);
219
220 if (enabled != apic->sw_enabled) {
221 apic->sw_enabled = enabled;
222 if (enabled) {
223 static_key_slow_dec_deferred(&apic_sw_disabled);
224 recalculate_apic_map(apic->vcpu->kvm);
225 } else
226 static_key_slow_inc(&apic_sw_disabled.key);
227 }
228 }
229
230 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
231 {
232 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
233 recalculate_apic_map(apic->vcpu->kvm);
234 }
235
236 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
237 {
238 kvm_lapic_set_reg(apic, APIC_LDR, id);
239 recalculate_apic_map(apic->vcpu->kvm);
240 }
241
242 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
243 {
244 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
245
246 kvm_lapic_set_reg(apic, APIC_ID, id);
247 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
248 recalculate_apic_map(apic->vcpu->kvm);
249 }
250
251 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
252 {
253 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
254 }
255
256 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
257 {
258 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
259 }
260
261 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
262 {
263 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
264 }
265
266 static inline int apic_lvtt_period(struct kvm_lapic *apic)
267 {
268 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
269 }
270
271 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
272 {
273 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
274 }
275
276 static inline int apic_lvt_nmi_mode(u32 lvt_val)
277 {
278 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
279 }
280
281 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
282 {
283 struct kvm_lapic *apic = vcpu->arch.apic;
284 struct kvm_cpuid_entry2 *feat;
285 u32 v = APIC_VERSION;
286
287 if (!lapic_in_kernel(vcpu))
288 return;
289
290 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
291 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
292 v |= APIC_LVR_DIRECTED_EOI;
293 kvm_lapic_set_reg(apic, APIC_LVR, v);
294 }
295
296 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
297 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
298 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
299 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
300 LINT_MASK, LINT_MASK, /* LVT0-1 */
301 LVT_MASK /* LVTERR */
302 };
303
304 static int find_highest_vector(void *bitmap)
305 {
306 int vec;
307 u32 *reg;
308
309 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
310 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
311 reg = bitmap + REG_POS(vec);
312 if (*reg)
313 return fls(*reg) - 1 + vec;
314 }
315
316 return -1;
317 }
318
319 static u8 count_vectors(void *bitmap)
320 {
321 int vec;
322 u32 *reg;
323 u8 count = 0;
324
325 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
326 reg = bitmap + REG_POS(vec);
327 count += hweight32(*reg);
328 }
329
330 return count;
331 }
332
333 void __kvm_apic_update_irr(u32 *pir, void *regs)
334 {
335 u32 i, pir_val;
336
337 for (i = 0; i <= 7; i++) {
338 pir_val = xchg(&pir[i], 0);
339 if (pir_val)
340 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
341 }
342 }
343 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
344
345 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
346 {
347 struct kvm_lapic *apic = vcpu->arch.apic;
348
349 __kvm_apic_update_irr(pir, apic->regs);
350
351 kvm_make_request(KVM_REQ_EVENT, vcpu);
352 }
353 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
354
355 static inline int apic_search_irr(struct kvm_lapic *apic)
356 {
357 return find_highest_vector(apic->regs + APIC_IRR);
358 }
359
360 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
361 {
362 int result;
363
364 /*
365 * Note that irr_pending is just a hint. It will be always
366 * true with virtual interrupt delivery enabled.
367 */
368 if (!apic->irr_pending)
369 return -1;
370
371 if (apic->vcpu->arch.apicv_active)
372 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
373 result = apic_search_irr(apic);
374 ASSERT(result == -1 || result >= 16);
375
376 return result;
377 }
378
379 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
380 {
381 struct kvm_vcpu *vcpu;
382
383 vcpu = apic->vcpu;
384
385 if (unlikely(vcpu->arch.apicv_active)) {
386 /* try to update RVI */
387 apic_clear_vector(vec, apic->regs + APIC_IRR);
388 kvm_make_request(KVM_REQ_EVENT, vcpu);
389 } else {
390 apic->irr_pending = false;
391 apic_clear_vector(vec, apic->regs + APIC_IRR);
392 if (apic_search_irr(apic) != -1)
393 apic->irr_pending = true;
394 }
395 }
396
397 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
398 {
399 struct kvm_vcpu *vcpu;
400
401 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
402 return;
403
404 vcpu = apic->vcpu;
405
406 /*
407 * With APIC virtualization enabled, all caching is disabled
408 * because the processor can modify ISR under the hood. Instead
409 * just set SVI.
410 */
411 if (unlikely(vcpu->arch.apicv_active))
412 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
413 else {
414 ++apic->isr_count;
415 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
416 /*
417 * ISR (in service register) bit is set when injecting an interrupt.
418 * The highest vector is injected. Thus the latest bit set matches
419 * the highest bit in ISR.
420 */
421 apic->highest_isr_cache = vec;
422 }
423 }
424
425 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
426 {
427 int result;
428
429 /*
430 * Note that isr_count is always 1, and highest_isr_cache
431 * is always -1, with APIC virtualization enabled.
432 */
433 if (!apic->isr_count)
434 return -1;
435 if (likely(apic->highest_isr_cache != -1))
436 return apic->highest_isr_cache;
437
438 result = find_highest_vector(apic->regs + APIC_ISR);
439 ASSERT(result == -1 || result >= 16);
440
441 return result;
442 }
443
444 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
445 {
446 struct kvm_vcpu *vcpu;
447 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
448 return;
449
450 vcpu = apic->vcpu;
451
452 /*
453 * We do get here for APIC virtualization enabled if the guest
454 * uses the Hyper-V APIC enlightenment. In this case we may need
455 * to trigger a new interrupt delivery by writing the SVI field;
456 * on the other hand isr_count and highest_isr_cache are unused
457 * and must be left alone.
458 */
459 if (unlikely(vcpu->arch.apicv_active))
460 kvm_x86_ops->hwapic_isr_update(vcpu,
461 apic_find_highest_isr(apic));
462 else {
463 --apic->isr_count;
464 BUG_ON(apic->isr_count < 0);
465 apic->highest_isr_cache = -1;
466 }
467 }
468
469 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
470 {
471 /* This may race with setting of irr in __apic_accept_irq() and
472 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
473 * will cause vmexit immediately and the value will be recalculated
474 * on the next vmentry.
475 */
476 return apic_find_highest_irr(vcpu->arch.apic);
477 }
478
479 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
480 int vector, int level, int trig_mode,
481 struct dest_map *dest_map);
482
483 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
484 struct dest_map *dest_map)
485 {
486 struct kvm_lapic *apic = vcpu->arch.apic;
487
488 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
489 irq->level, irq->trig_mode, dest_map);
490 }
491
492 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
493 {
494
495 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
496 sizeof(val));
497 }
498
499 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
500 {
501
502 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
503 sizeof(*val));
504 }
505
506 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
507 {
508 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
509 }
510
511 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
512 {
513 u8 val;
514 if (pv_eoi_get_user(vcpu, &val) < 0)
515 apic_debug("Can't read EOI MSR value: 0x%llx\n",
516 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
517 return val & 0x1;
518 }
519
520 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
521 {
522 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
523 apic_debug("Can't set EOI MSR value: 0x%llx\n",
524 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
525 return;
526 }
527 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
528 }
529
530 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
531 {
532 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
533 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
534 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
535 return;
536 }
537 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
538 }
539
540 static void apic_update_ppr(struct kvm_lapic *apic)
541 {
542 u32 tpr, isrv, ppr, old_ppr;
543 int isr;
544
545 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
546 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
547 isr = apic_find_highest_isr(apic);
548 isrv = (isr != -1) ? isr : 0;
549
550 if ((tpr & 0xf0) >= (isrv & 0xf0))
551 ppr = tpr & 0xff;
552 else
553 ppr = isrv & 0xf0;
554
555 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
556 apic, ppr, isr, isrv);
557
558 if (old_ppr != ppr) {
559 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
560 if (ppr < old_ppr)
561 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
562 }
563 }
564
565 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
566 {
567 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
568 apic_update_ppr(apic);
569 }
570
571 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
572 {
573 if (apic_x2apic_mode(apic))
574 return mda == X2APIC_BROADCAST;
575
576 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
577 }
578
579 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
580 {
581 if (kvm_apic_broadcast(apic, mda))
582 return true;
583
584 if (apic_x2apic_mode(apic))
585 return mda == kvm_apic_id(apic);
586
587 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
588 }
589
590 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
591 {
592 u32 logical_id;
593
594 if (kvm_apic_broadcast(apic, mda))
595 return true;
596
597 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
598
599 if (apic_x2apic_mode(apic))
600 return ((logical_id >> 16) == (mda >> 16))
601 && (logical_id & mda & 0xffff) != 0;
602
603 logical_id = GET_APIC_LOGICAL_ID(logical_id);
604 mda = GET_APIC_DEST_FIELD(mda);
605
606 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
607 case APIC_DFR_FLAT:
608 return (logical_id & mda) != 0;
609 case APIC_DFR_CLUSTER:
610 return ((logical_id >> 4) == (mda >> 4))
611 && (logical_id & mda & 0xf) != 0;
612 default:
613 apic_debug("Bad DFR vcpu %d: %08x\n",
614 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
615 return false;
616 }
617 }
618
619 /* KVM APIC implementation has two quirks
620 * - dest always begins at 0 while xAPIC MDA has offset 24,
621 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
622 */
623 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
624 struct kvm_lapic *target)
625 {
626 bool ipi = source != NULL;
627 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
628
629 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
630 return X2APIC_BROADCAST;
631
632 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
633 }
634
635 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
636 int short_hand, unsigned int dest, int dest_mode)
637 {
638 struct kvm_lapic *target = vcpu->arch.apic;
639 u32 mda = kvm_apic_mda(dest, source, target);
640
641 apic_debug("target %p, source %p, dest 0x%x, "
642 "dest_mode 0x%x, short_hand 0x%x\n",
643 target, source, dest, dest_mode, short_hand);
644
645 ASSERT(target);
646 switch (short_hand) {
647 case APIC_DEST_NOSHORT:
648 if (dest_mode == APIC_DEST_PHYSICAL)
649 return kvm_apic_match_physical_addr(target, mda);
650 else
651 return kvm_apic_match_logical_addr(target, mda);
652 case APIC_DEST_SELF:
653 return target == source;
654 case APIC_DEST_ALLINC:
655 return true;
656 case APIC_DEST_ALLBUT:
657 return target != source;
658 default:
659 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
660 short_hand);
661 return false;
662 }
663 }
664 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
665
666 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
667 const unsigned long *bitmap, u32 bitmap_size)
668 {
669 u32 mod;
670 int i, idx = -1;
671
672 mod = vector % dest_vcpus;
673
674 for (i = 0; i <= mod; i++) {
675 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
676 BUG_ON(idx == bitmap_size);
677 }
678
679 return idx;
680 }
681
682 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
683 {
684 if (!kvm->arch.disabled_lapic_found) {
685 kvm->arch.disabled_lapic_found = true;
686 printk(KERN_INFO
687 "Disabled LAPIC found during irq injection\n");
688 }
689 }
690
691 /* Return true if the interrupt can be handled by using *bitmap as index mask
692 * for valid destinations in *dst array.
693 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
694 * Note: we may have zero kvm_lapic destinations when we return true, which
695 * means that the interrupt should be dropped. In this case, *bitmap would be
696 * zero and *dst undefined.
697 */
698 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
699 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
700 struct kvm_apic_map *map, struct kvm_lapic ***dst,
701 unsigned long *bitmap)
702 {
703 int i, lowest;
704 bool x2apic_ipi;
705
706 if (irq->shorthand == APIC_DEST_SELF && src) {
707 *dst = src;
708 *bitmap = 1;
709 return true;
710 } else if (irq->shorthand)
711 return false;
712
713 x2apic_ipi = src && *src && apic_x2apic_mode(*src);
714 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
715 return false;
716
717 if (!map)
718 return false;
719
720 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
721 if (irq->dest_id > map->max_apic_id) {
722 *bitmap = 0;
723 } else {
724 *dst = &map->phys_map[irq->dest_id];
725 *bitmap = 1;
726 }
727 return true;
728 }
729
730 *bitmap = 0;
731 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
732 (u16 *)bitmap))
733 return false;
734
735 if (!kvm_lowest_prio_delivery(irq))
736 return true;
737
738 if (!kvm_vector_hashing_enabled()) {
739 lowest = -1;
740 for_each_set_bit(i, bitmap, 16) {
741 if (!(*dst)[i])
742 continue;
743 if (lowest < 0)
744 lowest = i;
745 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
746 (*dst)[lowest]->vcpu) < 0)
747 lowest = i;
748 }
749 } else {
750 if (!*bitmap)
751 return true;
752
753 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
754 bitmap, 16);
755
756 if (!(*dst)[lowest]) {
757 kvm_apic_disabled_lapic_found(kvm);
758 *bitmap = 0;
759 return true;
760 }
761 }
762
763 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
764
765 return true;
766 }
767
768 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
769 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
770 {
771 struct kvm_apic_map *map;
772 unsigned long bitmap;
773 struct kvm_lapic **dst = NULL;
774 int i;
775 bool ret;
776
777 *r = -1;
778
779 if (irq->shorthand == APIC_DEST_SELF) {
780 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
781 return true;
782 }
783
784 rcu_read_lock();
785 map = rcu_dereference(kvm->arch.apic_map);
786
787 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
788 if (ret)
789 for_each_set_bit(i, &bitmap, 16) {
790 if (!dst[i])
791 continue;
792 if (*r < 0)
793 *r = 0;
794 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
795 }
796
797 rcu_read_unlock();
798 return ret;
799 }
800
801 /*
802 * This routine tries to handler interrupts in posted mode, here is how
803 * it deals with different cases:
804 * - For single-destination interrupts, handle it in posted mode
805 * - Else if vector hashing is enabled and it is a lowest-priority
806 * interrupt, handle it in posted mode and use the following mechanism
807 * to find the destinaiton vCPU.
808 * 1. For lowest-priority interrupts, store all the possible
809 * destination vCPUs in an array.
810 * 2. Use "guest vector % max number of destination vCPUs" to find
811 * the right destination vCPU in the array for the lowest-priority
812 * interrupt.
813 * - Otherwise, use remapped mode to inject the interrupt.
814 */
815 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
816 struct kvm_vcpu **dest_vcpu)
817 {
818 struct kvm_apic_map *map;
819 unsigned long bitmap;
820 struct kvm_lapic **dst = NULL;
821 bool ret = false;
822
823 if (irq->shorthand)
824 return false;
825
826 rcu_read_lock();
827 map = rcu_dereference(kvm->arch.apic_map);
828
829 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
830 hweight16(bitmap) == 1) {
831 unsigned long i = find_first_bit(&bitmap, 16);
832
833 if (dst[i]) {
834 *dest_vcpu = dst[i]->vcpu;
835 ret = true;
836 }
837 }
838
839 rcu_read_unlock();
840 return ret;
841 }
842
843 /*
844 * Add a pending IRQ into lapic.
845 * Return 1 if successfully added and 0 if discarded.
846 */
847 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
848 int vector, int level, int trig_mode,
849 struct dest_map *dest_map)
850 {
851 int result = 0;
852 struct kvm_vcpu *vcpu = apic->vcpu;
853
854 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
855 trig_mode, vector);
856 switch (delivery_mode) {
857 case APIC_DM_LOWEST:
858 vcpu->arch.apic_arb_prio++;
859 case APIC_DM_FIXED:
860 if (unlikely(trig_mode && !level))
861 break;
862
863 /* FIXME add logic for vcpu on reset */
864 if (unlikely(!apic_enabled(apic)))
865 break;
866
867 result = 1;
868
869 if (dest_map) {
870 __set_bit(vcpu->vcpu_id, dest_map->map);
871 dest_map->vectors[vcpu->vcpu_id] = vector;
872 }
873
874 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
875 if (trig_mode)
876 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
877 else
878 apic_clear_vector(vector, apic->regs + APIC_TMR);
879 }
880
881 if (vcpu->arch.apicv_active)
882 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
883 else {
884 kvm_lapic_set_irr(vector, apic);
885
886 kvm_make_request(KVM_REQ_EVENT, vcpu);
887 kvm_vcpu_kick(vcpu);
888 }
889 break;
890
891 case APIC_DM_REMRD:
892 result = 1;
893 vcpu->arch.pv.pv_unhalted = 1;
894 kvm_make_request(KVM_REQ_EVENT, vcpu);
895 kvm_vcpu_kick(vcpu);
896 break;
897
898 case APIC_DM_SMI:
899 result = 1;
900 kvm_make_request(KVM_REQ_SMI, vcpu);
901 kvm_vcpu_kick(vcpu);
902 break;
903
904 case APIC_DM_NMI:
905 result = 1;
906 kvm_inject_nmi(vcpu);
907 kvm_vcpu_kick(vcpu);
908 break;
909
910 case APIC_DM_INIT:
911 if (!trig_mode || level) {
912 result = 1;
913 /* assumes that there are only KVM_APIC_INIT/SIPI */
914 apic->pending_events = (1UL << KVM_APIC_INIT);
915 /* make sure pending_events is visible before sending
916 * the request */
917 smp_wmb();
918 kvm_make_request(KVM_REQ_EVENT, vcpu);
919 kvm_vcpu_kick(vcpu);
920 } else {
921 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
922 vcpu->vcpu_id);
923 }
924 break;
925
926 case APIC_DM_STARTUP:
927 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
928 vcpu->vcpu_id, vector);
929 result = 1;
930 apic->sipi_vector = vector;
931 /* make sure sipi_vector is visible for the receiver */
932 smp_wmb();
933 set_bit(KVM_APIC_SIPI, &apic->pending_events);
934 kvm_make_request(KVM_REQ_EVENT, vcpu);
935 kvm_vcpu_kick(vcpu);
936 break;
937
938 case APIC_DM_EXTINT:
939 /*
940 * Should only be called by kvm_apic_local_deliver() with LVT0,
941 * before NMI watchdog was enabled. Already handled by
942 * kvm_apic_accept_pic_intr().
943 */
944 break;
945
946 default:
947 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
948 delivery_mode);
949 break;
950 }
951 return result;
952 }
953
954 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
955 {
956 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
957 }
958
959 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
960 {
961 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
962 }
963
964 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
965 {
966 int trigger_mode;
967
968 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
969 if (!kvm_ioapic_handles_vector(apic, vector))
970 return;
971
972 /* Request a KVM exit to inform the userspace IOAPIC. */
973 if (irqchip_split(apic->vcpu->kvm)) {
974 apic->vcpu->arch.pending_ioapic_eoi = vector;
975 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
976 return;
977 }
978
979 if (apic_test_vector(vector, apic->regs + APIC_TMR))
980 trigger_mode = IOAPIC_LEVEL_TRIG;
981 else
982 trigger_mode = IOAPIC_EDGE_TRIG;
983
984 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
985 }
986
987 static int apic_set_eoi(struct kvm_lapic *apic)
988 {
989 int vector = apic_find_highest_isr(apic);
990
991 trace_kvm_eoi(apic, vector);
992
993 /*
994 * Not every write EOI will has corresponding ISR,
995 * one example is when Kernel check timer on setup_IO_APIC
996 */
997 if (vector == -1)
998 return vector;
999
1000 apic_clear_isr(vector, apic);
1001 apic_update_ppr(apic);
1002
1003 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1004 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1005
1006 kvm_ioapic_send_eoi(apic, vector);
1007 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1008 return vector;
1009 }
1010
1011 /*
1012 * this interface assumes a trap-like exit, which has already finished
1013 * desired side effect including vISR and vPPR update.
1014 */
1015 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1016 {
1017 struct kvm_lapic *apic = vcpu->arch.apic;
1018
1019 trace_kvm_eoi(apic, vector);
1020
1021 kvm_ioapic_send_eoi(apic, vector);
1022 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1023 }
1024 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1025
1026 static void apic_send_ipi(struct kvm_lapic *apic)
1027 {
1028 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1029 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1030 struct kvm_lapic_irq irq;
1031
1032 irq.vector = icr_low & APIC_VECTOR_MASK;
1033 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1034 irq.dest_mode = icr_low & APIC_DEST_MASK;
1035 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1036 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1037 irq.shorthand = icr_low & APIC_SHORT_MASK;
1038 irq.msi_redir_hint = false;
1039 if (apic_x2apic_mode(apic))
1040 irq.dest_id = icr_high;
1041 else
1042 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1043
1044 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1045
1046 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1047 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1048 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1049 "msi_redir_hint 0x%x\n",
1050 icr_high, icr_low, irq.shorthand, irq.dest_id,
1051 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1052 irq.vector, irq.msi_redir_hint);
1053
1054 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1055 }
1056
1057 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1058 {
1059 ktime_t remaining;
1060 s64 ns;
1061 u32 tmcct;
1062
1063 ASSERT(apic != NULL);
1064
1065 /* if initial count is 0, current count should also be 0 */
1066 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1067 apic->lapic_timer.period == 0)
1068 return 0;
1069
1070 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1071 if (ktime_to_ns(remaining) < 0)
1072 remaining = ktime_set(0, 0);
1073
1074 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1075 tmcct = div64_u64(ns,
1076 (APIC_BUS_CYCLE_NS * apic->divide_count));
1077
1078 return tmcct;
1079 }
1080
1081 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1082 {
1083 struct kvm_vcpu *vcpu = apic->vcpu;
1084 struct kvm_run *run = vcpu->run;
1085
1086 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1087 run->tpr_access.rip = kvm_rip_read(vcpu);
1088 run->tpr_access.is_write = write;
1089 }
1090
1091 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1092 {
1093 if (apic->vcpu->arch.tpr_access_reporting)
1094 __report_tpr_access(apic, write);
1095 }
1096
1097 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1098 {
1099 u32 val = 0;
1100
1101 if (offset >= LAPIC_MMIO_LENGTH)
1102 return 0;
1103
1104 switch (offset) {
1105 case APIC_ARBPRI:
1106 apic_debug("Access APIC ARBPRI register which is for P6\n");
1107 break;
1108
1109 case APIC_TMCCT: /* Timer CCR */
1110 if (apic_lvtt_tscdeadline(apic))
1111 return 0;
1112
1113 val = apic_get_tmcct(apic);
1114 break;
1115 case APIC_PROCPRI:
1116 apic_update_ppr(apic);
1117 val = kvm_lapic_get_reg(apic, offset);
1118 break;
1119 case APIC_TASKPRI:
1120 report_tpr_access(apic, false);
1121 /* fall thru */
1122 default:
1123 val = kvm_lapic_get_reg(apic, offset);
1124 break;
1125 }
1126
1127 return val;
1128 }
1129
1130 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1131 {
1132 return container_of(dev, struct kvm_lapic, dev);
1133 }
1134
1135 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1136 void *data)
1137 {
1138 unsigned char alignment = offset & 0xf;
1139 u32 result;
1140 /* this bitmask has a bit cleared for each reserved register */
1141 static const u64 rmask = 0x43ff01ffffffe70cULL;
1142
1143 if ((alignment + len) > 4) {
1144 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1145 offset, len);
1146 return 1;
1147 }
1148
1149 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1150 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1151 offset);
1152 return 1;
1153 }
1154
1155 result = __apic_read(apic, offset & ~0xf);
1156
1157 trace_kvm_apic_read(offset, result);
1158
1159 switch (len) {
1160 case 1:
1161 case 2:
1162 case 4:
1163 memcpy(data, (char *)&result + alignment, len);
1164 break;
1165 default:
1166 printk(KERN_ERR "Local APIC read with len = %x, "
1167 "should be 1,2, or 4 instead\n", len);
1168 break;
1169 }
1170 return 0;
1171 }
1172 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1173
1174 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1175 {
1176 return kvm_apic_hw_enabled(apic) &&
1177 addr >= apic->base_address &&
1178 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1179 }
1180
1181 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1182 gpa_t address, int len, void *data)
1183 {
1184 struct kvm_lapic *apic = to_lapic(this);
1185 u32 offset = address - apic->base_address;
1186
1187 if (!apic_mmio_in_range(apic, address))
1188 return -EOPNOTSUPP;
1189
1190 kvm_lapic_reg_read(apic, offset, len, data);
1191
1192 return 0;
1193 }
1194
1195 static void update_divide_count(struct kvm_lapic *apic)
1196 {
1197 u32 tmp1, tmp2, tdcr;
1198
1199 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1200 tmp1 = tdcr & 0xf;
1201 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1202 apic->divide_count = 0x1 << (tmp2 & 0x7);
1203
1204 apic_debug("timer divide count is 0x%x\n",
1205 apic->divide_count);
1206 }
1207
1208 static void apic_update_lvtt(struct kvm_lapic *apic)
1209 {
1210 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1211 apic->lapic_timer.timer_mode_mask;
1212
1213 if (apic->lapic_timer.timer_mode != timer_mode) {
1214 apic->lapic_timer.timer_mode = timer_mode;
1215 hrtimer_cancel(&apic->lapic_timer.timer);
1216 }
1217 }
1218
1219 static void apic_timer_expired(struct kvm_lapic *apic)
1220 {
1221 struct kvm_vcpu *vcpu = apic->vcpu;
1222 struct swait_queue_head *q = &vcpu->wq;
1223 struct kvm_timer *ktimer = &apic->lapic_timer;
1224
1225 if (atomic_read(&apic->lapic_timer.pending))
1226 return;
1227
1228 atomic_inc(&apic->lapic_timer.pending);
1229 kvm_set_pending_timer(vcpu);
1230
1231 if (swait_active(q))
1232 swake_up(q);
1233
1234 if (apic_lvtt_tscdeadline(apic))
1235 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1236 }
1237
1238 /*
1239 * On APICv, this test will cause a busy wait
1240 * during a higher-priority task.
1241 */
1242
1243 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1244 {
1245 struct kvm_lapic *apic = vcpu->arch.apic;
1246 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1247
1248 if (kvm_apic_hw_enabled(apic)) {
1249 int vec = reg & APIC_VECTOR_MASK;
1250 void *bitmap = apic->regs + APIC_ISR;
1251
1252 if (vcpu->arch.apicv_active)
1253 bitmap = apic->regs + APIC_IRR;
1254
1255 if (apic_test_vector(vec, bitmap))
1256 return true;
1257 }
1258 return false;
1259 }
1260
1261 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1262 {
1263 struct kvm_lapic *apic = vcpu->arch.apic;
1264 u64 guest_tsc, tsc_deadline;
1265
1266 if (!lapic_in_kernel(vcpu))
1267 return;
1268
1269 if (apic->lapic_timer.expired_tscdeadline == 0)
1270 return;
1271
1272 if (!lapic_timer_int_injected(vcpu))
1273 return;
1274
1275 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1276 apic->lapic_timer.expired_tscdeadline = 0;
1277 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1278 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1279
1280 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1281 if (guest_tsc < tsc_deadline)
1282 __delay(tsc_deadline - guest_tsc);
1283 }
1284
1285 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1286 {
1287 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1288 u64 ns = 0;
1289 ktime_t expire;
1290 struct kvm_vcpu *vcpu = apic->vcpu;
1291 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1292 unsigned long flags;
1293 ktime_t now;
1294
1295 if (unlikely(!tscdeadline || !this_tsc_khz))
1296 return;
1297
1298 local_irq_save(flags);
1299
1300 now = apic->lapic_timer.timer.base->get_time();
1301 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1302 if (likely(tscdeadline > guest_tsc)) {
1303 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1304 do_div(ns, this_tsc_khz);
1305 expire = ktime_add_ns(now, ns);
1306 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1307 hrtimer_start(&apic->lapic_timer.timer,
1308 expire, HRTIMER_MODE_ABS_PINNED);
1309 } else
1310 apic_timer_expired(apic);
1311
1312 local_irq_restore(flags);
1313 }
1314
1315 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1316 {
1317 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1318 }
1319 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1320
1321 static void cancel_hv_tscdeadline(struct kvm_lapic *apic)
1322 {
1323 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1324 apic->lapic_timer.hv_timer_in_use = false;
1325 }
1326
1327 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1328 {
1329 struct kvm_lapic *apic = vcpu->arch.apic;
1330
1331 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1332 WARN_ON(swait_active(&vcpu->wq));
1333 cancel_hv_tscdeadline(apic);
1334 apic_timer_expired(apic);
1335 }
1336 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1337
1338 static bool start_hv_tscdeadline(struct kvm_lapic *apic)
1339 {
1340 u64 tscdeadline = apic->lapic_timer.tscdeadline;
1341
1342 if (atomic_read(&apic->lapic_timer.pending) ||
1343 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1344 if (apic->lapic_timer.hv_timer_in_use)
1345 cancel_hv_tscdeadline(apic);
1346 } else {
1347 apic->lapic_timer.hv_timer_in_use = true;
1348 hrtimer_cancel(&apic->lapic_timer.timer);
1349
1350 /* In case the sw timer triggered in the window */
1351 if (atomic_read(&apic->lapic_timer.pending))
1352 cancel_hv_tscdeadline(apic);
1353 }
1354 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1355 apic->lapic_timer.hv_timer_in_use);
1356 return apic->lapic_timer.hv_timer_in_use;
1357 }
1358
1359 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1360 {
1361 struct kvm_lapic *apic = vcpu->arch.apic;
1362
1363 WARN_ON(apic->lapic_timer.hv_timer_in_use);
1364
1365 if (apic_lvtt_tscdeadline(apic))
1366 start_hv_tscdeadline(apic);
1367 }
1368 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1369
1370 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1371 {
1372 struct kvm_lapic *apic = vcpu->arch.apic;
1373
1374 /* Possibly the TSC deadline timer is not enabled yet */
1375 if (!apic->lapic_timer.hv_timer_in_use)
1376 return;
1377
1378 cancel_hv_tscdeadline(apic);
1379
1380 if (atomic_read(&apic->lapic_timer.pending))
1381 return;
1382
1383 start_sw_tscdeadline(apic);
1384 }
1385 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1386
1387 static void start_apic_timer(struct kvm_lapic *apic)
1388 {
1389 ktime_t now;
1390
1391 atomic_set(&apic->lapic_timer.pending, 0);
1392
1393 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1394 /* lapic timer in oneshot or periodic mode */
1395 now = apic->lapic_timer.timer.base->get_time();
1396 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1397 * APIC_BUS_CYCLE_NS * apic->divide_count;
1398
1399 if (!apic->lapic_timer.period)
1400 return;
1401 /*
1402 * Do not allow the guest to program periodic timers with small
1403 * interval, since the hrtimers are not throttled by the host
1404 * scheduler.
1405 */
1406 if (apic_lvtt_period(apic)) {
1407 s64 min_period = min_timer_period_us * 1000LL;
1408
1409 if (apic->lapic_timer.period < min_period) {
1410 pr_info_ratelimited(
1411 "kvm: vcpu %i: requested %lld ns "
1412 "lapic timer period limited to %lld ns\n",
1413 apic->vcpu->vcpu_id,
1414 apic->lapic_timer.period, min_period);
1415 apic->lapic_timer.period = min_period;
1416 }
1417 }
1418
1419 hrtimer_start(&apic->lapic_timer.timer,
1420 ktime_add_ns(now, apic->lapic_timer.period),
1421 HRTIMER_MODE_ABS_PINNED);
1422
1423 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1424 PRIx64 ", "
1425 "timer initial count 0x%x, period %lldns, "
1426 "expire @ 0x%016" PRIx64 ".\n", __func__,
1427 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1428 kvm_lapic_get_reg(apic, APIC_TMICT),
1429 apic->lapic_timer.period,
1430 ktime_to_ns(ktime_add_ns(now,
1431 apic->lapic_timer.period)));
1432 } else if (apic_lvtt_tscdeadline(apic)) {
1433 if (!(kvm_x86_ops->set_hv_timer && start_hv_tscdeadline(apic)))
1434 start_sw_tscdeadline(apic);
1435 }
1436 }
1437
1438 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1439 {
1440 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1441
1442 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1443 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1444 if (lvt0_in_nmi_mode) {
1445 apic_debug("Receive NMI setting on APIC_LVT0 "
1446 "for cpu %d\n", apic->vcpu->vcpu_id);
1447 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1448 } else
1449 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1450 }
1451 }
1452
1453 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1454 {
1455 int ret = 0;
1456
1457 trace_kvm_apic_write(reg, val);
1458
1459 switch (reg) {
1460 case APIC_ID: /* Local APIC ID */
1461 if (!apic_x2apic_mode(apic))
1462 kvm_apic_set_xapic_id(apic, val >> 24);
1463 else
1464 ret = 1;
1465 break;
1466
1467 case APIC_TASKPRI:
1468 report_tpr_access(apic, true);
1469 apic_set_tpr(apic, val & 0xff);
1470 break;
1471
1472 case APIC_EOI:
1473 apic_set_eoi(apic);
1474 break;
1475
1476 case APIC_LDR:
1477 if (!apic_x2apic_mode(apic))
1478 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1479 else
1480 ret = 1;
1481 break;
1482
1483 case APIC_DFR:
1484 if (!apic_x2apic_mode(apic)) {
1485 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1486 recalculate_apic_map(apic->vcpu->kvm);
1487 } else
1488 ret = 1;
1489 break;
1490
1491 case APIC_SPIV: {
1492 u32 mask = 0x3ff;
1493 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1494 mask |= APIC_SPIV_DIRECTED_EOI;
1495 apic_set_spiv(apic, val & mask);
1496 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1497 int i;
1498 u32 lvt_val;
1499
1500 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1501 lvt_val = kvm_lapic_get_reg(apic,
1502 APIC_LVTT + 0x10 * i);
1503 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1504 lvt_val | APIC_LVT_MASKED);
1505 }
1506 apic_update_lvtt(apic);
1507 atomic_set(&apic->lapic_timer.pending, 0);
1508
1509 }
1510 break;
1511 }
1512 case APIC_ICR:
1513 /* No delay here, so we always clear the pending bit */
1514 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1515 apic_send_ipi(apic);
1516 break;
1517
1518 case APIC_ICR2:
1519 if (!apic_x2apic_mode(apic))
1520 val &= 0xff000000;
1521 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1522 break;
1523
1524 case APIC_LVT0:
1525 apic_manage_nmi_watchdog(apic, val);
1526 case APIC_LVTTHMR:
1527 case APIC_LVTPC:
1528 case APIC_LVT1:
1529 case APIC_LVTERR:
1530 /* TODO: Check vector */
1531 if (!kvm_apic_sw_enabled(apic))
1532 val |= APIC_LVT_MASKED;
1533
1534 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1535 kvm_lapic_set_reg(apic, reg, val);
1536
1537 break;
1538
1539 case APIC_LVTT:
1540 if (!kvm_apic_sw_enabled(apic))
1541 val |= APIC_LVT_MASKED;
1542 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1543 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1544 apic_update_lvtt(apic);
1545 break;
1546
1547 case APIC_TMICT:
1548 if (apic_lvtt_tscdeadline(apic))
1549 break;
1550
1551 hrtimer_cancel(&apic->lapic_timer.timer);
1552 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1553 start_apic_timer(apic);
1554 break;
1555
1556 case APIC_TDCR:
1557 if (val & 4)
1558 apic_debug("KVM_WRITE:TDCR %x\n", val);
1559 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1560 update_divide_count(apic);
1561 break;
1562
1563 case APIC_ESR:
1564 if (apic_x2apic_mode(apic) && val != 0) {
1565 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1566 ret = 1;
1567 }
1568 break;
1569
1570 case APIC_SELF_IPI:
1571 if (apic_x2apic_mode(apic)) {
1572 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1573 } else
1574 ret = 1;
1575 break;
1576 default:
1577 ret = 1;
1578 break;
1579 }
1580 if (ret)
1581 apic_debug("Local APIC Write to read-only register %x\n", reg);
1582 return ret;
1583 }
1584 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1585
1586 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1587 gpa_t address, int len, const void *data)
1588 {
1589 struct kvm_lapic *apic = to_lapic(this);
1590 unsigned int offset = address - apic->base_address;
1591 u32 val;
1592
1593 if (!apic_mmio_in_range(apic, address))
1594 return -EOPNOTSUPP;
1595
1596 /*
1597 * APIC register must be aligned on 128-bits boundary.
1598 * 32/64/128 bits registers must be accessed thru 32 bits.
1599 * Refer SDM 8.4.1
1600 */
1601 if (len != 4 || (offset & 0xf)) {
1602 /* Don't shout loud, $infamous_os would cause only noise. */
1603 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1604 return 0;
1605 }
1606
1607 val = *(u32*)data;
1608
1609 /* too common printing */
1610 if (offset != APIC_EOI)
1611 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1612 "0x%x\n", __func__, offset, len, val);
1613
1614 kvm_lapic_reg_write(apic, offset & 0xff0, val);
1615
1616 return 0;
1617 }
1618
1619 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1620 {
1621 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1622 }
1623 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1624
1625 /* emulate APIC access in a trap manner */
1626 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1627 {
1628 u32 val = 0;
1629
1630 /* hw has done the conditional check and inst decode */
1631 offset &= 0xff0;
1632
1633 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1634
1635 /* TODO: optimize to just emulate side effect w/o one more write */
1636 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1637 }
1638 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1639
1640 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1641 {
1642 struct kvm_lapic *apic = vcpu->arch.apic;
1643
1644 if (!vcpu->arch.apic)
1645 return;
1646
1647 hrtimer_cancel(&apic->lapic_timer.timer);
1648
1649 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1650 static_key_slow_dec_deferred(&apic_hw_disabled);
1651
1652 if (!apic->sw_enabled)
1653 static_key_slow_dec_deferred(&apic_sw_disabled);
1654
1655 if (apic->regs)
1656 free_page((unsigned long)apic->regs);
1657
1658 kfree(apic);
1659 }
1660
1661 /*
1662 *----------------------------------------------------------------------
1663 * LAPIC interface
1664 *----------------------------------------------------------------------
1665 */
1666
1667 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1668 {
1669 struct kvm_lapic *apic = vcpu->arch.apic;
1670
1671 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1672 apic_lvtt_period(apic))
1673 return 0;
1674
1675 return apic->lapic_timer.tscdeadline;
1676 }
1677
1678 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1679 {
1680 struct kvm_lapic *apic = vcpu->arch.apic;
1681
1682 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1683 apic_lvtt_period(apic))
1684 return;
1685
1686 hrtimer_cancel(&apic->lapic_timer.timer);
1687 apic->lapic_timer.tscdeadline = data;
1688 start_apic_timer(apic);
1689 }
1690
1691 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1692 {
1693 struct kvm_lapic *apic = vcpu->arch.apic;
1694
1695 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1696 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1697 }
1698
1699 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1700 {
1701 u64 tpr;
1702
1703 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1704
1705 return (tpr & 0xf0) >> 4;
1706 }
1707
1708 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1709 {
1710 u64 old_value = vcpu->arch.apic_base;
1711 struct kvm_lapic *apic = vcpu->arch.apic;
1712
1713 if (!apic) {
1714 value |= MSR_IA32_APICBASE_BSP;
1715 vcpu->arch.apic_base = value;
1716 return;
1717 }
1718
1719 vcpu->arch.apic_base = value;
1720
1721 /* update jump label if enable bit changes */
1722 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1723 if (value & MSR_IA32_APICBASE_ENABLE) {
1724 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1725 static_key_slow_dec_deferred(&apic_hw_disabled);
1726 } else
1727 static_key_slow_inc(&apic_hw_disabled.key);
1728 recalculate_apic_map(vcpu->kvm);
1729 }
1730
1731 if ((old_value ^ value) & X2APIC_ENABLE) {
1732 if (value & X2APIC_ENABLE) {
1733 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1734 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1735 } else
1736 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1737 }
1738
1739 apic->base_address = apic->vcpu->arch.apic_base &
1740 MSR_IA32_APICBASE_BASE;
1741
1742 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1743 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1744 pr_warn_once("APIC base relocation is unsupported by KVM");
1745
1746 /* with FSB delivery interrupt, we can restart APIC functionality */
1747 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1748 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1749
1750 }
1751
1752 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1753 {
1754 struct kvm_lapic *apic;
1755 int i;
1756
1757 apic_debug("%s\n", __func__);
1758
1759 ASSERT(vcpu);
1760 apic = vcpu->arch.apic;
1761 ASSERT(apic != NULL);
1762
1763 /* Stop the timer in case it's a reset to an active apic */
1764 hrtimer_cancel(&apic->lapic_timer.timer);
1765
1766 if (!init_event)
1767 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1768 kvm_apic_set_version(apic->vcpu);
1769
1770 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1771 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1772 apic_update_lvtt(apic);
1773 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1774 kvm_lapic_set_reg(apic, APIC_LVT0,
1775 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1776 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1777
1778 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1779 apic_set_spiv(apic, 0xff);
1780 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1781 if (!apic_x2apic_mode(apic))
1782 kvm_apic_set_ldr(apic, 0);
1783 kvm_lapic_set_reg(apic, APIC_ESR, 0);
1784 kvm_lapic_set_reg(apic, APIC_ICR, 0);
1785 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1786 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1787 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1788 for (i = 0; i < 8; i++) {
1789 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1790 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1791 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1792 }
1793 apic->irr_pending = vcpu->arch.apicv_active;
1794 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1795 apic->highest_isr_cache = -1;
1796 update_divide_count(apic);
1797 atomic_set(&apic->lapic_timer.pending, 0);
1798 if (kvm_vcpu_is_bsp(vcpu))
1799 kvm_lapic_set_base(vcpu,
1800 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1801 vcpu->arch.pv_eoi.msr_val = 0;
1802 apic_update_ppr(apic);
1803
1804 vcpu->arch.apic_arb_prio = 0;
1805 vcpu->arch.apic_attention = 0;
1806
1807 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1808 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1809 vcpu, kvm_apic_id(apic),
1810 vcpu->arch.apic_base, apic->base_address);
1811 }
1812
1813 /*
1814 *----------------------------------------------------------------------
1815 * timer interface
1816 *----------------------------------------------------------------------
1817 */
1818
1819 static bool lapic_is_periodic(struct kvm_lapic *apic)
1820 {
1821 return apic_lvtt_period(apic);
1822 }
1823
1824 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1825 {
1826 struct kvm_lapic *apic = vcpu->arch.apic;
1827
1828 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1829 return atomic_read(&apic->lapic_timer.pending);
1830
1831 return 0;
1832 }
1833
1834 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1835 {
1836 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1837 int vector, mode, trig_mode;
1838
1839 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1840 vector = reg & APIC_VECTOR_MASK;
1841 mode = reg & APIC_MODE_MASK;
1842 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1843 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1844 NULL);
1845 }
1846 return 0;
1847 }
1848
1849 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1850 {
1851 struct kvm_lapic *apic = vcpu->arch.apic;
1852
1853 if (apic)
1854 kvm_apic_local_deliver(apic, APIC_LVT0);
1855 }
1856
1857 static const struct kvm_io_device_ops apic_mmio_ops = {
1858 .read = apic_mmio_read,
1859 .write = apic_mmio_write,
1860 };
1861
1862 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1863 {
1864 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1865 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1866
1867 apic_timer_expired(apic);
1868
1869 if (lapic_is_periodic(apic)) {
1870 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1871 return HRTIMER_RESTART;
1872 } else
1873 return HRTIMER_NORESTART;
1874 }
1875
1876 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1877 {
1878 struct kvm_lapic *apic;
1879
1880 ASSERT(vcpu != NULL);
1881 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1882
1883 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1884 if (!apic)
1885 goto nomem;
1886
1887 vcpu->arch.apic = apic;
1888
1889 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1890 if (!apic->regs) {
1891 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1892 vcpu->vcpu_id);
1893 goto nomem_free_apic;
1894 }
1895 apic->vcpu = vcpu;
1896
1897 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1898 HRTIMER_MODE_ABS_PINNED);
1899 apic->lapic_timer.timer.function = apic_timer_fn;
1900
1901 /*
1902 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1903 * thinking that APIC satet has changed.
1904 */
1905 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1906 kvm_lapic_set_base(vcpu,
1907 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1908
1909 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1910 kvm_lapic_reset(vcpu, false);
1911 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1912
1913 return 0;
1914 nomem_free_apic:
1915 kfree(apic);
1916 nomem:
1917 return -ENOMEM;
1918 }
1919
1920 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1921 {
1922 struct kvm_lapic *apic = vcpu->arch.apic;
1923 int highest_irr;
1924
1925 if (!apic_enabled(apic))
1926 return -1;
1927
1928 apic_update_ppr(apic);
1929 highest_irr = apic_find_highest_irr(apic);
1930 if ((highest_irr == -1) ||
1931 ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
1932 return -1;
1933 return highest_irr;
1934 }
1935
1936 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1937 {
1938 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
1939 int r = 0;
1940
1941 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1942 r = 1;
1943 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1944 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1945 r = 1;
1946 return r;
1947 }
1948
1949 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1950 {
1951 struct kvm_lapic *apic = vcpu->arch.apic;
1952
1953 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1954 kvm_apic_local_deliver(apic, APIC_LVTT);
1955 if (apic_lvtt_tscdeadline(apic))
1956 apic->lapic_timer.tscdeadline = 0;
1957 atomic_set(&apic->lapic_timer.pending, 0);
1958 }
1959 }
1960
1961 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1962 {
1963 int vector = kvm_apic_has_interrupt(vcpu);
1964 struct kvm_lapic *apic = vcpu->arch.apic;
1965
1966 if (vector == -1)
1967 return -1;
1968
1969 /*
1970 * We get here even with APIC virtualization enabled, if doing
1971 * nested virtualization and L1 runs with the "acknowledge interrupt
1972 * on exit" mode. Then we cannot inject the interrupt via RVI,
1973 * because the process would deliver it through the IDT.
1974 */
1975
1976 apic_set_isr(vector, apic);
1977 apic_update_ppr(apic);
1978 apic_clear_irr(vector, apic);
1979
1980 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
1981 apic_clear_isr(vector, apic);
1982 apic_update_ppr(apic);
1983 }
1984
1985 return vector;
1986 }
1987
1988 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
1989 struct kvm_lapic_state *s, bool set)
1990 {
1991 if (apic_x2apic_mode(vcpu->arch.apic)) {
1992 u32 *id = (u32 *)(s->regs + APIC_ID);
1993
1994 if (set)
1995 *id >>= 24;
1996 else
1997 *id <<= 24;
1998 }
1999
2000 return 0;
2001 }
2002
2003 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2004 {
2005 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2006 return kvm_apic_state_fixup(vcpu, s, false);
2007 }
2008
2009 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2010 {
2011 struct kvm_lapic *apic = vcpu->arch.apic;
2012 int r;
2013
2014
2015 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2016 /* set SPIV separately to get count of SW disabled APICs right */
2017 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2018
2019 r = kvm_apic_state_fixup(vcpu, s, true);
2020 if (r)
2021 return r;
2022 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2023
2024 recalculate_apic_map(vcpu->kvm);
2025 kvm_apic_set_version(vcpu);
2026
2027 apic_update_ppr(apic);
2028 hrtimer_cancel(&apic->lapic_timer.timer);
2029 apic_update_lvtt(apic);
2030 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2031 update_divide_count(apic);
2032 start_apic_timer(apic);
2033 apic->irr_pending = true;
2034 apic->isr_count = vcpu->arch.apicv_active ?
2035 1 : count_vectors(apic->regs + APIC_ISR);
2036 apic->highest_isr_cache = -1;
2037 if (vcpu->arch.apicv_active) {
2038 if (kvm_x86_ops->apicv_post_state_restore)
2039 kvm_x86_ops->apicv_post_state_restore(vcpu);
2040 kvm_x86_ops->hwapic_irr_update(vcpu,
2041 apic_find_highest_irr(apic));
2042 kvm_x86_ops->hwapic_isr_update(vcpu,
2043 apic_find_highest_isr(apic));
2044 }
2045 kvm_make_request(KVM_REQ_EVENT, vcpu);
2046 if (ioapic_in_kernel(vcpu->kvm))
2047 kvm_rtc_eoi_tracking_restore_one(vcpu);
2048
2049 vcpu->arch.apic_arb_prio = 0;
2050
2051 return 0;
2052 }
2053
2054 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2055 {
2056 struct hrtimer *timer;
2057
2058 if (!lapic_in_kernel(vcpu))
2059 return;
2060
2061 timer = &vcpu->arch.apic->lapic_timer.timer;
2062 if (hrtimer_cancel(timer))
2063 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2064 }
2065
2066 /*
2067 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2068 *
2069 * Detect whether guest triggered PV EOI since the
2070 * last entry. If yes, set EOI on guests's behalf.
2071 * Clear PV EOI in guest memory in any case.
2072 */
2073 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2074 struct kvm_lapic *apic)
2075 {
2076 bool pending;
2077 int vector;
2078 /*
2079 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2080 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2081 *
2082 * KVM_APIC_PV_EOI_PENDING is unset:
2083 * -> host disabled PV EOI.
2084 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2085 * -> host enabled PV EOI, guest did not execute EOI yet.
2086 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2087 * -> host enabled PV EOI, guest executed EOI.
2088 */
2089 BUG_ON(!pv_eoi_enabled(vcpu));
2090 pending = pv_eoi_get_pending(vcpu);
2091 /*
2092 * Clear pending bit in any case: it will be set again on vmentry.
2093 * While this might not be ideal from performance point of view,
2094 * this makes sure pv eoi is only enabled when we know it's safe.
2095 */
2096 pv_eoi_clr_pending(vcpu);
2097 if (pending)
2098 return;
2099 vector = apic_set_eoi(apic);
2100 trace_kvm_pv_eoi(apic, vector);
2101 }
2102
2103 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2104 {
2105 u32 data;
2106
2107 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2108 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2109
2110 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2111 return;
2112
2113 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2114 sizeof(u32)))
2115 return;
2116
2117 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2118 }
2119
2120 /*
2121 * apic_sync_pv_eoi_to_guest - called before vmentry
2122 *
2123 * Detect whether it's safe to enable PV EOI and
2124 * if yes do so.
2125 */
2126 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2127 struct kvm_lapic *apic)
2128 {
2129 if (!pv_eoi_enabled(vcpu) ||
2130 /* IRR set or many bits in ISR: could be nested. */
2131 apic->irr_pending ||
2132 /* Cache not set: could be safe but we don't bother. */
2133 apic->highest_isr_cache == -1 ||
2134 /* Need EOI to update ioapic. */
2135 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2136 /*
2137 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2138 * so we need not do anything here.
2139 */
2140 return;
2141 }
2142
2143 pv_eoi_set_pending(apic->vcpu);
2144 }
2145
2146 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2147 {
2148 u32 data, tpr;
2149 int max_irr, max_isr;
2150 struct kvm_lapic *apic = vcpu->arch.apic;
2151
2152 apic_sync_pv_eoi_to_guest(vcpu, apic);
2153
2154 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2155 return;
2156
2157 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2158 max_irr = apic_find_highest_irr(apic);
2159 if (max_irr < 0)
2160 max_irr = 0;
2161 max_isr = apic_find_highest_isr(apic);
2162 if (max_isr < 0)
2163 max_isr = 0;
2164 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2165
2166 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2167 sizeof(u32));
2168 }
2169
2170 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2171 {
2172 if (vapic_addr) {
2173 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2174 &vcpu->arch.apic->vapic_cache,
2175 vapic_addr, sizeof(u32)))
2176 return -EINVAL;
2177 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2178 } else {
2179 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2180 }
2181
2182 vcpu->arch.apic->vapic_addr = vapic_addr;
2183 return 0;
2184 }
2185
2186 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2187 {
2188 struct kvm_lapic *apic = vcpu->arch.apic;
2189 u32 reg = (msr - APIC_BASE_MSR) << 4;
2190
2191 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2192 return 1;
2193
2194 if (reg == APIC_ICR2)
2195 return 1;
2196
2197 /* if this is ICR write vector before command */
2198 if (reg == APIC_ICR)
2199 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2200 return kvm_lapic_reg_write(apic, reg, (u32)data);
2201 }
2202
2203 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2204 {
2205 struct kvm_lapic *apic = vcpu->arch.apic;
2206 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2207
2208 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2209 return 1;
2210
2211 if (reg == APIC_DFR || reg == APIC_ICR2) {
2212 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2213 reg);
2214 return 1;
2215 }
2216
2217 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2218 return 1;
2219 if (reg == APIC_ICR)
2220 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2221
2222 *data = (((u64)high) << 32) | low;
2223
2224 return 0;
2225 }
2226
2227 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2228 {
2229 struct kvm_lapic *apic = vcpu->arch.apic;
2230
2231 if (!lapic_in_kernel(vcpu))
2232 return 1;
2233
2234 /* if this is ICR write vector before command */
2235 if (reg == APIC_ICR)
2236 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2237 return kvm_lapic_reg_write(apic, reg, (u32)data);
2238 }
2239
2240 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2241 {
2242 struct kvm_lapic *apic = vcpu->arch.apic;
2243 u32 low, high = 0;
2244
2245 if (!lapic_in_kernel(vcpu))
2246 return 1;
2247
2248 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2249 return 1;
2250 if (reg == APIC_ICR)
2251 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2252
2253 *data = (((u64)high) << 32) | low;
2254
2255 return 0;
2256 }
2257
2258 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2259 {
2260 u64 addr = data & ~KVM_MSR_ENABLED;
2261 if (!IS_ALIGNED(addr, 4))
2262 return 1;
2263
2264 vcpu->arch.pv_eoi.msr_val = data;
2265 if (!pv_eoi_enabled(vcpu))
2266 return 0;
2267 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2268 addr, sizeof(u8));
2269 }
2270
2271 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2272 {
2273 struct kvm_lapic *apic = vcpu->arch.apic;
2274 u8 sipi_vector;
2275 unsigned long pe;
2276
2277 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2278 return;
2279
2280 /*
2281 * INITs are latched while in SMM. Because an SMM CPU cannot
2282 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2283 * and delay processing of INIT until the next RSM.
2284 */
2285 if (is_smm(vcpu)) {
2286 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2287 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2288 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2289 return;
2290 }
2291
2292 pe = xchg(&apic->pending_events, 0);
2293 if (test_bit(KVM_APIC_INIT, &pe)) {
2294 kvm_lapic_reset(vcpu, true);
2295 kvm_vcpu_reset(vcpu, true);
2296 if (kvm_vcpu_is_bsp(apic->vcpu))
2297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2298 else
2299 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2300 }
2301 if (test_bit(KVM_APIC_SIPI, &pe) &&
2302 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2303 /* evaluate pending_events before reading the vector */
2304 smp_rmb();
2305 sipi_vector = apic->sipi_vector;
2306 apic_debug("vcpu %d received sipi with vector # %x\n",
2307 vcpu->vcpu_id, sipi_vector);
2308 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2309 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2310 }
2311 }
2312
2313 void kvm_lapic_init(void)
2314 {
2315 /* do not patch jump label more than once per second */
2316 jump_label_rate_limit(&apic_hw_disabled, HZ);
2317 jump_label_rate_limit(&apic_sw_disabled, HZ);
2318 }
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