1 // SPDX-License-Identifier: GPL-2.0-only
4 * Local APIC virtualization
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
19 #include <linux/kvm_host.h>
20 #include <linux/kvm.h>
22 #include <linux/highmem.h>
23 #include <linux/smp.h>
24 #include <linux/hrtimer.h>
26 #include <linux/export.h>
27 #include <linux/math64.h>
28 #include <linux/slab.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/delay.h>
35 #include <linux/atomic.h>
36 #include <linux/jump_label.h>
37 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 /* 14 is the version for Xeon and Pentium 8.4.8*/
57 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
58 #define LAPIC_MMIO_LENGTH (1 << 12)
59 /* followed define is not in apicdef.h */
60 #define MAX_APIC_VECTOR 256
61 #define APIC_VECTORS_PER_REG 32
63 static bool lapic_timer_advance_dynamic __read_mostly
;
64 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
65 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
66 #define LAPIC_TIMER_ADVANCE_NS_INIT 1000
67 #define LAPIC_TIMER_ADVANCE_NS_MAX 5000
68 /* step-by-step approximation to mitigate fluctuation */
69 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
71 static inline int apic_test_vector(int vec
, void *bitmap
)
73 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
76 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
78 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
80 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
81 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
84 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
86 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
89 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
91 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
94 struct static_key_deferred apic_hw_disabled __read_mostly
;
95 struct static_key_deferred apic_sw_disabled __read_mostly
;
97 static inline int apic_enabled(struct kvm_lapic
*apic
)
99 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
103 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
107 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
109 static inline u32
kvm_x2apic_id(struct kvm_lapic
*apic
)
111 return apic
->vcpu
->vcpu_id
;
114 static bool kvm_can_post_timer_interrupt(struct kvm_vcpu
*vcpu
)
116 return pi_inject_timer
&& kvm_vcpu_apicv_active(vcpu
);
119 bool kvm_can_use_hv_timer(struct kvm_vcpu
*vcpu
)
121 return kvm_x86_ops
.set_hv_timer
122 && !(kvm_mwait_in_guest(vcpu
->kvm
) ||
123 kvm_can_post_timer_interrupt(vcpu
));
125 EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer
);
127 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu
*vcpu
)
129 return kvm_can_post_timer_interrupt(vcpu
) && vcpu
->mode
== IN_GUEST_MODE
;
132 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map
*map
,
133 u32 dest_id
, struct kvm_lapic
***cluster
, u16
*mask
) {
135 case KVM_APIC_MODE_X2APIC
: {
136 u32 offset
= (dest_id
>> 16) * 16;
137 u32 max_apic_id
= map
->max_apic_id
;
139 if (offset
<= max_apic_id
) {
140 u8 cluster_size
= min(max_apic_id
- offset
+ 1, 16U);
142 offset
= array_index_nospec(offset
, map
->max_apic_id
+ 1);
143 *cluster
= &map
->phys_map
[offset
];
144 *mask
= dest_id
& (0xffff >> (16 - cluster_size
));
151 case KVM_APIC_MODE_XAPIC_FLAT
:
152 *cluster
= map
->xapic_flat_map
;
153 *mask
= dest_id
& 0xff;
155 case KVM_APIC_MODE_XAPIC_CLUSTER
:
156 *cluster
= map
->xapic_cluster_map
[(dest_id
>> 4) & 0xf];
157 *mask
= dest_id
& 0xf;
165 static void kvm_apic_map_free(struct rcu_head
*rcu
)
167 struct kvm_apic_map
*map
= container_of(rcu
, struct kvm_apic_map
, rcu
);
173 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
175 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
176 * apic_map_lock_held.
184 void kvm_recalculate_apic_map(struct kvm
*kvm
)
186 struct kvm_apic_map
*new, *old
= NULL
;
187 struct kvm_vcpu
*vcpu
;
189 u32 max_id
= 255; /* enough space for any xAPIC ID */
191 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */
192 if (atomic_read_acquire(&kvm
->arch
.apic_map_dirty
) == CLEAN
)
195 mutex_lock(&kvm
->arch
.apic_map_lock
);
197 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map
198 * (if clean) or the APIC registers (if dirty).
200 if (atomic_cmpxchg_acquire(&kvm
->arch
.apic_map_dirty
,
201 DIRTY
, UPDATE_IN_PROGRESS
) == CLEAN
) {
202 /* Someone else has updated the map. */
203 mutex_unlock(&kvm
->arch
.apic_map_lock
);
207 kvm_for_each_vcpu(i
, vcpu
, kvm
)
208 if (kvm_apic_present(vcpu
))
209 max_id
= max(max_id
, kvm_x2apic_id(vcpu
->arch
.apic
));
211 new = kvzalloc(sizeof(struct kvm_apic_map
) +
212 sizeof(struct kvm_lapic
*) * ((u64
)max_id
+ 1),
218 new->max_apic_id
= max_id
;
220 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
221 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
222 struct kvm_lapic
**cluster
;
228 if (!kvm_apic_present(vcpu
))
231 xapic_id
= kvm_xapic_id(apic
);
232 x2apic_id
= kvm_x2apic_id(apic
);
234 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
235 if ((apic_x2apic_mode(apic
) || x2apic_id
> 0xff) &&
236 x2apic_id
<= new->max_apic_id
)
237 new->phys_map
[x2apic_id
] = apic
;
239 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
240 * prevent them from masking VCPUs with APIC ID <= 0xff.
242 if (!apic_x2apic_mode(apic
) && !new->phys_map
[xapic_id
])
243 new->phys_map
[xapic_id
] = apic
;
245 if (!kvm_apic_sw_enabled(apic
))
248 ldr
= kvm_lapic_get_reg(apic
, APIC_LDR
);
250 if (apic_x2apic_mode(apic
)) {
251 new->mode
|= KVM_APIC_MODE_X2APIC
;
253 ldr
= GET_APIC_LOGICAL_ID(ldr
);
254 if (kvm_lapic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
255 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
257 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
260 if (!kvm_apic_map_get_logical_dest(new, ldr
, &cluster
, &mask
))
264 cluster
[ffs(mask
) - 1] = apic
;
267 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
268 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
269 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
271 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
272 * If another update has come in, leave it DIRTY.
274 atomic_cmpxchg_release(&kvm
->arch
.apic_map_dirty
,
275 UPDATE_IN_PROGRESS
, CLEAN
);
276 mutex_unlock(&kvm
->arch
.apic_map_lock
);
279 call_rcu(&old
->rcu
, kvm_apic_map_free
);
281 kvm_make_scan_ioapic_request(kvm
);
284 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
286 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
288 kvm_lapic_set_reg(apic
, APIC_SPIV
, val
);
290 if (enabled
!= apic
->sw_enabled
) {
291 apic
->sw_enabled
= enabled
;
293 static_key_slow_dec_deferred(&apic_sw_disabled
);
295 static_key_slow_inc(&apic_sw_disabled
.key
);
297 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
301 static inline void kvm_apic_set_xapic_id(struct kvm_lapic
*apic
, u8 id
)
303 kvm_lapic_set_reg(apic
, APIC_ID
, id
<< 24);
304 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
307 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
309 kvm_lapic_set_reg(apic
, APIC_LDR
, id
);
310 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
313 static inline void kvm_apic_set_dfr(struct kvm_lapic
*apic
, u32 val
)
315 kvm_lapic_set_reg(apic
, APIC_DFR
, val
);
316 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
319 static inline u32
kvm_apic_calc_x2apic_ldr(u32 id
)
321 return ((id
>> 4) << 16) | (1 << (id
& 0xf));
324 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic
*apic
, u32 id
)
326 u32 ldr
= kvm_apic_calc_x2apic_ldr(id
);
328 WARN_ON_ONCE(id
!= apic
->vcpu
->vcpu_id
);
330 kvm_lapic_set_reg(apic
, APIC_ID
, id
);
331 kvm_lapic_set_reg(apic
, APIC_LDR
, ldr
);
332 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
335 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
337 return !(kvm_lapic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
340 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
342 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
345 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
347 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
350 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
352 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
355 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
357 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
360 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
362 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
363 u32 v
= APIC_VERSION
;
365 if (!lapic_in_kernel(vcpu
))
369 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
370 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
371 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
372 * version first and level-triggered interrupts never get EOIed in
375 if (guest_cpuid_has(vcpu
, X86_FEATURE_X2APIC
) &&
376 !ioapic_in_kernel(vcpu
->kvm
))
377 v
|= APIC_LVR_DIRECTED_EOI
;
378 kvm_lapic_set_reg(apic
, APIC_LVR
, v
);
381 static const unsigned int apic_lvt_mask
[KVM_APIC_LVT_NUM
] = {
382 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
383 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
384 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
385 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
386 LVT_MASK
/* LVTERR */
389 static int find_highest_vector(void *bitmap
)
394 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
395 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
396 reg
= bitmap
+ REG_POS(vec
);
398 return __fls(*reg
) + vec
;
404 static u8
count_vectors(void *bitmap
)
410 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
411 reg
= bitmap
+ REG_POS(vec
);
412 count
+= hweight32(*reg
);
418 bool __kvm_apic_update_irr(u32
*pir
, void *regs
, int *max_irr
)
421 u32 pir_val
, irr_val
, prev_irr_val
;
424 max_updated_irr
= -1;
427 for (i
= vec
= 0; i
<= 7; i
++, vec
+= 32) {
428 pir_val
= READ_ONCE(pir
[i
]);
429 irr_val
= *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10));
431 prev_irr_val
= irr_val
;
432 irr_val
|= xchg(&pir
[i
], 0);
433 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) = irr_val
;
434 if (prev_irr_val
!= irr_val
) {
436 __fls(irr_val
^ prev_irr_val
) + vec
;
440 *max_irr
= __fls(irr_val
) + vec
;
443 return ((max_updated_irr
!= -1) &&
444 (max_updated_irr
== *max_irr
));
446 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
448 bool kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
, int *max_irr
)
450 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
452 return __kvm_apic_update_irr(pir
, apic
->regs
, max_irr
);
454 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
456 static inline int apic_search_irr(struct kvm_lapic
*apic
)
458 return find_highest_vector(apic
->regs
+ APIC_IRR
);
461 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
466 * Note that irr_pending is just a hint. It will be always
467 * true with virtual interrupt delivery enabled.
469 if (!apic
->irr_pending
)
472 result
= apic_search_irr(apic
);
473 ASSERT(result
== -1 || result
>= 16);
478 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
480 struct kvm_vcpu
*vcpu
;
484 if (unlikely(vcpu
->arch
.apicv_active
)) {
485 /* need to update RVI */
486 kvm_lapic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
487 kvm_x86_ops
.hwapic_irr_update(vcpu
,
488 apic_find_highest_irr(apic
));
490 apic
->irr_pending
= false;
491 kvm_lapic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
492 if (apic_search_irr(apic
) != -1)
493 apic
->irr_pending
= true;
497 void kvm_apic_clear_irr(struct kvm_vcpu
*vcpu
, int vec
)
499 apic_clear_irr(vec
, vcpu
->arch
.apic
);
501 EXPORT_SYMBOL_GPL(kvm_apic_clear_irr
);
503 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
505 struct kvm_vcpu
*vcpu
;
507 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
513 * With APIC virtualization enabled, all caching is disabled
514 * because the processor can modify ISR under the hood. Instead
517 if (unlikely(vcpu
->arch
.apicv_active
))
518 kvm_x86_ops
.hwapic_isr_update(vcpu
, vec
);
521 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
523 * ISR (in service register) bit is set when injecting an interrupt.
524 * The highest vector is injected. Thus the latest bit set matches
525 * the highest bit in ISR.
527 apic
->highest_isr_cache
= vec
;
531 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
536 * Note that isr_count is always 1, and highest_isr_cache
537 * is always -1, with APIC virtualization enabled.
539 if (!apic
->isr_count
)
541 if (likely(apic
->highest_isr_cache
!= -1))
542 return apic
->highest_isr_cache
;
544 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
545 ASSERT(result
== -1 || result
>= 16);
550 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
552 struct kvm_vcpu
*vcpu
;
553 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
559 * We do get here for APIC virtualization enabled if the guest
560 * uses the Hyper-V APIC enlightenment. In this case we may need
561 * to trigger a new interrupt delivery by writing the SVI field;
562 * on the other hand isr_count and highest_isr_cache are unused
563 * and must be left alone.
565 if (unlikely(vcpu
->arch
.apicv_active
))
566 kvm_x86_ops
.hwapic_isr_update(vcpu
,
567 apic_find_highest_isr(apic
));
570 BUG_ON(apic
->isr_count
< 0);
571 apic
->highest_isr_cache
= -1;
575 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
577 /* This may race with setting of irr in __apic_accept_irq() and
578 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
579 * will cause vmexit immediately and the value will be recalculated
580 * on the next vmentry.
582 return apic_find_highest_irr(vcpu
->arch
.apic
);
584 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr
);
586 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
587 int vector
, int level
, int trig_mode
,
588 struct dest_map
*dest_map
);
590 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
591 struct dest_map
*dest_map
)
593 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
595 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
596 irq
->level
, irq
->trig_mode
, dest_map
);
599 static int __pv_send_ipi(unsigned long *ipi_bitmap
, struct kvm_apic_map
*map
,
600 struct kvm_lapic_irq
*irq
, u32 min
)
603 struct kvm_vcpu
*vcpu
;
605 if (min
> map
->max_apic_id
)
608 for_each_set_bit(i
, ipi_bitmap
,
609 min((u32
)BITS_PER_LONG
, (map
->max_apic_id
- min
+ 1))) {
610 if (map
->phys_map
[min
+ i
]) {
611 vcpu
= map
->phys_map
[min
+ i
]->vcpu
;
612 count
+= kvm_apic_set_irq(vcpu
, irq
, NULL
);
619 int kvm_pv_send_ipi(struct kvm
*kvm
, unsigned long ipi_bitmap_low
,
620 unsigned long ipi_bitmap_high
, u32 min
,
621 unsigned long icr
, int op_64_bit
)
623 struct kvm_apic_map
*map
;
624 struct kvm_lapic_irq irq
= {0};
625 int cluster_size
= op_64_bit
? 64 : 32;
628 if (icr
& (APIC_DEST_MASK
| APIC_SHORT_MASK
))
631 irq
.vector
= icr
& APIC_VECTOR_MASK
;
632 irq
.delivery_mode
= icr
& APIC_MODE_MASK
;
633 irq
.level
= (icr
& APIC_INT_ASSERT
) != 0;
634 irq
.trig_mode
= icr
& APIC_INT_LEVELTRIG
;
637 map
= rcu_dereference(kvm
->arch
.apic_map
);
641 count
= __pv_send_ipi(&ipi_bitmap_low
, map
, &irq
, min
);
643 count
+= __pv_send_ipi(&ipi_bitmap_high
, map
, &irq
, min
);
650 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
653 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
657 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
660 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
664 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
666 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
669 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
672 if (pv_eoi_get_user(vcpu
, &val
) < 0) {
673 printk(KERN_WARNING
"Can't read EOI MSR value: 0x%llx\n",
674 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
680 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
682 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
683 printk(KERN_WARNING
"Can't set EOI MSR value: 0x%llx\n",
684 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
687 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
690 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
692 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
693 printk(KERN_WARNING
"Can't clear EOI MSR value: 0x%llx\n",
694 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
697 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
700 static int apic_has_interrupt_for_ppr(struct kvm_lapic
*apic
, u32 ppr
)
703 if (apic
->vcpu
->arch
.apicv_active
)
704 highest_irr
= kvm_x86_ops
.sync_pir_to_irr(apic
->vcpu
);
706 highest_irr
= apic_find_highest_irr(apic
);
707 if (highest_irr
== -1 || (highest_irr
& 0xF0) <= ppr
)
712 static bool __apic_update_ppr(struct kvm_lapic
*apic
, u32
*new_ppr
)
714 u32 tpr
, isrv
, ppr
, old_ppr
;
717 old_ppr
= kvm_lapic_get_reg(apic
, APIC_PROCPRI
);
718 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
);
719 isr
= apic_find_highest_isr(apic
);
720 isrv
= (isr
!= -1) ? isr
: 0;
722 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
729 kvm_lapic_set_reg(apic
, APIC_PROCPRI
, ppr
);
731 return ppr
< old_ppr
;
734 static void apic_update_ppr(struct kvm_lapic
*apic
)
738 if (__apic_update_ppr(apic
, &ppr
) &&
739 apic_has_interrupt_for_ppr(apic
, ppr
) != -1)
740 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
743 void kvm_apic_update_ppr(struct kvm_vcpu
*vcpu
)
745 apic_update_ppr(vcpu
->arch
.apic
);
747 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr
);
749 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
751 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, tpr
);
752 apic_update_ppr(apic
);
755 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
757 return mda
== (apic_x2apic_mode(apic
) ?
758 X2APIC_BROADCAST
: APIC_BROADCAST
);
761 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
763 if (kvm_apic_broadcast(apic
, mda
))
766 if (apic_x2apic_mode(apic
))
767 return mda
== kvm_x2apic_id(apic
);
770 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
771 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
772 * this allows unique addressing of VCPUs with APIC ID over 0xff.
773 * The 0xff condition is needed because writeable xAPIC ID.
775 if (kvm_x2apic_id(apic
) > 0xff && mda
== kvm_x2apic_id(apic
))
778 return mda
== kvm_xapic_id(apic
);
781 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
785 if (kvm_apic_broadcast(apic
, mda
))
788 logical_id
= kvm_lapic_get_reg(apic
, APIC_LDR
);
790 if (apic_x2apic_mode(apic
))
791 return ((logical_id
>> 16) == (mda
>> 16))
792 && (logical_id
& mda
& 0xffff) != 0;
794 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
796 switch (kvm_lapic_get_reg(apic
, APIC_DFR
)) {
798 return (logical_id
& mda
) != 0;
799 case APIC_DFR_CLUSTER
:
800 return ((logical_id
>> 4) == (mda
>> 4))
801 && (logical_id
& mda
& 0xf) != 0;
807 /* The KVM local APIC implementation has two quirks:
809 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
810 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
811 * KVM doesn't do that aliasing.
813 * - in-kernel IOAPIC messages have to be delivered directly to
814 * x2APIC, because the kernel does not support interrupt remapping.
815 * In order to support broadcast without interrupt remapping, x2APIC
816 * rewrites the destination of non-IPI messages from APIC_BROADCAST
817 * to X2APIC_BROADCAST.
819 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
820 * important when userspace wants to use x2APIC-format MSIs, because
821 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
823 static u32
kvm_apic_mda(struct kvm_vcpu
*vcpu
, unsigned int dest_id
,
824 struct kvm_lapic
*source
, struct kvm_lapic
*target
)
826 bool ipi
= source
!= NULL
;
828 if (!vcpu
->kvm
->arch
.x2apic_broadcast_quirk_disabled
&&
829 !ipi
&& dest_id
== APIC_BROADCAST
&& apic_x2apic_mode(target
))
830 return X2APIC_BROADCAST
;
835 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
836 int shorthand
, unsigned int dest
, int dest_mode
)
838 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
839 u32 mda
= kvm_apic_mda(vcpu
, dest
, source
, target
);
843 case APIC_DEST_NOSHORT
:
844 if (dest_mode
== APIC_DEST_PHYSICAL
)
845 return kvm_apic_match_physical_addr(target
, mda
);
847 return kvm_apic_match_logical_addr(target
, mda
);
849 return target
== source
;
850 case APIC_DEST_ALLINC
:
852 case APIC_DEST_ALLBUT
:
853 return target
!= source
;
858 EXPORT_SYMBOL_GPL(kvm_apic_match_dest
);
860 int kvm_vector_to_index(u32 vector
, u32 dest_vcpus
,
861 const unsigned long *bitmap
, u32 bitmap_size
)
866 mod
= vector
% dest_vcpus
;
868 for (i
= 0; i
<= mod
; i
++) {
869 idx
= find_next_bit(bitmap
, bitmap_size
, idx
+ 1);
870 BUG_ON(idx
== bitmap_size
);
876 static void kvm_apic_disabled_lapic_found(struct kvm
*kvm
)
878 if (!kvm
->arch
.disabled_lapic_found
) {
879 kvm
->arch
.disabled_lapic_found
= true;
881 "Disabled LAPIC found during irq injection\n");
885 static bool kvm_apic_is_broadcast_dest(struct kvm
*kvm
, struct kvm_lapic
**src
,
886 struct kvm_lapic_irq
*irq
, struct kvm_apic_map
*map
)
888 if (kvm
->arch
.x2apic_broadcast_quirk_disabled
) {
889 if ((irq
->dest_id
== APIC_BROADCAST
&&
890 map
->mode
!= KVM_APIC_MODE_X2APIC
))
892 if (irq
->dest_id
== X2APIC_BROADCAST
)
895 bool x2apic_ipi
= src
&& *src
&& apic_x2apic_mode(*src
);
896 if (irq
->dest_id
== (x2apic_ipi
?
897 X2APIC_BROADCAST
: APIC_BROADCAST
))
904 /* Return true if the interrupt can be handled by using *bitmap as index mask
905 * for valid destinations in *dst array.
906 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
907 * Note: we may have zero kvm_lapic destinations when we return true, which
908 * means that the interrupt should be dropped. In this case, *bitmap would be
909 * zero and *dst undefined.
911 static inline bool kvm_apic_map_get_dest_lapic(struct kvm
*kvm
,
912 struct kvm_lapic
**src
, struct kvm_lapic_irq
*irq
,
913 struct kvm_apic_map
*map
, struct kvm_lapic
***dst
,
914 unsigned long *bitmap
)
918 if (irq
->shorthand
== APIC_DEST_SELF
&& src
) {
922 } else if (irq
->shorthand
)
925 if (!map
|| kvm_apic_is_broadcast_dest(kvm
, src
, irq
, map
))
928 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
929 if (irq
->dest_id
> map
->max_apic_id
) {
932 u32 dest_id
= array_index_nospec(irq
->dest_id
, map
->max_apic_id
+ 1);
933 *dst
= &map
->phys_map
[dest_id
];
940 if (!kvm_apic_map_get_logical_dest(map
, irq
->dest_id
, dst
,
944 if (!kvm_lowest_prio_delivery(irq
))
947 if (!kvm_vector_hashing_enabled()) {
949 for_each_set_bit(i
, bitmap
, 16) {
954 else if (kvm_apic_compare_prio((*dst
)[i
]->vcpu
,
955 (*dst
)[lowest
]->vcpu
) < 0)
962 lowest
= kvm_vector_to_index(irq
->vector
, hweight16(*bitmap
),
965 if (!(*dst
)[lowest
]) {
966 kvm_apic_disabled_lapic_found(kvm
);
972 *bitmap
= (lowest
>= 0) ? 1 << lowest
: 0;
977 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
978 struct kvm_lapic_irq
*irq
, int *r
, struct dest_map
*dest_map
)
980 struct kvm_apic_map
*map
;
981 unsigned long bitmap
;
982 struct kvm_lapic
**dst
= NULL
;
988 if (irq
->shorthand
== APIC_DEST_SELF
) {
989 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
994 map
= rcu_dereference(kvm
->arch
.apic_map
);
996 ret
= kvm_apic_map_get_dest_lapic(kvm
, &src
, irq
, map
, &dst
, &bitmap
);
999 for_each_set_bit(i
, &bitmap
, 16) {
1002 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
1011 * This routine tries to handle interrupts in posted mode, here is how
1012 * it deals with different cases:
1013 * - For single-destination interrupts, handle it in posted mode
1014 * - Else if vector hashing is enabled and it is a lowest-priority
1015 * interrupt, handle it in posted mode and use the following mechanism
1016 * to find the destination vCPU.
1017 * 1. For lowest-priority interrupts, store all the possible
1018 * destination vCPUs in an array.
1019 * 2. Use "guest vector % max number of destination vCPUs" to find
1020 * the right destination vCPU in the array for the lowest-priority
1022 * - Otherwise, use remapped mode to inject the interrupt.
1024 bool kvm_intr_is_single_vcpu_fast(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
1025 struct kvm_vcpu
**dest_vcpu
)
1027 struct kvm_apic_map
*map
;
1028 unsigned long bitmap
;
1029 struct kvm_lapic
**dst
= NULL
;
1036 map
= rcu_dereference(kvm
->arch
.apic_map
);
1038 if (kvm_apic_map_get_dest_lapic(kvm
, NULL
, irq
, map
, &dst
, &bitmap
) &&
1039 hweight16(bitmap
) == 1) {
1040 unsigned long i
= find_first_bit(&bitmap
, 16);
1043 *dest_vcpu
= dst
[i
]->vcpu
;
1053 * Add a pending IRQ into lapic.
1054 * Return 1 if successfully added and 0 if discarded.
1056 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
1057 int vector
, int level
, int trig_mode
,
1058 struct dest_map
*dest_map
)
1061 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1063 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
1065 switch (delivery_mode
) {
1066 case APIC_DM_LOWEST
:
1067 vcpu
->arch
.apic_arb_prio
++;
1070 if (unlikely(trig_mode
&& !level
))
1073 /* FIXME add logic for vcpu on reset */
1074 if (unlikely(!apic_enabled(apic
)))
1080 __set_bit(vcpu
->vcpu_id
, dest_map
->map
);
1081 dest_map
->vectors
[vcpu
->vcpu_id
] = vector
;
1084 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
) != !!trig_mode
) {
1086 kvm_lapic_set_vector(vector
,
1087 apic
->regs
+ APIC_TMR
);
1089 kvm_lapic_clear_vector(vector
,
1090 apic
->regs
+ APIC_TMR
);
1093 if (kvm_x86_ops
.deliver_posted_interrupt(vcpu
, vector
)) {
1094 kvm_lapic_set_irr(vector
, apic
);
1095 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1096 kvm_vcpu_kick(vcpu
);
1102 vcpu
->arch
.pv
.pv_unhalted
= 1;
1103 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1104 kvm_vcpu_kick(vcpu
);
1109 kvm_make_request(KVM_REQ_SMI
, vcpu
);
1110 kvm_vcpu_kick(vcpu
);
1115 kvm_inject_nmi(vcpu
);
1116 kvm_vcpu_kick(vcpu
);
1120 if (!trig_mode
|| level
) {
1122 /* assumes that there are only KVM_APIC_INIT/SIPI */
1123 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
1124 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1125 kvm_vcpu_kick(vcpu
);
1129 case APIC_DM_STARTUP
:
1131 apic
->sipi_vector
= vector
;
1132 /* make sure sipi_vector is visible for the receiver */
1134 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
1135 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1136 kvm_vcpu_kick(vcpu
);
1139 case APIC_DM_EXTINT
:
1141 * Should only be called by kvm_apic_local_deliver() with LVT0,
1142 * before NMI watchdog was enabled. Already handled by
1143 * kvm_apic_accept_pic_intr().
1148 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
1156 * This routine identifies the destination vcpus mask meant to receive the
1157 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1158 * out the destination vcpus array and set the bitmap or it traverses to
1159 * each available vcpu to identify the same.
1161 void kvm_bitmap_or_dest_vcpus(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
1162 unsigned long *vcpu_bitmap
)
1164 struct kvm_lapic
**dest_vcpu
= NULL
;
1165 struct kvm_lapic
*src
= NULL
;
1166 struct kvm_apic_map
*map
;
1167 struct kvm_vcpu
*vcpu
;
1168 unsigned long bitmap
;
1173 map
= rcu_dereference(kvm
->arch
.apic_map
);
1175 ret
= kvm_apic_map_get_dest_lapic(kvm
, &src
, irq
, map
, &dest_vcpu
,
1178 for_each_set_bit(i
, &bitmap
, 16) {
1181 vcpu_idx
= dest_vcpu
[i
]->vcpu
->vcpu_idx
;
1182 __set_bit(vcpu_idx
, vcpu_bitmap
);
1185 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1186 if (!kvm_apic_present(vcpu
))
1188 if (!kvm_apic_match_dest(vcpu
, NULL
,
1193 __set_bit(i
, vcpu_bitmap
);
1199 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
1201 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
1204 static bool kvm_ioapic_handles_vector(struct kvm_lapic
*apic
, int vector
)
1206 return test_bit(vector
, apic
->vcpu
->arch
.ioapic_handled_vectors
);
1209 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
1213 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1214 if (!kvm_ioapic_handles_vector(apic
, vector
))
1217 /* Request a KVM exit to inform the userspace IOAPIC. */
1218 if (irqchip_split(apic
->vcpu
->kvm
)) {
1219 apic
->vcpu
->arch
.pending_ioapic_eoi
= vector
;
1220 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT
, apic
->vcpu
);
1224 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
1225 trigger_mode
= IOAPIC_LEVEL_TRIG
;
1227 trigger_mode
= IOAPIC_EDGE_TRIG
;
1229 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
1232 static int apic_set_eoi(struct kvm_lapic
*apic
)
1234 int vector
= apic_find_highest_isr(apic
);
1236 trace_kvm_eoi(apic
, vector
);
1239 * Not every write EOI will has corresponding ISR,
1240 * one example is when Kernel check timer on setup_IO_APIC
1245 apic_clear_isr(vector
, apic
);
1246 apic_update_ppr(apic
);
1248 if (test_bit(vector
, vcpu_to_synic(apic
->vcpu
)->vec_bitmap
))
1249 kvm_hv_synic_send_eoi(apic
->vcpu
, vector
);
1251 kvm_ioapic_send_eoi(apic
, vector
);
1252 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1257 * this interface assumes a trap-like exit, which has already finished
1258 * desired side effect including vISR and vPPR update.
1260 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
1262 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1264 trace_kvm_eoi(apic
, vector
);
1266 kvm_ioapic_send_eoi(apic
, vector
);
1267 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1269 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
1271 void kvm_apic_send_ipi(struct kvm_lapic
*apic
, u32 icr_low
, u32 icr_high
)
1273 struct kvm_lapic_irq irq
;
1275 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
1276 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
1277 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
1278 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
1279 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
1280 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
1281 irq
.msi_redir_hint
= false;
1282 if (apic_x2apic_mode(apic
))
1283 irq
.dest_id
= icr_high
;
1285 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
1287 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
1289 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
1292 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
1294 ktime_t remaining
, now
;
1298 ASSERT(apic
!= NULL
);
1300 /* if initial count is 0, current count should also be 0 */
1301 if (kvm_lapic_get_reg(apic
, APIC_TMICT
) == 0 ||
1302 apic
->lapic_timer
.period
== 0)
1306 remaining
= ktime_sub(apic
->lapic_timer
.target_expiration
, now
);
1307 if (ktime_to_ns(remaining
) < 0)
1310 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
1311 tmcct
= div64_u64(ns
,
1312 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
1317 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1319 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1320 struct kvm_run
*run
= vcpu
->run
;
1322 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
1323 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
1324 run
->tpr_access
.is_write
= write
;
1327 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1329 if (apic
->vcpu
->arch
.tpr_access_reporting
)
1330 __report_tpr_access(apic
, write
);
1333 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
1337 if (offset
>= LAPIC_MMIO_LENGTH
)
1344 case APIC_TMCCT
: /* Timer CCR */
1345 if (apic_lvtt_tscdeadline(apic
))
1348 val
= apic_get_tmcct(apic
);
1351 apic_update_ppr(apic
);
1352 val
= kvm_lapic_get_reg(apic
, offset
);
1355 report_tpr_access(apic
, false);
1358 val
= kvm_lapic_get_reg(apic
, offset
);
1365 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1367 return container_of(dev
, struct kvm_lapic
, dev
);
1370 #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1371 #define APIC_REGS_MASK(first, count) \
1372 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1374 int kvm_lapic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1377 unsigned char alignment
= offset
& 0xf;
1379 /* this bitmask has a bit cleared for each reserved register */
1380 u64 valid_reg_mask
=
1381 APIC_REG_MASK(APIC_ID
) |
1382 APIC_REG_MASK(APIC_LVR
) |
1383 APIC_REG_MASK(APIC_TASKPRI
) |
1384 APIC_REG_MASK(APIC_PROCPRI
) |
1385 APIC_REG_MASK(APIC_LDR
) |
1386 APIC_REG_MASK(APIC_DFR
) |
1387 APIC_REG_MASK(APIC_SPIV
) |
1388 APIC_REGS_MASK(APIC_ISR
, APIC_ISR_NR
) |
1389 APIC_REGS_MASK(APIC_TMR
, APIC_ISR_NR
) |
1390 APIC_REGS_MASK(APIC_IRR
, APIC_ISR_NR
) |
1391 APIC_REG_MASK(APIC_ESR
) |
1392 APIC_REG_MASK(APIC_ICR
) |
1393 APIC_REG_MASK(APIC_ICR2
) |
1394 APIC_REG_MASK(APIC_LVTT
) |
1395 APIC_REG_MASK(APIC_LVTTHMR
) |
1396 APIC_REG_MASK(APIC_LVTPC
) |
1397 APIC_REG_MASK(APIC_LVT0
) |
1398 APIC_REG_MASK(APIC_LVT1
) |
1399 APIC_REG_MASK(APIC_LVTERR
) |
1400 APIC_REG_MASK(APIC_TMICT
) |
1401 APIC_REG_MASK(APIC_TMCCT
) |
1402 APIC_REG_MASK(APIC_TDCR
);
1404 /* ARBPRI is not valid on x2APIC */
1405 if (!apic_x2apic_mode(apic
))
1406 valid_reg_mask
|= APIC_REG_MASK(APIC_ARBPRI
);
1408 if (offset
> 0x3f0 || !(valid_reg_mask
& APIC_REG_MASK(offset
)))
1411 result
= __apic_read(apic
, offset
& ~0xf);
1413 trace_kvm_apic_read(offset
, result
);
1419 memcpy(data
, (char *)&result
+ alignment
, len
);
1422 printk(KERN_ERR
"Local APIC read with len = %x, "
1423 "should be 1,2, or 4 instead\n", len
);
1428 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read
);
1430 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1432 return addr
>= apic
->base_address
&&
1433 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1436 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1437 gpa_t address
, int len
, void *data
)
1439 struct kvm_lapic
*apic
= to_lapic(this);
1440 u32 offset
= address
- apic
->base_address
;
1442 if (!apic_mmio_in_range(apic
, address
))
1445 if (!kvm_apic_hw_enabled(apic
) || apic_x2apic_mode(apic
)) {
1446 if (!kvm_check_has_quirk(vcpu
->kvm
,
1447 KVM_X86_QUIRK_LAPIC_MMIO_HOLE
))
1450 memset(data
, 0xff, len
);
1454 kvm_lapic_reg_read(apic
, offset
, len
, data
);
1459 static void update_divide_count(struct kvm_lapic
*apic
)
1461 u32 tmp1
, tmp2
, tdcr
;
1463 tdcr
= kvm_lapic_get_reg(apic
, APIC_TDCR
);
1465 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1466 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1469 static void limit_periodic_timer_frequency(struct kvm_lapic
*apic
)
1472 * Do not allow the guest to program periodic timers with small
1473 * interval, since the hrtimers are not throttled by the host
1476 if (apic_lvtt_period(apic
) && apic
->lapic_timer
.period
) {
1477 s64 min_period
= min_timer_period_us
* 1000LL;
1479 if (apic
->lapic_timer
.period
< min_period
) {
1480 pr_info_ratelimited(
1481 "kvm: vcpu %i: requested %lld ns "
1482 "lapic timer period limited to %lld ns\n",
1483 apic
->vcpu
->vcpu_id
,
1484 apic
->lapic_timer
.period
, min_period
);
1485 apic
->lapic_timer
.period
= min_period
;
1490 static void cancel_hv_timer(struct kvm_lapic
*apic
);
1492 static void apic_update_lvtt(struct kvm_lapic
*apic
)
1494 u32 timer_mode
= kvm_lapic_get_reg(apic
, APIC_LVTT
) &
1495 apic
->lapic_timer
.timer_mode_mask
;
1497 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1498 if (apic_lvtt_tscdeadline(apic
) != (timer_mode
==
1499 APIC_LVT_TIMER_TSCDEADLINE
)) {
1500 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1502 if (apic
->lapic_timer
.hv_timer_in_use
)
1503 cancel_hv_timer(apic
);
1505 kvm_lapic_set_reg(apic
, APIC_TMICT
, 0);
1506 apic
->lapic_timer
.period
= 0;
1507 apic
->lapic_timer
.tscdeadline
= 0;
1509 apic
->lapic_timer
.timer_mode
= timer_mode
;
1510 limit_periodic_timer_frequency(apic
);
1515 * On APICv, this test will cause a busy wait
1516 * during a higher-priority task.
1519 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1521 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1522 u32 reg
= kvm_lapic_get_reg(apic
, APIC_LVTT
);
1524 if (kvm_apic_hw_enabled(apic
)) {
1525 int vec
= reg
& APIC_VECTOR_MASK
;
1526 void *bitmap
= apic
->regs
+ APIC_ISR
;
1528 if (vcpu
->arch
.apicv_active
)
1529 bitmap
= apic
->regs
+ APIC_IRR
;
1531 if (apic_test_vector(vec
, bitmap
))
1537 static inline void __wait_lapic_expire(struct kvm_vcpu
*vcpu
, u64 guest_cycles
)
1539 u64 timer_advance_ns
= vcpu
->arch
.apic
->lapic_timer
.timer_advance_ns
;
1542 * If the guest TSC is running at a different ratio than the host, then
1543 * convert the delay to nanoseconds to achieve an accurate delay. Note
1544 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1545 * always for VMX enabled hardware.
1547 if (vcpu
->arch
.tsc_scaling_ratio
== kvm_default_tsc_scaling_ratio
) {
1548 __delay(min(guest_cycles
,
1549 nsec_to_cycles(vcpu
, timer_advance_ns
)));
1551 u64 delay_ns
= guest_cycles
* 1000000ULL;
1552 do_div(delay_ns
, vcpu
->arch
.virtual_tsc_khz
);
1553 ndelay(min_t(u32
, delay_ns
, timer_advance_ns
));
1557 static inline void adjust_lapic_timer_advance(struct kvm_vcpu
*vcpu
,
1558 s64 advance_expire_delta
)
1560 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1561 u32 timer_advance_ns
= apic
->lapic_timer
.timer_advance_ns
;
1564 /* Do not adjust for tiny fluctuations or large random spikes. */
1565 if (abs(advance_expire_delta
) > LAPIC_TIMER_ADVANCE_ADJUST_MAX
||
1566 abs(advance_expire_delta
) < LAPIC_TIMER_ADVANCE_ADJUST_MIN
)
1570 if (advance_expire_delta
< 0) {
1571 ns
= -advance_expire_delta
* 1000000ULL;
1572 do_div(ns
, vcpu
->arch
.virtual_tsc_khz
);
1573 timer_advance_ns
-= ns
/LAPIC_TIMER_ADVANCE_ADJUST_STEP
;
1576 ns
= advance_expire_delta
* 1000000ULL;
1577 do_div(ns
, vcpu
->arch
.virtual_tsc_khz
);
1578 timer_advance_ns
+= ns
/LAPIC_TIMER_ADVANCE_ADJUST_STEP
;
1581 if (unlikely(timer_advance_ns
> LAPIC_TIMER_ADVANCE_NS_MAX
))
1582 timer_advance_ns
= LAPIC_TIMER_ADVANCE_NS_INIT
;
1583 apic
->lapic_timer
.timer_advance_ns
= timer_advance_ns
;
1586 static void __kvm_wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1588 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1589 u64 guest_tsc
, tsc_deadline
;
1591 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1592 apic
->lapic_timer
.expired_tscdeadline
= 0;
1593 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1594 apic
->lapic_timer
.advance_expire_delta
= guest_tsc
- tsc_deadline
;
1596 if (guest_tsc
< tsc_deadline
)
1597 __wait_lapic_expire(vcpu
, tsc_deadline
- guest_tsc
);
1599 if (lapic_timer_advance_dynamic
)
1600 adjust_lapic_timer_advance(vcpu
, apic
->lapic_timer
.advance_expire_delta
);
1603 void kvm_wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1605 if (lapic_in_kernel(vcpu
) &&
1606 vcpu
->arch
.apic
->lapic_timer
.expired_tscdeadline
&&
1607 vcpu
->arch
.apic
->lapic_timer
.timer_advance_ns
&&
1608 lapic_timer_int_injected(vcpu
))
1609 __kvm_wait_lapic_expire(vcpu
);
1611 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire
);
1613 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic
*apic
)
1615 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1617 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1618 if (apic_lvtt_tscdeadline(apic
)) {
1619 ktimer
->tscdeadline
= 0;
1620 } else if (apic_lvtt_oneshot(apic
)) {
1621 ktimer
->tscdeadline
= 0;
1622 ktimer
->target_expiration
= 0;
1626 static void apic_timer_expired(struct kvm_lapic
*apic
, bool from_timer_fn
)
1628 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1629 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1631 if (atomic_read(&apic
->lapic_timer
.pending
))
1634 if (apic_lvtt_tscdeadline(apic
) || ktimer
->hv_timer_in_use
)
1635 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1637 if (!from_timer_fn
&& vcpu
->arch
.apicv_active
) {
1638 WARN_ON(kvm_get_running_vcpu() != vcpu
);
1639 kvm_apic_inject_pending_timer_irqs(apic
);
1643 if (kvm_use_posted_timer_interrupt(apic
->vcpu
)) {
1644 kvm_wait_lapic_expire(vcpu
);
1645 kvm_apic_inject_pending_timer_irqs(apic
);
1649 atomic_inc(&apic
->lapic_timer
.pending
);
1650 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1652 kvm_vcpu_kick(vcpu
);
1655 static void start_sw_tscdeadline(struct kvm_lapic
*apic
)
1657 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1658 u64 guest_tsc
, tscdeadline
= ktimer
->tscdeadline
;
1661 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1662 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1663 unsigned long flags
;
1666 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1669 local_irq_save(flags
);
1672 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1674 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1675 do_div(ns
, this_tsc_khz
);
1677 if (likely(tscdeadline
> guest_tsc
) &&
1678 likely(ns
> apic
->lapic_timer
.timer_advance_ns
)) {
1679 expire
= ktime_add_ns(now
, ns
);
1680 expire
= ktime_sub_ns(expire
, ktimer
->timer_advance_ns
);
1681 hrtimer_start(&ktimer
->timer
, expire
, HRTIMER_MODE_ABS_HARD
);
1683 apic_timer_expired(apic
, false);
1685 local_irq_restore(flags
);
1688 static inline u64
tmict_to_ns(struct kvm_lapic
*apic
, u32 tmict
)
1690 return (u64
)tmict
* APIC_BUS_CYCLE_NS
* (u64
)apic
->divide_count
;
1693 static void update_target_expiration(struct kvm_lapic
*apic
, uint32_t old_divisor
)
1695 ktime_t now
, remaining
;
1696 u64 ns_remaining_old
, ns_remaining_new
;
1698 apic
->lapic_timer
.period
=
1699 tmict_to_ns(apic
, kvm_lapic_get_reg(apic
, APIC_TMICT
));
1700 limit_periodic_timer_frequency(apic
);
1703 remaining
= ktime_sub(apic
->lapic_timer
.target_expiration
, now
);
1704 if (ktime_to_ns(remaining
) < 0)
1707 ns_remaining_old
= ktime_to_ns(remaining
);
1708 ns_remaining_new
= mul_u64_u32_div(ns_remaining_old
,
1709 apic
->divide_count
, old_divisor
);
1711 apic
->lapic_timer
.tscdeadline
+=
1712 nsec_to_cycles(apic
->vcpu
, ns_remaining_new
) -
1713 nsec_to_cycles(apic
->vcpu
, ns_remaining_old
);
1714 apic
->lapic_timer
.target_expiration
= ktime_add_ns(now
, ns_remaining_new
);
1717 static bool set_target_expiration(struct kvm_lapic
*apic
, u32 count_reg
)
1724 apic
->lapic_timer
.period
=
1725 tmict_to_ns(apic
, kvm_lapic_get_reg(apic
, APIC_TMICT
));
1727 if (!apic
->lapic_timer
.period
) {
1728 apic
->lapic_timer
.tscdeadline
= 0;
1732 limit_periodic_timer_frequency(apic
);
1733 deadline
= apic
->lapic_timer
.period
;
1735 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1736 if (unlikely(count_reg
!= APIC_TMICT
)) {
1737 deadline
= tmict_to_ns(apic
,
1738 kvm_lapic_get_reg(apic
, count_reg
));
1739 if (unlikely(deadline
<= 0))
1740 deadline
= apic
->lapic_timer
.period
;
1741 else if (unlikely(deadline
> apic
->lapic_timer
.period
)) {
1742 pr_info_ratelimited(
1743 "kvm: vcpu %i: requested lapic timer restore with "
1744 "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
1745 "Using initial count to start timer.\n",
1746 apic
->vcpu
->vcpu_id
,
1748 kvm_lapic_get_reg(apic
, count_reg
),
1749 deadline
, apic
->lapic_timer
.period
);
1750 kvm_lapic_set_reg(apic
, count_reg
, 0);
1751 deadline
= apic
->lapic_timer
.period
;
1756 apic
->lapic_timer
.tscdeadline
= kvm_read_l1_tsc(apic
->vcpu
, tscl
) +
1757 nsec_to_cycles(apic
->vcpu
, deadline
);
1758 apic
->lapic_timer
.target_expiration
= ktime_add_ns(now
, deadline
);
1763 static void advance_periodic_target_expiration(struct kvm_lapic
*apic
)
1765 ktime_t now
= ktime_get();
1770 * Synchronize both deadlines to the same time source or
1771 * differences in the periods (caused by differences in the
1772 * underlying clocks or numerical approximation errors) will
1773 * cause the two to drift apart over time as the errors
1776 apic
->lapic_timer
.target_expiration
=
1777 ktime_add_ns(apic
->lapic_timer
.target_expiration
,
1778 apic
->lapic_timer
.period
);
1779 delta
= ktime_sub(apic
->lapic_timer
.target_expiration
, now
);
1780 apic
->lapic_timer
.tscdeadline
= kvm_read_l1_tsc(apic
->vcpu
, tscl
) +
1781 nsec_to_cycles(apic
->vcpu
, delta
);
1784 static void start_sw_period(struct kvm_lapic
*apic
)
1786 if (!apic
->lapic_timer
.period
)
1789 if (ktime_after(ktime_get(),
1790 apic
->lapic_timer
.target_expiration
)) {
1791 apic_timer_expired(apic
, false);
1793 if (apic_lvtt_oneshot(apic
))
1796 advance_periodic_target_expiration(apic
);
1799 hrtimer_start(&apic
->lapic_timer
.timer
,
1800 apic
->lapic_timer
.target_expiration
,
1801 HRTIMER_MODE_ABS_HARD
);
1804 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu
*vcpu
)
1806 if (!lapic_in_kernel(vcpu
))
1809 return vcpu
->arch
.apic
->lapic_timer
.hv_timer_in_use
;
1811 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use
);
1813 static void cancel_hv_timer(struct kvm_lapic
*apic
)
1815 WARN_ON(preemptible());
1816 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1817 kvm_x86_ops
.cancel_hv_timer(apic
->vcpu
);
1818 apic
->lapic_timer
.hv_timer_in_use
= false;
1821 static bool start_hv_timer(struct kvm_lapic
*apic
)
1823 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1824 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1827 WARN_ON(preemptible());
1828 if (!kvm_can_use_hv_timer(vcpu
))
1831 if (!ktimer
->tscdeadline
)
1834 if (kvm_x86_ops
.set_hv_timer(vcpu
, ktimer
->tscdeadline
, &expired
))
1837 ktimer
->hv_timer_in_use
= true;
1838 hrtimer_cancel(&ktimer
->timer
);
1841 * To simplify handling the periodic timer, leave the hv timer running
1842 * even if the deadline timer has expired, i.e. rely on the resulting
1843 * VM-Exit to recompute the periodic timer's target expiration.
1845 if (!apic_lvtt_period(apic
)) {
1847 * Cancel the hv timer if the sw timer fired while the hv timer
1848 * was being programmed, or if the hv timer itself expired.
1850 if (atomic_read(&ktimer
->pending
)) {
1851 cancel_hv_timer(apic
);
1852 } else if (expired
) {
1853 apic_timer_expired(apic
, false);
1854 cancel_hv_timer(apic
);
1858 trace_kvm_hv_timer_state(vcpu
->vcpu_id
, ktimer
->hv_timer_in_use
);
1863 static void start_sw_timer(struct kvm_lapic
*apic
)
1865 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1867 WARN_ON(preemptible());
1868 if (apic
->lapic_timer
.hv_timer_in_use
)
1869 cancel_hv_timer(apic
);
1870 if (!apic_lvtt_period(apic
) && atomic_read(&ktimer
->pending
))
1873 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1874 start_sw_period(apic
);
1875 else if (apic_lvtt_tscdeadline(apic
))
1876 start_sw_tscdeadline(apic
);
1877 trace_kvm_hv_timer_state(apic
->vcpu
->vcpu_id
, false);
1880 static void restart_apic_timer(struct kvm_lapic
*apic
)
1884 if (!apic_lvtt_period(apic
) && atomic_read(&apic
->lapic_timer
.pending
))
1887 if (!start_hv_timer(apic
))
1888 start_sw_timer(apic
);
1893 void kvm_lapic_expired_hv_timer(struct kvm_vcpu
*vcpu
)
1895 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1898 /* If the preempt notifier has already run, it also called apic_timer_expired */
1899 if (!apic
->lapic_timer
.hv_timer_in_use
)
1901 WARN_ON(rcuwait_active(&vcpu
->wait
));
1902 cancel_hv_timer(apic
);
1903 apic_timer_expired(apic
, false);
1905 if (apic_lvtt_period(apic
) && apic
->lapic_timer
.period
) {
1906 advance_periodic_target_expiration(apic
);
1907 restart_apic_timer(apic
);
1912 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer
);
1914 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu
*vcpu
)
1916 restart_apic_timer(vcpu
->arch
.apic
);
1918 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer
);
1920 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu
*vcpu
)
1922 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1925 /* Possibly the TSC deadline timer is not enabled yet */
1926 if (apic
->lapic_timer
.hv_timer_in_use
)
1927 start_sw_timer(apic
);
1930 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer
);
1932 void kvm_lapic_restart_hv_timer(struct kvm_vcpu
*vcpu
)
1934 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1936 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1937 restart_apic_timer(apic
);
1940 static void __start_apic_timer(struct kvm_lapic
*apic
, u32 count_reg
)
1942 atomic_set(&apic
->lapic_timer
.pending
, 0);
1944 if ((apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1945 && !set_target_expiration(apic
, count_reg
))
1948 restart_apic_timer(apic
);
1951 static void start_apic_timer(struct kvm_lapic
*apic
)
1953 __start_apic_timer(apic
, APIC_TMICT
);
1956 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1958 bool lvt0_in_nmi_mode
= apic_lvt_nmi_mode(lvt0_val
);
1960 if (apic
->lvt0_in_nmi_mode
!= lvt0_in_nmi_mode
) {
1961 apic
->lvt0_in_nmi_mode
= lvt0_in_nmi_mode
;
1962 if (lvt0_in_nmi_mode
) {
1963 atomic_inc(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1965 atomic_dec(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1969 int kvm_lapic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1973 trace_kvm_apic_write(reg
, val
);
1976 case APIC_ID
: /* Local APIC ID */
1977 if (!apic_x2apic_mode(apic
))
1978 kvm_apic_set_xapic_id(apic
, val
>> 24);
1984 report_tpr_access(apic
, true);
1985 apic_set_tpr(apic
, val
& 0xff);
1993 if (!apic_x2apic_mode(apic
))
1994 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
2000 if (!apic_x2apic_mode(apic
))
2001 kvm_apic_set_dfr(apic
, val
| 0x0FFFFFFF);
2008 if (kvm_lapic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
2009 mask
|= APIC_SPIV_DIRECTED_EOI
;
2010 apic_set_spiv(apic
, val
& mask
);
2011 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
2015 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++) {
2016 lvt_val
= kvm_lapic_get_reg(apic
,
2017 APIC_LVTT
+ 0x10 * i
);
2018 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
2019 lvt_val
| APIC_LVT_MASKED
);
2021 apic_update_lvtt(apic
);
2022 atomic_set(&apic
->lapic_timer
.pending
, 0);
2028 /* No delay here, so we always clear the pending bit */
2030 kvm_apic_send_ipi(apic
, val
, kvm_lapic_get_reg(apic
, APIC_ICR2
));
2031 kvm_lapic_set_reg(apic
, APIC_ICR
, val
);
2035 if (!apic_x2apic_mode(apic
))
2037 kvm_lapic_set_reg(apic
, APIC_ICR2
, val
);
2041 apic_manage_nmi_watchdog(apic
, val
);
2047 /* TODO: Check vector */
2051 if (!kvm_apic_sw_enabled(apic
))
2052 val
|= APIC_LVT_MASKED
;
2053 size
= ARRAY_SIZE(apic_lvt_mask
);
2054 index
= array_index_nospec(
2055 (reg
- APIC_LVTT
) >> 4, size
);
2056 val
&= apic_lvt_mask
[index
];
2057 kvm_lapic_set_reg(apic
, reg
, val
);
2062 if (!kvm_apic_sw_enabled(apic
))
2063 val
|= APIC_LVT_MASKED
;
2064 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
2065 kvm_lapic_set_reg(apic
, APIC_LVTT
, val
);
2066 apic_update_lvtt(apic
);
2070 if (apic_lvtt_tscdeadline(apic
))
2073 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2074 kvm_lapic_set_reg(apic
, APIC_TMICT
, val
);
2075 start_apic_timer(apic
);
2079 uint32_t old_divisor
= apic
->divide_count
;
2081 kvm_lapic_set_reg(apic
, APIC_TDCR
, val
& 0xb);
2082 update_divide_count(apic
);
2083 if (apic
->divide_count
!= old_divisor
&&
2084 apic
->lapic_timer
.period
) {
2085 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2086 update_target_expiration(apic
, old_divisor
);
2087 restart_apic_timer(apic
);
2092 if (apic_x2apic_mode(apic
) && val
!= 0)
2097 if (apic_x2apic_mode(apic
)) {
2098 kvm_lapic_reg_write(apic
, APIC_ICR
,
2099 APIC_DEST_SELF
| (val
& APIC_VECTOR_MASK
));
2108 kvm_recalculate_apic_map(apic
->vcpu
->kvm
);
2112 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write
);
2114 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
2115 gpa_t address
, int len
, const void *data
)
2117 struct kvm_lapic
*apic
= to_lapic(this);
2118 unsigned int offset
= address
- apic
->base_address
;
2121 if (!apic_mmio_in_range(apic
, address
))
2124 if (!kvm_apic_hw_enabled(apic
) || apic_x2apic_mode(apic
)) {
2125 if (!kvm_check_has_quirk(vcpu
->kvm
,
2126 KVM_X86_QUIRK_LAPIC_MMIO_HOLE
))
2133 * APIC register must be aligned on 128-bits boundary.
2134 * 32/64/128 bits registers must be accessed thru 32 bits.
2137 if (len
!= 4 || (offset
& 0xf))
2142 kvm_lapic_reg_write(apic
, offset
& 0xff0, val
);
2147 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
2149 kvm_lapic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
2151 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
2153 /* emulate APIC access in a trap manner */
2154 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
2158 /* hw has done the conditional check and inst decode */
2161 kvm_lapic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
2163 /* TODO: optimize to just emulate side effect w/o one more write */
2164 kvm_lapic_reg_write(vcpu
->arch
.apic
, offset
, val
);
2166 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
2168 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
2170 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2172 if (!vcpu
->arch
.apic
)
2175 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2177 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
2178 static_key_slow_dec_deferred(&apic_hw_disabled
);
2180 if (!apic
->sw_enabled
)
2181 static_key_slow_dec_deferred(&apic_sw_disabled
);
2184 free_page((unsigned long)apic
->regs
);
2190 *----------------------------------------------------------------------
2192 *----------------------------------------------------------------------
2194 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
2196 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2198 if (!kvm_apic_present(vcpu
) || !apic_lvtt_tscdeadline(apic
))
2201 return apic
->lapic_timer
.tscdeadline
;
2204 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
2206 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2208 if (!kvm_apic_present(vcpu
) || !apic_lvtt_tscdeadline(apic
))
2211 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2212 apic
->lapic_timer
.tscdeadline
= data
;
2213 start_apic_timer(apic
);
2216 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
2218 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2220 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
2221 | (kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 4));
2224 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
2228 tpr
= (u64
) kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
2230 return (tpr
& 0xf0) >> 4;
2233 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
2235 u64 old_value
= vcpu
->arch
.apic_base
;
2236 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2239 value
|= MSR_IA32_APICBASE_BSP
;
2241 vcpu
->arch
.apic_base
= value
;
2243 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
)
2244 kvm_update_cpuid_runtime(vcpu
);
2249 /* update jump label if enable bit changes */
2250 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
2251 if (value
& MSR_IA32_APICBASE_ENABLE
) {
2252 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
2253 static_key_slow_dec_deferred(&apic_hw_disabled
);
2255 static_key_slow_inc(&apic_hw_disabled
.key
);
2256 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
2260 if (((old_value
^ value
) & X2APIC_ENABLE
) && (value
& X2APIC_ENABLE
))
2261 kvm_apic_set_x2apic_id(apic
, vcpu
->vcpu_id
);
2263 if ((old_value
^ value
) & (MSR_IA32_APICBASE_ENABLE
| X2APIC_ENABLE
))
2264 kvm_x86_ops
.set_virtual_apic_mode(vcpu
);
2266 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
2267 MSR_IA32_APICBASE_BASE
;
2269 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
2270 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
2271 pr_warn_once("APIC base relocation is unsupported by KVM");
2274 void kvm_apic_update_apicv(struct kvm_vcpu
*vcpu
)
2276 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2278 if (vcpu
->arch
.apicv_active
) {
2279 /* irr_pending is always true when apicv is activated. */
2280 apic
->irr_pending
= true;
2281 apic
->isr_count
= 1;
2283 apic
->irr_pending
= (apic_search_irr(apic
) != -1);
2284 apic
->isr_count
= count_vectors(apic
->regs
+ APIC_ISR
);
2287 EXPORT_SYMBOL_GPL(kvm_apic_update_apicv
);
2289 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
2291 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2297 /* Stop the timer in case it's a reset to an active apic */
2298 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2301 kvm_lapic_set_base(vcpu
, APIC_DEFAULT_PHYS_BASE
|
2302 MSR_IA32_APICBASE_ENABLE
);
2303 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
2305 kvm_apic_set_version(apic
->vcpu
);
2307 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++)
2308 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
2309 apic_update_lvtt(apic
);
2310 if (kvm_vcpu_is_reset_bsp(vcpu
) &&
2311 kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_LINT0_REENABLED
))
2312 kvm_lapic_set_reg(apic
, APIC_LVT0
,
2313 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
2314 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
2316 kvm_apic_set_dfr(apic
, 0xffffffffU
);
2317 apic_set_spiv(apic
, 0xff);
2318 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, 0);
2319 if (!apic_x2apic_mode(apic
))
2320 kvm_apic_set_ldr(apic
, 0);
2321 kvm_lapic_set_reg(apic
, APIC_ESR
, 0);
2322 kvm_lapic_set_reg(apic
, APIC_ICR
, 0);
2323 kvm_lapic_set_reg(apic
, APIC_ICR2
, 0);
2324 kvm_lapic_set_reg(apic
, APIC_TDCR
, 0);
2325 kvm_lapic_set_reg(apic
, APIC_TMICT
, 0);
2326 for (i
= 0; i
< 8; i
++) {
2327 kvm_lapic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
2328 kvm_lapic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
2329 kvm_lapic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
2331 kvm_apic_update_apicv(vcpu
);
2332 apic
->highest_isr_cache
= -1;
2333 update_divide_count(apic
);
2334 atomic_set(&apic
->lapic_timer
.pending
, 0);
2335 if (kvm_vcpu_is_bsp(vcpu
))
2336 kvm_lapic_set_base(vcpu
,
2337 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
2338 vcpu
->arch
.pv_eoi
.msr_val
= 0;
2339 apic_update_ppr(apic
);
2340 if (vcpu
->arch
.apicv_active
) {
2341 kvm_x86_ops
.apicv_post_state_restore(vcpu
);
2342 kvm_x86_ops
.hwapic_irr_update(vcpu
, -1);
2343 kvm_x86_ops
.hwapic_isr_update(vcpu
, -1);
2346 vcpu
->arch
.apic_arb_prio
= 0;
2347 vcpu
->arch
.apic_attention
= 0;
2349 kvm_recalculate_apic_map(vcpu
->kvm
);
2353 *----------------------------------------------------------------------
2355 *----------------------------------------------------------------------
2358 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
2360 return apic_lvtt_period(apic
);
2363 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
2365 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2367 if (apic_enabled(apic
) && apic_lvt_enabled(apic
, APIC_LVTT
))
2368 return atomic_read(&apic
->lapic_timer
.pending
);
2373 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
2375 u32 reg
= kvm_lapic_get_reg(apic
, lvt_type
);
2376 int vector
, mode
, trig_mode
;
2378 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
2379 vector
= reg
& APIC_VECTOR_MASK
;
2380 mode
= reg
& APIC_MODE_MASK
;
2381 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
2382 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
2388 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
2390 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2393 kvm_apic_local_deliver(apic
, APIC_LVT0
);
2396 static const struct kvm_io_device_ops apic_mmio_ops
= {
2397 .read
= apic_mmio_read
,
2398 .write
= apic_mmio_write
,
2401 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
2403 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
2404 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
2406 apic_timer_expired(apic
, true);
2408 if (lapic_is_periodic(apic
)) {
2409 advance_periodic_target_expiration(apic
);
2410 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
2411 return HRTIMER_RESTART
;
2413 return HRTIMER_NORESTART
;
2416 int kvm_create_lapic(struct kvm_vcpu
*vcpu
, int timer_advance_ns
)
2418 struct kvm_lapic
*apic
;
2420 ASSERT(vcpu
!= NULL
);
2422 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL_ACCOUNT
);
2426 vcpu
->arch
.apic
= apic
;
2428 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
2430 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
2432 goto nomem_free_apic
;
2436 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
2437 HRTIMER_MODE_ABS_HARD
);
2438 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
2439 if (timer_advance_ns
== -1) {
2440 apic
->lapic_timer
.timer_advance_ns
= LAPIC_TIMER_ADVANCE_NS_INIT
;
2441 lapic_timer_advance_dynamic
= true;
2443 apic
->lapic_timer
.timer_advance_ns
= timer_advance_ns
;
2444 lapic_timer_advance_dynamic
= false;
2448 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2449 * thinking that APIC state has changed.
2451 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
2452 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
2453 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
2458 vcpu
->arch
.apic
= NULL
;
2463 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
2465 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2468 if (!kvm_apic_hw_enabled(apic
))
2471 __apic_update_ppr(apic
, &ppr
);
2472 return apic_has_interrupt_for_ppr(apic
, ppr
);
2474 EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt
);
2476 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
2478 u32 lvt0
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
2480 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
2482 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
2483 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
2488 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
2490 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2492 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
2493 kvm_apic_inject_pending_timer_irqs(apic
);
2494 atomic_set(&apic
->lapic_timer
.pending
, 0);
2498 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
2500 int vector
= kvm_apic_has_interrupt(vcpu
);
2501 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2508 * We get here even with APIC virtualization enabled, if doing
2509 * nested virtualization and L1 runs with the "acknowledge interrupt
2510 * on exit" mode. Then we cannot inject the interrupt via RVI,
2511 * because the process would deliver it through the IDT.
2514 apic_clear_irr(vector
, apic
);
2515 if (test_bit(vector
, vcpu_to_synic(vcpu
)->auto_eoi_bitmap
)) {
2517 * For auto-EOI interrupts, there might be another pending
2518 * interrupt above PPR, so check whether to raise another
2521 apic_update_ppr(apic
);
2524 * For normal interrupts, PPR has been raised and there cannot
2525 * be a higher-priority pending interrupt---except if there was
2526 * a concurrent interrupt injection, but that would have
2527 * triggered KVM_REQ_EVENT already.
2529 apic_set_isr(vector
, apic
);
2530 __apic_update_ppr(apic
, &ppr
);
2536 static int kvm_apic_state_fixup(struct kvm_vcpu
*vcpu
,
2537 struct kvm_lapic_state
*s
, bool set
)
2539 if (apic_x2apic_mode(vcpu
->arch
.apic
)) {
2540 u32
*id
= (u32
*)(s
->regs
+ APIC_ID
);
2541 u32
*ldr
= (u32
*)(s
->regs
+ APIC_LDR
);
2543 if (vcpu
->kvm
->arch
.x2apic_format
) {
2544 if (*id
!= vcpu
->vcpu_id
)
2553 /* In x2APIC mode, the LDR is fixed and based on the id */
2555 *ldr
= kvm_apic_calc_x2apic_ldr(*id
);
2561 int kvm_apic_get_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2563 memcpy(s
->regs
, vcpu
->arch
.apic
->regs
, sizeof(*s
));
2566 * Get calculated timer current count for remaining timer period (if
2567 * any) and store it in the returned register set.
2569 __kvm_lapic_set_reg(s
->regs
, APIC_TMCCT
,
2570 __apic_read(vcpu
->arch
.apic
, APIC_TMCCT
));
2572 return kvm_apic_state_fixup(vcpu
, s
, false);
2575 int kvm_apic_set_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2577 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2580 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
2581 /* set SPIV separately to get count of SW disabled APICs right */
2582 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
2584 r
= kvm_apic_state_fixup(vcpu
, s
, true);
2586 kvm_recalculate_apic_map(vcpu
->kvm
);
2589 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof(*s
));
2591 atomic_set_release(&apic
->vcpu
->kvm
->arch
.apic_map_dirty
, DIRTY
);
2592 kvm_recalculate_apic_map(vcpu
->kvm
);
2593 kvm_apic_set_version(vcpu
);
2595 apic_update_ppr(apic
);
2596 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2597 apic_update_lvtt(apic
);
2598 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
2599 update_divide_count(apic
);
2600 __start_apic_timer(apic
, APIC_TMCCT
);
2601 kvm_apic_update_apicv(vcpu
);
2602 apic
->highest_isr_cache
= -1;
2603 if (vcpu
->arch
.apicv_active
) {
2604 kvm_x86_ops
.apicv_post_state_restore(vcpu
);
2605 kvm_x86_ops
.hwapic_irr_update(vcpu
,
2606 apic_find_highest_irr(apic
));
2607 kvm_x86_ops
.hwapic_isr_update(vcpu
,
2608 apic_find_highest_isr(apic
));
2610 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2611 if (ioapic_in_kernel(vcpu
->kvm
))
2612 kvm_rtc_eoi_tracking_restore_one(vcpu
);
2614 vcpu
->arch
.apic_arb_prio
= 0;
2619 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
2621 struct hrtimer
*timer
;
2623 if (!lapic_in_kernel(vcpu
) ||
2624 kvm_can_post_timer_interrupt(vcpu
))
2627 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
2628 if (hrtimer_cancel(timer
))
2629 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS_HARD
);
2633 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2635 * Detect whether guest triggered PV EOI since the
2636 * last entry. If yes, set EOI on guests's behalf.
2637 * Clear PV EOI in guest memory in any case.
2639 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
2640 struct kvm_lapic
*apic
)
2645 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2646 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2648 * KVM_APIC_PV_EOI_PENDING is unset:
2649 * -> host disabled PV EOI.
2650 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2651 * -> host enabled PV EOI, guest did not execute EOI yet.
2652 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2653 * -> host enabled PV EOI, guest executed EOI.
2655 BUG_ON(!pv_eoi_enabled(vcpu
));
2656 pending
= pv_eoi_get_pending(vcpu
);
2658 * Clear pending bit in any case: it will be set again on vmentry.
2659 * While this might not be ideal from performance point of view,
2660 * this makes sure pv eoi is only enabled when we know it's safe.
2662 pv_eoi_clr_pending(vcpu
);
2665 vector
= apic_set_eoi(apic
);
2666 trace_kvm_pv_eoi(apic
, vector
);
2669 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
2673 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
2674 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
2676 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2679 if (kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2683 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
2687 * apic_sync_pv_eoi_to_guest - called before vmentry
2689 * Detect whether it's safe to enable PV EOI and
2692 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
2693 struct kvm_lapic
*apic
)
2695 if (!pv_eoi_enabled(vcpu
) ||
2696 /* IRR set or many bits in ISR: could be nested. */
2697 apic
->irr_pending
||
2698 /* Cache not set: could be safe but we don't bother. */
2699 apic
->highest_isr_cache
== -1 ||
2700 /* Need EOI to update ioapic. */
2701 kvm_ioapic_handles_vector(apic
, apic
->highest_isr_cache
)) {
2703 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2704 * so we need not do anything here.
2709 pv_eoi_set_pending(apic
->vcpu
);
2712 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
2715 int max_irr
, max_isr
;
2716 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2718 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
2720 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2723 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
2724 max_irr
= apic_find_highest_irr(apic
);
2727 max_isr
= apic_find_highest_isr(apic
);
2730 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
2732 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2736 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
2739 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
2740 &vcpu
->arch
.apic
->vapic_cache
,
2741 vapic_addr
, sizeof(u32
)))
2743 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2745 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2748 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
2752 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
2754 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2755 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
2757 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2760 if (reg
== APIC_ICR2
)
2763 /* if this is ICR write vector before command */
2764 if (reg
== APIC_ICR
)
2765 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2766 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2769 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
2771 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2772 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
2774 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2777 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
)
2780 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2782 if (reg
== APIC_ICR
)
2783 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2785 *data
= (((u64
)high
) << 32) | low
;
2790 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
2792 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2794 if (!lapic_in_kernel(vcpu
))
2797 /* if this is ICR write vector before command */
2798 if (reg
== APIC_ICR
)
2799 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2800 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2803 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2805 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2808 if (!lapic_in_kernel(vcpu
))
2811 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2813 if (reg
== APIC_ICR
)
2814 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2816 *data
= (((u64
)high
) << 32) | low
;
2821 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
, unsigned long len
)
2823 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2824 struct gfn_to_hva_cache
*ghc
= &vcpu
->arch
.pv_eoi
.data
;
2825 unsigned long new_len
;
2827 if (!IS_ALIGNED(addr
, 4))
2830 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2831 if (!pv_eoi_enabled(vcpu
))
2834 if (addr
== ghc
->gpa
&& len
<= ghc
->len
)
2839 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, ghc
, addr
, new_len
);
2842 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2844 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2848 if (!lapic_in_kernel(vcpu
) || !apic
->pending_events
)
2852 * INITs are latched while CPU is in specific states
2853 * (SMM, VMX non-root mode, SVM with GIF=0).
2854 * Because a CPU cannot be in these states immediately
2855 * after it has processed an INIT signal (and thus in
2856 * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2857 * and leave the INIT pending.
2859 if (kvm_vcpu_latch_init(vcpu
)) {
2860 WARN_ON_ONCE(vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
);
2861 if (test_bit(KVM_APIC_SIPI
, &apic
->pending_events
))
2862 clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
2866 pe
= xchg(&apic
->pending_events
, 0);
2867 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2868 kvm_vcpu_reset(vcpu
, true);
2869 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2870 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2872 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2874 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2875 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2876 /* evaluate pending_events before reading the vector */
2878 sipi_vector
= apic
->sipi_vector
;
2879 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2880 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2884 void kvm_lapic_init(void)
2886 /* do not patch jump label more than once per second */
2887 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2888 jump_label_rate_limit(&apic_sw_disabled
, HZ
);
2891 void kvm_lapic_exit(void)
2893 static_key_deferred_flush(&apic_hw_disabled
);
2894 static_key_deferred_flush(&apic_sw_disabled
);