3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 #define APIC_BUS_CYCLE_NS 1
59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60 #define apic_debug(fmt, arg...)
62 #define APIC_LVT_NUM 6
63 /* 14 is the version for Xeon and Pentium 8.4.8*/
64 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
65 #define LAPIC_MMIO_LENGTH (1 << 12)
66 /* followed define is not in apicdef.h */
67 #define APIC_SHORT_MASK 0xc0000
68 #define APIC_DEST_NOSHORT 0x0
69 #define APIC_DEST_MASK 0x800
70 #define MAX_APIC_VECTOR 256
71 #define APIC_VECTORS_PER_REG 32
73 #define APIC_BROADCAST 0xFF
74 #define X2APIC_BROADCAST 0xFFFFFFFFul
76 #define VEC_POS(v) ((v) & (32 - 1))
77 #define REG_POS(v) (((v) >> 5) << 4)
79 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
81 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
84 static inline int apic_test_vector(int vec
, void *bitmap
)
86 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
89 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
91 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
93 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
94 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
97 static inline void apic_set_vector(int vec
, void *bitmap
)
99 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
102 static inline void apic_clear_vector(int vec
, void *bitmap
)
104 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
107 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
109 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
112 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
114 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
117 struct static_key_deferred apic_hw_disabled __read_mostly
;
118 struct static_key_deferred apic_sw_disabled __read_mostly
;
120 static inline int apic_enabled(struct kvm_lapic
*apic
)
122 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
126 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
129 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
130 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
132 /* The logical map is definitely wrong if we have multiple
133 * modes at the same time. (Physical map is always right.)
135 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map
*map
)
137 return !(map
->mode
& (map
->mode
- 1));
141 apic_logical_id(struct kvm_apic_map
*map
, u32 dest_id
, u16
*cid
, u16
*lid
)
145 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER
!= 4);
146 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT
!= 8);
147 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC
!= 16);
148 lid_bits
= map
->mode
;
150 *cid
= dest_id
>> lid_bits
;
151 *lid
= dest_id
& ((1 << lid_bits
) - 1);
154 static void recalculate_apic_map(struct kvm
*kvm
)
156 struct kvm_apic_map
*new, *old
= NULL
;
157 struct kvm_vcpu
*vcpu
;
160 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
162 mutex_lock(&kvm
->arch
.apic_map_lock
);
167 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
168 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
172 if (!kvm_apic_present(vcpu
))
175 aid
= kvm_apic_id(apic
);
176 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
178 if (aid
< ARRAY_SIZE(new->phys_map
))
179 new->phys_map
[aid
] = apic
;
181 if (apic_x2apic_mode(apic
)) {
182 new->mode
|= KVM_APIC_MODE_X2APIC
;
184 ldr
= GET_APIC_LOGICAL_ID(ldr
);
185 if (kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
186 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
188 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
191 if (!kvm_apic_logical_map_valid(new))
194 apic_logical_id(new, ldr
, &cid
, &lid
);
196 if (lid
&& cid
< ARRAY_SIZE(new->logical_map
))
197 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
200 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
201 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
202 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
203 mutex_unlock(&kvm
->arch
.apic_map_lock
);
208 kvm_make_scan_ioapic_request(kvm
);
211 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
213 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
215 apic_set_reg(apic
, APIC_SPIV
, val
);
217 if (enabled
!= apic
->sw_enabled
) {
218 apic
->sw_enabled
= enabled
;
220 static_key_slow_dec_deferred(&apic_sw_disabled
);
221 recalculate_apic_map(apic
->vcpu
->kvm
);
223 static_key_slow_inc(&apic_sw_disabled
.key
);
227 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
229 apic_set_reg(apic
, APIC_ID
, id
<< 24);
230 recalculate_apic_map(apic
->vcpu
->kvm
);
233 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
235 apic_set_reg(apic
, APIC_LDR
, id
);
236 recalculate_apic_map(apic
->vcpu
->kvm
);
239 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic
*apic
, u8 id
)
241 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
243 apic_set_reg(apic
, APIC_ID
, id
<< 24);
244 apic_set_reg(apic
, APIC_LDR
, ldr
);
245 recalculate_apic_map(apic
->vcpu
->kvm
);
248 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
250 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
253 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
255 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
258 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
260 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
263 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
265 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
268 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
270 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
273 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
275 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
278 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
280 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
281 struct kvm_cpuid_entry2
*feat
;
282 u32 v
= APIC_VERSION
;
284 if (!kvm_vcpu_has_lapic(vcpu
))
287 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
288 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
289 v
|= APIC_LVR_DIRECTED_EOI
;
290 apic_set_reg(apic
, APIC_LVR
, v
);
293 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
294 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
295 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
296 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
297 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
298 LVT_MASK
/* LVTERR */
301 static int find_highest_vector(void *bitmap
)
306 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
307 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
308 reg
= bitmap
+ REG_POS(vec
);
310 return fls(*reg
) - 1 + vec
;
316 static u8
count_vectors(void *bitmap
)
322 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
323 reg
= bitmap
+ REG_POS(vec
);
324 count
+= hweight32(*reg
);
330 void __kvm_apic_update_irr(u32
*pir
, void *regs
)
334 for (i
= 0; i
<= 7; i
++) {
335 pir_val
= xchg(&pir
[i
], 0);
337 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
340 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
342 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
344 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
346 __kvm_apic_update_irr(pir
, apic
->regs
);
348 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
350 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
352 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
354 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
356 * irr_pending must be true if any interrupt is pending; set it after
357 * APIC_IRR to avoid race with apic_clear_irr
359 apic
->irr_pending
= true;
362 static inline int apic_search_irr(struct kvm_lapic
*apic
)
364 return find_highest_vector(apic
->regs
+ APIC_IRR
);
367 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
372 * Note that irr_pending is just a hint. It will be always
373 * true with virtual interrupt delivery enabled.
375 if (!apic
->irr_pending
)
378 if (apic
->vcpu
->arch
.apicv_active
)
379 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
380 result
= apic_search_irr(apic
);
381 ASSERT(result
== -1 || result
>= 16);
386 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
388 struct kvm_vcpu
*vcpu
;
392 if (unlikely(vcpu
->arch
.apicv_active
)) {
393 /* try to update RVI */
394 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
395 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
397 apic
->irr_pending
= false;
398 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
399 if (apic_search_irr(apic
) != -1)
400 apic
->irr_pending
= true;
404 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
406 struct kvm_vcpu
*vcpu
;
408 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
414 * With APIC virtualization enabled, all caching is disabled
415 * because the processor can modify ISR under the hood. Instead
418 if (unlikely(vcpu
->arch
.apicv_active
))
419 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
422 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
424 * ISR (in service register) bit is set when injecting an interrupt.
425 * The highest vector is injected. Thus the latest bit set matches
426 * the highest bit in ISR.
428 apic
->highest_isr_cache
= vec
;
432 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
437 * Note that isr_count is always 1, and highest_isr_cache
438 * is always -1, with APIC virtualization enabled.
440 if (!apic
->isr_count
)
442 if (likely(apic
->highest_isr_cache
!= -1))
443 return apic
->highest_isr_cache
;
445 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
446 ASSERT(result
== -1 || result
>= 16);
451 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
453 struct kvm_vcpu
*vcpu
;
454 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
460 * We do get here for APIC virtualization enabled if the guest
461 * uses the Hyper-V APIC enlightenment. In this case we may need
462 * to trigger a new interrupt delivery by writing the SVI field;
463 * on the other hand isr_count and highest_isr_cache are unused
464 * and must be left alone.
466 if (unlikely(vcpu
->arch
.apicv_active
))
467 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
468 apic_find_highest_isr(apic
));
471 BUG_ON(apic
->isr_count
< 0);
472 apic
->highest_isr_cache
= -1;
476 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
480 /* This may race with setting of irr in __apic_accept_irq() and
481 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
482 * will cause vmexit immediately and the value will be recalculated
483 * on the next vmentry.
485 if (!kvm_vcpu_has_lapic(vcpu
))
487 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
492 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
493 int vector
, int level
, int trig_mode
,
494 unsigned long *dest_map
);
496 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
497 unsigned long *dest_map
)
499 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
501 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
502 irq
->level
, irq
->trig_mode
, dest_map
);
505 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
508 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
512 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
515 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
519 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
521 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
524 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
527 if (pv_eoi_get_user(vcpu
, &val
) < 0)
528 apic_debug("Can't read EOI MSR value: 0x%llx\n",
529 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
533 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
535 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
536 apic_debug("Can't set EOI MSR value: 0x%llx\n",
537 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
540 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
543 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
545 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
546 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
547 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
550 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
553 static void apic_update_ppr(struct kvm_lapic
*apic
)
555 u32 tpr
, isrv
, ppr
, old_ppr
;
558 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
559 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
560 isr
= apic_find_highest_isr(apic
);
561 isrv
= (isr
!= -1) ? isr
: 0;
563 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
568 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
569 apic
, ppr
, isr
, isrv
);
571 if (old_ppr
!= ppr
) {
572 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
574 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
578 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
580 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
581 apic_update_ppr(apic
);
584 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
586 if (apic_x2apic_mode(apic
))
587 return mda
== X2APIC_BROADCAST
;
589 return GET_APIC_DEST_FIELD(mda
) == APIC_BROADCAST
;
592 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
594 if (kvm_apic_broadcast(apic
, mda
))
597 if (apic_x2apic_mode(apic
))
598 return mda
== kvm_apic_id(apic
);
600 return mda
== SET_APIC_DEST_FIELD(kvm_apic_id(apic
));
603 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
607 if (kvm_apic_broadcast(apic
, mda
))
610 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
612 if (apic_x2apic_mode(apic
))
613 return ((logical_id
>> 16) == (mda
>> 16))
614 && (logical_id
& mda
& 0xffff) != 0;
616 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
617 mda
= GET_APIC_DEST_FIELD(mda
);
619 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
621 return (logical_id
& mda
) != 0;
622 case APIC_DFR_CLUSTER
:
623 return ((logical_id
>> 4) == (mda
>> 4))
624 && (logical_id
& mda
& 0xf) != 0;
626 apic_debug("Bad DFR vcpu %d: %08x\n",
627 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
632 /* KVM APIC implementation has two quirks
633 * - dest always begins at 0 while xAPIC MDA has offset 24,
634 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
636 static u32
kvm_apic_mda(unsigned int dest_id
, struct kvm_lapic
*source
,
637 struct kvm_lapic
*target
)
639 bool ipi
= source
!= NULL
;
640 bool x2apic_mda
= apic_x2apic_mode(ipi
? source
: target
);
642 if (!ipi
&& dest_id
== APIC_BROADCAST
&& x2apic_mda
)
643 return X2APIC_BROADCAST
;
645 return x2apic_mda
? dest_id
: SET_APIC_DEST_FIELD(dest_id
);
648 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
649 int short_hand
, unsigned int dest
, int dest_mode
)
651 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
652 u32 mda
= kvm_apic_mda(dest
, source
, target
);
654 apic_debug("target %p, source %p, dest 0x%x, "
655 "dest_mode 0x%x, short_hand 0x%x\n",
656 target
, source
, dest
, dest_mode
, short_hand
);
659 switch (short_hand
) {
660 case APIC_DEST_NOSHORT
:
661 if (dest_mode
== APIC_DEST_PHYSICAL
)
662 return kvm_apic_match_physical_addr(target
, mda
);
664 return kvm_apic_match_logical_addr(target
, mda
);
666 return target
== source
;
667 case APIC_DEST_ALLINC
:
669 case APIC_DEST_ALLBUT
:
670 return target
!= source
;
672 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
678 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
679 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
681 struct kvm_apic_map
*map
;
682 unsigned long bitmap
= 1;
683 struct kvm_lapic
**dst
;
685 bool ret
, x2apic_ipi
;
689 if (irq
->shorthand
== APIC_DEST_SELF
) {
690 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
697 x2apic_ipi
= src
&& apic_x2apic_mode(src
);
698 if (irq
->dest_id
== (x2apic_ipi
? X2APIC_BROADCAST
: APIC_BROADCAST
))
703 map
= rcu_dereference(kvm
->arch
.apic_map
);
710 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
711 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
714 dst
= &map
->phys_map
[irq
->dest_id
];
718 if (!kvm_apic_logical_map_valid(map
)) {
723 apic_logical_id(map
, irq
->dest_id
, &cid
, (u16
*)&bitmap
);
725 if (cid
>= ARRAY_SIZE(map
->logical_map
))
728 dst
= map
->logical_map
[cid
];
730 if (kvm_lowest_prio_delivery(irq
)) {
732 for_each_set_bit(i
, &bitmap
, 16) {
737 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
741 bitmap
= (l
>= 0) ? 1 << l
: 0;
745 for_each_set_bit(i
, &bitmap
, 16) {
750 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
757 bool kvm_intr_is_single_vcpu_fast(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
758 struct kvm_vcpu
**dest_vcpu
)
760 struct kvm_apic_map
*map
;
762 struct kvm_lapic
*dst
= NULL
;
768 map
= rcu_dereference(kvm
->arch
.apic_map
);
773 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
774 if (irq
->dest_id
== 0xFF)
777 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
780 dst
= map
->phys_map
[irq
->dest_id
];
781 if (dst
&& kvm_apic_present(dst
->vcpu
))
782 *dest_vcpu
= dst
->vcpu
;
787 unsigned long bitmap
= 1;
790 if (!kvm_apic_logical_map_valid(map
))
793 apic_logical_id(map
, irq
->dest_id
, &cid
, (u16
*)&bitmap
);
795 if (cid
>= ARRAY_SIZE(map
->logical_map
))
798 for_each_set_bit(i
, &bitmap
, 16) {
799 dst
= map
->logical_map
[cid
][i
];
804 if (dst
&& kvm_apic_present(dst
->vcpu
))
805 *dest_vcpu
= dst
->vcpu
;
817 * Add a pending IRQ into lapic.
818 * Return 1 if successfully added and 0 if discarded.
820 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
821 int vector
, int level
, int trig_mode
,
822 unsigned long *dest_map
)
825 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
827 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
829 switch (delivery_mode
) {
831 vcpu
->arch
.apic_arb_prio
++;
833 if (unlikely(trig_mode
&& !level
))
836 /* FIXME add logic for vcpu on reset */
837 if (unlikely(!apic_enabled(apic
)))
843 __set_bit(vcpu
->vcpu_id
, dest_map
);
845 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
) != !!trig_mode
) {
847 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
849 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
852 if (vcpu
->arch
.apicv_active
)
853 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
855 apic_set_irr(vector
, apic
);
857 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
864 vcpu
->arch
.pv
.pv_unhalted
= 1;
865 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
871 kvm_make_request(KVM_REQ_SMI
, vcpu
);
877 kvm_inject_nmi(vcpu
);
882 if (!trig_mode
|| level
) {
884 /* assumes that there are only KVM_APIC_INIT/SIPI */
885 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
886 /* make sure pending_events is visible before sending
889 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
892 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
897 case APIC_DM_STARTUP
:
898 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
899 vcpu
->vcpu_id
, vector
);
901 apic
->sipi_vector
= vector
;
902 /* make sure sipi_vector is visible for the receiver */
904 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
905 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
911 * Should only be called by kvm_apic_local_deliver() with LVT0,
912 * before NMI watchdog was enabled. Already handled by
913 * kvm_apic_accept_pic_intr().
918 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
925 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
927 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
930 static bool kvm_ioapic_handles_vector(struct kvm_lapic
*apic
, int vector
)
932 return test_bit(vector
, apic
->vcpu
->arch
.ioapic_handled_vectors
);
935 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
939 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
940 if (!kvm_ioapic_handles_vector(apic
, vector
))
943 /* Request a KVM exit to inform the userspace IOAPIC. */
944 if (irqchip_split(apic
->vcpu
->kvm
)) {
945 apic
->vcpu
->arch
.pending_ioapic_eoi
= vector
;
946 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT
, apic
->vcpu
);
950 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
951 trigger_mode
= IOAPIC_LEVEL_TRIG
;
953 trigger_mode
= IOAPIC_EDGE_TRIG
;
955 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
958 static int apic_set_eoi(struct kvm_lapic
*apic
)
960 int vector
= apic_find_highest_isr(apic
);
962 trace_kvm_eoi(apic
, vector
);
965 * Not every write EOI will has corresponding ISR,
966 * one example is when Kernel check timer on setup_IO_APIC
971 apic_clear_isr(vector
, apic
);
972 apic_update_ppr(apic
);
974 if (test_bit(vector
, vcpu_to_synic(apic
->vcpu
)->vec_bitmap
))
975 kvm_hv_synic_send_eoi(apic
->vcpu
, vector
);
977 kvm_ioapic_send_eoi(apic
, vector
);
978 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
983 * this interface assumes a trap-like exit, which has already finished
984 * desired side effect including vISR and vPPR update.
986 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
988 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
990 trace_kvm_eoi(apic
, vector
);
992 kvm_ioapic_send_eoi(apic
, vector
);
993 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
995 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
997 static void apic_send_ipi(struct kvm_lapic
*apic
)
999 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
1000 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
1001 struct kvm_lapic_irq irq
;
1003 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
1004 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
1005 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
1006 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
1007 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
1008 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
1009 irq
.msi_redir_hint
= false;
1010 if (apic_x2apic_mode(apic
))
1011 irq
.dest_id
= icr_high
;
1013 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
1015 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
1017 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1018 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1019 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1020 "msi_redir_hint 0x%x\n",
1021 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
1022 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
1023 irq
.vector
, irq
.msi_redir_hint
);
1025 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
1028 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
1034 ASSERT(apic
!= NULL
);
1036 /* if initial count is 0, current count should also be 0 */
1037 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
1038 apic
->lapic_timer
.period
== 0)
1041 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
1042 if (ktime_to_ns(remaining
) < 0)
1043 remaining
= ktime_set(0, 0);
1045 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
1046 tmcct
= div64_u64(ns
,
1047 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
1052 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1054 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1055 struct kvm_run
*run
= vcpu
->run
;
1057 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
1058 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
1059 run
->tpr_access
.is_write
= write
;
1062 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1064 if (apic
->vcpu
->arch
.tpr_access_reporting
)
1065 __report_tpr_access(apic
, write
);
1068 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
1072 if (offset
>= LAPIC_MMIO_LENGTH
)
1077 if (apic_x2apic_mode(apic
))
1078 val
= kvm_apic_id(apic
);
1080 val
= kvm_apic_id(apic
) << 24;
1083 apic_debug("Access APIC ARBPRI register which is for P6\n");
1086 case APIC_TMCCT
: /* Timer CCR */
1087 if (apic_lvtt_tscdeadline(apic
))
1090 val
= apic_get_tmcct(apic
);
1093 apic_update_ppr(apic
);
1094 val
= kvm_apic_get_reg(apic
, offset
);
1097 report_tpr_access(apic
, false);
1100 val
= kvm_apic_get_reg(apic
, offset
);
1107 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1109 return container_of(dev
, struct kvm_lapic
, dev
);
1112 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1115 unsigned char alignment
= offset
& 0xf;
1117 /* this bitmask has a bit cleared for each reserved register */
1118 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1120 if ((alignment
+ len
) > 4) {
1121 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1126 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1127 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1132 result
= __apic_read(apic
, offset
& ~0xf);
1134 trace_kvm_apic_read(offset
, result
);
1140 memcpy(data
, (char *)&result
+ alignment
, len
);
1143 printk(KERN_ERR
"Local APIC read with len = %x, "
1144 "should be 1,2, or 4 instead\n", len
);
1150 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1152 return kvm_apic_hw_enabled(apic
) &&
1153 addr
>= apic
->base_address
&&
1154 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1157 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1158 gpa_t address
, int len
, void *data
)
1160 struct kvm_lapic
*apic
= to_lapic(this);
1161 u32 offset
= address
- apic
->base_address
;
1163 if (!apic_mmio_in_range(apic
, address
))
1166 apic_reg_read(apic
, offset
, len
, data
);
1171 static void update_divide_count(struct kvm_lapic
*apic
)
1173 u32 tmp1
, tmp2
, tdcr
;
1175 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1177 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1178 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1180 apic_debug("timer divide count is 0x%x\n",
1181 apic
->divide_count
);
1184 static void apic_update_lvtt(struct kvm_lapic
*apic
)
1186 u32 timer_mode
= kvm_apic_get_reg(apic
, APIC_LVTT
) &
1187 apic
->lapic_timer
.timer_mode_mask
;
1189 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1190 apic
->lapic_timer
.timer_mode
= timer_mode
;
1191 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1195 static void apic_timer_expired(struct kvm_lapic
*apic
)
1197 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1198 wait_queue_head_t
*q
= &vcpu
->wq
;
1199 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1201 if (atomic_read(&apic
->lapic_timer
.pending
))
1204 atomic_inc(&apic
->lapic_timer
.pending
);
1205 kvm_set_pending_timer(vcpu
);
1207 if (waitqueue_active(q
))
1208 wake_up_interruptible(q
);
1210 if (apic_lvtt_tscdeadline(apic
))
1211 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1215 * On APICv, this test will cause a busy wait
1216 * during a higher-priority task.
1219 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1221 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1222 u32 reg
= kvm_apic_get_reg(apic
, APIC_LVTT
);
1224 if (kvm_apic_hw_enabled(apic
)) {
1225 int vec
= reg
& APIC_VECTOR_MASK
;
1226 void *bitmap
= apic
->regs
+ APIC_ISR
;
1228 if (vcpu
->arch
.apicv_active
)
1229 bitmap
= apic
->regs
+ APIC_IRR
;
1231 if (apic_test_vector(vec
, bitmap
))
1237 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1239 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1240 u64 guest_tsc
, tsc_deadline
;
1242 if (!kvm_vcpu_has_lapic(vcpu
))
1245 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1248 if (!lapic_timer_int_injected(vcpu
))
1251 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1252 apic
->lapic_timer
.expired_tscdeadline
= 0;
1253 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1254 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1256 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1257 if (guest_tsc
< tsc_deadline
)
1258 __delay(tsc_deadline
- guest_tsc
);
1261 static void start_apic_timer(struct kvm_lapic
*apic
)
1265 atomic_set(&apic
->lapic_timer
.pending
, 0);
1267 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1268 /* lapic timer in oneshot or periodic mode */
1269 now
= apic
->lapic_timer
.timer
.base
->get_time();
1270 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1271 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1273 if (!apic
->lapic_timer
.period
)
1276 * Do not allow the guest to program periodic timers with small
1277 * interval, since the hrtimers are not throttled by the host
1280 if (apic_lvtt_period(apic
)) {
1281 s64 min_period
= min_timer_period_us
* 1000LL;
1283 if (apic
->lapic_timer
.period
< min_period
) {
1284 pr_info_ratelimited(
1285 "kvm: vcpu %i: requested %lld ns "
1286 "lapic timer period limited to %lld ns\n",
1287 apic
->vcpu
->vcpu_id
,
1288 apic
->lapic_timer
.period
, min_period
);
1289 apic
->lapic_timer
.period
= min_period
;
1293 hrtimer_start(&apic
->lapic_timer
.timer
,
1294 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1297 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1299 "timer initial count 0x%x, period %lldns, "
1300 "expire @ 0x%016" PRIx64
".\n", __func__
,
1301 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1302 kvm_apic_get_reg(apic
, APIC_TMICT
),
1303 apic
->lapic_timer
.period
,
1304 ktime_to_ns(ktime_add_ns(now
,
1305 apic
->lapic_timer
.period
)));
1306 } else if (apic_lvtt_tscdeadline(apic
)) {
1307 /* lapic timer in tsc deadline mode */
1308 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1311 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1312 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1313 unsigned long flags
;
1315 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1318 local_irq_save(flags
);
1320 now
= apic
->lapic_timer
.timer
.base
->get_time();
1321 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1322 if (likely(tscdeadline
> guest_tsc
)) {
1323 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1324 do_div(ns
, this_tsc_khz
);
1325 expire
= ktime_add_ns(now
, ns
);
1326 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1327 hrtimer_start(&apic
->lapic_timer
.timer
,
1328 expire
, HRTIMER_MODE_ABS
);
1330 apic_timer_expired(apic
);
1332 local_irq_restore(flags
);
1336 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1338 bool lvt0_in_nmi_mode
= apic_lvt_nmi_mode(lvt0_val
);
1340 if (apic
->lvt0_in_nmi_mode
!= lvt0_in_nmi_mode
) {
1341 apic
->lvt0_in_nmi_mode
= lvt0_in_nmi_mode
;
1342 if (lvt0_in_nmi_mode
) {
1343 apic_debug("Receive NMI setting on APIC_LVT0 "
1344 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1345 atomic_inc(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1347 atomic_dec(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1351 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1355 trace_kvm_apic_write(reg
, val
);
1358 case APIC_ID
: /* Local APIC ID */
1359 if (!apic_x2apic_mode(apic
))
1360 kvm_apic_set_id(apic
, val
>> 24);
1366 report_tpr_access(apic
, true);
1367 apic_set_tpr(apic
, val
& 0xff);
1375 if (!apic_x2apic_mode(apic
))
1376 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1382 if (!apic_x2apic_mode(apic
)) {
1383 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1384 recalculate_apic_map(apic
->vcpu
->kvm
);
1391 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1392 mask
|= APIC_SPIV_DIRECTED_EOI
;
1393 apic_set_spiv(apic
, val
& mask
);
1394 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1398 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1399 lvt_val
= kvm_apic_get_reg(apic
,
1400 APIC_LVTT
+ 0x10 * i
);
1401 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1402 lvt_val
| APIC_LVT_MASKED
);
1404 apic_update_lvtt(apic
);
1405 atomic_set(&apic
->lapic_timer
.pending
, 0);
1411 /* No delay here, so we always clear the pending bit */
1412 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1413 apic_send_ipi(apic
);
1417 if (!apic_x2apic_mode(apic
))
1419 apic_set_reg(apic
, APIC_ICR2
, val
);
1423 apic_manage_nmi_watchdog(apic
, val
);
1428 /* TODO: Check vector */
1429 if (!kvm_apic_sw_enabled(apic
))
1430 val
|= APIC_LVT_MASKED
;
1432 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1433 apic_set_reg(apic
, reg
, val
);
1438 if (!kvm_apic_sw_enabled(apic
))
1439 val
|= APIC_LVT_MASKED
;
1440 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1441 apic_set_reg(apic
, APIC_LVTT
, val
);
1442 apic_update_lvtt(apic
);
1446 if (apic_lvtt_tscdeadline(apic
))
1449 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1450 apic_set_reg(apic
, APIC_TMICT
, val
);
1451 start_apic_timer(apic
);
1456 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1457 apic_set_reg(apic
, APIC_TDCR
, val
);
1458 update_divide_count(apic
);
1462 if (apic_x2apic_mode(apic
) && val
!= 0) {
1463 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1469 if (apic_x2apic_mode(apic
)) {
1470 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1479 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1483 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1484 gpa_t address
, int len
, const void *data
)
1486 struct kvm_lapic
*apic
= to_lapic(this);
1487 unsigned int offset
= address
- apic
->base_address
;
1490 if (!apic_mmio_in_range(apic
, address
))
1494 * APIC register must be aligned on 128-bits boundary.
1495 * 32/64/128 bits registers must be accessed thru 32 bits.
1498 if (len
!= 4 || (offset
& 0xf)) {
1499 /* Don't shout loud, $infamous_os would cause only noise. */
1500 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1506 /* too common printing */
1507 if (offset
!= APIC_EOI
)
1508 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1509 "0x%x\n", __func__
, offset
, len
, val
);
1511 apic_reg_write(apic
, offset
& 0xff0, val
);
1516 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1518 if (kvm_vcpu_has_lapic(vcpu
))
1519 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1521 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1523 /* emulate APIC access in a trap manner */
1524 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1528 /* hw has done the conditional check and inst decode */
1531 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1533 /* TODO: optimize to just emulate side effect w/o one more write */
1534 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1536 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1538 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1540 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1542 if (!vcpu
->arch
.apic
)
1545 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1547 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1548 static_key_slow_dec_deferred(&apic_hw_disabled
);
1550 if (!apic
->sw_enabled
)
1551 static_key_slow_dec_deferred(&apic_sw_disabled
);
1554 free_page((unsigned long)apic
->regs
);
1560 *----------------------------------------------------------------------
1562 *----------------------------------------------------------------------
1565 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1567 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1569 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1570 apic_lvtt_period(apic
))
1573 return apic
->lapic_timer
.tscdeadline
;
1576 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1578 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1580 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1581 apic_lvtt_period(apic
))
1584 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1585 apic
->lapic_timer
.tscdeadline
= data
;
1586 start_apic_timer(apic
);
1589 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1591 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1593 if (!kvm_vcpu_has_lapic(vcpu
))
1596 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1597 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1600 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1604 if (!kvm_vcpu_has_lapic(vcpu
))
1607 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1609 return (tpr
& 0xf0) >> 4;
1612 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1614 u64 old_value
= vcpu
->arch
.apic_base
;
1615 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1618 value
|= MSR_IA32_APICBASE_BSP
;
1619 vcpu
->arch
.apic_base
= value
;
1623 vcpu
->arch
.apic_base
= value
;
1625 /* update jump label if enable bit changes */
1626 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1627 if (value
& MSR_IA32_APICBASE_ENABLE
)
1628 static_key_slow_dec_deferred(&apic_hw_disabled
);
1630 static_key_slow_inc(&apic_hw_disabled
.key
);
1631 recalculate_apic_map(vcpu
->kvm
);
1634 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1635 if (value
& X2APIC_ENABLE
) {
1636 kvm_apic_set_x2apic_id(apic
, vcpu
->vcpu_id
);
1637 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1639 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1642 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1643 MSR_IA32_APICBASE_BASE
;
1645 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1646 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1647 pr_warn_once("APIC base relocation is unsupported by KVM");
1649 /* with FSB delivery interrupt, we can restart APIC functionality */
1650 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1651 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1655 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1657 struct kvm_lapic
*apic
;
1660 apic_debug("%s\n", __func__
);
1663 apic
= vcpu
->arch
.apic
;
1664 ASSERT(apic
!= NULL
);
1666 /* Stop the timer in case it's a reset to an active apic */
1667 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1670 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1671 kvm_apic_set_version(apic
->vcpu
);
1673 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1674 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1675 apic_update_lvtt(apic
);
1676 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_LINT0_REENABLED
))
1677 apic_set_reg(apic
, APIC_LVT0
,
1678 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1679 apic_manage_nmi_watchdog(apic
, kvm_apic_get_reg(apic
, APIC_LVT0
));
1681 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1682 apic_set_spiv(apic
, 0xff);
1683 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1684 if (!apic_x2apic_mode(apic
))
1685 kvm_apic_set_ldr(apic
, 0);
1686 apic_set_reg(apic
, APIC_ESR
, 0);
1687 apic_set_reg(apic
, APIC_ICR
, 0);
1688 apic_set_reg(apic
, APIC_ICR2
, 0);
1689 apic_set_reg(apic
, APIC_TDCR
, 0);
1690 apic_set_reg(apic
, APIC_TMICT
, 0);
1691 for (i
= 0; i
< 8; i
++) {
1692 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1693 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1694 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1696 apic
->irr_pending
= vcpu
->arch
.apicv_active
;
1697 apic
->isr_count
= vcpu
->arch
.apicv_active
? 1 : 0;
1698 apic
->highest_isr_cache
= -1;
1699 update_divide_count(apic
);
1700 atomic_set(&apic
->lapic_timer
.pending
, 0);
1701 if (kvm_vcpu_is_bsp(vcpu
))
1702 kvm_lapic_set_base(vcpu
,
1703 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1704 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1705 apic_update_ppr(apic
);
1707 vcpu
->arch
.apic_arb_prio
= 0;
1708 vcpu
->arch
.apic_attention
= 0;
1710 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1711 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1712 vcpu
, kvm_apic_id(apic
),
1713 vcpu
->arch
.apic_base
, apic
->base_address
);
1717 *----------------------------------------------------------------------
1719 *----------------------------------------------------------------------
1722 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1724 return apic_lvtt_period(apic
);
1727 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1729 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1731 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1732 apic_lvt_enabled(apic
, APIC_LVTT
))
1733 return atomic_read(&apic
->lapic_timer
.pending
);
1738 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1740 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1741 int vector
, mode
, trig_mode
;
1743 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1744 vector
= reg
& APIC_VECTOR_MASK
;
1745 mode
= reg
& APIC_MODE_MASK
;
1746 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1747 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1753 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1755 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1758 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1761 static const struct kvm_io_device_ops apic_mmio_ops
= {
1762 .read
= apic_mmio_read
,
1763 .write
= apic_mmio_write
,
1766 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1768 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1769 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1771 apic_timer_expired(apic
);
1773 if (lapic_is_periodic(apic
)) {
1774 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1775 return HRTIMER_RESTART
;
1777 return HRTIMER_NORESTART
;
1780 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1782 struct kvm_lapic
*apic
;
1784 ASSERT(vcpu
!= NULL
);
1785 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1787 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1791 vcpu
->arch
.apic
= apic
;
1793 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1795 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1797 goto nomem_free_apic
;
1801 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1803 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1806 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1807 * thinking that APIC satet has changed.
1809 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1810 kvm_lapic_set_base(vcpu
,
1811 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1813 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1814 kvm_lapic_reset(vcpu
, false);
1815 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1824 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1826 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1829 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1832 apic_update_ppr(apic
);
1833 highest_irr
= apic_find_highest_irr(apic
);
1834 if ((highest_irr
== -1) ||
1835 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1840 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1842 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1845 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1847 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1848 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1853 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1855 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1857 if (!kvm_vcpu_has_lapic(vcpu
))
1860 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1861 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1862 if (apic_lvtt_tscdeadline(apic
))
1863 apic
->lapic_timer
.tscdeadline
= 0;
1864 atomic_set(&apic
->lapic_timer
.pending
, 0);
1868 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1870 int vector
= kvm_apic_has_interrupt(vcpu
);
1871 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1877 * We get here even with APIC virtualization enabled, if doing
1878 * nested virtualization and L1 runs with the "acknowledge interrupt
1879 * on exit" mode. Then we cannot inject the interrupt via RVI,
1880 * because the process would deliver it through the IDT.
1883 apic_set_isr(vector
, apic
);
1884 apic_update_ppr(apic
);
1885 apic_clear_irr(vector
, apic
);
1887 if (test_bit(vector
, vcpu_to_synic(vcpu
)->auto_eoi_bitmap
)) {
1888 apic_clear_isr(vector
, apic
);
1889 apic_update_ppr(apic
);
1895 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1896 struct kvm_lapic_state
*s
)
1898 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1900 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1901 /* set SPIV separately to get count of SW disabled APICs right */
1902 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1903 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1904 /* call kvm_apic_set_id() to put apic into apic_map */
1905 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1906 kvm_apic_set_version(vcpu
);
1908 apic_update_ppr(apic
);
1909 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1910 apic_update_lvtt(apic
);
1911 apic_manage_nmi_watchdog(apic
, kvm_apic_get_reg(apic
, APIC_LVT0
));
1912 update_divide_count(apic
);
1913 start_apic_timer(apic
);
1914 apic
->irr_pending
= true;
1915 apic
->isr_count
= vcpu
->arch
.apicv_active
?
1916 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1917 apic
->highest_isr_cache
= -1;
1918 if (vcpu
->arch
.apicv_active
) {
1919 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1920 apic_find_highest_irr(apic
));
1921 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
1922 apic_find_highest_isr(apic
));
1924 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1925 if (ioapic_in_kernel(vcpu
->kvm
))
1926 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1928 vcpu
->arch
.apic_arb_prio
= 0;
1931 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1933 struct hrtimer
*timer
;
1935 if (!kvm_vcpu_has_lapic(vcpu
))
1938 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1939 if (hrtimer_cancel(timer
))
1940 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1944 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1946 * Detect whether guest triggered PV EOI since the
1947 * last entry. If yes, set EOI on guests's behalf.
1948 * Clear PV EOI in guest memory in any case.
1950 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1951 struct kvm_lapic
*apic
)
1956 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1957 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1959 * KVM_APIC_PV_EOI_PENDING is unset:
1960 * -> host disabled PV EOI.
1961 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1962 * -> host enabled PV EOI, guest did not execute EOI yet.
1963 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1964 * -> host enabled PV EOI, guest executed EOI.
1966 BUG_ON(!pv_eoi_enabled(vcpu
));
1967 pending
= pv_eoi_get_pending(vcpu
);
1969 * Clear pending bit in any case: it will be set again on vmentry.
1970 * While this might not be ideal from performance point of view,
1971 * this makes sure pv eoi is only enabled when we know it's safe.
1973 pv_eoi_clr_pending(vcpu
);
1976 vector
= apic_set_eoi(apic
);
1977 trace_kvm_pv_eoi(apic
, vector
);
1980 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1984 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1985 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1987 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1990 if (kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1994 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1998 * apic_sync_pv_eoi_to_guest - called before vmentry
2000 * Detect whether it's safe to enable PV EOI and
2003 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
2004 struct kvm_lapic
*apic
)
2006 if (!pv_eoi_enabled(vcpu
) ||
2007 /* IRR set or many bits in ISR: could be nested. */
2008 apic
->irr_pending
||
2009 /* Cache not set: could be safe but we don't bother. */
2010 apic
->highest_isr_cache
== -1 ||
2011 /* Need EOI to update ioapic. */
2012 kvm_ioapic_handles_vector(apic
, apic
->highest_isr_cache
)) {
2014 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2015 * so we need not do anything here.
2020 pv_eoi_set_pending(apic
->vcpu
);
2023 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
2026 int max_irr
, max_isr
;
2027 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2029 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
2031 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2034 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
2035 max_irr
= apic_find_highest_irr(apic
);
2038 max_isr
= apic_find_highest_isr(apic
);
2041 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
2043 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2047 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
2050 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
2051 &vcpu
->arch
.apic
->vapic_cache
,
2052 vapic_addr
, sizeof(u32
)))
2054 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2056 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2059 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
2063 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
2065 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2066 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
2068 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2071 if (reg
== APIC_ICR2
)
2074 /* if this is ICR write vector before command */
2075 if (reg
== APIC_ICR
)
2076 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2077 return apic_reg_write(apic
, reg
, (u32
)data
);
2080 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
2082 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2083 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
2085 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2088 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
2089 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2094 if (apic_reg_read(apic
, reg
, 4, &low
))
2096 if (reg
== APIC_ICR
)
2097 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2099 *data
= (((u64
)high
) << 32) | low
;
2104 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
2106 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2108 if (!kvm_vcpu_has_lapic(vcpu
))
2111 /* if this is ICR write vector before command */
2112 if (reg
== APIC_ICR
)
2113 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2114 return apic_reg_write(apic
, reg
, (u32
)data
);
2117 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2119 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2122 if (!kvm_vcpu_has_lapic(vcpu
))
2125 if (apic_reg_read(apic
, reg
, 4, &low
))
2127 if (reg
== APIC_ICR
)
2128 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2130 *data
= (((u64
)high
) << 32) | low
;
2135 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
2137 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2138 if (!IS_ALIGNED(addr
, 4))
2141 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2142 if (!pv_eoi_enabled(vcpu
))
2144 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2148 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2150 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2154 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
2158 * INITs are latched while in SMM. Because an SMM CPU cannot
2159 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2160 * and delay processing of INIT until the next RSM.
2163 WARN_ON_ONCE(vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
);
2164 if (test_bit(KVM_APIC_SIPI
, &apic
->pending_events
))
2165 clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
2169 pe
= xchg(&apic
->pending_events
, 0);
2170 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2171 kvm_lapic_reset(vcpu
, true);
2172 kvm_vcpu_reset(vcpu
, true);
2173 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2174 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2176 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2178 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2179 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2180 /* evaluate pending_events before reading the vector */
2182 sipi_vector
= apic
->sipi_vector
;
2183 apic_debug("vcpu %d received sipi with vector # %x\n",
2184 vcpu
->vcpu_id
, sipi_vector
);
2185 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2186 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2190 void kvm_lapic_init(void)
2192 /* do not patch jump label more than once per second */
2193 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2194 jump_label_rate_limit(&apic_sw_disabled
, HZ
);