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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / lapic.c
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/export.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
40 #include "irq.h"
41 #include "trace.h"
42 #include "x86.h"
43 #include "cpuid.h"
44 #include "hyperv.h"
45
46 #ifndef CONFIG_X86_64
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #else
49 #define mod_64(x, y) ((x) % (y))
50 #endif
51
52 #define PRId64 "d"
53 #define PRIx64 "llx"
54 #define PRIu64 "u"
55 #define PRIo64 "o"
56
57 #define APIC_BUS_CYCLE_NS 1
58
59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60 #define apic_debug(fmt, arg...)
61
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
71
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
74
75 static inline int apic_test_vector(int vec, void *bitmap)
76 {
77 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78 }
79
80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
81 {
82 struct kvm_lapic *apic = vcpu->arch.apic;
83
84 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
85 apic_test_vector(vector, apic->regs + APIC_IRR);
86 }
87
88 static inline void apic_clear_vector(int vec, void *bitmap)
89 {
90 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91 }
92
93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
94 {
95 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96 }
97
98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
99 {
100 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 }
102
103 struct static_key_deferred apic_hw_disabled __read_mostly;
104 struct static_key_deferred apic_sw_disabled __read_mostly;
105
106 static inline int apic_enabled(struct kvm_lapic *apic)
107 {
108 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
109 }
110
111 #define LVT_MASK \
112 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
113
114 #define LINT_MASK \
115 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
116 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
117
118 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
119 {
120 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
121 }
122
123 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
124 {
125 return apic->vcpu->vcpu_id;
126 }
127
128 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
129 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
130 switch (map->mode) {
131 case KVM_APIC_MODE_X2APIC: {
132 u32 offset = (dest_id >> 16) * 16;
133 u32 max_apic_id = map->max_apic_id;
134
135 if (offset <= max_apic_id) {
136 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
137
138 *cluster = &map->phys_map[offset];
139 *mask = dest_id & (0xffff >> (16 - cluster_size));
140 } else {
141 *mask = 0;
142 }
143
144 return true;
145 }
146 case KVM_APIC_MODE_XAPIC_FLAT:
147 *cluster = map->xapic_flat_map;
148 *mask = dest_id & 0xff;
149 return true;
150 case KVM_APIC_MODE_XAPIC_CLUSTER:
151 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
152 *mask = dest_id & 0xf;
153 return true;
154 default:
155 /* Not optimized. */
156 return false;
157 }
158 }
159
160 static void kvm_apic_map_free(struct rcu_head *rcu)
161 {
162 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
163
164 kvfree(map);
165 }
166
167 static void recalculate_apic_map(struct kvm *kvm)
168 {
169 struct kvm_apic_map *new, *old = NULL;
170 struct kvm_vcpu *vcpu;
171 int i;
172 u32 max_id = 255; /* enough space for any xAPIC ID */
173
174 mutex_lock(&kvm->arch.apic_map_lock);
175
176 kvm_for_each_vcpu(i, vcpu, kvm)
177 if (kvm_apic_present(vcpu))
178 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
179
180 new = kvm_kvzalloc(sizeof(struct kvm_apic_map) +
181 sizeof(struct kvm_lapic *) * ((u64)max_id + 1));
182
183 if (!new)
184 goto out;
185
186 new->max_apic_id = max_id;
187
188 kvm_for_each_vcpu(i, vcpu, kvm) {
189 struct kvm_lapic *apic = vcpu->arch.apic;
190 struct kvm_lapic **cluster;
191 u16 mask;
192 u32 ldr, aid;
193
194 if (!kvm_apic_present(vcpu))
195 continue;
196
197 aid = apic_x2apic_mode(apic) ? kvm_x2apic_id(apic)
198 : kvm_xapic_id(apic);
199 if (aid <= new->max_apic_id)
200 new->phys_map[aid] = apic;
201
202 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
203
204 if (apic_x2apic_mode(apic)) {
205 new->mode |= KVM_APIC_MODE_X2APIC;
206 } else if (ldr) {
207 ldr = GET_APIC_LOGICAL_ID(ldr);
208 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
209 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
210 else
211 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
212 }
213
214 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
215 continue;
216
217 if (mask)
218 cluster[ffs(mask) - 1] = apic;
219 }
220 out:
221 old = rcu_dereference_protected(kvm->arch.apic_map,
222 lockdep_is_held(&kvm->arch.apic_map_lock));
223 rcu_assign_pointer(kvm->arch.apic_map, new);
224 mutex_unlock(&kvm->arch.apic_map_lock);
225
226 if (old)
227 call_rcu(&old->rcu, kvm_apic_map_free);
228
229 kvm_make_scan_ioapic_request(kvm);
230 }
231
232 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
233 {
234 bool enabled = val & APIC_SPIV_APIC_ENABLED;
235
236 kvm_lapic_set_reg(apic, APIC_SPIV, val);
237
238 if (enabled != apic->sw_enabled) {
239 apic->sw_enabled = enabled;
240 if (enabled) {
241 static_key_slow_dec_deferred(&apic_sw_disabled);
242 recalculate_apic_map(apic->vcpu->kvm);
243 } else
244 static_key_slow_inc(&apic_sw_disabled.key);
245 }
246 }
247
248 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
249 {
250 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
251 recalculate_apic_map(apic->vcpu->kvm);
252 }
253
254 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
255 {
256 kvm_lapic_set_reg(apic, APIC_LDR, id);
257 recalculate_apic_map(apic->vcpu->kvm);
258 }
259
260 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
261 {
262 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
263
264 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
265
266 kvm_lapic_set_reg(apic, APIC_ID, id);
267 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
268 recalculate_apic_map(apic->vcpu->kvm);
269 }
270
271 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
272 {
273 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
274 }
275
276 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
277 {
278 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
279 }
280
281 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
282 {
283 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
284 }
285
286 static inline int apic_lvtt_period(struct kvm_lapic *apic)
287 {
288 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
289 }
290
291 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
292 {
293 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
294 }
295
296 static inline int apic_lvt_nmi_mode(u32 lvt_val)
297 {
298 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
299 }
300
301 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
302 {
303 struct kvm_lapic *apic = vcpu->arch.apic;
304 struct kvm_cpuid_entry2 *feat;
305 u32 v = APIC_VERSION;
306
307 if (!lapic_in_kernel(vcpu))
308 return;
309
310 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
311 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
312 v |= APIC_LVR_DIRECTED_EOI;
313 kvm_lapic_set_reg(apic, APIC_LVR, v);
314 }
315
316 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
317 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
318 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
319 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
320 LINT_MASK, LINT_MASK, /* LVT0-1 */
321 LVT_MASK /* LVTERR */
322 };
323
324 static int find_highest_vector(void *bitmap)
325 {
326 int vec;
327 u32 *reg;
328
329 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
330 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
331 reg = bitmap + REG_POS(vec);
332 if (*reg)
333 return fls(*reg) - 1 + vec;
334 }
335
336 return -1;
337 }
338
339 static u8 count_vectors(void *bitmap)
340 {
341 int vec;
342 u32 *reg;
343 u8 count = 0;
344
345 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
346 reg = bitmap + REG_POS(vec);
347 count += hweight32(*reg);
348 }
349
350 return count;
351 }
352
353 void __kvm_apic_update_irr(u32 *pir, void *regs)
354 {
355 u32 i, pir_val;
356
357 for (i = 0; i <= 7; i++) {
358 pir_val = READ_ONCE(pir[i]);
359 if (pir_val) {
360 pir_val = xchg(&pir[i], 0);
361 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
362 }
363 }
364 }
365 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
366
367 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
368 {
369 struct kvm_lapic *apic = vcpu->arch.apic;
370
371 __kvm_apic_update_irr(pir, apic->regs);
372
373 kvm_make_request(KVM_REQ_EVENT, vcpu);
374 }
375 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
376
377 static inline int apic_search_irr(struct kvm_lapic *apic)
378 {
379 return find_highest_vector(apic->regs + APIC_IRR);
380 }
381
382 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
383 {
384 int result;
385
386 /*
387 * Note that irr_pending is just a hint. It will be always
388 * true with virtual interrupt delivery enabled.
389 */
390 if (!apic->irr_pending)
391 return -1;
392
393 if (apic->vcpu->arch.apicv_active)
394 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
395 result = apic_search_irr(apic);
396 ASSERT(result == -1 || result >= 16);
397
398 return result;
399 }
400
401 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
402 {
403 struct kvm_vcpu *vcpu;
404
405 vcpu = apic->vcpu;
406
407 if (unlikely(vcpu->arch.apicv_active)) {
408 /* try to update RVI */
409 apic_clear_vector(vec, apic->regs + APIC_IRR);
410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411 } else {
412 apic->irr_pending = false;
413 apic_clear_vector(vec, apic->regs + APIC_IRR);
414 if (apic_search_irr(apic) != -1)
415 apic->irr_pending = true;
416 }
417 }
418
419 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
420 {
421 struct kvm_vcpu *vcpu;
422
423 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
424 return;
425
426 vcpu = apic->vcpu;
427
428 /*
429 * With APIC virtualization enabled, all caching is disabled
430 * because the processor can modify ISR under the hood. Instead
431 * just set SVI.
432 */
433 if (unlikely(vcpu->arch.apicv_active))
434 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
435 else {
436 ++apic->isr_count;
437 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
438 /*
439 * ISR (in service register) bit is set when injecting an interrupt.
440 * The highest vector is injected. Thus the latest bit set matches
441 * the highest bit in ISR.
442 */
443 apic->highest_isr_cache = vec;
444 }
445 }
446
447 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
448 {
449 int result;
450
451 /*
452 * Note that isr_count is always 1, and highest_isr_cache
453 * is always -1, with APIC virtualization enabled.
454 */
455 if (!apic->isr_count)
456 return -1;
457 if (likely(apic->highest_isr_cache != -1))
458 return apic->highest_isr_cache;
459
460 result = find_highest_vector(apic->regs + APIC_ISR);
461 ASSERT(result == -1 || result >= 16);
462
463 return result;
464 }
465
466 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
467 {
468 struct kvm_vcpu *vcpu;
469 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
470 return;
471
472 vcpu = apic->vcpu;
473
474 /*
475 * We do get here for APIC virtualization enabled if the guest
476 * uses the Hyper-V APIC enlightenment. In this case we may need
477 * to trigger a new interrupt delivery by writing the SVI field;
478 * on the other hand isr_count and highest_isr_cache are unused
479 * and must be left alone.
480 */
481 if (unlikely(vcpu->arch.apicv_active))
482 kvm_x86_ops->hwapic_isr_update(vcpu,
483 apic_find_highest_isr(apic));
484 else {
485 --apic->isr_count;
486 BUG_ON(apic->isr_count < 0);
487 apic->highest_isr_cache = -1;
488 }
489 }
490
491 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
492 {
493 /* This may race with setting of irr in __apic_accept_irq() and
494 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
495 * will cause vmexit immediately and the value will be recalculated
496 * on the next vmentry.
497 */
498 return apic_find_highest_irr(vcpu->arch.apic);
499 }
500
501 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
502 int vector, int level, int trig_mode,
503 struct dest_map *dest_map);
504
505 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
506 struct dest_map *dest_map)
507 {
508 struct kvm_lapic *apic = vcpu->arch.apic;
509
510 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
511 irq->level, irq->trig_mode, dest_map);
512 }
513
514 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
515 {
516
517 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
518 sizeof(val));
519 }
520
521 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
522 {
523
524 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
525 sizeof(*val));
526 }
527
528 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
529 {
530 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
531 }
532
533 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
534 {
535 u8 val;
536 if (pv_eoi_get_user(vcpu, &val) < 0)
537 apic_debug("Can't read EOI MSR value: 0x%llx\n",
538 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
539 return val & 0x1;
540 }
541
542 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
543 {
544 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
545 apic_debug("Can't set EOI MSR value: 0x%llx\n",
546 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
547 return;
548 }
549 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
550 }
551
552 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
553 {
554 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
555 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
556 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
557 return;
558 }
559 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
560 }
561
562 static void apic_update_ppr(struct kvm_lapic *apic)
563 {
564 u32 tpr, isrv, ppr, old_ppr;
565 int isr;
566
567 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
568 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
569 isr = apic_find_highest_isr(apic);
570 isrv = (isr != -1) ? isr : 0;
571
572 if ((tpr & 0xf0) >= (isrv & 0xf0))
573 ppr = tpr & 0xff;
574 else
575 ppr = isrv & 0xf0;
576
577 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
578 apic, ppr, isr, isrv);
579
580 if (old_ppr != ppr) {
581 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
582 if (ppr < old_ppr)
583 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
584 }
585 }
586
587 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
588 {
589 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
590 apic_update_ppr(apic);
591 }
592
593 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
594 {
595 if (apic_x2apic_mode(apic))
596 return mda == X2APIC_BROADCAST;
597
598 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
599 }
600
601 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
602 {
603 if (kvm_apic_broadcast(apic, mda))
604 return true;
605
606 if (apic_x2apic_mode(apic))
607 return mda == kvm_x2apic_id(apic);
608
609 return mda == SET_APIC_DEST_FIELD(kvm_xapic_id(apic));
610 }
611
612 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
613 {
614 u32 logical_id;
615
616 if (kvm_apic_broadcast(apic, mda))
617 return true;
618
619 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
620
621 if (apic_x2apic_mode(apic))
622 return ((logical_id >> 16) == (mda >> 16))
623 && (logical_id & mda & 0xffff) != 0;
624
625 logical_id = GET_APIC_LOGICAL_ID(logical_id);
626 mda = GET_APIC_DEST_FIELD(mda);
627
628 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
629 case APIC_DFR_FLAT:
630 return (logical_id & mda) != 0;
631 case APIC_DFR_CLUSTER:
632 return ((logical_id >> 4) == (mda >> 4))
633 && (logical_id & mda & 0xf) != 0;
634 default:
635 apic_debug("Bad DFR vcpu %d: %08x\n",
636 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
637 return false;
638 }
639 }
640
641 /* The KVM local APIC implementation has two quirks:
642 *
643 * - the xAPIC MDA stores the destination at bits 24-31, while this
644 * is not true of struct kvm_lapic_irq's dest_id field. This is
645 * just a quirk in the API and is not problematic.
646 *
647 * - in-kernel IOAPIC messages have to be delivered directly to
648 * x2APIC, because the kernel does not support interrupt remapping.
649 * In order to support broadcast without interrupt remapping, x2APIC
650 * rewrites the destination of non-IPI messages from APIC_BROADCAST
651 * to X2APIC_BROADCAST.
652 *
653 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
654 * important when userspace wants to use x2APIC-format MSIs, because
655 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
656 */
657 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
658 struct kvm_lapic *source, struct kvm_lapic *target)
659 {
660 bool ipi = source != NULL;
661 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
662
663 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
664 !ipi && dest_id == APIC_BROADCAST && x2apic_mda)
665 return X2APIC_BROADCAST;
666
667 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
668 }
669
670 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
671 int short_hand, unsigned int dest, int dest_mode)
672 {
673 struct kvm_lapic *target = vcpu->arch.apic;
674 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
675
676 apic_debug("target %p, source %p, dest 0x%x, "
677 "dest_mode 0x%x, short_hand 0x%x\n",
678 target, source, dest, dest_mode, short_hand);
679
680 ASSERT(target);
681 switch (short_hand) {
682 case APIC_DEST_NOSHORT:
683 if (dest_mode == APIC_DEST_PHYSICAL)
684 return kvm_apic_match_physical_addr(target, mda);
685 else
686 return kvm_apic_match_logical_addr(target, mda);
687 case APIC_DEST_SELF:
688 return target == source;
689 case APIC_DEST_ALLINC:
690 return true;
691 case APIC_DEST_ALLBUT:
692 return target != source;
693 default:
694 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
695 short_hand);
696 return false;
697 }
698 }
699 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
700
701 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
702 const unsigned long *bitmap, u32 bitmap_size)
703 {
704 u32 mod;
705 int i, idx = -1;
706
707 mod = vector % dest_vcpus;
708
709 for (i = 0; i <= mod; i++) {
710 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
711 BUG_ON(idx == bitmap_size);
712 }
713
714 return idx;
715 }
716
717 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
718 {
719 if (!kvm->arch.disabled_lapic_found) {
720 kvm->arch.disabled_lapic_found = true;
721 printk(KERN_INFO
722 "Disabled LAPIC found during irq injection\n");
723 }
724 }
725
726 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
727 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
728 {
729 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
730 if ((irq->dest_id == APIC_BROADCAST &&
731 map->mode != KVM_APIC_MODE_X2APIC))
732 return true;
733 if (irq->dest_id == X2APIC_BROADCAST)
734 return true;
735 } else {
736 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
737 if (irq->dest_id == (x2apic_ipi ?
738 X2APIC_BROADCAST : APIC_BROADCAST))
739 return true;
740 }
741
742 return false;
743 }
744
745 /* Return true if the interrupt can be handled by using *bitmap as index mask
746 * for valid destinations in *dst array.
747 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
748 * Note: we may have zero kvm_lapic destinations when we return true, which
749 * means that the interrupt should be dropped. In this case, *bitmap would be
750 * zero and *dst undefined.
751 */
752 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
753 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
754 struct kvm_apic_map *map, struct kvm_lapic ***dst,
755 unsigned long *bitmap)
756 {
757 int i, lowest;
758
759 if (irq->shorthand == APIC_DEST_SELF && src) {
760 *dst = src;
761 *bitmap = 1;
762 return true;
763 } else if (irq->shorthand)
764 return false;
765
766 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
767 return false;
768
769 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
770 if (irq->dest_id > map->max_apic_id) {
771 *bitmap = 0;
772 } else {
773 *dst = &map->phys_map[irq->dest_id];
774 *bitmap = 1;
775 }
776 return true;
777 }
778
779 *bitmap = 0;
780 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
781 (u16 *)bitmap))
782 return false;
783
784 if (!kvm_lowest_prio_delivery(irq))
785 return true;
786
787 if (!kvm_vector_hashing_enabled()) {
788 lowest = -1;
789 for_each_set_bit(i, bitmap, 16) {
790 if (!(*dst)[i])
791 continue;
792 if (lowest < 0)
793 lowest = i;
794 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
795 (*dst)[lowest]->vcpu) < 0)
796 lowest = i;
797 }
798 } else {
799 if (!*bitmap)
800 return true;
801
802 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
803 bitmap, 16);
804
805 if (!(*dst)[lowest]) {
806 kvm_apic_disabled_lapic_found(kvm);
807 *bitmap = 0;
808 return true;
809 }
810 }
811
812 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
813
814 return true;
815 }
816
817 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
818 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
819 {
820 struct kvm_apic_map *map;
821 unsigned long bitmap;
822 struct kvm_lapic **dst = NULL;
823 int i;
824 bool ret;
825
826 *r = -1;
827
828 if (irq->shorthand == APIC_DEST_SELF) {
829 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
830 return true;
831 }
832
833 rcu_read_lock();
834 map = rcu_dereference(kvm->arch.apic_map);
835
836 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
837 if (ret)
838 for_each_set_bit(i, &bitmap, 16) {
839 if (!dst[i])
840 continue;
841 if (*r < 0)
842 *r = 0;
843 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
844 }
845
846 rcu_read_unlock();
847 return ret;
848 }
849
850 /*
851 * This routine tries to handler interrupts in posted mode, here is how
852 * it deals with different cases:
853 * - For single-destination interrupts, handle it in posted mode
854 * - Else if vector hashing is enabled and it is a lowest-priority
855 * interrupt, handle it in posted mode and use the following mechanism
856 * to find the destinaiton vCPU.
857 * 1. For lowest-priority interrupts, store all the possible
858 * destination vCPUs in an array.
859 * 2. Use "guest vector % max number of destination vCPUs" to find
860 * the right destination vCPU in the array for the lowest-priority
861 * interrupt.
862 * - Otherwise, use remapped mode to inject the interrupt.
863 */
864 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
865 struct kvm_vcpu **dest_vcpu)
866 {
867 struct kvm_apic_map *map;
868 unsigned long bitmap;
869 struct kvm_lapic **dst = NULL;
870 bool ret = false;
871
872 if (irq->shorthand)
873 return false;
874
875 rcu_read_lock();
876 map = rcu_dereference(kvm->arch.apic_map);
877
878 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
879 hweight16(bitmap) == 1) {
880 unsigned long i = find_first_bit(&bitmap, 16);
881
882 if (dst[i]) {
883 *dest_vcpu = dst[i]->vcpu;
884 ret = true;
885 }
886 }
887
888 rcu_read_unlock();
889 return ret;
890 }
891
892 /*
893 * Add a pending IRQ into lapic.
894 * Return 1 if successfully added and 0 if discarded.
895 */
896 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
897 int vector, int level, int trig_mode,
898 struct dest_map *dest_map)
899 {
900 int result = 0;
901 struct kvm_vcpu *vcpu = apic->vcpu;
902
903 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
904 trig_mode, vector);
905 switch (delivery_mode) {
906 case APIC_DM_LOWEST:
907 vcpu->arch.apic_arb_prio++;
908 case APIC_DM_FIXED:
909 if (unlikely(trig_mode && !level))
910 break;
911
912 /* FIXME add logic for vcpu on reset */
913 if (unlikely(!apic_enabled(apic)))
914 break;
915
916 result = 1;
917
918 if (dest_map) {
919 __set_bit(vcpu->vcpu_id, dest_map->map);
920 dest_map->vectors[vcpu->vcpu_id] = vector;
921 }
922
923 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
924 if (trig_mode)
925 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
926 else
927 apic_clear_vector(vector, apic->regs + APIC_TMR);
928 }
929
930 if (vcpu->arch.apicv_active)
931 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
932 else {
933 kvm_lapic_set_irr(vector, apic);
934
935 kvm_make_request(KVM_REQ_EVENT, vcpu);
936 kvm_vcpu_kick(vcpu);
937 }
938 break;
939
940 case APIC_DM_REMRD:
941 result = 1;
942 vcpu->arch.pv.pv_unhalted = 1;
943 kvm_make_request(KVM_REQ_EVENT, vcpu);
944 kvm_vcpu_kick(vcpu);
945 break;
946
947 case APIC_DM_SMI:
948 result = 1;
949 kvm_make_request(KVM_REQ_SMI, vcpu);
950 kvm_vcpu_kick(vcpu);
951 break;
952
953 case APIC_DM_NMI:
954 result = 1;
955 kvm_inject_nmi(vcpu);
956 kvm_vcpu_kick(vcpu);
957 break;
958
959 case APIC_DM_INIT:
960 if (!trig_mode || level) {
961 result = 1;
962 /* assumes that there are only KVM_APIC_INIT/SIPI */
963 apic->pending_events = (1UL << KVM_APIC_INIT);
964 /* make sure pending_events is visible before sending
965 * the request */
966 smp_wmb();
967 kvm_make_request(KVM_REQ_EVENT, vcpu);
968 kvm_vcpu_kick(vcpu);
969 } else {
970 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
971 vcpu->vcpu_id);
972 }
973 break;
974
975 case APIC_DM_STARTUP:
976 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
977 vcpu->vcpu_id, vector);
978 result = 1;
979 apic->sipi_vector = vector;
980 /* make sure sipi_vector is visible for the receiver */
981 smp_wmb();
982 set_bit(KVM_APIC_SIPI, &apic->pending_events);
983 kvm_make_request(KVM_REQ_EVENT, vcpu);
984 kvm_vcpu_kick(vcpu);
985 break;
986
987 case APIC_DM_EXTINT:
988 /*
989 * Should only be called by kvm_apic_local_deliver() with LVT0,
990 * before NMI watchdog was enabled. Already handled by
991 * kvm_apic_accept_pic_intr().
992 */
993 break;
994
995 default:
996 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
997 delivery_mode);
998 break;
999 }
1000 return result;
1001 }
1002
1003 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1004 {
1005 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1006 }
1007
1008 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1009 {
1010 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1011 }
1012
1013 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1014 {
1015 int trigger_mode;
1016
1017 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1018 if (!kvm_ioapic_handles_vector(apic, vector))
1019 return;
1020
1021 /* Request a KVM exit to inform the userspace IOAPIC. */
1022 if (irqchip_split(apic->vcpu->kvm)) {
1023 apic->vcpu->arch.pending_ioapic_eoi = vector;
1024 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1025 return;
1026 }
1027
1028 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1029 trigger_mode = IOAPIC_LEVEL_TRIG;
1030 else
1031 trigger_mode = IOAPIC_EDGE_TRIG;
1032
1033 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1034 }
1035
1036 static int apic_set_eoi(struct kvm_lapic *apic)
1037 {
1038 int vector = apic_find_highest_isr(apic);
1039
1040 trace_kvm_eoi(apic, vector);
1041
1042 /*
1043 * Not every write EOI will has corresponding ISR,
1044 * one example is when Kernel check timer on setup_IO_APIC
1045 */
1046 if (vector == -1)
1047 return vector;
1048
1049 apic_clear_isr(vector, apic);
1050 apic_update_ppr(apic);
1051
1052 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1053 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1054
1055 kvm_ioapic_send_eoi(apic, vector);
1056 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1057 return vector;
1058 }
1059
1060 /*
1061 * this interface assumes a trap-like exit, which has already finished
1062 * desired side effect including vISR and vPPR update.
1063 */
1064 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1065 {
1066 struct kvm_lapic *apic = vcpu->arch.apic;
1067
1068 trace_kvm_eoi(apic, vector);
1069
1070 kvm_ioapic_send_eoi(apic, vector);
1071 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1072 }
1073 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1074
1075 static void apic_send_ipi(struct kvm_lapic *apic)
1076 {
1077 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1078 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1079 struct kvm_lapic_irq irq;
1080
1081 irq.vector = icr_low & APIC_VECTOR_MASK;
1082 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1083 irq.dest_mode = icr_low & APIC_DEST_MASK;
1084 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1085 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1086 irq.shorthand = icr_low & APIC_SHORT_MASK;
1087 irq.msi_redir_hint = false;
1088 if (apic_x2apic_mode(apic))
1089 irq.dest_id = icr_high;
1090 else
1091 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1092
1093 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1094
1095 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1096 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1097 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1098 "msi_redir_hint 0x%x\n",
1099 icr_high, icr_low, irq.shorthand, irq.dest_id,
1100 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1101 irq.vector, irq.msi_redir_hint);
1102
1103 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1104 }
1105
1106 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1107 {
1108 ktime_t remaining, now;
1109 s64 ns;
1110 u32 tmcct;
1111
1112 ASSERT(apic != NULL);
1113
1114 /* if initial count is 0, current count should also be 0 */
1115 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1116 apic->lapic_timer.period == 0)
1117 return 0;
1118
1119 now = ktime_get();
1120 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1121 if (ktime_to_ns(remaining) < 0)
1122 remaining = 0;
1123
1124 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1125 tmcct = div64_u64(ns,
1126 (APIC_BUS_CYCLE_NS * apic->divide_count));
1127
1128 return tmcct;
1129 }
1130
1131 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1132 {
1133 struct kvm_vcpu *vcpu = apic->vcpu;
1134 struct kvm_run *run = vcpu->run;
1135
1136 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1137 run->tpr_access.rip = kvm_rip_read(vcpu);
1138 run->tpr_access.is_write = write;
1139 }
1140
1141 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1142 {
1143 if (apic->vcpu->arch.tpr_access_reporting)
1144 __report_tpr_access(apic, write);
1145 }
1146
1147 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1148 {
1149 u32 val = 0;
1150
1151 if (offset >= LAPIC_MMIO_LENGTH)
1152 return 0;
1153
1154 switch (offset) {
1155 case APIC_ARBPRI:
1156 apic_debug("Access APIC ARBPRI register which is for P6\n");
1157 break;
1158
1159 case APIC_TMCCT: /* Timer CCR */
1160 if (apic_lvtt_tscdeadline(apic))
1161 return 0;
1162
1163 val = apic_get_tmcct(apic);
1164 break;
1165 case APIC_PROCPRI:
1166 apic_update_ppr(apic);
1167 val = kvm_lapic_get_reg(apic, offset);
1168 break;
1169 case APIC_TASKPRI:
1170 report_tpr_access(apic, false);
1171 /* fall thru */
1172 default:
1173 val = kvm_lapic_get_reg(apic, offset);
1174 break;
1175 }
1176
1177 return val;
1178 }
1179
1180 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1181 {
1182 return container_of(dev, struct kvm_lapic, dev);
1183 }
1184
1185 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1186 void *data)
1187 {
1188 unsigned char alignment = offset & 0xf;
1189 u32 result;
1190 /* this bitmask has a bit cleared for each reserved register */
1191 static const u64 rmask = 0x43ff01ffffffe70cULL;
1192
1193 if ((alignment + len) > 4) {
1194 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1195 offset, len);
1196 return 1;
1197 }
1198
1199 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1200 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1201 offset);
1202 return 1;
1203 }
1204
1205 result = __apic_read(apic, offset & ~0xf);
1206
1207 trace_kvm_apic_read(offset, result);
1208
1209 switch (len) {
1210 case 1:
1211 case 2:
1212 case 4:
1213 memcpy(data, (char *)&result + alignment, len);
1214 break;
1215 default:
1216 printk(KERN_ERR "Local APIC read with len = %x, "
1217 "should be 1,2, or 4 instead\n", len);
1218 break;
1219 }
1220 return 0;
1221 }
1222 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1223
1224 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1225 {
1226 return kvm_apic_hw_enabled(apic) &&
1227 addr >= apic->base_address &&
1228 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1229 }
1230
1231 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1232 gpa_t address, int len, void *data)
1233 {
1234 struct kvm_lapic *apic = to_lapic(this);
1235 u32 offset = address - apic->base_address;
1236
1237 if (!apic_mmio_in_range(apic, address))
1238 return -EOPNOTSUPP;
1239
1240 kvm_lapic_reg_read(apic, offset, len, data);
1241
1242 return 0;
1243 }
1244
1245 static void update_divide_count(struct kvm_lapic *apic)
1246 {
1247 u32 tmp1, tmp2, tdcr;
1248
1249 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1250 tmp1 = tdcr & 0xf;
1251 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1252 apic->divide_count = 0x1 << (tmp2 & 0x7);
1253
1254 apic_debug("timer divide count is 0x%x\n",
1255 apic->divide_count);
1256 }
1257
1258 static void apic_update_lvtt(struct kvm_lapic *apic)
1259 {
1260 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1261 apic->lapic_timer.timer_mode_mask;
1262
1263 if (apic->lapic_timer.timer_mode != timer_mode) {
1264 apic->lapic_timer.timer_mode = timer_mode;
1265 hrtimer_cancel(&apic->lapic_timer.timer);
1266 }
1267 }
1268
1269 static void apic_timer_expired(struct kvm_lapic *apic)
1270 {
1271 struct kvm_vcpu *vcpu = apic->vcpu;
1272 struct swait_queue_head *q = &vcpu->wq;
1273 struct kvm_timer *ktimer = &apic->lapic_timer;
1274
1275 if (atomic_read(&apic->lapic_timer.pending))
1276 return;
1277
1278 atomic_inc(&apic->lapic_timer.pending);
1279 kvm_set_pending_timer(vcpu);
1280
1281 if (swait_active(q))
1282 swake_up(q);
1283
1284 if (apic_lvtt_tscdeadline(apic))
1285 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1286 }
1287
1288 /*
1289 * On APICv, this test will cause a busy wait
1290 * during a higher-priority task.
1291 */
1292
1293 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1294 {
1295 struct kvm_lapic *apic = vcpu->arch.apic;
1296 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1297
1298 if (kvm_apic_hw_enabled(apic)) {
1299 int vec = reg & APIC_VECTOR_MASK;
1300 void *bitmap = apic->regs + APIC_ISR;
1301
1302 if (vcpu->arch.apicv_active)
1303 bitmap = apic->regs + APIC_IRR;
1304
1305 if (apic_test_vector(vec, bitmap))
1306 return true;
1307 }
1308 return false;
1309 }
1310
1311 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1312 {
1313 struct kvm_lapic *apic = vcpu->arch.apic;
1314 u64 guest_tsc, tsc_deadline;
1315
1316 if (!lapic_in_kernel(vcpu))
1317 return;
1318
1319 if (apic->lapic_timer.expired_tscdeadline == 0)
1320 return;
1321
1322 if (!lapic_timer_int_injected(vcpu))
1323 return;
1324
1325 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1326 apic->lapic_timer.expired_tscdeadline = 0;
1327 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1328 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1329
1330 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1331 if (guest_tsc < tsc_deadline)
1332 __delay(min(tsc_deadline - guest_tsc,
1333 nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1334 }
1335
1336 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1337 {
1338 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1339 u64 ns = 0;
1340 ktime_t expire;
1341 struct kvm_vcpu *vcpu = apic->vcpu;
1342 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1343 unsigned long flags;
1344 ktime_t now;
1345
1346 if (unlikely(!tscdeadline || !this_tsc_khz))
1347 return;
1348
1349 local_irq_save(flags);
1350
1351 now = ktime_get();
1352 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1353 if (likely(tscdeadline > guest_tsc)) {
1354 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1355 do_div(ns, this_tsc_khz);
1356 expire = ktime_add_ns(now, ns);
1357 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1358 hrtimer_start(&apic->lapic_timer.timer,
1359 expire, HRTIMER_MODE_ABS_PINNED);
1360 } else
1361 apic_timer_expired(apic);
1362
1363 local_irq_restore(flags);
1364 }
1365
1366 static void start_sw_period(struct kvm_lapic *apic)
1367 {
1368 if (!apic->lapic_timer.period)
1369 return;
1370
1371 if (apic_lvtt_oneshot(apic) &&
1372 ktime_after(ktime_get(),
1373 apic->lapic_timer.target_expiration)) {
1374 apic_timer_expired(apic);
1375 return;
1376 }
1377
1378 hrtimer_start(&apic->lapic_timer.timer,
1379 apic->lapic_timer.target_expiration,
1380 HRTIMER_MODE_ABS_PINNED);
1381 }
1382
1383 static bool set_target_expiration(struct kvm_lapic *apic)
1384 {
1385 ktime_t now;
1386 u64 tscl = rdtsc();
1387
1388 now = ktime_get();
1389 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1390 * APIC_BUS_CYCLE_NS * apic->divide_count;
1391
1392 if (!apic->lapic_timer.period)
1393 return false;
1394
1395 /*
1396 * Do not allow the guest to program periodic timers with small
1397 * interval, since the hrtimers are not throttled by the host
1398 * scheduler.
1399 */
1400 if (apic_lvtt_period(apic)) {
1401 s64 min_period = min_timer_period_us * 1000LL;
1402
1403 if (apic->lapic_timer.period < min_period) {
1404 pr_info_ratelimited(
1405 "kvm: vcpu %i: requested %lld ns "
1406 "lapic timer period limited to %lld ns\n",
1407 apic->vcpu->vcpu_id,
1408 apic->lapic_timer.period, min_period);
1409 apic->lapic_timer.period = min_period;
1410 }
1411 }
1412
1413 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1414 PRIx64 ", "
1415 "timer initial count 0x%x, period %lldns, "
1416 "expire @ 0x%016" PRIx64 ".\n", __func__,
1417 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1418 kvm_lapic_get_reg(apic, APIC_TMICT),
1419 apic->lapic_timer.period,
1420 ktime_to_ns(ktime_add_ns(now,
1421 apic->lapic_timer.period)));
1422
1423 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1424 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1425 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1426
1427 return true;
1428 }
1429
1430 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1431 {
1432 apic->lapic_timer.tscdeadline +=
1433 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1434 apic->lapic_timer.target_expiration =
1435 ktime_add_ns(apic->lapic_timer.target_expiration,
1436 apic->lapic_timer.period);
1437 }
1438
1439 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1440 {
1441 if (!lapic_in_kernel(vcpu))
1442 return false;
1443
1444 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1445 }
1446 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1447
1448 static void cancel_hv_timer(struct kvm_lapic *apic)
1449 {
1450 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1451 apic->lapic_timer.hv_timer_in_use = false;
1452 }
1453
1454 static bool start_hv_timer(struct kvm_lapic *apic)
1455 {
1456 u64 tscdeadline = apic->lapic_timer.tscdeadline;
1457
1458 if ((atomic_read(&apic->lapic_timer.pending) &&
1459 !apic_lvtt_period(apic)) ||
1460 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1461 if (apic->lapic_timer.hv_timer_in_use)
1462 cancel_hv_timer(apic);
1463 } else {
1464 apic->lapic_timer.hv_timer_in_use = true;
1465 hrtimer_cancel(&apic->lapic_timer.timer);
1466
1467 /* In case the sw timer triggered in the window */
1468 if (atomic_read(&apic->lapic_timer.pending) &&
1469 !apic_lvtt_period(apic))
1470 cancel_hv_timer(apic);
1471 }
1472 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1473 apic->lapic_timer.hv_timer_in_use);
1474 return apic->lapic_timer.hv_timer_in_use;
1475 }
1476
1477 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1478 {
1479 struct kvm_lapic *apic = vcpu->arch.apic;
1480
1481 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1482 WARN_ON(swait_active(&vcpu->wq));
1483 cancel_hv_timer(apic);
1484 apic_timer_expired(apic);
1485
1486 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1487 advance_periodic_target_expiration(apic);
1488 if (!start_hv_timer(apic))
1489 start_sw_period(apic);
1490 }
1491 }
1492 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1493
1494 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1495 {
1496 struct kvm_lapic *apic = vcpu->arch.apic;
1497
1498 WARN_ON(apic->lapic_timer.hv_timer_in_use);
1499
1500 start_hv_timer(apic);
1501 }
1502 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1503
1504 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1505 {
1506 struct kvm_lapic *apic = vcpu->arch.apic;
1507
1508 /* Possibly the TSC deadline timer is not enabled yet */
1509 if (!apic->lapic_timer.hv_timer_in_use)
1510 return;
1511
1512 cancel_hv_timer(apic);
1513
1514 if (atomic_read(&apic->lapic_timer.pending))
1515 return;
1516
1517 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1518 start_sw_period(apic);
1519 else if (apic_lvtt_tscdeadline(apic))
1520 start_sw_tscdeadline(apic);
1521 }
1522 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1523
1524 static void start_apic_timer(struct kvm_lapic *apic)
1525 {
1526 atomic_set(&apic->lapic_timer.pending, 0);
1527
1528 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1529 if (set_target_expiration(apic) &&
1530 !(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1531 start_sw_period(apic);
1532 } else if (apic_lvtt_tscdeadline(apic)) {
1533 if (!(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1534 start_sw_tscdeadline(apic);
1535 }
1536 }
1537
1538 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1539 {
1540 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1541
1542 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1543 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1544 if (lvt0_in_nmi_mode) {
1545 apic_debug("Receive NMI setting on APIC_LVT0 "
1546 "for cpu %d\n", apic->vcpu->vcpu_id);
1547 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1548 } else
1549 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1550 }
1551 }
1552
1553 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1554 {
1555 int ret = 0;
1556
1557 trace_kvm_apic_write(reg, val);
1558
1559 switch (reg) {
1560 case APIC_ID: /* Local APIC ID */
1561 if (!apic_x2apic_mode(apic))
1562 kvm_apic_set_xapic_id(apic, val >> 24);
1563 else
1564 ret = 1;
1565 break;
1566
1567 case APIC_TASKPRI:
1568 report_tpr_access(apic, true);
1569 apic_set_tpr(apic, val & 0xff);
1570 break;
1571
1572 case APIC_EOI:
1573 apic_set_eoi(apic);
1574 break;
1575
1576 case APIC_LDR:
1577 if (!apic_x2apic_mode(apic))
1578 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1579 else
1580 ret = 1;
1581 break;
1582
1583 case APIC_DFR:
1584 if (!apic_x2apic_mode(apic)) {
1585 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1586 recalculate_apic_map(apic->vcpu->kvm);
1587 } else
1588 ret = 1;
1589 break;
1590
1591 case APIC_SPIV: {
1592 u32 mask = 0x3ff;
1593 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1594 mask |= APIC_SPIV_DIRECTED_EOI;
1595 apic_set_spiv(apic, val & mask);
1596 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1597 int i;
1598 u32 lvt_val;
1599
1600 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1601 lvt_val = kvm_lapic_get_reg(apic,
1602 APIC_LVTT + 0x10 * i);
1603 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1604 lvt_val | APIC_LVT_MASKED);
1605 }
1606 apic_update_lvtt(apic);
1607 atomic_set(&apic->lapic_timer.pending, 0);
1608
1609 }
1610 break;
1611 }
1612 case APIC_ICR:
1613 /* No delay here, so we always clear the pending bit */
1614 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1615 apic_send_ipi(apic);
1616 break;
1617
1618 case APIC_ICR2:
1619 if (!apic_x2apic_mode(apic))
1620 val &= 0xff000000;
1621 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1622 break;
1623
1624 case APIC_LVT0:
1625 apic_manage_nmi_watchdog(apic, val);
1626 case APIC_LVTTHMR:
1627 case APIC_LVTPC:
1628 case APIC_LVT1:
1629 case APIC_LVTERR:
1630 /* TODO: Check vector */
1631 if (!kvm_apic_sw_enabled(apic))
1632 val |= APIC_LVT_MASKED;
1633
1634 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1635 kvm_lapic_set_reg(apic, reg, val);
1636
1637 break;
1638
1639 case APIC_LVTT:
1640 if (!kvm_apic_sw_enabled(apic))
1641 val |= APIC_LVT_MASKED;
1642 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1643 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1644 apic_update_lvtt(apic);
1645 break;
1646
1647 case APIC_TMICT:
1648 if (apic_lvtt_tscdeadline(apic))
1649 break;
1650
1651 hrtimer_cancel(&apic->lapic_timer.timer);
1652 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1653 start_apic_timer(apic);
1654 break;
1655
1656 case APIC_TDCR:
1657 if (val & 4)
1658 apic_debug("KVM_WRITE:TDCR %x\n", val);
1659 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1660 update_divide_count(apic);
1661 break;
1662
1663 case APIC_ESR:
1664 if (apic_x2apic_mode(apic) && val != 0) {
1665 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1666 ret = 1;
1667 }
1668 break;
1669
1670 case APIC_SELF_IPI:
1671 if (apic_x2apic_mode(apic)) {
1672 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1673 } else
1674 ret = 1;
1675 break;
1676 default:
1677 ret = 1;
1678 break;
1679 }
1680 if (ret)
1681 apic_debug("Local APIC Write to read-only register %x\n", reg);
1682 return ret;
1683 }
1684 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1685
1686 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1687 gpa_t address, int len, const void *data)
1688 {
1689 struct kvm_lapic *apic = to_lapic(this);
1690 unsigned int offset = address - apic->base_address;
1691 u32 val;
1692
1693 if (!apic_mmio_in_range(apic, address))
1694 return -EOPNOTSUPP;
1695
1696 /*
1697 * APIC register must be aligned on 128-bits boundary.
1698 * 32/64/128 bits registers must be accessed thru 32 bits.
1699 * Refer SDM 8.4.1
1700 */
1701 if (len != 4 || (offset & 0xf)) {
1702 /* Don't shout loud, $infamous_os would cause only noise. */
1703 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1704 return 0;
1705 }
1706
1707 val = *(u32*)data;
1708
1709 /* too common printing */
1710 if (offset != APIC_EOI)
1711 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1712 "0x%x\n", __func__, offset, len, val);
1713
1714 kvm_lapic_reg_write(apic, offset & 0xff0, val);
1715
1716 return 0;
1717 }
1718
1719 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1720 {
1721 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1722 }
1723 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1724
1725 /* emulate APIC access in a trap manner */
1726 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1727 {
1728 u32 val = 0;
1729
1730 /* hw has done the conditional check and inst decode */
1731 offset &= 0xff0;
1732
1733 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1734
1735 /* TODO: optimize to just emulate side effect w/o one more write */
1736 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1737 }
1738 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1739
1740 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1741 {
1742 struct kvm_lapic *apic = vcpu->arch.apic;
1743
1744 if (!vcpu->arch.apic)
1745 return;
1746
1747 hrtimer_cancel(&apic->lapic_timer.timer);
1748
1749 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1750 static_key_slow_dec_deferred(&apic_hw_disabled);
1751
1752 if (!apic->sw_enabled)
1753 static_key_slow_dec_deferred(&apic_sw_disabled);
1754
1755 if (apic->regs)
1756 free_page((unsigned long)apic->regs);
1757
1758 kfree(apic);
1759 }
1760
1761 /*
1762 *----------------------------------------------------------------------
1763 * LAPIC interface
1764 *----------------------------------------------------------------------
1765 */
1766 u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu)
1767 {
1768 struct kvm_lapic *apic = vcpu->arch.apic;
1769
1770 if (!lapic_in_kernel(vcpu))
1771 return 0;
1772
1773 return apic->lapic_timer.tscdeadline;
1774 }
1775
1776 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1777 {
1778 struct kvm_lapic *apic = vcpu->arch.apic;
1779
1780 if (!lapic_in_kernel(vcpu) ||
1781 !apic_lvtt_tscdeadline(apic))
1782 return 0;
1783
1784 return apic->lapic_timer.tscdeadline;
1785 }
1786
1787 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1788 {
1789 struct kvm_lapic *apic = vcpu->arch.apic;
1790
1791 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1792 apic_lvtt_period(apic))
1793 return;
1794
1795 hrtimer_cancel(&apic->lapic_timer.timer);
1796 apic->lapic_timer.tscdeadline = data;
1797 start_apic_timer(apic);
1798 }
1799
1800 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1801 {
1802 struct kvm_lapic *apic = vcpu->arch.apic;
1803
1804 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1805 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1806 }
1807
1808 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1809 {
1810 u64 tpr;
1811
1812 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1813
1814 return (tpr & 0xf0) >> 4;
1815 }
1816
1817 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1818 {
1819 u64 old_value = vcpu->arch.apic_base;
1820 struct kvm_lapic *apic = vcpu->arch.apic;
1821
1822 if (!apic)
1823 value |= MSR_IA32_APICBASE_BSP;
1824
1825 vcpu->arch.apic_base = value;
1826
1827 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1828 kvm_update_cpuid(vcpu);
1829
1830 if (!apic)
1831 return;
1832
1833 /* update jump label if enable bit changes */
1834 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1835 if (value & MSR_IA32_APICBASE_ENABLE) {
1836 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1837 static_key_slow_dec_deferred(&apic_hw_disabled);
1838 } else {
1839 static_key_slow_inc(&apic_hw_disabled.key);
1840 recalculate_apic_map(vcpu->kvm);
1841 }
1842 }
1843
1844 if ((old_value ^ value) & X2APIC_ENABLE) {
1845 if (value & X2APIC_ENABLE) {
1846 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1847 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1848 } else
1849 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1850 }
1851
1852 apic->base_address = apic->vcpu->arch.apic_base &
1853 MSR_IA32_APICBASE_BASE;
1854
1855 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1856 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1857 pr_warn_once("APIC base relocation is unsupported by KVM");
1858
1859 /* with FSB delivery interrupt, we can restart APIC functionality */
1860 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1861 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1862
1863 }
1864
1865 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1866 {
1867 struct kvm_lapic *apic;
1868 int i;
1869
1870 apic_debug("%s\n", __func__);
1871
1872 ASSERT(vcpu);
1873 apic = vcpu->arch.apic;
1874 ASSERT(apic != NULL);
1875
1876 /* Stop the timer in case it's a reset to an active apic */
1877 hrtimer_cancel(&apic->lapic_timer.timer);
1878
1879 if (!init_event) {
1880 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1881 MSR_IA32_APICBASE_ENABLE);
1882 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1883 }
1884 kvm_apic_set_version(apic->vcpu);
1885
1886 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1887 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1888 apic_update_lvtt(apic);
1889 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1890 kvm_lapic_set_reg(apic, APIC_LVT0,
1891 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1892 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1893
1894 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1895 apic_set_spiv(apic, 0xff);
1896 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1897 if (!apic_x2apic_mode(apic))
1898 kvm_apic_set_ldr(apic, 0);
1899 kvm_lapic_set_reg(apic, APIC_ESR, 0);
1900 kvm_lapic_set_reg(apic, APIC_ICR, 0);
1901 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1902 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1903 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1904 for (i = 0; i < 8; i++) {
1905 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1906 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1907 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1908 }
1909 apic->irr_pending = vcpu->arch.apicv_active;
1910 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1911 apic->highest_isr_cache = -1;
1912 update_divide_count(apic);
1913 atomic_set(&apic->lapic_timer.pending, 0);
1914 if (kvm_vcpu_is_bsp(vcpu))
1915 kvm_lapic_set_base(vcpu,
1916 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1917 vcpu->arch.pv_eoi.msr_val = 0;
1918 apic_update_ppr(apic);
1919
1920 vcpu->arch.apic_arb_prio = 0;
1921 vcpu->arch.apic_attention = 0;
1922
1923 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
1924 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1925 vcpu, kvm_lapic_get_reg(apic, APIC_ID),
1926 vcpu->arch.apic_base, apic->base_address);
1927 }
1928
1929 /*
1930 *----------------------------------------------------------------------
1931 * timer interface
1932 *----------------------------------------------------------------------
1933 */
1934
1935 static bool lapic_is_periodic(struct kvm_lapic *apic)
1936 {
1937 return apic_lvtt_period(apic);
1938 }
1939
1940 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1941 {
1942 struct kvm_lapic *apic = vcpu->arch.apic;
1943
1944 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1945 return atomic_read(&apic->lapic_timer.pending);
1946
1947 return 0;
1948 }
1949
1950 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1951 {
1952 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1953 int vector, mode, trig_mode;
1954
1955 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1956 vector = reg & APIC_VECTOR_MASK;
1957 mode = reg & APIC_MODE_MASK;
1958 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1959 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1960 NULL);
1961 }
1962 return 0;
1963 }
1964
1965 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1966 {
1967 struct kvm_lapic *apic = vcpu->arch.apic;
1968
1969 if (apic)
1970 kvm_apic_local_deliver(apic, APIC_LVT0);
1971 }
1972
1973 static const struct kvm_io_device_ops apic_mmio_ops = {
1974 .read = apic_mmio_read,
1975 .write = apic_mmio_write,
1976 };
1977
1978 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1979 {
1980 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1981 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1982
1983 apic_timer_expired(apic);
1984
1985 if (lapic_is_periodic(apic)) {
1986 advance_periodic_target_expiration(apic);
1987 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1988 return HRTIMER_RESTART;
1989 } else
1990 return HRTIMER_NORESTART;
1991 }
1992
1993 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1994 {
1995 struct kvm_lapic *apic;
1996
1997 ASSERT(vcpu != NULL);
1998 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1999
2000 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2001 if (!apic)
2002 goto nomem;
2003
2004 vcpu->arch.apic = apic;
2005
2006 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2007 if (!apic->regs) {
2008 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2009 vcpu->vcpu_id);
2010 goto nomem_free_apic;
2011 }
2012 apic->vcpu = vcpu;
2013
2014 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2015 HRTIMER_MODE_ABS_PINNED);
2016 apic->lapic_timer.timer.function = apic_timer_fn;
2017
2018 /*
2019 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2020 * thinking that APIC satet has changed.
2021 */
2022 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2023 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2024 kvm_lapic_reset(vcpu, false);
2025 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2026
2027 return 0;
2028 nomem_free_apic:
2029 kfree(apic);
2030 nomem:
2031 return -ENOMEM;
2032 }
2033
2034 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2035 {
2036 struct kvm_lapic *apic = vcpu->arch.apic;
2037 int highest_irr;
2038
2039 if (!apic_enabled(apic))
2040 return -1;
2041
2042 apic_update_ppr(apic);
2043 highest_irr = apic_find_highest_irr(apic);
2044 if ((highest_irr == -1) ||
2045 ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
2046 return -1;
2047 return highest_irr;
2048 }
2049
2050 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2051 {
2052 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2053 int r = 0;
2054
2055 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2056 r = 1;
2057 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2058 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2059 r = 1;
2060 return r;
2061 }
2062
2063 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2064 {
2065 struct kvm_lapic *apic = vcpu->arch.apic;
2066
2067 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2068 kvm_apic_local_deliver(apic, APIC_LVTT);
2069 if (apic_lvtt_tscdeadline(apic))
2070 apic->lapic_timer.tscdeadline = 0;
2071 if (apic_lvtt_oneshot(apic)) {
2072 apic->lapic_timer.tscdeadline = 0;
2073 apic->lapic_timer.target_expiration = 0;
2074 }
2075 atomic_set(&apic->lapic_timer.pending, 0);
2076 }
2077 }
2078
2079 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2080 {
2081 int vector = kvm_apic_has_interrupt(vcpu);
2082 struct kvm_lapic *apic = vcpu->arch.apic;
2083
2084 if (vector == -1)
2085 return -1;
2086
2087 /*
2088 * We get here even with APIC virtualization enabled, if doing
2089 * nested virtualization and L1 runs with the "acknowledge interrupt
2090 * on exit" mode. Then we cannot inject the interrupt via RVI,
2091 * because the process would deliver it through the IDT.
2092 */
2093
2094 apic_set_isr(vector, apic);
2095 apic_update_ppr(apic);
2096 apic_clear_irr(vector, apic);
2097
2098 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2099 apic_clear_isr(vector, apic);
2100 apic_update_ppr(apic);
2101 }
2102
2103 return vector;
2104 }
2105
2106 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2107 struct kvm_lapic_state *s, bool set)
2108 {
2109 if (apic_x2apic_mode(vcpu->arch.apic)) {
2110 u32 *id = (u32 *)(s->regs + APIC_ID);
2111
2112 if (vcpu->kvm->arch.x2apic_format) {
2113 if (*id != vcpu->vcpu_id)
2114 return -EINVAL;
2115 } else {
2116 if (set)
2117 *id >>= 24;
2118 else
2119 *id <<= 24;
2120 }
2121 }
2122
2123 return 0;
2124 }
2125
2126 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2127 {
2128 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2129 return kvm_apic_state_fixup(vcpu, s, false);
2130 }
2131
2132 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2133 {
2134 struct kvm_lapic *apic = vcpu->arch.apic;
2135 int r;
2136
2137
2138 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2139 /* set SPIV separately to get count of SW disabled APICs right */
2140 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2141
2142 r = kvm_apic_state_fixup(vcpu, s, true);
2143 if (r)
2144 return r;
2145 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2146
2147 recalculate_apic_map(vcpu->kvm);
2148 kvm_apic_set_version(vcpu);
2149
2150 apic_update_ppr(apic);
2151 hrtimer_cancel(&apic->lapic_timer.timer);
2152 apic_update_lvtt(apic);
2153 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2154 update_divide_count(apic);
2155 start_apic_timer(apic);
2156 apic->irr_pending = true;
2157 apic->isr_count = vcpu->arch.apicv_active ?
2158 1 : count_vectors(apic->regs + APIC_ISR);
2159 apic->highest_isr_cache = -1;
2160 if (vcpu->arch.apicv_active) {
2161 if (kvm_x86_ops->apicv_post_state_restore)
2162 kvm_x86_ops->apicv_post_state_restore(vcpu);
2163 kvm_x86_ops->hwapic_irr_update(vcpu,
2164 apic_find_highest_irr(apic));
2165 kvm_x86_ops->hwapic_isr_update(vcpu,
2166 apic_find_highest_isr(apic));
2167 }
2168 kvm_make_request(KVM_REQ_EVENT, vcpu);
2169 if (ioapic_in_kernel(vcpu->kvm))
2170 kvm_rtc_eoi_tracking_restore_one(vcpu);
2171
2172 vcpu->arch.apic_arb_prio = 0;
2173
2174 return 0;
2175 }
2176
2177 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2178 {
2179 struct hrtimer *timer;
2180
2181 if (!lapic_in_kernel(vcpu))
2182 return;
2183
2184 timer = &vcpu->arch.apic->lapic_timer.timer;
2185 if (hrtimer_cancel(timer))
2186 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2187 }
2188
2189 /*
2190 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2191 *
2192 * Detect whether guest triggered PV EOI since the
2193 * last entry. If yes, set EOI on guests's behalf.
2194 * Clear PV EOI in guest memory in any case.
2195 */
2196 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2197 struct kvm_lapic *apic)
2198 {
2199 bool pending;
2200 int vector;
2201 /*
2202 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2203 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2204 *
2205 * KVM_APIC_PV_EOI_PENDING is unset:
2206 * -> host disabled PV EOI.
2207 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2208 * -> host enabled PV EOI, guest did not execute EOI yet.
2209 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2210 * -> host enabled PV EOI, guest executed EOI.
2211 */
2212 BUG_ON(!pv_eoi_enabled(vcpu));
2213 pending = pv_eoi_get_pending(vcpu);
2214 /*
2215 * Clear pending bit in any case: it will be set again on vmentry.
2216 * While this might not be ideal from performance point of view,
2217 * this makes sure pv eoi is only enabled when we know it's safe.
2218 */
2219 pv_eoi_clr_pending(vcpu);
2220 if (pending)
2221 return;
2222 vector = apic_set_eoi(apic);
2223 trace_kvm_pv_eoi(apic, vector);
2224 }
2225
2226 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2227 {
2228 u32 data;
2229
2230 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2231 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2232
2233 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2234 return;
2235
2236 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2237 sizeof(u32)))
2238 return;
2239
2240 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2241 }
2242
2243 /*
2244 * apic_sync_pv_eoi_to_guest - called before vmentry
2245 *
2246 * Detect whether it's safe to enable PV EOI and
2247 * if yes do so.
2248 */
2249 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2250 struct kvm_lapic *apic)
2251 {
2252 if (!pv_eoi_enabled(vcpu) ||
2253 /* IRR set or many bits in ISR: could be nested. */
2254 apic->irr_pending ||
2255 /* Cache not set: could be safe but we don't bother. */
2256 apic->highest_isr_cache == -1 ||
2257 /* Need EOI to update ioapic. */
2258 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2259 /*
2260 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2261 * so we need not do anything here.
2262 */
2263 return;
2264 }
2265
2266 pv_eoi_set_pending(apic->vcpu);
2267 }
2268
2269 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2270 {
2271 u32 data, tpr;
2272 int max_irr, max_isr;
2273 struct kvm_lapic *apic = vcpu->arch.apic;
2274
2275 apic_sync_pv_eoi_to_guest(vcpu, apic);
2276
2277 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2278 return;
2279
2280 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2281 max_irr = apic_find_highest_irr(apic);
2282 if (max_irr < 0)
2283 max_irr = 0;
2284 max_isr = apic_find_highest_isr(apic);
2285 if (max_isr < 0)
2286 max_isr = 0;
2287 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2288
2289 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2290 sizeof(u32));
2291 }
2292
2293 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2294 {
2295 if (vapic_addr) {
2296 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2297 &vcpu->arch.apic->vapic_cache,
2298 vapic_addr, sizeof(u32)))
2299 return -EINVAL;
2300 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2301 } else {
2302 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2303 }
2304
2305 vcpu->arch.apic->vapic_addr = vapic_addr;
2306 return 0;
2307 }
2308
2309 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2310 {
2311 struct kvm_lapic *apic = vcpu->arch.apic;
2312 u32 reg = (msr - APIC_BASE_MSR) << 4;
2313
2314 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2315 return 1;
2316
2317 if (reg == APIC_ICR2)
2318 return 1;
2319
2320 /* if this is ICR write vector before command */
2321 if (reg == APIC_ICR)
2322 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2323 return kvm_lapic_reg_write(apic, reg, (u32)data);
2324 }
2325
2326 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2327 {
2328 struct kvm_lapic *apic = vcpu->arch.apic;
2329 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2330
2331 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2332 return 1;
2333
2334 if (reg == APIC_DFR || reg == APIC_ICR2) {
2335 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2336 reg);
2337 return 1;
2338 }
2339
2340 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2341 return 1;
2342 if (reg == APIC_ICR)
2343 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2344
2345 *data = (((u64)high) << 32) | low;
2346
2347 return 0;
2348 }
2349
2350 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2351 {
2352 struct kvm_lapic *apic = vcpu->arch.apic;
2353
2354 if (!lapic_in_kernel(vcpu))
2355 return 1;
2356
2357 /* if this is ICR write vector before command */
2358 if (reg == APIC_ICR)
2359 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2360 return kvm_lapic_reg_write(apic, reg, (u32)data);
2361 }
2362
2363 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2364 {
2365 struct kvm_lapic *apic = vcpu->arch.apic;
2366 u32 low, high = 0;
2367
2368 if (!lapic_in_kernel(vcpu))
2369 return 1;
2370
2371 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2372 return 1;
2373 if (reg == APIC_ICR)
2374 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2375
2376 *data = (((u64)high) << 32) | low;
2377
2378 return 0;
2379 }
2380
2381 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2382 {
2383 u64 addr = data & ~KVM_MSR_ENABLED;
2384 if (!IS_ALIGNED(addr, 4))
2385 return 1;
2386
2387 vcpu->arch.pv_eoi.msr_val = data;
2388 if (!pv_eoi_enabled(vcpu))
2389 return 0;
2390 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2391 addr, sizeof(u8));
2392 }
2393
2394 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2395 {
2396 struct kvm_lapic *apic = vcpu->arch.apic;
2397 u8 sipi_vector;
2398 unsigned long pe;
2399
2400 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2401 return;
2402
2403 /*
2404 * INITs are latched while in SMM. Because an SMM CPU cannot
2405 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2406 * and delay processing of INIT until the next RSM.
2407 */
2408 if (is_smm(vcpu)) {
2409 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2410 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2411 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2412 return;
2413 }
2414
2415 pe = xchg(&apic->pending_events, 0);
2416 if (test_bit(KVM_APIC_INIT, &pe)) {
2417 kvm_lapic_reset(vcpu, true);
2418 kvm_vcpu_reset(vcpu, true);
2419 if (kvm_vcpu_is_bsp(apic->vcpu))
2420 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2421 else
2422 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2423 }
2424 if (test_bit(KVM_APIC_SIPI, &pe) &&
2425 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2426 /* evaluate pending_events before reading the vector */
2427 smp_rmb();
2428 sipi_vector = apic->sipi_vector;
2429 apic_debug("vcpu %d received sipi with vector # %x\n",
2430 vcpu->vcpu_id, sipi_vector);
2431 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2432 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2433 }
2434 }
2435
2436 void kvm_lapic_init(void)
2437 {
2438 /* do not patch jump label more than once per second */
2439 jump_label_rate_limit(&apic_hw_disabled, HZ);
2440 jump_label_rate_limit(&apic_sw_disabled, HZ);
2441 }
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