3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #define mod_64(x, y) ((x) % (y))
55 #define APIC_BUS_CYCLE_NS 1
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
71 #define VEC_POS(v) ((v) & (32 - 1))
72 #define REG_POS(v) (((v) >> 5) << 4)
74 static unsigned int min_timer_period_us
= 500;
75 module_param(min_timer_period_us
, uint
, S_IRUGO
| S_IWUSR
);
77 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
79 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
82 static inline int apic_test_and_set_vector(int vec
, void *bitmap
)
84 return test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
87 static inline int apic_test_and_clear_vector(int vec
, void *bitmap
)
89 return test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
92 static inline int apic_test_vector(int vec
, void *bitmap
)
94 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
97 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
99 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
101 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
102 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
105 static inline void apic_set_vector(int vec
, void *bitmap
)
107 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
110 static inline void apic_clear_vector(int vec
, void *bitmap
)
112 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
115 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
117 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
120 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
122 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
125 struct static_key_deferred apic_hw_disabled __read_mostly
;
126 struct static_key_deferred apic_sw_disabled __read_mostly
;
128 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
130 if ((kvm_apic_get_reg(apic
, APIC_SPIV
) ^ val
) & APIC_SPIV_APIC_ENABLED
) {
131 if (val
& APIC_SPIV_APIC_ENABLED
)
132 static_key_slow_dec_deferred(&apic_sw_disabled
);
134 static_key_slow_inc(&apic_sw_disabled
.key
);
136 apic_set_reg(apic
, APIC_SPIV
, val
);
139 static inline int apic_enabled(struct kvm_lapic
*apic
)
141 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
145 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
148 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
149 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
151 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
153 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
156 static void recalculate_apic_map(struct kvm
*kvm
)
158 struct kvm_apic_map
*new, *old
= NULL
;
159 struct kvm_vcpu
*vcpu
;
162 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
164 mutex_lock(&kvm
->arch
.apic_map_lock
);
170 /* flat mode is default */
173 new->lid_mask
= 0xff;
175 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
176 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
180 if (!kvm_apic_present(vcpu
))
184 * All APICs have to be configured in the same mode by an OS.
185 * We take advatage of this while building logical id loockup
186 * table. After reset APICs are in xapic/flat mode, so if we
187 * find apic with different setting we assume this is the mode
188 * OS wants all apics to be in; build lookup table accordingly.
190 if (apic_x2apic_mode(apic
)) {
193 new->cid_mask
= new->lid_mask
= 0xffff;
194 } else if (kvm_apic_sw_enabled(apic
) &&
195 !new->cid_mask
/* flat mode */ &&
196 kvm_apic_get_reg(apic
, APIC_DFR
) == APIC_DFR_CLUSTER
) {
202 new->phys_map
[kvm_apic_id(apic
)] = apic
;
204 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
205 cid
= apic_cluster_id(new, ldr
);
206 lid
= apic_logical_id(new, ldr
);
209 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
212 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
213 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
214 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
215 mutex_unlock(&kvm
->arch
.apic_map_lock
);
220 kvm_vcpu_request_scan_ioapic(kvm
);
223 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
225 apic_set_reg(apic
, APIC_ID
, id
<< 24);
226 recalculate_apic_map(apic
->vcpu
->kvm
);
229 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
231 apic_set_reg(apic
, APIC_LDR
, id
);
232 recalculate_apic_map(apic
->vcpu
->kvm
);
235 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
237 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
240 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
242 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
245 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
247 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
248 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_ONESHOT
);
251 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
253 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
254 apic
->lapic_timer
.timer_mode_mask
) == APIC_LVT_TIMER_PERIODIC
);
257 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
259 return ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
260 apic
->lapic_timer
.timer_mode_mask
) ==
261 APIC_LVT_TIMER_TSCDEADLINE
);
264 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
266 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
269 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
271 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
272 struct kvm_cpuid_entry2
*feat
;
273 u32 v
= APIC_VERSION
;
275 if (!kvm_vcpu_has_lapic(vcpu
))
278 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
279 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
280 v
|= APIC_LVR_DIRECTED_EOI
;
281 apic_set_reg(apic
, APIC_LVR
, v
);
284 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
285 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
286 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
287 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
288 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
289 LVT_MASK
/* LVTERR */
292 static int find_highest_vector(void *bitmap
)
297 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
298 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
299 reg
= bitmap
+ REG_POS(vec
);
301 return fls(*reg
) - 1 + vec
;
307 static u8
count_vectors(void *bitmap
)
313 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
314 reg
= bitmap
+ REG_POS(vec
);
315 count
+= hweight32(*reg
);
321 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
324 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
326 for (i
= 0; i
<= 7; i
++) {
327 pir_val
= xchg(&pir
[i
], 0);
329 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
332 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
334 static inline int apic_test_and_set_irr(int vec
, struct kvm_lapic
*apic
)
336 apic
->irr_pending
= true;
337 return apic_test_and_set_vector(vec
, apic
->regs
+ APIC_IRR
);
340 static inline int apic_search_irr(struct kvm_lapic
*apic
)
342 return find_highest_vector(apic
->regs
+ APIC_IRR
);
345 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
350 * Note that irr_pending is just a hint. It will be always
351 * true with virtual interrupt delivery enabled.
353 if (!apic
->irr_pending
)
356 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
357 result
= apic_search_irr(apic
);
358 ASSERT(result
== -1 || result
>= 16);
363 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
365 apic
->irr_pending
= false;
366 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
367 if (apic_search_irr(apic
) != -1)
368 apic
->irr_pending
= true;
371 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
373 if (!__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
375 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
377 * ISR (in service register) bit is set when injecting an interrupt.
378 * The highest vector is injected. Thus the latest bit set matches
379 * the highest bit in ISR.
381 apic
->highest_isr_cache
= vec
;
384 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
386 if (__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
388 BUG_ON(apic
->isr_count
< 0);
389 apic
->highest_isr_cache
= -1;
392 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
396 /* This may race with setting of irr in __apic_accept_irq() and
397 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
398 * will cause vmexit immediately and the value will be recalculated
399 * on the next vmentry.
401 if (!kvm_vcpu_has_lapic(vcpu
))
403 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
408 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
409 int vector
, int level
, int trig_mode
,
410 unsigned long *dest_map
);
412 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
413 unsigned long *dest_map
)
415 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
417 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
418 irq
->level
, irq
->trig_mode
, dest_map
);
421 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
424 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
428 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
431 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
435 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
437 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
440 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
443 if (pv_eoi_get_user(vcpu
, &val
) < 0)
444 apic_debug("Can't read EOI MSR value: 0x%llx\n",
445 (unsigned long long)vcpi
->arch
.pv_eoi
.msr_val
);
449 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
451 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
452 apic_debug("Can't set EOI MSR value: 0x%llx\n",
453 (unsigned long long)vcpi
->arch
.pv_eoi
.msr_val
);
456 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
459 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
461 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
462 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
463 (unsigned long long)vcpi
->arch
.pv_eoi
.msr_val
);
466 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
469 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
473 /* Note that isr_count is always 1 with vid enabled */
474 if (!apic
->isr_count
)
476 if (likely(apic
->highest_isr_cache
!= -1))
477 return apic
->highest_isr_cache
;
479 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
480 ASSERT(result
== -1 || result
>= 16);
485 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
487 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
490 for (i
= 0; i
< 8; i
++)
491 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
494 static void apic_update_ppr(struct kvm_lapic
*apic
)
496 u32 tpr
, isrv
, ppr
, old_ppr
;
499 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
500 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
501 isr
= apic_find_highest_isr(apic
);
502 isrv
= (isr
!= -1) ? isr
: 0;
504 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
509 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
510 apic
, ppr
, isr
, isrv
);
512 if (old_ppr
!= ppr
) {
513 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
515 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
519 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
521 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
522 apic_update_ppr(apic
);
525 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
527 return dest
== 0xff || kvm_apic_id(apic
) == dest
;
530 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
535 if (apic_x2apic_mode(apic
)) {
536 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
537 return logical_id
& mda
;
540 logical_id
= GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic
, APIC_LDR
));
542 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
544 if (logical_id
& mda
)
547 case APIC_DFR_CLUSTER
:
548 if (((logical_id
>> 4) == (mda
>> 0x4))
549 && (logical_id
& mda
& 0xf))
553 apic_debug("Bad DFR vcpu %d: %08x\n",
554 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
561 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
562 int short_hand
, int dest
, int dest_mode
)
565 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
567 apic_debug("target %p, source %p, dest 0x%x, "
568 "dest_mode 0x%x, short_hand 0x%x\n",
569 target
, source
, dest
, dest_mode
, short_hand
);
572 switch (short_hand
) {
573 case APIC_DEST_NOSHORT
:
576 result
= kvm_apic_match_physical_addr(target
, dest
);
579 result
= kvm_apic_match_logical_addr(target
, dest
);
582 result
= (target
== source
);
584 case APIC_DEST_ALLINC
:
587 case APIC_DEST_ALLBUT
:
588 result
= (target
!= source
);
591 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
599 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
600 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
602 struct kvm_apic_map
*map
;
603 unsigned long bitmap
= 1;
604 struct kvm_lapic
**dst
;
610 if (irq
->shorthand
== APIC_DEST_SELF
) {
611 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
619 map
= rcu_dereference(kvm
->arch
.apic_map
);
624 if (irq
->dest_mode
== 0) { /* physical mode */
625 if (irq
->delivery_mode
== APIC_DM_LOWEST
||
626 irq
->dest_id
== 0xff)
628 dst
= &map
->phys_map
[irq
->dest_id
& 0xff];
630 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
632 dst
= map
->logical_map
[apic_cluster_id(map
, mda
)];
634 bitmap
= apic_logical_id(map
, mda
);
636 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
638 for_each_set_bit(i
, &bitmap
, 16) {
643 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
647 bitmap
= (l
>= 0) ? 1 << l
: 0;
651 for_each_set_bit(i
, &bitmap
, 16) {
656 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
666 * Add a pending IRQ into lapic.
667 * Return 1 if successfully added and 0 if discarded.
669 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
670 int vector
, int level
, int trig_mode
,
671 unsigned long *dest_map
)
674 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
676 switch (delivery_mode
) {
678 vcpu
->arch
.apic_arb_prio
++;
680 /* FIXME add logic for vcpu on reset */
681 if (unlikely(!apic_enabled(apic
)))
685 __set_bit(vcpu
->vcpu_id
, dest_map
);
687 if (kvm_x86_ops
->deliver_posted_interrupt
) {
689 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
691 result
= !apic_test_and_set_irr(vector
, apic
);
695 apic_debug("level trig mode repeatedly "
696 "for vector %d", vector
);
700 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
704 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
705 trig_mode
, vector
, !result
);
709 apic_debug("Ignoring delivery mode 3\n");
713 apic_debug("Ignoring guest SMI\n");
718 kvm_inject_nmi(vcpu
);
723 if (!trig_mode
|| level
) {
725 /* assumes that there are only KVM_APIC_INIT/SIPI */
726 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
727 /* make sure pending_events is visible before sending
730 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
733 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
738 case APIC_DM_STARTUP
:
739 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
740 vcpu
->vcpu_id
, vector
);
742 apic
->sipi_vector
= vector
;
743 /* make sure sipi_vector is visible for the receiver */
745 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
746 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
752 * Should only be called by kvm_apic_local_deliver() with LVT0,
753 * before NMI watchdog was enabled. Already handled by
754 * kvm_apic_accept_pic_intr().
759 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
766 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
768 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
771 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
773 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
774 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
776 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
777 trigger_mode
= IOAPIC_LEVEL_TRIG
;
779 trigger_mode
= IOAPIC_EDGE_TRIG
;
780 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
784 static int apic_set_eoi(struct kvm_lapic
*apic
)
786 int vector
= apic_find_highest_isr(apic
);
788 trace_kvm_eoi(apic
, vector
);
791 * Not every write EOI will has corresponding ISR,
792 * one example is when Kernel check timer on setup_IO_APIC
797 apic_clear_isr(vector
, apic
);
798 apic_update_ppr(apic
);
800 kvm_ioapic_send_eoi(apic
, vector
);
801 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
806 * this interface assumes a trap-like exit, which has already finished
807 * desired side effect including vISR and vPPR update.
809 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
811 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
813 trace_kvm_eoi(apic
, vector
);
815 kvm_ioapic_send_eoi(apic
, vector
);
816 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
818 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
820 static void apic_send_ipi(struct kvm_lapic
*apic
)
822 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
823 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
824 struct kvm_lapic_irq irq
;
826 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
827 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
828 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
829 irq
.level
= icr_low
& APIC_INT_ASSERT
;
830 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
831 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
832 if (apic_x2apic_mode(apic
))
833 irq
.dest_id
= icr_high
;
835 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
837 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
839 apic_debug("icr_high 0x%x, icr_low 0x%x, "
840 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
841 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
842 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
843 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
846 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
849 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
855 ASSERT(apic
!= NULL
);
857 /* if initial count is 0, current count should also be 0 */
858 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0)
861 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
862 if (ktime_to_ns(remaining
) < 0)
863 remaining
= ktime_set(0, 0);
865 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
866 tmcct
= div64_u64(ns
,
867 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
872 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
874 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
875 struct kvm_run
*run
= vcpu
->run
;
877 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
878 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
879 run
->tpr_access
.is_write
= write
;
882 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
884 if (apic
->vcpu
->arch
.tpr_access_reporting
)
885 __report_tpr_access(apic
, write
);
888 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
892 if (offset
>= LAPIC_MMIO_LENGTH
)
897 if (apic_x2apic_mode(apic
))
898 val
= kvm_apic_id(apic
);
900 val
= kvm_apic_id(apic
) << 24;
903 apic_debug("Access APIC ARBPRI register which is for P6\n");
906 case APIC_TMCCT
: /* Timer CCR */
907 if (apic_lvtt_tscdeadline(apic
))
910 val
= apic_get_tmcct(apic
);
913 apic_update_ppr(apic
);
914 val
= kvm_apic_get_reg(apic
, offset
);
917 report_tpr_access(apic
, false);
920 val
= kvm_apic_get_reg(apic
, offset
);
927 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
929 return container_of(dev
, struct kvm_lapic
, dev
);
932 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
935 unsigned char alignment
= offset
& 0xf;
937 /* this bitmask has a bit cleared for each reserved register */
938 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
940 if ((alignment
+ len
) > 4) {
941 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
946 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
947 apic_debug("KVM_APIC_READ: read reserved register %x\n",
952 result
= __apic_read(apic
, offset
& ~0xf);
954 trace_kvm_apic_read(offset
, result
);
960 memcpy(data
, (char *)&result
+ alignment
, len
);
963 printk(KERN_ERR
"Local APIC read with len = %x, "
964 "should be 1,2, or 4 instead\n", len
);
970 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
972 return kvm_apic_hw_enabled(apic
) &&
973 addr
>= apic
->base_address
&&
974 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
977 static int apic_mmio_read(struct kvm_io_device
*this,
978 gpa_t address
, int len
, void *data
)
980 struct kvm_lapic
*apic
= to_lapic(this);
981 u32 offset
= address
- apic
->base_address
;
983 if (!apic_mmio_in_range(apic
, address
))
986 apic_reg_read(apic
, offset
, len
, data
);
991 static void update_divide_count(struct kvm_lapic
*apic
)
993 u32 tmp1
, tmp2
, tdcr
;
995 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
997 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
998 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1000 apic_debug("timer divide count is 0x%x\n",
1001 apic
->divide_count
);
1004 static void start_apic_timer(struct kvm_lapic
*apic
)
1007 atomic_set(&apic
->lapic_timer
.pending
, 0);
1009 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1010 /* lapic timer in oneshot or periodic mode */
1011 now
= apic
->lapic_timer
.timer
.base
->get_time();
1012 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1013 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1015 if (!apic
->lapic_timer
.period
)
1018 * Do not allow the guest to program periodic timers with small
1019 * interval, since the hrtimers are not throttled by the host
1022 if (apic_lvtt_period(apic
)) {
1023 s64 min_period
= min_timer_period_us
* 1000LL;
1025 if (apic
->lapic_timer
.period
< min_period
) {
1026 pr_info_ratelimited(
1027 "kvm: vcpu %i: requested %lld ns "
1028 "lapic timer period limited to %lld ns\n",
1029 apic
->vcpu
->vcpu_id
,
1030 apic
->lapic_timer
.period
, min_period
);
1031 apic
->lapic_timer
.period
= min_period
;
1035 hrtimer_start(&apic
->lapic_timer
.timer
,
1036 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1039 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1041 "timer initial count 0x%x, period %lldns, "
1042 "expire @ 0x%016" PRIx64
".\n", __func__
,
1043 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1044 kvm_apic_get_reg(apic
, APIC_TMICT
),
1045 apic
->lapic_timer
.period
,
1046 ktime_to_ns(ktime_add_ns(now
,
1047 apic
->lapic_timer
.period
)));
1048 } else if (apic_lvtt_tscdeadline(apic
)) {
1049 /* lapic timer in tsc deadline mode */
1050 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1052 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1053 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1054 unsigned long flags
;
1056 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1059 local_irq_save(flags
);
1061 now
= apic
->lapic_timer
.timer
.base
->get_time();
1062 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1063 if (likely(tscdeadline
> guest_tsc
)) {
1064 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1065 do_div(ns
, this_tsc_khz
);
1067 hrtimer_start(&apic
->lapic_timer
.timer
,
1068 ktime_add_ns(now
, ns
), HRTIMER_MODE_ABS
);
1070 local_irq_restore(flags
);
1074 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1076 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1078 if (apic_lvt_nmi_mode(lvt0_val
)) {
1079 if (!nmi_wd_enabled
) {
1080 apic_debug("Receive NMI setting on APIC_LVT0 "
1081 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1082 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1084 } else if (nmi_wd_enabled
)
1085 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1088 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1092 trace_kvm_apic_write(reg
, val
);
1095 case APIC_ID
: /* Local APIC ID */
1096 if (!apic_x2apic_mode(apic
))
1097 kvm_apic_set_id(apic
, val
>> 24);
1103 report_tpr_access(apic
, true);
1104 apic_set_tpr(apic
, val
& 0xff);
1112 if (!apic_x2apic_mode(apic
))
1113 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1119 if (!apic_x2apic_mode(apic
)) {
1120 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1121 recalculate_apic_map(apic
->vcpu
->kvm
);
1128 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1129 mask
|= APIC_SPIV_DIRECTED_EOI
;
1130 apic_set_spiv(apic
, val
& mask
);
1131 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1135 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1136 lvt_val
= kvm_apic_get_reg(apic
,
1137 APIC_LVTT
+ 0x10 * i
);
1138 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1139 lvt_val
| APIC_LVT_MASKED
);
1141 atomic_set(&apic
->lapic_timer
.pending
, 0);
1147 /* No delay here, so we always clear the pending bit */
1148 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1149 apic_send_ipi(apic
);
1153 if (!apic_x2apic_mode(apic
))
1155 apic_set_reg(apic
, APIC_ICR2
, val
);
1159 apic_manage_nmi_watchdog(apic
, val
);
1164 /* TODO: Check vector */
1165 if (!kvm_apic_sw_enabled(apic
))
1166 val
|= APIC_LVT_MASKED
;
1168 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1169 apic_set_reg(apic
, reg
, val
);
1174 if ((kvm_apic_get_reg(apic
, APIC_LVTT
) &
1175 apic
->lapic_timer
.timer_mode_mask
) !=
1176 (val
& apic
->lapic_timer
.timer_mode_mask
))
1177 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1179 if (!kvm_apic_sw_enabled(apic
))
1180 val
|= APIC_LVT_MASKED
;
1181 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1182 apic_set_reg(apic
, APIC_LVTT
, val
);
1186 if (apic_lvtt_tscdeadline(apic
))
1189 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1190 apic_set_reg(apic
, APIC_TMICT
, val
);
1191 start_apic_timer(apic
);
1196 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1197 apic_set_reg(apic
, APIC_TDCR
, val
);
1198 update_divide_count(apic
);
1202 if (apic_x2apic_mode(apic
) && val
!= 0) {
1203 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1209 if (apic_x2apic_mode(apic
)) {
1210 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1219 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1223 static int apic_mmio_write(struct kvm_io_device
*this,
1224 gpa_t address
, int len
, const void *data
)
1226 struct kvm_lapic
*apic
= to_lapic(this);
1227 unsigned int offset
= address
- apic
->base_address
;
1230 if (!apic_mmio_in_range(apic
, address
))
1234 * APIC register must be aligned on 128-bits boundary.
1235 * 32/64/128 bits registers must be accessed thru 32 bits.
1238 if (len
!= 4 || (offset
& 0xf)) {
1239 /* Don't shout loud, $infamous_os would cause only noise. */
1240 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1246 /* too common printing */
1247 if (offset
!= APIC_EOI
)
1248 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1249 "0x%x\n", __func__
, offset
, len
, val
);
1251 apic_reg_write(apic
, offset
& 0xff0, val
);
1256 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1258 if (kvm_vcpu_has_lapic(vcpu
))
1259 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1261 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1263 /* emulate APIC access in a trap manner */
1264 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1268 /* hw has done the conditional check and inst decode */
1271 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1273 /* TODO: optimize to just emulate side effect w/o one more write */
1274 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1276 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1278 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1280 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1282 if (!vcpu
->arch
.apic
)
1285 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1287 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1288 static_key_slow_dec_deferred(&apic_hw_disabled
);
1290 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
))
1291 static_key_slow_dec_deferred(&apic_sw_disabled
);
1294 free_page((unsigned long)apic
->regs
);
1300 *----------------------------------------------------------------------
1302 *----------------------------------------------------------------------
1305 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1307 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1309 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1310 apic_lvtt_period(apic
))
1313 return apic
->lapic_timer
.tscdeadline
;
1316 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1318 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1320 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1321 apic_lvtt_period(apic
))
1324 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1325 apic
->lapic_timer
.tscdeadline
= data
;
1326 start_apic_timer(apic
);
1329 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1331 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1333 if (!kvm_vcpu_has_lapic(vcpu
))
1336 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1337 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1340 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1344 if (!kvm_vcpu_has_lapic(vcpu
))
1347 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1349 return (tpr
& 0xf0) >> 4;
1352 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1354 u64 old_value
= vcpu
->arch
.apic_base
;
1355 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1358 value
|= MSR_IA32_APICBASE_BSP
;
1359 vcpu
->arch
.apic_base
= value
;
1363 /* update jump label if enable bit changes */
1364 if ((vcpu
->arch
.apic_base
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1365 if (value
& MSR_IA32_APICBASE_ENABLE
)
1366 static_key_slow_dec_deferred(&apic_hw_disabled
);
1368 static_key_slow_inc(&apic_hw_disabled
.key
);
1369 recalculate_apic_map(vcpu
->kvm
);
1372 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1373 value
&= ~MSR_IA32_APICBASE_BSP
;
1375 vcpu
->arch
.apic_base
= value
;
1376 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1377 if (value
& X2APIC_ENABLE
) {
1378 u32 id
= kvm_apic_id(apic
);
1379 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1380 kvm_apic_set_ldr(apic
, ldr
);
1381 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1383 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1386 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1387 MSR_IA32_APICBASE_BASE
;
1389 /* with FSB delivery interrupt, we can restart APIC functionality */
1390 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1391 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1395 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1397 struct kvm_lapic
*apic
;
1400 apic_debug("%s\n", __func__
);
1403 apic
= vcpu
->arch
.apic
;
1404 ASSERT(apic
!= NULL
);
1406 /* Stop the timer in case it's a reset to an active apic */
1407 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1409 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1410 kvm_apic_set_version(apic
->vcpu
);
1412 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1413 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1414 apic_set_reg(apic
, APIC_LVT0
,
1415 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1417 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1418 apic_set_spiv(apic
, 0xff);
1419 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1420 kvm_apic_set_ldr(apic
, 0);
1421 apic_set_reg(apic
, APIC_ESR
, 0);
1422 apic_set_reg(apic
, APIC_ICR
, 0);
1423 apic_set_reg(apic
, APIC_ICR2
, 0);
1424 apic_set_reg(apic
, APIC_TDCR
, 0);
1425 apic_set_reg(apic
, APIC_TMICT
, 0);
1426 for (i
= 0; i
< 8; i
++) {
1427 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1428 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1429 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1431 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1432 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1433 apic
->highest_isr_cache
= -1;
1434 update_divide_count(apic
);
1435 atomic_set(&apic
->lapic_timer
.pending
, 0);
1436 if (kvm_vcpu_is_bsp(vcpu
))
1437 kvm_lapic_set_base(vcpu
,
1438 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1439 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1440 apic_update_ppr(apic
);
1442 vcpu
->arch
.apic_arb_prio
= 0;
1443 vcpu
->arch
.apic_attention
= 0;
1445 apic_debug(KERN_INFO
"%s: vcpu=%p, id=%d, base_msr="
1446 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1447 vcpu
, kvm_apic_id(apic
),
1448 vcpu
->arch
.apic_base
, apic
->base_address
);
1452 *----------------------------------------------------------------------
1454 *----------------------------------------------------------------------
1457 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1459 return apic_lvtt_period(apic
);
1462 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1464 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1466 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1467 apic_lvt_enabled(apic
, APIC_LVTT
))
1468 return atomic_read(&apic
->lapic_timer
.pending
);
1473 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1475 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1476 int vector
, mode
, trig_mode
;
1478 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1479 vector
= reg
& APIC_VECTOR_MASK
;
1480 mode
= reg
& APIC_MODE_MASK
;
1481 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1482 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1488 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1490 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1493 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1496 static const struct kvm_io_device_ops apic_mmio_ops
= {
1497 .read
= apic_mmio_read
,
1498 .write
= apic_mmio_write
,
1501 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1503 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1504 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1505 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1506 wait_queue_head_t
*q
= &vcpu
->wq
;
1509 * There is a race window between reading and incrementing, but we do
1510 * not care about potentially losing timer events in the !reinject
1511 * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked
1512 * in vcpu_enter_guest.
1514 if (!atomic_read(&ktimer
->pending
)) {
1515 atomic_inc(&ktimer
->pending
);
1516 /* FIXME: this code should not know anything about vcpus */
1517 kvm_make_request(KVM_REQ_PENDING_TIMER
, vcpu
);
1520 if (waitqueue_active(q
))
1521 wake_up_interruptible(q
);
1523 if (lapic_is_periodic(apic
)) {
1524 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1525 return HRTIMER_RESTART
;
1527 return HRTIMER_NORESTART
;
1530 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1532 struct kvm_lapic
*apic
;
1534 ASSERT(vcpu
!= NULL
);
1535 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1537 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1541 vcpu
->arch
.apic
= apic
;
1543 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1545 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1547 goto nomem_free_apic
;
1551 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1553 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1556 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1557 * thinking that APIC satet has changed.
1559 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1560 kvm_lapic_set_base(vcpu
,
1561 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1563 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1564 kvm_lapic_reset(vcpu
);
1565 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1574 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1576 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1579 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1582 apic_update_ppr(apic
);
1583 highest_irr
= apic_find_highest_irr(apic
);
1584 if ((highest_irr
== -1) ||
1585 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1590 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1592 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1595 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1597 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1598 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1603 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1605 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1607 if (!kvm_vcpu_has_lapic(vcpu
))
1610 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1611 if (kvm_apic_local_deliver(apic
, APIC_LVTT
))
1612 atomic_dec(&apic
->lapic_timer
.pending
);
1616 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1618 int vector
= kvm_apic_has_interrupt(vcpu
);
1619 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1624 apic_set_isr(vector
, apic
);
1625 apic_update_ppr(apic
);
1626 apic_clear_irr(vector
, apic
);
1630 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1631 struct kvm_lapic_state
*s
)
1633 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1635 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1636 /* set SPIV separately to get count of SW disabled APICs right */
1637 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1638 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1639 /* call kvm_apic_set_id() to put apic into apic_map */
1640 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1641 kvm_apic_set_version(vcpu
);
1643 apic_update_ppr(apic
);
1644 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1645 update_divide_count(apic
);
1646 start_apic_timer(apic
);
1647 apic
->irr_pending
= true;
1648 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1649 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1650 apic
->highest_isr_cache
= -1;
1651 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, apic_find_highest_isr(apic
));
1652 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1653 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1656 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1658 struct hrtimer
*timer
;
1660 if (!kvm_vcpu_has_lapic(vcpu
))
1663 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1664 if (hrtimer_cancel(timer
))
1665 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1669 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1671 * Detect whether guest triggered PV EOI since the
1672 * last entry. If yes, set EOI on guests's behalf.
1673 * Clear PV EOI in guest memory in any case.
1675 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1676 struct kvm_lapic
*apic
)
1681 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1682 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1684 * KVM_APIC_PV_EOI_PENDING is unset:
1685 * -> host disabled PV EOI.
1686 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1687 * -> host enabled PV EOI, guest did not execute EOI yet.
1688 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1689 * -> host enabled PV EOI, guest executed EOI.
1691 BUG_ON(!pv_eoi_enabled(vcpu
));
1692 pending
= pv_eoi_get_pending(vcpu
);
1694 * Clear pending bit in any case: it will be set again on vmentry.
1695 * While this might not be ideal from performance point of view,
1696 * this makes sure pv eoi is only enabled when we know it's safe.
1698 pv_eoi_clr_pending(vcpu
);
1701 vector
= apic_set_eoi(apic
);
1702 trace_kvm_pv_eoi(apic
, vector
);
1705 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1710 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1711 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1713 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1716 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
);
1717 data
= *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
));
1718 kunmap_atomic(vapic
);
1720 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1724 * apic_sync_pv_eoi_to_guest - called before vmentry
1726 * Detect whether it's safe to enable PV EOI and
1729 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1730 struct kvm_lapic
*apic
)
1732 if (!pv_eoi_enabled(vcpu
) ||
1733 /* IRR set or many bits in ISR: could be nested. */
1734 apic
->irr_pending
||
1735 /* Cache not set: could be safe but we don't bother. */
1736 apic
->highest_isr_cache
== -1 ||
1737 /* Need EOI to update ioapic. */
1738 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1740 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1741 * so we need not do anything here.
1746 pv_eoi_set_pending(apic
->vcpu
);
1749 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1752 int max_irr
, max_isr
;
1753 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1756 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1758 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1761 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1762 max_irr
= apic_find_highest_irr(apic
);
1765 max_isr
= apic_find_highest_isr(apic
);
1768 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1770 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
);
1771 *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
)) = data
;
1772 kunmap_atomic(vapic
);
1775 void kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1777 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1779 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1781 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1784 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1786 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1787 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1789 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1792 /* if this is ICR write vector before command */
1794 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1795 return apic_reg_write(apic
, reg
, (u32
)data
);
1798 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1800 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1801 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1803 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1806 if (apic_reg_read(apic
, reg
, 4, &low
))
1809 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1811 *data
= (((u64
)high
) << 32) | low
;
1816 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1818 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1820 if (!kvm_vcpu_has_lapic(vcpu
))
1823 /* if this is ICR write vector before command */
1824 if (reg
== APIC_ICR
)
1825 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1826 return apic_reg_write(apic
, reg
, (u32
)data
);
1829 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1831 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1834 if (!kvm_vcpu_has_lapic(vcpu
))
1837 if (apic_reg_read(apic
, reg
, 4, &low
))
1839 if (reg
== APIC_ICR
)
1840 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1842 *data
= (((u64
)high
) << 32) | low
;
1847 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1849 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1850 if (!IS_ALIGNED(addr
, 4))
1853 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1854 if (!pv_eoi_enabled(vcpu
))
1856 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
1860 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
1862 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1863 unsigned int sipi_vector
;
1865 if (!kvm_vcpu_has_lapic(vcpu
))
1868 if (test_and_clear_bit(KVM_APIC_INIT
, &apic
->pending_events
)) {
1869 kvm_lapic_reset(vcpu
);
1870 kvm_vcpu_reset(vcpu
);
1871 if (kvm_vcpu_is_bsp(apic
->vcpu
))
1872 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1874 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
1876 if (test_and_clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
) &&
1877 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
1878 /* evaluate pending_events before reading the vector */
1880 sipi_vector
= apic
->sipi_vector
;
1881 pr_debug("vcpu %d received sipi with vector # %x\n",
1882 vcpu
->vcpu_id
, sipi_vector
);
1883 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
1884 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
1888 void kvm_lapic_init(void)
1890 /* do not patch jump label more than once per second */
1891 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
1892 jump_label_rate_limit(&apic_sw_disabled
, HZ
);