3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/export.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
60 /* 14 is the version for Xeon and Pentium 8.4.8*/
61 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
62 #define LAPIC_MMIO_LENGTH (1 << 12)
63 /* followed define is not in apicdef.h */
64 #define APIC_SHORT_MASK 0xc0000
65 #define APIC_DEST_NOSHORT 0x0
66 #define APIC_DEST_MASK 0x800
67 #define MAX_APIC_VECTOR 256
68 #define APIC_VECTORS_PER_REG 32
70 #define APIC_BROADCAST 0xFF
71 #define X2APIC_BROADCAST 0xFFFFFFFFul
73 static inline int apic_test_vector(int vec
, void *bitmap
)
75 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
78 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
80 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
82 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
83 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
86 static inline void apic_clear_vector(int vec
, void *bitmap
)
88 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
91 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
93 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
96 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
98 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
101 struct static_key_deferred apic_hw_disabled __read_mostly
;
102 struct static_key_deferred apic_sw_disabled __read_mostly
;
104 static inline int apic_enabled(struct kvm_lapic
*apic
)
106 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
110 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
113 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
114 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
116 static inline u8
kvm_xapic_id(struct kvm_lapic
*apic
)
118 return kvm_lapic_get_reg(apic
, APIC_ID
) >> 24;
121 static inline u32
kvm_x2apic_id(struct kvm_lapic
*apic
)
123 return apic
->vcpu
->vcpu_id
;
126 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map
*map
,
127 u32 dest_id
, struct kvm_lapic
***cluster
, u16
*mask
) {
129 case KVM_APIC_MODE_X2APIC
: {
130 u32 offset
= (dest_id
>> 16) * 16;
131 u32 max_apic_id
= map
->max_apic_id
;
133 if (offset
<= max_apic_id
) {
134 u8 cluster_size
= min(max_apic_id
- offset
+ 1, 16U);
136 *cluster
= &map
->phys_map
[offset
];
137 *mask
= dest_id
& (0xffff >> (16 - cluster_size
));
144 case KVM_APIC_MODE_XAPIC_FLAT
:
145 *cluster
= map
->xapic_flat_map
;
146 *mask
= dest_id
& 0xff;
148 case KVM_APIC_MODE_XAPIC_CLUSTER
:
149 *cluster
= map
->xapic_cluster_map
[(dest_id
>> 4) & 0xf];
150 *mask
= dest_id
& 0xf;
158 static void kvm_apic_map_free(struct rcu_head
*rcu
)
160 struct kvm_apic_map
*map
= container_of(rcu
, struct kvm_apic_map
, rcu
);
165 static void recalculate_apic_map(struct kvm
*kvm
)
167 struct kvm_apic_map
*new, *old
= NULL
;
168 struct kvm_vcpu
*vcpu
;
170 u32 max_id
= 255; /* enough space for any xAPIC ID */
172 mutex_lock(&kvm
->arch
.apic_map_lock
);
174 kvm_for_each_vcpu(i
, vcpu
, kvm
)
175 if (kvm_apic_present(vcpu
))
176 max_id
= max(max_id
, kvm_x2apic_id(vcpu
->arch
.apic
));
178 new = kvzalloc(sizeof(struct kvm_apic_map
) +
179 sizeof(struct kvm_lapic
*) * ((u64
)max_id
+ 1), GFP_KERNEL
);
184 new->max_apic_id
= max_id
;
186 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
187 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
188 struct kvm_lapic
**cluster
;
194 if (!kvm_apic_present(vcpu
))
197 xapic_id
= kvm_xapic_id(apic
);
198 x2apic_id
= kvm_x2apic_id(apic
);
200 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
201 if ((apic_x2apic_mode(apic
) || x2apic_id
> 0xff) &&
202 x2apic_id
<= new->max_apic_id
)
203 new->phys_map
[x2apic_id
] = apic
;
205 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
206 * prevent them from masking VCPUs with APIC ID <= 0xff.
208 if (!apic_x2apic_mode(apic
) && !new->phys_map
[xapic_id
])
209 new->phys_map
[xapic_id
] = apic
;
211 ldr
= kvm_lapic_get_reg(apic
, APIC_LDR
);
213 if (apic_x2apic_mode(apic
)) {
214 new->mode
|= KVM_APIC_MODE_X2APIC
;
216 ldr
= GET_APIC_LOGICAL_ID(ldr
);
217 if (kvm_lapic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
218 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
220 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
223 if (!kvm_apic_map_get_logical_dest(new, ldr
, &cluster
, &mask
))
227 cluster
[ffs(mask
) - 1] = apic
;
230 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
231 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
232 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
233 mutex_unlock(&kvm
->arch
.apic_map_lock
);
236 call_rcu(&old
->rcu
, kvm_apic_map_free
);
238 kvm_make_scan_ioapic_request(kvm
);
241 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
243 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
245 kvm_lapic_set_reg(apic
, APIC_SPIV
, val
);
247 if (enabled
!= apic
->sw_enabled
) {
248 apic
->sw_enabled
= enabled
;
250 static_key_slow_dec_deferred(&apic_sw_disabled
);
251 recalculate_apic_map(apic
->vcpu
->kvm
);
253 static_key_slow_inc(&apic_sw_disabled
.key
);
257 static inline void kvm_apic_set_xapic_id(struct kvm_lapic
*apic
, u8 id
)
259 kvm_lapic_set_reg(apic
, APIC_ID
, id
<< 24);
260 recalculate_apic_map(apic
->vcpu
->kvm
);
263 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
265 kvm_lapic_set_reg(apic
, APIC_LDR
, id
);
266 recalculate_apic_map(apic
->vcpu
->kvm
);
269 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic
*apic
, u32 id
)
271 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
273 WARN_ON_ONCE(id
!= apic
->vcpu
->vcpu_id
);
275 kvm_lapic_set_reg(apic
, APIC_ID
, id
);
276 kvm_lapic_set_reg(apic
, APIC_LDR
, ldr
);
277 recalculate_apic_map(apic
->vcpu
->kvm
);
280 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
282 return !(kvm_lapic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
285 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
287 return kvm_lapic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
290 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
292 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
295 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
297 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
300 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
302 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
305 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
307 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
310 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
312 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
313 struct kvm_cpuid_entry2
*feat
;
314 u32 v
= APIC_VERSION
;
316 if (!lapic_in_kernel(vcpu
))
319 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
320 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
321 v
|= APIC_LVR_DIRECTED_EOI
;
322 kvm_lapic_set_reg(apic
, APIC_LVR
, v
);
325 static const unsigned int apic_lvt_mask
[KVM_APIC_LVT_NUM
] = {
326 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
327 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
328 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
329 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
330 LVT_MASK
/* LVTERR */
333 static int find_highest_vector(void *bitmap
)
338 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
339 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
340 reg
= bitmap
+ REG_POS(vec
);
342 return __fls(*reg
) + vec
;
348 static u8
count_vectors(void *bitmap
)
354 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
355 reg
= bitmap
+ REG_POS(vec
);
356 count
+= hweight32(*reg
);
362 int __kvm_apic_update_irr(u32
*pir
, void *regs
)
365 u32 pir_val
, irr_val
;
368 for (i
= vec
= 0; i
<= 7; i
++, vec
+= 32) {
369 pir_val
= READ_ONCE(pir
[i
]);
370 irr_val
= *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10));
372 irr_val
|= xchg(&pir
[i
], 0);
373 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) = irr_val
;
376 max_irr
= __fls(irr_val
) + vec
;
381 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
383 int kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
385 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
387 return __kvm_apic_update_irr(pir
, apic
->regs
);
389 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
391 static inline int apic_search_irr(struct kvm_lapic
*apic
)
393 return find_highest_vector(apic
->regs
+ APIC_IRR
);
396 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
401 * Note that irr_pending is just a hint. It will be always
402 * true with virtual interrupt delivery enabled.
404 if (!apic
->irr_pending
)
407 result
= apic_search_irr(apic
);
408 ASSERT(result
== -1 || result
>= 16);
413 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
415 struct kvm_vcpu
*vcpu
;
419 if (unlikely(vcpu
->arch
.apicv_active
)) {
420 /* need to update RVI */
421 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
422 kvm_x86_ops
->hwapic_irr_update(vcpu
,
423 apic_find_highest_irr(apic
));
425 apic
->irr_pending
= false;
426 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
427 if (apic_search_irr(apic
) != -1)
428 apic
->irr_pending
= true;
432 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
434 struct kvm_vcpu
*vcpu
;
436 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
442 * With APIC virtualization enabled, all caching is disabled
443 * because the processor can modify ISR under the hood. Instead
446 if (unlikely(vcpu
->arch
.apicv_active
))
447 kvm_x86_ops
->hwapic_isr_update(vcpu
, vec
);
450 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
452 * ISR (in service register) bit is set when injecting an interrupt.
453 * The highest vector is injected. Thus the latest bit set matches
454 * the highest bit in ISR.
456 apic
->highest_isr_cache
= vec
;
460 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
465 * Note that isr_count is always 1, and highest_isr_cache
466 * is always -1, with APIC virtualization enabled.
468 if (!apic
->isr_count
)
470 if (likely(apic
->highest_isr_cache
!= -1))
471 return apic
->highest_isr_cache
;
473 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
474 ASSERT(result
== -1 || result
>= 16);
479 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
481 struct kvm_vcpu
*vcpu
;
482 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
488 * We do get here for APIC virtualization enabled if the guest
489 * uses the Hyper-V APIC enlightenment. In this case we may need
490 * to trigger a new interrupt delivery by writing the SVI field;
491 * on the other hand isr_count and highest_isr_cache are unused
492 * and must be left alone.
494 if (unlikely(vcpu
->arch
.apicv_active
))
495 kvm_x86_ops
->hwapic_isr_update(vcpu
,
496 apic_find_highest_isr(apic
));
499 BUG_ON(apic
->isr_count
< 0);
500 apic
->highest_isr_cache
= -1;
504 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
506 /* This may race with setting of irr in __apic_accept_irq() and
507 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
508 * will cause vmexit immediately and the value will be recalculated
509 * on the next vmentry.
511 return apic_find_highest_irr(vcpu
->arch
.apic
);
513 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr
);
515 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
516 int vector
, int level
, int trig_mode
,
517 struct dest_map
*dest_map
);
519 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
520 struct dest_map
*dest_map
)
522 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
524 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
525 irq
->level
, irq
->trig_mode
, dest_map
);
528 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
531 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
535 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
538 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
542 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
544 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
547 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
550 if (pv_eoi_get_user(vcpu
, &val
) < 0)
551 apic_debug("Can't read EOI MSR value: 0x%llx\n",
552 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
556 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
558 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
559 apic_debug("Can't set EOI MSR value: 0x%llx\n",
560 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
563 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
566 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
568 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
569 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
570 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
573 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
576 static int apic_has_interrupt_for_ppr(struct kvm_lapic
*apic
, u32 ppr
)
579 if (kvm_x86_ops
->sync_pir_to_irr
&& apic
->vcpu
->arch
.apicv_active
)
580 highest_irr
= kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
582 highest_irr
= apic_find_highest_irr(apic
);
583 if (highest_irr
== -1 || (highest_irr
& 0xF0) <= ppr
)
588 static bool __apic_update_ppr(struct kvm_lapic
*apic
, u32
*new_ppr
)
590 u32 tpr
, isrv
, ppr
, old_ppr
;
593 old_ppr
= kvm_lapic_get_reg(apic
, APIC_PROCPRI
);
594 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
);
595 isr
= apic_find_highest_isr(apic
);
596 isrv
= (isr
!= -1) ? isr
: 0;
598 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
603 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
604 apic
, ppr
, isr
, isrv
);
608 kvm_lapic_set_reg(apic
, APIC_PROCPRI
, ppr
);
610 return ppr
< old_ppr
;
613 static void apic_update_ppr(struct kvm_lapic
*apic
)
617 if (__apic_update_ppr(apic
, &ppr
) &&
618 apic_has_interrupt_for_ppr(apic
, ppr
) != -1)
619 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
622 void kvm_apic_update_ppr(struct kvm_vcpu
*vcpu
)
624 apic_update_ppr(vcpu
->arch
.apic
);
626 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr
);
628 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
630 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, tpr
);
631 apic_update_ppr(apic
);
634 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
636 return mda
== (apic_x2apic_mode(apic
) ?
637 X2APIC_BROADCAST
: APIC_BROADCAST
);
640 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
642 if (kvm_apic_broadcast(apic
, mda
))
645 if (apic_x2apic_mode(apic
))
646 return mda
== kvm_x2apic_id(apic
);
649 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
650 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
651 * this allows unique addressing of VCPUs with APIC ID over 0xff.
652 * The 0xff condition is needed because writeable xAPIC ID.
654 if (kvm_x2apic_id(apic
) > 0xff && mda
== kvm_x2apic_id(apic
))
657 return mda
== kvm_xapic_id(apic
);
660 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
664 if (kvm_apic_broadcast(apic
, mda
))
667 logical_id
= kvm_lapic_get_reg(apic
, APIC_LDR
);
669 if (apic_x2apic_mode(apic
))
670 return ((logical_id
>> 16) == (mda
>> 16))
671 && (logical_id
& mda
& 0xffff) != 0;
673 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
675 switch (kvm_lapic_get_reg(apic
, APIC_DFR
)) {
677 return (logical_id
& mda
) != 0;
678 case APIC_DFR_CLUSTER
:
679 return ((logical_id
>> 4) == (mda
>> 4))
680 && (logical_id
& mda
& 0xf) != 0;
682 apic_debug("Bad DFR vcpu %d: %08x\n",
683 apic
->vcpu
->vcpu_id
, kvm_lapic_get_reg(apic
, APIC_DFR
));
688 /* The KVM local APIC implementation has two quirks:
690 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
691 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
692 * KVM doesn't do that aliasing.
694 * - in-kernel IOAPIC messages have to be delivered directly to
695 * x2APIC, because the kernel does not support interrupt remapping.
696 * In order to support broadcast without interrupt remapping, x2APIC
697 * rewrites the destination of non-IPI messages from APIC_BROADCAST
698 * to X2APIC_BROADCAST.
700 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
701 * important when userspace wants to use x2APIC-format MSIs, because
702 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
704 static u32
kvm_apic_mda(struct kvm_vcpu
*vcpu
, unsigned int dest_id
,
705 struct kvm_lapic
*source
, struct kvm_lapic
*target
)
707 bool ipi
= source
!= NULL
;
709 if (!vcpu
->kvm
->arch
.x2apic_broadcast_quirk_disabled
&&
710 !ipi
&& dest_id
== APIC_BROADCAST
&& apic_x2apic_mode(target
))
711 return X2APIC_BROADCAST
;
716 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
717 int short_hand
, unsigned int dest
, int dest_mode
)
719 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
720 u32 mda
= kvm_apic_mda(vcpu
, dest
, source
, target
);
722 apic_debug("target %p, source %p, dest 0x%x, "
723 "dest_mode 0x%x, short_hand 0x%x\n",
724 target
, source
, dest
, dest_mode
, short_hand
);
727 switch (short_hand
) {
728 case APIC_DEST_NOSHORT
:
729 if (dest_mode
== APIC_DEST_PHYSICAL
)
730 return kvm_apic_match_physical_addr(target
, mda
);
732 return kvm_apic_match_logical_addr(target
, mda
);
734 return target
== source
;
735 case APIC_DEST_ALLINC
:
737 case APIC_DEST_ALLBUT
:
738 return target
!= source
;
740 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
745 EXPORT_SYMBOL_GPL(kvm_apic_match_dest
);
747 int kvm_vector_to_index(u32 vector
, u32 dest_vcpus
,
748 const unsigned long *bitmap
, u32 bitmap_size
)
753 mod
= vector
% dest_vcpus
;
755 for (i
= 0; i
<= mod
; i
++) {
756 idx
= find_next_bit(bitmap
, bitmap_size
, idx
+ 1);
757 BUG_ON(idx
== bitmap_size
);
763 static void kvm_apic_disabled_lapic_found(struct kvm
*kvm
)
765 if (!kvm
->arch
.disabled_lapic_found
) {
766 kvm
->arch
.disabled_lapic_found
= true;
768 "Disabled LAPIC found during irq injection\n");
772 static bool kvm_apic_is_broadcast_dest(struct kvm
*kvm
, struct kvm_lapic
**src
,
773 struct kvm_lapic_irq
*irq
, struct kvm_apic_map
*map
)
775 if (kvm
->arch
.x2apic_broadcast_quirk_disabled
) {
776 if ((irq
->dest_id
== APIC_BROADCAST
&&
777 map
->mode
!= KVM_APIC_MODE_X2APIC
))
779 if (irq
->dest_id
== X2APIC_BROADCAST
)
782 bool x2apic_ipi
= src
&& *src
&& apic_x2apic_mode(*src
);
783 if (irq
->dest_id
== (x2apic_ipi
?
784 X2APIC_BROADCAST
: APIC_BROADCAST
))
791 /* Return true if the interrupt can be handled by using *bitmap as index mask
792 * for valid destinations in *dst array.
793 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
794 * Note: we may have zero kvm_lapic destinations when we return true, which
795 * means that the interrupt should be dropped. In this case, *bitmap would be
796 * zero and *dst undefined.
798 static inline bool kvm_apic_map_get_dest_lapic(struct kvm
*kvm
,
799 struct kvm_lapic
**src
, struct kvm_lapic_irq
*irq
,
800 struct kvm_apic_map
*map
, struct kvm_lapic
***dst
,
801 unsigned long *bitmap
)
805 if (irq
->shorthand
== APIC_DEST_SELF
&& src
) {
809 } else if (irq
->shorthand
)
812 if (!map
|| kvm_apic_is_broadcast_dest(kvm
, src
, irq
, map
))
815 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
816 if (irq
->dest_id
> map
->max_apic_id
) {
819 *dst
= &map
->phys_map
[irq
->dest_id
];
826 if (!kvm_apic_map_get_logical_dest(map
, irq
->dest_id
, dst
,
830 if (!kvm_lowest_prio_delivery(irq
))
833 if (!kvm_vector_hashing_enabled()) {
835 for_each_set_bit(i
, bitmap
, 16) {
840 else if (kvm_apic_compare_prio((*dst
)[i
]->vcpu
,
841 (*dst
)[lowest
]->vcpu
) < 0)
848 lowest
= kvm_vector_to_index(irq
->vector
, hweight16(*bitmap
),
851 if (!(*dst
)[lowest
]) {
852 kvm_apic_disabled_lapic_found(kvm
);
858 *bitmap
= (lowest
>= 0) ? 1 << lowest
: 0;
863 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
864 struct kvm_lapic_irq
*irq
, int *r
, struct dest_map
*dest_map
)
866 struct kvm_apic_map
*map
;
867 unsigned long bitmap
;
868 struct kvm_lapic
**dst
= NULL
;
874 if (irq
->shorthand
== APIC_DEST_SELF
) {
875 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
880 map
= rcu_dereference(kvm
->arch
.apic_map
);
882 ret
= kvm_apic_map_get_dest_lapic(kvm
, &src
, irq
, map
, &dst
, &bitmap
);
884 for_each_set_bit(i
, &bitmap
, 16) {
889 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
897 * This routine tries to handler interrupts in posted mode, here is how
898 * it deals with different cases:
899 * - For single-destination interrupts, handle it in posted mode
900 * - Else if vector hashing is enabled and it is a lowest-priority
901 * interrupt, handle it in posted mode and use the following mechanism
902 * to find the destinaiton vCPU.
903 * 1. For lowest-priority interrupts, store all the possible
904 * destination vCPUs in an array.
905 * 2. Use "guest vector % max number of destination vCPUs" to find
906 * the right destination vCPU in the array for the lowest-priority
908 * - Otherwise, use remapped mode to inject the interrupt.
910 bool kvm_intr_is_single_vcpu_fast(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
911 struct kvm_vcpu
**dest_vcpu
)
913 struct kvm_apic_map
*map
;
914 unsigned long bitmap
;
915 struct kvm_lapic
**dst
= NULL
;
922 map
= rcu_dereference(kvm
->arch
.apic_map
);
924 if (kvm_apic_map_get_dest_lapic(kvm
, NULL
, irq
, map
, &dst
, &bitmap
) &&
925 hweight16(bitmap
) == 1) {
926 unsigned long i
= find_first_bit(&bitmap
, 16);
929 *dest_vcpu
= dst
[i
]->vcpu
;
939 * Add a pending IRQ into lapic.
940 * Return 1 if successfully added and 0 if discarded.
942 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
943 int vector
, int level
, int trig_mode
,
944 struct dest_map
*dest_map
)
947 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
949 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
951 switch (delivery_mode
) {
953 vcpu
->arch
.apic_arb_prio
++;
955 if (unlikely(trig_mode
&& !level
))
958 /* FIXME add logic for vcpu on reset */
959 if (unlikely(!apic_enabled(apic
)))
965 __set_bit(vcpu
->vcpu_id
, dest_map
->map
);
966 dest_map
->vectors
[vcpu
->vcpu_id
] = vector
;
969 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
) != !!trig_mode
) {
971 kvm_lapic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
973 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
976 if (vcpu
->arch
.apicv_active
)
977 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
979 kvm_lapic_set_irr(vector
, apic
);
981 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
988 vcpu
->arch
.pv
.pv_unhalted
= 1;
989 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
995 kvm_make_request(KVM_REQ_SMI
, vcpu
);
1001 kvm_inject_nmi(vcpu
);
1002 kvm_vcpu_kick(vcpu
);
1006 if (!trig_mode
|| level
) {
1008 /* assumes that there are only KVM_APIC_INIT/SIPI */
1009 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
1010 /* make sure pending_events is visible before sending
1013 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1014 kvm_vcpu_kick(vcpu
);
1016 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1021 case APIC_DM_STARTUP
:
1022 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1023 vcpu
->vcpu_id
, vector
);
1025 apic
->sipi_vector
= vector
;
1026 /* make sure sipi_vector is visible for the receiver */
1028 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
1029 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1030 kvm_vcpu_kick(vcpu
);
1033 case APIC_DM_EXTINT
:
1035 * Should only be called by kvm_apic_local_deliver() with LVT0,
1036 * before NMI watchdog was enabled. Already handled by
1037 * kvm_apic_accept_pic_intr().
1042 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
1049 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
1051 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
1054 static bool kvm_ioapic_handles_vector(struct kvm_lapic
*apic
, int vector
)
1056 return test_bit(vector
, apic
->vcpu
->arch
.ioapic_handled_vectors
);
1059 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
1063 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1064 if (!kvm_ioapic_handles_vector(apic
, vector
))
1067 /* Request a KVM exit to inform the userspace IOAPIC. */
1068 if (irqchip_split(apic
->vcpu
->kvm
)) {
1069 apic
->vcpu
->arch
.pending_ioapic_eoi
= vector
;
1070 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT
, apic
->vcpu
);
1074 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
1075 trigger_mode
= IOAPIC_LEVEL_TRIG
;
1077 trigger_mode
= IOAPIC_EDGE_TRIG
;
1079 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
1082 static int apic_set_eoi(struct kvm_lapic
*apic
)
1084 int vector
= apic_find_highest_isr(apic
);
1086 trace_kvm_eoi(apic
, vector
);
1089 * Not every write EOI will has corresponding ISR,
1090 * one example is when Kernel check timer on setup_IO_APIC
1095 apic_clear_isr(vector
, apic
);
1096 apic_update_ppr(apic
);
1098 if (test_bit(vector
, vcpu_to_synic(apic
->vcpu
)->vec_bitmap
))
1099 kvm_hv_synic_send_eoi(apic
->vcpu
, vector
);
1101 kvm_ioapic_send_eoi(apic
, vector
);
1102 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1107 * this interface assumes a trap-like exit, which has already finished
1108 * desired side effect including vISR and vPPR update.
1110 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
1112 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1114 trace_kvm_eoi(apic
, vector
);
1116 kvm_ioapic_send_eoi(apic
, vector
);
1117 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1119 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
1121 static void apic_send_ipi(struct kvm_lapic
*apic
)
1123 u32 icr_low
= kvm_lapic_get_reg(apic
, APIC_ICR
);
1124 u32 icr_high
= kvm_lapic_get_reg(apic
, APIC_ICR2
);
1125 struct kvm_lapic_irq irq
;
1127 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
1128 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
1129 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
1130 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
1131 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
1132 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
1133 irq
.msi_redir_hint
= false;
1134 if (apic_x2apic_mode(apic
))
1135 irq
.dest_id
= icr_high
;
1137 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
1139 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
1141 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1142 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1143 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1144 "msi_redir_hint 0x%x\n",
1145 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
1146 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
1147 irq
.vector
, irq
.msi_redir_hint
);
1149 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
1152 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
1154 ktime_t remaining
, now
;
1158 ASSERT(apic
!= NULL
);
1160 /* if initial count is 0, current count should also be 0 */
1161 if (kvm_lapic_get_reg(apic
, APIC_TMICT
) == 0 ||
1162 apic
->lapic_timer
.period
== 0)
1166 remaining
= ktime_sub(apic
->lapic_timer
.target_expiration
, now
);
1167 if (ktime_to_ns(remaining
) < 0)
1170 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
1171 tmcct
= div64_u64(ns
,
1172 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
1177 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1179 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1180 struct kvm_run
*run
= vcpu
->run
;
1182 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
1183 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
1184 run
->tpr_access
.is_write
= write
;
1187 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1189 if (apic
->vcpu
->arch
.tpr_access_reporting
)
1190 __report_tpr_access(apic
, write
);
1193 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
1197 if (offset
>= LAPIC_MMIO_LENGTH
)
1202 apic_debug("Access APIC ARBPRI register which is for P6\n");
1205 case APIC_TMCCT
: /* Timer CCR */
1206 if (apic_lvtt_tscdeadline(apic
))
1209 val
= apic_get_tmcct(apic
);
1212 apic_update_ppr(apic
);
1213 val
= kvm_lapic_get_reg(apic
, offset
);
1216 report_tpr_access(apic
, false);
1219 val
= kvm_lapic_get_reg(apic
, offset
);
1226 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1228 return container_of(dev
, struct kvm_lapic
, dev
);
1231 int kvm_lapic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1234 unsigned char alignment
= offset
& 0xf;
1236 /* this bitmask has a bit cleared for each reserved register */
1237 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1239 if ((alignment
+ len
) > 4) {
1240 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1245 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1246 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1251 result
= __apic_read(apic
, offset
& ~0xf);
1253 trace_kvm_apic_read(offset
, result
);
1259 memcpy(data
, (char *)&result
+ alignment
, len
);
1262 printk(KERN_ERR
"Local APIC read with len = %x, "
1263 "should be 1,2, or 4 instead\n", len
);
1268 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read
);
1270 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1272 return kvm_apic_hw_enabled(apic
) &&
1273 addr
>= apic
->base_address
&&
1274 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1277 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1278 gpa_t address
, int len
, void *data
)
1280 struct kvm_lapic
*apic
= to_lapic(this);
1281 u32 offset
= address
- apic
->base_address
;
1283 if (!apic_mmio_in_range(apic
, address
))
1286 kvm_lapic_reg_read(apic
, offset
, len
, data
);
1291 static void update_divide_count(struct kvm_lapic
*apic
)
1293 u32 tmp1
, tmp2
, tdcr
;
1295 tdcr
= kvm_lapic_get_reg(apic
, APIC_TDCR
);
1297 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1298 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1300 apic_debug("timer divide count is 0x%x\n",
1301 apic
->divide_count
);
1304 static void limit_periodic_timer_frequency(struct kvm_lapic
*apic
)
1307 * Do not allow the guest to program periodic timers with small
1308 * interval, since the hrtimers are not throttled by the host
1311 if (apic_lvtt_period(apic
) && apic
->lapic_timer
.period
) {
1312 s64 min_period
= min_timer_period_us
* 1000LL;
1314 if (apic
->lapic_timer
.period
< min_period
) {
1315 pr_info_ratelimited(
1316 "kvm: vcpu %i: requested %lld ns "
1317 "lapic timer period limited to %lld ns\n",
1318 apic
->vcpu
->vcpu_id
,
1319 apic
->lapic_timer
.period
, min_period
);
1320 apic
->lapic_timer
.period
= min_period
;
1325 static void apic_update_lvtt(struct kvm_lapic
*apic
)
1327 u32 timer_mode
= kvm_lapic_get_reg(apic
, APIC_LVTT
) &
1328 apic
->lapic_timer
.timer_mode_mask
;
1330 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1331 if (apic_lvtt_tscdeadline(apic
) != (timer_mode
==
1332 APIC_LVT_TIMER_TSCDEADLINE
)) {
1333 kvm_lapic_set_reg(apic
, APIC_TMICT
, 0);
1334 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1336 apic
->lapic_timer
.timer_mode
= timer_mode
;
1337 limit_periodic_timer_frequency(apic
);
1341 static void apic_timer_expired(struct kvm_lapic
*apic
)
1343 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1344 struct swait_queue_head
*q
= &vcpu
->wq
;
1345 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1347 if (atomic_read(&apic
->lapic_timer
.pending
))
1350 atomic_inc(&apic
->lapic_timer
.pending
);
1351 kvm_set_pending_timer(vcpu
);
1354 * For x86, the atomic_inc() is serialized, thus
1355 * using swait_active() is safe.
1357 if (swait_active(q
))
1360 if (apic_lvtt_tscdeadline(apic
))
1361 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1365 * On APICv, this test will cause a busy wait
1366 * during a higher-priority task.
1369 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1371 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1372 u32 reg
= kvm_lapic_get_reg(apic
, APIC_LVTT
);
1374 if (kvm_apic_hw_enabled(apic
)) {
1375 int vec
= reg
& APIC_VECTOR_MASK
;
1376 void *bitmap
= apic
->regs
+ APIC_ISR
;
1378 if (vcpu
->arch
.apicv_active
)
1379 bitmap
= apic
->regs
+ APIC_IRR
;
1381 if (apic_test_vector(vec
, bitmap
))
1387 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1389 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1390 u64 guest_tsc
, tsc_deadline
;
1392 if (!lapic_in_kernel(vcpu
))
1395 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1398 if (!lapic_timer_int_injected(vcpu
))
1401 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1402 apic
->lapic_timer
.expired_tscdeadline
= 0;
1403 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1404 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1406 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1407 if (guest_tsc
< tsc_deadline
)
1408 __delay(min(tsc_deadline
- guest_tsc
,
1409 nsec_to_cycles(vcpu
, lapic_timer_advance_ns
)));
1412 static void start_sw_tscdeadline(struct kvm_lapic
*apic
)
1414 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1417 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1418 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1419 unsigned long flags
;
1422 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1425 local_irq_save(flags
);
1428 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1429 if (likely(tscdeadline
> guest_tsc
)) {
1430 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1431 do_div(ns
, this_tsc_khz
);
1432 expire
= ktime_add_ns(now
, ns
);
1433 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1434 hrtimer_start(&apic
->lapic_timer
.timer
,
1435 expire
, HRTIMER_MODE_ABS_PINNED
);
1437 apic_timer_expired(apic
);
1439 local_irq_restore(flags
);
1442 static void start_sw_period(struct kvm_lapic
*apic
)
1444 if (!apic
->lapic_timer
.period
)
1447 if (apic_lvtt_oneshot(apic
) &&
1448 ktime_after(ktime_get(),
1449 apic
->lapic_timer
.target_expiration
)) {
1450 apic_timer_expired(apic
);
1454 hrtimer_start(&apic
->lapic_timer
.timer
,
1455 apic
->lapic_timer
.target_expiration
,
1456 HRTIMER_MODE_ABS_PINNED
);
1459 static bool set_target_expiration(struct kvm_lapic
*apic
)
1465 apic
->lapic_timer
.period
= (u64
)kvm_lapic_get_reg(apic
, APIC_TMICT
)
1466 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1468 if (!apic
->lapic_timer
.period
)
1471 limit_periodic_timer_frequency(apic
);
1473 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1475 "timer initial count 0x%x, period %lldns, "
1476 "expire @ 0x%016" PRIx64
".\n", __func__
,
1477 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1478 kvm_lapic_get_reg(apic
, APIC_TMICT
),
1479 apic
->lapic_timer
.period
,
1480 ktime_to_ns(ktime_add_ns(now
,
1481 apic
->lapic_timer
.period
)));
1483 apic
->lapic_timer
.tscdeadline
= kvm_read_l1_tsc(apic
->vcpu
, tscl
) +
1484 nsec_to_cycles(apic
->vcpu
, apic
->lapic_timer
.period
);
1485 apic
->lapic_timer
.target_expiration
= ktime_add_ns(now
, apic
->lapic_timer
.period
);
1490 static void advance_periodic_target_expiration(struct kvm_lapic
*apic
)
1492 apic
->lapic_timer
.tscdeadline
+=
1493 nsec_to_cycles(apic
->vcpu
, apic
->lapic_timer
.period
);
1494 apic
->lapic_timer
.target_expiration
=
1495 ktime_add_ns(apic
->lapic_timer
.target_expiration
,
1496 apic
->lapic_timer
.period
);
1499 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu
*vcpu
)
1501 if (!lapic_in_kernel(vcpu
))
1504 return vcpu
->arch
.apic
->lapic_timer
.hv_timer_in_use
;
1506 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use
);
1508 static void cancel_hv_timer(struct kvm_lapic
*apic
)
1510 WARN_ON(preemptible());
1511 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1512 kvm_x86_ops
->cancel_hv_timer(apic
->vcpu
);
1513 apic
->lapic_timer
.hv_timer_in_use
= false;
1516 static bool start_hv_timer(struct kvm_lapic
*apic
)
1518 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1521 WARN_ON(preemptible());
1522 if (!kvm_x86_ops
->set_hv_timer
)
1525 if (!apic_lvtt_period(apic
) && atomic_read(&ktimer
->pending
))
1528 r
= kvm_x86_ops
->set_hv_timer(apic
->vcpu
, ktimer
->tscdeadline
);
1532 ktimer
->hv_timer_in_use
= true;
1533 hrtimer_cancel(&ktimer
->timer
);
1536 * Also recheck ktimer->pending, in case the sw timer triggered in
1537 * the window. For periodic timer, leave the hv timer running for
1538 * simplicity, and the deadline will be recomputed on the next vmexit.
1540 if (!apic_lvtt_period(apic
) && (r
|| atomic_read(&ktimer
->pending
))) {
1542 apic_timer_expired(apic
);
1546 trace_kvm_hv_timer_state(apic
->vcpu
->vcpu_id
, true);
1550 static void start_sw_timer(struct kvm_lapic
*apic
)
1552 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1554 WARN_ON(preemptible());
1555 if (apic
->lapic_timer
.hv_timer_in_use
)
1556 cancel_hv_timer(apic
);
1557 if (!apic_lvtt_period(apic
) && atomic_read(&ktimer
->pending
))
1560 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1561 start_sw_period(apic
);
1562 else if (apic_lvtt_tscdeadline(apic
))
1563 start_sw_tscdeadline(apic
);
1564 trace_kvm_hv_timer_state(apic
->vcpu
->vcpu_id
, false);
1567 static void restart_apic_timer(struct kvm_lapic
*apic
)
1570 if (!start_hv_timer(apic
))
1571 start_sw_timer(apic
);
1575 void kvm_lapic_expired_hv_timer(struct kvm_vcpu
*vcpu
)
1577 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1580 /* If the preempt notifier has already run, it also called apic_timer_expired */
1581 if (!apic
->lapic_timer
.hv_timer_in_use
)
1583 WARN_ON(swait_active(&vcpu
->wq
));
1584 cancel_hv_timer(apic
);
1585 apic_timer_expired(apic
);
1587 if (apic_lvtt_period(apic
) && apic
->lapic_timer
.period
) {
1588 advance_periodic_target_expiration(apic
);
1589 restart_apic_timer(apic
);
1594 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer
);
1596 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu
*vcpu
)
1598 restart_apic_timer(vcpu
->arch
.apic
);
1600 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer
);
1602 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu
*vcpu
)
1604 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1607 /* Possibly the TSC deadline timer is not enabled yet */
1608 if (apic
->lapic_timer
.hv_timer_in_use
)
1609 start_sw_timer(apic
);
1612 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer
);
1614 void kvm_lapic_restart_hv_timer(struct kvm_vcpu
*vcpu
)
1616 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1618 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1619 restart_apic_timer(apic
);
1622 static void start_apic_timer(struct kvm_lapic
*apic
)
1624 atomic_set(&apic
->lapic_timer
.pending
, 0);
1626 if ((apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1627 && !set_target_expiration(apic
))
1630 restart_apic_timer(apic
);
1633 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1635 bool lvt0_in_nmi_mode
= apic_lvt_nmi_mode(lvt0_val
);
1637 if (apic
->lvt0_in_nmi_mode
!= lvt0_in_nmi_mode
) {
1638 apic
->lvt0_in_nmi_mode
= lvt0_in_nmi_mode
;
1639 if (lvt0_in_nmi_mode
) {
1640 apic_debug("Receive NMI setting on APIC_LVT0 "
1641 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1642 atomic_inc(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1644 atomic_dec(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1648 int kvm_lapic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1652 trace_kvm_apic_write(reg
, val
);
1655 case APIC_ID
: /* Local APIC ID */
1656 if (!apic_x2apic_mode(apic
))
1657 kvm_apic_set_xapic_id(apic
, val
>> 24);
1663 report_tpr_access(apic
, true);
1664 apic_set_tpr(apic
, val
& 0xff);
1672 if (!apic_x2apic_mode(apic
))
1673 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1679 if (!apic_x2apic_mode(apic
)) {
1680 kvm_lapic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1681 recalculate_apic_map(apic
->vcpu
->kvm
);
1688 if (kvm_lapic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1689 mask
|= APIC_SPIV_DIRECTED_EOI
;
1690 apic_set_spiv(apic
, val
& mask
);
1691 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1695 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++) {
1696 lvt_val
= kvm_lapic_get_reg(apic
,
1697 APIC_LVTT
+ 0x10 * i
);
1698 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1699 lvt_val
| APIC_LVT_MASKED
);
1701 apic_update_lvtt(apic
);
1702 atomic_set(&apic
->lapic_timer
.pending
, 0);
1708 /* No delay here, so we always clear the pending bit */
1709 kvm_lapic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1710 apic_send_ipi(apic
);
1714 if (!apic_x2apic_mode(apic
))
1716 kvm_lapic_set_reg(apic
, APIC_ICR2
, val
);
1720 apic_manage_nmi_watchdog(apic
, val
);
1725 /* TODO: Check vector */
1726 if (!kvm_apic_sw_enabled(apic
))
1727 val
|= APIC_LVT_MASKED
;
1729 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1730 kvm_lapic_set_reg(apic
, reg
, val
);
1735 if (!kvm_apic_sw_enabled(apic
))
1736 val
|= APIC_LVT_MASKED
;
1737 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1738 kvm_lapic_set_reg(apic
, APIC_LVTT
, val
);
1739 apic_update_lvtt(apic
);
1743 if (apic_lvtt_tscdeadline(apic
))
1746 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1747 kvm_lapic_set_reg(apic
, APIC_TMICT
, val
);
1748 start_apic_timer(apic
);
1753 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1754 kvm_lapic_set_reg(apic
, APIC_TDCR
, val
);
1755 update_divide_count(apic
);
1759 if (apic_x2apic_mode(apic
) && val
!= 0) {
1760 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1766 if (apic_x2apic_mode(apic
)) {
1767 kvm_lapic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1776 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1779 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write
);
1781 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1782 gpa_t address
, int len
, const void *data
)
1784 struct kvm_lapic
*apic
= to_lapic(this);
1785 unsigned int offset
= address
- apic
->base_address
;
1788 if (!apic_mmio_in_range(apic
, address
))
1792 * APIC register must be aligned on 128-bits boundary.
1793 * 32/64/128 bits registers must be accessed thru 32 bits.
1796 if (len
!= 4 || (offset
& 0xf)) {
1797 /* Don't shout loud, $infamous_os would cause only noise. */
1798 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1804 /* too common printing */
1805 if (offset
!= APIC_EOI
)
1806 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1807 "0x%x\n", __func__
, offset
, len
, val
);
1809 kvm_lapic_reg_write(apic
, offset
& 0xff0, val
);
1814 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1816 kvm_lapic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1818 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1820 /* emulate APIC access in a trap manner */
1821 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1825 /* hw has done the conditional check and inst decode */
1828 kvm_lapic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1830 /* TODO: optimize to just emulate side effect w/o one more write */
1831 kvm_lapic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1833 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1835 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1837 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1839 if (!vcpu
->arch
.apic
)
1842 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1844 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1845 static_key_slow_dec_deferred(&apic_hw_disabled
);
1847 if (!apic
->sw_enabled
)
1848 static_key_slow_dec_deferred(&apic_sw_disabled
);
1851 free_page((unsigned long)apic
->regs
);
1857 *----------------------------------------------------------------------
1859 *----------------------------------------------------------------------
1861 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1863 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1865 if (!lapic_in_kernel(vcpu
) ||
1866 !apic_lvtt_tscdeadline(apic
))
1869 return apic
->lapic_timer
.tscdeadline
;
1872 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1874 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1876 if (!lapic_in_kernel(vcpu
) || apic_lvtt_oneshot(apic
) ||
1877 apic_lvtt_period(apic
))
1880 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1881 apic
->lapic_timer
.tscdeadline
= data
;
1882 start_apic_timer(apic
);
1885 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1887 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1889 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1890 | (kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 4));
1893 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1897 tpr
= (u64
) kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1899 return (tpr
& 0xf0) >> 4;
1902 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1904 u64 old_value
= vcpu
->arch
.apic_base
;
1905 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1908 value
|= MSR_IA32_APICBASE_BSP
;
1910 vcpu
->arch
.apic_base
= value
;
1912 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
)
1913 kvm_update_cpuid(vcpu
);
1918 /* update jump label if enable bit changes */
1919 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1920 if (value
& MSR_IA32_APICBASE_ENABLE
) {
1921 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
1922 static_key_slow_dec_deferred(&apic_hw_disabled
);
1924 static_key_slow_inc(&apic_hw_disabled
.key
);
1925 recalculate_apic_map(vcpu
->kvm
);
1929 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1930 if (value
& X2APIC_ENABLE
) {
1931 kvm_apic_set_x2apic_id(apic
, vcpu
->vcpu_id
);
1932 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1934 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1937 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1938 MSR_IA32_APICBASE_BASE
;
1940 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1941 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1942 pr_warn_once("APIC base relocation is unsupported by KVM");
1944 /* with FSB delivery interrupt, we can restart APIC functionality */
1945 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1946 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1950 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1952 struct kvm_lapic
*apic
;
1955 apic_debug("%s\n", __func__
);
1958 apic
= vcpu
->arch
.apic
;
1959 ASSERT(apic
!= NULL
);
1961 /* Stop the timer in case it's a reset to an active apic */
1962 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1965 kvm_lapic_set_base(vcpu
, APIC_DEFAULT_PHYS_BASE
|
1966 MSR_IA32_APICBASE_ENABLE
);
1967 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
1969 kvm_apic_set_version(apic
->vcpu
);
1971 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++)
1972 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1973 apic_update_lvtt(apic
);
1974 if (kvm_vcpu_is_reset_bsp(vcpu
) &&
1975 kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_LINT0_REENABLED
))
1976 kvm_lapic_set_reg(apic
, APIC_LVT0
,
1977 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1978 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
1980 kvm_lapic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1981 apic_set_spiv(apic
, 0xff);
1982 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, 0);
1983 if (!apic_x2apic_mode(apic
))
1984 kvm_apic_set_ldr(apic
, 0);
1985 kvm_lapic_set_reg(apic
, APIC_ESR
, 0);
1986 kvm_lapic_set_reg(apic
, APIC_ICR
, 0);
1987 kvm_lapic_set_reg(apic
, APIC_ICR2
, 0);
1988 kvm_lapic_set_reg(apic
, APIC_TDCR
, 0);
1989 kvm_lapic_set_reg(apic
, APIC_TMICT
, 0);
1990 for (i
= 0; i
< 8; i
++) {
1991 kvm_lapic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1992 kvm_lapic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1993 kvm_lapic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1995 apic
->irr_pending
= vcpu
->arch
.apicv_active
;
1996 apic
->isr_count
= vcpu
->arch
.apicv_active
? 1 : 0;
1997 apic
->highest_isr_cache
= -1;
1998 update_divide_count(apic
);
1999 atomic_set(&apic
->lapic_timer
.pending
, 0);
2000 if (kvm_vcpu_is_bsp(vcpu
))
2001 kvm_lapic_set_base(vcpu
,
2002 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
2003 vcpu
->arch
.pv_eoi
.msr_val
= 0;
2004 apic_update_ppr(apic
);
2006 vcpu
->arch
.apic_arb_prio
= 0;
2007 vcpu
->arch
.apic_attention
= 0;
2009 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2010 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
2011 vcpu
, kvm_lapic_get_reg(apic
, APIC_ID
),
2012 vcpu
->arch
.apic_base
, apic
->base_address
);
2016 *----------------------------------------------------------------------
2018 *----------------------------------------------------------------------
2021 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
2023 return apic_lvtt_period(apic
);
2026 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
2028 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2030 if (apic_enabled(apic
) && apic_lvt_enabled(apic
, APIC_LVTT
))
2031 return atomic_read(&apic
->lapic_timer
.pending
);
2036 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
2038 u32 reg
= kvm_lapic_get_reg(apic
, lvt_type
);
2039 int vector
, mode
, trig_mode
;
2041 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
2042 vector
= reg
& APIC_VECTOR_MASK
;
2043 mode
= reg
& APIC_MODE_MASK
;
2044 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
2045 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
2051 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
2053 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2056 kvm_apic_local_deliver(apic
, APIC_LVT0
);
2059 static const struct kvm_io_device_ops apic_mmio_ops
= {
2060 .read
= apic_mmio_read
,
2061 .write
= apic_mmio_write
,
2064 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
2066 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
2067 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
2069 apic_timer_expired(apic
);
2071 if (lapic_is_periodic(apic
)) {
2072 advance_periodic_target_expiration(apic
);
2073 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
2074 return HRTIMER_RESTART
;
2076 return HRTIMER_NORESTART
;
2079 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
2081 struct kvm_lapic
*apic
;
2083 ASSERT(vcpu
!= NULL
);
2084 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
2086 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
2090 vcpu
->arch
.apic
= apic
;
2092 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
2094 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
2096 goto nomem_free_apic
;
2100 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
2101 HRTIMER_MODE_ABS_PINNED
);
2102 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
2105 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2106 * thinking that APIC satet has changed.
2108 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
2109 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
2110 kvm_lapic_reset(vcpu
, false);
2111 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
2120 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
2122 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2125 if (!apic_enabled(apic
))
2128 __apic_update_ppr(apic
, &ppr
);
2129 return apic_has_interrupt_for_ppr(apic
, ppr
);
2132 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
2134 u32 lvt0
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
2137 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
2139 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
2140 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
2145 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
2147 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2149 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
2150 kvm_apic_local_deliver(apic
, APIC_LVTT
);
2151 if (apic_lvtt_tscdeadline(apic
))
2152 apic
->lapic_timer
.tscdeadline
= 0;
2153 if (apic_lvtt_oneshot(apic
)) {
2154 apic
->lapic_timer
.tscdeadline
= 0;
2155 apic
->lapic_timer
.target_expiration
= 0;
2157 atomic_set(&apic
->lapic_timer
.pending
, 0);
2161 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
2163 int vector
= kvm_apic_has_interrupt(vcpu
);
2164 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2171 * We get here even with APIC virtualization enabled, if doing
2172 * nested virtualization and L1 runs with the "acknowledge interrupt
2173 * on exit" mode. Then we cannot inject the interrupt via RVI,
2174 * because the process would deliver it through the IDT.
2177 apic_clear_irr(vector
, apic
);
2178 if (test_bit(vector
, vcpu_to_synic(vcpu
)->auto_eoi_bitmap
)) {
2180 * For auto-EOI interrupts, there might be another pending
2181 * interrupt above PPR, so check whether to raise another
2184 apic_update_ppr(apic
);
2187 * For normal interrupts, PPR has been raised and there cannot
2188 * be a higher-priority pending interrupt---except if there was
2189 * a concurrent interrupt injection, but that would have
2190 * triggered KVM_REQ_EVENT already.
2192 apic_set_isr(vector
, apic
);
2193 __apic_update_ppr(apic
, &ppr
);
2199 static int kvm_apic_state_fixup(struct kvm_vcpu
*vcpu
,
2200 struct kvm_lapic_state
*s
, bool set
)
2202 if (apic_x2apic_mode(vcpu
->arch
.apic
)) {
2203 u32
*id
= (u32
*)(s
->regs
+ APIC_ID
);
2205 if (vcpu
->kvm
->arch
.x2apic_format
) {
2206 if (*id
!= vcpu
->vcpu_id
)
2219 int kvm_apic_get_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2221 memcpy(s
->regs
, vcpu
->arch
.apic
->regs
, sizeof(*s
));
2222 return kvm_apic_state_fixup(vcpu
, s
, false);
2225 int kvm_apic_set_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2227 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2231 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
2232 /* set SPIV separately to get count of SW disabled APICs right */
2233 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
2235 r
= kvm_apic_state_fixup(vcpu
, s
, true);
2238 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
2240 recalculate_apic_map(vcpu
->kvm
);
2241 kvm_apic_set_version(vcpu
);
2243 apic_update_ppr(apic
);
2244 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2245 apic_update_lvtt(apic
);
2246 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
2247 update_divide_count(apic
);
2248 start_apic_timer(apic
);
2249 apic
->irr_pending
= true;
2250 apic
->isr_count
= vcpu
->arch
.apicv_active
?
2251 1 : count_vectors(apic
->regs
+ APIC_ISR
);
2252 apic
->highest_isr_cache
= -1;
2253 if (vcpu
->arch
.apicv_active
) {
2254 kvm_x86_ops
->apicv_post_state_restore(vcpu
);
2255 kvm_x86_ops
->hwapic_irr_update(vcpu
,
2256 apic_find_highest_irr(apic
));
2257 kvm_x86_ops
->hwapic_isr_update(vcpu
,
2258 apic_find_highest_isr(apic
));
2260 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2261 if (ioapic_in_kernel(vcpu
->kvm
))
2262 kvm_rtc_eoi_tracking_restore_one(vcpu
);
2264 vcpu
->arch
.apic_arb_prio
= 0;
2269 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
2271 struct hrtimer
*timer
;
2273 if (!lapic_in_kernel(vcpu
))
2276 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
2277 if (hrtimer_cancel(timer
))
2278 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS_PINNED
);
2282 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2284 * Detect whether guest triggered PV EOI since the
2285 * last entry. If yes, set EOI on guests's behalf.
2286 * Clear PV EOI in guest memory in any case.
2288 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
2289 struct kvm_lapic
*apic
)
2294 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2295 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2297 * KVM_APIC_PV_EOI_PENDING is unset:
2298 * -> host disabled PV EOI.
2299 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2300 * -> host enabled PV EOI, guest did not execute EOI yet.
2301 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2302 * -> host enabled PV EOI, guest executed EOI.
2304 BUG_ON(!pv_eoi_enabled(vcpu
));
2305 pending
= pv_eoi_get_pending(vcpu
);
2307 * Clear pending bit in any case: it will be set again on vmentry.
2308 * While this might not be ideal from performance point of view,
2309 * this makes sure pv eoi is only enabled when we know it's safe.
2311 pv_eoi_clr_pending(vcpu
);
2314 vector
= apic_set_eoi(apic
);
2315 trace_kvm_pv_eoi(apic
, vector
);
2318 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
2322 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
2323 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
2325 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2328 if (kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2332 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
2336 * apic_sync_pv_eoi_to_guest - called before vmentry
2338 * Detect whether it's safe to enable PV EOI and
2341 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
2342 struct kvm_lapic
*apic
)
2344 if (!pv_eoi_enabled(vcpu
) ||
2345 /* IRR set or many bits in ISR: could be nested. */
2346 apic
->irr_pending
||
2347 /* Cache not set: could be safe but we don't bother. */
2348 apic
->highest_isr_cache
== -1 ||
2349 /* Need EOI to update ioapic. */
2350 kvm_ioapic_handles_vector(apic
, apic
->highest_isr_cache
)) {
2352 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2353 * so we need not do anything here.
2358 pv_eoi_set_pending(apic
->vcpu
);
2361 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
2364 int max_irr
, max_isr
;
2365 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2367 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
2369 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2372 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
2373 max_irr
= apic_find_highest_irr(apic
);
2376 max_isr
= apic_find_highest_isr(apic
);
2379 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
2381 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2385 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
2388 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
2389 &vcpu
->arch
.apic
->vapic_cache
,
2390 vapic_addr
, sizeof(u32
)))
2392 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2394 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2397 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
2401 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
2403 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2404 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
2406 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2409 if (reg
== APIC_ICR2
)
2412 /* if this is ICR write vector before command */
2413 if (reg
== APIC_ICR
)
2414 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2415 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2418 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
2420 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2421 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
2423 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2426 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
2427 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2432 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2434 if (reg
== APIC_ICR
)
2435 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2437 *data
= (((u64
)high
) << 32) | low
;
2442 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
2444 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2446 if (!lapic_in_kernel(vcpu
))
2449 /* if this is ICR write vector before command */
2450 if (reg
== APIC_ICR
)
2451 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2452 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2455 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2457 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2460 if (!lapic_in_kernel(vcpu
))
2463 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2465 if (reg
== APIC_ICR
)
2466 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2468 *data
= (((u64
)high
) << 32) | low
;
2473 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
2475 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2476 if (!IS_ALIGNED(addr
, 4))
2479 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2480 if (!pv_eoi_enabled(vcpu
))
2482 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2486 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2488 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2492 if (!lapic_in_kernel(vcpu
) || !apic
->pending_events
)
2496 * INITs are latched while in SMM. Because an SMM CPU cannot
2497 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2498 * and delay processing of INIT until the next RSM.
2501 WARN_ON_ONCE(vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
);
2502 if (test_bit(KVM_APIC_SIPI
, &apic
->pending_events
))
2503 clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
2507 pe
= xchg(&apic
->pending_events
, 0);
2508 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2509 kvm_lapic_reset(vcpu
, true);
2510 kvm_vcpu_reset(vcpu
, true);
2511 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2512 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2514 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2516 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2517 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2518 /* evaluate pending_events before reading the vector */
2520 sipi_vector
= apic
->sipi_vector
;
2521 apic_debug("vcpu %d received sipi with vector # %x\n",
2522 vcpu
->vcpu_id
, sipi_vector
);
2523 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2524 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2528 void kvm_lapic_init(void)
2530 /* do not patch jump label more than once per second */
2531 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2532 jump_label_rate_limit(&apic_sw_disabled
, HZ
);
2535 void kvm_lapic_exit(void)
2537 static_key_deferred_flush(&apic_hw_disabled
);
2538 static_key_deferred_flush(&apic_sw_disabled
);