3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/export.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 #define APIC_BUS_CYCLE_NS 1
59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60 #define apic_debug(fmt, arg...)
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 static inline int apic_test_vector(int vec
, void *bitmap
)
77 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
80 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
82 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
84 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
85 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
88 static inline void apic_clear_vector(int vec
, void *bitmap
)
90 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
93 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
95 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
98 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
100 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
103 struct static_key_deferred apic_hw_disabled __read_mostly
;
104 struct static_key_deferred apic_sw_disabled __read_mostly
;
106 static inline int apic_enabled(struct kvm_lapic
*apic
)
108 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
112 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
115 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
116 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
118 static inline u8
kvm_xapic_id(struct kvm_lapic
*apic
)
120 return kvm_lapic_get_reg(apic
, APIC_ID
) >> 24;
123 static inline u32
kvm_x2apic_id(struct kvm_lapic
*apic
)
125 return apic
->vcpu
->vcpu_id
;
128 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map
*map
,
129 u32 dest_id
, struct kvm_lapic
***cluster
, u16
*mask
) {
131 case KVM_APIC_MODE_X2APIC
: {
132 u32 offset
= (dest_id
>> 16) * 16;
133 u32 max_apic_id
= map
->max_apic_id
;
135 if (offset
<= max_apic_id
) {
136 u8 cluster_size
= min(max_apic_id
- offset
+ 1, 16U);
138 *cluster
= &map
->phys_map
[offset
];
139 *mask
= dest_id
& (0xffff >> (16 - cluster_size
));
146 case KVM_APIC_MODE_XAPIC_FLAT
:
147 *cluster
= map
->xapic_flat_map
;
148 *mask
= dest_id
& 0xff;
150 case KVM_APIC_MODE_XAPIC_CLUSTER
:
151 *cluster
= map
->xapic_cluster_map
[(dest_id
>> 4) & 0xf];
152 *mask
= dest_id
& 0xf;
160 static void kvm_apic_map_free(struct rcu_head
*rcu
)
162 struct kvm_apic_map
*map
= container_of(rcu
, struct kvm_apic_map
, rcu
);
167 static void recalculate_apic_map(struct kvm
*kvm
)
169 struct kvm_apic_map
*new, *old
= NULL
;
170 struct kvm_vcpu
*vcpu
;
172 u32 max_id
= 255; /* enough space for any xAPIC ID */
174 mutex_lock(&kvm
->arch
.apic_map_lock
);
176 kvm_for_each_vcpu(i
, vcpu
, kvm
)
177 if (kvm_apic_present(vcpu
))
178 max_id
= max(max_id
, kvm_x2apic_id(vcpu
->arch
.apic
));
180 new = kvzalloc(sizeof(struct kvm_apic_map
) +
181 sizeof(struct kvm_lapic
*) * ((u64
)max_id
+ 1), GFP_KERNEL
);
186 new->max_apic_id
= max_id
;
188 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
189 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
190 struct kvm_lapic
**cluster
;
196 if (!kvm_apic_present(vcpu
))
199 xapic_id
= kvm_xapic_id(apic
);
200 x2apic_id
= kvm_x2apic_id(apic
);
202 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
203 if ((apic_x2apic_mode(apic
) || x2apic_id
> 0xff) &&
204 x2apic_id
<= new->max_apic_id
)
205 new->phys_map
[x2apic_id
] = apic
;
207 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
208 * prevent them from masking VCPUs with APIC ID <= 0xff.
210 if (!apic_x2apic_mode(apic
) && !new->phys_map
[xapic_id
])
211 new->phys_map
[xapic_id
] = apic
;
213 ldr
= kvm_lapic_get_reg(apic
, APIC_LDR
);
215 if (apic_x2apic_mode(apic
)) {
216 new->mode
|= KVM_APIC_MODE_X2APIC
;
218 ldr
= GET_APIC_LOGICAL_ID(ldr
);
219 if (kvm_lapic_get_reg(apic
, APIC_DFR
) == APIC_DFR_FLAT
)
220 new->mode
|= KVM_APIC_MODE_XAPIC_FLAT
;
222 new->mode
|= KVM_APIC_MODE_XAPIC_CLUSTER
;
225 if (!kvm_apic_map_get_logical_dest(new, ldr
, &cluster
, &mask
))
229 cluster
[ffs(mask
) - 1] = apic
;
232 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
233 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
234 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
235 mutex_unlock(&kvm
->arch
.apic_map_lock
);
238 call_rcu(&old
->rcu
, kvm_apic_map_free
);
240 kvm_make_scan_ioapic_request(kvm
);
243 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
245 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
247 kvm_lapic_set_reg(apic
, APIC_SPIV
, val
);
249 if (enabled
!= apic
->sw_enabled
) {
250 apic
->sw_enabled
= enabled
;
252 static_key_slow_dec_deferred(&apic_sw_disabled
);
253 recalculate_apic_map(apic
->vcpu
->kvm
);
255 static_key_slow_inc(&apic_sw_disabled
.key
);
259 static inline void kvm_apic_set_xapic_id(struct kvm_lapic
*apic
, u8 id
)
261 kvm_lapic_set_reg(apic
, APIC_ID
, id
<< 24);
262 recalculate_apic_map(apic
->vcpu
->kvm
);
265 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
267 kvm_lapic_set_reg(apic
, APIC_LDR
, id
);
268 recalculate_apic_map(apic
->vcpu
->kvm
);
271 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic
*apic
, u32 id
)
273 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
275 WARN_ON_ONCE(id
!= apic
->vcpu
->vcpu_id
);
277 kvm_lapic_set_reg(apic
, APIC_ID
, id
);
278 kvm_lapic_set_reg(apic
, APIC_LDR
, ldr
);
279 recalculate_apic_map(apic
->vcpu
->kvm
);
282 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
284 return !(kvm_lapic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
287 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
289 return kvm_lapic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
292 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
294 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
297 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
299 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
302 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
304 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
307 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
309 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
312 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
314 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
315 struct kvm_cpuid_entry2
*feat
;
316 u32 v
= APIC_VERSION
;
318 if (!lapic_in_kernel(vcpu
))
321 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
322 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
323 v
|= APIC_LVR_DIRECTED_EOI
;
324 kvm_lapic_set_reg(apic
, APIC_LVR
, v
);
327 static const unsigned int apic_lvt_mask
[KVM_APIC_LVT_NUM
] = {
328 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
329 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
330 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
331 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
332 LVT_MASK
/* LVTERR */
335 static int find_highest_vector(void *bitmap
)
340 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
341 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
342 reg
= bitmap
+ REG_POS(vec
);
344 return __fls(*reg
) + vec
;
350 static u8
count_vectors(void *bitmap
)
356 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
357 reg
= bitmap
+ REG_POS(vec
);
358 count
+= hweight32(*reg
);
364 int __kvm_apic_update_irr(u32
*pir
, void *regs
)
367 u32 pir_val
, irr_val
;
370 for (i
= vec
= 0; i
<= 7; i
++, vec
+= 32) {
371 pir_val
= READ_ONCE(pir
[i
]);
372 irr_val
= *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10));
374 irr_val
|= xchg(&pir
[i
], 0);
375 *((u32
*)(regs
+ APIC_IRR
+ i
* 0x10)) = irr_val
;
378 max_irr
= __fls(irr_val
) + vec
;
383 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr
);
385 int kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
387 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
389 return __kvm_apic_update_irr(pir
, apic
->regs
);
391 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
393 static inline int apic_search_irr(struct kvm_lapic
*apic
)
395 return find_highest_vector(apic
->regs
+ APIC_IRR
);
398 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
403 * Note that irr_pending is just a hint. It will be always
404 * true with virtual interrupt delivery enabled.
406 if (!apic
->irr_pending
)
409 result
= apic_search_irr(apic
);
410 ASSERT(result
== -1 || result
>= 16);
415 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
417 struct kvm_vcpu
*vcpu
;
421 if (unlikely(vcpu
->arch
.apicv_active
)) {
422 /* need to update RVI */
423 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
424 kvm_x86_ops
->hwapic_irr_update(vcpu
,
425 apic_find_highest_irr(apic
));
427 apic
->irr_pending
= false;
428 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
429 if (apic_search_irr(apic
) != -1)
430 apic
->irr_pending
= true;
434 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
436 struct kvm_vcpu
*vcpu
;
438 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
444 * With APIC virtualization enabled, all caching is disabled
445 * because the processor can modify ISR under the hood. Instead
448 if (unlikely(vcpu
->arch
.apicv_active
))
449 kvm_x86_ops
->hwapic_isr_update(vcpu
, vec
);
452 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
454 * ISR (in service register) bit is set when injecting an interrupt.
455 * The highest vector is injected. Thus the latest bit set matches
456 * the highest bit in ISR.
458 apic
->highest_isr_cache
= vec
;
462 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
467 * Note that isr_count is always 1, and highest_isr_cache
468 * is always -1, with APIC virtualization enabled.
470 if (!apic
->isr_count
)
472 if (likely(apic
->highest_isr_cache
!= -1))
473 return apic
->highest_isr_cache
;
475 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
476 ASSERT(result
== -1 || result
>= 16);
481 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
483 struct kvm_vcpu
*vcpu
;
484 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
490 * We do get here for APIC virtualization enabled if the guest
491 * uses the Hyper-V APIC enlightenment. In this case we may need
492 * to trigger a new interrupt delivery by writing the SVI field;
493 * on the other hand isr_count and highest_isr_cache are unused
494 * and must be left alone.
496 if (unlikely(vcpu
->arch
.apicv_active
))
497 kvm_x86_ops
->hwapic_isr_update(vcpu
,
498 apic_find_highest_isr(apic
));
501 BUG_ON(apic
->isr_count
< 0);
502 apic
->highest_isr_cache
= -1;
506 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
508 /* This may race with setting of irr in __apic_accept_irq() and
509 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
510 * will cause vmexit immediately and the value will be recalculated
511 * on the next vmentry.
513 return apic_find_highest_irr(vcpu
->arch
.apic
);
515 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr
);
517 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
518 int vector
, int level
, int trig_mode
,
519 struct dest_map
*dest_map
);
521 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
522 struct dest_map
*dest_map
)
524 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
526 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
527 irq
->level
, irq
->trig_mode
, dest_map
);
530 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
533 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
537 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
540 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
544 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
546 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
549 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
552 if (pv_eoi_get_user(vcpu
, &val
) < 0)
553 apic_debug("Can't read EOI MSR value: 0x%llx\n",
554 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
558 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
560 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
561 apic_debug("Can't set EOI MSR value: 0x%llx\n",
562 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
565 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
568 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
570 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
571 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
572 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
575 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
578 static int apic_has_interrupt_for_ppr(struct kvm_lapic
*apic
, u32 ppr
)
581 if (kvm_x86_ops
->sync_pir_to_irr
&& apic
->vcpu
->arch
.apicv_active
)
582 highest_irr
= kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
584 highest_irr
= apic_find_highest_irr(apic
);
585 if (highest_irr
== -1 || (highest_irr
& 0xF0) <= ppr
)
590 static bool __apic_update_ppr(struct kvm_lapic
*apic
, u32
*new_ppr
)
592 u32 tpr
, isrv
, ppr
, old_ppr
;
595 old_ppr
= kvm_lapic_get_reg(apic
, APIC_PROCPRI
);
596 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
);
597 isr
= apic_find_highest_isr(apic
);
598 isrv
= (isr
!= -1) ? isr
: 0;
600 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
605 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
606 apic
, ppr
, isr
, isrv
);
610 kvm_lapic_set_reg(apic
, APIC_PROCPRI
, ppr
);
612 return ppr
< old_ppr
;
615 static void apic_update_ppr(struct kvm_lapic
*apic
)
619 if (__apic_update_ppr(apic
, &ppr
) &&
620 apic_has_interrupt_for_ppr(apic
, ppr
) != -1)
621 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
624 void kvm_apic_update_ppr(struct kvm_vcpu
*vcpu
)
626 apic_update_ppr(vcpu
->arch
.apic
);
628 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr
);
630 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
632 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, tpr
);
633 apic_update_ppr(apic
);
636 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 mda
)
638 return mda
== (apic_x2apic_mode(apic
) ?
639 X2APIC_BROADCAST
: APIC_BROADCAST
);
642 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 mda
)
644 if (kvm_apic_broadcast(apic
, mda
))
647 if (apic_x2apic_mode(apic
))
648 return mda
== kvm_x2apic_id(apic
);
651 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
652 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
653 * this allows unique addressing of VCPUs with APIC ID over 0xff.
654 * The 0xff condition is needed because writeable xAPIC ID.
656 if (kvm_x2apic_id(apic
) > 0xff && mda
== kvm_x2apic_id(apic
))
659 return mda
== kvm_xapic_id(apic
);
662 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
666 if (kvm_apic_broadcast(apic
, mda
))
669 logical_id
= kvm_lapic_get_reg(apic
, APIC_LDR
);
671 if (apic_x2apic_mode(apic
))
672 return ((logical_id
>> 16) == (mda
>> 16))
673 && (logical_id
& mda
& 0xffff) != 0;
675 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
677 switch (kvm_lapic_get_reg(apic
, APIC_DFR
)) {
679 return (logical_id
& mda
) != 0;
680 case APIC_DFR_CLUSTER
:
681 return ((logical_id
>> 4) == (mda
>> 4))
682 && (logical_id
& mda
& 0xf) != 0;
684 apic_debug("Bad DFR vcpu %d: %08x\n",
685 apic
->vcpu
->vcpu_id
, kvm_lapic_get_reg(apic
, APIC_DFR
));
690 /* The KVM local APIC implementation has two quirks:
692 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
693 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
694 * KVM doesn't do that aliasing.
696 * - in-kernel IOAPIC messages have to be delivered directly to
697 * x2APIC, because the kernel does not support interrupt remapping.
698 * In order to support broadcast without interrupt remapping, x2APIC
699 * rewrites the destination of non-IPI messages from APIC_BROADCAST
700 * to X2APIC_BROADCAST.
702 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
703 * important when userspace wants to use x2APIC-format MSIs, because
704 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
706 static u32
kvm_apic_mda(struct kvm_vcpu
*vcpu
, unsigned int dest_id
,
707 struct kvm_lapic
*source
, struct kvm_lapic
*target
)
709 bool ipi
= source
!= NULL
;
711 if (!vcpu
->kvm
->arch
.x2apic_broadcast_quirk_disabled
&&
712 !ipi
&& dest_id
== APIC_BROADCAST
&& apic_x2apic_mode(target
))
713 return X2APIC_BROADCAST
;
718 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
719 int short_hand
, unsigned int dest
, int dest_mode
)
721 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
722 u32 mda
= kvm_apic_mda(vcpu
, dest
, source
, target
);
724 apic_debug("target %p, source %p, dest 0x%x, "
725 "dest_mode 0x%x, short_hand 0x%x\n",
726 target
, source
, dest
, dest_mode
, short_hand
);
729 switch (short_hand
) {
730 case APIC_DEST_NOSHORT
:
731 if (dest_mode
== APIC_DEST_PHYSICAL
)
732 return kvm_apic_match_physical_addr(target
, mda
);
734 return kvm_apic_match_logical_addr(target
, mda
);
736 return target
== source
;
737 case APIC_DEST_ALLINC
:
739 case APIC_DEST_ALLBUT
:
740 return target
!= source
;
742 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
747 EXPORT_SYMBOL_GPL(kvm_apic_match_dest
);
749 int kvm_vector_to_index(u32 vector
, u32 dest_vcpus
,
750 const unsigned long *bitmap
, u32 bitmap_size
)
755 mod
= vector
% dest_vcpus
;
757 for (i
= 0; i
<= mod
; i
++) {
758 idx
= find_next_bit(bitmap
, bitmap_size
, idx
+ 1);
759 BUG_ON(idx
== bitmap_size
);
765 static void kvm_apic_disabled_lapic_found(struct kvm
*kvm
)
767 if (!kvm
->arch
.disabled_lapic_found
) {
768 kvm
->arch
.disabled_lapic_found
= true;
770 "Disabled LAPIC found during irq injection\n");
774 static bool kvm_apic_is_broadcast_dest(struct kvm
*kvm
, struct kvm_lapic
**src
,
775 struct kvm_lapic_irq
*irq
, struct kvm_apic_map
*map
)
777 if (kvm
->arch
.x2apic_broadcast_quirk_disabled
) {
778 if ((irq
->dest_id
== APIC_BROADCAST
&&
779 map
->mode
!= KVM_APIC_MODE_X2APIC
))
781 if (irq
->dest_id
== X2APIC_BROADCAST
)
784 bool x2apic_ipi
= src
&& *src
&& apic_x2apic_mode(*src
);
785 if (irq
->dest_id
== (x2apic_ipi
?
786 X2APIC_BROADCAST
: APIC_BROADCAST
))
793 /* Return true if the interrupt can be handled by using *bitmap as index mask
794 * for valid destinations in *dst array.
795 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
796 * Note: we may have zero kvm_lapic destinations when we return true, which
797 * means that the interrupt should be dropped. In this case, *bitmap would be
798 * zero and *dst undefined.
800 static inline bool kvm_apic_map_get_dest_lapic(struct kvm
*kvm
,
801 struct kvm_lapic
**src
, struct kvm_lapic_irq
*irq
,
802 struct kvm_apic_map
*map
, struct kvm_lapic
***dst
,
803 unsigned long *bitmap
)
807 if (irq
->shorthand
== APIC_DEST_SELF
&& src
) {
811 } else if (irq
->shorthand
)
814 if (!map
|| kvm_apic_is_broadcast_dest(kvm
, src
, irq
, map
))
817 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
818 if (irq
->dest_id
> map
->max_apic_id
) {
821 *dst
= &map
->phys_map
[irq
->dest_id
];
828 if (!kvm_apic_map_get_logical_dest(map
, irq
->dest_id
, dst
,
832 if (!kvm_lowest_prio_delivery(irq
))
835 if (!kvm_vector_hashing_enabled()) {
837 for_each_set_bit(i
, bitmap
, 16) {
842 else if (kvm_apic_compare_prio((*dst
)[i
]->vcpu
,
843 (*dst
)[lowest
]->vcpu
) < 0)
850 lowest
= kvm_vector_to_index(irq
->vector
, hweight16(*bitmap
),
853 if (!(*dst
)[lowest
]) {
854 kvm_apic_disabled_lapic_found(kvm
);
860 *bitmap
= (lowest
>= 0) ? 1 << lowest
: 0;
865 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
866 struct kvm_lapic_irq
*irq
, int *r
, struct dest_map
*dest_map
)
868 struct kvm_apic_map
*map
;
869 unsigned long bitmap
;
870 struct kvm_lapic
**dst
= NULL
;
876 if (irq
->shorthand
== APIC_DEST_SELF
) {
877 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
882 map
= rcu_dereference(kvm
->arch
.apic_map
);
884 ret
= kvm_apic_map_get_dest_lapic(kvm
, &src
, irq
, map
, &dst
, &bitmap
);
886 for_each_set_bit(i
, &bitmap
, 16) {
891 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
899 * This routine tries to handler interrupts in posted mode, here is how
900 * it deals with different cases:
901 * - For single-destination interrupts, handle it in posted mode
902 * - Else if vector hashing is enabled and it is a lowest-priority
903 * interrupt, handle it in posted mode and use the following mechanism
904 * to find the destinaiton vCPU.
905 * 1. For lowest-priority interrupts, store all the possible
906 * destination vCPUs in an array.
907 * 2. Use "guest vector % max number of destination vCPUs" to find
908 * the right destination vCPU in the array for the lowest-priority
910 * - Otherwise, use remapped mode to inject the interrupt.
912 bool kvm_intr_is_single_vcpu_fast(struct kvm
*kvm
, struct kvm_lapic_irq
*irq
,
913 struct kvm_vcpu
**dest_vcpu
)
915 struct kvm_apic_map
*map
;
916 unsigned long bitmap
;
917 struct kvm_lapic
**dst
= NULL
;
924 map
= rcu_dereference(kvm
->arch
.apic_map
);
926 if (kvm_apic_map_get_dest_lapic(kvm
, NULL
, irq
, map
, &dst
, &bitmap
) &&
927 hweight16(bitmap
) == 1) {
928 unsigned long i
= find_first_bit(&bitmap
, 16);
931 *dest_vcpu
= dst
[i
]->vcpu
;
941 * Add a pending IRQ into lapic.
942 * Return 1 if successfully added and 0 if discarded.
944 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
945 int vector
, int level
, int trig_mode
,
946 struct dest_map
*dest_map
)
949 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
951 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
953 switch (delivery_mode
) {
955 vcpu
->arch
.apic_arb_prio
++;
957 if (unlikely(trig_mode
&& !level
))
960 /* FIXME add logic for vcpu on reset */
961 if (unlikely(!apic_enabled(apic
)))
967 __set_bit(vcpu
->vcpu_id
, dest_map
->map
);
968 dest_map
->vectors
[vcpu
->vcpu_id
] = vector
;
971 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
) != !!trig_mode
) {
973 kvm_lapic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
975 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
978 if (vcpu
->arch
.apicv_active
)
979 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
981 kvm_lapic_set_irr(vector
, apic
);
983 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
990 vcpu
->arch
.pv
.pv_unhalted
= 1;
991 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
997 kvm_make_request(KVM_REQ_SMI
, vcpu
);
1003 kvm_inject_nmi(vcpu
);
1004 kvm_vcpu_kick(vcpu
);
1008 if (!trig_mode
|| level
) {
1010 /* assumes that there are only KVM_APIC_INIT/SIPI */
1011 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
1012 /* make sure pending_events is visible before sending
1015 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1016 kvm_vcpu_kick(vcpu
);
1018 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1023 case APIC_DM_STARTUP
:
1024 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1025 vcpu
->vcpu_id
, vector
);
1027 apic
->sipi_vector
= vector
;
1028 /* make sure sipi_vector is visible for the receiver */
1030 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
1031 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1032 kvm_vcpu_kick(vcpu
);
1035 case APIC_DM_EXTINT
:
1037 * Should only be called by kvm_apic_local_deliver() with LVT0,
1038 * before NMI watchdog was enabled. Already handled by
1039 * kvm_apic_accept_pic_intr().
1044 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
1051 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
1053 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
1056 static bool kvm_ioapic_handles_vector(struct kvm_lapic
*apic
, int vector
)
1058 return test_bit(vector
, apic
->vcpu
->arch
.ioapic_handled_vectors
);
1061 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
1065 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1066 if (!kvm_ioapic_handles_vector(apic
, vector
))
1069 /* Request a KVM exit to inform the userspace IOAPIC. */
1070 if (irqchip_split(apic
->vcpu
->kvm
)) {
1071 apic
->vcpu
->arch
.pending_ioapic_eoi
= vector
;
1072 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT
, apic
->vcpu
);
1076 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
1077 trigger_mode
= IOAPIC_LEVEL_TRIG
;
1079 trigger_mode
= IOAPIC_EDGE_TRIG
;
1081 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
1084 static int apic_set_eoi(struct kvm_lapic
*apic
)
1086 int vector
= apic_find_highest_isr(apic
);
1088 trace_kvm_eoi(apic
, vector
);
1091 * Not every write EOI will has corresponding ISR,
1092 * one example is when Kernel check timer on setup_IO_APIC
1097 apic_clear_isr(vector
, apic
);
1098 apic_update_ppr(apic
);
1100 if (test_bit(vector
, vcpu_to_synic(apic
->vcpu
)->vec_bitmap
))
1101 kvm_hv_synic_send_eoi(apic
->vcpu
, vector
);
1103 kvm_ioapic_send_eoi(apic
, vector
);
1104 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1109 * this interface assumes a trap-like exit, which has already finished
1110 * desired side effect including vISR and vPPR update.
1112 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
1114 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1116 trace_kvm_eoi(apic
, vector
);
1118 kvm_ioapic_send_eoi(apic
, vector
);
1119 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
1121 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
1123 static void apic_send_ipi(struct kvm_lapic
*apic
)
1125 u32 icr_low
= kvm_lapic_get_reg(apic
, APIC_ICR
);
1126 u32 icr_high
= kvm_lapic_get_reg(apic
, APIC_ICR2
);
1127 struct kvm_lapic_irq irq
;
1129 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
1130 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
1131 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
1132 irq
.level
= (icr_low
& APIC_INT_ASSERT
) != 0;
1133 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
1134 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
1135 irq
.msi_redir_hint
= false;
1136 if (apic_x2apic_mode(apic
))
1137 irq
.dest_id
= icr_high
;
1139 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
1141 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
1143 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1144 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1145 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1146 "msi_redir_hint 0x%x\n",
1147 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
1148 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
1149 irq
.vector
, irq
.msi_redir_hint
);
1151 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
1154 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
1156 ktime_t remaining
, now
;
1160 ASSERT(apic
!= NULL
);
1162 /* if initial count is 0, current count should also be 0 */
1163 if (kvm_lapic_get_reg(apic
, APIC_TMICT
) == 0 ||
1164 apic
->lapic_timer
.period
== 0)
1168 remaining
= ktime_sub(apic
->lapic_timer
.target_expiration
, now
);
1169 if (ktime_to_ns(remaining
) < 0)
1172 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
1173 tmcct
= div64_u64(ns
,
1174 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
1179 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1181 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1182 struct kvm_run
*run
= vcpu
->run
;
1184 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
1185 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
1186 run
->tpr_access
.is_write
= write
;
1189 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
1191 if (apic
->vcpu
->arch
.tpr_access_reporting
)
1192 __report_tpr_access(apic
, write
);
1195 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
1199 if (offset
>= LAPIC_MMIO_LENGTH
)
1204 apic_debug("Access APIC ARBPRI register which is for P6\n");
1207 case APIC_TMCCT
: /* Timer CCR */
1208 if (apic_lvtt_tscdeadline(apic
))
1211 val
= apic_get_tmcct(apic
);
1214 apic_update_ppr(apic
);
1215 val
= kvm_lapic_get_reg(apic
, offset
);
1218 report_tpr_access(apic
, false);
1221 val
= kvm_lapic_get_reg(apic
, offset
);
1228 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
1230 return container_of(dev
, struct kvm_lapic
, dev
);
1233 int kvm_lapic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
1236 unsigned char alignment
= offset
& 0xf;
1238 /* this bitmask has a bit cleared for each reserved register */
1239 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
1241 if ((alignment
+ len
) > 4) {
1242 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1247 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1248 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1253 result
= __apic_read(apic
, offset
& ~0xf);
1255 trace_kvm_apic_read(offset
, result
);
1261 memcpy(data
, (char *)&result
+ alignment
, len
);
1264 printk(KERN_ERR
"Local APIC read with len = %x, "
1265 "should be 1,2, or 4 instead\n", len
);
1270 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read
);
1272 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1274 return kvm_apic_hw_enabled(apic
) &&
1275 addr
>= apic
->base_address
&&
1276 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1279 static int apic_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1280 gpa_t address
, int len
, void *data
)
1282 struct kvm_lapic
*apic
= to_lapic(this);
1283 u32 offset
= address
- apic
->base_address
;
1285 if (!apic_mmio_in_range(apic
, address
))
1288 kvm_lapic_reg_read(apic
, offset
, len
, data
);
1293 static void update_divide_count(struct kvm_lapic
*apic
)
1295 u32 tmp1
, tmp2
, tdcr
;
1297 tdcr
= kvm_lapic_get_reg(apic
, APIC_TDCR
);
1299 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1300 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1302 apic_debug("timer divide count is 0x%x\n",
1303 apic
->divide_count
);
1306 static void apic_update_lvtt(struct kvm_lapic
*apic
)
1308 u32 timer_mode
= kvm_lapic_get_reg(apic
, APIC_LVTT
) &
1309 apic
->lapic_timer
.timer_mode_mask
;
1311 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1312 apic
->lapic_timer
.timer_mode
= timer_mode
;
1313 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1317 static void apic_timer_expired(struct kvm_lapic
*apic
)
1319 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1320 struct swait_queue_head
*q
= &vcpu
->wq
;
1321 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1323 if (atomic_read(&apic
->lapic_timer
.pending
))
1326 atomic_inc(&apic
->lapic_timer
.pending
);
1327 kvm_set_pending_timer(vcpu
);
1329 if (swait_active(q
))
1332 if (apic_lvtt_tscdeadline(apic
))
1333 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1337 * On APICv, this test will cause a busy wait
1338 * during a higher-priority task.
1341 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1343 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1344 u32 reg
= kvm_lapic_get_reg(apic
, APIC_LVTT
);
1346 if (kvm_apic_hw_enabled(apic
)) {
1347 int vec
= reg
& APIC_VECTOR_MASK
;
1348 void *bitmap
= apic
->regs
+ APIC_ISR
;
1350 if (vcpu
->arch
.apicv_active
)
1351 bitmap
= apic
->regs
+ APIC_IRR
;
1353 if (apic_test_vector(vec
, bitmap
))
1359 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1361 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1362 u64 guest_tsc
, tsc_deadline
;
1364 if (!lapic_in_kernel(vcpu
))
1367 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1370 if (!lapic_timer_int_injected(vcpu
))
1373 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1374 apic
->lapic_timer
.expired_tscdeadline
= 0;
1375 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1376 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1378 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1379 if (guest_tsc
< tsc_deadline
)
1380 __delay(min(tsc_deadline
- guest_tsc
,
1381 nsec_to_cycles(vcpu
, lapic_timer_advance_ns
)));
1384 static void start_sw_tscdeadline(struct kvm_lapic
*apic
)
1386 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1389 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1390 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1391 unsigned long flags
;
1394 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1397 local_irq_save(flags
);
1400 guest_tsc
= kvm_read_l1_tsc(vcpu
, rdtsc());
1401 if (likely(tscdeadline
> guest_tsc
)) {
1402 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1403 do_div(ns
, this_tsc_khz
);
1404 expire
= ktime_add_ns(now
, ns
);
1405 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1406 hrtimer_start(&apic
->lapic_timer
.timer
,
1407 expire
, HRTIMER_MODE_ABS_PINNED
);
1409 apic_timer_expired(apic
);
1411 local_irq_restore(flags
);
1414 static void start_sw_period(struct kvm_lapic
*apic
)
1416 if (!apic
->lapic_timer
.period
)
1419 if (apic_lvtt_oneshot(apic
) &&
1420 ktime_after(ktime_get(),
1421 apic
->lapic_timer
.target_expiration
)) {
1422 apic_timer_expired(apic
);
1426 hrtimer_start(&apic
->lapic_timer
.timer
,
1427 apic
->lapic_timer
.target_expiration
,
1428 HRTIMER_MODE_ABS_PINNED
);
1431 static bool set_target_expiration(struct kvm_lapic
*apic
)
1437 apic
->lapic_timer
.period
= (u64
)kvm_lapic_get_reg(apic
, APIC_TMICT
)
1438 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1440 if (!apic
->lapic_timer
.period
)
1444 * Do not allow the guest to program periodic timers with small
1445 * interval, since the hrtimers are not throttled by the host
1448 if (apic_lvtt_period(apic
)) {
1449 s64 min_period
= min_timer_period_us
* 1000LL;
1451 if (apic
->lapic_timer
.period
< min_period
) {
1452 pr_info_ratelimited(
1453 "kvm: vcpu %i: requested %lld ns "
1454 "lapic timer period limited to %lld ns\n",
1455 apic
->vcpu
->vcpu_id
,
1456 apic
->lapic_timer
.period
, min_period
);
1457 apic
->lapic_timer
.period
= min_period
;
1461 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1463 "timer initial count 0x%x, period %lldns, "
1464 "expire @ 0x%016" PRIx64
".\n", __func__
,
1465 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1466 kvm_lapic_get_reg(apic
, APIC_TMICT
),
1467 apic
->lapic_timer
.period
,
1468 ktime_to_ns(ktime_add_ns(now
,
1469 apic
->lapic_timer
.period
)));
1471 apic
->lapic_timer
.tscdeadline
= kvm_read_l1_tsc(apic
->vcpu
, tscl
) +
1472 nsec_to_cycles(apic
->vcpu
, apic
->lapic_timer
.period
);
1473 apic
->lapic_timer
.target_expiration
= ktime_add_ns(now
, apic
->lapic_timer
.period
);
1478 static void advance_periodic_target_expiration(struct kvm_lapic
*apic
)
1480 apic
->lapic_timer
.tscdeadline
+=
1481 nsec_to_cycles(apic
->vcpu
, apic
->lapic_timer
.period
);
1482 apic
->lapic_timer
.target_expiration
=
1483 ktime_add_ns(apic
->lapic_timer
.target_expiration
,
1484 apic
->lapic_timer
.period
);
1487 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu
*vcpu
)
1489 if (!lapic_in_kernel(vcpu
))
1492 return vcpu
->arch
.apic
->lapic_timer
.hv_timer_in_use
;
1494 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use
);
1496 static void cancel_hv_timer(struct kvm_lapic
*apic
)
1498 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1500 kvm_x86_ops
->cancel_hv_timer(apic
->vcpu
);
1501 apic
->lapic_timer
.hv_timer_in_use
= false;
1505 static bool start_hv_timer(struct kvm_lapic
*apic
)
1507 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1510 if (!kvm_x86_ops
->set_hv_timer
)
1513 if (!apic_lvtt_period(apic
) && atomic_read(&ktimer
->pending
))
1516 r
= kvm_x86_ops
->set_hv_timer(apic
->vcpu
, ktimer
->tscdeadline
);
1520 ktimer
->hv_timer_in_use
= true;
1521 hrtimer_cancel(&ktimer
->timer
);
1524 * Also recheck ktimer->pending, in case the sw timer triggered in
1525 * the window. For periodic timer, leave the hv timer running for
1526 * simplicity, and the deadline will be recomputed on the next vmexit.
1528 if (!apic_lvtt_period(apic
) && (r
|| atomic_read(&ktimer
->pending
))) {
1530 apic_timer_expired(apic
);
1534 trace_kvm_hv_timer_state(apic
->vcpu
->vcpu_id
, true);
1538 static void start_sw_timer(struct kvm_lapic
*apic
)
1540 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1541 if (apic
->lapic_timer
.hv_timer_in_use
)
1542 cancel_hv_timer(apic
);
1543 if (!apic_lvtt_period(apic
) && atomic_read(&ktimer
->pending
))
1546 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1547 start_sw_period(apic
);
1548 else if (apic_lvtt_tscdeadline(apic
))
1549 start_sw_tscdeadline(apic
);
1550 trace_kvm_hv_timer_state(apic
->vcpu
->vcpu_id
, false);
1553 static void restart_apic_timer(struct kvm_lapic
*apic
)
1555 if (!start_hv_timer(apic
))
1556 start_sw_timer(apic
);
1559 void kvm_lapic_expired_hv_timer(struct kvm_vcpu
*vcpu
)
1561 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1563 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1564 WARN_ON(swait_active(&vcpu
->wq
));
1565 cancel_hv_timer(apic
);
1566 apic_timer_expired(apic
);
1568 if (apic_lvtt_period(apic
) && apic
->lapic_timer
.period
) {
1569 advance_periodic_target_expiration(apic
);
1570 restart_apic_timer(apic
);
1573 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer
);
1575 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu
*vcpu
)
1577 restart_apic_timer(vcpu
->arch
.apic
);
1579 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer
);
1581 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu
*vcpu
)
1583 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1585 /* Possibly the TSC deadline timer is not enabled yet */
1586 if (apic
->lapic_timer
.hv_timer_in_use
)
1587 start_sw_timer(apic
);
1589 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer
);
1591 void kvm_lapic_restart_hv_timer(struct kvm_vcpu
*vcpu
)
1593 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1595 WARN_ON(!apic
->lapic_timer
.hv_timer_in_use
);
1596 restart_apic_timer(apic
);
1599 static void start_apic_timer(struct kvm_lapic
*apic
)
1601 atomic_set(&apic
->lapic_timer
.pending
, 0);
1603 if ((apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
))
1604 && !set_target_expiration(apic
))
1607 restart_apic_timer(apic
);
1610 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1612 bool lvt0_in_nmi_mode
= apic_lvt_nmi_mode(lvt0_val
);
1614 if (apic
->lvt0_in_nmi_mode
!= lvt0_in_nmi_mode
) {
1615 apic
->lvt0_in_nmi_mode
= lvt0_in_nmi_mode
;
1616 if (lvt0_in_nmi_mode
) {
1617 apic_debug("Receive NMI setting on APIC_LVT0 "
1618 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1619 atomic_inc(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1621 atomic_dec(&apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
);
1625 int kvm_lapic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1629 trace_kvm_apic_write(reg
, val
);
1632 case APIC_ID
: /* Local APIC ID */
1633 if (!apic_x2apic_mode(apic
))
1634 kvm_apic_set_xapic_id(apic
, val
>> 24);
1640 report_tpr_access(apic
, true);
1641 apic_set_tpr(apic
, val
& 0xff);
1649 if (!apic_x2apic_mode(apic
))
1650 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1656 if (!apic_x2apic_mode(apic
)) {
1657 kvm_lapic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1658 recalculate_apic_map(apic
->vcpu
->kvm
);
1665 if (kvm_lapic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1666 mask
|= APIC_SPIV_DIRECTED_EOI
;
1667 apic_set_spiv(apic
, val
& mask
);
1668 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1672 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++) {
1673 lvt_val
= kvm_lapic_get_reg(apic
,
1674 APIC_LVTT
+ 0x10 * i
);
1675 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1676 lvt_val
| APIC_LVT_MASKED
);
1678 apic_update_lvtt(apic
);
1679 atomic_set(&apic
->lapic_timer
.pending
, 0);
1685 /* No delay here, so we always clear the pending bit */
1686 kvm_lapic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1687 apic_send_ipi(apic
);
1691 if (!apic_x2apic_mode(apic
))
1693 kvm_lapic_set_reg(apic
, APIC_ICR2
, val
);
1697 apic_manage_nmi_watchdog(apic
, val
);
1702 /* TODO: Check vector */
1703 if (!kvm_apic_sw_enabled(apic
))
1704 val
|= APIC_LVT_MASKED
;
1706 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1707 kvm_lapic_set_reg(apic
, reg
, val
);
1712 if (!kvm_apic_sw_enabled(apic
))
1713 val
|= APIC_LVT_MASKED
;
1714 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1715 kvm_lapic_set_reg(apic
, APIC_LVTT
, val
);
1716 apic_update_lvtt(apic
);
1720 if (apic_lvtt_tscdeadline(apic
))
1723 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1724 kvm_lapic_set_reg(apic
, APIC_TMICT
, val
);
1725 start_apic_timer(apic
);
1730 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1731 kvm_lapic_set_reg(apic
, APIC_TDCR
, val
);
1732 update_divide_count(apic
);
1736 if (apic_x2apic_mode(apic
) && val
!= 0) {
1737 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1743 if (apic_x2apic_mode(apic
)) {
1744 kvm_lapic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1753 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1756 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write
);
1758 static int apic_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*this,
1759 gpa_t address
, int len
, const void *data
)
1761 struct kvm_lapic
*apic
= to_lapic(this);
1762 unsigned int offset
= address
- apic
->base_address
;
1765 if (!apic_mmio_in_range(apic
, address
))
1769 * APIC register must be aligned on 128-bits boundary.
1770 * 32/64/128 bits registers must be accessed thru 32 bits.
1773 if (len
!= 4 || (offset
& 0xf)) {
1774 /* Don't shout loud, $infamous_os would cause only noise. */
1775 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1781 /* too common printing */
1782 if (offset
!= APIC_EOI
)
1783 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1784 "0x%x\n", __func__
, offset
, len
, val
);
1786 kvm_lapic_reg_write(apic
, offset
& 0xff0, val
);
1791 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1793 kvm_lapic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1795 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1797 /* emulate APIC access in a trap manner */
1798 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1802 /* hw has done the conditional check and inst decode */
1805 kvm_lapic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1807 /* TODO: optimize to just emulate side effect w/o one more write */
1808 kvm_lapic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1810 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1812 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1814 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1816 if (!vcpu
->arch
.apic
)
1819 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1821 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1822 static_key_slow_dec_deferred(&apic_hw_disabled
);
1824 if (!apic
->sw_enabled
)
1825 static_key_slow_dec_deferred(&apic_sw_disabled
);
1828 free_page((unsigned long)apic
->regs
);
1834 *----------------------------------------------------------------------
1836 *----------------------------------------------------------------------
1838 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1840 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1842 if (!lapic_in_kernel(vcpu
) ||
1843 !apic_lvtt_tscdeadline(apic
))
1846 return apic
->lapic_timer
.tscdeadline
;
1849 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1851 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1853 if (!lapic_in_kernel(vcpu
) || apic_lvtt_oneshot(apic
) ||
1854 apic_lvtt_period(apic
))
1857 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1858 apic
->lapic_timer
.tscdeadline
= data
;
1859 start_apic_timer(apic
);
1862 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1864 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1866 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1867 | (kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 4));
1870 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1874 tpr
= (u64
) kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1876 return (tpr
& 0xf0) >> 4;
1879 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1881 u64 old_value
= vcpu
->arch
.apic_base
;
1882 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1885 value
|= MSR_IA32_APICBASE_BSP
;
1887 vcpu
->arch
.apic_base
= value
;
1889 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
)
1890 kvm_update_cpuid(vcpu
);
1895 /* update jump label if enable bit changes */
1896 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1897 if (value
& MSR_IA32_APICBASE_ENABLE
) {
1898 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
1899 static_key_slow_dec_deferred(&apic_hw_disabled
);
1901 static_key_slow_inc(&apic_hw_disabled
.key
);
1902 recalculate_apic_map(vcpu
->kvm
);
1906 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1907 if (value
& X2APIC_ENABLE
) {
1908 kvm_apic_set_x2apic_id(apic
, vcpu
->vcpu_id
);
1909 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1911 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1914 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1915 MSR_IA32_APICBASE_BASE
;
1917 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1918 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1919 pr_warn_once("APIC base relocation is unsupported by KVM");
1921 /* with FSB delivery interrupt, we can restart APIC functionality */
1922 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1923 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1927 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1929 struct kvm_lapic
*apic
;
1932 apic_debug("%s\n", __func__
);
1935 apic
= vcpu
->arch
.apic
;
1936 ASSERT(apic
!= NULL
);
1938 /* Stop the timer in case it's a reset to an active apic */
1939 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1942 kvm_lapic_set_base(vcpu
, APIC_DEFAULT_PHYS_BASE
|
1943 MSR_IA32_APICBASE_ENABLE
);
1944 kvm_apic_set_xapic_id(apic
, vcpu
->vcpu_id
);
1946 kvm_apic_set_version(apic
->vcpu
);
1948 for (i
= 0; i
< KVM_APIC_LVT_NUM
; i
++)
1949 kvm_lapic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1950 apic_update_lvtt(apic
);
1951 if (kvm_vcpu_is_reset_bsp(vcpu
) &&
1952 kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_LINT0_REENABLED
))
1953 kvm_lapic_set_reg(apic
, APIC_LVT0
,
1954 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1955 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
1957 kvm_lapic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1958 apic_set_spiv(apic
, 0xff);
1959 kvm_lapic_set_reg(apic
, APIC_TASKPRI
, 0);
1960 if (!apic_x2apic_mode(apic
))
1961 kvm_apic_set_ldr(apic
, 0);
1962 kvm_lapic_set_reg(apic
, APIC_ESR
, 0);
1963 kvm_lapic_set_reg(apic
, APIC_ICR
, 0);
1964 kvm_lapic_set_reg(apic
, APIC_ICR2
, 0);
1965 kvm_lapic_set_reg(apic
, APIC_TDCR
, 0);
1966 kvm_lapic_set_reg(apic
, APIC_TMICT
, 0);
1967 for (i
= 0; i
< 8; i
++) {
1968 kvm_lapic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1969 kvm_lapic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1970 kvm_lapic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1972 apic
->irr_pending
= vcpu
->arch
.apicv_active
;
1973 apic
->isr_count
= vcpu
->arch
.apicv_active
? 1 : 0;
1974 apic
->highest_isr_cache
= -1;
1975 update_divide_count(apic
);
1976 atomic_set(&apic
->lapic_timer
.pending
, 0);
1977 if (kvm_vcpu_is_bsp(vcpu
))
1978 kvm_lapic_set_base(vcpu
,
1979 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1980 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1981 apic_update_ppr(apic
);
1983 vcpu
->arch
.apic_arb_prio
= 0;
1984 vcpu
->arch
.apic_attention
= 0;
1986 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
1987 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1988 vcpu
, kvm_lapic_get_reg(apic
, APIC_ID
),
1989 vcpu
->arch
.apic_base
, apic
->base_address
);
1993 *----------------------------------------------------------------------
1995 *----------------------------------------------------------------------
1998 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
2000 return apic_lvtt_period(apic
);
2003 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
2005 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2007 if (apic_enabled(apic
) && apic_lvt_enabled(apic
, APIC_LVTT
))
2008 return atomic_read(&apic
->lapic_timer
.pending
);
2013 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
2015 u32 reg
= kvm_lapic_get_reg(apic
, lvt_type
);
2016 int vector
, mode
, trig_mode
;
2018 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
2019 vector
= reg
& APIC_VECTOR_MASK
;
2020 mode
= reg
& APIC_MODE_MASK
;
2021 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
2022 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
2028 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
2030 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2033 kvm_apic_local_deliver(apic
, APIC_LVT0
);
2036 static const struct kvm_io_device_ops apic_mmio_ops
= {
2037 .read
= apic_mmio_read
,
2038 .write
= apic_mmio_write
,
2041 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
2043 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
2044 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
2046 apic_timer_expired(apic
);
2048 if (lapic_is_periodic(apic
)) {
2049 advance_periodic_target_expiration(apic
);
2050 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
2051 return HRTIMER_RESTART
;
2053 return HRTIMER_NORESTART
;
2056 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
2058 struct kvm_lapic
*apic
;
2060 ASSERT(vcpu
!= NULL
);
2061 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
2063 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
2067 vcpu
->arch
.apic
= apic
;
2069 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
2071 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
2073 goto nomem_free_apic
;
2077 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
2078 HRTIMER_MODE_ABS_PINNED
);
2079 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
2082 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2083 * thinking that APIC satet has changed.
2085 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
2086 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
2087 kvm_lapic_reset(vcpu
, false);
2088 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
2097 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
2099 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2102 if (!apic_enabled(apic
))
2105 __apic_update_ppr(apic
, &ppr
);
2106 return apic_has_interrupt_for_ppr(apic
, ppr
);
2109 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
2111 u32 lvt0
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
2114 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
2116 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
2117 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
2122 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
2124 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2126 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
2127 kvm_apic_local_deliver(apic
, APIC_LVTT
);
2128 if (apic_lvtt_tscdeadline(apic
))
2129 apic
->lapic_timer
.tscdeadline
= 0;
2130 if (apic_lvtt_oneshot(apic
)) {
2131 apic
->lapic_timer
.tscdeadline
= 0;
2132 apic
->lapic_timer
.target_expiration
= 0;
2134 atomic_set(&apic
->lapic_timer
.pending
, 0);
2138 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
2140 int vector
= kvm_apic_has_interrupt(vcpu
);
2141 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2148 * We get here even with APIC virtualization enabled, if doing
2149 * nested virtualization and L1 runs with the "acknowledge interrupt
2150 * on exit" mode. Then we cannot inject the interrupt via RVI,
2151 * because the process would deliver it through the IDT.
2154 apic_clear_irr(vector
, apic
);
2155 if (test_bit(vector
, vcpu_to_synic(vcpu
)->auto_eoi_bitmap
)) {
2157 * For auto-EOI interrupts, there might be another pending
2158 * interrupt above PPR, so check whether to raise another
2161 apic_update_ppr(apic
);
2164 * For normal interrupts, PPR has been raised and there cannot
2165 * be a higher-priority pending interrupt---except if there was
2166 * a concurrent interrupt injection, but that would have
2167 * triggered KVM_REQ_EVENT already.
2169 apic_set_isr(vector
, apic
);
2170 __apic_update_ppr(apic
, &ppr
);
2176 static int kvm_apic_state_fixup(struct kvm_vcpu
*vcpu
,
2177 struct kvm_lapic_state
*s
, bool set
)
2179 if (apic_x2apic_mode(vcpu
->arch
.apic
)) {
2180 u32
*id
= (u32
*)(s
->regs
+ APIC_ID
);
2182 if (vcpu
->kvm
->arch
.x2apic_format
) {
2183 if (*id
!= vcpu
->vcpu_id
)
2196 int kvm_apic_get_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2198 memcpy(s
->regs
, vcpu
->arch
.apic
->regs
, sizeof(*s
));
2199 return kvm_apic_state_fixup(vcpu
, s
, false);
2202 int kvm_apic_set_state(struct kvm_vcpu
*vcpu
, struct kvm_lapic_state
*s
)
2204 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2208 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
2209 /* set SPIV separately to get count of SW disabled APICs right */
2210 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
2212 r
= kvm_apic_state_fixup(vcpu
, s
, true);
2215 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
2217 recalculate_apic_map(vcpu
->kvm
);
2218 kvm_apic_set_version(vcpu
);
2220 apic_update_ppr(apic
);
2221 hrtimer_cancel(&apic
->lapic_timer
.timer
);
2222 apic_update_lvtt(apic
);
2223 apic_manage_nmi_watchdog(apic
, kvm_lapic_get_reg(apic
, APIC_LVT0
));
2224 update_divide_count(apic
);
2225 start_apic_timer(apic
);
2226 apic
->irr_pending
= true;
2227 apic
->isr_count
= vcpu
->arch
.apicv_active
?
2228 1 : count_vectors(apic
->regs
+ APIC_ISR
);
2229 apic
->highest_isr_cache
= -1;
2230 if (vcpu
->arch
.apicv_active
) {
2231 kvm_x86_ops
->apicv_post_state_restore(vcpu
);
2232 kvm_x86_ops
->hwapic_irr_update(vcpu
,
2233 apic_find_highest_irr(apic
));
2234 kvm_x86_ops
->hwapic_isr_update(vcpu
,
2235 apic_find_highest_isr(apic
));
2237 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2238 if (ioapic_in_kernel(vcpu
->kvm
))
2239 kvm_rtc_eoi_tracking_restore_one(vcpu
);
2241 vcpu
->arch
.apic_arb_prio
= 0;
2246 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
2248 struct hrtimer
*timer
;
2250 if (!lapic_in_kernel(vcpu
))
2253 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
2254 if (hrtimer_cancel(timer
))
2255 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS_PINNED
);
2259 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2261 * Detect whether guest triggered PV EOI since the
2262 * last entry. If yes, set EOI on guests's behalf.
2263 * Clear PV EOI in guest memory in any case.
2265 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
2266 struct kvm_lapic
*apic
)
2271 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2272 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2274 * KVM_APIC_PV_EOI_PENDING is unset:
2275 * -> host disabled PV EOI.
2276 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2277 * -> host enabled PV EOI, guest did not execute EOI yet.
2278 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2279 * -> host enabled PV EOI, guest executed EOI.
2281 BUG_ON(!pv_eoi_enabled(vcpu
));
2282 pending
= pv_eoi_get_pending(vcpu
);
2284 * Clear pending bit in any case: it will be set again on vmentry.
2285 * While this might not be ideal from performance point of view,
2286 * this makes sure pv eoi is only enabled when we know it's safe.
2288 pv_eoi_clr_pending(vcpu
);
2291 vector
= apic_set_eoi(apic
);
2292 trace_kvm_pv_eoi(apic
, vector
);
2295 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
2299 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
2300 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
2302 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2305 if (kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2309 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
2313 * apic_sync_pv_eoi_to_guest - called before vmentry
2315 * Detect whether it's safe to enable PV EOI and
2318 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
2319 struct kvm_lapic
*apic
)
2321 if (!pv_eoi_enabled(vcpu
) ||
2322 /* IRR set or many bits in ISR: could be nested. */
2323 apic
->irr_pending
||
2324 /* Cache not set: could be safe but we don't bother. */
2325 apic
->highest_isr_cache
== -1 ||
2326 /* Need EOI to update ioapic. */
2327 kvm_ioapic_handles_vector(apic
, apic
->highest_isr_cache
)) {
2329 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2330 * so we need not do anything here.
2335 pv_eoi_set_pending(apic
->vcpu
);
2338 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
2341 int max_irr
, max_isr
;
2342 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2344 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
2346 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
2349 tpr
= kvm_lapic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
2350 max_irr
= apic_find_highest_irr(apic
);
2353 max_isr
= apic_find_highest_isr(apic
);
2356 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
2358 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
2362 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
2365 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
2366 &vcpu
->arch
.apic
->vapic_cache
,
2367 vapic_addr
, sizeof(u32
)))
2369 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2371 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
2374 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
2378 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
2380 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2381 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
2383 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2386 if (reg
== APIC_ICR2
)
2389 /* if this is ICR write vector before command */
2390 if (reg
== APIC_ICR
)
2391 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2392 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2395 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
2397 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2398 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
2400 if (!lapic_in_kernel(vcpu
) || !apic_x2apic_mode(apic
))
2403 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
2404 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2409 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2411 if (reg
== APIC_ICR
)
2412 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2414 *data
= (((u64
)high
) << 32) | low
;
2419 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
2421 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2423 if (!lapic_in_kernel(vcpu
))
2426 /* if this is ICR write vector before command */
2427 if (reg
== APIC_ICR
)
2428 kvm_lapic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
2429 return kvm_lapic_reg_write(apic
, reg
, (u32
)data
);
2432 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
2434 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2437 if (!lapic_in_kernel(vcpu
))
2440 if (kvm_lapic_reg_read(apic
, reg
, 4, &low
))
2442 if (reg
== APIC_ICR
)
2443 kvm_lapic_reg_read(apic
, APIC_ICR2
, 4, &high
);
2445 *data
= (((u64
)high
) << 32) | low
;
2450 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
2452 u64 addr
= data
& ~KVM_MSR_ENABLED
;
2453 if (!IS_ALIGNED(addr
, 4))
2456 vcpu
->arch
.pv_eoi
.msr_val
= data
;
2457 if (!pv_eoi_enabled(vcpu
))
2459 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2463 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2465 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2469 if (!lapic_in_kernel(vcpu
) || !apic
->pending_events
)
2473 * INITs are latched while in SMM. Because an SMM CPU cannot
2474 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2475 * and delay processing of INIT until the next RSM.
2478 WARN_ON_ONCE(vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
);
2479 if (test_bit(KVM_APIC_SIPI
, &apic
->pending_events
))
2480 clear_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
2484 pe
= xchg(&apic
->pending_events
, 0);
2485 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2486 kvm_lapic_reset(vcpu
, true);
2487 kvm_vcpu_reset(vcpu
, true);
2488 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2489 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2491 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2493 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2494 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2495 /* evaluate pending_events before reading the vector */
2497 sipi_vector
= apic
->sipi_vector
;
2498 apic_debug("vcpu %d received sipi with vector # %x\n",
2499 vcpu
->vcpu_id
, sipi_vector
);
2500 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2501 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2505 void kvm_lapic_init(void)
2507 /* do not patch jump label more than once per second */
2508 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2509 jump_label_rate_limit(&apic_sw_disabled
, HZ
);
2512 void kvm_lapic_exit(void)
2514 static_key_deferred_flush(&apic_hw_disabled
);
2515 static_key_deferred_flush(&apic_sw_disabled
);