arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include <linux/kvm_host.h>
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/math64.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/atomic.h>
  35 #include "kvm_cache_regs.h"
  36 #include "irq.h"
  37
  38 #ifndef CONFIG_X86_64
  39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  40 #else
  41 #define mod_64(x, y) ((x) % (y))
  42 #endif
  43
  44 #define PRId64 "d"
  45 #define PRIx64 "llx"
  46 #define PRIu64 "u"
  47 #define PRIo64 "o"
  48
  49 #define APIC_BUS_CYCLE_NS 1
  50
  51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  52 #define apic_debug(fmt, arg...)
  53
  54 #define APIC_LVT_NUM                    6
  55 /* 14 is the version for Xeon and Pentium 8.4.8*/
  56 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  57 #define LAPIC_MMIO_LENGTH               (1 << 12)
  58 /* followed define is not in apicdef.h */
  59 #define APIC_SHORT_MASK                 0xc0000
  60 #define APIC_DEST_NOSHORT               0x0
  61 #define APIC_DEST_MASK                  0x800
  62 #define MAX_APIC_VECTOR                 256
  63
  64 #define VEC_POS(v) ((v) & (32 - 1))
  65 #define REG_POS(v) (((v) >> 5) << 4)
  66
  67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  68 {
  69         return *((u32 *) (apic->regs + reg_off));
  70 }
  71
  72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  73 {
  74         *((u32 *) (apic->regs + reg_off)) = val;
  75 }
  76
  77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  78 {
  79         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  80 }
  81
  82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  83 {
  84         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 static inline void apic_set_vector(int vec, void *bitmap)
  88 {
  89         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  90 }
  91
  92 static inline void apic_clear_vector(int vec, void *bitmap)
  93 {
  94         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  95 }
  96
  97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  98 {
  99         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 100 }
 101
 102 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 103 {
 104         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 105 }
 106
 107 static inline int apic_enabled(struct kvm_lapic *apic)
 108 {
 109         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 110 }
 111
 112 #define LVT_MASK        \
 113         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 114
 115 #define LINT_MASK       \
 116         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 117          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 118
 119 static inline int kvm_apic_id(struct kvm_lapic *apic)
 120 {
 121         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 122 }
 123
 124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 125 {
 126         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 127 }
 128
 129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 130 {
 131         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 132 }
 133
 134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 135 {
 136         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 137 }
 138
 139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 140 {
 141         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 142 }
 143
 144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 145         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 146         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 147         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 148         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 149         LVT_MASK                /* LVTERR */
 150 };
 151
 152 static int find_highest_vector(void *bitmap)
 153 {
 154         u32 *word = bitmap;
 155         int word_offset = MAX_APIC_VECTOR >> 5;
 156
 157         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 158                 continue;
 159
 160         if (likely(!word_offset && !word[0]))
 161                 return -1;
 162         else
 163                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 164 }
 165
 166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 167 {
 168         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 169 }
 170
 171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 172 {
 173         apic_clear_vector(vec, apic->regs + APIC_IRR);
 174 }
 175
 176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 177 {
 178         int result;
 179
 180         result = find_highest_vector(apic->regs + APIC_IRR);
 181         ASSERT(result == -1 || result >= 16);
 182
 183         return result;
 184 }
 185
 186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 187 {
 188         struct kvm_lapic *apic = vcpu->arch.apic;
 189         int highest_irr;
 190
 191         if (!apic)
 192                 return 0;
 193         highest_irr = apic_find_highest_irr(apic);
 194
 195         return highest_irr;
 196 }
 197 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 198
 199 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 200                              int vector, int level, int trig_mode);
 201
 202 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
 203 {
 204         struct kvm_lapic *apic = vcpu->arch.apic;
 205         int lapic_dmode;
 206
 207         switch (dmode) {
 208         case IOAPIC_LOWEST_PRIORITY:
 209                 lapic_dmode = APIC_DM_LOWEST;
 210                 break;
 211         case IOAPIC_FIXED:
 212                 lapic_dmode = APIC_DM_FIXED;
 213                 break;
 214         case IOAPIC_NMI:
 215                 lapic_dmode = APIC_DM_NMI;
 216                 break;
 217         default:
 218                 printk(KERN_DEBUG"Ignoring delivery mode %d\n", dmode);
 219                 return 0;
 220                 break;
 221         }
 222         return __apic_accept_irq(apic, lapic_dmode, vec, 1, trig);
 223 }
 224
 225 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 226 {
 227         int result;
 228
 229         result = find_highest_vector(apic->regs + APIC_ISR);
 230         ASSERT(result == -1 || result >= 16);
 231
 232         return result;
 233 }
 234
 235 static void apic_update_ppr(struct kvm_lapic *apic)
 236 {
 237         u32 tpr, isrv, ppr;
 238         int isr;
 239
 240         tpr = apic_get_reg(apic, APIC_TASKPRI);
 241         isr = apic_find_highest_isr(apic);
 242         isrv = (isr != -1) ? isr : 0;
 243
 244         if ((tpr & 0xf0) >= (isrv & 0xf0))
 245                 ppr = tpr & 0xff;
 246         else
 247                 ppr = isrv & 0xf0;
 248
 249         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 250                    apic, ppr, isr, isrv);
 251
 252         apic_set_reg(apic, APIC_PROCPRI, ppr);
 253 }
 254
 255 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 256 {
 257         apic_set_reg(apic, APIC_TASKPRI, tpr);
 258         apic_update_ppr(apic);
 259 }
 260
 261 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 262 {
 263         return dest == 0xff || kvm_apic_id(apic) == dest;
 264 }
 265
 266 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 267 {
 268         int result = 0;
 269         u8 logical_id;
 270
 271         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 272
 273         switch (apic_get_reg(apic, APIC_DFR)) {
 274         case APIC_DFR_FLAT:
 275                 if (logical_id & mda)
 276                         result = 1;
 277                 break;
 278         case APIC_DFR_CLUSTER:
 279                 if (((logical_id >> 4) == (mda >> 0x4))
 280                     && (logical_id & mda & 0xf))
 281                         result = 1;
 282                 break;
 283         default:
 284                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 285                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 286                 break;
 287         }
 288
 289         return result;
 290 }
 291
 292 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 293                            int short_hand, int dest, int dest_mode)
 294 {
 295         int result = 0;
 296         struct kvm_lapic *target = vcpu->arch.apic;
 297
 298         apic_debug("target %p, source %p, dest 0x%x, "
 299                    "dest_mode 0x%x, short_hand 0x%x\n",
 300                    target, source, dest, dest_mode, short_hand);
 301
 302         ASSERT(!target);
 303         switch (short_hand) {
 304         case APIC_DEST_NOSHORT:
 305                 if (dest_mode == 0)
 306                         /* Physical mode. */
 307                         result = kvm_apic_match_physical_addr(target, dest);
 308                 else
 309                         /* Logical mode. */
 310                         result = kvm_apic_match_logical_addr(target, dest);
 311                 break;
 312         case APIC_DEST_SELF:
 313                 result = (target == source);
 314                 break;
 315         case APIC_DEST_ALLINC:
 316                 result = 1;
 317                 break;
 318         case APIC_DEST_ALLBUT:
 319                 result = (target != source);
 320                 break;
 321         default:
 322                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 323                        short_hand);
 324                 break;
 325         }
 326
 327         return result;
 328 }
 329
 330 /*
 331  * Add a pending IRQ into lapic.
 332  * Return 1 if successfully added and 0 if discarded.
 333  */
 334 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 335                              int vector, int level, int trig_mode)
 336 {
 337         int result = 0;
 338         struct kvm_vcpu *vcpu = apic->vcpu;
 339
 340         switch (delivery_mode) {
 341         case APIC_DM_LOWEST:
 342                 vcpu->arch.apic_arb_prio++;
 343         case APIC_DM_FIXED:
 344                 /* FIXME add logic for vcpu on reset */
 345                 if (unlikely(!apic_enabled(apic)))
 346                         break;
 347
 348                 result = !apic_test_and_set_irr(vector, apic);
 349                 if (!result) {
 350                         if (trig_mode)
 351                                 apic_debug("level trig mode repeatedly for "
 352                                                 "vector %d", vector);
 353                         break;
 354                 }
 355
 356                 if (trig_mode) {
 357                         apic_debug("level trig mode for vector %d", vector);
 358                         apic_set_vector(vector, apic->regs + APIC_TMR);
 359                 } else
 360                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 361                 kvm_vcpu_kick(vcpu);
 362                 break;
 363
 364         case APIC_DM_REMRD:
 365                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 366                 break;
 367
 368         case APIC_DM_SMI:
 369                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 370                 break;
 371
 372         case APIC_DM_NMI:
 373                 result = 1;
 374                 kvm_inject_nmi(vcpu);
 375                 kvm_vcpu_kick(vcpu);
 376                 break;
 377
 378         case APIC_DM_INIT:
 379                 if (level) {
 380                         result = 1;
 381                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 382                                 printk(KERN_DEBUG
 383                                        "INIT on a runnable vcpu %d\n",
 384                                        vcpu->vcpu_id);
 385                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 386                         kvm_vcpu_kick(vcpu);
 387                 } else {
 388                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 389                                    vcpu->vcpu_id);
 390                 }
 391                 break;
 392
 393         case APIC_DM_STARTUP:
 394                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 395                            vcpu->vcpu_id, vector);
 396                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 397                         result = 1;
 398                         vcpu->arch.sipi_vector = vector;
 399                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 400                         kvm_vcpu_kick(vcpu);
 401                 }
 402                 break;
 403
 404         case APIC_DM_EXTINT:
 405                 /*
 406                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 407                  * before NMI watchdog was enabled. Already handled by
 408                  * kvm_apic_accept_pic_intr().
 409                  */
 410                 break;
 411
 412         default:
 413                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 414                        delivery_mode);
 415                 break;
 416         }
 417         return result;
 418 }
 419
 420 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 421 {
 422         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 423 }
 424
 425 static void apic_set_eoi(struct kvm_lapic *apic)
 426 {
 427         int vector = apic_find_highest_isr(apic);
 428         int trigger_mode;
 429         /*
 430          * Not every write EOI will has corresponding ISR,
 431          * one example is when Kernel check timer on setup_IO_APIC
 432          */
 433         if (vector == -1)
 434                 return;
 435
 436         apic_clear_vector(vector, apic->regs + APIC_ISR);
 437         apic_update_ppr(apic);
 438
 439         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 440                 trigger_mode = IOAPIC_LEVEL_TRIG;
 441         else
 442                 trigger_mode = IOAPIC_EDGE_TRIG;
 443         kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 444 }
 445
 446 static void apic_send_ipi(struct kvm_lapic *apic)
 447 {
 448         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 449         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 450
 451         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 452         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 453         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 454         unsigned int level = icr_low & APIC_INT_ASSERT;
 455         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 456         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 457         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 458
 459         DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
 460         int i;
 461
 462         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 463                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 464                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 465                    icr_high, icr_low, short_hand, dest,
 466                    trig_mode, level, dest_mode, delivery_mode, vector);
 467
 468         kvm_get_intr_delivery_bitmask(apic->vcpu->kvm, apic, dest, dest_mode,
 469                         delivery_mode == APIC_DM_LOWEST, short_hand,
 470                         deliver_bitmask);
 471
 472         while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
 473                         < KVM_MAX_VCPUS) {
 474                 struct kvm_vcpu *vcpu = apic->vcpu->kvm->vcpus[i];
 475                 __clear_bit(i, deliver_bitmask);
 476                 if (vcpu)
 477                         __apic_accept_irq(vcpu->arch.apic, delivery_mode,
 478                                         vector, level, trig_mode);
 479         }
 480 }
 481
 482 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 483 {
 484         ktime_t remaining;
 485         s64 ns;
 486         u32 tmcct;
 487
 488         ASSERT(apic != NULL);
 489
 490         /* if initial count is 0, current count should also be 0 */
 491         if (apic_get_reg(apic, APIC_TMICT) == 0)
 492                 return 0;
 493
 494         remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
 495         if (ktime_to_ns(remaining) < 0)
 496                 remaining = ktime_set(0, 0);
 497
 498         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 499         tmcct = div64_u64(ns,
 500                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 501
 502         return tmcct;
 503 }
 504
 505 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 506 {
 507         struct kvm_vcpu *vcpu = apic->vcpu;
 508         struct kvm_run *run = vcpu->run;
 509
 510         set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
 511         run->tpr_access.rip = kvm_rip_read(vcpu);
 512         run->tpr_access.is_write = write;
 513 }
 514
 515 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 516 {
 517         if (apic->vcpu->arch.tpr_access_reporting)
 518                 __report_tpr_access(apic, write);
 519 }
 520
 521 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 522 {
 523         u32 val = 0;
 524
 525         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 526
 527         if (offset >= LAPIC_MMIO_LENGTH)
 528                 return 0;
 529
 530         switch (offset) {
 531         case APIC_ARBPRI:
 532                 printk(KERN_WARNING "Access APIC ARBPRI register "
 533                        "which is for P6\n");
 534                 break;
 535
 536         case APIC_TMCCT:        /* Timer CCR */
 537                 val = apic_get_tmcct(apic);
 538                 break;
 539
 540         case APIC_TASKPRI:
 541                 report_tpr_access(apic, false);
 542                 /* fall thru */
 543         default:
 544                 apic_update_ppr(apic);
 545                 val = apic_get_reg(apic, offset);
 546                 break;
 547         }
 548
 549         return val;
 550 }
 551
 552 static void apic_mmio_read(struct kvm_io_device *this,
 553                            gpa_t address, int len, void *data)
 554 {
 555         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 556         unsigned int offset = address - apic->base_address;
 557         unsigned char alignment = offset & 0xf;
 558         u32 result;
 559
 560         if ((alignment + len) > 4) {
 561                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 562                        (unsigned long)address, len);
 563                 return;
 564         }
 565         result = __apic_read(apic, offset & ~0xf);
 566
 567         switch (len) {
 568         case 1:
 569         case 2:
 570         case 4:
 571                 memcpy(data, (char *)&result + alignment, len);
 572                 break;
 573         default:
 574                 printk(KERN_ERR "Local APIC read with len = %x, "
 575                        "should be 1,2, or 4 instead\n", len);
 576                 break;
 577         }
 578 }
 579
 580 static void update_divide_count(struct kvm_lapic *apic)
 581 {
 582         u32 tmp1, tmp2, tdcr;
 583
 584         tdcr = apic_get_reg(apic, APIC_TDCR);
 585         tmp1 = tdcr & 0xf;
 586         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 587         apic->divide_count = 0x1 << (tmp2 & 0x7);
 588
 589         apic_debug("timer divide count is 0x%x\n",
 590                                    apic->lapic_timer.divide_count);
 591 }
 592
 593 static void start_apic_timer(struct kvm_lapic *apic)
 594 {
 595         ktime_t now = apic->lapic_timer.timer.base->get_time();
 596
 597         apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
 598                     APIC_BUS_CYCLE_NS * apic->divide_count;
 599         atomic_set(&apic->lapic_timer.pending, 0);
 600
 601         if (!apic->lapic_timer.period)
 602                 return;
 603
 604         hrtimer_start(&apic->lapic_timer.timer,
 605                       ktime_add_ns(now, apic->lapic_timer.period),
 606                       HRTIMER_MODE_ABS);
 607
 608         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 609                            PRIx64 ", "
 610                            "timer initial count 0x%x, period %lldns, "
 611                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 612                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 613                            apic_get_reg(apic, APIC_TMICT),
 614                            apic->lapic_timer.period,
 615                            ktime_to_ns(ktime_add_ns(now,
 616                                         apic->lapic_timer.period)));
 617 }
 618
 619 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 620 {
 621         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 622
 623         if (apic_lvt_nmi_mode(lvt0_val)) {
 624                 if (!nmi_wd_enabled) {
 625                         apic_debug("Receive NMI setting on APIC_LVT0 "
 626                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 627                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 628                 }
 629         } else if (nmi_wd_enabled)
 630                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 631 }
 632
 633 static void apic_mmio_write(struct kvm_io_device *this,
 634                             gpa_t address, int len, const void *data)
 635 {
 636         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 637         unsigned int offset = address - apic->base_address;
 638         unsigned char alignment = offset & 0xf;
 639         u32 val;
 640
 641         /*
 642          * APIC register must be aligned on 128-bits boundary.
 643          * 32/64/128 bits registers must be accessed thru 32 bits.
 644          * Refer SDM 8.4.1
 645          */
 646         if (len != 4 || alignment) {
 647                 /* Don't shout loud, $infamous_os would cause only noise. */
 648                 apic_debug("apic write: bad size=%d %lx\n",
 649                            len, (long)address);
 650                 return;
 651         }
 652
 653         val = *(u32 *) data;
 654
 655         /* too common printing */
 656         if (offset != APIC_EOI)
 657                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 658                            "0x%x\n", __func__, offset, len, val);
 659
 660         offset &= 0xff0;
 661
 662         KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
 663
 664         switch (offset) {
 665         case APIC_ID:           /* Local APIC ID */
 666                 apic_set_reg(apic, APIC_ID, val);
 667                 break;
 668
 669         case APIC_TASKPRI:
 670                 report_tpr_access(apic, true);
 671                 apic_set_tpr(apic, val & 0xff);
 672                 break;
 673
 674         case APIC_EOI:
 675                 apic_set_eoi(apic);
 676                 break;
 677
 678         case APIC_LDR:
 679                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 680                 break;
 681
 682         case APIC_DFR:
 683                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 684                 break;
 685
 686         case APIC_SPIV:
 687                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 688                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 689                         int i;
 690                         u32 lvt_val;
 691
 692                         for (i = 0; i < APIC_LVT_NUM; i++) {
 693                                 lvt_val = apic_get_reg(apic,
 694                                                        APIC_LVTT + 0x10 * i);
 695                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 696                                              lvt_val | APIC_LVT_MASKED);
 697                         }
 698                         atomic_set(&apic->lapic_timer.pending, 0);
 699
 700                 }
 701                 break;
 702
 703         case APIC_ICR:
 704                 /* No delay here, so we always clear the pending bit */
 705                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 706                 apic_send_ipi(apic);
 707                 break;
 708
 709         case APIC_ICR2:
 710                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 711                 break;
 712
 713         case APIC_LVT0:
 714                 apic_manage_nmi_watchdog(apic, val);
 715         case APIC_LVTT:
 716         case APIC_LVTTHMR:
 717         case APIC_LVTPC:
 718         case APIC_LVT1:
 719         case APIC_LVTERR:
 720                 /* TODO: Check vector */
 721                 if (!apic_sw_enabled(apic))
 722                         val |= APIC_LVT_MASKED;
 723
 724                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 725                 apic_set_reg(apic, offset, val);
 726
 727                 break;
 728
 729         case APIC_TMICT:
 730                 hrtimer_cancel(&apic->lapic_timer.timer);
 731                 apic_set_reg(apic, APIC_TMICT, val);
 732                 start_apic_timer(apic);
 733                 return;
 734
 735         case APIC_TDCR:
 736                 if (val & 4)
 737                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 738                 apic_set_reg(apic, APIC_TDCR, val);
 739                 update_divide_count(apic);
 740                 break;
 741
 742         default:
 743                 apic_debug("Local APIC Write to read-only register %x\n",
 744                            offset);
 745                 break;
 746         }
 747
 748 }
 749
 750 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
 751                            int len, int size)
 752 {
 753         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 754         int ret = 0;
 755
 756
 757         if (apic_hw_enabled(apic) &&
 758             (addr >= apic->base_address) &&
 759             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 760                 ret = 1;
 761
 762         return ret;
 763 }
 764
 765 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 766 {
 767         if (!vcpu->arch.apic)
 768                 return;
 769
 770         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 771
 772         if (vcpu->arch.apic->regs_page)
 773                 __free_page(vcpu->arch.apic->regs_page);
 774
 775         kfree(vcpu->arch.apic);
 776 }
 777
 778 /*
 779  *----------------------------------------------------------------------
 780  * LAPIC interface
 781  *----------------------------------------------------------------------
 782  */
 783
 784 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 785 {
 786         struct kvm_lapic *apic = vcpu->arch.apic;
 787
 788         if (!apic)
 789                 return;
 790         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 791                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 792 }
 793 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 794
 795 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 796 {
 797         struct kvm_lapic *apic = vcpu->arch.apic;
 798         u64 tpr;
 799
 800         if (!apic)
 801                 return 0;
 802         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 803
 804         return (tpr & 0xf0) >> 4;
 805 }
 806 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 807
 808 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 809 {
 810         struct kvm_lapic *apic = vcpu->arch.apic;
 811
 812         if (!apic) {
 813                 value |= MSR_IA32_APICBASE_BSP;
 814                 vcpu->arch.apic_base = value;
 815                 return;
 816         }
 817         if (apic->vcpu->vcpu_id)
 818                 value &= ~MSR_IA32_APICBASE_BSP;
 819
 820         vcpu->arch.apic_base = value;
 821         apic->base_address = apic->vcpu->arch.apic_base &
 822                              MSR_IA32_APICBASE_BASE;
 823
 824         /* with FSB delivery interrupt, we can restart APIC functionality */
 825         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 826                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 827
 828 }
 829
 830 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 831 {
 832         return vcpu->arch.apic_base;
 833 }
 834 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 835
 836 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 837 {
 838         struct kvm_lapic *apic;
 839         int i;
 840
 841         apic_debug("%s\n", __func__);
 842
 843         ASSERT(vcpu);
 844         apic = vcpu->arch.apic;
 845         ASSERT(apic != NULL);
 846
 847         /* Stop the timer in case it's a reset to an active apic */
 848         hrtimer_cancel(&apic->lapic_timer.timer);
 849
 850         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 851         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 852
 853         for (i = 0; i < APIC_LVT_NUM; i++)
 854                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 855         apic_set_reg(apic, APIC_LVT0,
 856                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 857
 858         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 859         apic_set_reg(apic, APIC_SPIV, 0xff);
 860         apic_set_reg(apic, APIC_TASKPRI, 0);
 861         apic_set_reg(apic, APIC_LDR, 0);
 862         apic_set_reg(apic, APIC_ESR, 0);
 863         apic_set_reg(apic, APIC_ICR, 0);
 864         apic_set_reg(apic, APIC_ICR2, 0);
 865         apic_set_reg(apic, APIC_TDCR, 0);
 866         apic_set_reg(apic, APIC_TMICT, 0);
 867         for (i = 0; i < 8; i++) {
 868                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 869                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 870                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 871         }
 872         update_divide_count(apic);
 873         atomic_set(&apic->lapic_timer.pending, 0);
 874         if (vcpu->vcpu_id == 0)
 875                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 876         apic_update_ppr(apic);
 877
 878         vcpu->arch.apic_arb_prio = 0;
 879
 880         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 881                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 882                    vcpu, kvm_apic_id(apic),
 883                    vcpu->arch.apic_base, apic->base_address);
 884 }
 885 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 886
 887 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 888 {
 889         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 890 }
 891
 892 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 893 {
 894         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 895 }
 896 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 897
 898 /*
 899  *----------------------------------------------------------------------
 900  * timer interface
 901  *----------------------------------------------------------------------
 902  */
 903
 904 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 905 {
 906         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
 907                                               lapic_timer);
 908         return apic_lvtt_period(apic);
 909 }
 910
 911 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
 912 {
 913         struct kvm_lapic *lapic = vcpu->arch.apic;
 914
 915         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
 916                 return atomic_read(&lapic->lapic_timer.pending);
 917
 918         return 0;
 919 }
 920
 921 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 922 {
 923         u32 reg = apic_get_reg(apic, lvt_type);
 924         int vector, mode, trig_mode;
 925
 926         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 927                 vector = reg & APIC_VECTOR_MASK;
 928                 mode = reg & APIC_MODE_MASK;
 929                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
 930                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
 931         }
 932         return 0;
 933 }
 934
 935 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
 936 {
 937         struct kvm_lapic *apic = vcpu->arch.apic;
 938
 939         if (apic)
 940                 kvm_apic_local_deliver(apic, APIC_LVT0);
 941 }
 942
 943 struct kvm_timer_ops lapic_timer_ops = {
 944         .is_periodic = lapic_is_periodic,
 945 };
 946
 947 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 948 {
 949         struct kvm_lapic *apic;
 950
 951         ASSERT(vcpu != NULL);
 952         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 953
 954         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 955         if (!apic)
 956                 goto nomem;
 957
 958         vcpu->arch.apic = apic;
 959
 960         apic->regs_page = alloc_page(GFP_KERNEL);
 961         if (apic->regs_page == NULL) {
 962                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 963                        vcpu->vcpu_id);
 964                 goto nomem_free_apic;
 965         }
 966         apic->regs = page_address(apic->regs_page);
 967         memset(apic->regs, 0, PAGE_SIZE);
 968         apic->vcpu = vcpu;
 969
 970         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
 971                      HRTIMER_MODE_ABS);
 972         apic->lapic_timer.timer.function = kvm_timer_fn;
 973         apic->lapic_timer.t_ops = &lapic_timer_ops;
 974         apic->lapic_timer.kvm = vcpu->kvm;
 975         apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
 976
 977         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 978         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 979
 980         kvm_lapic_reset(vcpu);
 981         apic->dev.read = apic_mmio_read;
 982         apic->dev.write = apic_mmio_write;
 983         apic->dev.in_range = apic_mmio_range;
 984         apic->dev.private = apic;
 985
 986         return 0;
 987 nomem_free_apic:
 988         kfree(apic);
 989 nomem:
 990         return -ENOMEM;
 991 }
 992 EXPORT_SYMBOL_GPL(kvm_create_lapic);
 993
 994 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 995 {
 996         struct kvm_lapic *apic = vcpu->arch.apic;
 997         int highest_irr;
 998
 999         if (!apic || !apic_enabled(apic))
1000                 return -1;
1001
1002         apic_update_ppr(apic);
1003         highest_irr = apic_find_highest_irr(apic);
1004         if ((highest_irr == -1) ||
1005             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1006                 return -1;
1007         return highest_irr;
1008 }
1009
1010 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1011 {
1012         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1013         int r = 0;
1014
1015         if (vcpu->vcpu_id == 0) {
1016                 if (!apic_hw_enabled(vcpu->arch.apic))
1017                         r = 1;
1018                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1019                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1020                         r = 1;
1021         }
1022         return r;
1023 }
1024
1025 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1026 {
1027         struct kvm_lapic *apic = vcpu->arch.apic;
1028
1029         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1030                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1031                         atomic_dec(&apic->lapic_timer.pending);
1032         }
1033 }
1034
1035 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1036 {
1037         int vector = kvm_apic_has_interrupt(vcpu);
1038         struct kvm_lapic *apic = vcpu->arch.apic;
1039
1040         if (vector == -1)
1041                 return -1;
1042
1043         apic_set_vector(vector, apic->regs + APIC_ISR);
1044         apic_update_ppr(apic);
1045         apic_clear_irr(vector, apic);
1046         return vector;
1047 }
1048
1049 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1050 {
1051         struct kvm_lapic *apic = vcpu->arch.apic;
1052
1053         apic->base_address = vcpu->arch.apic_base &
1054                              MSR_IA32_APICBASE_BASE;
1055         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1056         apic_update_ppr(apic);
1057         hrtimer_cancel(&apic->lapic_timer.timer);
1058         update_divide_count(apic);
1059         start_apic_timer(apic);
1060 }
1061
1062 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1063 {
1064         struct kvm_lapic *apic = vcpu->arch.apic;
1065         struct hrtimer *timer;
1066
1067         if (!apic)
1068                 return;
1069
1070         timer = &apic->lapic_timer.timer;
1071         if (hrtimer_cancel(timer))
1072                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1073 }
1074
1075 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1076 {
1077         u32 data;
1078         void *vapic;
1079
1080         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1081                 return;
1082
1083         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1084         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1085         kunmap_atomic(vapic, KM_USER0);
1086
1087         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1088 }
1089
1090 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1091 {
1092         u32 data, tpr;
1093         int max_irr, max_isr;
1094         struct kvm_lapic *apic;
1095         void *vapic;
1096
1097         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1098                 return;
1099
1100         apic = vcpu->arch.apic;
1101         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1102         max_irr = apic_find_highest_irr(apic);
1103         if (max_irr < 0)
1104                 max_irr = 0;
1105         max_isr = apic_find_highest_isr(apic);
1106         if (max_isr < 0)
1107                 max_isr = 0;
1108         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1109
1110         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1111         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1112         kunmap_atomic(vapic, KM_USER0);
1113 }
1114
1115 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1116 {
1117         if (!irqchip_in_kernel(vcpu->kvm))
1118                 return;
1119
1120         vcpu->arch.apic->vapic_addr = vapic_addr;
1121 }