1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
55 extern bool itlb_multihit_kvm_mitigation
;
57 static int __read_mostly nx_huge_pages
= -1;
58 #ifdef CONFIG_PREEMPT_RT
59 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
60 static uint __read_mostly nx_huge_pages_recovery_ratio
= 0;
62 static uint __read_mostly nx_huge_pages_recovery_ratio
= 60;
65 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
);
66 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
);
68 static const struct kernel_param_ops nx_huge_pages_ops
= {
69 .set
= set_nx_huge_pages
,
70 .get
= param_get_bool
,
73 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops
= {
74 .set
= set_nx_huge_pages_recovery_ratio
,
75 .get
= param_get_uint
,
78 module_param_cb(nx_huge_pages
, &nx_huge_pages_ops
, &nx_huge_pages
, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages
, "bool");
80 module_param_cb(nx_huge_pages_recovery_ratio
, &nx_huge_pages_recovery_ratio_ops
,
81 &nx_huge_pages_recovery_ratio
, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio
, "uint");
84 static bool __read_mostly force_flush_and_sync_on_reuse
;
85 module_param_named(flush_on_reuse
, force_flush_and_sync_on_reuse
, bool, 0644);
88 * When setting this variable to true it enables Two-Dimensional-Paging
89 * where the hardware walks 2 page tables:
90 * 1. the guest-virtual to guest-physical
91 * 2. while doing 1. it walks guest-physical to host-physical
92 * If the hardware supports that we don't need to do shadow paging.
94 bool tdp_enabled
= false;
96 static int max_huge_page_level __read_mostly
;
97 static int max_tdp_level __read_mostly
;
100 AUDIT_PRE_PAGE_FAULT
,
101 AUDIT_POST_PAGE_FAULT
,
103 AUDIT_POST_PTE_WRITE
,
110 module_param(dbg
, bool, 0644);
113 #define PTE_PREFETCH_NUM 8
115 #define PT32_LEVEL_BITS 10
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
120 #define PT32_LVL_OFFSET_MASK(level) \
121 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT32_INDEX(address, level)\
125 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #include <trace/events/kvm.h>
137 /* make pte_list_desc fit well in cache line */
138 #define PTE_LIST_EXT 3
141 * Return values of handle_mmio_page_fault, mmu.page_fault, and fast_page_fault().
143 * RET_PF_RETRY: let CPU fault again on the address.
144 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
145 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
146 * RET_PF_FIXED: The faulting entry has been fixed.
147 * RET_PF_SPURIOUS: The faulting entry was already fixed, e.g. by another vCPU.
157 struct pte_list_desc
{
158 u64
*sptes
[PTE_LIST_EXT
];
159 struct pte_list_desc
*more
;
162 struct kvm_shadow_walk_iterator
{
170 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
171 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
173 shadow_walk_okay(&(_walker)); \
174 shadow_walk_next(&(_walker)))
176 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
177 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
178 shadow_walk_okay(&(_walker)); \
179 shadow_walk_next(&(_walker)))
181 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
182 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
183 shadow_walk_okay(&(_walker)) && \
184 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
185 __shadow_walk_next(&(_walker), spte))
187 static struct kmem_cache
*pte_list_desc_cache
;
188 struct kmem_cache
*mmu_page_header_cache
;
189 static struct percpu_counter kvm_total_used_mmu_pages
;
191 static void mmu_spte_set(u64
*sptep
, u64 spte
);
192 static union kvm_mmu_page_role
193 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
);
195 #define CREATE_TRACE_POINTS
196 #include "mmutrace.h"
199 static inline bool kvm_available_flush_tlb_with_range(void)
201 return kvm_x86_ops
.tlb_remote_flush_with_range
;
204 static void kvm_flush_remote_tlbs_with_range(struct kvm
*kvm
,
205 struct kvm_tlb_range
*range
)
209 if (range
&& kvm_x86_ops
.tlb_remote_flush_with_range
)
210 ret
= kvm_x86_ops
.tlb_remote_flush_with_range(kvm
, range
);
213 kvm_flush_remote_tlbs(kvm
);
216 void kvm_flush_remote_tlbs_with_address(struct kvm
*kvm
,
217 u64 start_gfn
, u64 pages
)
219 struct kvm_tlb_range range
;
221 range
.start_gfn
= start_gfn
;
224 kvm_flush_remote_tlbs_with_range(kvm
, &range
);
227 bool is_nx_huge_page_enabled(void)
229 return READ_ONCE(nx_huge_pages
);
232 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
235 u64 mask
= make_mmio_spte(vcpu
, gfn
, access
);
236 unsigned int gen
= get_mmio_spte_generation(mask
);
238 access
= mask
& ACC_ALL
;
240 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
241 mmu_spte_set(sptep
, mask
);
244 static gfn_t
get_mmio_spte_gfn(u64 spte
)
246 u64 gpa
= spte
& shadow_nonpresent_or_rsvd_lower_gfn_mask
;
248 gpa
|= (spte
>> shadow_nonpresent_or_rsvd_mask_len
)
249 & shadow_nonpresent_or_rsvd_mask
;
251 return gpa
>> PAGE_SHIFT
;
254 static unsigned get_mmio_spte_access(u64 spte
)
256 return spte
& shadow_mmio_access_mask
;
259 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
260 kvm_pfn_t pfn
, unsigned int access
)
262 if (unlikely(is_noslot_pfn(pfn
))) {
263 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
270 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
272 u64 kvm_gen
, spte_gen
, gen
;
274 gen
= kvm_vcpu_memslots(vcpu
)->generation
;
275 if (unlikely(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
))
278 kvm_gen
= gen
& MMIO_SPTE_GEN_MASK
;
279 spte_gen
= get_mmio_spte_generation(spte
);
281 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
282 return likely(kvm_gen
== spte_gen
);
285 static gpa_t
translate_gpa(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 access
,
286 struct x86_exception
*exception
)
288 /* Check if guest physical address doesn't exceed guest maximum */
289 if (kvm_vcpu_is_illegal_gpa(vcpu
, gpa
)) {
290 exception
->error_code
|= PFERR_RSVD_MASK
;
297 static int is_cpuid_PSE36(void)
302 static int is_nx(struct kvm_vcpu
*vcpu
)
304 return vcpu
->arch
.efer
& EFER_NX
;
307 static gfn_t
pse36_gfn_delta(u32 gpte
)
309 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
311 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
315 static void __set_spte(u64
*sptep
, u64 spte
)
317 WRITE_ONCE(*sptep
, spte
);
320 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
322 WRITE_ONCE(*sptep
, spte
);
325 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
327 return xchg(sptep
, spte
);
330 static u64
__get_spte_lockless(u64
*sptep
)
332 return READ_ONCE(*sptep
);
343 static void count_spte_clear(u64
*sptep
, u64 spte
)
345 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
347 if (is_shadow_present_pte(spte
))
350 /* Ensure the spte is completely set before we increase the count */
352 sp
->clear_spte_count
++;
355 static void __set_spte(u64
*sptep
, u64 spte
)
357 union split_spte
*ssptep
, sspte
;
359 ssptep
= (union split_spte
*)sptep
;
360 sspte
= (union split_spte
)spte
;
362 ssptep
->spte_high
= sspte
.spte_high
;
365 * If we map the spte from nonpresent to present, We should store
366 * the high bits firstly, then set present bit, so cpu can not
367 * fetch this spte while we are setting the spte.
371 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
374 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
376 union split_spte
*ssptep
, sspte
;
378 ssptep
= (union split_spte
*)sptep
;
379 sspte
= (union split_spte
)spte
;
381 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
384 * If we map the spte from present to nonpresent, we should clear
385 * present bit firstly to avoid vcpu fetch the old high bits.
389 ssptep
->spte_high
= sspte
.spte_high
;
390 count_spte_clear(sptep
, spte
);
393 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
395 union split_spte
*ssptep
, sspte
, orig
;
397 ssptep
= (union split_spte
*)sptep
;
398 sspte
= (union split_spte
)spte
;
400 /* xchg acts as a barrier before the setting of the high bits */
401 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
402 orig
.spte_high
= ssptep
->spte_high
;
403 ssptep
->spte_high
= sspte
.spte_high
;
404 count_spte_clear(sptep
, spte
);
410 * The idea using the light way get the spte on x86_32 guest is from
411 * gup_get_pte (mm/gup.c).
413 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
414 * coalesces them and we are running out of the MMU lock. Therefore
415 * we need to protect against in-progress updates of the spte.
417 * Reading the spte while an update is in progress may get the old value
418 * for the high part of the spte. The race is fine for a present->non-present
419 * change (because the high part of the spte is ignored for non-present spte),
420 * but for a present->present change we must reread the spte.
422 * All such changes are done in two steps (present->non-present and
423 * non-present->present), hence it is enough to count the number of
424 * present->non-present updates: if it changed while reading the spte,
425 * we might have hit the race. This is done using clear_spte_count.
427 static u64
__get_spte_lockless(u64
*sptep
)
429 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
430 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
434 count
= sp
->clear_spte_count
;
437 spte
.spte_low
= orig
->spte_low
;
440 spte
.spte_high
= orig
->spte_high
;
443 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
444 count
!= sp
->clear_spte_count
))
451 static bool spte_has_volatile_bits(u64 spte
)
453 if (!is_shadow_present_pte(spte
))
457 * Always atomically update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_can_locklessly_be_made_writable(spte
) ||
463 is_access_track_spte(spte
))
466 if (spte_ad_enabled(spte
)) {
467 if ((spte
& shadow_accessed_mask
) == 0 ||
468 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
475 /* Rules for using mmu_spte_set:
476 * Set the sptep from nonpresent to present.
477 * Note: the sptep being assigned *must* be either not present
478 * or in a state where the hardware will not attempt to update
481 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
483 WARN_ON(is_shadow_present_pte(*sptep
));
484 __set_spte(sptep
, new_spte
);
488 * Update the SPTE (excluding the PFN), but do not track changes in its
489 * accessed/dirty status.
491 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
493 u64 old_spte
= *sptep
;
495 WARN_ON(!is_shadow_present_pte(new_spte
));
497 if (!is_shadow_present_pte(old_spte
)) {
498 mmu_spte_set(sptep
, new_spte
);
502 if (!spte_has_volatile_bits(old_spte
))
503 __update_clear_spte_fast(sptep
, new_spte
);
505 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
507 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
512 /* Rules for using mmu_spte_update:
513 * Update the state bits, it means the mapped pfn is not changed.
515 * Whenever we overwrite a writable spte with a read-only one we
516 * should flush remote TLBs. Otherwise rmap_write_protect
517 * will find a read-only spte, even though the writable spte
518 * might be cached on a CPU's TLB, the return value indicates this
521 * Returns true if the TLB needs to be flushed
523 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
526 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
528 if (!is_shadow_present_pte(old_spte
))
532 * For the spte updated out of mmu-lock is safe, since
533 * we always atomically update it, see the comments in
534 * spte_has_volatile_bits().
536 if (spte_can_locklessly_be_made_writable(old_spte
) &&
537 !is_writable_pte(new_spte
))
541 * Flush TLB when accessed/dirty states are changed in the page tables,
542 * to guarantee consistency between TLB and page tables.
545 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
547 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
550 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
552 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
559 * Rules for using mmu_spte_clear_track_bits:
560 * It sets the sptep from present to nonpresent, and track the
561 * state bits, it is used to clear the last level sptep.
562 * Returns non-zero if the PTE was previously valid.
564 static int mmu_spte_clear_track_bits(u64
*sptep
)
567 u64 old_spte
= *sptep
;
569 if (!spte_has_volatile_bits(old_spte
))
570 __update_clear_spte_fast(sptep
, 0ull);
572 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
574 if (!is_shadow_present_pte(old_spte
))
577 pfn
= spte_to_pfn(old_spte
);
580 * KVM does not hold the refcount of the page used by
581 * kvm mmu, before reclaiming the page, we should
582 * unmap it from mmu first.
584 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
586 if (is_accessed_spte(old_spte
))
587 kvm_set_pfn_accessed(pfn
);
589 if (is_dirty_spte(old_spte
))
590 kvm_set_pfn_dirty(pfn
);
596 * Rules for using mmu_spte_clear_no_track:
597 * Directly clear spte without caring the state bits of sptep,
598 * it is used to set the upper level spte.
600 static void mmu_spte_clear_no_track(u64
*sptep
)
602 __update_clear_spte_fast(sptep
, 0ull);
605 static u64
mmu_spte_get_lockless(u64
*sptep
)
607 return __get_spte_lockless(sptep
);
610 /* Restore an acc-track PTE back to a regular PTE */
611 static u64
restore_acc_track_spte(u64 spte
)
614 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
615 & shadow_acc_track_saved_bits_mask
;
617 WARN_ON_ONCE(spte_ad_enabled(spte
));
618 WARN_ON_ONCE(!is_access_track_spte(spte
));
620 new_spte
&= ~shadow_acc_track_mask
;
621 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
622 shadow_acc_track_saved_bits_shift
);
623 new_spte
|= saved_bits
;
628 /* Returns the Accessed status of the PTE and resets it at the same time. */
629 static bool mmu_spte_age(u64
*sptep
)
631 u64 spte
= mmu_spte_get_lockless(sptep
);
633 if (!is_accessed_spte(spte
))
636 if (spte_ad_enabled(spte
)) {
637 clear_bit((ffs(shadow_accessed_mask
) - 1),
638 (unsigned long *)sptep
);
641 * Capture the dirty status of the page, so that it doesn't get
642 * lost when the SPTE is marked for access tracking.
644 if (is_writable_pte(spte
))
645 kvm_set_pfn_dirty(spte_to_pfn(spte
));
647 spte
= mark_spte_for_access_track(spte
);
648 mmu_spte_update_no_track(sptep
, spte
);
654 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
657 * Prevent page table teardown by making any free-er wait during
658 * kvm_flush_remote_tlbs() IPI to all active vcpus.
663 * Make sure a following spte read is not reordered ahead of the write
666 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
669 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
672 * Make sure the write to vcpu->mode is not reordered in front of
673 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
674 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
676 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
680 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
, bool maybe_indirect
)
684 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
685 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
686 1 + PT64_ROOT_MAX_LEVEL
+ PTE_PREFETCH_NUM
);
689 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
,
690 PT64_ROOT_MAX_LEVEL
);
693 if (maybe_indirect
) {
694 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
,
695 PT64_ROOT_MAX_LEVEL
);
699 return kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
700 PT64_ROOT_MAX_LEVEL
);
703 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
705 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
);
706 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
);
707 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
);
708 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
);
711 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
713 return kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
716 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
718 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
721 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
723 if (!sp
->role
.direct
)
724 return sp
->gfns
[index
];
726 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
729 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
731 if (!sp
->role
.direct
) {
732 sp
->gfns
[index
] = gfn
;
736 if (WARN_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
)))
737 pr_err_ratelimited("gfn mismatch under direct page %llx "
738 "(expected %llx, got %llx)\n",
740 kvm_mmu_page_get_gfn(sp
, index
), gfn
);
744 * Return the pointer to the large page information for a given gfn,
745 * handling slots that are not large page aligned.
747 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
748 struct kvm_memory_slot
*slot
,
753 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
754 return &slot
->arch
.lpage_info
[level
- 2][idx
];
757 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
758 gfn_t gfn
, int count
)
760 struct kvm_lpage_info
*linfo
;
763 for (i
= PG_LEVEL_2M
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
764 linfo
= lpage_info_slot(gfn
, slot
, i
);
765 linfo
->disallow_lpage
+= count
;
766 WARN_ON(linfo
->disallow_lpage
< 0);
770 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
772 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
775 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
777 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
780 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
782 struct kvm_memslots
*slots
;
783 struct kvm_memory_slot
*slot
;
786 kvm
->arch
.indirect_shadow_pages
++;
788 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
789 slot
= __gfn_to_memslot(slots
, gfn
);
791 /* the non-leaf shadow pages are keeping readonly. */
792 if (sp
->role
.level
> PG_LEVEL_4K
)
793 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
794 KVM_PAGE_TRACK_WRITE
);
796 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
799 static void account_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
801 if (sp
->lpage_disallowed
)
804 ++kvm
->stat
.nx_lpage_splits
;
805 list_add_tail(&sp
->lpage_disallowed_link
,
806 &kvm
->arch
.lpage_disallowed_mmu_pages
);
807 sp
->lpage_disallowed
= true;
810 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
812 struct kvm_memslots
*slots
;
813 struct kvm_memory_slot
*slot
;
816 kvm
->arch
.indirect_shadow_pages
--;
818 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
819 slot
= __gfn_to_memslot(slots
, gfn
);
820 if (sp
->role
.level
> PG_LEVEL_4K
)
821 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
822 KVM_PAGE_TRACK_WRITE
);
824 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
827 static void unaccount_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
829 --kvm
->stat
.nx_lpage_splits
;
830 sp
->lpage_disallowed
= false;
831 list_del(&sp
->lpage_disallowed_link
);
834 static struct kvm_memory_slot
*
835 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
838 struct kvm_memory_slot
*slot
;
840 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
841 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
843 if (no_dirty_log
&& slot
->dirty_bitmap
)
850 * About rmap_head encoding:
852 * If the bit zero of rmap_head->val is clear, then it points to the only spte
853 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
854 * pte_list_desc containing more mappings.
858 * Returns the number of pointers in the rmap chain, not counting the new one.
860 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
861 struct kvm_rmap_head
*rmap_head
)
863 struct pte_list_desc
*desc
;
866 if (!rmap_head
->val
) {
867 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
868 rmap_head
->val
= (unsigned long)spte
;
869 } else if (!(rmap_head
->val
& 1)) {
870 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
871 desc
= mmu_alloc_pte_list_desc(vcpu
);
872 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
873 desc
->sptes
[1] = spte
;
874 rmap_head
->val
= (unsigned long)desc
| 1;
877 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
878 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
879 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
881 count
+= PTE_LIST_EXT
;
883 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
884 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
887 for (i
= 0; desc
->sptes
[i
]; ++i
)
889 desc
->sptes
[i
] = spte
;
895 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
896 struct pte_list_desc
*desc
, int i
,
897 struct pte_list_desc
*prev_desc
)
901 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
903 desc
->sptes
[i
] = desc
->sptes
[j
];
904 desc
->sptes
[j
] = NULL
;
907 if (!prev_desc
&& !desc
->more
)
911 prev_desc
->more
= desc
->more
;
913 rmap_head
->val
= (unsigned long)desc
->more
| 1;
914 mmu_free_pte_list_desc(desc
);
917 static void __pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
919 struct pte_list_desc
*desc
;
920 struct pte_list_desc
*prev_desc
;
923 if (!rmap_head
->val
) {
924 pr_err("%s: %p 0->BUG\n", __func__
, spte
);
926 } else if (!(rmap_head
->val
& 1)) {
927 rmap_printk("%s: %p 1->0\n", __func__
, spte
);
928 if ((u64
*)rmap_head
->val
!= spte
) {
929 pr_err("%s: %p 1->BUG\n", __func__
, spte
);
934 rmap_printk("%s: %p many->many\n", __func__
, spte
);
935 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
938 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
939 if (desc
->sptes
[i
] == spte
) {
940 pte_list_desc_remove_entry(rmap_head
,
948 pr_err("%s: %p many->many\n", __func__
, spte
);
953 static void pte_list_remove(struct kvm_rmap_head
*rmap_head
, u64
*sptep
)
955 mmu_spte_clear_track_bits(sptep
);
956 __pte_list_remove(sptep
, rmap_head
);
959 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
960 struct kvm_memory_slot
*slot
)
964 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
965 return &slot
->arch
.rmap
[level
- PG_LEVEL_4K
][idx
];
968 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
969 struct kvm_mmu_page
*sp
)
971 struct kvm_memslots
*slots
;
972 struct kvm_memory_slot
*slot
;
974 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
975 slot
= __gfn_to_memslot(slots
, gfn
);
976 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
979 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
981 struct kvm_mmu_memory_cache
*mc
;
983 mc
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
984 return kvm_mmu_memory_cache_nr_free_objects(mc
);
987 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
989 struct kvm_mmu_page
*sp
;
990 struct kvm_rmap_head
*rmap_head
;
992 sp
= sptep_to_sp(spte
);
993 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
994 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
995 return pte_list_add(vcpu
, spte
, rmap_head
);
998 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1000 struct kvm_mmu_page
*sp
;
1002 struct kvm_rmap_head
*rmap_head
;
1004 sp
= sptep_to_sp(spte
);
1005 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1006 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1007 __pte_list_remove(spte
, rmap_head
);
1011 * Used by the following functions to iterate through the sptes linked by a
1012 * rmap. All fields are private and not assumed to be used outside.
1014 struct rmap_iterator
{
1015 /* private fields */
1016 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1017 int pos
; /* index of the sptep */
1021 * Iteration must be started by this function. This should also be used after
1022 * removing/dropping sptes from the rmap link because in such cases the
1023 * information in the iterator may not be valid.
1025 * Returns sptep if found, NULL otherwise.
1027 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1028 struct rmap_iterator
*iter
)
1032 if (!rmap_head
->val
)
1035 if (!(rmap_head
->val
& 1)) {
1037 sptep
= (u64
*)rmap_head
->val
;
1041 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1043 sptep
= iter
->desc
->sptes
[iter
->pos
];
1045 BUG_ON(!is_shadow_present_pte(*sptep
));
1050 * Must be used with a valid iterator: e.g. after rmap_get_first().
1052 * Returns sptep if found, NULL otherwise.
1054 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1059 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1061 sptep
= iter
->desc
->sptes
[iter
->pos
];
1066 iter
->desc
= iter
->desc
->more
;
1070 /* desc->sptes[0] cannot be NULL */
1071 sptep
= iter
->desc
->sptes
[iter
->pos
];
1078 BUG_ON(!is_shadow_present_pte(*sptep
));
1082 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1083 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1084 _spte_; _spte_ = rmap_get_next(_iter_))
1086 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1088 if (mmu_spte_clear_track_bits(sptep
))
1089 rmap_remove(kvm
, sptep
);
1093 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1095 if (is_large_pte(*sptep
)) {
1096 WARN_ON(sptep_to_sp(sptep
)->role
.level
== PG_LEVEL_4K
);
1097 drop_spte(kvm
, sptep
);
1105 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1107 if (__drop_large_spte(vcpu
->kvm
, sptep
)) {
1108 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
1110 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1111 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1116 * Write-protect on the specified @sptep, @pt_protect indicates whether
1117 * spte write-protection is caused by protecting shadow page table.
1119 * Note: write protection is difference between dirty logging and spte
1121 * - for dirty logging, the spte can be set to writable at anytime if
1122 * its dirty bitmap is properly set.
1123 * - for spte protection, the spte can be writable only after unsync-ing
1126 * Return true if tlb need be flushed.
1128 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1132 if (!is_writable_pte(spte
) &&
1133 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1136 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1139 spte
&= ~SPTE_MMU_WRITEABLE
;
1140 spte
= spte
& ~PT_WRITABLE_MASK
;
1142 return mmu_spte_update(sptep
, spte
);
1145 static bool __rmap_write_protect(struct kvm
*kvm
,
1146 struct kvm_rmap_head
*rmap_head
,
1150 struct rmap_iterator iter
;
1153 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1154 flush
|= spte_write_protect(sptep
, pt_protect
);
1159 static bool spte_clear_dirty(u64
*sptep
)
1163 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1165 MMU_WARN_ON(!spte_ad_enabled(spte
));
1166 spte
&= ~shadow_dirty_mask
;
1167 return mmu_spte_update(sptep
, spte
);
1170 static bool spte_wrprot_for_clear_dirty(u64
*sptep
)
1172 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1173 (unsigned long *)sptep
);
1174 if (was_writable
&& !spte_ad_enabled(*sptep
))
1175 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1177 return was_writable
;
1181 * Gets the GFN ready for another round of dirty logging by clearing the
1182 * - D bit on ad-enabled SPTEs, and
1183 * - W bit on ad-disabled SPTEs.
1184 * Returns true iff any D or W bits were cleared.
1186 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1189 struct rmap_iterator iter
;
1192 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1193 if (spte_ad_need_write_protect(*sptep
))
1194 flush
|= spte_wrprot_for_clear_dirty(sptep
);
1196 flush
|= spte_clear_dirty(sptep
);
1201 static bool spte_set_dirty(u64
*sptep
)
1205 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1208 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1209 * do not bother adding back write access to pages marked
1210 * SPTE_AD_WRPROT_ONLY_MASK.
1212 spte
|= shadow_dirty_mask
;
1214 return mmu_spte_update(sptep
, spte
);
1217 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1220 struct rmap_iterator iter
;
1223 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1224 if (spte_ad_enabled(*sptep
))
1225 flush
|= spte_set_dirty(sptep
);
1231 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1232 * @kvm: kvm instance
1233 * @slot: slot to protect
1234 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1235 * @mask: indicates which pages we should protect
1237 * Used when we do not need to care about huge page mappings: e.g. during dirty
1238 * logging we do not have any such mappings.
1240 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1241 struct kvm_memory_slot
*slot
,
1242 gfn_t gfn_offset
, unsigned long mask
)
1244 struct kvm_rmap_head
*rmap_head
;
1247 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1249 __rmap_write_protect(kvm
, rmap_head
, false);
1251 /* clear the first set bit */
1257 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1258 * protect the page if the D-bit isn't supported.
1259 * @kvm: kvm instance
1260 * @slot: slot to clear D-bit
1261 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1262 * @mask: indicates which pages we should clear D-bit
1264 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1266 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1267 struct kvm_memory_slot
*slot
,
1268 gfn_t gfn_offset
, unsigned long mask
)
1270 struct kvm_rmap_head
*rmap_head
;
1273 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1275 __rmap_clear_dirty(kvm
, rmap_head
);
1277 /* clear the first set bit */
1281 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1284 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1287 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1288 * enable dirty logging for them.
1290 * Used when we do not need to care about huge page mappings: e.g. during dirty
1291 * logging we do not have any such mappings.
1293 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1294 struct kvm_memory_slot
*slot
,
1295 gfn_t gfn_offset
, unsigned long mask
)
1297 if (kvm_x86_ops
.enable_log_dirty_pt_masked
)
1298 kvm_x86_ops
.enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1301 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1304 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1305 struct kvm_memory_slot
*slot
, u64 gfn
)
1307 struct kvm_rmap_head
*rmap_head
;
1309 bool write_protected
= false;
1311 for (i
= PG_LEVEL_4K
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
1312 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1313 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1316 return write_protected
;
1319 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1321 struct kvm_memory_slot
*slot
;
1323 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1324 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1327 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1330 struct rmap_iterator iter
;
1333 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1334 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1336 pte_list_remove(rmap_head
, sptep
);
1343 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1344 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1347 return kvm_zap_rmapp(kvm
, rmap_head
);
1350 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1351 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1355 struct rmap_iterator iter
;
1358 pte_t
*ptep
= (pte_t
*)data
;
1361 WARN_ON(pte_huge(*ptep
));
1362 new_pfn
= pte_pfn(*ptep
);
1365 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1366 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1367 sptep
, *sptep
, gfn
, level
);
1371 if (pte_write(*ptep
)) {
1372 pte_list_remove(rmap_head
, sptep
);
1375 new_spte
= kvm_mmu_changed_pte_notifier_make_spte(
1378 mmu_spte_clear_track_bits(sptep
);
1379 mmu_spte_set(sptep
, new_spte
);
1383 if (need_flush
&& kvm_available_flush_tlb_with_range()) {
1384 kvm_flush_remote_tlbs_with_address(kvm
, gfn
, 1);
1391 struct slot_rmap_walk_iterator
{
1393 struct kvm_memory_slot
*slot
;
1399 /* output fields. */
1401 struct kvm_rmap_head
*rmap
;
1404 /* private field. */
1405 struct kvm_rmap_head
*end_rmap
;
1409 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1411 iterator
->level
= level
;
1412 iterator
->gfn
= iterator
->start_gfn
;
1413 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1414 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1419 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1420 struct kvm_memory_slot
*slot
, int start_level
,
1421 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1423 iterator
->slot
= slot
;
1424 iterator
->start_level
= start_level
;
1425 iterator
->end_level
= end_level
;
1426 iterator
->start_gfn
= start_gfn
;
1427 iterator
->end_gfn
= end_gfn
;
1429 rmap_walk_init_level(iterator
, iterator
->start_level
);
1432 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1434 return !!iterator
->rmap
;
1437 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1439 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1440 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1444 if (++iterator
->level
> iterator
->end_level
) {
1445 iterator
->rmap
= NULL
;
1449 rmap_walk_init_level(iterator
, iterator
->level
);
1452 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1453 _start_gfn, _end_gfn, _iter_) \
1454 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1455 _end_level_, _start_gfn, _end_gfn); \
1456 slot_rmap_walk_okay(_iter_); \
1457 slot_rmap_walk_next(_iter_))
1459 static int kvm_handle_hva_range(struct kvm
*kvm
,
1460 unsigned long start
,
1463 int (*handler
)(struct kvm
*kvm
,
1464 struct kvm_rmap_head
*rmap_head
,
1465 struct kvm_memory_slot
*slot
,
1468 unsigned long data
))
1470 struct kvm_memslots
*slots
;
1471 struct kvm_memory_slot
*memslot
;
1472 struct slot_rmap_walk_iterator iterator
;
1476 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1477 slots
= __kvm_memslots(kvm
, i
);
1478 kvm_for_each_memslot(memslot
, slots
) {
1479 unsigned long hva_start
, hva_end
;
1480 gfn_t gfn_start
, gfn_end
;
1482 hva_start
= max(start
, memslot
->userspace_addr
);
1483 hva_end
= min(end
, memslot
->userspace_addr
+
1484 (memslot
->npages
<< PAGE_SHIFT
));
1485 if (hva_start
>= hva_end
)
1488 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1489 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1491 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1492 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1494 for_each_slot_rmap_range(memslot
, PG_LEVEL_4K
,
1495 KVM_MAX_HUGEPAGE_LEVEL
,
1496 gfn_start
, gfn_end
- 1,
1498 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1499 iterator
.gfn
, iterator
.level
, data
);
1506 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1508 int (*handler
)(struct kvm
*kvm
,
1509 struct kvm_rmap_head
*rmap_head
,
1510 struct kvm_memory_slot
*slot
,
1511 gfn_t gfn
, int level
,
1512 unsigned long data
))
1514 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1517 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
,
1520 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1523 int kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1525 return kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1528 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1529 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1533 struct rmap_iterator iter
;
1536 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1537 young
|= mmu_spte_age(sptep
);
1539 trace_kvm_age_page(gfn
, level
, slot
, young
);
1543 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1544 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1545 int level
, unsigned long data
)
1548 struct rmap_iterator iter
;
1550 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1551 if (is_accessed_spte(*sptep
))
1556 #define RMAP_RECYCLE_THRESHOLD 1000
1558 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1560 struct kvm_rmap_head
*rmap_head
;
1561 struct kvm_mmu_page
*sp
;
1563 sp
= sptep_to_sp(spte
);
1565 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1567 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1568 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1569 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1572 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1574 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1577 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1579 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1583 static int is_empty_shadow_page(u64
*spt
)
1588 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1589 if (is_shadow_present_pte(*pos
)) {
1590 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1599 * This value is the sum of all of the kvm instances's
1600 * kvm->arch.n_used_mmu_pages values. We need a global,
1601 * aggregate version in order to make the slab shrinker
1604 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, unsigned long nr
)
1606 kvm
->arch
.n_used_mmu_pages
+= nr
;
1607 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1610 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1612 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1613 hlist_del(&sp
->hash_link
);
1614 list_del(&sp
->link
);
1615 free_page((unsigned long)sp
->spt
);
1616 if (!sp
->role
.direct
)
1617 free_page((unsigned long)sp
->gfns
);
1618 kmem_cache_free(mmu_page_header_cache
, sp
);
1621 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1623 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1626 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1627 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1632 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1635 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1638 __pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1641 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1644 mmu_page_remove_parent_pte(sp
, parent_pte
);
1645 mmu_spte_clear_no_track(parent_pte
);
1648 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1650 struct kvm_mmu_page
*sp
;
1652 sp
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1653 sp
->spt
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_shadow_page_cache
);
1655 sp
->gfns
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_gfn_array_cache
);
1656 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1659 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1660 * depends on valid pages being added to the head of the list. See
1661 * comments in kvm_zap_obsolete_pages().
1663 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
1664 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1665 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1669 static void mark_unsync(u64
*spte
);
1670 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1673 struct rmap_iterator iter
;
1675 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1680 static void mark_unsync(u64
*spte
)
1682 struct kvm_mmu_page
*sp
;
1685 sp
= sptep_to_sp(spte
);
1686 index
= spte
- sp
->spt
;
1687 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1689 if (sp
->unsync_children
++)
1691 kvm_mmu_mark_parents_unsync(sp
);
1694 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1695 struct kvm_mmu_page
*sp
)
1700 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1701 struct kvm_mmu_page
*sp
, u64
*spte
,
1707 #define KVM_PAGE_ARRAY_NR 16
1709 struct kvm_mmu_pages
{
1710 struct mmu_page_and_offset
{
1711 struct kvm_mmu_page
*sp
;
1713 } page
[KVM_PAGE_ARRAY_NR
];
1717 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1723 for (i
=0; i
< pvec
->nr
; i
++)
1724 if (pvec
->page
[i
].sp
== sp
)
1727 pvec
->page
[pvec
->nr
].sp
= sp
;
1728 pvec
->page
[pvec
->nr
].idx
= idx
;
1730 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1733 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1735 --sp
->unsync_children
;
1736 WARN_ON((int)sp
->unsync_children
< 0);
1737 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1740 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1741 struct kvm_mmu_pages
*pvec
)
1743 int i
, ret
, nr_unsync_leaf
= 0;
1745 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1746 struct kvm_mmu_page
*child
;
1747 u64 ent
= sp
->spt
[i
];
1749 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1750 clear_unsync_child_bit(sp
, i
);
1754 child
= to_shadow_page(ent
& PT64_BASE_ADDR_MASK
);
1756 if (child
->unsync_children
) {
1757 if (mmu_pages_add(pvec
, child
, i
))
1760 ret
= __mmu_unsync_walk(child
, pvec
);
1762 clear_unsync_child_bit(sp
, i
);
1764 } else if (ret
> 0) {
1765 nr_unsync_leaf
+= ret
;
1768 } else if (child
->unsync
) {
1770 if (mmu_pages_add(pvec
, child
, i
))
1773 clear_unsync_child_bit(sp
, i
);
1776 return nr_unsync_leaf
;
1779 #define INVALID_INDEX (-1)
1781 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1782 struct kvm_mmu_pages
*pvec
)
1785 if (!sp
->unsync_children
)
1788 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1789 return __mmu_unsync_walk(sp
, pvec
);
1792 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1794 WARN_ON(!sp
->unsync
);
1795 trace_kvm_mmu_sync_page(sp
);
1797 --kvm
->stat
.mmu_unsync
;
1800 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1801 struct list_head
*invalid_list
);
1802 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1803 struct list_head
*invalid_list
);
1805 #define for_each_valid_sp(_kvm, _sp, _list) \
1806 hlist_for_each_entry(_sp, _list, hash_link) \
1807 if (is_obsolete_sp((_kvm), (_sp))) { \
1810 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1811 for_each_valid_sp(_kvm, _sp, \
1812 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1813 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1815 static inline bool is_ept_sp(struct kvm_mmu_page
*sp
)
1817 return sp
->role
.cr0_wp
&& sp
->role
.smap_andnot_wp
;
1820 /* @sp->gfn should be write-protected at the call site */
1821 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1822 struct list_head
*invalid_list
)
1824 if ((!is_ept_sp(sp
) && sp
->role
.gpte_is_8_bytes
!= !!is_pae(vcpu
)) ||
1825 vcpu
->arch
.mmu
->sync_page(vcpu
, sp
) == 0) {
1826 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1833 static bool kvm_mmu_remote_flush_or_zap(struct kvm
*kvm
,
1834 struct list_head
*invalid_list
,
1837 if (!remote_flush
&& list_empty(invalid_list
))
1840 if (!list_empty(invalid_list
))
1841 kvm_mmu_commit_zap_page(kvm
, invalid_list
);
1843 kvm_flush_remote_tlbs(kvm
);
1847 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1848 struct list_head
*invalid_list
,
1849 bool remote_flush
, bool local_flush
)
1851 if (kvm_mmu_remote_flush_or_zap(vcpu
->kvm
, invalid_list
, remote_flush
))
1855 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
1858 #ifdef CONFIG_KVM_MMU_AUDIT
1859 #include "mmu_audit.c"
1861 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1862 static void mmu_audit_disable(void) { }
1865 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1867 return sp
->role
.invalid
||
1868 unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1871 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1872 struct list_head
*invalid_list
)
1874 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1875 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
1878 /* @gfn should be write-protected at the call site */
1879 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1880 struct list_head
*invalid_list
)
1882 struct kvm_mmu_page
*s
;
1885 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
1889 WARN_ON(s
->role
.level
!= PG_LEVEL_4K
);
1890 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
1896 struct mmu_page_path
{
1897 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
1898 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
1901 #define for_each_sp(pvec, sp, parents, i) \
1902 for (i = mmu_pages_first(&pvec, &parents); \
1903 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1904 i = mmu_pages_next(&pvec, &parents, i))
1906 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1907 struct mmu_page_path
*parents
,
1912 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1913 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1914 unsigned idx
= pvec
->page
[n
].idx
;
1915 int level
= sp
->role
.level
;
1917 parents
->idx
[level
-1] = idx
;
1918 if (level
== PG_LEVEL_4K
)
1921 parents
->parent
[level
-2] = sp
;
1927 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
1928 struct mmu_page_path
*parents
)
1930 struct kvm_mmu_page
*sp
;
1936 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
1938 sp
= pvec
->page
[0].sp
;
1939 level
= sp
->role
.level
;
1940 WARN_ON(level
== PG_LEVEL_4K
);
1942 parents
->parent
[level
-2] = sp
;
1944 /* Also set up a sentinel. Further entries in pvec are all
1945 * children of sp, so this element is never overwritten.
1947 parents
->parent
[level
-1] = NULL
;
1948 return mmu_pages_next(pvec
, parents
, 0);
1951 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1953 struct kvm_mmu_page
*sp
;
1954 unsigned int level
= 0;
1957 unsigned int idx
= parents
->idx
[level
];
1958 sp
= parents
->parent
[level
];
1962 WARN_ON(idx
== INVALID_INDEX
);
1963 clear_unsync_child_bit(sp
, idx
);
1965 } while (!sp
->unsync_children
);
1968 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1969 struct kvm_mmu_page
*parent
)
1972 struct kvm_mmu_page
*sp
;
1973 struct mmu_page_path parents
;
1974 struct kvm_mmu_pages pages
;
1975 LIST_HEAD(invalid_list
);
1978 while (mmu_unsync_walk(parent
, &pages
)) {
1979 bool protected = false;
1981 for_each_sp(pages
, sp
, parents
, i
)
1982 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
1985 kvm_flush_remote_tlbs(vcpu
->kvm
);
1989 for_each_sp(pages
, sp
, parents
, i
) {
1990 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
1991 mmu_pages_clear_parents(&parents
);
1993 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
1994 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
1995 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2000 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2003 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2005 atomic_set(&sp
->write_flooding_count
, 0);
2008 static void clear_sp_write_flooding_count(u64
*spte
)
2010 __clear_sp_write_flooding_count(sptep_to_sp(spte
));
2013 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2018 unsigned int access
)
2020 bool direct_mmu
= vcpu
->arch
.mmu
->direct_map
;
2021 union kvm_mmu_page_role role
;
2022 struct hlist_head
*sp_list
;
2024 struct kvm_mmu_page
*sp
;
2025 bool need_sync
= false;
2028 LIST_HEAD(invalid_list
);
2030 role
= vcpu
->arch
.mmu
->mmu_role
.base
;
2032 role
.direct
= direct
;
2034 role
.gpte_is_8_bytes
= true;
2035 role
.access
= access
;
2036 if (!direct_mmu
&& vcpu
->arch
.mmu
->root_level
<= PT32_ROOT_LEVEL
) {
2037 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2038 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2039 role
.quadrant
= quadrant
;
2042 sp_list
= &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)];
2043 for_each_valid_sp(vcpu
->kvm
, sp
, sp_list
) {
2044 if (sp
->gfn
!= gfn
) {
2049 if (!need_sync
&& sp
->unsync
)
2052 if (sp
->role
.word
!= role
.word
)
2056 goto trace_get_page
;
2059 /* The page is good, but __kvm_sync_page might still end
2060 * up zapping it. If so, break in order to rebuild it.
2062 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2065 WARN_ON(!list_empty(&invalid_list
));
2066 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2069 if (sp
->unsync_children
)
2070 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2072 __clear_sp_write_flooding_count(sp
);
2075 trace_kvm_mmu_get_page(sp
, false);
2079 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2081 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2085 hlist_add_head(&sp
->hash_link
, sp_list
);
2088 * we should do write protection before syncing pages
2089 * otherwise the content of the synced shadow page may
2090 * be inconsistent with guest page table.
2092 account_shadowed(vcpu
->kvm
, sp
);
2093 if (level
== PG_LEVEL_4K
&& rmap_write_protect(vcpu
, gfn
))
2094 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
, 1);
2096 if (level
> PG_LEVEL_4K
&& need_sync
)
2097 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2099 trace_kvm_mmu_get_page(sp
, true);
2101 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2103 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2104 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2108 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator
*iterator
,
2109 struct kvm_vcpu
*vcpu
, hpa_t root
,
2112 iterator
->addr
= addr
;
2113 iterator
->shadow_addr
= root
;
2114 iterator
->level
= vcpu
->arch
.mmu
->shadow_root_level
;
2116 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2117 vcpu
->arch
.mmu
->root_level
< PT64_ROOT_4LEVEL
&&
2118 !vcpu
->arch
.mmu
->direct_map
)
2121 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2123 * prev_root is currently only used for 64-bit hosts. So only
2124 * the active root_hpa is valid here.
2126 BUG_ON(root
!= vcpu
->arch
.mmu
->root_hpa
);
2128 iterator
->shadow_addr
2129 = vcpu
->arch
.mmu
->pae_root
[(addr
>> 30) & 3];
2130 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2132 if (!iterator
->shadow_addr
)
2133 iterator
->level
= 0;
2137 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2138 struct kvm_vcpu
*vcpu
, u64 addr
)
2140 shadow_walk_init_using_root(iterator
, vcpu
, vcpu
->arch
.mmu
->root_hpa
,
2144 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2146 if (iterator
->level
< PG_LEVEL_4K
)
2149 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2150 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2154 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2157 if (is_last_spte(spte
, iterator
->level
)) {
2158 iterator
->level
= 0;
2162 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2166 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2168 __shadow_walk_next(iterator
, *iterator
->sptep
);
2171 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2172 struct kvm_mmu_page
*sp
)
2176 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2178 spte
= make_nonleaf_spte(sp
->spt
, sp_ad_disabled(sp
));
2180 mmu_spte_set(sptep
, spte
);
2182 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2184 if (sp
->unsync_children
|| sp
->unsync
)
2188 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2189 unsigned direct_access
)
2191 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2192 struct kvm_mmu_page
*child
;
2195 * For the direct sp, if the guest pte's dirty bit
2196 * changed form clean to dirty, it will corrupt the
2197 * sp's access: allow writable in the read-only sp,
2198 * so we should update the spte at this point to get
2199 * a new sp with the correct access.
2201 child
= to_shadow_page(*sptep
& PT64_BASE_ADDR_MASK
);
2202 if (child
->role
.access
== direct_access
)
2205 drop_parent_pte(child
, sptep
);
2206 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, child
->gfn
, 1);
2210 /* Returns the number of zapped non-leaf child shadow pages. */
2211 static int mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2212 u64
*spte
, struct list_head
*invalid_list
)
2215 struct kvm_mmu_page
*child
;
2218 if (is_shadow_present_pte(pte
)) {
2219 if (is_last_spte(pte
, sp
->role
.level
)) {
2220 drop_spte(kvm
, spte
);
2221 if (is_large_pte(pte
))
2224 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2225 drop_parent_pte(child
, spte
);
2228 * Recursively zap nested TDP SPs, parentless SPs are
2229 * unlikely to be used again in the near future. This
2230 * avoids retaining a large number of stale nested SPs.
2232 if (tdp_enabled
&& invalid_list
&&
2233 child
->role
.guest_mode
&& !child
->parent_ptes
.val
)
2234 return kvm_mmu_prepare_zap_page(kvm
, child
,
2237 } else if (is_mmio_spte(pte
)) {
2238 mmu_spte_clear_no_track(spte
);
2243 static int kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2244 struct kvm_mmu_page
*sp
,
2245 struct list_head
*invalid_list
)
2250 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2251 zapped
+= mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
, invalid_list
);
2256 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2259 struct rmap_iterator iter
;
2261 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2262 drop_parent_pte(sp
, sptep
);
2265 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2266 struct kvm_mmu_page
*parent
,
2267 struct list_head
*invalid_list
)
2270 struct mmu_page_path parents
;
2271 struct kvm_mmu_pages pages
;
2273 if (parent
->role
.level
== PG_LEVEL_4K
)
2276 while (mmu_unsync_walk(parent
, &pages
)) {
2277 struct kvm_mmu_page
*sp
;
2279 for_each_sp(pages
, sp
, parents
, i
) {
2280 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2281 mmu_pages_clear_parents(&parents
);
2289 static bool __kvm_mmu_prepare_zap_page(struct kvm
*kvm
,
2290 struct kvm_mmu_page
*sp
,
2291 struct list_head
*invalid_list
,
2296 trace_kvm_mmu_prepare_zap_page(sp
);
2297 ++kvm
->stat
.mmu_shadow_zapped
;
2298 *nr_zapped
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2299 *nr_zapped
+= kvm_mmu_page_unlink_children(kvm
, sp
, invalid_list
);
2300 kvm_mmu_unlink_parents(kvm
, sp
);
2302 /* Zapping children means active_mmu_pages has become unstable. */
2303 list_unstable
= *nr_zapped
;
2305 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2306 unaccount_shadowed(kvm
, sp
);
2309 kvm_unlink_unsync_page(kvm
, sp
);
2310 if (!sp
->root_count
) {
2315 * Already invalid pages (previously active roots) are not on
2316 * the active page list. See list_del() in the "else" case of
2319 if (sp
->role
.invalid
)
2320 list_add(&sp
->link
, invalid_list
);
2322 list_move(&sp
->link
, invalid_list
);
2323 kvm_mod_used_mmu_pages(kvm
, -1);
2326 * Remove the active root from the active page list, the root
2327 * will be explicitly freed when the root_count hits zero.
2329 list_del(&sp
->link
);
2332 * Obsolete pages cannot be used on any vCPUs, see the comment
2333 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2334 * treats invalid shadow pages as being obsolete.
2336 if (!is_obsolete_sp(kvm
, sp
))
2337 kvm_reload_remote_mmus(kvm
);
2340 if (sp
->lpage_disallowed
)
2341 unaccount_huge_nx_page(kvm
, sp
);
2343 sp
->role
.invalid
= 1;
2344 return list_unstable
;
2347 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2348 struct list_head
*invalid_list
)
2352 __kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
, &nr_zapped
);
2356 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2357 struct list_head
*invalid_list
)
2359 struct kvm_mmu_page
*sp
, *nsp
;
2361 if (list_empty(invalid_list
))
2365 * We need to make sure everyone sees our modifications to
2366 * the page tables and see changes to vcpu->mode here. The barrier
2367 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2368 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2370 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2371 * guest mode and/or lockless shadow page table walks.
2373 kvm_flush_remote_tlbs(kvm
);
2375 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2376 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2377 kvm_mmu_free_page(sp
);
2381 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm
*kvm
,
2382 unsigned long nr_to_zap
)
2384 unsigned long total_zapped
= 0;
2385 struct kvm_mmu_page
*sp
, *tmp
;
2386 LIST_HEAD(invalid_list
);
2390 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2394 list_for_each_entry_safe(sp
, tmp
, &kvm
->arch
.active_mmu_pages
, link
) {
2396 * Don't zap active root pages, the page itself can't be freed
2397 * and zapping it will just force vCPUs to realloc and reload.
2402 unstable
= __kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
,
2404 total_zapped
+= nr_zapped
;
2405 if (total_zapped
>= nr_to_zap
)
2412 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2414 kvm
->stat
.mmu_recycled
+= total_zapped
;
2415 return total_zapped
;
2418 static inline unsigned long kvm_mmu_available_pages(struct kvm
*kvm
)
2420 if (kvm
->arch
.n_max_mmu_pages
> kvm
->arch
.n_used_mmu_pages
)
2421 return kvm
->arch
.n_max_mmu_pages
-
2422 kvm
->arch
.n_used_mmu_pages
;
2427 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
2429 unsigned long avail
= kvm_mmu_available_pages(vcpu
->kvm
);
2431 if (likely(avail
>= KVM_MIN_FREE_MMU_PAGES
))
2434 kvm_mmu_zap_oldest_mmu_pages(vcpu
->kvm
, KVM_REFILL_PAGES
- avail
);
2436 if (!kvm_mmu_available_pages(vcpu
->kvm
))
2442 * Changing the number of mmu pages allocated to the vm
2443 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2445 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned long goal_nr_mmu_pages
)
2447 spin_lock(&kvm
->mmu_lock
);
2449 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2450 kvm_mmu_zap_oldest_mmu_pages(kvm
, kvm
->arch
.n_used_mmu_pages
-
2453 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2456 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2458 spin_unlock(&kvm
->mmu_lock
);
2461 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2463 struct kvm_mmu_page
*sp
;
2464 LIST_HEAD(invalid_list
);
2467 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2469 spin_lock(&kvm
->mmu_lock
);
2470 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2471 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2474 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2476 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2477 spin_unlock(&kvm
->mmu_lock
);
2481 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2483 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2485 trace_kvm_mmu_unsync_page(sp
);
2486 ++vcpu
->kvm
->stat
.mmu_unsync
;
2489 kvm_mmu_mark_parents_unsync(sp
);
2492 bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2495 struct kvm_mmu_page
*sp
;
2497 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2500 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2507 WARN_ON(sp
->role
.level
!= PG_LEVEL_4K
);
2508 kvm_unsync_page(vcpu
, sp
);
2512 * We need to ensure that the marking of unsync pages is visible
2513 * before the SPTE is updated to allow writes because
2514 * kvm_mmu_sync_roots() checks the unsync flags without holding
2515 * the MMU lock and so can race with this. If the SPTE was updated
2516 * before the page had been marked as unsync-ed, something like the
2517 * following could happen:
2520 * ---------------------------------------------------------------------
2521 * 1.2 Host updates SPTE
2523 * 2.1 Guest writes a GPTE for GVA X.
2524 * (GPTE being in the guest page table shadowed
2525 * by the SP from CPU 1.)
2526 * This reads SPTE during the page table walk.
2527 * Since SPTE.W is read as 1, there is no
2530 * 2.2 Guest issues TLB flush.
2531 * That causes a VM Exit.
2533 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2534 * Since it is false, so it just returns.
2536 * 2.4 Guest accesses GVA X.
2537 * Since the mapping in the SP was not updated,
2538 * so the old mapping for GVA X incorrectly
2542 * (sp->unsync = true)
2544 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2545 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2546 * pairs with this write barrier.
2553 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2554 unsigned int pte_access
, int level
,
2555 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2556 bool can_unsync
, bool host_writable
)
2559 struct kvm_mmu_page
*sp
;
2562 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2565 sp
= sptep_to_sp(sptep
);
2567 ret
= make_spte(vcpu
, pte_access
, level
, gfn
, pfn
, *sptep
, speculative
,
2568 can_unsync
, host_writable
, sp_ad_disabled(sp
), &spte
);
2570 if (spte
& PT_WRITABLE_MASK
)
2571 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2574 ret
|= SET_SPTE_SPURIOUS
;
2575 else if (mmu_spte_update(sptep
, spte
))
2576 ret
|= SET_SPTE_NEED_REMOTE_TLB_FLUSH
;
2580 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2581 unsigned int pte_access
, bool write_fault
, int level
,
2582 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2585 int was_rmapped
= 0;
2588 int ret
= RET_PF_FIXED
;
2591 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2592 *sptep
, write_fault
, gfn
);
2594 if (is_shadow_present_pte(*sptep
)) {
2596 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2597 * the parent of the now unreachable PTE.
2599 if (level
> PG_LEVEL_4K
&& !is_large_pte(*sptep
)) {
2600 struct kvm_mmu_page
*child
;
2603 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2604 drop_parent_pte(child
, sptep
);
2606 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2607 pgprintk("hfn old %llx new %llx\n",
2608 spte_to_pfn(*sptep
), pfn
);
2609 drop_spte(vcpu
->kvm
, sptep
);
2615 set_spte_ret
= set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
,
2616 speculative
, true, host_writable
);
2617 if (set_spte_ret
& SET_SPTE_WRITE_PROTECTED_PT
) {
2619 ret
= RET_PF_EMULATE
;
2620 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2623 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
|| flush
)
2624 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
,
2625 KVM_PAGES_PER_HPAGE(level
));
2627 if (unlikely(is_mmio_spte(*sptep
)))
2628 ret
= RET_PF_EMULATE
;
2631 * The fault is fully spurious if and only if the new SPTE and old SPTE
2632 * are identical, and emulation is not required.
2634 if ((set_spte_ret
& SET_SPTE_SPURIOUS
) && ret
== RET_PF_FIXED
) {
2635 WARN_ON_ONCE(!was_rmapped
);
2636 return RET_PF_SPURIOUS
;
2639 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2640 trace_kvm_mmu_set_spte(level
, gfn
, sptep
);
2641 if (!was_rmapped
&& is_large_pte(*sptep
))
2642 ++vcpu
->kvm
->stat
.lpages
;
2644 if (is_shadow_present_pte(*sptep
)) {
2646 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2647 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2648 rmap_recycle(vcpu
, sptep
, gfn
);
2655 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2658 struct kvm_memory_slot
*slot
;
2660 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2662 return KVM_PFN_ERR_FAULT
;
2664 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2667 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2668 struct kvm_mmu_page
*sp
,
2669 u64
*start
, u64
*end
)
2671 struct page
*pages
[PTE_PREFETCH_NUM
];
2672 struct kvm_memory_slot
*slot
;
2673 unsigned int access
= sp
->role
.access
;
2677 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2678 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2682 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2686 for (i
= 0; i
< ret
; i
++, gfn
++, start
++) {
2687 mmu_set_spte(vcpu
, start
, access
, false, sp
->role
.level
, gfn
,
2688 page_to_pfn(pages
[i
]), true, true);
2695 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2696 struct kvm_mmu_page
*sp
, u64
*sptep
)
2698 u64
*spte
, *start
= NULL
;
2701 WARN_ON(!sp
->role
.direct
);
2703 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2706 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2707 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2710 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2718 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2720 struct kvm_mmu_page
*sp
;
2722 sp
= sptep_to_sp(sptep
);
2725 * Without accessed bits, there's no way to distinguish between
2726 * actually accessed translations and prefetched, so disable pte
2727 * prefetch if accessed bits aren't available.
2729 if (sp_ad_disabled(sp
))
2732 if (sp
->role
.level
> PG_LEVEL_4K
)
2735 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2738 static int host_pfn_mapping_level(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2739 kvm_pfn_t pfn
, struct kvm_memory_slot
*slot
)
2745 if (!PageCompound(pfn_to_page(pfn
)) && !kvm_is_zone_device_pfn(pfn
))
2749 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2750 * is not solely for performance, it's also necessary to avoid the
2751 * "writable" check in __gfn_to_hva_many(), which will always fail on
2752 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2753 * page fault steps have already verified the guest isn't writing a
2754 * read-only memslot.
2756 hva
= __gfn_to_hva_memslot(slot
, gfn
);
2758 pte
= lookup_address_in_mm(vcpu
->kvm
->mm
, hva
, &level
);
2765 static int kvm_mmu_hugepage_adjust(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2766 int max_level
, kvm_pfn_t
*pfnp
,
2767 bool huge_page_disallowed
, int *req_level
)
2769 struct kvm_memory_slot
*slot
;
2770 struct kvm_lpage_info
*linfo
;
2771 kvm_pfn_t pfn
= *pfnp
;
2775 *req_level
= PG_LEVEL_4K
;
2777 if (unlikely(max_level
== PG_LEVEL_4K
))
2780 if (is_error_noslot_pfn(pfn
) || kvm_is_reserved_pfn(pfn
))
2783 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, true);
2787 max_level
= min(max_level
, max_huge_page_level
);
2788 for ( ; max_level
> PG_LEVEL_4K
; max_level
--) {
2789 linfo
= lpage_info_slot(gfn
, slot
, max_level
);
2790 if (!linfo
->disallow_lpage
)
2794 if (max_level
== PG_LEVEL_4K
)
2797 level
= host_pfn_mapping_level(vcpu
, gfn
, pfn
, slot
);
2798 if (level
== PG_LEVEL_4K
)
2801 *req_level
= level
= min(level
, max_level
);
2804 * Enforce the iTLB multihit workaround after capturing the requested
2805 * level, which will be used to do precise, accurate accounting.
2807 if (huge_page_disallowed
)
2811 * mmu_notifier_retry() was successful and mmu_lock is held, so
2812 * the pmd can't be split from under us.
2814 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2815 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2816 *pfnp
= pfn
& ~mask
;
2821 static void disallowed_hugepage_adjust(u64 spte
, gfn_t gfn
, int cur_level
,
2822 kvm_pfn_t
*pfnp
, int *levelp
)
2824 int level
= *levelp
;
2826 if (cur_level
== level
&& level
> PG_LEVEL_4K
&&
2827 is_shadow_present_pte(spte
) &&
2828 !is_large_pte(spte
)) {
2830 * A small SPTE exists for this pfn, but FNAME(fetch)
2831 * and __direct_map would like to create a large PTE
2832 * instead: just force them to go down another level,
2833 * patching back for them into pfn the next 9 bits of
2836 u64 page_mask
= KVM_PAGES_PER_HPAGE(level
) -
2837 KVM_PAGES_PER_HPAGE(level
- 1);
2838 *pfnp
|= gfn
& page_mask
;
2843 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
2844 int map_writable
, int max_level
, kvm_pfn_t pfn
,
2845 bool prefault
, bool is_tdp
)
2847 bool nx_huge_page_workaround_enabled
= is_nx_huge_page_enabled();
2848 bool write
= error_code
& PFERR_WRITE_MASK
;
2849 bool exec
= error_code
& PFERR_FETCH_MASK
;
2850 bool huge_page_disallowed
= exec
&& nx_huge_page_workaround_enabled
;
2851 struct kvm_shadow_walk_iterator it
;
2852 struct kvm_mmu_page
*sp
;
2853 int level
, req_level
, ret
;
2854 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
2855 gfn_t base_gfn
= gfn
;
2857 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
2858 return RET_PF_RETRY
;
2860 level
= kvm_mmu_hugepage_adjust(vcpu
, gfn
, max_level
, &pfn
,
2861 huge_page_disallowed
, &req_level
);
2863 trace_kvm_mmu_spte_requested(gpa
, level
, pfn
);
2864 for_each_shadow_entry(vcpu
, gpa
, it
) {
2866 * We cannot overwrite existing page tables with an NX
2867 * large page, as the leaf could be executable.
2869 if (nx_huge_page_workaround_enabled
)
2870 disallowed_hugepage_adjust(*it
.sptep
, gfn
, it
.level
,
2873 base_gfn
= gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
2874 if (it
.level
== level
)
2877 drop_large_spte(vcpu
, it
.sptep
);
2878 if (!is_shadow_present_pte(*it
.sptep
)) {
2879 sp
= kvm_mmu_get_page(vcpu
, base_gfn
, it
.addr
,
2880 it
.level
- 1, true, ACC_ALL
);
2882 link_shadow_page(vcpu
, it
.sptep
, sp
);
2883 if (is_tdp
&& huge_page_disallowed
&&
2884 req_level
>= it
.level
)
2885 account_huge_nx_page(vcpu
->kvm
, sp
);
2889 ret
= mmu_set_spte(vcpu
, it
.sptep
, ACC_ALL
,
2890 write
, level
, base_gfn
, pfn
, prefault
,
2892 if (ret
== RET_PF_SPURIOUS
)
2895 direct_pte_prefetch(vcpu
, it
.sptep
);
2896 ++vcpu
->stat
.pf_fixed
;
2900 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2902 send_sig_mceerr(BUS_MCEERR_AR
, (void __user
*)address
, PAGE_SHIFT
, tsk
);
2905 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2908 * Do not cache the mmio info caused by writing the readonly gfn
2909 * into the spte otherwise read access on readonly gfn also can
2910 * caused mmio page fault and treat it as mmio access.
2912 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2913 return RET_PF_EMULATE
;
2915 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2916 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
2917 return RET_PF_RETRY
;
2923 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2924 kvm_pfn_t pfn
, unsigned int access
,
2927 /* The pfn is invalid, report the error! */
2928 if (unlikely(is_error_pfn(pfn
))) {
2929 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2933 if (unlikely(is_noslot_pfn(pfn
)))
2934 vcpu_cache_mmio_info(vcpu
, gva
, gfn
,
2935 access
& shadow_mmio_access_mask
);
2940 static bool page_fault_can_be_fast(u32 error_code
)
2943 * Do not fix the mmio spte with invalid generation number which
2944 * need to be updated by slow page fault path.
2946 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2949 /* See if the page fault is due to an NX violation */
2950 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
2951 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
2955 * #PF can be fast if:
2956 * 1. The shadow page table entry is not present, which could mean that
2957 * the fault is potentially caused by access tracking (if enabled).
2958 * 2. The shadow page table entry is present and the fault
2959 * is caused by write-protect, that means we just need change the W
2960 * bit of the spte which can be done out of mmu-lock.
2962 * However, if access tracking is disabled we know that a non-present
2963 * page must be a genuine page fault where we have to create a new SPTE.
2964 * So, if access tracking is disabled, we return true only for write
2965 * accesses to a present page.
2968 return shadow_acc_track_mask
!= 0 ||
2969 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
2970 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
2974 * Returns true if the SPTE was fixed successfully. Otherwise,
2975 * someone else modified the SPTE from its original value.
2978 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2979 u64
*sptep
, u64 old_spte
, u64 new_spte
)
2983 WARN_ON(!sp
->role
.direct
);
2986 * Theoretically we could also set dirty bit (and flush TLB) here in
2987 * order to eliminate unnecessary PML logging. See comments in
2988 * set_spte. But fast_page_fault is very unlikely to happen with PML
2989 * enabled, so we do not do this. This might result in the same GPA
2990 * to be logged in PML buffer again when the write really happens, and
2991 * eventually to be called by mark_page_dirty twice. But it's also no
2992 * harm. This also avoids the TLB flush needed after setting dirty bit
2993 * so non-PML cases won't be impacted.
2995 * Compare with set_spte where instead shadow_dirty_mask is set.
2997 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3000 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3002 * The gfn of direct spte is stable since it is
3003 * calculated by sp->gfn.
3005 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3006 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3012 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3014 if (fault_err_code
& PFERR_FETCH_MASK
)
3015 return is_executable_pte(spte
);
3017 if (fault_err_code
& PFERR_WRITE_MASK
)
3018 return is_writable_pte(spte
);
3020 /* Fault was on Read access */
3021 return spte
& PT_PRESENT_MASK
;
3025 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3027 static int fast_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3030 struct kvm_shadow_walk_iterator iterator
;
3031 struct kvm_mmu_page
*sp
;
3032 int ret
= RET_PF_INVALID
;
3034 uint retry_count
= 0;
3036 if (!page_fault_can_be_fast(error_code
))
3039 walk_shadow_page_lockless_begin(vcpu
);
3044 for_each_shadow_entry_lockless(vcpu
, cr2_or_gpa
, iterator
, spte
)
3045 if (!is_shadow_present_pte(spte
))
3048 sp
= sptep_to_sp(iterator
.sptep
);
3049 if (!is_last_spte(spte
, sp
->role
.level
))
3053 * Check whether the memory access that caused the fault would
3054 * still cause it if it were to be performed right now. If not,
3055 * then this is a spurious fault caused by TLB lazily flushed,
3056 * or some other CPU has already fixed the PTE after the
3057 * current CPU took the fault.
3059 * Need not check the access of upper level table entries since
3060 * they are always ACC_ALL.
3062 if (is_access_allowed(error_code
, spte
)) {
3063 ret
= RET_PF_SPURIOUS
;
3069 if (is_access_track_spte(spte
))
3070 new_spte
= restore_acc_track_spte(new_spte
);
3073 * Currently, to simplify the code, write-protection can
3074 * be removed in the fast path only if the SPTE was
3075 * write-protected for dirty-logging or access tracking.
3077 if ((error_code
& PFERR_WRITE_MASK
) &&
3078 spte_can_locklessly_be_made_writable(spte
)) {
3079 new_spte
|= PT_WRITABLE_MASK
;
3082 * Do not fix write-permission on the large spte. Since
3083 * we only dirty the first page into the dirty-bitmap in
3084 * fast_pf_fix_direct_spte(), other pages are missed
3085 * if its slot has dirty logging enabled.
3087 * Instead, we let the slow page fault path create a
3088 * normal spte to fix the access.
3090 * See the comments in kvm_arch_commit_memory_region().
3092 if (sp
->role
.level
> PG_LEVEL_4K
)
3096 /* Verify that the fault can be handled in the fast path */
3097 if (new_spte
== spte
||
3098 !is_access_allowed(error_code
, new_spte
))
3102 * Currently, fast page fault only works for direct mapping
3103 * since the gfn is not stable for indirect shadow page. See
3104 * Documentation/virt/kvm/locking.rst to get more detail.
3106 if (fast_pf_fix_direct_spte(vcpu
, sp
, iterator
.sptep
, spte
,
3112 if (++retry_count
> 4) {
3113 printk_once(KERN_WARNING
3114 "kvm: Fast #PF retrying more than 4 times.\n");
3120 trace_fast_page_fault(vcpu
, cr2_or_gpa
, error_code
, iterator
.sptep
,
3122 walk_shadow_page_lockless_end(vcpu
);
3127 static void mmu_free_root_page(struct kvm
*kvm
, hpa_t
*root_hpa
,
3128 struct list_head
*invalid_list
)
3130 struct kvm_mmu_page
*sp
;
3132 if (!VALID_PAGE(*root_hpa
))
3135 sp
= to_shadow_page(*root_hpa
& PT64_BASE_ADDR_MASK
);
3137 if (kvm_mmu_put_root(kvm
, sp
)) {
3138 if (sp
->tdp_mmu_page
)
3139 kvm_tdp_mmu_free_root(kvm
, sp
);
3140 else if (sp
->role
.invalid
)
3141 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
3144 *root_hpa
= INVALID_PAGE
;
3147 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3148 void kvm_mmu_free_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3149 ulong roots_to_free
)
3151 struct kvm
*kvm
= vcpu
->kvm
;
3153 LIST_HEAD(invalid_list
);
3154 bool free_active_root
= roots_to_free
& KVM_MMU_ROOT_CURRENT
;
3156 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS
>= BITS_PER_LONG
);
3158 /* Before acquiring the MMU lock, see if we need to do any real work. */
3159 if (!(free_active_root
&& VALID_PAGE(mmu
->root_hpa
))) {
3160 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3161 if ((roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
)) &&
3162 VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
3165 if (i
== KVM_MMU_NUM_PREV_ROOTS
)
3169 spin_lock(&kvm
->mmu_lock
);
3171 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3172 if (roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
))
3173 mmu_free_root_page(kvm
, &mmu
->prev_roots
[i
].hpa
,
3176 if (free_active_root
) {
3177 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3178 (mmu
->root_level
>= PT64_ROOT_4LEVEL
|| mmu
->direct_map
)) {
3179 mmu_free_root_page(kvm
, &mmu
->root_hpa
, &invalid_list
);
3181 for (i
= 0; i
< 4; ++i
)
3182 if (mmu
->pae_root
[i
] != 0)
3183 mmu_free_root_page(kvm
,
3186 mmu
->root_hpa
= INVALID_PAGE
;
3191 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3192 spin_unlock(&kvm
->mmu_lock
);
3194 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots
);
3196 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3200 if (!kvm_vcpu_is_visible_gfn(vcpu
, root_gfn
)) {
3201 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3208 static hpa_t
mmu_alloc_root(struct kvm_vcpu
*vcpu
, gfn_t gfn
, gva_t gva
,
3209 u8 level
, bool direct
)
3211 struct kvm_mmu_page
*sp
;
3213 spin_lock(&vcpu
->kvm
->mmu_lock
);
3215 if (make_mmu_pages_available(vcpu
)) {
3216 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3217 return INVALID_PAGE
;
3219 sp
= kvm_mmu_get_page(vcpu
, gfn
, gva
, level
, direct
, ACC_ALL
);
3222 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3223 return __pa(sp
->spt
);
3226 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3228 u8 shadow_root_level
= vcpu
->arch
.mmu
->shadow_root_level
;
3232 if (vcpu
->kvm
->arch
.tdp_mmu_enabled
) {
3233 root
= kvm_tdp_mmu_get_vcpu_root_hpa(vcpu
);
3235 if (!VALID_PAGE(root
))
3237 vcpu
->arch
.mmu
->root_hpa
= root
;
3238 } else if (shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3239 root
= mmu_alloc_root(vcpu
, 0, 0, shadow_root_level
,
3242 if (!VALID_PAGE(root
))
3244 vcpu
->arch
.mmu
->root_hpa
= root
;
3245 } else if (shadow_root_level
== PT32E_ROOT_LEVEL
) {
3246 for (i
= 0; i
< 4; ++i
) {
3247 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
->pae_root
[i
]));
3249 root
= mmu_alloc_root(vcpu
, i
<< (30 - PAGE_SHIFT
),
3250 i
<< 30, PT32_ROOT_LEVEL
, true);
3251 if (!VALID_PAGE(root
))
3253 vcpu
->arch
.mmu
->pae_root
[i
] = root
| PT_PRESENT_MASK
;
3255 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->pae_root
);
3259 /* root_pgd is ignored for direct MMUs. */
3260 vcpu
->arch
.mmu
->root_pgd
= 0;
3265 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3268 gfn_t root_gfn
, root_pgd
;
3272 root_pgd
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3273 root_gfn
= root_pgd
>> PAGE_SHIFT
;
3275 if (mmu_check_root(vcpu
, root_gfn
))
3279 * Do we shadow a long mode page table? If so we need to
3280 * write-protect the guests page table root.
3282 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3283 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
));
3285 root
= mmu_alloc_root(vcpu
, root_gfn
, 0,
3286 vcpu
->arch
.mmu
->shadow_root_level
, false);
3287 if (!VALID_PAGE(root
))
3289 vcpu
->arch
.mmu
->root_hpa
= root
;
3294 * We shadow a 32 bit page table. This may be a legacy 2-level
3295 * or a PAE 3-level page table. In either case we need to be aware that
3296 * the shadow page table may be a PAE or a long mode page table.
3298 pm_mask
= PT_PRESENT_MASK
;
3299 if (vcpu
->arch
.mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
)
3300 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3302 for (i
= 0; i
< 4; ++i
) {
3303 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
->pae_root
[i
]));
3304 if (vcpu
->arch
.mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3305 pdptr
= vcpu
->arch
.mmu
->get_pdptr(vcpu
, i
);
3306 if (!(pdptr
& PT_PRESENT_MASK
)) {
3307 vcpu
->arch
.mmu
->pae_root
[i
] = 0;
3310 root_gfn
= pdptr
>> PAGE_SHIFT
;
3311 if (mmu_check_root(vcpu
, root_gfn
))
3315 root
= mmu_alloc_root(vcpu
, root_gfn
, i
<< 30,
3316 PT32_ROOT_LEVEL
, false);
3317 if (!VALID_PAGE(root
))
3319 vcpu
->arch
.mmu
->pae_root
[i
] = root
| pm_mask
;
3321 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->pae_root
);
3324 * If we shadow a 32 bit page table with a long mode page
3325 * table we enter this path.
3327 if (vcpu
->arch
.mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
) {
3328 if (vcpu
->arch
.mmu
->lm_root
== NULL
) {
3330 * The additional page necessary for this is only
3331 * allocated on demand.
3336 lm_root
= (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3337 if (lm_root
== NULL
)
3340 lm_root
[0] = __pa(vcpu
->arch
.mmu
->pae_root
) | pm_mask
;
3342 vcpu
->arch
.mmu
->lm_root
= lm_root
;
3345 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->lm_root
);
3349 vcpu
->arch
.mmu
->root_pgd
= root_pgd
;
3354 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3356 if (vcpu
->arch
.mmu
->direct_map
)
3357 return mmu_alloc_direct_roots(vcpu
);
3359 return mmu_alloc_shadow_roots(vcpu
);
3362 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3365 struct kvm_mmu_page
*sp
;
3367 if (vcpu
->arch
.mmu
->direct_map
)
3370 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
3373 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3375 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3376 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3377 sp
= to_shadow_page(root
);
3380 * Even if another CPU was marking the SP as unsync-ed
3381 * simultaneously, any guest page table changes are not
3382 * guaranteed to be visible anyway until this VCPU issues a TLB
3383 * flush strictly after those changes are made. We only need to
3384 * ensure that the other CPU sets these flags before any actual
3385 * changes to the page tables are made. The comments in
3386 * mmu_need_write_protect() describe what could go wrong if this
3387 * requirement isn't satisfied.
3389 if (!smp_load_acquire(&sp
->unsync
) &&
3390 !smp_load_acquire(&sp
->unsync_children
))
3393 spin_lock(&vcpu
->kvm
->mmu_lock
);
3394 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3396 mmu_sync_children(vcpu
, sp
);
3398 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3399 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3403 spin_lock(&vcpu
->kvm
->mmu_lock
);
3404 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3406 for (i
= 0; i
< 4; ++i
) {
3407 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3409 if (root
&& VALID_PAGE(root
)) {
3410 root
&= PT64_BASE_ADDR_MASK
;
3411 sp
= to_shadow_page(root
);
3412 mmu_sync_children(vcpu
, sp
);
3416 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3417 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3419 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3421 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3422 u32 access
, struct x86_exception
*exception
)
3425 exception
->error_code
= 0;
3429 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3431 struct x86_exception
*exception
)
3434 exception
->error_code
= 0;
3435 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3439 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3441 int bit7
= (pte
>> 7) & 1;
3443 return pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1];
3446 static bool __is_bad_mt_xwr(struct rsvd_bits_validate
*rsvd_check
, u64 pte
)
3448 return rsvd_check
->bad_mt_xwr
& BIT_ULL(pte
& 0x3f);
3451 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3454 * A nested guest cannot use the MMIO cache if it is using nested
3455 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3457 if (mmu_is_nested(vcpu
))
3461 return vcpu_match_mmio_gpa(vcpu
, addr
);
3463 return vcpu_match_mmio_gva(vcpu
, addr
);
3466 /* return true if reserved bit is detected on spte. */
3468 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3470 struct kvm_shadow_walk_iterator iterator
;
3471 u64 sptes
[PT64_ROOT_MAX_LEVEL
], spte
= 0ull;
3472 struct rsvd_bits_validate
*rsvd_check
;
3474 bool reserved
= false;
3476 rsvd_check
= &vcpu
->arch
.mmu
->shadow_zero_check
;
3478 walk_shadow_page_lockless_begin(vcpu
);
3480 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3481 leaf
= root
= iterator
.level
;
3482 shadow_walk_okay(&iterator
);
3483 __shadow_walk_next(&iterator
, spte
)) {
3484 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3486 sptes
[leaf
- 1] = spte
;
3489 if (!is_shadow_present_pte(spte
))
3493 * Use a bitwise-OR instead of a logical-OR to aggregate the
3494 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3495 * adding a Jcc in the loop.
3497 reserved
|= __is_bad_mt_xwr(rsvd_check
, spte
) |
3498 __is_rsvd_bits_set(rsvd_check
, spte
, iterator
.level
);
3501 walk_shadow_page_lockless_end(vcpu
);
3504 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3506 while (root
> leaf
) {
3507 pr_err("------ spte 0x%llx level %d.\n",
3508 sptes
[root
- 1], root
);
3517 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3522 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3523 return RET_PF_EMULATE
;
3525 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3526 if (WARN_ON(reserved
))
3529 if (is_mmio_spte(spte
)) {
3530 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3531 unsigned int access
= get_mmio_spte_access(spte
);
3533 if (!check_mmio_spte(vcpu
, spte
))
3534 return RET_PF_INVALID
;
3539 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3540 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3541 return RET_PF_EMULATE
;
3545 * If the page table is zapped by other cpus, let CPU fault again on
3548 return RET_PF_RETRY
;
3551 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3552 u32 error_code
, gfn_t gfn
)
3554 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3557 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3558 !(error_code
& PFERR_WRITE_MASK
))
3562 * guest is writing the page which is write tracked which can
3563 * not be fixed by page fault handler.
3565 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3571 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3573 struct kvm_shadow_walk_iterator iterator
;
3576 walk_shadow_page_lockless_begin(vcpu
);
3577 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3578 clear_sp_write_flooding_count(iterator
.sptep
);
3579 if (!is_shadow_present_pte(spte
))
3582 walk_shadow_page_lockless_end(vcpu
);
3585 static bool kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3588 struct kvm_arch_async_pf arch
;
3590 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3592 arch
.direct_map
= vcpu
->arch
.mmu
->direct_map
;
3593 arch
.cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3595 return kvm_setup_async_pf(vcpu
, cr2_or_gpa
,
3596 kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3599 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3600 gpa_t cr2_or_gpa
, kvm_pfn_t
*pfn
, bool write
,
3603 struct kvm_memory_slot
*slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3606 /* Don't expose private memslots to L2. */
3607 if (is_guest_mode(vcpu
) && !kvm_is_visible_memslot(slot
)) {
3608 *pfn
= KVM_PFN_NOSLOT
;
3614 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3616 return false; /* *pfn has correct page already */
3618 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3619 trace_kvm_try_async_get_page(cr2_or_gpa
, gfn
);
3620 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3621 trace_kvm_async_pf_doublefault(cr2_or_gpa
, gfn
);
3622 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3624 } else if (kvm_arch_setup_async_pf(vcpu
, cr2_or_gpa
, gfn
))
3628 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3632 static int direct_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3633 bool prefault
, int max_level
, bool is_tdp
)
3635 bool write
= error_code
& PFERR_WRITE_MASK
;
3638 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3639 unsigned long mmu_seq
;
3643 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3644 return RET_PF_EMULATE
;
3646 r
= fast_page_fault(vcpu
, gpa
, error_code
);
3647 if (r
!= RET_PF_INVALID
)
3650 r
= mmu_topup_memory_caches(vcpu
, false);
3654 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3657 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3658 return RET_PF_RETRY
;
3660 if (handle_abnormal_pfn(vcpu
, is_tdp
? 0 : gpa
, gfn
, pfn
, ACC_ALL
, &r
))
3664 spin_lock(&vcpu
->kvm
->mmu_lock
);
3665 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3667 r
= make_mmu_pages_available(vcpu
);
3670 r
= __direct_map(vcpu
, gpa
, error_code
, map_writable
, max_level
, pfn
,
3674 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3675 kvm_release_pfn_clean(pfn
);
3679 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3680 u32 error_code
, bool prefault
)
3682 pgprintk("%s: gva %lx error %x\n", __func__
, gpa
, error_code
);
3684 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3685 return direct_page_fault(vcpu
, gpa
& PAGE_MASK
, error_code
, prefault
,
3686 PG_LEVEL_2M
, false);
3689 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3690 u64 fault_address
, char *insn
, int insn_len
)
3693 u32 flags
= vcpu
->arch
.apf
.host_apf_flags
;
3695 #ifndef CONFIG_X86_64
3696 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3697 if (WARN_ON_ONCE(fault_address
>> 32))
3701 vcpu
->arch
.l1tf_flush_l1d
= true;
3703 trace_kvm_page_fault(fault_address
, error_code
);
3705 if (kvm_event_needs_reinjection(vcpu
))
3706 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3707 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3709 } else if (flags
& KVM_PV_REASON_PAGE_NOT_PRESENT
) {
3710 vcpu
->arch
.apf
.host_apf_flags
= 0;
3711 local_irq_disable();
3712 kvm_async_pf_task_wait_schedule(fault_address
);
3715 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags
);
3720 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3722 int kvm_tdp_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3727 for (max_level
= KVM_MAX_HUGEPAGE_LEVEL
;
3728 max_level
> PG_LEVEL_4K
;
3730 int page_num
= KVM_PAGES_PER_HPAGE(max_level
);
3731 gfn_t base
= (gpa
>> PAGE_SHIFT
) & ~(page_num
- 1);
3733 if (kvm_mtrr_check_gfn_range_consistency(vcpu
, base
, page_num
))
3737 return direct_page_fault(vcpu
, gpa
, error_code
, prefault
,
3741 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3742 struct kvm_mmu
*context
)
3744 context
->page_fault
= nonpaging_page_fault
;
3745 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3746 context
->sync_page
= nonpaging_sync_page
;
3747 context
->invlpg
= NULL
;
3748 context
->update_pte
= nonpaging_update_pte
;
3749 context
->root_level
= 0;
3750 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3751 context
->direct_map
= true;
3752 context
->nx
= false;
3755 static inline bool is_root_usable(struct kvm_mmu_root_info
*root
, gpa_t pgd
,
3756 union kvm_mmu_page_role role
)
3758 return (role
.direct
|| pgd
== root
->pgd
) &&
3759 VALID_PAGE(root
->hpa
) && to_shadow_page(root
->hpa
) &&
3760 role
.word
== to_shadow_page(root
->hpa
)->role
.word
;
3764 * Find out if a previously cached root matching the new pgd/role is available.
3765 * The current root is also inserted into the cache.
3766 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3768 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3769 * false is returned. This root should now be freed by the caller.
3771 static bool cached_root_available(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3772 union kvm_mmu_page_role new_role
)
3775 struct kvm_mmu_root_info root
;
3776 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3778 root
.pgd
= mmu
->root_pgd
;
3779 root
.hpa
= mmu
->root_hpa
;
3781 if (is_root_usable(&root
, new_pgd
, new_role
))
3784 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
3785 swap(root
, mmu
->prev_roots
[i
]);
3787 if (is_root_usable(&root
, new_pgd
, new_role
))
3791 mmu
->root_hpa
= root
.hpa
;
3792 mmu
->root_pgd
= root
.pgd
;
3794 return i
< KVM_MMU_NUM_PREV_ROOTS
;
3797 static bool fast_pgd_switch(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3798 union kvm_mmu_page_role new_role
)
3800 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3803 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3804 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3805 * later if necessary.
3807 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3808 mmu
->root_level
>= PT64_ROOT_4LEVEL
)
3809 return cached_root_available(vcpu
, new_pgd
, new_role
);
3814 static void __kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3815 union kvm_mmu_page_role new_role
,
3816 bool skip_tlb_flush
, bool skip_mmu_sync
)
3818 if (!fast_pgd_switch(vcpu
, new_pgd
, new_role
)) {
3819 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
, KVM_MMU_ROOT_CURRENT
);
3824 * It's possible that the cached previous root page is obsolete because
3825 * of a change in the MMU generation number. However, changing the
3826 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3827 * free the root set here and allocate a new one.
3829 kvm_make_request(KVM_REQ_LOAD_MMU_PGD
, vcpu
);
3831 if (!skip_mmu_sync
|| force_flush_and_sync_on_reuse
)
3832 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
3833 if (!skip_tlb_flush
|| force_flush_and_sync_on_reuse
)
3834 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
3837 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3838 * switching to a new CR3, that GVA->GPA mapping may no longer be
3839 * valid. So clear any cached MMIO info even when we don't need to sync
3840 * the shadow page tables.
3842 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3844 __clear_sp_write_flooding_count(to_shadow_page(vcpu
->arch
.mmu
->root_hpa
));
3847 void kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
, bool skip_tlb_flush
,
3850 __kvm_mmu_new_pgd(vcpu
, new_pgd
, kvm_mmu_calc_root_page_role(vcpu
),
3851 skip_tlb_flush
, skip_mmu_sync
);
3853 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd
);
3855 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3857 return kvm_read_cr3(vcpu
);
3860 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3861 unsigned int access
, int *nr_present
)
3863 if (unlikely(is_mmio_spte(*sptep
))) {
3864 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3865 mmu_spte_clear_no_track(sptep
);
3870 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3877 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3878 unsigned level
, unsigned gpte
)
3881 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3882 * If it is clear, there are no large pages at this level, so clear
3883 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3885 gpte
&= level
- mmu
->last_nonleaf_level
;
3888 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3889 * iff level <= PG_LEVEL_4K, which for our purpose means
3890 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3892 gpte
|= level
- PG_LEVEL_4K
- 1;
3894 return gpte
& PT_PAGE_SIZE_MASK
;
3897 #define PTTYPE_EPT 18 /* arbitrary */
3898 #define PTTYPE PTTYPE_EPT
3899 #include "paging_tmpl.h"
3903 #include "paging_tmpl.h"
3907 #include "paging_tmpl.h"
3911 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3912 struct rsvd_bits_validate
*rsvd_check
,
3913 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
3916 u64 exb_bit_rsvd
= 0;
3917 u64 gbpages_bit_rsvd
= 0;
3918 u64 nonleaf_bit8_rsvd
= 0;
3920 rsvd_check
->bad_mt_xwr
= 0;
3923 exb_bit_rsvd
= rsvd_bits(63, 63);
3925 gbpages_bit_rsvd
= rsvd_bits(7, 7);
3928 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3929 * leaf entries) on AMD CPUs only.
3932 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
3935 case PT32_ROOT_LEVEL
:
3936 /* no rsvd bits for 2 level 4K page table entries */
3937 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
3938 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
3939 rsvd_check
->rsvd_bits_mask
[1][0] =
3940 rsvd_check
->rsvd_bits_mask
[0][0];
3943 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
3947 if (is_cpuid_PSE36())
3948 /* 36bits PSE 4MB page */
3949 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3951 /* 32 bits PSE 4MB page */
3952 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3954 case PT32E_ROOT_LEVEL
:
3955 rsvd_check
->rsvd_bits_mask
[0][2] =
3956 rsvd_bits(maxphyaddr
, 63) |
3957 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3958 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3959 rsvd_bits(maxphyaddr
, 62); /* PDE */
3960 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3961 rsvd_bits(maxphyaddr
, 62); /* PTE */
3962 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3963 rsvd_bits(maxphyaddr
, 62) |
3964 rsvd_bits(13, 20); /* large page */
3965 rsvd_check
->rsvd_bits_mask
[1][0] =
3966 rsvd_check
->rsvd_bits_mask
[0][0];
3968 case PT64_ROOT_5LEVEL
:
3969 rsvd_check
->rsvd_bits_mask
[0][4] = exb_bit_rsvd
|
3970 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3971 rsvd_bits(maxphyaddr
, 51);
3972 rsvd_check
->rsvd_bits_mask
[1][4] =
3973 rsvd_check
->rsvd_bits_mask
[0][4];
3975 case PT64_ROOT_4LEVEL
:
3976 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3977 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3978 rsvd_bits(maxphyaddr
, 51);
3979 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3981 rsvd_bits(maxphyaddr
, 51);
3982 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3983 rsvd_bits(maxphyaddr
, 51);
3984 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3985 rsvd_bits(maxphyaddr
, 51);
3986 rsvd_check
->rsvd_bits_mask
[1][3] =
3987 rsvd_check
->rsvd_bits_mask
[0][3];
3988 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3989 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
3991 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3992 rsvd_bits(maxphyaddr
, 51) |
3993 rsvd_bits(13, 20); /* large page */
3994 rsvd_check
->rsvd_bits_mask
[1][0] =
3995 rsvd_check
->rsvd_bits_mask
[0][0];
4000 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4001 struct kvm_mmu
*context
)
4003 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4004 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4006 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4008 guest_cpuid_is_amd_or_hygon(vcpu
));
4012 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4013 int maxphyaddr
, bool execonly
)
4017 rsvd_check
->rsvd_bits_mask
[0][4] =
4018 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4019 rsvd_check
->rsvd_bits_mask
[0][3] =
4020 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4021 rsvd_check
->rsvd_bits_mask
[0][2] =
4022 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4023 rsvd_check
->rsvd_bits_mask
[0][1] =
4024 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4025 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4028 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4029 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4030 rsvd_check
->rsvd_bits_mask
[1][2] =
4031 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4032 rsvd_check
->rsvd_bits_mask
[1][1] =
4033 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4034 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4036 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4037 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4038 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4039 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4040 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4042 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4043 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4045 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4048 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4049 struct kvm_mmu
*context
, bool execonly
)
4051 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4052 cpuid_maxphyaddr(vcpu
), execonly
);
4056 * the page table on host is the shadow page table for the page
4057 * table in guest or amd nested guest, its mmu features completely
4058 * follow the features in guest.
4061 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4063 bool uses_nx
= context
->nx
||
4064 context
->mmu_role
.base
.smep_andnot_wp
;
4065 struct rsvd_bits_validate
*shadow_zero_check
;
4069 * Passing "true" to the last argument is okay; it adds a check
4070 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4072 shadow_zero_check
= &context
->shadow_zero_check
;
4073 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4075 context
->shadow_root_level
, uses_nx
,
4076 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4077 is_pse(vcpu
), true);
4079 if (!shadow_me_mask
)
4082 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4083 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4084 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4088 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4090 static inline bool boot_cpu_is_amd(void)
4092 WARN_ON_ONCE(!tdp_enabled
);
4093 return shadow_x_mask
== 0;
4097 * the direct page table on host, use as much mmu features as
4098 * possible, however, kvm currently does not do execution-protection.
4101 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4102 struct kvm_mmu
*context
)
4104 struct rsvd_bits_validate
*shadow_zero_check
;
4107 shadow_zero_check
= &context
->shadow_zero_check
;
4109 if (boot_cpu_is_amd())
4110 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4112 context
->shadow_root_level
, false,
4113 boot_cpu_has(X86_FEATURE_GBPAGES
),
4116 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4120 if (!shadow_me_mask
)
4123 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4124 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4125 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4130 * as the comments in reset_shadow_zero_bits_mask() except it
4131 * is the shadow page table for intel nested guest.
4134 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4135 struct kvm_mmu
*context
, bool execonly
)
4137 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4138 shadow_phys_bits
, execonly
);
4141 #define BYTE_MASK(access) \
4142 ((1 & (access) ? 2 : 0) | \
4143 (2 & (access) ? 4 : 0) | \
4144 (3 & (access) ? 8 : 0) | \
4145 (4 & (access) ? 16 : 0) | \
4146 (5 & (access) ? 32 : 0) | \
4147 (6 & (access) ? 64 : 0) | \
4148 (7 & (access) ? 128 : 0))
4151 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4152 struct kvm_mmu
*mmu
, bool ept
)
4156 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4157 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4158 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4160 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4161 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4162 bool cr0_wp
= is_write_protection(vcpu
);
4164 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4165 unsigned pfec
= byte
<< 1;
4168 * Each "*f" variable has a 1 bit for each UWX value
4169 * that causes a fault with the given PFEC.
4172 /* Faults from writes to non-writable pages */
4173 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? (u8
)~w
: 0;
4174 /* Faults from user mode accesses to supervisor pages */
4175 u8 uf
= (pfec
& PFERR_USER_MASK
) ? (u8
)~u
: 0;
4176 /* Faults from fetches of non-executable pages*/
4177 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? (u8
)~x
: 0;
4178 /* Faults from kernel mode fetches of user pages */
4180 /* Faults from kernel mode accesses of user pages */
4184 /* Faults from kernel mode accesses to user pages */
4185 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4187 /* Not really needed: !nx will cause pte.nx to fault */
4191 /* Allow supervisor writes if !cr0.wp */
4193 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4195 /* Disallow supervisor fetches of user code if cr4.smep */
4197 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4200 * SMAP:kernel-mode data accesses from user-mode
4201 * mappings should fault. A fault is considered
4202 * as a SMAP violation if all of the following
4203 * conditions are true:
4204 * - X86_CR4_SMAP is set in CR4
4205 * - A user page is accessed
4206 * - The access is not a fetch
4207 * - Page fault in kernel mode
4208 * - if CPL = 3 or X86_EFLAGS_AC is clear
4210 * Here, we cover the first three conditions.
4211 * The fourth is computed dynamically in permission_fault();
4212 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4213 * *not* subject to SMAP restrictions.
4216 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4219 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4224 * PKU is an additional mechanism by which the paging controls access to
4225 * user-mode addresses based on the value in the PKRU register. Protection
4226 * key violations are reported through a bit in the page fault error code.
4227 * Unlike other bits of the error code, the PK bit is not known at the
4228 * call site of e.g. gva_to_gpa; it must be computed directly in
4229 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4230 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4232 * In particular the following conditions come from the error code, the
4233 * page tables and the machine state:
4234 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4235 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4236 * - PK is always zero if U=0 in the page tables
4237 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4239 * The PKRU bitmask caches the result of these four conditions. The error
4240 * code (minus the P bit) and the page table's U bit form an index into the
4241 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4242 * with the two bits of the PKRU register corresponding to the protection key.
4243 * For the first three conditions above the bits will be 00, thus masking
4244 * away both AD and WD. For all reads or if the last condition holds, WD
4245 * only will be masked away.
4247 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4258 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4259 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4264 wp
= is_write_protection(vcpu
);
4266 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4267 unsigned pfec
, pkey_bits
;
4268 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4271 ff
= pfec
& PFERR_FETCH_MASK
;
4272 uf
= pfec
& PFERR_USER_MASK
;
4273 wf
= pfec
& PFERR_WRITE_MASK
;
4275 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4276 pte_user
= pfec
& PFERR_RSVD_MASK
;
4279 * Only need to check the access which is not an
4280 * instruction fetch and is to a user page.
4282 check_pkey
= (!ff
&& pte_user
);
4284 * write access is controlled by PKRU if it is a
4285 * user access or CR0.WP = 1.
4287 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4289 /* PKRU.AD stops both read and write access. */
4290 pkey_bits
= !!check_pkey
;
4291 /* PKRU.WD stops write access. */
4292 pkey_bits
|= (!!check_write
) << 1;
4294 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4298 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4300 unsigned root_level
= mmu
->root_level
;
4302 mmu
->last_nonleaf_level
= root_level
;
4303 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4304 mmu
->last_nonleaf_level
++;
4307 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4308 struct kvm_mmu
*context
,
4311 context
->nx
= is_nx(vcpu
);
4312 context
->root_level
= level
;
4314 reset_rsvds_bits_mask(vcpu
, context
);
4315 update_permission_bitmask(vcpu
, context
, false);
4316 update_pkru_bitmask(vcpu
, context
, false);
4317 update_last_nonleaf_level(vcpu
, context
);
4319 MMU_WARN_ON(!is_pae(vcpu
));
4320 context
->page_fault
= paging64_page_fault
;
4321 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4322 context
->sync_page
= paging64_sync_page
;
4323 context
->invlpg
= paging64_invlpg
;
4324 context
->update_pte
= paging64_update_pte
;
4325 context
->shadow_root_level
= level
;
4326 context
->direct_map
= false;
4329 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4330 struct kvm_mmu
*context
)
4332 int root_level
= is_la57_mode(vcpu
) ?
4333 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4335 paging64_init_context_common(vcpu
, context
, root_level
);
4338 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4339 struct kvm_mmu
*context
)
4341 context
->nx
= false;
4342 context
->root_level
= PT32_ROOT_LEVEL
;
4344 reset_rsvds_bits_mask(vcpu
, context
);
4345 update_permission_bitmask(vcpu
, context
, false);
4346 update_pkru_bitmask(vcpu
, context
, false);
4347 update_last_nonleaf_level(vcpu
, context
);
4349 context
->page_fault
= paging32_page_fault
;
4350 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4351 context
->sync_page
= paging32_sync_page
;
4352 context
->invlpg
= paging32_invlpg
;
4353 context
->update_pte
= paging32_update_pte
;
4354 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4355 context
->direct_map
= false;
4358 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4359 struct kvm_mmu
*context
)
4361 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4364 static union kvm_mmu_extended_role
kvm_calc_mmu_role_ext(struct kvm_vcpu
*vcpu
)
4366 union kvm_mmu_extended_role ext
= {0};
4368 ext
.cr0_pg
= !!is_paging(vcpu
);
4369 ext
.cr4_pae
= !!is_pae(vcpu
);
4370 ext
.cr4_smep
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4371 ext
.cr4_smap
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4372 ext
.cr4_pse
= !!is_pse(vcpu
);
4373 ext
.cr4_pke
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
);
4374 ext
.maxphyaddr
= cpuid_maxphyaddr(vcpu
);
4381 static union kvm_mmu_role
kvm_calc_mmu_role_common(struct kvm_vcpu
*vcpu
,
4384 union kvm_mmu_role role
= {0};
4386 role
.base
.access
= ACC_ALL
;
4387 role
.base
.nxe
= !!is_nx(vcpu
);
4388 role
.base
.cr0_wp
= is_write_protection(vcpu
);
4389 role
.base
.smm
= is_smm(vcpu
);
4390 role
.base
.guest_mode
= is_guest_mode(vcpu
);
4395 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
4400 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu
*vcpu
)
4402 /* Use 5-level TDP if and only if it's useful/necessary. */
4403 if (max_tdp_level
== 5 && cpuid_maxphyaddr(vcpu
) <= 48)
4406 return max_tdp_level
;
4409 static union kvm_mmu_role
4410 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4412 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4414 role
.base
.ad_disabled
= (shadow_accessed_mask
== 0);
4415 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4416 role
.base
.direct
= true;
4417 role
.base
.gpte_is_8_bytes
= true;
4422 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4424 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4425 union kvm_mmu_role new_role
=
4426 kvm_calc_tdp_mmu_root_page_role(vcpu
, false);
4428 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4431 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4432 context
->page_fault
= kvm_tdp_page_fault
;
4433 context
->sync_page
= nonpaging_sync_page
;
4434 context
->invlpg
= NULL
;
4435 context
->update_pte
= nonpaging_update_pte
;
4436 context
->shadow_root_level
= kvm_mmu_get_tdp_level(vcpu
);
4437 context
->direct_map
= true;
4438 context
->get_guest_pgd
= get_cr3
;
4439 context
->get_pdptr
= kvm_pdptr_read
;
4440 context
->inject_page_fault
= kvm_inject_page_fault
;
4442 if (!is_paging(vcpu
)) {
4443 context
->nx
= false;
4444 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4445 context
->root_level
= 0;
4446 } else if (is_long_mode(vcpu
)) {
4447 context
->nx
= is_nx(vcpu
);
4448 context
->root_level
= is_la57_mode(vcpu
) ?
4449 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4450 reset_rsvds_bits_mask(vcpu
, context
);
4451 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4452 } else if (is_pae(vcpu
)) {
4453 context
->nx
= is_nx(vcpu
);
4454 context
->root_level
= PT32E_ROOT_LEVEL
;
4455 reset_rsvds_bits_mask(vcpu
, context
);
4456 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4458 context
->nx
= false;
4459 context
->root_level
= PT32_ROOT_LEVEL
;
4460 reset_rsvds_bits_mask(vcpu
, context
);
4461 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4464 update_permission_bitmask(vcpu
, context
, false);
4465 update_pkru_bitmask(vcpu
, context
, false);
4466 update_last_nonleaf_level(vcpu
, context
);
4467 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4470 static union kvm_mmu_role
4471 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu
*vcpu
, bool base_only
)
4473 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4475 role
.base
.smep_andnot_wp
= role
.ext
.cr4_smep
&&
4476 !is_write_protection(vcpu
);
4477 role
.base
.smap_andnot_wp
= role
.ext
.cr4_smap
&&
4478 !is_write_protection(vcpu
);
4479 role
.base
.gpte_is_8_bytes
= !!is_pae(vcpu
);
4484 static union kvm_mmu_role
4485 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4487 union kvm_mmu_role role
=
4488 kvm_calc_shadow_root_page_role_common(vcpu
, base_only
);
4490 role
.base
.direct
= !is_paging(vcpu
);
4492 if (!is_long_mode(vcpu
))
4493 role
.base
.level
= PT32E_ROOT_LEVEL
;
4494 else if (is_la57_mode(vcpu
))
4495 role
.base
.level
= PT64_ROOT_5LEVEL
;
4497 role
.base
.level
= PT64_ROOT_4LEVEL
;
4502 static void shadow_mmu_init_context(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
,
4503 u32 cr0
, u32 cr4
, u32 efer
,
4504 union kvm_mmu_role new_role
)
4506 if (!(cr0
& X86_CR0_PG
))
4507 nonpaging_init_context(vcpu
, context
);
4508 else if (efer
& EFER_LMA
)
4509 paging64_init_context(vcpu
, context
);
4510 else if (cr4
& X86_CR4_PAE
)
4511 paging32E_init_context(vcpu
, context
);
4513 paging32_init_context(vcpu
, context
);
4515 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4516 reset_shadow_zero_bits_mask(vcpu
, context
);
4519 static void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, u32 cr0
, u32 cr4
, u32 efer
)
4521 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4522 union kvm_mmu_role new_role
=
4523 kvm_calc_shadow_mmu_root_page_role(vcpu
, false);
4525 if (new_role
.as_u64
!= context
->mmu_role
.as_u64
)
4526 shadow_mmu_init_context(vcpu
, context
, cr0
, cr4
, efer
, new_role
);
4529 static union kvm_mmu_role
4530 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu
*vcpu
)
4532 union kvm_mmu_role role
=
4533 kvm_calc_shadow_root_page_role_common(vcpu
, false);
4535 role
.base
.direct
= false;
4536 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4541 void kvm_init_shadow_npt_mmu(struct kvm_vcpu
*vcpu
, u32 cr0
, u32 cr4
, u32 efer
,
4544 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4545 union kvm_mmu_role new_role
= kvm_calc_shadow_npt_root_page_role(vcpu
);
4547 context
->shadow_root_level
= new_role
.base
.level
;
4549 __kvm_mmu_new_pgd(vcpu
, nested_cr3
, new_role
.base
, false, false);
4551 if (new_role
.as_u64
!= context
->mmu_role
.as_u64
)
4552 shadow_mmu_init_context(vcpu
, context
, cr0
, cr4
, efer
, new_role
);
4554 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu
);
4556 static union kvm_mmu_role
4557 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu
*vcpu
, bool accessed_dirty
,
4558 bool execonly
, u8 level
)
4560 union kvm_mmu_role role
= {0};
4562 /* SMM flag is inherited from root_mmu */
4563 role
.base
.smm
= vcpu
->arch
.root_mmu
.mmu_role
.base
.smm
;
4565 role
.base
.level
= level
;
4566 role
.base
.gpte_is_8_bytes
= true;
4567 role
.base
.direct
= false;
4568 role
.base
.ad_disabled
= !accessed_dirty
;
4569 role
.base
.guest_mode
= true;
4570 role
.base
.access
= ACC_ALL
;
4573 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4574 * SMAP variation to denote shadow EPT entries.
4576 role
.base
.cr0_wp
= true;
4577 role
.base
.smap_andnot_wp
= true;
4579 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
4580 role
.ext
.execonly
= execonly
;
4585 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4586 bool accessed_dirty
, gpa_t new_eptp
)
4588 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4589 u8 level
= vmx_eptp_page_walk_level(new_eptp
);
4590 union kvm_mmu_role new_role
=
4591 kvm_calc_shadow_ept_root_page_role(vcpu
, accessed_dirty
,
4594 __kvm_mmu_new_pgd(vcpu
, new_eptp
, new_role
.base
, true, true);
4596 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4599 context
->shadow_root_level
= level
;
4602 context
->ept_ad
= accessed_dirty
;
4603 context
->page_fault
= ept_page_fault
;
4604 context
->gva_to_gpa
= ept_gva_to_gpa
;
4605 context
->sync_page
= ept_sync_page
;
4606 context
->invlpg
= ept_invlpg
;
4607 context
->update_pte
= ept_update_pte
;
4608 context
->root_level
= level
;
4609 context
->direct_map
= false;
4610 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4612 update_permission_bitmask(vcpu
, context
, true);
4613 update_pkru_bitmask(vcpu
, context
, true);
4614 update_last_nonleaf_level(vcpu
, context
);
4615 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4616 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4618 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4620 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4622 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4624 kvm_init_shadow_mmu(vcpu
,
4625 kvm_read_cr0_bits(vcpu
, X86_CR0_PG
),
4626 kvm_read_cr4_bits(vcpu
, X86_CR4_PAE
),
4629 context
->get_guest_pgd
= get_cr3
;
4630 context
->get_pdptr
= kvm_pdptr_read
;
4631 context
->inject_page_fault
= kvm_inject_page_fault
;
4634 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4636 union kvm_mmu_role new_role
= kvm_calc_mmu_role_common(vcpu
, false);
4637 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4639 if (new_role
.as_u64
== g_context
->mmu_role
.as_u64
)
4642 g_context
->mmu_role
.as_u64
= new_role
.as_u64
;
4643 g_context
->get_guest_pgd
= get_cr3
;
4644 g_context
->get_pdptr
= kvm_pdptr_read
;
4645 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4648 * L2 page tables are never shadowed, so there is no need to sync
4651 g_context
->invlpg
= NULL
;
4654 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4655 * L1's nested page tables (e.g. EPT12). The nested translation
4656 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4657 * L2's page tables as the first level of translation and L1's
4658 * nested page tables as the second level of translation. Basically
4659 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4661 if (!is_paging(vcpu
)) {
4662 g_context
->nx
= false;
4663 g_context
->root_level
= 0;
4664 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4665 } else if (is_long_mode(vcpu
)) {
4666 g_context
->nx
= is_nx(vcpu
);
4667 g_context
->root_level
= is_la57_mode(vcpu
) ?
4668 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4669 reset_rsvds_bits_mask(vcpu
, g_context
);
4670 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4671 } else if (is_pae(vcpu
)) {
4672 g_context
->nx
= is_nx(vcpu
);
4673 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4674 reset_rsvds_bits_mask(vcpu
, g_context
);
4675 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4677 g_context
->nx
= false;
4678 g_context
->root_level
= PT32_ROOT_LEVEL
;
4679 reset_rsvds_bits_mask(vcpu
, g_context
);
4680 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4683 update_permission_bitmask(vcpu
, g_context
, false);
4684 update_pkru_bitmask(vcpu
, g_context
, false);
4685 update_last_nonleaf_level(vcpu
, g_context
);
4688 void kvm_init_mmu(struct kvm_vcpu
*vcpu
, bool reset_roots
)
4693 vcpu
->arch
.mmu
->root_hpa
= INVALID_PAGE
;
4695 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
4696 vcpu
->arch
.mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
4699 if (mmu_is_nested(vcpu
))
4700 init_kvm_nested_mmu(vcpu
);
4701 else if (tdp_enabled
)
4702 init_kvm_tdp_mmu(vcpu
);
4704 init_kvm_softmmu(vcpu
);
4706 EXPORT_SYMBOL_GPL(kvm_init_mmu
);
4708 static union kvm_mmu_page_role
4709 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
)
4711 union kvm_mmu_role role
;
4714 role
= kvm_calc_tdp_mmu_root_page_role(vcpu
, true);
4716 role
= kvm_calc_shadow_mmu_root_page_role(vcpu
, true);
4721 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4723 kvm_mmu_unload(vcpu
);
4724 kvm_init_mmu(vcpu
, true);
4726 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4728 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4732 r
= mmu_topup_memory_caches(vcpu
, !vcpu
->arch
.mmu
->direct_map
);
4735 r
= mmu_alloc_roots(vcpu
);
4736 kvm_mmu_sync_roots(vcpu
);
4739 kvm_mmu_load_pgd(vcpu
);
4740 kvm_x86_ops
.tlb_flush_current(vcpu
);
4744 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4746 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4748 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.root_mmu
, KVM_MMU_ROOTS_ALL
);
4749 WARN_ON(VALID_PAGE(vcpu
->arch
.root_mmu
.root_hpa
));
4750 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
4751 WARN_ON(VALID_PAGE(vcpu
->arch
.guest_mmu
.root_hpa
));
4753 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4755 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4756 struct kvm_mmu_page
*sp
, u64
*spte
,
4759 if (sp
->role
.level
!= PG_LEVEL_4K
) {
4760 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4764 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4765 vcpu
->arch
.mmu
->update_pte(vcpu
, sp
, spte
, new);
4768 static bool need_remote_flush(u64 old
, u64
new)
4770 if (!is_shadow_present_pte(old
))
4772 if (!is_shadow_present_pte(new))
4774 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4776 old
^= shadow_nx_mask
;
4777 new ^= shadow_nx_mask
;
4778 return (old
& ~new & PT64_PERM_MASK
) != 0;
4781 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4788 * Assume that the pte write on a page table of the same type
4789 * as the current vcpu paging mode since we update the sptes only
4790 * when they have the same mode.
4792 if (is_pae(vcpu
) && *bytes
== 4) {
4793 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4798 if (*bytes
== 4 || *bytes
== 8) {
4799 r
= kvm_vcpu_read_guest_atomic(vcpu
, *gpa
, &gentry
, *bytes
);
4808 * If we're seeing too many writes to a page, it may no longer be a page table,
4809 * or we may be forking, in which case it is better to unmap the page.
4811 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4814 * Skip write-flooding detected for the sp whose level is 1, because
4815 * it can become unsync, then the guest page is not write-protected.
4817 if (sp
->role
.level
== PG_LEVEL_4K
)
4820 atomic_inc(&sp
->write_flooding_count
);
4821 return atomic_read(&sp
->write_flooding_count
) >= 3;
4825 * Misaligned accesses are too much trouble to fix up; also, they usually
4826 * indicate a page is not used as a page table.
4828 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4831 unsigned offset
, pte_size
, misaligned
;
4833 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4834 gpa
, bytes
, sp
->role
.word
);
4836 offset
= offset_in_page(gpa
);
4837 pte_size
= sp
->role
.gpte_is_8_bytes
? 8 : 4;
4840 * Sometimes, the OS only writes the last one bytes to update status
4841 * bits, for example, in linux, andb instruction is used in clear_bit().
4843 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4846 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4847 misaligned
|= bytes
< 4;
4852 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4854 unsigned page_offset
, quadrant
;
4858 page_offset
= offset_in_page(gpa
);
4859 level
= sp
->role
.level
;
4861 if (!sp
->role
.gpte_is_8_bytes
) {
4862 page_offset
<<= 1; /* 32->64 */
4864 * A 32-bit pde maps 4MB while the shadow pdes map
4865 * only 2MB. So we need to double the offset again
4866 * and zap two pdes instead of one.
4868 if (level
== PT32_ROOT_LEVEL
) {
4869 page_offset
&= ~7; /* kill rounding error */
4873 quadrant
= page_offset
>> PAGE_SHIFT
;
4874 page_offset
&= ~PAGE_MASK
;
4875 if (quadrant
!= sp
->role
.quadrant
)
4879 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4884 * Ignore various flags when determining if a SPTE can be immediately
4885 * overwritten for the current MMU.
4886 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
4887 * match the current MMU role, as MMU's level tracks the root level.
4888 * - access: updated based on the new guest PTE
4889 * - quadrant: handled by get_written_sptes()
4890 * - invalid: always false (loop only walks valid shadow pages)
4892 static const union kvm_mmu_page_role role_ign
= {
4899 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4900 const u8
*new, int bytes
,
4901 struct kvm_page_track_notifier_node
*node
)
4903 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4904 struct kvm_mmu_page
*sp
;
4905 LIST_HEAD(invalid_list
);
4906 u64 entry
, gentry
, *spte
;
4908 bool remote_flush
, local_flush
;
4911 * If we don't have indirect shadow pages, it means no page is
4912 * write-protected, so we can exit simply.
4914 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4917 remote_flush
= local_flush
= false;
4919 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4922 * No need to care whether allocation memory is successful
4923 * or not since pte prefetch is skiped if it does not have
4924 * enough objects in the cache.
4926 mmu_topup_memory_caches(vcpu
, true);
4928 spin_lock(&vcpu
->kvm
->mmu_lock
);
4930 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, &bytes
);
4932 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4933 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4935 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4936 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4937 detect_write_flooding(sp
)) {
4938 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4939 ++vcpu
->kvm
->stat
.mmu_flooded
;
4943 spte
= get_written_sptes(sp
, gpa
, &npte
);
4949 u32 base_role
= vcpu
->arch
.mmu
->mmu_role
.base
.word
;
4952 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
, NULL
);
4954 !((sp
->role
.word
^ base_role
) & ~role_ign
.word
) &&
4956 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4957 if (need_remote_flush(entry
, *spte
))
4958 remote_flush
= true;
4962 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4963 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4964 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4967 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4972 if (vcpu
->arch
.mmu
->direct_map
)
4975 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4977 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4981 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4983 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
, u64 error_code
,
4984 void *insn
, int insn_len
)
4986 int r
, emulation_type
= EMULTYPE_PF
;
4987 bool direct
= vcpu
->arch
.mmu
->direct_map
;
4989 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
4990 return RET_PF_RETRY
;
4993 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4994 r
= handle_mmio_page_fault(vcpu
, cr2_or_gpa
, direct
);
4995 if (r
== RET_PF_EMULATE
)
4999 if (r
== RET_PF_INVALID
) {
5000 r
= kvm_mmu_do_page_fault(vcpu
, cr2_or_gpa
,
5001 lower_32_bits(error_code
), false);
5002 if (WARN_ON_ONCE(r
== RET_PF_INVALID
))
5008 if (r
!= RET_PF_EMULATE
)
5012 * Before emulating the instruction, check if the error code
5013 * was due to a RO violation while translating the guest page.
5014 * This can occur when using nested virtualization with nested
5015 * paging in both guests. If true, we simply unprotect the page
5016 * and resume the guest.
5018 if (vcpu
->arch
.mmu
->direct_map
&&
5019 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
5020 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2_or_gpa
));
5025 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5026 * optimistically try to just unprotect the page and let the processor
5027 * re-execute the instruction that caused the page fault. Do not allow
5028 * retrying MMIO emulation, as it's not only pointless but could also
5029 * cause us to enter an infinite loop because the processor will keep
5030 * faulting on the non-existent MMIO address. Retrying an instruction
5031 * from a nested guest is also pointless and dangerous as we are only
5032 * explicitly shadowing L1's page tables, i.e. unprotecting something
5033 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5035 if (!mmio_info_in_cache(vcpu
, cr2_or_gpa
, direct
) && !is_guest_mode(vcpu
))
5036 emulation_type
|= EMULTYPE_ALLOW_RETRY_PF
;
5038 return x86_emulate_instruction(vcpu
, cr2_or_gpa
, emulation_type
, insn
,
5041 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
5043 void kvm_mmu_invalidate_gva(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
5044 gva_t gva
, hpa_t root_hpa
)
5048 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5049 if (mmu
!= &vcpu
->arch
.guest_mmu
) {
5050 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5051 if (is_noncanonical_address(gva
, vcpu
))
5054 kvm_x86_ops
.tlb_flush_gva(vcpu
, gva
);
5060 if (root_hpa
== INVALID_PAGE
) {
5061 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5064 * INVLPG is required to invalidate any global mappings for the VA,
5065 * irrespective of PCID. Since it would take us roughly similar amount
5066 * of work to determine whether any of the prev_root mappings of the VA
5067 * is marked global, or to just sync it blindly, so we might as well
5068 * just always sync it.
5070 * Mappings not reachable via the current cr3 or the prev_roots will be
5071 * synced when switching to that cr3, so nothing needs to be done here
5074 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5075 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
5076 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5078 mmu
->invlpg(vcpu
, gva
, root_hpa
);
5081 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva
);
5083 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
5085 kvm_mmu_invalidate_gva(vcpu
, vcpu
->arch
.mmu
, gva
, INVALID_PAGE
);
5086 ++vcpu
->stat
.invlpg
;
5088 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
5091 void kvm_mmu_invpcid_gva(struct kvm_vcpu
*vcpu
, gva_t gva
, unsigned long pcid
)
5093 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5094 bool tlb_flush
= false;
5097 if (pcid
== kvm_get_active_pcid(vcpu
)) {
5098 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5102 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
5103 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
) &&
5104 pcid
== kvm_get_pcid(vcpu
, mmu
->prev_roots
[i
].pgd
)) {
5105 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5111 kvm_x86_ops
.tlb_flush_gva(vcpu
, gva
);
5113 ++vcpu
->stat
.invlpg
;
5116 * Mappings not reachable via the current cr3 or the prev_roots will be
5117 * synced when switching to that cr3, so nothing needs to be done here
5121 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva
);
5123 void kvm_configure_mmu(bool enable_tdp
, int tdp_max_root_level
,
5124 int tdp_huge_page_level
)
5126 tdp_enabled
= enable_tdp
;
5127 max_tdp_level
= tdp_max_root_level
;
5130 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5131 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5132 * the kernel is not. But, KVM never creates a page size greater than
5133 * what is used by the kernel for any given HVA, i.e. the kernel's
5134 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5137 max_huge_page_level
= tdp_huge_page_level
;
5138 else if (boot_cpu_has(X86_FEATURE_GBPAGES
))
5139 max_huge_page_level
= PG_LEVEL_1G
;
5141 max_huge_page_level
= PG_LEVEL_2M
;
5143 EXPORT_SYMBOL_GPL(kvm_configure_mmu
);
5145 /* The return value indicates if tlb flush on all vcpus is needed. */
5146 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
5148 /* The caller should hold mmu-lock before calling this function. */
5149 static __always_inline
bool
5150 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5151 slot_level_handler fn
, int start_level
, int end_level
,
5152 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5154 struct slot_rmap_walk_iterator iterator
;
5157 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5158 end_gfn
, &iterator
) {
5160 flush
|= fn(kvm
, iterator
.rmap
);
5162 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5163 if (flush
&& lock_flush_tlb
) {
5164 kvm_flush_remote_tlbs_with_address(kvm
,
5166 iterator
.gfn
- start_gfn
+ 1);
5169 cond_resched_lock(&kvm
->mmu_lock
);
5173 if (flush
&& lock_flush_tlb
) {
5174 kvm_flush_remote_tlbs_with_address(kvm
, start_gfn
,
5175 end_gfn
- start_gfn
+ 1);
5182 static __always_inline
bool
5183 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5184 slot_level_handler fn
, int start_level
, int end_level
,
5185 bool lock_flush_tlb
)
5187 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5188 end_level
, memslot
->base_gfn
,
5189 memslot
->base_gfn
+ memslot
->npages
- 1,
5193 static __always_inline
bool
5194 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5195 slot_level_handler fn
, bool lock_flush_tlb
)
5197 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
,
5198 KVM_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5201 static __always_inline
bool
5202 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5203 slot_level_handler fn
, bool lock_flush_tlb
)
5205 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
+ 1,
5206 KVM_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5209 static __always_inline
bool
5210 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5211 slot_level_handler fn
, bool lock_flush_tlb
)
5213 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
,
5214 PG_LEVEL_4K
, lock_flush_tlb
);
5217 static void free_mmu_pages(struct kvm_mmu
*mmu
)
5219 free_page((unsigned long)mmu
->pae_root
);
5220 free_page((unsigned long)mmu
->lm_root
);
5223 static int __kvm_mmu_create(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
5228 mmu
->root_hpa
= INVALID_PAGE
;
5230 mmu
->translate_gpa
= translate_gpa
;
5231 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5232 mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5235 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5236 * while the PDP table is a per-vCPU construct that's allocated at MMU
5237 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5238 * x86_64. Therefore we need to allocate the PDP table in the first
5239 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5240 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5241 * skip allocating the PDP table.
5243 if (tdp_enabled
&& kvm_mmu_get_tdp_level(vcpu
) > PT32E_ROOT_LEVEL
)
5246 page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_DMA32
);
5250 mmu
->pae_root
= page_address(page
);
5251 for (i
= 0; i
< 4; ++i
)
5252 mmu
->pae_root
[i
] = INVALID_PAGE
;
5257 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5261 vcpu
->arch
.mmu_pte_list_desc_cache
.kmem_cache
= pte_list_desc_cache
;
5262 vcpu
->arch
.mmu_pte_list_desc_cache
.gfp_zero
= __GFP_ZERO
;
5264 vcpu
->arch
.mmu_page_header_cache
.kmem_cache
= mmu_page_header_cache
;
5265 vcpu
->arch
.mmu_page_header_cache
.gfp_zero
= __GFP_ZERO
;
5267 vcpu
->arch
.mmu_shadow_page_cache
.gfp_zero
= __GFP_ZERO
;
5269 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
5270 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
5272 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5274 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.guest_mmu
);
5278 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.root_mmu
);
5280 goto fail_allocate_root
;
5284 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5288 #define BATCH_ZAP_PAGES 10
5289 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5291 struct kvm_mmu_page
*sp
, *node
;
5292 int nr_zapped
, batch
= 0;
5295 list_for_each_entry_safe_reverse(sp
, node
,
5296 &kvm
->arch
.active_mmu_pages
, link
) {
5298 * No obsolete valid page exists before a newly created page
5299 * since active_mmu_pages is a FIFO list.
5301 if (!is_obsolete_sp(kvm
, sp
))
5305 * Invalid pages should never land back on the list of active
5306 * pages. Skip the bogus page, otherwise we'll get stuck in an
5307 * infinite loop if the page gets put back on the list (again).
5309 if (WARN_ON(sp
->role
.invalid
))
5313 * No need to flush the TLB since we're only zapping shadow
5314 * pages with an obsolete generation number and all vCPUS have
5315 * loaded a new root, i.e. the shadow pages being zapped cannot
5316 * be in active use by the guest.
5318 if (batch
>= BATCH_ZAP_PAGES
&&
5319 cond_resched_lock(&kvm
->mmu_lock
)) {
5324 if (__kvm_mmu_prepare_zap_page(kvm
, sp
,
5325 &kvm
->arch
.zapped_obsolete_pages
, &nr_zapped
)) {
5332 * Trigger a remote TLB flush before freeing the page tables to ensure
5333 * KVM is not in the middle of a lockless shadow page table walk, which
5334 * may reference the pages.
5336 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5340 * Fast invalidate all shadow pages and use lock-break technique
5341 * to zap obsolete pages.
5343 * It's required when memslot is being deleted or VM is being
5344 * destroyed, in these cases, we should ensure that KVM MMU does
5345 * not use any resource of the being-deleted slot or all slots
5346 * after calling the function.
5348 static void kvm_mmu_zap_all_fast(struct kvm
*kvm
)
5350 lockdep_assert_held(&kvm
->slots_lock
);
5352 spin_lock(&kvm
->mmu_lock
);
5353 trace_kvm_mmu_zap_all_fast(kvm
);
5356 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5357 * held for the entire duration of zapping obsolete pages, it's
5358 * impossible for there to be multiple invalid generations associated
5359 * with *valid* shadow pages at any given time, i.e. there is exactly
5360 * one valid generation and (at most) one invalid generation.
5362 kvm
->arch
.mmu_valid_gen
= kvm
->arch
.mmu_valid_gen
? 0 : 1;
5365 * Notify all vcpus to reload its shadow page table and flush TLB.
5366 * Then all vcpus will switch to new shadow page table with the new
5369 * Note: we need to do this under the protection of mmu_lock,
5370 * otherwise, vcpu would purge shadow page but miss tlb flush.
5372 kvm_reload_remote_mmus(kvm
);
5374 kvm_zap_obsolete_pages(kvm
);
5376 if (kvm
->arch
.tdp_mmu_enabled
)
5377 kvm_tdp_mmu_zap_all(kvm
);
5379 spin_unlock(&kvm
->mmu_lock
);
5382 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5384 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5387 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5388 struct kvm_memory_slot
*slot
,
5389 struct kvm_page_track_notifier_node
*node
)
5391 kvm_mmu_zap_all_fast(kvm
);
5394 void kvm_mmu_init_vm(struct kvm
*kvm
)
5396 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5398 kvm_mmu_init_tdp_mmu(kvm
);
5400 node
->track_write
= kvm_mmu_pte_write
;
5401 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5402 kvm_page_track_register_notifier(kvm
, node
);
5405 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5407 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5409 kvm_page_track_unregister_notifier(kvm
, node
);
5411 kvm_mmu_uninit_tdp_mmu(kvm
);
5414 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5416 struct kvm_memslots
*slots
;
5417 struct kvm_memory_slot
*memslot
;
5421 spin_lock(&kvm
->mmu_lock
);
5422 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5423 slots
= __kvm_memslots(kvm
, i
);
5424 kvm_for_each_memslot(memslot
, slots
) {
5427 start
= max(gfn_start
, memslot
->base_gfn
);
5428 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5432 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5434 KVM_MAX_HUGEPAGE_LEVEL
,
5435 start
, end
- 1, true);
5439 if (kvm
->arch
.tdp_mmu_enabled
) {
5440 flush
= kvm_tdp_mmu_zap_gfn_range(kvm
, gfn_start
, gfn_end
);
5442 kvm_flush_remote_tlbs(kvm
);
5445 spin_unlock(&kvm
->mmu_lock
);
5448 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5449 struct kvm_rmap_head
*rmap_head
)
5451 return __rmap_write_protect(kvm
, rmap_head
, false);
5454 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5455 struct kvm_memory_slot
*memslot
,
5460 spin_lock(&kvm
->mmu_lock
);
5461 flush
= slot_handle_level(kvm
, memslot
, slot_rmap_write_protect
,
5462 start_level
, KVM_MAX_HUGEPAGE_LEVEL
, false);
5463 spin_unlock(&kvm
->mmu_lock
);
5466 * We can flush all the TLBs out of the mmu lock without TLB
5467 * corruption since we just change the spte from writable to
5468 * readonly so that we only need to care the case of changing
5469 * spte from present to present (changing the spte from present
5470 * to nonpresent will flush all the TLBs immediately), in other
5471 * words, the only case we care is mmu_spte_update() where we
5472 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5473 * instead of PT_WRITABLE_MASK, that means it does not depend
5474 * on PT_WRITABLE_MASK anymore.
5477 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5480 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5481 struct kvm_rmap_head
*rmap_head
)
5484 struct rmap_iterator iter
;
5485 int need_tlb_flush
= 0;
5487 struct kvm_mmu_page
*sp
;
5490 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5491 sp
= sptep_to_sp(sptep
);
5492 pfn
= spte_to_pfn(*sptep
);
5495 * We cannot do huge page mapping for indirect shadow pages,
5496 * which are found on the last rmap (level = 1) when not using
5497 * tdp; such shadow pages are synced with the page table in
5498 * the guest, and the guest page table is using 4K page size
5499 * mapping if the indirect sp has level = 1.
5501 if (sp
->role
.direct
&& !kvm_is_reserved_pfn(pfn
) &&
5502 (kvm_is_zone_device_pfn(pfn
) ||
5503 PageCompound(pfn_to_page(pfn
)))) {
5504 pte_list_remove(rmap_head
, sptep
);
5506 if (kvm_available_flush_tlb_with_range())
5507 kvm_flush_remote_tlbs_with_address(kvm
, sp
->gfn
,
5508 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
5516 return need_tlb_flush
;
5519 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5520 const struct kvm_memory_slot
*memslot
)
5522 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5523 spin_lock(&kvm
->mmu_lock
);
5524 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5525 kvm_mmu_zap_collapsible_spte
, true);
5526 spin_unlock(&kvm
->mmu_lock
);
5529 void kvm_arch_flush_remote_tlbs_memslot(struct kvm
*kvm
,
5530 struct kvm_memory_slot
*memslot
)
5533 * All current use cases for flushing the TLBs for a specific memslot
5534 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5535 * The interaction between the various operations on memslot must be
5536 * serialized by slots_locks to ensure the TLB flush from one operation
5537 * is observed by any other operation on the same memslot.
5539 lockdep_assert_held(&kvm
->slots_lock
);
5540 kvm_flush_remote_tlbs_with_address(kvm
, memslot
->base_gfn
,
5544 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5545 struct kvm_memory_slot
*memslot
)
5549 spin_lock(&kvm
->mmu_lock
);
5550 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5551 spin_unlock(&kvm
->mmu_lock
);
5554 * It's also safe to flush TLBs out of mmu lock here as currently this
5555 * function is only used for dirty logging, in which case flushing TLB
5556 * out of mmu lock also guarantees no dirty pages will be lost in
5560 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5562 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5564 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5565 struct kvm_memory_slot
*memslot
)
5569 spin_lock(&kvm
->mmu_lock
);
5570 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5572 spin_unlock(&kvm
->mmu_lock
);
5575 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5577 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5579 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5580 struct kvm_memory_slot
*memslot
)
5584 spin_lock(&kvm
->mmu_lock
);
5585 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5586 spin_unlock(&kvm
->mmu_lock
);
5589 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5591 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5593 void kvm_mmu_zap_all(struct kvm
*kvm
)
5595 struct kvm_mmu_page
*sp
, *node
;
5596 LIST_HEAD(invalid_list
);
5599 spin_lock(&kvm
->mmu_lock
);
5601 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
5602 if (WARN_ON(sp
->role
.invalid
))
5604 if (__kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
, &ign
))
5606 if (cond_resched_lock(&kvm
->mmu_lock
))
5610 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5612 if (kvm
->arch
.tdp_mmu_enabled
)
5613 kvm_tdp_mmu_zap_all(kvm
);
5615 spin_unlock(&kvm
->mmu_lock
);
5618 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, u64 gen
)
5620 WARN_ON(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
);
5622 gen
&= MMIO_SPTE_GEN_MASK
;
5625 * Generation numbers are incremented in multiples of the number of
5626 * address spaces in order to provide unique generations across all
5627 * address spaces. Strip what is effectively the address space
5628 * modifier prior to checking for a wrap of the MMIO generation so
5629 * that a wrap in any address space is detected.
5631 gen
&= ~((u64
)KVM_ADDRESS_SPACE_NUM
- 1);
5634 * The very rare case: if the MMIO generation number has wrapped,
5635 * zap all shadow pages.
5637 if (unlikely(gen
== 0)) {
5638 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5639 kvm_mmu_zap_all_fast(kvm
);
5643 static unsigned long
5644 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5647 int nr_to_scan
= sc
->nr_to_scan
;
5648 unsigned long freed
= 0;
5650 mutex_lock(&kvm_lock
);
5652 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5654 LIST_HEAD(invalid_list
);
5657 * Never scan more than sc->nr_to_scan VM instances.
5658 * Will not hit this condition practically since we do not try
5659 * to shrink more than one VM and it is very unlikely to see
5660 * !n_used_mmu_pages so many times.
5665 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5666 * here. We may skip a VM instance errorneosly, but we do not
5667 * want to shrink a VM that only started to populate its MMU
5670 if (!kvm
->arch
.n_used_mmu_pages
&&
5671 !kvm_has_zapped_obsolete_pages(kvm
))
5674 idx
= srcu_read_lock(&kvm
->srcu
);
5675 spin_lock(&kvm
->mmu_lock
);
5677 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5678 kvm_mmu_commit_zap_page(kvm
,
5679 &kvm
->arch
.zapped_obsolete_pages
);
5683 freed
= kvm_mmu_zap_oldest_mmu_pages(kvm
, sc
->nr_to_scan
);
5686 spin_unlock(&kvm
->mmu_lock
);
5687 srcu_read_unlock(&kvm
->srcu
, idx
);
5690 * unfair on small ones
5691 * per-vm shrinkers cry out
5692 * sadness comes quickly
5694 list_move_tail(&kvm
->vm_list
, &vm_list
);
5698 mutex_unlock(&kvm_lock
);
5702 static unsigned long
5703 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5705 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5708 static struct shrinker mmu_shrinker
= {
5709 .count_objects
= mmu_shrink_count
,
5710 .scan_objects
= mmu_shrink_scan
,
5711 .seeks
= DEFAULT_SEEKS
* 10,
5714 static void mmu_destroy_caches(void)
5716 kmem_cache_destroy(pte_list_desc_cache
);
5717 kmem_cache_destroy(mmu_page_header_cache
);
5720 static void kvm_set_mmio_spte_mask(void)
5725 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5726 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5727 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5728 * 52-bit physical addresses then there are no reserved PA bits in the
5729 * PTEs and so the reserved PA approach must be disabled.
5731 if (shadow_phys_bits
< 52)
5732 mask
= BIT_ULL(51) | PT_PRESENT_MASK
;
5736 kvm_mmu_set_mmio_spte_mask(mask
, ACC_WRITE_MASK
| ACC_USER_MASK
);
5739 static bool get_nx_auto_mode(void)
5741 /* Return true when CPU has the bug, and mitigations are ON */
5742 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT
) && !cpu_mitigations_off();
5745 static void __set_nx_huge_pages(bool val
)
5747 nx_huge_pages
= itlb_multihit_kvm_mitigation
= val
;
5750 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
)
5752 bool old_val
= nx_huge_pages
;
5755 /* In "auto" mode deploy workaround only if CPU has the bug. */
5756 if (sysfs_streq(val
, "off"))
5758 else if (sysfs_streq(val
, "force"))
5760 else if (sysfs_streq(val
, "auto"))
5761 new_val
= get_nx_auto_mode();
5762 else if (strtobool(val
, &new_val
) < 0)
5765 __set_nx_huge_pages(new_val
);
5767 if (new_val
!= old_val
) {
5770 mutex_lock(&kvm_lock
);
5772 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5773 mutex_lock(&kvm
->slots_lock
);
5774 kvm_mmu_zap_all_fast(kvm
);
5775 mutex_unlock(&kvm
->slots_lock
);
5777 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
5779 mutex_unlock(&kvm_lock
);
5785 int kvm_mmu_module_init(void)
5789 if (nx_huge_pages
== -1)
5790 __set_nx_huge_pages(get_nx_auto_mode());
5793 * MMU roles use union aliasing which is, generally speaking, an
5794 * undefined behavior. However, we supposedly know how compilers behave
5795 * and the current status quo is unlikely to change. Guardians below are
5796 * supposed to let us know if the assumption becomes false.
5798 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role
) != sizeof(u32
));
5799 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role
) != sizeof(u32
));
5800 BUILD_BUG_ON(sizeof(union kvm_mmu_role
) != sizeof(u64
));
5802 kvm_mmu_reset_all_pte_masks();
5804 kvm_set_mmio_spte_mask();
5806 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5807 sizeof(struct pte_list_desc
),
5808 0, SLAB_ACCOUNT
, NULL
);
5809 if (!pte_list_desc_cache
)
5812 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5813 sizeof(struct kvm_mmu_page
),
5814 0, SLAB_ACCOUNT
, NULL
);
5815 if (!mmu_page_header_cache
)
5818 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5821 ret
= register_shrinker(&mmu_shrinker
);
5828 mmu_destroy_caches();
5833 * Calculate mmu pages needed for kvm.
5835 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm
*kvm
)
5837 unsigned long nr_mmu_pages
;
5838 unsigned long nr_pages
= 0;
5839 struct kvm_memslots
*slots
;
5840 struct kvm_memory_slot
*memslot
;
5843 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5844 slots
= __kvm_memslots(kvm
, i
);
5846 kvm_for_each_memslot(memslot
, slots
)
5847 nr_pages
+= memslot
->npages
;
5850 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5851 nr_mmu_pages
= max(nr_mmu_pages
, KVM_MIN_ALLOC_MMU_PAGES
);
5853 return nr_mmu_pages
;
5856 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5858 kvm_mmu_unload(vcpu
);
5859 free_mmu_pages(&vcpu
->arch
.root_mmu
);
5860 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5861 mmu_free_memory_caches(vcpu
);
5864 void kvm_mmu_module_exit(void)
5866 mmu_destroy_caches();
5867 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5868 unregister_shrinker(&mmu_shrinker
);
5869 mmu_audit_disable();
5872 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
)
5874 unsigned int old_val
;
5877 old_val
= nx_huge_pages_recovery_ratio
;
5878 err
= param_set_uint(val
, kp
);
5882 if (READ_ONCE(nx_huge_pages
) &&
5883 !old_val
&& nx_huge_pages_recovery_ratio
) {
5886 mutex_lock(&kvm_lock
);
5888 list_for_each_entry(kvm
, &vm_list
, vm_list
)
5889 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
5891 mutex_unlock(&kvm_lock
);
5897 static void kvm_recover_nx_lpages(struct kvm
*kvm
)
5900 struct kvm_mmu_page
*sp
;
5902 LIST_HEAD(invalid_list
);
5905 rcu_idx
= srcu_read_lock(&kvm
->srcu
);
5906 spin_lock(&kvm
->mmu_lock
);
5908 ratio
= READ_ONCE(nx_huge_pages_recovery_ratio
);
5909 to_zap
= ratio
? DIV_ROUND_UP(kvm
->stat
.nx_lpage_splits
, ratio
) : 0;
5910 for ( ; to_zap
; --to_zap
) {
5911 if (list_empty(&kvm
->arch
.lpage_disallowed_mmu_pages
))
5915 * We use a separate list instead of just using active_mmu_pages
5916 * because the number of lpage_disallowed pages is expected to
5917 * be relatively small compared to the total.
5919 sp
= list_first_entry(&kvm
->arch
.lpage_disallowed_mmu_pages
,
5920 struct kvm_mmu_page
,
5921 lpage_disallowed_link
);
5922 WARN_ON_ONCE(!sp
->lpage_disallowed
);
5923 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
5924 WARN_ON_ONCE(sp
->lpage_disallowed
);
5926 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5927 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5928 cond_resched_lock(&kvm
->mmu_lock
);
5931 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5933 spin_unlock(&kvm
->mmu_lock
);
5934 srcu_read_unlock(&kvm
->srcu
, rcu_idx
);
5937 static long get_nx_lpage_recovery_timeout(u64 start_time
)
5939 return READ_ONCE(nx_huge_pages
) && READ_ONCE(nx_huge_pages_recovery_ratio
)
5940 ? start_time
+ 60 * HZ
- get_jiffies_64()
5941 : MAX_SCHEDULE_TIMEOUT
;
5944 static int kvm_nx_lpage_recovery_worker(struct kvm
*kvm
, uintptr_t data
)
5947 long remaining_time
;
5950 start_time
= get_jiffies_64();
5951 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
5953 set_current_state(TASK_INTERRUPTIBLE
);
5954 while (!kthread_should_stop() && remaining_time
> 0) {
5955 schedule_timeout(remaining_time
);
5956 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
5957 set_current_state(TASK_INTERRUPTIBLE
);
5960 set_current_state(TASK_RUNNING
);
5962 if (kthread_should_stop())
5965 kvm_recover_nx_lpages(kvm
);
5969 int kvm_mmu_post_init_vm(struct kvm
*kvm
)
5973 err
= kvm_vm_create_worker_thread(kvm
, kvm_nx_lpage_recovery_worker
, 0,
5974 "kvm-nx-lpage-recovery",
5975 &kvm
->arch
.nx_lpage_recovery_thread
);
5977 kthread_unpark(kvm
->arch
.nx_lpage_recovery_thread
);
5982 void kvm_mmu_pre_destroy_vm(struct kvm
*kvm
)
5984 if (kvm
->arch
.nx_lpage_recovery_thread
)
5985 kthread_stop(kvm
->arch
.nx_lpage_recovery_thread
);