1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation
;
58 static int __read_mostly nx_huge_pages
= -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio
= 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio
= 60;
66 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
);
67 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
);
69 static const struct kernel_param_ops nx_huge_pages_ops
= {
70 .set
= set_nx_huge_pages
,
71 .get
= param_get_bool
,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops
= {
75 .set
= set_nx_huge_pages_recovery_ratio
,
76 .get
= param_get_uint
,
79 module_param_cb(nx_huge_pages
, &nx_huge_pages_ops
, &nx_huge_pages
, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages
, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio
, &nx_huge_pages_recovery_ratio_ops
,
82 &nx_huge_pages_recovery_ratio
, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio
, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse
;
86 module_param_named(flush_on_reuse
, force_flush_and_sync_on_reuse
, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled
= false;
97 static int max_huge_page_level __read_mostly
;
98 static int max_tdp_level __read_mostly
;
101 AUDIT_PRE_PAGE_FAULT
,
102 AUDIT_POST_PAGE_FAULT
,
104 AUDIT_POST_PTE_WRITE
,
111 module_param(dbg
, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc
{
142 u64
*sptes
[PTE_LIST_EXT
];
143 struct pte_list_desc
*more
;
146 struct kvm_shadow_walk_iterator
{
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache
*pte_list_desc_cache
;
172 struct kmem_cache
*mmu_page_header_cache
;
173 static struct percpu_counter kvm_total_used_mmu_pages
;
175 static void mmu_spte_set(u64
*sptep
, u64 spte
);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
);
179 #define CREATE_TRACE_POINTS
180 #include "mmutrace.h"
183 static inline bool kvm_available_flush_tlb_with_range(void)
185 return kvm_x86_ops
.tlb_remote_flush_with_range
;
188 static void kvm_flush_remote_tlbs_with_range(struct kvm
*kvm
,
189 struct kvm_tlb_range
*range
)
193 if (range
&& kvm_x86_ops
.tlb_remote_flush_with_range
)
194 ret
= static_call(kvm_x86_tlb_remote_flush_with_range
)(kvm
, range
);
197 kvm_flush_remote_tlbs(kvm
);
200 void kvm_flush_remote_tlbs_with_address(struct kvm
*kvm
,
201 u64 start_gfn
, u64 pages
)
203 struct kvm_tlb_range range
;
205 range
.start_gfn
= start_gfn
;
208 kvm_flush_remote_tlbs_with_range(kvm
, &range
);
211 bool is_nx_huge_page_enabled(void)
213 return READ_ONCE(nx_huge_pages
);
216 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
219 u64 spte
= make_mmio_spte(vcpu
, gfn
, access
);
221 trace_mark_mmio_spte(sptep
, gfn
, spte
);
222 mmu_spte_set(sptep
, spte
);
225 static gfn_t
get_mmio_spte_gfn(u64 spte
)
227 u64 gpa
= spte
& shadow_nonpresent_or_rsvd_lower_gfn_mask
;
229 gpa
|= (spte
>> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN
)
230 & shadow_nonpresent_or_rsvd_mask
;
232 return gpa
>> PAGE_SHIFT
;
235 static unsigned get_mmio_spte_access(u64 spte
)
237 return spte
& shadow_mmio_access_mask
;
240 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
242 u64 kvm_gen
, spte_gen
, gen
;
244 gen
= kvm_vcpu_memslots(vcpu
)->generation
;
245 if (unlikely(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
))
248 kvm_gen
= gen
& MMIO_SPTE_GEN_MASK
;
249 spte_gen
= get_mmio_spte_generation(spte
);
251 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
252 return likely(kvm_gen
== spte_gen
);
255 static gpa_t
translate_gpa(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 access
,
256 struct x86_exception
*exception
)
258 /* Check if guest physical address doesn't exceed guest maximum */
259 if (kvm_vcpu_is_illegal_gpa(vcpu
, gpa
)) {
260 exception
->error_code
|= PFERR_RSVD_MASK
;
267 static int is_cpuid_PSE36(void)
272 static int is_nx(struct kvm_vcpu
*vcpu
)
274 return vcpu
->arch
.efer
& EFER_NX
;
277 static gfn_t
pse36_gfn_delta(u32 gpte
)
279 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
281 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
285 static void __set_spte(u64
*sptep
, u64 spte
)
287 WRITE_ONCE(*sptep
, spte
);
290 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
292 WRITE_ONCE(*sptep
, spte
);
295 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
297 return xchg(sptep
, spte
);
300 static u64
__get_spte_lockless(u64
*sptep
)
302 return READ_ONCE(*sptep
);
313 static void count_spte_clear(u64
*sptep
, u64 spte
)
315 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
317 if (is_shadow_present_pte(spte
))
320 /* Ensure the spte is completely set before we increase the count */
322 sp
->clear_spte_count
++;
325 static void __set_spte(u64
*sptep
, u64 spte
)
327 union split_spte
*ssptep
, sspte
;
329 ssptep
= (union split_spte
*)sptep
;
330 sspte
= (union split_spte
)spte
;
332 ssptep
->spte_high
= sspte
.spte_high
;
335 * If we map the spte from nonpresent to present, We should store
336 * the high bits firstly, then set present bit, so cpu can not
337 * fetch this spte while we are setting the spte.
341 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
344 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
346 union split_spte
*ssptep
, sspte
;
348 ssptep
= (union split_spte
*)sptep
;
349 sspte
= (union split_spte
)spte
;
351 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
354 * If we map the spte from present to nonpresent, we should clear
355 * present bit firstly to avoid vcpu fetch the old high bits.
359 ssptep
->spte_high
= sspte
.spte_high
;
360 count_spte_clear(sptep
, spte
);
363 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
365 union split_spte
*ssptep
, sspte
, orig
;
367 ssptep
= (union split_spte
*)sptep
;
368 sspte
= (union split_spte
)spte
;
370 /* xchg acts as a barrier before the setting of the high bits */
371 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
372 orig
.spte_high
= ssptep
->spte_high
;
373 ssptep
->spte_high
= sspte
.spte_high
;
374 count_spte_clear(sptep
, spte
);
380 * The idea using the light way get the spte on x86_32 guest is from
381 * gup_get_pte (mm/gup.c).
383 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
384 * coalesces them and we are running out of the MMU lock. Therefore
385 * we need to protect against in-progress updates of the spte.
387 * Reading the spte while an update is in progress may get the old value
388 * for the high part of the spte. The race is fine for a present->non-present
389 * change (because the high part of the spte is ignored for non-present spte),
390 * but for a present->present change we must reread the spte.
392 * All such changes are done in two steps (present->non-present and
393 * non-present->present), hence it is enough to count the number of
394 * present->non-present updates: if it changed while reading the spte,
395 * we might have hit the race. This is done using clear_spte_count.
397 static u64
__get_spte_lockless(u64
*sptep
)
399 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
400 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
404 count
= sp
->clear_spte_count
;
407 spte
.spte_low
= orig
->spte_low
;
410 spte
.spte_high
= orig
->spte_high
;
413 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
414 count
!= sp
->clear_spte_count
))
421 static bool spte_has_volatile_bits(u64 spte
)
423 if (!is_shadow_present_pte(spte
))
427 * Always atomically update spte if it can be updated
428 * out of mmu-lock, it can ensure dirty bit is not lost,
429 * also, it can help us to get a stable is_writable_pte()
430 * to ensure tlb flush is not missed.
432 if (spte_can_locklessly_be_made_writable(spte
) ||
433 is_access_track_spte(spte
))
436 if (spte_ad_enabled(spte
)) {
437 if ((spte
& shadow_accessed_mask
) == 0 ||
438 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
445 /* Rules for using mmu_spte_set:
446 * Set the sptep from nonpresent to present.
447 * Note: the sptep being assigned *must* be either not present
448 * or in a state where the hardware will not attempt to update
451 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
453 WARN_ON(is_shadow_present_pte(*sptep
));
454 __set_spte(sptep
, new_spte
);
458 * Update the SPTE (excluding the PFN), but do not track changes in its
459 * accessed/dirty status.
461 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
463 u64 old_spte
= *sptep
;
465 WARN_ON(!is_shadow_present_pte(new_spte
));
467 if (!is_shadow_present_pte(old_spte
)) {
468 mmu_spte_set(sptep
, new_spte
);
472 if (!spte_has_volatile_bits(old_spte
))
473 __update_clear_spte_fast(sptep
, new_spte
);
475 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
477 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
482 /* Rules for using mmu_spte_update:
483 * Update the state bits, it means the mapped pfn is not changed.
485 * Whenever we overwrite a writable spte with a read-only one we
486 * should flush remote TLBs. Otherwise rmap_write_protect
487 * will find a read-only spte, even though the writable spte
488 * might be cached on a CPU's TLB, the return value indicates this
491 * Returns true if the TLB needs to be flushed
493 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
496 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
498 if (!is_shadow_present_pte(old_spte
))
502 * For the spte updated out of mmu-lock is safe, since
503 * we always atomically update it, see the comments in
504 * spte_has_volatile_bits().
506 if (spte_can_locklessly_be_made_writable(old_spte
) &&
507 !is_writable_pte(new_spte
))
511 * Flush TLB when accessed/dirty states are changed in the page tables,
512 * to guarantee consistency between TLB and page tables.
515 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
517 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
520 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
522 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
529 * Rules for using mmu_spte_clear_track_bits:
530 * It sets the sptep from present to nonpresent, and track the
531 * state bits, it is used to clear the last level sptep.
532 * Returns non-zero if the PTE was previously valid.
534 static int mmu_spte_clear_track_bits(u64
*sptep
)
537 u64 old_spte
= *sptep
;
539 if (!spte_has_volatile_bits(old_spte
))
540 __update_clear_spte_fast(sptep
, 0ull);
542 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
544 if (!is_shadow_present_pte(old_spte
))
547 pfn
= spte_to_pfn(old_spte
);
550 * KVM does not hold the refcount of the page used by
551 * kvm mmu, before reclaiming the page, we should
552 * unmap it from mmu first.
554 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
556 if (is_accessed_spte(old_spte
))
557 kvm_set_pfn_accessed(pfn
);
559 if (is_dirty_spte(old_spte
))
560 kvm_set_pfn_dirty(pfn
);
566 * Rules for using mmu_spte_clear_no_track:
567 * Directly clear spte without caring the state bits of sptep,
568 * it is used to set the upper level spte.
570 static void mmu_spte_clear_no_track(u64
*sptep
)
572 __update_clear_spte_fast(sptep
, 0ull);
575 static u64
mmu_spte_get_lockless(u64
*sptep
)
577 return __get_spte_lockless(sptep
);
580 /* Restore an acc-track PTE back to a regular PTE */
581 static u64
restore_acc_track_spte(u64 spte
)
584 u64 saved_bits
= (spte
>> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
)
585 & SHADOW_ACC_TRACK_SAVED_BITS_MASK
;
587 WARN_ON_ONCE(spte_ad_enabled(spte
));
588 WARN_ON_ONCE(!is_access_track_spte(spte
));
590 new_spte
&= ~shadow_acc_track_mask
;
591 new_spte
&= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK
<<
592 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
);
593 new_spte
|= saved_bits
;
598 /* Returns the Accessed status of the PTE and resets it at the same time. */
599 static bool mmu_spte_age(u64
*sptep
)
601 u64 spte
= mmu_spte_get_lockless(sptep
);
603 if (!is_accessed_spte(spte
))
606 if (spte_ad_enabled(spte
)) {
607 clear_bit((ffs(shadow_accessed_mask
) - 1),
608 (unsigned long *)sptep
);
611 * Capture the dirty status of the page, so that it doesn't get
612 * lost when the SPTE is marked for access tracking.
614 if (is_writable_pte(spte
))
615 kvm_set_pfn_dirty(spte_to_pfn(spte
));
617 spte
= mark_spte_for_access_track(spte
);
618 mmu_spte_update_no_track(sptep
, spte
);
624 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
627 * Prevent page table teardown by making any free-er wait during
628 * kvm_flush_remote_tlbs() IPI to all active vcpus.
633 * Make sure a following spte read is not reordered ahead of the write
636 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
639 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
642 * Make sure the write to vcpu->mode is not reordered in front of
643 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
644 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
646 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
650 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
, bool maybe_indirect
)
654 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
655 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
656 1 + PT64_ROOT_MAX_LEVEL
+ PTE_PREFETCH_NUM
);
659 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
,
660 PT64_ROOT_MAX_LEVEL
);
663 if (maybe_indirect
) {
664 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
,
665 PT64_ROOT_MAX_LEVEL
);
669 return kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
670 PT64_ROOT_MAX_LEVEL
);
673 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
675 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
);
676 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
);
677 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
);
678 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
);
681 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
683 return kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
686 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
688 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
691 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
693 if (!sp
->role
.direct
)
694 return sp
->gfns
[index
];
696 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
699 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
701 if (!sp
->role
.direct
) {
702 sp
->gfns
[index
] = gfn
;
706 if (WARN_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
)))
707 pr_err_ratelimited("gfn mismatch under direct page %llx "
708 "(expected %llx, got %llx)\n",
710 kvm_mmu_page_get_gfn(sp
, index
), gfn
);
714 * Return the pointer to the large page information for a given gfn,
715 * handling slots that are not large page aligned.
717 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
718 struct kvm_memory_slot
*slot
,
723 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
724 return &slot
->arch
.lpage_info
[level
- 2][idx
];
727 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
728 gfn_t gfn
, int count
)
730 struct kvm_lpage_info
*linfo
;
733 for (i
= PG_LEVEL_2M
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
734 linfo
= lpage_info_slot(gfn
, slot
, i
);
735 linfo
->disallow_lpage
+= count
;
736 WARN_ON(linfo
->disallow_lpage
< 0);
740 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
742 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
745 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
747 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
750 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
752 struct kvm_memslots
*slots
;
753 struct kvm_memory_slot
*slot
;
756 kvm
->arch
.indirect_shadow_pages
++;
758 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
759 slot
= __gfn_to_memslot(slots
, gfn
);
761 /* the non-leaf shadow pages are keeping readonly. */
762 if (sp
->role
.level
> PG_LEVEL_4K
)
763 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
764 KVM_PAGE_TRACK_WRITE
);
766 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
769 void account_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
771 if (sp
->lpage_disallowed
)
774 ++kvm
->stat
.nx_lpage_splits
;
775 list_add_tail(&sp
->lpage_disallowed_link
,
776 &kvm
->arch
.lpage_disallowed_mmu_pages
);
777 sp
->lpage_disallowed
= true;
780 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
782 struct kvm_memslots
*slots
;
783 struct kvm_memory_slot
*slot
;
786 kvm
->arch
.indirect_shadow_pages
--;
788 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
789 slot
= __gfn_to_memslot(slots
, gfn
);
790 if (sp
->role
.level
> PG_LEVEL_4K
)
791 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
792 KVM_PAGE_TRACK_WRITE
);
794 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
797 void unaccount_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
799 --kvm
->stat
.nx_lpage_splits
;
800 sp
->lpage_disallowed
= false;
801 list_del(&sp
->lpage_disallowed_link
);
804 static struct kvm_memory_slot
*
805 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
808 struct kvm_memory_slot
*slot
;
810 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
811 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
813 if (no_dirty_log
&& kvm_slot_dirty_track_enabled(slot
))
820 * About rmap_head encoding:
822 * If the bit zero of rmap_head->val is clear, then it points to the only spte
823 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
824 * pte_list_desc containing more mappings.
828 * Returns the number of pointers in the rmap chain, not counting the new one.
830 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
831 struct kvm_rmap_head
*rmap_head
)
833 struct pte_list_desc
*desc
;
836 if (!rmap_head
->val
) {
837 rmap_printk("%p %llx 0->1\n", spte
, *spte
);
838 rmap_head
->val
= (unsigned long)spte
;
839 } else if (!(rmap_head
->val
& 1)) {
840 rmap_printk("%p %llx 1->many\n", spte
, *spte
);
841 desc
= mmu_alloc_pte_list_desc(vcpu
);
842 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
843 desc
->sptes
[1] = spte
;
844 rmap_head
->val
= (unsigned long)desc
| 1;
847 rmap_printk("%p %llx many->many\n", spte
, *spte
);
848 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
849 while (desc
->sptes
[PTE_LIST_EXT
-1]) {
850 count
+= PTE_LIST_EXT
;
853 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
859 for (i
= 0; desc
->sptes
[i
]; ++i
)
861 desc
->sptes
[i
] = spte
;
867 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
868 struct pte_list_desc
*desc
, int i
,
869 struct pte_list_desc
*prev_desc
)
873 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
875 desc
->sptes
[i
] = desc
->sptes
[j
];
876 desc
->sptes
[j
] = NULL
;
879 if (!prev_desc
&& !desc
->more
)
883 prev_desc
->more
= desc
->more
;
885 rmap_head
->val
= (unsigned long)desc
->more
| 1;
886 mmu_free_pte_list_desc(desc
);
889 static void __pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
891 struct pte_list_desc
*desc
;
892 struct pte_list_desc
*prev_desc
;
895 if (!rmap_head
->val
) {
896 pr_err("%s: %p 0->BUG\n", __func__
, spte
);
898 } else if (!(rmap_head
->val
& 1)) {
899 rmap_printk("%p 1->0\n", spte
);
900 if ((u64
*)rmap_head
->val
!= spte
) {
901 pr_err("%s: %p 1->BUG\n", __func__
, spte
);
906 rmap_printk("%p many->many\n", spte
);
907 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
910 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
911 if (desc
->sptes
[i
] == spte
) {
912 pte_list_desc_remove_entry(rmap_head
,
920 pr_err("%s: %p many->many\n", __func__
, spte
);
925 static void pte_list_remove(struct kvm_rmap_head
*rmap_head
, u64
*sptep
)
927 mmu_spte_clear_track_bits(sptep
);
928 __pte_list_remove(sptep
, rmap_head
);
931 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
932 struct kvm_memory_slot
*slot
)
936 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
937 return &slot
->arch
.rmap
[level
- PG_LEVEL_4K
][idx
];
940 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
941 struct kvm_mmu_page
*sp
)
943 struct kvm_memslots
*slots
;
944 struct kvm_memory_slot
*slot
;
946 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
947 slot
= __gfn_to_memslot(slots
, gfn
);
948 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
951 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
953 struct kvm_mmu_memory_cache
*mc
;
955 mc
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
956 return kvm_mmu_memory_cache_nr_free_objects(mc
);
959 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
961 struct kvm_mmu_page
*sp
;
962 struct kvm_rmap_head
*rmap_head
;
964 sp
= sptep_to_sp(spte
);
965 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
966 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
967 return pte_list_add(vcpu
, spte
, rmap_head
);
970 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
972 struct kvm_mmu_page
*sp
;
974 struct kvm_rmap_head
*rmap_head
;
976 sp
= sptep_to_sp(spte
);
977 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
978 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
979 __pte_list_remove(spte
, rmap_head
);
983 * Used by the following functions to iterate through the sptes linked by a
984 * rmap. All fields are private and not assumed to be used outside.
986 struct rmap_iterator
{
988 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
989 int pos
; /* index of the sptep */
993 * Iteration must be started by this function. This should also be used after
994 * removing/dropping sptes from the rmap link because in such cases the
995 * information in the iterator may not be valid.
997 * Returns sptep if found, NULL otherwise.
999 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1000 struct rmap_iterator
*iter
)
1004 if (!rmap_head
->val
)
1007 if (!(rmap_head
->val
& 1)) {
1009 sptep
= (u64
*)rmap_head
->val
;
1013 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1015 sptep
= iter
->desc
->sptes
[iter
->pos
];
1017 BUG_ON(!is_shadow_present_pte(*sptep
));
1022 * Must be used with a valid iterator: e.g. after rmap_get_first().
1024 * Returns sptep if found, NULL otherwise.
1026 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1031 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1033 sptep
= iter
->desc
->sptes
[iter
->pos
];
1038 iter
->desc
= iter
->desc
->more
;
1042 /* desc->sptes[0] cannot be NULL */
1043 sptep
= iter
->desc
->sptes
[iter
->pos
];
1050 BUG_ON(!is_shadow_present_pte(*sptep
));
1054 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1055 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1056 _spte_; _spte_ = rmap_get_next(_iter_))
1058 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1060 if (mmu_spte_clear_track_bits(sptep
))
1061 rmap_remove(kvm
, sptep
);
1065 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1067 if (is_large_pte(*sptep
)) {
1068 WARN_ON(sptep_to_sp(sptep
)->role
.level
== PG_LEVEL_4K
);
1069 drop_spte(kvm
, sptep
);
1077 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1079 if (__drop_large_spte(vcpu
->kvm
, sptep
)) {
1080 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
1082 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1083 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1088 * Write-protect on the specified @sptep, @pt_protect indicates whether
1089 * spte write-protection is caused by protecting shadow page table.
1091 * Note: write protection is difference between dirty logging and spte
1093 * - for dirty logging, the spte can be set to writable at anytime if
1094 * its dirty bitmap is properly set.
1095 * - for spte protection, the spte can be writable only after unsync-ing
1098 * Return true if tlb need be flushed.
1100 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1104 if (!is_writable_pte(spte
) &&
1105 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1108 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1111 spte
&= ~shadow_mmu_writable_mask
;
1112 spte
= spte
& ~PT_WRITABLE_MASK
;
1114 return mmu_spte_update(sptep
, spte
);
1117 static bool __rmap_write_protect(struct kvm
*kvm
,
1118 struct kvm_rmap_head
*rmap_head
,
1122 struct rmap_iterator iter
;
1125 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1126 flush
|= spte_write_protect(sptep
, pt_protect
);
1131 static bool spte_clear_dirty(u64
*sptep
)
1135 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1137 MMU_WARN_ON(!spte_ad_enabled(spte
));
1138 spte
&= ~shadow_dirty_mask
;
1139 return mmu_spte_update(sptep
, spte
);
1142 static bool spte_wrprot_for_clear_dirty(u64
*sptep
)
1144 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1145 (unsigned long *)sptep
);
1146 if (was_writable
&& !spte_ad_enabled(*sptep
))
1147 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1149 return was_writable
;
1153 * Gets the GFN ready for another round of dirty logging by clearing the
1154 * - D bit on ad-enabled SPTEs, and
1155 * - W bit on ad-disabled SPTEs.
1156 * Returns true iff any D or W bits were cleared.
1158 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1159 struct kvm_memory_slot
*slot
)
1162 struct rmap_iterator iter
;
1165 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1166 if (spte_ad_need_write_protect(*sptep
))
1167 flush
|= spte_wrprot_for_clear_dirty(sptep
);
1169 flush
|= spte_clear_dirty(sptep
);
1175 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1176 * @kvm: kvm instance
1177 * @slot: slot to protect
1178 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1179 * @mask: indicates which pages we should protect
1181 * Used when we do not need to care about huge page mappings: e.g. during dirty
1182 * logging we do not have any such mappings.
1184 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1185 struct kvm_memory_slot
*slot
,
1186 gfn_t gfn_offset
, unsigned long mask
)
1188 struct kvm_rmap_head
*rmap_head
;
1190 if (is_tdp_mmu_enabled(kvm
))
1191 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1192 slot
->base_gfn
+ gfn_offset
, mask
, true);
1194 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1196 __rmap_write_protect(kvm
, rmap_head
, false);
1198 /* clear the first set bit */
1204 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1205 * protect the page if the D-bit isn't supported.
1206 * @kvm: kvm instance
1207 * @slot: slot to clear D-bit
1208 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1209 * @mask: indicates which pages we should clear D-bit
1211 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1213 static void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1214 struct kvm_memory_slot
*slot
,
1215 gfn_t gfn_offset
, unsigned long mask
)
1217 struct kvm_rmap_head
*rmap_head
;
1219 if (is_tdp_mmu_enabled(kvm
))
1220 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1221 slot
->base_gfn
+ gfn_offset
, mask
, false);
1223 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1225 __rmap_clear_dirty(kvm
, rmap_head
, slot
);
1227 /* clear the first set bit */
1233 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1236 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1237 * enable dirty logging for them.
1239 * Used when we do not need to care about huge page mappings: e.g. during dirty
1240 * logging we do not have any such mappings.
1242 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1243 struct kvm_memory_slot
*slot
,
1244 gfn_t gfn_offset
, unsigned long mask
)
1246 if (kvm_x86_ops
.cpu_dirty_log_size
)
1247 kvm_mmu_clear_dirty_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1249 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1252 int kvm_cpu_dirty_log_size(void)
1254 return kvm_x86_ops
.cpu_dirty_log_size
;
1257 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1258 struct kvm_memory_slot
*slot
, u64 gfn
)
1260 struct kvm_rmap_head
*rmap_head
;
1262 bool write_protected
= false;
1264 for (i
= PG_LEVEL_4K
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
1265 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1266 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1269 if (is_tdp_mmu_enabled(kvm
))
1271 kvm_tdp_mmu_write_protect_gfn(kvm
, slot
, gfn
);
1273 return write_protected
;
1276 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1278 struct kvm_memory_slot
*slot
;
1280 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1281 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1284 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1285 struct kvm_memory_slot
*slot
)
1288 struct rmap_iterator iter
;
1291 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1292 rmap_printk("spte %p %llx.\n", sptep
, *sptep
);
1294 pte_list_remove(rmap_head
, sptep
);
1301 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1302 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1305 return kvm_zap_rmapp(kvm
, rmap_head
, slot
);
1308 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1309 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1313 struct rmap_iterator iter
;
1316 pte_t
*ptep
= (pte_t
*)data
;
1319 WARN_ON(pte_huge(*ptep
));
1320 new_pfn
= pte_pfn(*ptep
);
1323 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1324 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1325 sptep
, *sptep
, gfn
, level
);
1329 if (pte_write(*ptep
)) {
1330 pte_list_remove(rmap_head
, sptep
);
1333 new_spte
= kvm_mmu_changed_pte_notifier_make_spte(
1336 mmu_spte_clear_track_bits(sptep
);
1337 mmu_spte_set(sptep
, new_spte
);
1341 if (need_flush
&& kvm_available_flush_tlb_with_range()) {
1342 kvm_flush_remote_tlbs_with_address(kvm
, gfn
, 1);
1349 struct slot_rmap_walk_iterator
{
1351 struct kvm_memory_slot
*slot
;
1357 /* output fields. */
1359 struct kvm_rmap_head
*rmap
;
1362 /* private field. */
1363 struct kvm_rmap_head
*end_rmap
;
1367 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1369 iterator
->level
= level
;
1370 iterator
->gfn
= iterator
->start_gfn
;
1371 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1372 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1377 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1378 struct kvm_memory_slot
*slot
, int start_level
,
1379 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1381 iterator
->slot
= slot
;
1382 iterator
->start_level
= start_level
;
1383 iterator
->end_level
= end_level
;
1384 iterator
->start_gfn
= start_gfn
;
1385 iterator
->end_gfn
= end_gfn
;
1387 rmap_walk_init_level(iterator
, iterator
->start_level
);
1390 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1392 return !!iterator
->rmap
;
1395 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1397 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1398 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1402 if (++iterator
->level
> iterator
->end_level
) {
1403 iterator
->rmap
= NULL
;
1407 rmap_walk_init_level(iterator
, iterator
->level
);
1410 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1411 _start_gfn, _end_gfn, _iter_) \
1412 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1413 _end_level_, _start_gfn, _end_gfn); \
1414 slot_rmap_walk_okay(_iter_); \
1415 slot_rmap_walk_next(_iter_))
1417 typedef int (*rmap_handler_t
)(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1418 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1419 int level
, unsigned long data
);
1421 static __always_inline
int kvm_handle_hva_range(struct kvm
*kvm
,
1422 unsigned long start
,
1425 rmap_handler_t handler
)
1427 struct kvm_memslots
*slots
;
1428 struct kvm_memory_slot
*memslot
;
1429 struct slot_rmap_walk_iterator iterator
;
1433 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1434 slots
= __kvm_memslots(kvm
, i
);
1435 kvm_for_each_memslot(memslot
, slots
) {
1436 unsigned long hva_start
, hva_end
;
1437 gfn_t gfn_start
, gfn_end
;
1439 hva_start
= max(start
, memslot
->userspace_addr
);
1440 hva_end
= min(end
, memslot
->userspace_addr
+
1441 (memslot
->npages
<< PAGE_SHIFT
));
1442 if (hva_start
>= hva_end
)
1445 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1446 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1448 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1449 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1451 for_each_slot_rmap_range(memslot
, PG_LEVEL_4K
,
1452 KVM_MAX_HUGEPAGE_LEVEL
,
1453 gfn_start
, gfn_end
- 1,
1455 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1456 iterator
.gfn
, iterator
.level
, data
);
1463 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1464 unsigned long data
, rmap_handler_t handler
)
1466 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1469 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
,
1474 r
= kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1476 if (is_tdp_mmu_enabled(kvm
))
1477 r
|= kvm_tdp_mmu_zap_hva_range(kvm
, start
, end
);
1482 int kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1486 r
= kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1488 if (is_tdp_mmu_enabled(kvm
))
1489 r
|= kvm_tdp_mmu_set_spte_hva(kvm
, hva
, &pte
);
1494 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1495 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1499 struct rmap_iterator iter
;
1502 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1503 young
|= mmu_spte_age(sptep
);
1505 trace_kvm_age_page(gfn
, level
, slot
, young
);
1509 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1510 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1511 int level
, unsigned long data
)
1514 struct rmap_iterator iter
;
1516 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1517 if (is_accessed_spte(*sptep
))
1522 #define RMAP_RECYCLE_THRESHOLD 1000
1524 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1526 struct kvm_rmap_head
*rmap_head
;
1527 struct kvm_mmu_page
*sp
;
1529 sp
= sptep_to_sp(spte
);
1531 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1533 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1534 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1535 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1538 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1542 young
= kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1543 if (is_tdp_mmu_enabled(kvm
))
1544 young
|= kvm_tdp_mmu_age_hva_range(kvm
, start
, end
);
1549 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1553 young
= kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1554 if (is_tdp_mmu_enabled(kvm
))
1555 young
|= kvm_tdp_mmu_test_age_hva(kvm
, hva
);
1561 static int is_empty_shadow_page(u64
*spt
)
1566 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1567 if (is_shadow_present_pte(*pos
)) {
1568 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1577 * This value is the sum of all of the kvm instances's
1578 * kvm->arch.n_used_mmu_pages values. We need a global,
1579 * aggregate version in order to make the slab shrinker
1582 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, unsigned long nr
)
1584 kvm
->arch
.n_used_mmu_pages
+= nr
;
1585 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1588 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1590 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1591 hlist_del(&sp
->hash_link
);
1592 list_del(&sp
->link
);
1593 free_page((unsigned long)sp
->spt
);
1594 if (!sp
->role
.direct
)
1595 free_page((unsigned long)sp
->gfns
);
1596 kmem_cache_free(mmu_page_header_cache
, sp
);
1599 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1601 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1604 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1605 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1610 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1613 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1616 __pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1619 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1622 mmu_page_remove_parent_pte(sp
, parent_pte
);
1623 mmu_spte_clear_no_track(parent_pte
);
1626 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1628 struct kvm_mmu_page
*sp
;
1630 sp
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1631 sp
->spt
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_shadow_page_cache
);
1633 sp
->gfns
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_gfn_array_cache
);
1634 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1637 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1638 * depends on valid pages being added to the head of the list. See
1639 * comments in kvm_zap_obsolete_pages().
1641 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
1642 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1643 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1647 static void mark_unsync(u64
*spte
);
1648 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1651 struct rmap_iterator iter
;
1653 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1658 static void mark_unsync(u64
*spte
)
1660 struct kvm_mmu_page
*sp
;
1663 sp
= sptep_to_sp(spte
);
1664 index
= spte
- sp
->spt
;
1665 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1667 if (sp
->unsync_children
++)
1669 kvm_mmu_mark_parents_unsync(sp
);
1672 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1673 struct kvm_mmu_page
*sp
)
1678 #define KVM_PAGE_ARRAY_NR 16
1680 struct kvm_mmu_pages
{
1681 struct mmu_page_and_offset
{
1682 struct kvm_mmu_page
*sp
;
1684 } page
[KVM_PAGE_ARRAY_NR
];
1688 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1694 for (i
=0; i
< pvec
->nr
; i
++)
1695 if (pvec
->page
[i
].sp
== sp
)
1698 pvec
->page
[pvec
->nr
].sp
= sp
;
1699 pvec
->page
[pvec
->nr
].idx
= idx
;
1701 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1704 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1706 --sp
->unsync_children
;
1707 WARN_ON((int)sp
->unsync_children
< 0);
1708 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1711 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1712 struct kvm_mmu_pages
*pvec
)
1714 int i
, ret
, nr_unsync_leaf
= 0;
1716 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1717 struct kvm_mmu_page
*child
;
1718 u64 ent
= sp
->spt
[i
];
1720 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1721 clear_unsync_child_bit(sp
, i
);
1725 child
= to_shadow_page(ent
& PT64_BASE_ADDR_MASK
);
1727 if (child
->unsync_children
) {
1728 if (mmu_pages_add(pvec
, child
, i
))
1731 ret
= __mmu_unsync_walk(child
, pvec
);
1733 clear_unsync_child_bit(sp
, i
);
1735 } else if (ret
> 0) {
1736 nr_unsync_leaf
+= ret
;
1739 } else if (child
->unsync
) {
1741 if (mmu_pages_add(pvec
, child
, i
))
1744 clear_unsync_child_bit(sp
, i
);
1747 return nr_unsync_leaf
;
1750 #define INVALID_INDEX (-1)
1752 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1753 struct kvm_mmu_pages
*pvec
)
1756 if (!sp
->unsync_children
)
1759 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1760 return __mmu_unsync_walk(sp
, pvec
);
1763 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1765 WARN_ON(!sp
->unsync
);
1766 trace_kvm_mmu_sync_page(sp
);
1768 --kvm
->stat
.mmu_unsync
;
1771 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1772 struct list_head
*invalid_list
);
1773 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1774 struct list_head
*invalid_list
);
1776 #define for_each_valid_sp(_kvm, _sp, _list) \
1777 hlist_for_each_entry(_sp, _list, hash_link) \
1778 if (is_obsolete_sp((_kvm), (_sp))) { \
1781 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1782 for_each_valid_sp(_kvm, _sp, \
1783 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1784 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1786 static inline bool is_ept_sp(struct kvm_mmu_page
*sp
)
1788 return sp
->role
.cr0_wp
&& sp
->role
.smap_andnot_wp
;
1791 /* @sp->gfn should be write-protected at the call site */
1792 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1793 struct list_head
*invalid_list
)
1795 if ((!is_ept_sp(sp
) && sp
->role
.gpte_is_8_bytes
!= !!is_pae(vcpu
)) ||
1796 vcpu
->arch
.mmu
->sync_page(vcpu
, sp
) == 0) {
1797 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1804 static bool kvm_mmu_remote_flush_or_zap(struct kvm
*kvm
,
1805 struct list_head
*invalid_list
,
1808 if (!remote_flush
&& list_empty(invalid_list
))
1811 if (!list_empty(invalid_list
))
1812 kvm_mmu_commit_zap_page(kvm
, invalid_list
);
1814 kvm_flush_remote_tlbs(kvm
);
1818 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1819 struct list_head
*invalid_list
,
1820 bool remote_flush
, bool local_flush
)
1822 if (kvm_mmu_remote_flush_or_zap(vcpu
->kvm
, invalid_list
, remote_flush
))
1826 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
1829 #ifdef CONFIG_KVM_MMU_AUDIT
1830 #include "mmu_audit.c"
1832 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1833 static void mmu_audit_disable(void) { }
1836 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1838 return sp
->role
.invalid
||
1839 unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1842 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1843 struct list_head
*invalid_list
)
1845 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1846 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
1849 /* @gfn should be write-protected at the call site */
1850 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1851 struct list_head
*invalid_list
)
1853 struct kvm_mmu_page
*s
;
1856 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
1860 WARN_ON(s
->role
.level
!= PG_LEVEL_4K
);
1861 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
1867 struct mmu_page_path
{
1868 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
1869 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
1872 #define for_each_sp(pvec, sp, parents, i) \
1873 for (i = mmu_pages_first(&pvec, &parents); \
1874 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1875 i = mmu_pages_next(&pvec, &parents, i))
1877 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1878 struct mmu_page_path
*parents
,
1883 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1884 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1885 unsigned idx
= pvec
->page
[n
].idx
;
1886 int level
= sp
->role
.level
;
1888 parents
->idx
[level
-1] = idx
;
1889 if (level
== PG_LEVEL_4K
)
1892 parents
->parent
[level
-2] = sp
;
1898 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
1899 struct mmu_page_path
*parents
)
1901 struct kvm_mmu_page
*sp
;
1907 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
1909 sp
= pvec
->page
[0].sp
;
1910 level
= sp
->role
.level
;
1911 WARN_ON(level
== PG_LEVEL_4K
);
1913 parents
->parent
[level
-2] = sp
;
1915 /* Also set up a sentinel. Further entries in pvec are all
1916 * children of sp, so this element is never overwritten.
1918 parents
->parent
[level
-1] = NULL
;
1919 return mmu_pages_next(pvec
, parents
, 0);
1922 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1924 struct kvm_mmu_page
*sp
;
1925 unsigned int level
= 0;
1928 unsigned int idx
= parents
->idx
[level
];
1929 sp
= parents
->parent
[level
];
1933 WARN_ON(idx
== INVALID_INDEX
);
1934 clear_unsync_child_bit(sp
, idx
);
1936 } while (!sp
->unsync_children
);
1939 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1940 struct kvm_mmu_page
*parent
)
1943 struct kvm_mmu_page
*sp
;
1944 struct mmu_page_path parents
;
1945 struct kvm_mmu_pages pages
;
1946 LIST_HEAD(invalid_list
);
1949 while (mmu_unsync_walk(parent
, &pages
)) {
1950 bool protected = false;
1952 for_each_sp(pages
, sp
, parents
, i
)
1953 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
1956 kvm_flush_remote_tlbs(vcpu
->kvm
);
1960 for_each_sp(pages
, sp
, parents
, i
) {
1961 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
1962 mmu_pages_clear_parents(&parents
);
1964 if (need_resched() || rwlock_needbreak(&vcpu
->kvm
->mmu_lock
)) {
1965 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
1966 cond_resched_rwlock_write(&vcpu
->kvm
->mmu_lock
);
1971 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
1974 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1976 atomic_set(&sp
->write_flooding_count
, 0);
1979 static void clear_sp_write_flooding_count(u64
*spte
)
1981 __clear_sp_write_flooding_count(sptep_to_sp(spte
));
1984 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1989 unsigned int access
)
1991 bool direct_mmu
= vcpu
->arch
.mmu
->direct_map
;
1992 union kvm_mmu_page_role role
;
1993 struct hlist_head
*sp_list
;
1995 struct kvm_mmu_page
*sp
;
1996 bool need_sync
= false;
1999 LIST_HEAD(invalid_list
);
2001 role
= vcpu
->arch
.mmu
->mmu_role
.base
;
2003 role
.direct
= direct
;
2005 role
.gpte_is_8_bytes
= true;
2006 role
.access
= access
;
2007 if (!direct_mmu
&& vcpu
->arch
.mmu
->root_level
<= PT32_ROOT_LEVEL
) {
2008 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2009 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2010 role
.quadrant
= quadrant
;
2013 sp_list
= &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)];
2014 for_each_valid_sp(vcpu
->kvm
, sp
, sp_list
) {
2015 if (sp
->gfn
!= gfn
) {
2020 if (!need_sync
&& sp
->unsync
)
2023 if (sp
->role
.word
!= role
.word
)
2027 goto trace_get_page
;
2030 /* The page is good, but __kvm_sync_page might still end
2031 * up zapping it. If so, break in order to rebuild it.
2033 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2036 WARN_ON(!list_empty(&invalid_list
));
2037 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2040 if (sp
->unsync_children
)
2041 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2043 __clear_sp_write_flooding_count(sp
);
2046 trace_kvm_mmu_get_page(sp
, false);
2050 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2052 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2056 hlist_add_head(&sp
->hash_link
, sp_list
);
2059 * we should do write protection before syncing pages
2060 * otherwise the content of the synced shadow page may
2061 * be inconsistent with guest page table.
2063 account_shadowed(vcpu
->kvm
, sp
);
2064 if (level
== PG_LEVEL_4K
&& rmap_write_protect(vcpu
, gfn
))
2065 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
, 1);
2067 if (level
> PG_LEVEL_4K
&& need_sync
)
2068 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2070 trace_kvm_mmu_get_page(sp
, true);
2072 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2074 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2075 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2079 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator
*iterator
,
2080 struct kvm_vcpu
*vcpu
, hpa_t root
,
2083 iterator
->addr
= addr
;
2084 iterator
->shadow_addr
= root
;
2085 iterator
->level
= vcpu
->arch
.mmu
->shadow_root_level
;
2087 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2088 vcpu
->arch
.mmu
->root_level
< PT64_ROOT_4LEVEL
&&
2089 !vcpu
->arch
.mmu
->direct_map
)
2092 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2094 * prev_root is currently only used for 64-bit hosts. So only
2095 * the active root_hpa is valid here.
2097 BUG_ON(root
!= vcpu
->arch
.mmu
->root_hpa
);
2099 iterator
->shadow_addr
2100 = vcpu
->arch
.mmu
->pae_root
[(addr
>> 30) & 3];
2101 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2103 if (!iterator
->shadow_addr
)
2104 iterator
->level
= 0;
2108 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2109 struct kvm_vcpu
*vcpu
, u64 addr
)
2111 shadow_walk_init_using_root(iterator
, vcpu
, vcpu
->arch
.mmu
->root_hpa
,
2115 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2117 if (iterator
->level
< PG_LEVEL_4K
)
2120 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2121 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2125 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2128 if (is_last_spte(spte
, iterator
->level
)) {
2129 iterator
->level
= 0;
2133 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2137 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2139 __shadow_walk_next(iterator
, *iterator
->sptep
);
2142 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2143 struct kvm_mmu_page
*sp
)
2147 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2149 spte
= make_nonleaf_spte(sp
->spt
, sp_ad_disabled(sp
));
2151 mmu_spte_set(sptep
, spte
);
2153 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2155 if (sp
->unsync_children
|| sp
->unsync
)
2159 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2160 unsigned direct_access
)
2162 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2163 struct kvm_mmu_page
*child
;
2166 * For the direct sp, if the guest pte's dirty bit
2167 * changed form clean to dirty, it will corrupt the
2168 * sp's access: allow writable in the read-only sp,
2169 * so we should update the spte at this point to get
2170 * a new sp with the correct access.
2172 child
= to_shadow_page(*sptep
& PT64_BASE_ADDR_MASK
);
2173 if (child
->role
.access
== direct_access
)
2176 drop_parent_pte(child
, sptep
);
2177 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, child
->gfn
, 1);
2181 /* Returns the number of zapped non-leaf child shadow pages. */
2182 static int mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2183 u64
*spte
, struct list_head
*invalid_list
)
2186 struct kvm_mmu_page
*child
;
2189 if (is_shadow_present_pte(pte
)) {
2190 if (is_last_spte(pte
, sp
->role
.level
)) {
2191 drop_spte(kvm
, spte
);
2192 if (is_large_pte(pte
))
2195 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2196 drop_parent_pte(child
, spte
);
2199 * Recursively zap nested TDP SPs, parentless SPs are
2200 * unlikely to be used again in the near future. This
2201 * avoids retaining a large number of stale nested SPs.
2203 if (tdp_enabled
&& invalid_list
&&
2204 child
->role
.guest_mode
&& !child
->parent_ptes
.val
)
2205 return kvm_mmu_prepare_zap_page(kvm
, child
,
2208 } else if (is_mmio_spte(pte
)) {
2209 mmu_spte_clear_no_track(spte
);
2214 static int kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2215 struct kvm_mmu_page
*sp
,
2216 struct list_head
*invalid_list
)
2221 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2222 zapped
+= mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
, invalid_list
);
2227 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2230 struct rmap_iterator iter
;
2232 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2233 drop_parent_pte(sp
, sptep
);
2236 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2237 struct kvm_mmu_page
*parent
,
2238 struct list_head
*invalid_list
)
2241 struct mmu_page_path parents
;
2242 struct kvm_mmu_pages pages
;
2244 if (parent
->role
.level
== PG_LEVEL_4K
)
2247 while (mmu_unsync_walk(parent
, &pages
)) {
2248 struct kvm_mmu_page
*sp
;
2250 for_each_sp(pages
, sp
, parents
, i
) {
2251 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2252 mmu_pages_clear_parents(&parents
);
2260 static bool __kvm_mmu_prepare_zap_page(struct kvm
*kvm
,
2261 struct kvm_mmu_page
*sp
,
2262 struct list_head
*invalid_list
,
2267 trace_kvm_mmu_prepare_zap_page(sp
);
2268 ++kvm
->stat
.mmu_shadow_zapped
;
2269 *nr_zapped
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2270 *nr_zapped
+= kvm_mmu_page_unlink_children(kvm
, sp
, invalid_list
);
2271 kvm_mmu_unlink_parents(kvm
, sp
);
2273 /* Zapping children means active_mmu_pages has become unstable. */
2274 list_unstable
= *nr_zapped
;
2276 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2277 unaccount_shadowed(kvm
, sp
);
2280 kvm_unlink_unsync_page(kvm
, sp
);
2281 if (!sp
->root_count
) {
2286 * Already invalid pages (previously active roots) are not on
2287 * the active page list. See list_del() in the "else" case of
2290 if (sp
->role
.invalid
)
2291 list_add(&sp
->link
, invalid_list
);
2293 list_move(&sp
->link
, invalid_list
);
2294 kvm_mod_used_mmu_pages(kvm
, -1);
2297 * Remove the active root from the active page list, the root
2298 * will be explicitly freed when the root_count hits zero.
2300 list_del(&sp
->link
);
2303 * Obsolete pages cannot be used on any vCPUs, see the comment
2304 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2305 * treats invalid shadow pages as being obsolete.
2307 if (!is_obsolete_sp(kvm
, sp
))
2308 kvm_reload_remote_mmus(kvm
);
2311 if (sp
->lpage_disallowed
)
2312 unaccount_huge_nx_page(kvm
, sp
);
2314 sp
->role
.invalid
= 1;
2315 return list_unstable
;
2318 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2319 struct list_head
*invalid_list
)
2323 __kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
, &nr_zapped
);
2327 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2328 struct list_head
*invalid_list
)
2330 struct kvm_mmu_page
*sp
, *nsp
;
2332 if (list_empty(invalid_list
))
2336 * We need to make sure everyone sees our modifications to
2337 * the page tables and see changes to vcpu->mode here. The barrier
2338 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2339 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2341 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2342 * guest mode and/or lockless shadow page table walks.
2344 kvm_flush_remote_tlbs(kvm
);
2346 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2347 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2348 kvm_mmu_free_page(sp
);
2352 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm
*kvm
,
2353 unsigned long nr_to_zap
)
2355 unsigned long total_zapped
= 0;
2356 struct kvm_mmu_page
*sp
, *tmp
;
2357 LIST_HEAD(invalid_list
);
2361 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2365 list_for_each_entry_safe_reverse(sp
, tmp
, &kvm
->arch
.active_mmu_pages
, link
) {
2367 * Don't zap active root pages, the page itself can't be freed
2368 * and zapping it will just force vCPUs to realloc and reload.
2373 unstable
= __kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
,
2375 total_zapped
+= nr_zapped
;
2376 if (total_zapped
>= nr_to_zap
)
2383 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2385 kvm
->stat
.mmu_recycled
+= total_zapped
;
2386 return total_zapped
;
2389 static inline unsigned long kvm_mmu_available_pages(struct kvm
*kvm
)
2391 if (kvm
->arch
.n_max_mmu_pages
> kvm
->arch
.n_used_mmu_pages
)
2392 return kvm
->arch
.n_max_mmu_pages
-
2393 kvm
->arch
.n_used_mmu_pages
;
2398 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
2400 unsigned long avail
= kvm_mmu_available_pages(vcpu
->kvm
);
2402 if (likely(avail
>= KVM_MIN_FREE_MMU_PAGES
))
2405 kvm_mmu_zap_oldest_mmu_pages(vcpu
->kvm
, KVM_REFILL_PAGES
- avail
);
2408 * Note, this check is intentionally soft, it only guarantees that one
2409 * page is available, while the caller may end up allocating as many as
2410 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2411 * exceeding the (arbitrary by default) limit will not harm the host,
2412 * being too agressive may unnecessarily kill the guest, and getting an
2413 * exact count is far more trouble than it's worth, especially in the
2416 if (!kvm_mmu_available_pages(vcpu
->kvm
))
2422 * Changing the number of mmu pages allocated to the vm
2423 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2425 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned long goal_nr_mmu_pages
)
2427 write_lock(&kvm
->mmu_lock
);
2429 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2430 kvm_mmu_zap_oldest_mmu_pages(kvm
, kvm
->arch
.n_used_mmu_pages
-
2433 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2436 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2438 write_unlock(&kvm
->mmu_lock
);
2441 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2443 struct kvm_mmu_page
*sp
;
2444 LIST_HEAD(invalid_list
);
2447 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2449 write_lock(&kvm
->mmu_lock
);
2450 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2451 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2454 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2456 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2457 write_unlock(&kvm
->mmu_lock
);
2462 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
2467 if (vcpu
->arch
.mmu
->direct_map
)
2470 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
2472 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
2477 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2479 trace_kvm_mmu_unsync_page(sp
);
2480 ++vcpu
->kvm
->stat
.mmu_unsync
;
2483 kvm_mmu_mark_parents_unsync(sp
);
2486 bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2489 struct kvm_mmu_page
*sp
;
2491 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2494 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2501 WARN_ON(sp
->role
.level
!= PG_LEVEL_4K
);
2502 kvm_unsync_page(vcpu
, sp
);
2506 * We need to ensure that the marking of unsync pages is visible
2507 * before the SPTE is updated to allow writes because
2508 * kvm_mmu_sync_roots() checks the unsync flags without holding
2509 * the MMU lock and so can race with this. If the SPTE was updated
2510 * before the page had been marked as unsync-ed, something like the
2511 * following could happen:
2514 * ---------------------------------------------------------------------
2515 * 1.2 Host updates SPTE
2517 * 2.1 Guest writes a GPTE for GVA X.
2518 * (GPTE being in the guest page table shadowed
2519 * by the SP from CPU 1.)
2520 * This reads SPTE during the page table walk.
2521 * Since SPTE.W is read as 1, there is no
2524 * 2.2 Guest issues TLB flush.
2525 * That causes a VM Exit.
2527 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2528 * Since it is false, so it just returns.
2530 * 2.4 Guest accesses GVA X.
2531 * Since the mapping in the SP was not updated,
2532 * so the old mapping for GVA X incorrectly
2536 * (sp->unsync = true)
2538 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2539 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2540 * pairs with this write barrier.
2547 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2548 unsigned int pte_access
, int level
,
2549 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2550 bool can_unsync
, bool host_writable
)
2553 struct kvm_mmu_page
*sp
;
2556 sp
= sptep_to_sp(sptep
);
2558 ret
= make_spte(vcpu
, pte_access
, level
, gfn
, pfn
, *sptep
, speculative
,
2559 can_unsync
, host_writable
, sp_ad_disabled(sp
), &spte
);
2561 if (spte
& PT_WRITABLE_MASK
)
2562 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2565 ret
|= SET_SPTE_SPURIOUS
;
2566 else if (mmu_spte_update(sptep
, spte
))
2567 ret
|= SET_SPTE_NEED_REMOTE_TLB_FLUSH
;
2571 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2572 unsigned int pte_access
, bool write_fault
, int level
,
2573 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2576 int was_rmapped
= 0;
2579 int ret
= RET_PF_FIXED
;
2582 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2583 *sptep
, write_fault
, gfn
);
2585 if (unlikely(is_noslot_pfn(pfn
))) {
2586 mark_mmio_spte(vcpu
, sptep
, gfn
, pte_access
);
2587 return RET_PF_EMULATE
;
2590 if (is_shadow_present_pte(*sptep
)) {
2592 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2593 * the parent of the now unreachable PTE.
2595 if (level
> PG_LEVEL_4K
&& !is_large_pte(*sptep
)) {
2596 struct kvm_mmu_page
*child
;
2599 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2600 drop_parent_pte(child
, sptep
);
2602 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2603 pgprintk("hfn old %llx new %llx\n",
2604 spte_to_pfn(*sptep
), pfn
);
2605 drop_spte(vcpu
->kvm
, sptep
);
2611 set_spte_ret
= set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
,
2612 speculative
, true, host_writable
);
2613 if (set_spte_ret
& SET_SPTE_WRITE_PROTECTED_PT
) {
2615 ret
= RET_PF_EMULATE
;
2616 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2619 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
|| flush
)
2620 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
,
2621 KVM_PAGES_PER_HPAGE(level
));
2624 * The fault is fully spurious if and only if the new SPTE and old SPTE
2625 * are identical, and emulation is not required.
2627 if ((set_spte_ret
& SET_SPTE_SPURIOUS
) && ret
== RET_PF_FIXED
) {
2628 WARN_ON_ONCE(!was_rmapped
);
2629 return RET_PF_SPURIOUS
;
2632 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2633 trace_kvm_mmu_set_spte(level
, gfn
, sptep
);
2634 if (!was_rmapped
&& is_large_pte(*sptep
))
2635 ++vcpu
->kvm
->stat
.lpages
;
2637 if (is_shadow_present_pte(*sptep
)) {
2639 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2640 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2641 rmap_recycle(vcpu
, sptep
, gfn
);
2648 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2651 struct kvm_memory_slot
*slot
;
2653 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2655 return KVM_PFN_ERR_FAULT
;
2657 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2660 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2661 struct kvm_mmu_page
*sp
,
2662 u64
*start
, u64
*end
)
2664 struct page
*pages
[PTE_PREFETCH_NUM
];
2665 struct kvm_memory_slot
*slot
;
2666 unsigned int access
= sp
->role
.access
;
2670 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2671 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2675 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2679 for (i
= 0; i
< ret
; i
++, gfn
++, start
++) {
2680 mmu_set_spte(vcpu
, start
, access
, false, sp
->role
.level
, gfn
,
2681 page_to_pfn(pages
[i
]), true, true);
2688 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2689 struct kvm_mmu_page
*sp
, u64
*sptep
)
2691 u64
*spte
, *start
= NULL
;
2694 WARN_ON(!sp
->role
.direct
);
2696 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2699 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2700 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2703 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2711 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2713 struct kvm_mmu_page
*sp
;
2715 sp
= sptep_to_sp(sptep
);
2718 * Without accessed bits, there's no way to distinguish between
2719 * actually accessed translations and prefetched, so disable pte
2720 * prefetch if accessed bits aren't available.
2722 if (sp_ad_disabled(sp
))
2725 if (sp
->role
.level
> PG_LEVEL_4K
)
2729 * If addresses are being invalidated, skip prefetching to avoid
2730 * accidentally prefetching those addresses.
2732 if (unlikely(vcpu
->kvm
->mmu_notifier_count
))
2735 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2738 static int host_pfn_mapping_level(struct kvm
*kvm
, gfn_t gfn
, kvm_pfn_t pfn
,
2739 struct kvm_memory_slot
*slot
)
2745 if (!PageCompound(pfn_to_page(pfn
)) && !kvm_is_zone_device_pfn(pfn
))
2749 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2750 * is not solely for performance, it's also necessary to avoid the
2751 * "writable" check in __gfn_to_hva_many(), which will always fail on
2752 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2753 * page fault steps have already verified the guest isn't writing a
2754 * read-only memslot.
2756 hva
= __gfn_to_hva_memslot(slot
, gfn
);
2758 pte
= lookup_address_in_mm(kvm
->mm
, hva
, &level
);
2765 int kvm_mmu_max_mapping_level(struct kvm
*kvm
, struct kvm_memory_slot
*slot
,
2766 gfn_t gfn
, kvm_pfn_t pfn
, int max_level
)
2768 struct kvm_lpage_info
*linfo
;
2770 max_level
= min(max_level
, max_huge_page_level
);
2771 for ( ; max_level
> PG_LEVEL_4K
; max_level
--) {
2772 linfo
= lpage_info_slot(gfn
, slot
, max_level
);
2773 if (!linfo
->disallow_lpage
)
2777 if (max_level
== PG_LEVEL_4K
)
2780 return host_pfn_mapping_level(kvm
, gfn
, pfn
, slot
);
2783 int kvm_mmu_hugepage_adjust(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2784 int max_level
, kvm_pfn_t
*pfnp
,
2785 bool huge_page_disallowed
, int *req_level
)
2787 struct kvm_memory_slot
*slot
;
2788 kvm_pfn_t pfn
= *pfnp
;
2792 *req_level
= PG_LEVEL_4K
;
2794 if (unlikely(max_level
== PG_LEVEL_4K
))
2797 if (is_error_noslot_pfn(pfn
) || kvm_is_reserved_pfn(pfn
))
2800 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, true);
2804 level
= kvm_mmu_max_mapping_level(vcpu
->kvm
, slot
, gfn
, pfn
, max_level
);
2805 if (level
== PG_LEVEL_4K
)
2808 *req_level
= level
= min(level
, max_level
);
2811 * Enforce the iTLB multihit workaround after capturing the requested
2812 * level, which will be used to do precise, accurate accounting.
2814 if (huge_page_disallowed
)
2818 * mmu_notifier_retry() was successful and mmu_lock is held, so
2819 * the pmd can't be split from under us.
2821 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2822 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2823 *pfnp
= pfn
& ~mask
;
2828 void disallowed_hugepage_adjust(u64 spte
, gfn_t gfn
, int cur_level
,
2829 kvm_pfn_t
*pfnp
, int *goal_levelp
)
2831 int level
= *goal_levelp
;
2833 if (cur_level
== level
&& level
> PG_LEVEL_4K
&&
2834 is_shadow_present_pte(spte
) &&
2835 !is_large_pte(spte
)) {
2837 * A small SPTE exists for this pfn, but FNAME(fetch)
2838 * and __direct_map would like to create a large PTE
2839 * instead: just force them to go down another level,
2840 * patching back for them into pfn the next 9 bits of
2843 u64 page_mask
= KVM_PAGES_PER_HPAGE(level
) -
2844 KVM_PAGES_PER_HPAGE(level
- 1);
2845 *pfnp
|= gfn
& page_mask
;
2850 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
2851 int map_writable
, int max_level
, kvm_pfn_t pfn
,
2852 bool prefault
, bool is_tdp
)
2854 bool nx_huge_page_workaround_enabled
= is_nx_huge_page_enabled();
2855 bool write
= error_code
& PFERR_WRITE_MASK
;
2856 bool exec
= error_code
& PFERR_FETCH_MASK
;
2857 bool huge_page_disallowed
= exec
&& nx_huge_page_workaround_enabled
;
2858 struct kvm_shadow_walk_iterator it
;
2859 struct kvm_mmu_page
*sp
;
2860 int level
, req_level
, ret
;
2861 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
2862 gfn_t base_gfn
= gfn
;
2864 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
2865 return RET_PF_RETRY
;
2867 level
= kvm_mmu_hugepage_adjust(vcpu
, gfn
, max_level
, &pfn
,
2868 huge_page_disallowed
, &req_level
);
2870 trace_kvm_mmu_spte_requested(gpa
, level
, pfn
);
2871 for_each_shadow_entry(vcpu
, gpa
, it
) {
2873 * We cannot overwrite existing page tables with an NX
2874 * large page, as the leaf could be executable.
2876 if (nx_huge_page_workaround_enabled
)
2877 disallowed_hugepage_adjust(*it
.sptep
, gfn
, it
.level
,
2880 base_gfn
= gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
2881 if (it
.level
== level
)
2884 drop_large_spte(vcpu
, it
.sptep
);
2885 if (!is_shadow_present_pte(*it
.sptep
)) {
2886 sp
= kvm_mmu_get_page(vcpu
, base_gfn
, it
.addr
,
2887 it
.level
- 1, true, ACC_ALL
);
2889 link_shadow_page(vcpu
, it
.sptep
, sp
);
2890 if (is_tdp
&& huge_page_disallowed
&&
2891 req_level
>= it
.level
)
2892 account_huge_nx_page(vcpu
->kvm
, sp
);
2896 ret
= mmu_set_spte(vcpu
, it
.sptep
, ACC_ALL
,
2897 write
, level
, base_gfn
, pfn
, prefault
,
2899 if (ret
== RET_PF_SPURIOUS
)
2902 direct_pte_prefetch(vcpu
, it
.sptep
);
2903 ++vcpu
->stat
.pf_fixed
;
2907 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2909 send_sig_mceerr(BUS_MCEERR_AR
, (void __user
*)address
, PAGE_SHIFT
, tsk
);
2912 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2915 * Do not cache the mmio info caused by writing the readonly gfn
2916 * into the spte otherwise read access on readonly gfn also can
2917 * caused mmio page fault and treat it as mmio access.
2919 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2920 return RET_PF_EMULATE
;
2922 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2923 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
2924 return RET_PF_RETRY
;
2930 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2931 kvm_pfn_t pfn
, unsigned int access
,
2934 /* The pfn is invalid, report the error! */
2935 if (unlikely(is_error_pfn(pfn
))) {
2936 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2940 if (unlikely(is_noslot_pfn(pfn
))) {
2941 vcpu_cache_mmio_info(vcpu
, gva
, gfn
,
2942 access
& shadow_mmio_access_mask
);
2944 * If MMIO caching is disabled, emulate immediately without
2945 * touching the shadow page tables as attempting to install an
2946 * MMIO SPTE will just be an expensive nop.
2948 if (unlikely(!shadow_mmio_value
)) {
2949 *ret_val
= RET_PF_EMULATE
;
2957 static bool page_fault_can_be_fast(u32 error_code
)
2960 * Do not fix the mmio spte with invalid generation number which
2961 * need to be updated by slow page fault path.
2963 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2966 /* See if the page fault is due to an NX violation */
2967 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
2968 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
2972 * #PF can be fast if:
2973 * 1. The shadow page table entry is not present, which could mean that
2974 * the fault is potentially caused by access tracking (if enabled).
2975 * 2. The shadow page table entry is present and the fault
2976 * is caused by write-protect, that means we just need change the W
2977 * bit of the spte which can be done out of mmu-lock.
2979 * However, if access tracking is disabled we know that a non-present
2980 * page must be a genuine page fault where we have to create a new SPTE.
2981 * So, if access tracking is disabled, we return true only for write
2982 * accesses to a present page.
2985 return shadow_acc_track_mask
!= 0 ||
2986 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
2987 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
2991 * Returns true if the SPTE was fixed successfully. Otherwise,
2992 * someone else modified the SPTE from its original value.
2995 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2996 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3000 WARN_ON(!sp
->role
.direct
);
3003 * Theoretically we could also set dirty bit (and flush TLB) here in
3004 * order to eliminate unnecessary PML logging. See comments in
3005 * set_spte. But fast_page_fault is very unlikely to happen with PML
3006 * enabled, so we do not do this. This might result in the same GPA
3007 * to be logged in PML buffer again when the write really happens, and
3008 * eventually to be called by mark_page_dirty twice. But it's also no
3009 * harm. This also avoids the TLB flush needed after setting dirty bit
3010 * so non-PML cases won't be impacted.
3012 * Compare with set_spte where instead shadow_dirty_mask is set.
3014 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3017 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3019 * The gfn of direct spte is stable since it is
3020 * calculated by sp->gfn.
3022 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3023 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3029 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3031 if (fault_err_code
& PFERR_FETCH_MASK
)
3032 return is_executable_pte(spte
);
3034 if (fault_err_code
& PFERR_WRITE_MASK
)
3035 return is_writable_pte(spte
);
3037 /* Fault was on Read access */
3038 return spte
& PT_PRESENT_MASK
;
3042 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3044 static int fast_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3047 struct kvm_shadow_walk_iterator iterator
;
3048 struct kvm_mmu_page
*sp
;
3049 int ret
= RET_PF_INVALID
;
3051 uint retry_count
= 0;
3053 if (!page_fault_can_be_fast(error_code
))
3056 walk_shadow_page_lockless_begin(vcpu
);
3061 for_each_shadow_entry_lockless(vcpu
, cr2_or_gpa
, iterator
, spte
)
3062 if (!is_shadow_present_pte(spte
))
3065 if (!is_shadow_present_pte(spte
))
3068 sp
= sptep_to_sp(iterator
.sptep
);
3069 if (!is_last_spte(spte
, sp
->role
.level
))
3073 * Check whether the memory access that caused the fault would
3074 * still cause it if it were to be performed right now. If not,
3075 * then this is a spurious fault caused by TLB lazily flushed,
3076 * or some other CPU has already fixed the PTE after the
3077 * current CPU took the fault.
3079 * Need not check the access of upper level table entries since
3080 * they are always ACC_ALL.
3082 if (is_access_allowed(error_code
, spte
)) {
3083 ret
= RET_PF_SPURIOUS
;
3089 if (is_access_track_spte(spte
))
3090 new_spte
= restore_acc_track_spte(new_spte
);
3093 * Currently, to simplify the code, write-protection can
3094 * be removed in the fast path only if the SPTE was
3095 * write-protected for dirty-logging or access tracking.
3097 if ((error_code
& PFERR_WRITE_MASK
) &&
3098 spte_can_locklessly_be_made_writable(spte
)) {
3099 new_spte
|= PT_WRITABLE_MASK
;
3102 * Do not fix write-permission on the large spte. Since
3103 * we only dirty the first page into the dirty-bitmap in
3104 * fast_pf_fix_direct_spte(), other pages are missed
3105 * if its slot has dirty logging enabled.
3107 * Instead, we let the slow page fault path create a
3108 * normal spte to fix the access.
3110 * See the comments in kvm_arch_commit_memory_region().
3112 if (sp
->role
.level
> PG_LEVEL_4K
)
3116 /* Verify that the fault can be handled in the fast path */
3117 if (new_spte
== spte
||
3118 !is_access_allowed(error_code
, new_spte
))
3122 * Currently, fast page fault only works for direct mapping
3123 * since the gfn is not stable for indirect shadow page. See
3124 * Documentation/virt/kvm/locking.rst to get more detail.
3126 if (fast_pf_fix_direct_spte(vcpu
, sp
, iterator
.sptep
, spte
,
3132 if (++retry_count
> 4) {
3133 printk_once(KERN_WARNING
3134 "kvm: Fast #PF retrying more than 4 times.\n");
3140 trace_fast_page_fault(vcpu
, cr2_or_gpa
, error_code
, iterator
.sptep
,
3142 walk_shadow_page_lockless_end(vcpu
);
3147 static void mmu_free_root_page(struct kvm
*kvm
, hpa_t
*root_hpa
,
3148 struct list_head
*invalid_list
)
3150 struct kvm_mmu_page
*sp
;
3152 if (!VALID_PAGE(*root_hpa
))
3155 sp
= to_shadow_page(*root_hpa
& PT64_BASE_ADDR_MASK
);
3157 if (kvm_mmu_put_root(kvm
, sp
)) {
3158 if (is_tdp_mmu_page(sp
))
3159 kvm_tdp_mmu_free_root(kvm
, sp
);
3160 else if (sp
->role
.invalid
)
3161 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
3164 *root_hpa
= INVALID_PAGE
;
3167 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3168 void kvm_mmu_free_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3169 ulong roots_to_free
)
3171 struct kvm
*kvm
= vcpu
->kvm
;
3173 LIST_HEAD(invalid_list
);
3174 bool free_active_root
= roots_to_free
& KVM_MMU_ROOT_CURRENT
;
3176 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS
>= BITS_PER_LONG
);
3178 /* Before acquiring the MMU lock, see if we need to do any real work. */
3179 if (!(free_active_root
&& VALID_PAGE(mmu
->root_hpa
))) {
3180 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3181 if ((roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
)) &&
3182 VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
3185 if (i
== KVM_MMU_NUM_PREV_ROOTS
)
3189 write_lock(&kvm
->mmu_lock
);
3191 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3192 if (roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
))
3193 mmu_free_root_page(kvm
, &mmu
->prev_roots
[i
].hpa
,
3196 if (free_active_root
) {
3197 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3198 (mmu
->root_level
>= PT64_ROOT_4LEVEL
|| mmu
->direct_map
)) {
3199 mmu_free_root_page(kvm
, &mmu
->root_hpa
, &invalid_list
);
3200 } else if (mmu
->pae_root
) {
3201 for (i
= 0; i
< 4; ++i
) {
3202 if (!IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]))
3205 mmu_free_root_page(kvm
, &mmu
->pae_root
[i
],
3207 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3210 mmu
->root_hpa
= INVALID_PAGE
;
3214 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3215 write_unlock(&kvm
->mmu_lock
);
3217 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots
);
3219 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3223 if (!kvm_vcpu_is_visible_gfn(vcpu
, root_gfn
)) {
3224 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3231 static hpa_t
mmu_alloc_root(struct kvm_vcpu
*vcpu
, gfn_t gfn
, gva_t gva
,
3232 u8 level
, bool direct
)
3234 struct kvm_mmu_page
*sp
;
3236 sp
= kvm_mmu_get_page(vcpu
, gfn
, gva
, level
, direct
, ACC_ALL
);
3239 return __pa(sp
->spt
);
3242 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3244 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3245 u8 shadow_root_level
= mmu
->shadow_root_level
;
3250 write_lock(&vcpu
->kvm
->mmu_lock
);
3251 r
= make_mmu_pages_available(vcpu
);
3255 if (is_tdp_mmu_enabled(vcpu
->kvm
)) {
3256 root
= kvm_tdp_mmu_get_vcpu_root_hpa(vcpu
);
3257 mmu
->root_hpa
= root
;
3258 } else if (shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3259 root
= mmu_alloc_root(vcpu
, 0, 0, shadow_root_level
, true);
3260 mmu
->root_hpa
= root
;
3261 } else if (shadow_root_level
== PT32E_ROOT_LEVEL
) {
3262 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3267 for (i
= 0; i
< 4; ++i
) {
3268 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3270 root
= mmu_alloc_root(vcpu
, i
<< (30 - PAGE_SHIFT
),
3271 i
<< 30, PT32_ROOT_LEVEL
, true);
3272 mmu
->pae_root
[i
] = root
| PT_PRESENT_MASK
|
3275 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3277 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level
);
3282 /* root_pgd is ignored for direct MMUs. */
3285 write_unlock(&vcpu
->kvm
->mmu_lock
);
3289 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3291 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3292 u64 pdptrs
[4], pm_mask
;
3293 gfn_t root_gfn
, root_pgd
;
3298 root_pgd
= mmu
->get_guest_pgd(vcpu
);
3299 root_gfn
= root_pgd
>> PAGE_SHIFT
;
3301 if (mmu_check_root(vcpu
, root_gfn
))
3305 * On SVM, reading PDPTRs might access guest memory, which might fault
3306 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3308 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3309 for (i
= 0; i
< 4; ++i
) {
3310 pdptrs
[i
] = mmu
->get_pdptr(vcpu
, i
);
3311 if (!(pdptrs
[i
] & PT_PRESENT_MASK
))
3314 if (mmu_check_root(vcpu
, pdptrs
[i
] >> PAGE_SHIFT
))
3319 write_lock(&vcpu
->kvm
->mmu_lock
);
3320 r
= make_mmu_pages_available(vcpu
);
3325 * Do we shadow a long mode page table? If so we need to
3326 * write-protect the guests page table root.
3328 if (mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3329 root
= mmu_alloc_root(vcpu
, root_gfn
, 0,
3330 mmu
->shadow_root_level
, false);
3331 mmu
->root_hpa
= root
;
3335 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3341 * We shadow a 32 bit page table. This may be a legacy 2-level
3342 * or a PAE 3-level page table. In either case we need to be aware that
3343 * the shadow page table may be a PAE or a long mode page table.
3345 pm_mask
= PT_PRESENT_MASK
| shadow_me_mask
;
3346 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
) {
3347 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3349 if (WARN_ON_ONCE(!mmu
->lm_root
)) {
3354 mmu
->lm_root
[0] = __pa(mmu
->pae_root
) | pm_mask
;
3357 for (i
= 0; i
< 4; ++i
) {
3358 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3360 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3361 if (!(pdptrs
[i
] & PT_PRESENT_MASK
)) {
3362 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3365 root_gfn
= pdptrs
[i
] >> PAGE_SHIFT
;
3368 root
= mmu_alloc_root(vcpu
, root_gfn
, i
<< 30,
3369 PT32_ROOT_LEVEL
, false);
3370 mmu
->pae_root
[i
] = root
| pm_mask
;
3373 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
)
3374 mmu
->root_hpa
= __pa(mmu
->lm_root
);
3376 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3379 mmu
->root_pgd
= root_pgd
;
3381 write_unlock(&vcpu
->kvm
->mmu_lock
);
3386 static int mmu_alloc_special_roots(struct kvm_vcpu
*vcpu
)
3388 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3389 u64
*lm_root
, *pae_root
;
3392 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3393 * tables are allocated and initialized at root creation as there is no
3394 * equivalent level in the guest's NPT to shadow. Allocate the tables
3395 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3397 if (mmu
->direct_map
|| mmu
->root_level
>= PT64_ROOT_4LEVEL
||
3398 mmu
->shadow_root_level
< PT64_ROOT_4LEVEL
)
3402 * This mess only works with 4-level paging and needs to be updated to
3403 * work with 5-level paging.
3405 if (WARN_ON_ONCE(mmu
->shadow_root_level
!= PT64_ROOT_4LEVEL
))
3408 if (mmu
->pae_root
&& mmu
->lm_root
)
3412 * The special roots should always be allocated in concert. Yell and
3413 * bail if KVM ends up in a state where only one of the roots is valid.
3415 if (WARN_ON_ONCE(!tdp_enabled
|| mmu
->pae_root
|| mmu
->lm_root
))
3419 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3420 * doesn't need to be decrypted.
3422 pae_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3426 lm_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3428 free_page((unsigned long)pae_root
);
3432 mmu
->pae_root
= pae_root
;
3433 mmu
->lm_root
= lm_root
;
3438 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3441 struct kvm_mmu_page
*sp
;
3443 if (vcpu
->arch
.mmu
->direct_map
)
3446 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
3449 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3451 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3452 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3453 sp
= to_shadow_page(root
);
3456 * Even if another CPU was marking the SP as unsync-ed
3457 * simultaneously, any guest page table changes are not
3458 * guaranteed to be visible anyway until this VCPU issues a TLB
3459 * flush strictly after those changes are made. We only need to
3460 * ensure that the other CPU sets these flags before any actual
3461 * changes to the page tables are made. The comments in
3462 * mmu_need_write_protect() describe what could go wrong if this
3463 * requirement isn't satisfied.
3465 if (!smp_load_acquire(&sp
->unsync
) &&
3466 !smp_load_acquire(&sp
->unsync_children
))
3469 write_lock(&vcpu
->kvm
->mmu_lock
);
3470 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3472 mmu_sync_children(vcpu
, sp
);
3474 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3475 write_unlock(&vcpu
->kvm
->mmu_lock
);
3479 write_lock(&vcpu
->kvm
->mmu_lock
);
3480 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3482 for (i
= 0; i
< 4; ++i
) {
3483 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3485 if (IS_VALID_PAE_ROOT(root
)) {
3486 root
&= PT64_BASE_ADDR_MASK
;
3487 sp
= to_shadow_page(root
);
3488 mmu_sync_children(vcpu
, sp
);
3492 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3493 write_unlock(&vcpu
->kvm
->mmu_lock
);
3496 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3497 u32 access
, struct x86_exception
*exception
)
3500 exception
->error_code
= 0;
3504 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3506 struct x86_exception
*exception
)
3509 exception
->error_code
= 0;
3510 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3514 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3516 int bit7
= (pte
>> 7) & 1;
3518 return pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1];
3521 static bool __is_bad_mt_xwr(struct rsvd_bits_validate
*rsvd_check
, u64 pte
)
3523 return rsvd_check
->bad_mt_xwr
& BIT_ULL(pte
& 0x3f);
3526 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3529 * A nested guest cannot use the MMIO cache if it is using nested
3530 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3532 if (mmu_is_nested(vcpu
))
3536 return vcpu_match_mmio_gpa(vcpu
, addr
);
3538 return vcpu_match_mmio_gva(vcpu
, addr
);
3542 * Return the level of the lowest level SPTE added to sptes.
3543 * That SPTE may be non-present.
3545 static int get_walk(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptes
, int *root_level
)
3547 struct kvm_shadow_walk_iterator iterator
;
3551 walk_shadow_page_lockless_begin(vcpu
);
3553 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3554 *root_level
= iterator
.level
;
3555 shadow_walk_okay(&iterator
);
3556 __shadow_walk_next(&iterator
, spte
)) {
3557 leaf
= iterator
.level
;
3558 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3562 if (!is_shadow_present_pte(spte
))
3566 walk_shadow_page_lockless_end(vcpu
);
3571 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3572 static bool get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3574 u64 sptes
[PT64_ROOT_MAX_LEVEL
+ 1];
3575 struct rsvd_bits_validate
*rsvd_check
;
3576 int root
, leaf
, level
;
3577 bool reserved
= false;
3579 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)) {
3584 if (is_tdp_mmu_root(vcpu
->kvm
, vcpu
->arch
.mmu
->root_hpa
))
3585 leaf
= kvm_tdp_mmu_get_walk(vcpu
, addr
, sptes
, &root
);
3587 leaf
= get_walk(vcpu
, addr
, sptes
, &root
);
3589 if (unlikely(leaf
< 0)) {
3594 *sptep
= sptes
[leaf
];
3597 * Skip reserved bits checks on the terminal leaf if it's not a valid
3598 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3599 * design, always have reserved bits set. The purpose of the checks is
3600 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3602 if (!is_shadow_present_pte(sptes
[leaf
]))
3605 rsvd_check
= &vcpu
->arch
.mmu
->shadow_zero_check
;
3607 for (level
= root
; level
>= leaf
; level
--)
3609 * Use a bitwise-OR instead of a logical-OR to aggregate the
3610 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3611 * adding a Jcc in the loop.
3613 reserved
|= __is_bad_mt_xwr(rsvd_check
, sptes
[level
]) |
3614 __is_rsvd_bits_set(rsvd_check
, sptes
[level
], level
);
3617 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3619 for (level
= root
; level
>= leaf
; level
--)
3620 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3621 sptes
[level
], level
,
3622 rsvd_check
->rsvd_bits_mask
[(sptes
[level
] >> 7) & 1][level
-1]);
3628 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3633 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3634 return RET_PF_EMULATE
;
3636 reserved
= get_mmio_spte(vcpu
, addr
, &spte
);
3637 if (WARN_ON(reserved
))
3640 if (is_mmio_spte(spte
)) {
3641 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3642 unsigned int access
= get_mmio_spte_access(spte
);
3644 if (!check_mmio_spte(vcpu
, spte
))
3645 return RET_PF_INVALID
;
3650 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3651 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3652 return RET_PF_EMULATE
;
3656 * If the page table is zapped by other cpus, let CPU fault again on
3659 return RET_PF_RETRY
;
3662 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3663 u32 error_code
, gfn_t gfn
)
3665 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3668 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3669 !(error_code
& PFERR_WRITE_MASK
))
3673 * guest is writing the page which is write tracked which can
3674 * not be fixed by page fault handler.
3676 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3682 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3684 struct kvm_shadow_walk_iterator iterator
;
3687 walk_shadow_page_lockless_begin(vcpu
);
3688 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3689 clear_sp_write_flooding_count(iterator
.sptep
);
3690 if (!is_shadow_present_pte(spte
))
3693 walk_shadow_page_lockless_end(vcpu
);
3696 static bool kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3699 struct kvm_arch_async_pf arch
;
3701 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3703 arch
.direct_map
= vcpu
->arch
.mmu
->direct_map
;
3704 arch
.cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3706 return kvm_setup_async_pf(vcpu
, cr2_or_gpa
,
3707 kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3710 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3711 gpa_t cr2_or_gpa
, kvm_pfn_t
*pfn
, hva_t
*hva
,
3712 bool write
, bool *writable
)
3714 struct kvm_memory_slot
*slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3718 * Retry the page fault if the gfn hit a memslot that is being deleted
3719 * or moved. This ensures any existing SPTEs for the old memslot will
3720 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3722 if (slot
&& (slot
->flags
& KVM_MEMSLOT_INVALID
))
3725 /* Don't expose private memslots to L2. */
3726 if (is_guest_mode(vcpu
) && !kvm_is_visible_memslot(slot
)) {
3727 *pfn
= KVM_PFN_NOSLOT
;
3733 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
,
3734 write
, writable
, hva
);
3736 return false; /* *pfn has correct page already */
3738 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3739 trace_kvm_try_async_get_page(cr2_or_gpa
, gfn
);
3740 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3741 trace_kvm_async_pf_doublefault(cr2_or_gpa
, gfn
);
3742 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3744 } else if (kvm_arch_setup_async_pf(vcpu
, cr2_or_gpa
, gfn
))
3748 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
,
3749 write
, writable
, hva
);
3753 static int direct_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3754 bool prefault
, int max_level
, bool is_tdp
)
3756 bool write
= error_code
& PFERR_WRITE_MASK
;
3759 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3760 unsigned long mmu_seq
;
3765 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3766 return RET_PF_EMULATE
;
3768 if (!is_tdp_mmu_root(vcpu
->kvm
, vcpu
->arch
.mmu
->root_hpa
)) {
3769 r
= fast_page_fault(vcpu
, gpa
, error_code
);
3770 if (r
!= RET_PF_INVALID
)
3774 r
= mmu_topup_memory_caches(vcpu
, false);
3778 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3781 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, &hva
,
3782 write
, &map_writable
))
3783 return RET_PF_RETRY
;
3785 if (handle_abnormal_pfn(vcpu
, is_tdp
? 0 : gpa
, gfn
, pfn
, ACC_ALL
, &r
))
3790 if (is_tdp_mmu_root(vcpu
->kvm
, vcpu
->arch
.mmu
->root_hpa
))
3791 read_lock(&vcpu
->kvm
->mmu_lock
);
3793 write_lock(&vcpu
->kvm
->mmu_lock
);
3795 if (!is_noslot_pfn(pfn
) && mmu_notifier_retry_hva(vcpu
->kvm
, mmu_seq
, hva
))
3797 r
= make_mmu_pages_available(vcpu
);
3801 if (is_tdp_mmu_root(vcpu
->kvm
, vcpu
->arch
.mmu
->root_hpa
))
3802 r
= kvm_tdp_mmu_map(vcpu
, gpa
, error_code
, map_writable
, max_level
,
3805 r
= __direct_map(vcpu
, gpa
, error_code
, map_writable
, max_level
, pfn
,
3809 if (is_tdp_mmu_root(vcpu
->kvm
, vcpu
->arch
.mmu
->root_hpa
))
3810 read_unlock(&vcpu
->kvm
->mmu_lock
);
3812 write_unlock(&vcpu
->kvm
->mmu_lock
);
3813 kvm_release_pfn_clean(pfn
);
3817 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3818 u32 error_code
, bool prefault
)
3820 pgprintk("%s: gva %lx error %x\n", __func__
, gpa
, error_code
);
3822 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3823 return direct_page_fault(vcpu
, gpa
& PAGE_MASK
, error_code
, prefault
,
3824 PG_LEVEL_2M
, false);
3827 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3828 u64 fault_address
, char *insn
, int insn_len
)
3831 u32 flags
= vcpu
->arch
.apf
.host_apf_flags
;
3833 #ifndef CONFIG_X86_64
3834 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3835 if (WARN_ON_ONCE(fault_address
>> 32))
3839 vcpu
->arch
.l1tf_flush_l1d
= true;
3841 trace_kvm_page_fault(fault_address
, error_code
);
3843 if (kvm_event_needs_reinjection(vcpu
))
3844 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3845 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3847 } else if (flags
& KVM_PV_REASON_PAGE_NOT_PRESENT
) {
3848 vcpu
->arch
.apf
.host_apf_flags
= 0;
3849 local_irq_disable();
3850 kvm_async_pf_task_wait_schedule(fault_address
);
3853 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags
);
3858 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3860 int kvm_tdp_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3865 for (max_level
= KVM_MAX_HUGEPAGE_LEVEL
;
3866 max_level
> PG_LEVEL_4K
;
3868 int page_num
= KVM_PAGES_PER_HPAGE(max_level
);
3869 gfn_t base
= (gpa
>> PAGE_SHIFT
) & ~(page_num
- 1);
3871 if (kvm_mtrr_check_gfn_range_consistency(vcpu
, base
, page_num
))
3875 return direct_page_fault(vcpu
, gpa
, error_code
, prefault
,
3879 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3880 struct kvm_mmu
*context
)
3882 context
->page_fault
= nonpaging_page_fault
;
3883 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3884 context
->sync_page
= nonpaging_sync_page
;
3885 context
->invlpg
= NULL
;
3886 context
->root_level
= 0;
3887 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3888 context
->direct_map
= true;
3889 context
->nx
= false;
3892 static inline bool is_root_usable(struct kvm_mmu_root_info
*root
, gpa_t pgd
,
3893 union kvm_mmu_page_role role
)
3895 return (role
.direct
|| pgd
== root
->pgd
) &&
3896 VALID_PAGE(root
->hpa
) && to_shadow_page(root
->hpa
) &&
3897 role
.word
== to_shadow_page(root
->hpa
)->role
.word
;
3901 * Find out if a previously cached root matching the new pgd/role is available.
3902 * The current root is also inserted into the cache.
3903 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3905 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3906 * false is returned. This root should now be freed by the caller.
3908 static bool cached_root_available(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3909 union kvm_mmu_page_role new_role
)
3912 struct kvm_mmu_root_info root
;
3913 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3915 root
.pgd
= mmu
->root_pgd
;
3916 root
.hpa
= mmu
->root_hpa
;
3918 if (is_root_usable(&root
, new_pgd
, new_role
))
3921 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
3922 swap(root
, mmu
->prev_roots
[i
]);
3924 if (is_root_usable(&root
, new_pgd
, new_role
))
3928 mmu
->root_hpa
= root
.hpa
;
3929 mmu
->root_pgd
= root
.pgd
;
3931 return i
< KVM_MMU_NUM_PREV_ROOTS
;
3934 static bool fast_pgd_switch(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3935 union kvm_mmu_page_role new_role
)
3937 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3940 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3941 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3942 * later if necessary.
3944 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3945 mmu
->root_level
>= PT64_ROOT_4LEVEL
)
3946 return cached_root_available(vcpu
, new_pgd
, new_role
);
3951 static void __kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
3952 union kvm_mmu_page_role new_role
,
3953 bool skip_tlb_flush
, bool skip_mmu_sync
)
3955 if (!fast_pgd_switch(vcpu
, new_pgd
, new_role
)) {
3956 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
, KVM_MMU_ROOT_CURRENT
);
3961 * It's possible that the cached previous root page is obsolete because
3962 * of a change in the MMU generation number. However, changing the
3963 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3964 * free the root set here and allocate a new one.
3966 kvm_make_request(KVM_REQ_LOAD_MMU_PGD
, vcpu
);
3968 if (!skip_mmu_sync
|| force_flush_and_sync_on_reuse
)
3969 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
3970 if (!skip_tlb_flush
|| force_flush_and_sync_on_reuse
)
3971 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
3974 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3975 * switching to a new CR3, that GVA->GPA mapping may no longer be
3976 * valid. So clear any cached MMIO info even when we don't need to sync
3977 * the shadow page tables.
3979 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3982 * If this is a direct root page, it doesn't have a write flooding
3983 * count. Otherwise, clear the write flooding count.
3985 if (!new_role
.direct
)
3986 __clear_sp_write_flooding_count(
3987 to_shadow_page(vcpu
->arch
.mmu
->root_hpa
));
3990 void kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
, bool skip_tlb_flush
,
3993 __kvm_mmu_new_pgd(vcpu
, new_pgd
, kvm_mmu_calc_root_page_role(vcpu
),
3994 skip_tlb_flush
, skip_mmu_sync
);
3996 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd
);
3998 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
4000 return kvm_read_cr3(vcpu
);
4003 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
4004 unsigned int access
, int *nr_present
)
4006 if (unlikely(is_mmio_spte(*sptep
))) {
4007 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
4008 mmu_spte_clear_no_track(sptep
);
4013 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
4020 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
4021 unsigned level
, unsigned gpte
)
4024 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4025 * If it is clear, there are no large pages at this level, so clear
4026 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4028 gpte
&= level
- mmu
->last_nonleaf_level
;
4031 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4032 * iff level <= PG_LEVEL_4K, which for our purpose means
4033 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4035 gpte
|= level
- PG_LEVEL_4K
- 1;
4037 return gpte
& PT_PAGE_SIZE_MASK
;
4040 #define PTTYPE_EPT 18 /* arbitrary */
4041 #define PTTYPE PTTYPE_EPT
4042 #include "paging_tmpl.h"
4046 #include "paging_tmpl.h"
4050 #include "paging_tmpl.h"
4054 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4055 struct rsvd_bits_validate
*rsvd_check
,
4056 u64 pa_bits_rsvd
, int level
, bool nx
, bool gbpages
,
4059 u64 gbpages_bit_rsvd
= 0;
4060 u64 nonleaf_bit8_rsvd
= 0;
4063 rsvd_check
->bad_mt_xwr
= 0;
4066 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4068 if (level
== PT32E_ROOT_LEVEL
)
4069 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 62);
4071 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4073 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4075 high_bits_rsvd
|= rsvd_bits(63, 63);
4078 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4079 * leaf entries) on AMD CPUs only.
4082 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4085 case PT32_ROOT_LEVEL
:
4086 /* no rsvd bits for 2 level 4K page table entries */
4087 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4088 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4089 rsvd_check
->rsvd_bits_mask
[1][0] =
4090 rsvd_check
->rsvd_bits_mask
[0][0];
4093 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4097 if (is_cpuid_PSE36())
4098 /* 36bits PSE 4MB page */
4099 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4101 /* 32 bits PSE 4MB page */
4102 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4104 case PT32E_ROOT_LEVEL
:
4105 rsvd_check
->rsvd_bits_mask
[0][2] = rsvd_bits(63, 63) |
4108 rsvd_bits(1, 2); /* PDPTE */
4109 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
; /* PDE */
4110 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
; /* PTE */
4111 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4112 rsvd_bits(13, 20); /* large page */
4113 rsvd_check
->rsvd_bits_mask
[1][0] =
4114 rsvd_check
->rsvd_bits_mask
[0][0];
4116 case PT64_ROOT_5LEVEL
:
4117 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
|
4120 rsvd_check
->rsvd_bits_mask
[1][4] =
4121 rsvd_check
->rsvd_bits_mask
[0][4];
4123 case PT64_ROOT_4LEVEL
:
4124 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
|
4127 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
|
4129 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
;
4130 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4131 rsvd_check
->rsvd_bits_mask
[1][3] =
4132 rsvd_check
->rsvd_bits_mask
[0][3];
4133 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
|
4136 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4137 rsvd_bits(13, 20); /* large page */
4138 rsvd_check
->rsvd_bits_mask
[1][0] =
4139 rsvd_check
->rsvd_bits_mask
[0][0];
4144 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4145 struct kvm_mmu
*context
)
4147 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4148 vcpu
->arch
.reserved_gpa_bits
,
4149 context
->root_level
, context
->nx
,
4150 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4152 guest_cpuid_is_amd_or_hygon(vcpu
));
4156 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4157 u64 pa_bits_rsvd
, bool execonly
)
4159 u64 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4162 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
| rsvd_bits(3, 7);
4163 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
| rsvd_bits(3, 7);
4164 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
| rsvd_bits(3, 6);
4165 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
| rsvd_bits(3, 6);
4166 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4169 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4170 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4171 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
| rsvd_bits(12, 29);
4172 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
| rsvd_bits(12, 20);
4173 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4175 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4176 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4177 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4178 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4179 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4181 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4182 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4184 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4187 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4188 struct kvm_mmu
*context
, bool execonly
)
4190 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4191 vcpu
->arch
.reserved_gpa_bits
, execonly
);
4194 static inline u64
reserved_hpa_bits(void)
4196 return rsvd_bits(shadow_phys_bits
, 63);
4200 * the page table on host is the shadow page table for the page
4201 * table in guest or amd nested guest, its mmu features completely
4202 * follow the features in guest.
4205 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4207 bool uses_nx
= context
->nx
||
4208 context
->mmu_role
.base
.smep_andnot_wp
;
4209 struct rsvd_bits_validate
*shadow_zero_check
;
4213 * Passing "true" to the last argument is okay; it adds a check
4214 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4216 shadow_zero_check
= &context
->shadow_zero_check
;
4217 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4218 reserved_hpa_bits(),
4219 context
->shadow_root_level
, uses_nx
,
4220 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4221 is_pse(vcpu
), true);
4223 if (!shadow_me_mask
)
4226 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4227 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4228 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4232 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4234 static inline bool boot_cpu_is_amd(void)
4236 WARN_ON_ONCE(!tdp_enabled
);
4237 return shadow_x_mask
== 0;
4241 * the direct page table on host, use as much mmu features as
4242 * possible, however, kvm currently does not do execution-protection.
4245 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4246 struct kvm_mmu
*context
)
4248 struct rsvd_bits_validate
*shadow_zero_check
;
4251 shadow_zero_check
= &context
->shadow_zero_check
;
4253 if (boot_cpu_is_amd())
4254 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4255 reserved_hpa_bits(),
4256 context
->shadow_root_level
, false,
4257 boot_cpu_has(X86_FEATURE_GBPAGES
),
4260 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4261 reserved_hpa_bits(), false);
4263 if (!shadow_me_mask
)
4266 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4267 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4268 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4273 * as the comments in reset_shadow_zero_bits_mask() except it
4274 * is the shadow page table for intel nested guest.
4277 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4278 struct kvm_mmu
*context
, bool execonly
)
4280 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4281 reserved_hpa_bits(), execonly
);
4284 #define BYTE_MASK(access) \
4285 ((1 & (access) ? 2 : 0) | \
4286 (2 & (access) ? 4 : 0) | \
4287 (3 & (access) ? 8 : 0) | \
4288 (4 & (access) ? 16 : 0) | \
4289 (5 & (access) ? 32 : 0) | \
4290 (6 & (access) ? 64 : 0) | \
4291 (7 & (access) ? 128 : 0))
4294 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4295 struct kvm_mmu
*mmu
, bool ept
)
4299 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4300 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4301 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4303 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4304 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4305 bool cr0_wp
= is_write_protection(vcpu
);
4307 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4308 unsigned pfec
= byte
<< 1;
4311 * Each "*f" variable has a 1 bit for each UWX value
4312 * that causes a fault with the given PFEC.
4315 /* Faults from writes to non-writable pages */
4316 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? (u8
)~w
: 0;
4317 /* Faults from user mode accesses to supervisor pages */
4318 u8 uf
= (pfec
& PFERR_USER_MASK
) ? (u8
)~u
: 0;
4319 /* Faults from fetches of non-executable pages*/
4320 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? (u8
)~x
: 0;
4321 /* Faults from kernel mode fetches of user pages */
4323 /* Faults from kernel mode accesses of user pages */
4327 /* Faults from kernel mode accesses to user pages */
4328 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4330 /* Not really needed: !nx will cause pte.nx to fault */
4334 /* Allow supervisor writes if !cr0.wp */
4336 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4338 /* Disallow supervisor fetches of user code if cr4.smep */
4340 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4343 * SMAP:kernel-mode data accesses from user-mode
4344 * mappings should fault. A fault is considered
4345 * as a SMAP violation if all of the following
4346 * conditions are true:
4347 * - X86_CR4_SMAP is set in CR4
4348 * - A user page is accessed
4349 * - The access is not a fetch
4350 * - Page fault in kernel mode
4351 * - if CPL = 3 or X86_EFLAGS_AC is clear
4353 * Here, we cover the first three conditions.
4354 * The fourth is computed dynamically in permission_fault();
4355 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4356 * *not* subject to SMAP restrictions.
4359 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4362 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4367 * PKU is an additional mechanism by which the paging controls access to
4368 * user-mode addresses based on the value in the PKRU register. Protection
4369 * key violations are reported through a bit in the page fault error code.
4370 * Unlike other bits of the error code, the PK bit is not known at the
4371 * call site of e.g. gva_to_gpa; it must be computed directly in
4372 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4373 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4375 * In particular the following conditions come from the error code, the
4376 * page tables and the machine state:
4377 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4378 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4379 * - PK is always zero if U=0 in the page tables
4380 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4382 * The PKRU bitmask caches the result of these four conditions. The error
4383 * code (minus the P bit) and the page table's U bit form an index into the
4384 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4385 * with the two bits of the PKRU register corresponding to the protection key.
4386 * For the first three conditions above the bits will be 00, thus masking
4387 * away both AD and WD. For all reads or if the last condition holds, WD
4388 * only will be masked away.
4390 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4401 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4402 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4407 wp
= is_write_protection(vcpu
);
4409 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4410 unsigned pfec
, pkey_bits
;
4411 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4414 ff
= pfec
& PFERR_FETCH_MASK
;
4415 uf
= pfec
& PFERR_USER_MASK
;
4416 wf
= pfec
& PFERR_WRITE_MASK
;
4418 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4419 pte_user
= pfec
& PFERR_RSVD_MASK
;
4422 * Only need to check the access which is not an
4423 * instruction fetch and is to a user page.
4425 check_pkey
= (!ff
&& pte_user
);
4427 * write access is controlled by PKRU if it is a
4428 * user access or CR0.WP = 1.
4430 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4432 /* PKRU.AD stops both read and write access. */
4433 pkey_bits
= !!check_pkey
;
4434 /* PKRU.WD stops write access. */
4435 pkey_bits
|= (!!check_write
) << 1;
4437 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4441 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4443 unsigned root_level
= mmu
->root_level
;
4445 mmu
->last_nonleaf_level
= root_level
;
4446 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4447 mmu
->last_nonleaf_level
++;
4450 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4451 struct kvm_mmu
*context
,
4454 context
->nx
= is_nx(vcpu
);
4455 context
->root_level
= level
;
4457 reset_rsvds_bits_mask(vcpu
, context
);
4458 update_permission_bitmask(vcpu
, context
, false);
4459 update_pkru_bitmask(vcpu
, context
, false);
4460 update_last_nonleaf_level(vcpu
, context
);
4462 MMU_WARN_ON(!is_pae(vcpu
));
4463 context
->page_fault
= paging64_page_fault
;
4464 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4465 context
->sync_page
= paging64_sync_page
;
4466 context
->invlpg
= paging64_invlpg
;
4467 context
->shadow_root_level
= level
;
4468 context
->direct_map
= false;
4471 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4472 struct kvm_mmu
*context
)
4474 int root_level
= is_la57_mode(vcpu
) ?
4475 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4477 paging64_init_context_common(vcpu
, context
, root_level
);
4480 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4481 struct kvm_mmu
*context
)
4483 context
->nx
= false;
4484 context
->root_level
= PT32_ROOT_LEVEL
;
4486 reset_rsvds_bits_mask(vcpu
, context
);
4487 update_permission_bitmask(vcpu
, context
, false);
4488 update_pkru_bitmask(vcpu
, context
, false);
4489 update_last_nonleaf_level(vcpu
, context
);
4491 context
->page_fault
= paging32_page_fault
;
4492 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4493 context
->sync_page
= paging32_sync_page
;
4494 context
->invlpg
= paging32_invlpg
;
4495 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4496 context
->direct_map
= false;
4499 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4500 struct kvm_mmu
*context
)
4502 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4505 static union kvm_mmu_extended_role
kvm_calc_mmu_role_ext(struct kvm_vcpu
*vcpu
)
4507 union kvm_mmu_extended_role ext
= {0};
4509 ext
.cr0_pg
= !!is_paging(vcpu
);
4510 ext
.cr4_pae
= !!is_pae(vcpu
);
4511 ext
.cr4_smep
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4512 ext
.cr4_smap
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4513 ext
.cr4_pse
= !!is_pse(vcpu
);
4514 ext
.cr4_pke
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
);
4515 ext
.maxphyaddr
= cpuid_maxphyaddr(vcpu
);
4522 static union kvm_mmu_role
kvm_calc_mmu_role_common(struct kvm_vcpu
*vcpu
,
4525 union kvm_mmu_role role
= {0};
4527 role
.base
.access
= ACC_ALL
;
4528 role
.base
.nxe
= !!is_nx(vcpu
);
4529 role
.base
.cr0_wp
= is_write_protection(vcpu
);
4530 role
.base
.smm
= is_smm(vcpu
);
4531 role
.base
.guest_mode
= is_guest_mode(vcpu
);
4536 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
4541 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu
*vcpu
)
4543 /* Use 5-level TDP if and only if it's useful/necessary. */
4544 if (max_tdp_level
== 5 && cpuid_maxphyaddr(vcpu
) <= 48)
4547 return max_tdp_level
;
4550 static union kvm_mmu_role
4551 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4553 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4555 role
.base
.ad_disabled
= (shadow_accessed_mask
== 0);
4556 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4557 role
.base
.direct
= true;
4558 role
.base
.gpte_is_8_bytes
= true;
4563 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4565 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4566 union kvm_mmu_role new_role
=
4567 kvm_calc_tdp_mmu_root_page_role(vcpu
, false);
4569 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4572 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4573 context
->page_fault
= kvm_tdp_page_fault
;
4574 context
->sync_page
= nonpaging_sync_page
;
4575 context
->invlpg
= NULL
;
4576 context
->shadow_root_level
= kvm_mmu_get_tdp_level(vcpu
);
4577 context
->direct_map
= true;
4578 context
->get_guest_pgd
= get_cr3
;
4579 context
->get_pdptr
= kvm_pdptr_read
;
4580 context
->inject_page_fault
= kvm_inject_page_fault
;
4582 if (!is_paging(vcpu
)) {
4583 context
->nx
= false;
4584 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4585 context
->root_level
= 0;
4586 } else if (is_long_mode(vcpu
)) {
4587 context
->nx
= is_nx(vcpu
);
4588 context
->root_level
= is_la57_mode(vcpu
) ?
4589 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4590 reset_rsvds_bits_mask(vcpu
, context
);
4591 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4592 } else if (is_pae(vcpu
)) {
4593 context
->nx
= is_nx(vcpu
);
4594 context
->root_level
= PT32E_ROOT_LEVEL
;
4595 reset_rsvds_bits_mask(vcpu
, context
);
4596 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4598 context
->nx
= false;
4599 context
->root_level
= PT32_ROOT_LEVEL
;
4600 reset_rsvds_bits_mask(vcpu
, context
);
4601 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4604 update_permission_bitmask(vcpu
, context
, false);
4605 update_pkru_bitmask(vcpu
, context
, false);
4606 update_last_nonleaf_level(vcpu
, context
);
4607 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4610 static union kvm_mmu_role
4611 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu
*vcpu
, bool base_only
)
4613 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4615 role
.base
.smep_andnot_wp
= role
.ext
.cr4_smep
&&
4616 !is_write_protection(vcpu
);
4617 role
.base
.smap_andnot_wp
= role
.ext
.cr4_smap
&&
4618 !is_write_protection(vcpu
);
4619 role
.base
.gpte_is_8_bytes
= !!is_pae(vcpu
);
4624 static union kvm_mmu_role
4625 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4627 union kvm_mmu_role role
=
4628 kvm_calc_shadow_root_page_role_common(vcpu
, base_only
);
4630 role
.base
.direct
= !is_paging(vcpu
);
4632 if (!is_long_mode(vcpu
))
4633 role
.base
.level
= PT32E_ROOT_LEVEL
;
4634 else if (is_la57_mode(vcpu
))
4635 role
.base
.level
= PT64_ROOT_5LEVEL
;
4637 role
.base
.level
= PT64_ROOT_4LEVEL
;
4642 static void shadow_mmu_init_context(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
,
4643 u32 cr0
, u32 cr4
, u32 efer
,
4644 union kvm_mmu_role new_role
)
4646 if (!(cr0
& X86_CR0_PG
))
4647 nonpaging_init_context(vcpu
, context
);
4648 else if (efer
& EFER_LMA
)
4649 paging64_init_context(vcpu
, context
);
4650 else if (cr4
& X86_CR4_PAE
)
4651 paging32E_init_context(vcpu
, context
);
4653 paging32_init_context(vcpu
, context
);
4655 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4656 reset_shadow_zero_bits_mask(vcpu
, context
);
4659 static void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, u32 cr0
, u32 cr4
, u32 efer
)
4661 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4662 union kvm_mmu_role new_role
=
4663 kvm_calc_shadow_mmu_root_page_role(vcpu
, false);
4665 if (new_role
.as_u64
!= context
->mmu_role
.as_u64
)
4666 shadow_mmu_init_context(vcpu
, context
, cr0
, cr4
, efer
, new_role
);
4669 static union kvm_mmu_role
4670 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu
*vcpu
)
4672 union kvm_mmu_role role
=
4673 kvm_calc_shadow_root_page_role_common(vcpu
, false);
4675 role
.base
.direct
= false;
4676 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4681 void kvm_init_shadow_npt_mmu(struct kvm_vcpu
*vcpu
, u32 cr0
, u32 cr4
, u32 efer
,
4684 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4685 union kvm_mmu_role new_role
= kvm_calc_shadow_npt_root_page_role(vcpu
);
4687 __kvm_mmu_new_pgd(vcpu
, nested_cr3
, new_role
.base
, false, false);
4689 if (new_role
.as_u64
!= context
->mmu_role
.as_u64
) {
4690 shadow_mmu_init_context(vcpu
, context
, cr0
, cr4
, efer
, new_role
);
4693 * Override the level set by the common init helper, nested TDP
4694 * always uses the host's TDP configuration.
4696 context
->shadow_root_level
= new_role
.base
.level
;
4699 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu
);
4701 static union kvm_mmu_role
4702 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu
*vcpu
, bool accessed_dirty
,
4703 bool execonly
, u8 level
)
4705 union kvm_mmu_role role
= {0};
4707 /* SMM flag is inherited from root_mmu */
4708 role
.base
.smm
= vcpu
->arch
.root_mmu
.mmu_role
.base
.smm
;
4710 role
.base
.level
= level
;
4711 role
.base
.gpte_is_8_bytes
= true;
4712 role
.base
.direct
= false;
4713 role
.base
.ad_disabled
= !accessed_dirty
;
4714 role
.base
.guest_mode
= true;
4715 role
.base
.access
= ACC_ALL
;
4718 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4719 * SMAP variation to denote shadow EPT entries.
4721 role
.base
.cr0_wp
= true;
4722 role
.base
.smap_andnot_wp
= true;
4724 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
4725 role
.ext
.execonly
= execonly
;
4730 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4731 bool accessed_dirty
, gpa_t new_eptp
)
4733 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4734 u8 level
= vmx_eptp_page_walk_level(new_eptp
);
4735 union kvm_mmu_role new_role
=
4736 kvm_calc_shadow_ept_root_page_role(vcpu
, accessed_dirty
,
4739 __kvm_mmu_new_pgd(vcpu
, new_eptp
, new_role
.base
, true, true);
4741 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4744 context
->shadow_root_level
= level
;
4747 context
->ept_ad
= accessed_dirty
;
4748 context
->page_fault
= ept_page_fault
;
4749 context
->gva_to_gpa
= ept_gva_to_gpa
;
4750 context
->sync_page
= ept_sync_page
;
4751 context
->invlpg
= ept_invlpg
;
4752 context
->root_level
= level
;
4753 context
->direct_map
= false;
4754 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4756 update_permission_bitmask(vcpu
, context
, true);
4757 update_pkru_bitmask(vcpu
, context
, true);
4758 update_last_nonleaf_level(vcpu
, context
);
4759 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4760 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4762 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4764 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4766 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4768 kvm_init_shadow_mmu(vcpu
,
4769 kvm_read_cr0_bits(vcpu
, X86_CR0_PG
),
4770 kvm_read_cr4_bits(vcpu
, X86_CR4_PAE
),
4773 context
->get_guest_pgd
= get_cr3
;
4774 context
->get_pdptr
= kvm_pdptr_read
;
4775 context
->inject_page_fault
= kvm_inject_page_fault
;
4778 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4780 union kvm_mmu_role new_role
= kvm_calc_mmu_role_common(vcpu
, false);
4781 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4783 if (new_role
.as_u64
== g_context
->mmu_role
.as_u64
)
4786 g_context
->mmu_role
.as_u64
= new_role
.as_u64
;
4787 g_context
->get_guest_pgd
= get_cr3
;
4788 g_context
->get_pdptr
= kvm_pdptr_read
;
4789 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4792 * L2 page tables are never shadowed, so there is no need to sync
4795 g_context
->invlpg
= NULL
;
4798 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4799 * L1's nested page tables (e.g. EPT12). The nested translation
4800 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4801 * L2's page tables as the first level of translation and L1's
4802 * nested page tables as the second level of translation. Basically
4803 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4805 if (!is_paging(vcpu
)) {
4806 g_context
->nx
= false;
4807 g_context
->root_level
= 0;
4808 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4809 } else if (is_long_mode(vcpu
)) {
4810 g_context
->nx
= is_nx(vcpu
);
4811 g_context
->root_level
= is_la57_mode(vcpu
) ?
4812 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4813 reset_rsvds_bits_mask(vcpu
, g_context
);
4814 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4815 } else if (is_pae(vcpu
)) {
4816 g_context
->nx
= is_nx(vcpu
);
4817 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4818 reset_rsvds_bits_mask(vcpu
, g_context
);
4819 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4821 g_context
->nx
= false;
4822 g_context
->root_level
= PT32_ROOT_LEVEL
;
4823 reset_rsvds_bits_mask(vcpu
, g_context
);
4824 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4827 update_permission_bitmask(vcpu
, g_context
, false);
4828 update_pkru_bitmask(vcpu
, g_context
, false);
4829 update_last_nonleaf_level(vcpu
, g_context
);
4832 void kvm_init_mmu(struct kvm_vcpu
*vcpu
, bool reset_roots
)
4837 vcpu
->arch
.mmu
->root_hpa
= INVALID_PAGE
;
4839 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
4840 vcpu
->arch
.mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
4843 if (mmu_is_nested(vcpu
))
4844 init_kvm_nested_mmu(vcpu
);
4845 else if (tdp_enabled
)
4846 init_kvm_tdp_mmu(vcpu
);
4848 init_kvm_softmmu(vcpu
);
4850 EXPORT_SYMBOL_GPL(kvm_init_mmu
);
4852 static union kvm_mmu_page_role
4853 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
)
4855 union kvm_mmu_role role
;
4858 role
= kvm_calc_tdp_mmu_root_page_role(vcpu
, true);
4860 role
= kvm_calc_shadow_mmu_root_page_role(vcpu
, true);
4865 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4867 kvm_mmu_unload(vcpu
);
4868 kvm_init_mmu(vcpu
, true);
4870 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4872 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4876 r
= mmu_topup_memory_caches(vcpu
, !vcpu
->arch
.mmu
->direct_map
);
4879 r
= mmu_alloc_special_roots(vcpu
);
4882 if (vcpu
->arch
.mmu
->direct_map
)
4883 r
= mmu_alloc_direct_roots(vcpu
);
4885 r
= mmu_alloc_shadow_roots(vcpu
);
4889 kvm_mmu_sync_roots(vcpu
);
4891 kvm_mmu_load_pgd(vcpu
);
4892 static_call(kvm_x86_tlb_flush_current
)(vcpu
);
4897 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4899 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.root_mmu
, KVM_MMU_ROOTS_ALL
);
4900 WARN_ON(VALID_PAGE(vcpu
->arch
.root_mmu
.root_hpa
));
4901 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
4902 WARN_ON(VALID_PAGE(vcpu
->arch
.guest_mmu
.root_hpa
));
4905 static bool need_remote_flush(u64 old
, u64
new)
4907 if (!is_shadow_present_pte(old
))
4909 if (!is_shadow_present_pte(new))
4911 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4913 old
^= shadow_nx_mask
;
4914 new ^= shadow_nx_mask
;
4915 return (old
& ~new & PT64_PERM_MASK
) != 0;
4918 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4925 * Assume that the pte write on a page table of the same type
4926 * as the current vcpu paging mode since we update the sptes only
4927 * when they have the same mode.
4929 if (is_pae(vcpu
) && *bytes
== 4) {
4930 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4935 if (*bytes
== 4 || *bytes
== 8) {
4936 r
= kvm_vcpu_read_guest_atomic(vcpu
, *gpa
, &gentry
, *bytes
);
4945 * If we're seeing too many writes to a page, it may no longer be a page table,
4946 * or we may be forking, in which case it is better to unmap the page.
4948 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4951 * Skip write-flooding detected for the sp whose level is 1, because
4952 * it can become unsync, then the guest page is not write-protected.
4954 if (sp
->role
.level
== PG_LEVEL_4K
)
4957 atomic_inc(&sp
->write_flooding_count
);
4958 return atomic_read(&sp
->write_flooding_count
) >= 3;
4962 * Misaligned accesses are too much trouble to fix up; also, they usually
4963 * indicate a page is not used as a page table.
4965 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4968 unsigned offset
, pte_size
, misaligned
;
4970 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4971 gpa
, bytes
, sp
->role
.word
);
4973 offset
= offset_in_page(gpa
);
4974 pte_size
= sp
->role
.gpte_is_8_bytes
? 8 : 4;
4977 * Sometimes, the OS only writes the last one bytes to update status
4978 * bits, for example, in linux, andb instruction is used in clear_bit().
4980 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4983 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4984 misaligned
|= bytes
< 4;
4989 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4991 unsigned page_offset
, quadrant
;
4995 page_offset
= offset_in_page(gpa
);
4996 level
= sp
->role
.level
;
4998 if (!sp
->role
.gpte_is_8_bytes
) {
4999 page_offset
<<= 1; /* 32->64 */
5001 * A 32-bit pde maps 4MB while the shadow pdes map
5002 * only 2MB. So we need to double the offset again
5003 * and zap two pdes instead of one.
5005 if (level
== PT32_ROOT_LEVEL
) {
5006 page_offset
&= ~7; /* kill rounding error */
5010 quadrant
= page_offset
>> PAGE_SHIFT
;
5011 page_offset
&= ~PAGE_MASK
;
5012 if (quadrant
!= sp
->role
.quadrant
)
5016 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
5020 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
5021 const u8
*new, int bytes
,
5022 struct kvm_page_track_notifier_node
*node
)
5024 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
5025 struct kvm_mmu_page
*sp
;
5026 LIST_HEAD(invalid_list
);
5027 u64 entry
, gentry
, *spte
;
5029 bool remote_flush
, local_flush
;
5032 * If we don't have indirect shadow pages, it means no page is
5033 * write-protected, so we can exit simply.
5035 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
5038 remote_flush
= local_flush
= false;
5040 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
5043 * No need to care whether allocation memory is successful
5044 * or not since pte prefetch is skiped if it does not have
5045 * enough objects in the cache.
5047 mmu_topup_memory_caches(vcpu
, true);
5049 write_lock(&vcpu
->kvm
->mmu_lock
);
5051 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, &bytes
);
5053 ++vcpu
->kvm
->stat
.mmu_pte_write
;
5054 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
5056 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
5057 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
5058 detect_write_flooding(sp
)) {
5059 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
5060 ++vcpu
->kvm
->stat
.mmu_flooded
;
5064 spte
= get_written_sptes(sp
, gpa
, &npte
);
5071 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
, NULL
);
5072 if (gentry
&& sp
->role
.level
!= PG_LEVEL_4K
)
5073 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
5074 if (need_remote_flush(entry
, *spte
))
5075 remote_flush
= true;
5079 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
5080 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
5081 write_unlock(&vcpu
->kvm
->mmu_lock
);
5084 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
, u64 error_code
,
5085 void *insn
, int insn_len
)
5087 int r
, emulation_type
= EMULTYPE_PF
;
5088 bool direct
= vcpu
->arch
.mmu
->direct_map
;
5090 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
5091 return RET_PF_RETRY
;
5094 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
5095 r
= handle_mmio_page_fault(vcpu
, cr2_or_gpa
, direct
);
5096 if (r
== RET_PF_EMULATE
)
5100 if (r
== RET_PF_INVALID
) {
5101 r
= kvm_mmu_do_page_fault(vcpu
, cr2_or_gpa
,
5102 lower_32_bits(error_code
), false);
5103 if (WARN_ON_ONCE(r
== RET_PF_INVALID
))
5109 if (r
!= RET_PF_EMULATE
)
5113 * Before emulating the instruction, check if the error code
5114 * was due to a RO violation while translating the guest page.
5115 * This can occur when using nested virtualization with nested
5116 * paging in both guests. If true, we simply unprotect the page
5117 * and resume the guest.
5119 if (vcpu
->arch
.mmu
->direct_map
&&
5120 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
5121 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2_or_gpa
));
5126 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5127 * optimistically try to just unprotect the page and let the processor
5128 * re-execute the instruction that caused the page fault. Do not allow
5129 * retrying MMIO emulation, as it's not only pointless but could also
5130 * cause us to enter an infinite loop because the processor will keep
5131 * faulting on the non-existent MMIO address. Retrying an instruction
5132 * from a nested guest is also pointless and dangerous as we are only
5133 * explicitly shadowing L1's page tables, i.e. unprotecting something
5134 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5136 if (!mmio_info_in_cache(vcpu
, cr2_or_gpa
, direct
) && !is_guest_mode(vcpu
))
5137 emulation_type
|= EMULTYPE_ALLOW_RETRY_PF
;
5139 return x86_emulate_instruction(vcpu
, cr2_or_gpa
, emulation_type
, insn
,
5142 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
5144 void kvm_mmu_invalidate_gva(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
5145 gva_t gva
, hpa_t root_hpa
)
5149 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5150 if (mmu
!= &vcpu
->arch
.guest_mmu
) {
5151 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5152 if (is_noncanonical_address(gva
, vcpu
))
5155 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5161 if (root_hpa
== INVALID_PAGE
) {
5162 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5165 * INVLPG is required to invalidate any global mappings for the VA,
5166 * irrespective of PCID. Since it would take us roughly similar amount
5167 * of work to determine whether any of the prev_root mappings of the VA
5168 * is marked global, or to just sync it blindly, so we might as well
5169 * just always sync it.
5171 * Mappings not reachable via the current cr3 or the prev_roots will be
5172 * synced when switching to that cr3, so nothing needs to be done here
5175 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5176 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
5177 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5179 mmu
->invlpg(vcpu
, gva
, root_hpa
);
5183 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
5185 kvm_mmu_invalidate_gva(vcpu
, vcpu
->arch
.mmu
, gva
, INVALID_PAGE
);
5186 ++vcpu
->stat
.invlpg
;
5188 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
5191 void kvm_mmu_invpcid_gva(struct kvm_vcpu
*vcpu
, gva_t gva
, unsigned long pcid
)
5193 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5194 bool tlb_flush
= false;
5197 if (pcid
== kvm_get_active_pcid(vcpu
)) {
5198 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5202 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
5203 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
) &&
5204 pcid
== kvm_get_pcid(vcpu
, mmu
->prev_roots
[i
].pgd
)) {
5205 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5211 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5213 ++vcpu
->stat
.invlpg
;
5216 * Mappings not reachable via the current cr3 or the prev_roots will be
5217 * synced when switching to that cr3, so nothing needs to be done here
5222 void kvm_configure_mmu(bool enable_tdp
, int tdp_max_root_level
,
5223 int tdp_huge_page_level
)
5225 tdp_enabled
= enable_tdp
;
5226 max_tdp_level
= tdp_max_root_level
;
5229 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5230 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5231 * the kernel is not. But, KVM never creates a page size greater than
5232 * what is used by the kernel for any given HVA, i.e. the kernel's
5233 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5236 max_huge_page_level
= tdp_huge_page_level
;
5237 else if (boot_cpu_has(X86_FEATURE_GBPAGES
))
5238 max_huge_page_level
= PG_LEVEL_1G
;
5240 max_huge_page_level
= PG_LEVEL_2M
;
5242 EXPORT_SYMBOL_GPL(kvm_configure_mmu
);
5244 /* The return value indicates if tlb flush on all vcpus is needed. */
5245 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
5246 struct kvm_memory_slot
*slot
);
5248 /* The caller should hold mmu-lock before calling this function. */
5249 static __always_inline
bool
5250 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5251 slot_level_handler fn
, int start_level
, int end_level
,
5252 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5254 struct slot_rmap_walk_iterator iterator
;
5257 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5258 end_gfn
, &iterator
) {
5260 flush
|= fn(kvm
, iterator
.rmap
, memslot
);
5262 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
5263 if (flush
&& lock_flush_tlb
) {
5264 kvm_flush_remote_tlbs_with_address(kvm
,
5266 iterator
.gfn
- start_gfn
+ 1);
5269 cond_resched_rwlock_write(&kvm
->mmu_lock
);
5273 if (flush
&& lock_flush_tlb
) {
5274 kvm_flush_remote_tlbs_with_address(kvm
, start_gfn
,
5275 end_gfn
- start_gfn
+ 1);
5282 static __always_inline
bool
5283 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5284 slot_level_handler fn
, int start_level
, int end_level
,
5285 bool lock_flush_tlb
)
5287 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5288 end_level
, memslot
->base_gfn
,
5289 memslot
->base_gfn
+ memslot
->npages
- 1,
5293 static __always_inline
bool
5294 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5295 slot_level_handler fn
, bool lock_flush_tlb
)
5297 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
,
5298 PG_LEVEL_4K
, lock_flush_tlb
);
5301 static void free_mmu_pages(struct kvm_mmu
*mmu
)
5303 if (!tdp_enabled
&& mmu
->pae_root
)
5304 set_memory_encrypted((unsigned long)mmu
->pae_root
, 1);
5305 free_page((unsigned long)mmu
->pae_root
);
5306 free_page((unsigned long)mmu
->lm_root
);
5309 static int __kvm_mmu_create(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
5314 mmu
->root_hpa
= INVALID_PAGE
;
5316 mmu
->translate_gpa
= translate_gpa
;
5317 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5318 mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5321 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5322 * while the PDP table is a per-vCPU construct that's allocated at MMU
5323 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5324 * x86_64. Therefore we need to allocate the PDP table in the first
5325 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5326 * generally doesn't use PAE paging and can skip allocating the PDP
5327 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5328 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5329 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5331 if (tdp_enabled
&& kvm_mmu_get_tdp_level(vcpu
) > PT32E_ROOT_LEVEL
)
5334 page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_DMA32
);
5338 mmu
->pae_root
= page_address(page
);
5341 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5342 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5343 * that KVM's writes and the CPU's reads get along. Note, this is
5344 * only necessary when using shadow paging, as 64-bit NPT can get at
5345 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5346 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5349 set_memory_decrypted((unsigned long)mmu
->pae_root
, 1);
5351 WARN_ON_ONCE(shadow_me_mask
);
5353 for (i
= 0; i
< 4; ++i
)
5354 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
5359 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5363 vcpu
->arch
.mmu_pte_list_desc_cache
.kmem_cache
= pte_list_desc_cache
;
5364 vcpu
->arch
.mmu_pte_list_desc_cache
.gfp_zero
= __GFP_ZERO
;
5366 vcpu
->arch
.mmu_page_header_cache
.kmem_cache
= mmu_page_header_cache
;
5367 vcpu
->arch
.mmu_page_header_cache
.gfp_zero
= __GFP_ZERO
;
5369 vcpu
->arch
.mmu_shadow_page_cache
.gfp_zero
= __GFP_ZERO
;
5371 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
5372 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
5374 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5376 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.guest_mmu
);
5380 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.root_mmu
);
5382 goto fail_allocate_root
;
5386 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5390 #define BATCH_ZAP_PAGES 10
5391 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5393 struct kvm_mmu_page
*sp
, *node
;
5394 int nr_zapped
, batch
= 0;
5397 list_for_each_entry_safe_reverse(sp
, node
,
5398 &kvm
->arch
.active_mmu_pages
, link
) {
5400 * No obsolete valid page exists before a newly created page
5401 * since active_mmu_pages is a FIFO list.
5403 if (!is_obsolete_sp(kvm
, sp
))
5407 * Invalid pages should never land back on the list of active
5408 * pages. Skip the bogus page, otherwise we'll get stuck in an
5409 * infinite loop if the page gets put back on the list (again).
5411 if (WARN_ON(sp
->role
.invalid
))
5415 * No need to flush the TLB since we're only zapping shadow
5416 * pages with an obsolete generation number and all vCPUS have
5417 * loaded a new root, i.e. the shadow pages being zapped cannot
5418 * be in active use by the guest.
5420 if (batch
>= BATCH_ZAP_PAGES
&&
5421 cond_resched_rwlock_write(&kvm
->mmu_lock
)) {
5426 if (__kvm_mmu_prepare_zap_page(kvm
, sp
,
5427 &kvm
->arch
.zapped_obsolete_pages
, &nr_zapped
)) {
5434 * Trigger a remote TLB flush before freeing the page tables to ensure
5435 * KVM is not in the middle of a lockless shadow page table walk, which
5436 * may reference the pages.
5438 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5442 * Fast invalidate all shadow pages and use lock-break technique
5443 * to zap obsolete pages.
5445 * It's required when memslot is being deleted or VM is being
5446 * destroyed, in these cases, we should ensure that KVM MMU does
5447 * not use any resource of the being-deleted slot or all slots
5448 * after calling the function.
5450 static void kvm_mmu_zap_all_fast(struct kvm
*kvm
)
5452 lockdep_assert_held(&kvm
->slots_lock
);
5454 write_lock(&kvm
->mmu_lock
);
5455 trace_kvm_mmu_zap_all_fast(kvm
);
5458 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5459 * held for the entire duration of zapping obsolete pages, it's
5460 * impossible for there to be multiple invalid generations associated
5461 * with *valid* shadow pages at any given time, i.e. there is exactly
5462 * one valid generation and (at most) one invalid generation.
5464 kvm
->arch
.mmu_valid_gen
= kvm
->arch
.mmu_valid_gen
? 0 : 1;
5467 * Notify all vcpus to reload its shadow page table and flush TLB.
5468 * Then all vcpus will switch to new shadow page table with the new
5471 * Note: we need to do this under the protection of mmu_lock,
5472 * otherwise, vcpu would purge shadow page but miss tlb flush.
5474 kvm_reload_remote_mmus(kvm
);
5476 kvm_zap_obsolete_pages(kvm
);
5478 if (is_tdp_mmu_enabled(kvm
))
5479 kvm_tdp_mmu_zap_all(kvm
);
5481 write_unlock(&kvm
->mmu_lock
);
5484 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5486 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5489 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5490 struct kvm_memory_slot
*slot
,
5491 struct kvm_page_track_notifier_node
*node
)
5493 kvm_mmu_zap_all_fast(kvm
);
5496 void kvm_mmu_init_vm(struct kvm
*kvm
)
5498 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5500 kvm_mmu_init_tdp_mmu(kvm
);
5502 node
->track_write
= kvm_mmu_pte_write
;
5503 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5504 kvm_page_track_register_notifier(kvm
, node
);
5507 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5509 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5511 kvm_page_track_unregister_notifier(kvm
, node
);
5513 kvm_mmu_uninit_tdp_mmu(kvm
);
5516 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5518 struct kvm_memslots
*slots
;
5519 struct kvm_memory_slot
*memslot
;
5523 write_lock(&kvm
->mmu_lock
);
5524 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5525 slots
= __kvm_memslots(kvm
, i
);
5526 kvm_for_each_memslot(memslot
, slots
) {
5529 start
= max(gfn_start
, memslot
->base_gfn
);
5530 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5534 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5536 KVM_MAX_HUGEPAGE_LEVEL
,
5537 start
, end
- 1, true);
5541 if (is_tdp_mmu_enabled(kvm
)) {
5542 flush
= kvm_tdp_mmu_zap_gfn_range(kvm
, gfn_start
, gfn_end
);
5544 kvm_flush_remote_tlbs(kvm
);
5547 write_unlock(&kvm
->mmu_lock
);
5550 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5551 struct kvm_rmap_head
*rmap_head
,
5552 struct kvm_memory_slot
*slot
)
5554 return __rmap_write_protect(kvm
, rmap_head
, false);
5557 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5558 struct kvm_memory_slot
*memslot
,
5563 write_lock(&kvm
->mmu_lock
);
5564 flush
= slot_handle_level(kvm
, memslot
, slot_rmap_write_protect
,
5565 start_level
, KVM_MAX_HUGEPAGE_LEVEL
, false);
5566 if (is_tdp_mmu_enabled(kvm
))
5567 flush
|= kvm_tdp_mmu_wrprot_slot(kvm
, memslot
, PG_LEVEL_4K
);
5568 write_unlock(&kvm
->mmu_lock
);
5571 * We can flush all the TLBs out of the mmu lock without TLB
5572 * corruption since we just change the spte from writable to
5573 * readonly so that we only need to care the case of changing
5574 * spte from present to present (changing the spte from present
5575 * to nonpresent will flush all the TLBs immediately), in other
5576 * words, the only case we care is mmu_spte_update() where we
5577 * have checked Host-writable | MMU-writable instead of
5578 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5582 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5585 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5586 struct kvm_rmap_head
*rmap_head
,
5587 struct kvm_memory_slot
*slot
)
5590 struct rmap_iterator iter
;
5591 int need_tlb_flush
= 0;
5593 struct kvm_mmu_page
*sp
;
5596 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5597 sp
= sptep_to_sp(sptep
);
5598 pfn
= spte_to_pfn(*sptep
);
5601 * We cannot do huge page mapping for indirect shadow pages,
5602 * which are found on the last rmap (level = 1) when not using
5603 * tdp; such shadow pages are synced with the page table in
5604 * the guest, and the guest page table is using 4K page size
5605 * mapping if the indirect sp has level = 1.
5607 if (sp
->role
.direct
&& !kvm_is_reserved_pfn(pfn
) &&
5608 sp
->role
.level
< kvm_mmu_max_mapping_level(kvm
, slot
, sp
->gfn
,
5609 pfn
, PG_LEVEL_NUM
)) {
5610 pte_list_remove(rmap_head
, sptep
);
5612 if (kvm_available_flush_tlb_with_range())
5613 kvm_flush_remote_tlbs_with_address(kvm
, sp
->gfn
,
5614 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
5622 return need_tlb_flush
;
5625 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5626 const struct kvm_memory_slot
*memslot
)
5628 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5629 struct kvm_memory_slot
*slot
= (struct kvm_memory_slot
*)memslot
;
5631 write_lock(&kvm
->mmu_lock
);
5632 slot_handle_leaf(kvm
, slot
, kvm_mmu_zap_collapsible_spte
, true);
5634 if (is_tdp_mmu_enabled(kvm
))
5635 kvm_tdp_mmu_zap_collapsible_sptes(kvm
, slot
);
5636 write_unlock(&kvm
->mmu_lock
);
5639 void kvm_arch_flush_remote_tlbs_memslot(struct kvm
*kvm
,
5640 struct kvm_memory_slot
*memslot
)
5643 * All current use cases for flushing the TLBs for a specific memslot
5644 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5645 * The interaction between the various operations on memslot must be
5646 * serialized by slots_locks to ensure the TLB flush from one operation
5647 * is observed by any other operation on the same memslot.
5649 lockdep_assert_held(&kvm
->slots_lock
);
5650 kvm_flush_remote_tlbs_with_address(kvm
, memslot
->base_gfn
,
5654 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5655 struct kvm_memory_slot
*memslot
)
5659 write_lock(&kvm
->mmu_lock
);
5660 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5661 if (is_tdp_mmu_enabled(kvm
))
5662 flush
|= kvm_tdp_mmu_clear_dirty_slot(kvm
, memslot
);
5663 write_unlock(&kvm
->mmu_lock
);
5666 * It's also safe to flush TLBs out of mmu lock here as currently this
5667 * function is only used for dirty logging, in which case flushing TLB
5668 * out of mmu lock also guarantees no dirty pages will be lost in
5672 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5675 void kvm_mmu_zap_all(struct kvm
*kvm
)
5677 struct kvm_mmu_page
*sp
, *node
;
5678 LIST_HEAD(invalid_list
);
5681 write_lock(&kvm
->mmu_lock
);
5683 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
5684 if (WARN_ON(sp
->role
.invalid
))
5686 if (__kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
, &ign
))
5688 if (cond_resched_rwlock_write(&kvm
->mmu_lock
))
5692 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5694 if (is_tdp_mmu_enabled(kvm
))
5695 kvm_tdp_mmu_zap_all(kvm
);
5697 write_unlock(&kvm
->mmu_lock
);
5700 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, u64 gen
)
5702 WARN_ON(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
);
5704 gen
&= MMIO_SPTE_GEN_MASK
;
5707 * Generation numbers are incremented in multiples of the number of
5708 * address spaces in order to provide unique generations across all
5709 * address spaces. Strip what is effectively the address space
5710 * modifier prior to checking for a wrap of the MMIO generation so
5711 * that a wrap in any address space is detected.
5713 gen
&= ~((u64
)KVM_ADDRESS_SPACE_NUM
- 1);
5716 * The very rare case: if the MMIO generation number has wrapped,
5717 * zap all shadow pages.
5719 if (unlikely(gen
== 0)) {
5720 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5721 kvm_mmu_zap_all_fast(kvm
);
5725 static unsigned long
5726 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5729 int nr_to_scan
= sc
->nr_to_scan
;
5730 unsigned long freed
= 0;
5732 mutex_lock(&kvm_lock
);
5734 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5736 LIST_HEAD(invalid_list
);
5739 * Never scan more than sc->nr_to_scan VM instances.
5740 * Will not hit this condition practically since we do not try
5741 * to shrink more than one VM and it is very unlikely to see
5742 * !n_used_mmu_pages so many times.
5747 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5748 * here. We may skip a VM instance errorneosly, but we do not
5749 * want to shrink a VM that only started to populate its MMU
5752 if (!kvm
->arch
.n_used_mmu_pages
&&
5753 !kvm_has_zapped_obsolete_pages(kvm
))
5756 idx
= srcu_read_lock(&kvm
->srcu
);
5757 write_lock(&kvm
->mmu_lock
);
5759 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5760 kvm_mmu_commit_zap_page(kvm
,
5761 &kvm
->arch
.zapped_obsolete_pages
);
5765 freed
= kvm_mmu_zap_oldest_mmu_pages(kvm
, sc
->nr_to_scan
);
5768 write_unlock(&kvm
->mmu_lock
);
5769 srcu_read_unlock(&kvm
->srcu
, idx
);
5772 * unfair on small ones
5773 * per-vm shrinkers cry out
5774 * sadness comes quickly
5776 list_move_tail(&kvm
->vm_list
, &vm_list
);
5780 mutex_unlock(&kvm_lock
);
5784 static unsigned long
5785 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5787 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5790 static struct shrinker mmu_shrinker
= {
5791 .count_objects
= mmu_shrink_count
,
5792 .scan_objects
= mmu_shrink_scan
,
5793 .seeks
= DEFAULT_SEEKS
* 10,
5796 static void mmu_destroy_caches(void)
5798 kmem_cache_destroy(pte_list_desc_cache
);
5799 kmem_cache_destroy(mmu_page_header_cache
);
5802 static bool get_nx_auto_mode(void)
5804 /* Return true when CPU has the bug, and mitigations are ON */
5805 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT
) && !cpu_mitigations_off();
5808 static void __set_nx_huge_pages(bool val
)
5810 nx_huge_pages
= itlb_multihit_kvm_mitigation
= val
;
5813 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
)
5815 bool old_val
= nx_huge_pages
;
5818 /* In "auto" mode deploy workaround only if CPU has the bug. */
5819 if (sysfs_streq(val
, "off"))
5821 else if (sysfs_streq(val
, "force"))
5823 else if (sysfs_streq(val
, "auto"))
5824 new_val
= get_nx_auto_mode();
5825 else if (strtobool(val
, &new_val
) < 0)
5828 __set_nx_huge_pages(new_val
);
5830 if (new_val
!= old_val
) {
5833 mutex_lock(&kvm_lock
);
5835 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5836 mutex_lock(&kvm
->slots_lock
);
5837 kvm_mmu_zap_all_fast(kvm
);
5838 mutex_unlock(&kvm
->slots_lock
);
5840 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
5842 mutex_unlock(&kvm_lock
);
5848 int kvm_mmu_module_init(void)
5852 if (nx_huge_pages
== -1)
5853 __set_nx_huge_pages(get_nx_auto_mode());
5856 * MMU roles use union aliasing which is, generally speaking, an
5857 * undefined behavior. However, we supposedly know how compilers behave
5858 * and the current status quo is unlikely to change. Guardians below are
5859 * supposed to let us know if the assumption becomes false.
5861 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role
) != sizeof(u32
));
5862 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role
) != sizeof(u32
));
5863 BUILD_BUG_ON(sizeof(union kvm_mmu_role
) != sizeof(u64
));
5865 kvm_mmu_reset_all_pte_masks();
5867 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5868 sizeof(struct pte_list_desc
),
5869 0, SLAB_ACCOUNT
, NULL
);
5870 if (!pte_list_desc_cache
)
5873 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5874 sizeof(struct kvm_mmu_page
),
5875 0, SLAB_ACCOUNT
, NULL
);
5876 if (!mmu_page_header_cache
)
5879 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5882 ret
= register_shrinker(&mmu_shrinker
);
5889 mmu_destroy_caches();
5894 * Calculate mmu pages needed for kvm.
5896 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm
*kvm
)
5898 unsigned long nr_mmu_pages
;
5899 unsigned long nr_pages
= 0;
5900 struct kvm_memslots
*slots
;
5901 struct kvm_memory_slot
*memslot
;
5904 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5905 slots
= __kvm_memslots(kvm
, i
);
5907 kvm_for_each_memslot(memslot
, slots
)
5908 nr_pages
+= memslot
->npages
;
5911 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5912 nr_mmu_pages
= max(nr_mmu_pages
, KVM_MIN_ALLOC_MMU_PAGES
);
5914 return nr_mmu_pages
;
5917 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5919 kvm_mmu_unload(vcpu
);
5920 free_mmu_pages(&vcpu
->arch
.root_mmu
);
5921 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5922 mmu_free_memory_caches(vcpu
);
5925 void kvm_mmu_module_exit(void)
5927 mmu_destroy_caches();
5928 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5929 unregister_shrinker(&mmu_shrinker
);
5930 mmu_audit_disable();
5933 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
)
5935 unsigned int old_val
;
5938 old_val
= nx_huge_pages_recovery_ratio
;
5939 err
= param_set_uint(val
, kp
);
5943 if (READ_ONCE(nx_huge_pages
) &&
5944 !old_val
&& nx_huge_pages_recovery_ratio
) {
5947 mutex_lock(&kvm_lock
);
5949 list_for_each_entry(kvm
, &vm_list
, vm_list
)
5950 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
5952 mutex_unlock(&kvm_lock
);
5958 static void kvm_recover_nx_lpages(struct kvm
*kvm
)
5961 struct kvm_mmu_page
*sp
;
5963 LIST_HEAD(invalid_list
);
5967 rcu_idx
= srcu_read_lock(&kvm
->srcu
);
5968 write_lock(&kvm
->mmu_lock
);
5970 ratio
= READ_ONCE(nx_huge_pages_recovery_ratio
);
5971 to_zap
= ratio
? DIV_ROUND_UP(kvm
->stat
.nx_lpage_splits
, ratio
) : 0;
5972 for ( ; to_zap
; --to_zap
) {
5973 if (list_empty(&kvm
->arch
.lpage_disallowed_mmu_pages
))
5977 * We use a separate list instead of just using active_mmu_pages
5978 * because the number of lpage_disallowed pages is expected to
5979 * be relatively small compared to the total.
5981 sp
= list_first_entry(&kvm
->arch
.lpage_disallowed_mmu_pages
,
5982 struct kvm_mmu_page
,
5983 lpage_disallowed_link
);
5984 WARN_ON_ONCE(!sp
->lpage_disallowed
);
5985 if (is_tdp_mmu_page(sp
)) {
5986 flush
= kvm_tdp_mmu_zap_sp(kvm
, sp
);
5988 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
5989 WARN_ON_ONCE(sp
->lpage_disallowed
);
5992 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
5993 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
5994 cond_resched_rwlock_write(&kvm
->mmu_lock
);
5998 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
6000 write_unlock(&kvm
->mmu_lock
);
6001 srcu_read_unlock(&kvm
->srcu
, rcu_idx
);
6004 static long get_nx_lpage_recovery_timeout(u64 start_time
)
6006 return READ_ONCE(nx_huge_pages
) && READ_ONCE(nx_huge_pages_recovery_ratio
)
6007 ? start_time
+ 60 * HZ
- get_jiffies_64()
6008 : MAX_SCHEDULE_TIMEOUT
;
6011 static int kvm_nx_lpage_recovery_worker(struct kvm
*kvm
, uintptr_t data
)
6014 long remaining_time
;
6017 start_time
= get_jiffies_64();
6018 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6020 set_current_state(TASK_INTERRUPTIBLE
);
6021 while (!kthread_should_stop() && remaining_time
> 0) {
6022 schedule_timeout(remaining_time
);
6023 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6024 set_current_state(TASK_INTERRUPTIBLE
);
6027 set_current_state(TASK_RUNNING
);
6029 if (kthread_should_stop())
6032 kvm_recover_nx_lpages(kvm
);
6036 int kvm_mmu_post_init_vm(struct kvm
*kvm
)
6040 err
= kvm_vm_create_worker_thread(kvm
, kvm_nx_lpage_recovery_worker
, 0,
6041 "kvm-nx-lpage-recovery",
6042 &kvm
->arch
.nx_lpage_recovery_thread
);
6044 kthread_unpark(kvm
->arch
.nx_lpage_recovery_thread
);
6049 void kvm_mmu_pre_destroy_vm(struct kvm
*kvm
)
6051 if (kvm
->arch
.nx_lpage_recovery_thread
)
6052 kthread_stop(kvm
->arch
.nx_lpage_recovery_thread
);