1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "kvm_cache_regs.h"
22 #include "kvm_emulate.h"
25 #include <linux/kvm_host.h>
26 #include <linux/types.h>
27 #include <linux/string.h>
29 #include <linux/highmem.h>
30 #include <linux/moduleparam.h>
31 #include <linux/export.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/sched/signal.h>
38 #include <linux/uaccess.h>
39 #include <linux/hash.h>
40 #include <linux/kern_levels.h>
41 #include <linux/kthread.h>
44 #include <asm/memtype.h>
45 #include <asm/cmpxchg.h>
46 #include <asm/e820/api.h>
49 #include <asm/kvm_page_track.h>
52 extern bool itlb_multihit_kvm_mitigation
;
54 static int __read_mostly nx_huge_pages
= -1;
55 #ifdef CONFIG_PREEMPT_RT
56 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
57 static uint __read_mostly nx_huge_pages_recovery_ratio
= 0;
59 static uint __read_mostly nx_huge_pages_recovery_ratio
= 60;
62 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
);
63 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
);
65 static struct kernel_param_ops nx_huge_pages_ops
= {
66 .set
= set_nx_huge_pages
,
67 .get
= param_get_bool
,
70 static struct kernel_param_ops nx_huge_pages_recovery_ratio_ops
= {
71 .set
= set_nx_huge_pages_recovery_ratio
,
72 .get
= param_get_uint
,
75 module_param_cb(nx_huge_pages
, &nx_huge_pages_ops
, &nx_huge_pages
, 0644);
76 __MODULE_PARM_TYPE(nx_huge_pages
, "bool");
77 module_param_cb(nx_huge_pages_recovery_ratio
, &nx_huge_pages_recovery_ratio_ops
,
78 &nx_huge_pages_recovery_ratio
, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio
, "uint");
82 * When setting this variable to true it enables Two-Dimensional-Paging
83 * where the hardware walks 2 page tables:
84 * 1. the guest-virtual to guest-physical
85 * 2. while doing 1. it walks guest-physical to host-physical
86 * If the hardware supports that we don't need to do shadow paging.
88 bool tdp_enabled
= false;
90 static int max_page_level __read_mostly
;
94 AUDIT_POST_PAGE_FAULT
,
105 module_param(dbg
, bool, 0644);
107 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
108 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
109 #define MMU_WARN_ON(x) WARN_ON(x)
111 #define pgprintk(x...) do { } while (0)
112 #define rmap_printk(x...) do { } while (0)
113 #define MMU_WARN_ON(x) do { } while (0)
116 #define PTE_PREFETCH_NUM 8
118 #define PT_FIRST_AVAIL_BITS_SHIFT 10
119 #define PT64_SECOND_AVAIL_BITS_SHIFT 54
122 * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
123 * Access Tracking SPTEs.
125 #define SPTE_SPECIAL_MASK (3ULL << 52)
126 #define SPTE_AD_ENABLED_MASK (0ULL << 52)
127 #define SPTE_AD_DISABLED_MASK (1ULL << 52)
128 #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
129 #define SPTE_MMIO_MASK (3ULL << 52)
131 #define PT64_LEVEL_BITS 9
133 #define PT64_LEVEL_SHIFT(level) \
134 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
136 #define PT64_INDEX(address, level)\
137 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
140 #define PT32_LEVEL_BITS 10
142 #define PT32_LEVEL_SHIFT(level) \
143 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
145 #define PT32_LVL_OFFSET_MASK(level) \
146 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
147 * PT32_LEVEL_BITS))) - 1))
149 #define PT32_INDEX(address, level)\
150 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
153 #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
154 #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
156 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
158 #define PT64_LVL_ADDR_MASK(level) \
159 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
160 * PT64_LEVEL_BITS))) - 1))
161 #define PT64_LVL_OFFSET_MASK(level) \
162 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
163 * PT64_LEVEL_BITS))) - 1))
165 #define PT32_BASE_ADDR_MASK PAGE_MASK
166 #define PT32_DIR_BASE_ADDR_MASK \
167 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
168 #define PT32_LVL_ADDR_MASK(level) \
169 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
170 * PT32_LEVEL_BITS))) - 1))
172 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
173 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
175 #define ACC_EXEC_MASK 1
176 #define ACC_WRITE_MASK PT_WRITABLE_MASK
177 #define ACC_USER_MASK PT_USER_MASK
178 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
180 /* The mask for the R/X bits in EPT PTEs */
181 #define PT64_EPT_READABLE_MASK 0x1ull
182 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
184 #include <trace/events/kvm.h>
186 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
187 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
189 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
191 /* make pte_list_desc fit well in cache line */
192 #define PTE_LIST_EXT 3
195 * Return values of handle_mmio_page_fault and mmu.page_fault:
196 * RET_PF_RETRY: let CPU fault again on the address.
197 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
199 * For handle_mmio_page_fault only:
200 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
208 struct pte_list_desc
{
209 u64
*sptes
[PTE_LIST_EXT
];
210 struct pte_list_desc
*more
;
213 struct kvm_shadow_walk_iterator
{
221 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
222 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
224 shadow_walk_okay(&(_walker)); \
225 shadow_walk_next(&(_walker)))
227 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
228 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
229 shadow_walk_okay(&(_walker)); \
230 shadow_walk_next(&(_walker)))
232 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
233 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
234 shadow_walk_okay(&(_walker)) && \
235 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
236 __shadow_walk_next(&(_walker), spte))
238 static struct kmem_cache
*pte_list_desc_cache
;
239 static struct kmem_cache
*mmu_page_header_cache
;
240 static struct percpu_counter kvm_total_used_mmu_pages
;
242 static u64 __read_mostly shadow_nx_mask
;
243 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
244 static u64 __read_mostly shadow_user_mask
;
245 static u64 __read_mostly shadow_accessed_mask
;
246 static u64 __read_mostly shadow_dirty_mask
;
247 static u64 __read_mostly shadow_mmio_mask
;
248 static u64 __read_mostly shadow_mmio_value
;
249 static u64 __read_mostly shadow_mmio_access_mask
;
250 static u64 __read_mostly shadow_present_mask
;
251 static u64 __read_mostly shadow_me_mask
;
254 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
255 * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
258 static u64 __read_mostly shadow_acc_track_mask
;
261 * The mask/shift to use for saving the original R/X bits when marking the PTE
262 * as not-present for access tracking purposes. We do not save the W bit as the
263 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
264 * restored only when a write is attempted to the page.
266 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
267 PT64_EPT_EXECUTABLE_MASK
;
268 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
271 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
272 * to guard against L1TF attacks.
274 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask
;
277 * The number of high-order 1 bits to use in the mask above.
279 static const u64 shadow_nonpresent_or_rsvd_mask_len
= 5;
282 * In some cases, we need to preserve the GFN of a non-present or reserved
283 * SPTE when we usurp the upper five bits of the physical address space to
284 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
285 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
286 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
287 * high and low parts. This mask covers the lower bits of the GFN.
289 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask
;
292 * The number of non-reserved physical address bits irrespective of features
293 * that repurpose legal bits, e.g. MKTME.
295 static u8 __read_mostly shadow_phys_bits
;
297 static void mmu_spte_set(u64
*sptep
, u64 spte
);
298 static bool is_executable_pte(u64 spte
);
299 static union kvm_mmu_page_role
300 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
);
302 #define CREATE_TRACE_POINTS
303 #include "mmutrace.h"
306 static inline bool kvm_available_flush_tlb_with_range(void)
308 return kvm_x86_ops
.tlb_remote_flush_with_range
;
311 static void kvm_flush_remote_tlbs_with_range(struct kvm
*kvm
,
312 struct kvm_tlb_range
*range
)
316 if (range
&& kvm_x86_ops
.tlb_remote_flush_with_range
)
317 ret
= kvm_x86_ops
.tlb_remote_flush_with_range(kvm
, range
);
320 kvm_flush_remote_tlbs(kvm
);
323 static void kvm_flush_remote_tlbs_with_address(struct kvm
*kvm
,
324 u64 start_gfn
, u64 pages
)
326 struct kvm_tlb_range range
;
328 range
.start_gfn
= start_gfn
;
331 kvm_flush_remote_tlbs_with_range(kvm
, &range
);
334 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
, u64 mmio_value
, u64 access_mask
)
336 BUG_ON((u64
)(unsigned)access_mask
!= access_mask
);
337 BUG_ON((mmio_mask
& mmio_value
) != mmio_value
);
338 shadow_mmio_value
= mmio_value
| SPTE_MMIO_MASK
;
339 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
340 shadow_mmio_access_mask
= access_mask
;
342 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
344 static bool is_mmio_spte(u64 spte
)
346 return (spte
& shadow_mmio_mask
) == shadow_mmio_value
;
349 static inline bool sp_ad_disabled(struct kvm_mmu_page
*sp
)
351 return sp
->role
.ad_disabled
;
354 static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu
*vcpu
)
357 * When using the EPT page-modification log, the GPAs in the log
358 * would come from L2 rather than L1. Therefore, we need to rely
359 * on write protection to record dirty pages. This also bypasses
360 * PML, since writes now result in a vmexit.
362 return vcpu
->arch
.mmu
== &vcpu
->arch
.guest_mmu
;
365 static inline bool spte_ad_enabled(u64 spte
)
367 MMU_WARN_ON(is_mmio_spte(spte
));
368 return (spte
& SPTE_SPECIAL_MASK
) != SPTE_AD_DISABLED_MASK
;
371 static inline bool spte_ad_need_write_protect(u64 spte
)
373 MMU_WARN_ON(is_mmio_spte(spte
));
374 return (spte
& SPTE_SPECIAL_MASK
) != SPTE_AD_ENABLED_MASK
;
377 static bool is_nx_huge_page_enabled(void)
379 return READ_ONCE(nx_huge_pages
);
382 static inline u64
spte_shadow_accessed_mask(u64 spte
)
384 MMU_WARN_ON(is_mmio_spte(spte
));
385 return spte_ad_enabled(spte
) ? shadow_accessed_mask
: 0;
388 static inline u64
spte_shadow_dirty_mask(u64 spte
)
390 MMU_WARN_ON(is_mmio_spte(spte
));
391 return spte_ad_enabled(spte
) ? shadow_dirty_mask
: 0;
394 static inline bool is_access_track_spte(u64 spte
)
396 return !spte_ad_enabled(spte
) && (spte
& shadow_acc_track_mask
) == 0;
400 * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
401 * the memslots generation and is derived as follows:
403 * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
404 * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61
406 * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
407 * the MMIO generation number, as doing so would require stealing a bit from
408 * the "real" generation number and thus effectively halve the maximum number
409 * of MMIO generations that can be handled before encountering a wrap (which
410 * requires a full MMU zap). The flag is instead explicitly queried when
411 * checking for MMIO spte cache hits.
413 #define MMIO_SPTE_GEN_MASK GENMASK_ULL(17, 0)
415 #define MMIO_SPTE_GEN_LOW_START 3
416 #define MMIO_SPTE_GEN_LOW_END 11
417 #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
418 MMIO_SPTE_GEN_LOW_START)
420 #define MMIO_SPTE_GEN_HIGH_START PT64_SECOND_AVAIL_BITS_SHIFT
421 #define MMIO_SPTE_GEN_HIGH_END 62
422 #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
423 MMIO_SPTE_GEN_HIGH_START)
425 static u64
generation_mmio_spte_mask(u64 gen
)
429 WARN_ON(gen
& ~MMIO_SPTE_GEN_MASK
);
430 BUILD_BUG_ON((MMIO_SPTE_GEN_HIGH_MASK
| MMIO_SPTE_GEN_LOW_MASK
) & SPTE_SPECIAL_MASK
);
432 mask
= (gen
<< MMIO_SPTE_GEN_LOW_START
) & MMIO_SPTE_GEN_LOW_MASK
;
433 mask
|= (gen
<< MMIO_SPTE_GEN_HIGH_START
) & MMIO_SPTE_GEN_HIGH_MASK
;
437 static u64
get_mmio_spte_generation(u64 spte
)
441 gen
= (spte
& MMIO_SPTE_GEN_LOW_MASK
) >> MMIO_SPTE_GEN_LOW_START
;
442 gen
|= (spte
& MMIO_SPTE_GEN_HIGH_MASK
) >> MMIO_SPTE_GEN_HIGH_START
;
446 static u64
make_mmio_spte(struct kvm_vcpu
*vcpu
, u64 gfn
, unsigned int access
)
449 u64 gen
= kvm_vcpu_memslots(vcpu
)->generation
& MMIO_SPTE_GEN_MASK
;
450 u64 mask
= generation_mmio_spte_mask(gen
);
451 u64 gpa
= gfn
<< PAGE_SHIFT
;
453 access
&= shadow_mmio_access_mask
;
454 mask
|= shadow_mmio_value
| access
;
455 mask
|= gpa
| shadow_nonpresent_or_rsvd_mask
;
456 mask
|= (gpa
& shadow_nonpresent_or_rsvd_mask
)
457 << shadow_nonpresent_or_rsvd_mask_len
;
462 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
465 u64 mask
= make_mmio_spte(vcpu
, gfn
, access
);
466 unsigned int gen
= get_mmio_spte_generation(mask
);
468 access
= mask
& ACC_ALL
;
470 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
471 mmu_spte_set(sptep
, mask
);
474 static gfn_t
get_mmio_spte_gfn(u64 spte
)
476 u64 gpa
= spte
& shadow_nonpresent_or_rsvd_lower_gfn_mask
;
478 gpa
|= (spte
>> shadow_nonpresent_or_rsvd_mask_len
)
479 & shadow_nonpresent_or_rsvd_mask
;
481 return gpa
>> PAGE_SHIFT
;
484 static unsigned get_mmio_spte_access(u64 spte
)
486 return spte
& shadow_mmio_access_mask
;
489 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
490 kvm_pfn_t pfn
, unsigned int access
)
492 if (unlikely(is_noslot_pfn(pfn
))) {
493 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
500 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
502 u64 kvm_gen
, spte_gen
, gen
;
504 gen
= kvm_vcpu_memslots(vcpu
)->generation
;
505 if (unlikely(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
))
508 kvm_gen
= gen
& MMIO_SPTE_GEN_MASK
;
509 spte_gen
= get_mmio_spte_generation(spte
);
511 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
512 return likely(kvm_gen
== spte_gen
);
516 * Sets the shadow PTE masks used by the MMU.
519 * - Setting either @accessed_mask or @dirty_mask requires setting both
520 * - At least one of @accessed_mask or @acc_track_mask must be set
522 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
523 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
524 u64 acc_track_mask
, u64 me_mask
)
526 BUG_ON(!dirty_mask
!= !accessed_mask
);
527 BUG_ON(!accessed_mask
&& !acc_track_mask
);
528 BUG_ON(acc_track_mask
& SPTE_SPECIAL_MASK
);
530 shadow_user_mask
= user_mask
;
531 shadow_accessed_mask
= accessed_mask
;
532 shadow_dirty_mask
= dirty_mask
;
533 shadow_nx_mask
= nx_mask
;
534 shadow_x_mask
= x_mask
;
535 shadow_present_mask
= p_mask
;
536 shadow_acc_track_mask
= acc_track_mask
;
537 shadow_me_mask
= me_mask
;
539 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
541 static u8
kvm_get_shadow_phys_bits(void)
544 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
545 * in CPU detection code, but the processor treats those reduced bits as
546 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
547 * the physical address bits reported by CPUID.
549 if (likely(boot_cpu_data
.extended_cpuid_level
>= 0x80000008))
550 return cpuid_eax(0x80000008) & 0xff;
553 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
554 * custom CPUID. Proceed with whatever the kernel found since these features
555 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
557 return boot_cpu_data
.x86_phys_bits
;
560 static void kvm_mmu_reset_all_pte_masks(void)
564 shadow_user_mask
= 0;
565 shadow_accessed_mask
= 0;
566 shadow_dirty_mask
= 0;
569 shadow_mmio_mask
= 0;
570 shadow_present_mask
= 0;
571 shadow_acc_track_mask
= 0;
573 shadow_phys_bits
= kvm_get_shadow_phys_bits();
576 * If the CPU has 46 or less physical address bits, then set an
577 * appropriate mask to guard against L1TF attacks. Otherwise, it is
578 * assumed that the CPU is not vulnerable to L1TF.
580 * Some Intel CPUs address the L1 cache using more PA bits than are
581 * reported by CPUID. Use the PA width of the L1 cache when possible
582 * to achieve more effective mitigation, e.g. if system RAM overlaps
583 * the most significant bits of legal physical address space.
585 shadow_nonpresent_or_rsvd_mask
= 0;
586 low_phys_bits
= boot_cpu_data
.x86_cache_bits
;
587 if (boot_cpu_data
.x86_cache_bits
<
588 52 - shadow_nonpresent_or_rsvd_mask_len
) {
589 shadow_nonpresent_or_rsvd_mask
=
590 rsvd_bits(boot_cpu_data
.x86_cache_bits
-
591 shadow_nonpresent_or_rsvd_mask_len
,
592 boot_cpu_data
.x86_cache_bits
- 1);
593 low_phys_bits
-= shadow_nonpresent_or_rsvd_mask_len
;
595 WARN_ON_ONCE(boot_cpu_has_bug(X86_BUG_L1TF
));
597 shadow_nonpresent_or_rsvd_lower_gfn_mask
=
598 GENMASK_ULL(low_phys_bits
- 1, PAGE_SHIFT
);
601 static int is_cpuid_PSE36(void)
606 static int is_nx(struct kvm_vcpu
*vcpu
)
608 return vcpu
->arch
.efer
& EFER_NX
;
611 static int is_shadow_present_pte(u64 pte
)
613 return (pte
!= 0) && !is_mmio_spte(pte
);
616 static int is_large_pte(u64 pte
)
618 return pte
& PT_PAGE_SIZE_MASK
;
621 static int is_last_spte(u64 pte
, int level
)
623 if (level
== PT_PAGE_TABLE_LEVEL
)
625 if (is_large_pte(pte
))
630 static bool is_executable_pte(u64 spte
)
632 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
635 static kvm_pfn_t
spte_to_pfn(u64 pte
)
637 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
640 static gfn_t
pse36_gfn_delta(u32 gpte
)
642 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
644 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
648 static void __set_spte(u64
*sptep
, u64 spte
)
650 WRITE_ONCE(*sptep
, spte
);
653 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
655 WRITE_ONCE(*sptep
, spte
);
658 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
660 return xchg(sptep
, spte
);
663 static u64
__get_spte_lockless(u64
*sptep
)
665 return READ_ONCE(*sptep
);
676 static void count_spte_clear(u64
*sptep
, u64 spte
)
678 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
680 if (is_shadow_present_pte(spte
))
683 /* Ensure the spte is completely set before we increase the count */
685 sp
->clear_spte_count
++;
688 static void __set_spte(u64
*sptep
, u64 spte
)
690 union split_spte
*ssptep
, sspte
;
692 ssptep
= (union split_spte
*)sptep
;
693 sspte
= (union split_spte
)spte
;
695 ssptep
->spte_high
= sspte
.spte_high
;
698 * If we map the spte from nonpresent to present, We should store
699 * the high bits firstly, then set present bit, so cpu can not
700 * fetch this spte while we are setting the spte.
704 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
707 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
709 union split_spte
*ssptep
, sspte
;
711 ssptep
= (union split_spte
*)sptep
;
712 sspte
= (union split_spte
)spte
;
714 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
717 * If we map the spte from present to nonpresent, we should clear
718 * present bit firstly to avoid vcpu fetch the old high bits.
722 ssptep
->spte_high
= sspte
.spte_high
;
723 count_spte_clear(sptep
, spte
);
726 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
728 union split_spte
*ssptep
, sspte
, orig
;
730 ssptep
= (union split_spte
*)sptep
;
731 sspte
= (union split_spte
)spte
;
733 /* xchg acts as a barrier before the setting of the high bits */
734 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
735 orig
.spte_high
= ssptep
->spte_high
;
736 ssptep
->spte_high
= sspte
.spte_high
;
737 count_spte_clear(sptep
, spte
);
743 * The idea using the light way get the spte on x86_32 guest is from
744 * gup_get_pte (mm/gup.c).
746 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
747 * coalesces them and we are running out of the MMU lock. Therefore
748 * we need to protect against in-progress updates of the spte.
750 * Reading the spte while an update is in progress may get the old value
751 * for the high part of the spte. The race is fine for a present->non-present
752 * change (because the high part of the spte is ignored for non-present spte),
753 * but for a present->present change we must reread the spte.
755 * All such changes are done in two steps (present->non-present and
756 * non-present->present), hence it is enough to count the number of
757 * present->non-present updates: if it changed while reading the spte,
758 * we might have hit the race. This is done using clear_spte_count.
760 static u64
__get_spte_lockless(u64
*sptep
)
762 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
763 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
767 count
= sp
->clear_spte_count
;
770 spte
.spte_low
= orig
->spte_low
;
773 spte
.spte_high
= orig
->spte_high
;
776 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
777 count
!= sp
->clear_spte_count
))
784 static bool spte_can_locklessly_be_made_writable(u64 spte
)
786 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
787 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
790 static bool spte_has_volatile_bits(u64 spte
)
792 if (!is_shadow_present_pte(spte
))
796 * Always atomically update spte if it can be updated
797 * out of mmu-lock, it can ensure dirty bit is not lost,
798 * also, it can help us to get a stable is_writable_pte()
799 * to ensure tlb flush is not missed.
801 if (spte_can_locklessly_be_made_writable(spte
) ||
802 is_access_track_spte(spte
))
805 if (spte_ad_enabled(spte
)) {
806 if ((spte
& shadow_accessed_mask
) == 0 ||
807 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
814 static bool is_accessed_spte(u64 spte
)
816 u64 accessed_mask
= spte_shadow_accessed_mask(spte
);
818 return accessed_mask
? spte
& accessed_mask
819 : !is_access_track_spte(spte
);
822 static bool is_dirty_spte(u64 spte
)
824 u64 dirty_mask
= spte_shadow_dirty_mask(spte
);
826 return dirty_mask
? spte
& dirty_mask
: spte
& PT_WRITABLE_MASK
;
829 /* Rules for using mmu_spte_set:
830 * Set the sptep from nonpresent to present.
831 * Note: the sptep being assigned *must* be either not present
832 * or in a state where the hardware will not attempt to update
835 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
837 WARN_ON(is_shadow_present_pte(*sptep
));
838 __set_spte(sptep
, new_spte
);
842 * Update the SPTE (excluding the PFN), but do not track changes in its
843 * accessed/dirty status.
845 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
847 u64 old_spte
= *sptep
;
849 WARN_ON(!is_shadow_present_pte(new_spte
));
851 if (!is_shadow_present_pte(old_spte
)) {
852 mmu_spte_set(sptep
, new_spte
);
856 if (!spte_has_volatile_bits(old_spte
))
857 __update_clear_spte_fast(sptep
, new_spte
);
859 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
861 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
866 /* Rules for using mmu_spte_update:
867 * Update the state bits, it means the mapped pfn is not changed.
869 * Whenever we overwrite a writable spte with a read-only one we
870 * should flush remote TLBs. Otherwise rmap_write_protect
871 * will find a read-only spte, even though the writable spte
872 * might be cached on a CPU's TLB, the return value indicates this
875 * Returns true if the TLB needs to be flushed
877 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
880 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
882 if (!is_shadow_present_pte(old_spte
))
886 * For the spte updated out of mmu-lock is safe, since
887 * we always atomically update it, see the comments in
888 * spte_has_volatile_bits().
890 if (spte_can_locklessly_be_made_writable(old_spte
) &&
891 !is_writable_pte(new_spte
))
895 * Flush TLB when accessed/dirty states are changed in the page tables,
896 * to guarantee consistency between TLB and page tables.
899 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
901 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
904 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
906 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
913 * Rules for using mmu_spte_clear_track_bits:
914 * It sets the sptep from present to nonpresent, and track the
915 * state bits, it is used to clear the last level sptep.
916 * Returns non-zero if the PTE was previously valid.
918 static int mmu_spte_clear_track_bits(u64
*sptep
)
921 u64 old_spte
= *sptep
;
923 if (!spte_has_volatile_bits(old_spte
))
924 __update_clear_spte_fast(sptep
, 0ull);
926 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
928 if (!is_shadow_present_pte(old_spte
))
931 pfn
= spte_to_pfn(old_spte
);
934 * KVM does not hold the refcount of the page used by
935 * kvm mmu, before reclaiming the page, we should
936 * unmap it from mmu first.
938 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
940 if (is_accessed_spte(old_spte
))
941 kvm_set_pfn_accessed(pfn
);
943 if (is_dirty_spte(old_spte
))
944 kvm_set_pfn_dirty(pfn
);
950 * Rules for using mmu_spte_clear_no_track:
951 * Directly clear spte without caring the state bits of sptep,
952 * it is used to set the upper level spte.
954 static void mmu_spte_clear_no_track(u64
*sptep
)
956 __update_clear_spte_fast(sptep
, 0ull);
959 static u64
mmu_spte_get_lockless(u64
*sptep
)
961 return __get_spte_lockless(sptep
);
964 static u64
mark_spte_for_access_track(u64 spte
)
966 if (spte_ad_enabled(spte
))
967 return spte
& ~shadow_accessed_mask
;
969 if (is_access_track_spte(spte
))
973 * Making an Access Tracking PTE will result in removal of write access
974 * from the PTE. So, verify that we will be able to restore the write
975 * access in the fast page fault path later on.
977 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
978 !spte_can_locklessly_be_made_writable(spte
),
979 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
981 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
982 shadow_acc_track_saved_bits_shift
),
983 "kvm: Access Tracking saved bit locations are not zero\n");
985 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
986 shadow_acc_track_saved_bits_shift
;
987 spte
&= ~shadow_acc_track_mask
;
992 /* Restore an acc-track PTE back to a regular PTE */
993 static u64
restore_acc_track_spte(u64 spte
)
996 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
997 & shadow_acc_track_saved_bits_mask
;
999 WARN_ON_ONCE(spte_ad_enabled(spte
));
1000 WARN_ON_ONCE(!is_access_track_spte(spte
));
1002 new_spte
&= ~shadow_acc_track_mask
;
1003 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
1004 shadow_acc_track_saved_bits_shift
);
1005 new_spte
|= saved_bits
;
1010 /* Returns the Accessed status of the PTE and resets it at the same time. */
1011 static bool mmu_spte_age(u64
*sptep
)
1013 u64 spte
= mmu_spte_get_lockless(sptep
);
1015 if (!is_accessed_spte(spte
))
1018 if (spte_ad_enabled(spte
)) {
1019 clear_bit((ffs(shadow_accessed_mask
) - 1),
1020 (unsigned long *)sptep
);
1023 * Capture the dirty status of the page, so that it doesn't get
1024 * lost when the SPTE is marked for access tracking.
1026 if (is_writable_pte(spte
))
1027 kvm_set_pfn_dirty(spte_to_pfn(spte
));
1029 spte
= mark_spte_for_access_track(spte
);
1030 mmu_spte_update_no_track(sptep
, spte
);
1036 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
1039 * Prevent page table teardown by making any free-er wait during
1040 * kvm_flush_remote_tlbs() IPI to all active vcpus.
1042 local_irq_disable();
1045 * Make sure a following spte read is not reordered ahead of the write
1048 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
1051 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
1054 * Make sure the write to vcpu->mode is not reordered in front of
1055 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
1056 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
1058 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
1062 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
1063 struct kmem_cache
*base_cache
, int min
)
1067 if (cache
->nobjs
>= min
)
1069 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
1070 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL_ACCOUNT
);
1072 return cache
->nobjs
>= min
? 0 : -ENOMEM
;
1073 cache
->objects
[cache
->nobjs
++] = obj
;
1078 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
1080 return cache
->nobjs
;
1083 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
1084 struct kmem_cache
*cache
)
1087 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
1090 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
1095 if (cache
->nobjs
>= min
)
1097 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
1098 page
= (void *)__get_free_page(GFP_KERNEL_ACCOUNT
);
1100 return cache
->nobjs
>= min
? 0 : -ENOMEM
;
1101 cache
->objects
[cache
->nobjs
++] = page
;
1106 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
1109 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
1112 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
1116 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
1117 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
1120 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
1123 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
1124 mmu_page_header_cache
, 4);
1129 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
1131 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
1132 pte_list_desc_cache
);
1133 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
1134 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
1135 mmu_page_header_cache
);
1138 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
1143 p
= mc
->objects
[--mc
->nobjs
];
1147 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
1149 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
1152 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
1154 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
1157 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
1159 if (!sp
->role
.direct
)
1160 return sp
->gfns
[index
];
1162 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
1165 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
1167 if (!sp
->role
.direct
) {
1168 sp
->gfns
[index
] = gfn
;
1172 if (WARN_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
)))
1173 pr_err_ratelimited("gfn mismatch under direct page %llx "
1174 "(expected %llx, got %llx)\n",
1176 kvm_mmu_page_get_gfn(sp
, index
), gfn
);
1180 * Return the pointer to the large page information for a given gfn,
1181 * handling slots that are not large page aligned.
1183 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
1184 struct kvm_memory_slot
*slot
,
1189 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1190 return &slot
->arch
.lpage_info
[level
- 2][idx
];
1193 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
1194 gfn_t gfn
, int count
)
1196 struct kvm_lpage_info
*linfo
;
1199 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1200 linfo
= lpage_info_slot(gfn
, slot
, i
);
1201 linfo
->disallow_lpage
+= count
;
1202 WARN_ON(linfo
->disallow_lpage
< 0);
1206 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
1208 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
1211 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
1213 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
1216 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1218 struct kvm_memslots
*slots
;
1219 struct kvm_memory_slot
*slot
;
1222 kvm
->arch
.indirect_shadow_pages
++;
1224 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1225 slot
= __gfn_to_memslot(slots
, gfn
);
1227 /* the non-leaf shadow pages are keeping readonly. */
1228 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1229 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
1230 KVM_PAGE_TRACK_WRITE
);
1232 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
1235 static void account_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1237 if (sp
->lpage_disallowed
)
1240 ++kvm
->stat
.nx_lpage_splits
;
1241 list_add_tail(&sp
->lpage_disallowed_link
,
1242 &kvm
->arch
.lpage_disallowed_mmu_pages
);
1243 sp
->lpage_disallowed
= true;
1246 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1248 struct kvm_memslots
*slots
;
1249 struct kvm_memory_slot
*slot
;
1252 kvm
->arch
.indirect_shadow_pages
--;
1254 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1255 slot
= __gfn_to_memslot(slots
, gfn
);
1256 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1257 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
1258 KVM_PAGE_TRACK_WRITE
);
1260 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
1263 static void unaccount_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1265 --kvm
->stat
.nx_lpage_splits
;
1266 sp
->lpage_disallowed
= false;
1267 list_del(&sp
->lpage_disallowed_link
);
1270 static struct kvm_memory_slot
*
1271 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1274 struct kvm_memory_slot
*slot
;
1276 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1277 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1279 if (no_dirty_log
&& slot
->dirty_bitmap
)
1286 * About rmap_head encoding:
1288 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1289 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1290 * pte_list_desc containing more mappings.
1294 * Returns the number of pointers in the rmap chain, not counting the new one.
1296 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1297 struct kvm_rmap_head
*rmap_head
)
1299 struct pte_list_desc
*desc
;
1302 if (!rmap_head
->val
) {
1303 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1304 rmap_head
->val
= (unsigned long)spte
;
1305 } else if (!(rmap_head
->val
& 1)) {
1306 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1307 desc
= mmu_alloc_pte_list_desc(vcpu
);
1308 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1309 desc
->sptes
[1] = spte
;
1310 rmap_head
->val
= (unsigned long)desc
| 1;
1313 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1314 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1315 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1317 count
+= PTE_LIST_EXT
;
1319 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1320 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1323 for (i
= 0; desc
->sptes
[i
]; ++i
)
1325 desc
->sptes
[i
] = spte
;
1331 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1332 struct pte_list_desc
*desc
, int i
,
1333 struct pte_list_desc
*prev_desc
)
1337 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1339 desc
->sptes
[i
] = desc
->sptes
[j
];
1340 desc
->sptes
[j
] = NULL
;
1343 if (!prev_desc
&& !desc
->more
)
1347 prev_desc
->more
= desc
->more
;
1349 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1350 mmu_free_pte_list_desc(desc
);
1353 static void __pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1355 struct pte_list_desc
*desc
;
1356 struct pte_list_desc
*prev_desc
;
1359 if (!rmap_head
->val
) {
1360 pr_err("%s: %p 0->BUG\n", __func__
, spte
);
1362 } else if (!(rmap_head
->val
& 1)) {
1363 rmap_printk("%s: %p 1->0\n", __func__
, spte
);
1364 if ((u64
*)rmap_head
->val
!= spte
) {
1365 pr_err("%s: %p 1->BUG\n", __func__
, spte
);
1370 rmap_printk("%s: %p many->many\n", __func__
, spte
);
1371 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1374 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1375 if (desc
->sptes
[i
] == spte
) {
1376 pte_list_desc_remove_entry(rmap_head
,
1377 desc
, i
, prev_desc
);
1384 pr_err("%s: %p many->many\n", __func__
, spte
);
1389 static void pte_list_remove(struct kvm_rmap_head
*rmap_head
, u64
*sptep
)
1391 mmu_spte_clear_track_bits(sptep
);
1392 __pte_list_remove(sptep
, rmap_head
);
1395 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1396 struct kvm_memory_slot
*slot
)
1400 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1401 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1404 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1405 struct kvm_mmu_page
*sp
)
1407 struct kvm_memslots
*slots
;
1408 struct kvm_memory_slot
*slot
;
1410 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1411 slot
= __gfn_to_memslot(slots
, gfn
);
1412 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1415 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1417 struct kvm_mmu_memory_cache
*cache
;
1419 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1420 return mmu_memory_cache_free_objects(cache
);
1423 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1425 struct kvm_mmu_page
*sp
;
1426 struct kvm_rmap_head
*rmap_head
;
1428 sp
= page_header(__pa(spte
));
1429 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1430 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1431 return pte_list_add(vcpu
, spte
, rmap_head
);
1434 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1436 struct kvm_mmu_page
*sp
;
1438 struct kvm_rmap_head
*rmap_head
;
1440 sp
= page_header(__pa(spte
));
1441 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1442 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1443 __pte_list_remove(spte
, rmap_head
);
1447 * Used by the following functions to iterate through the sptes linked by a
1448 * rmap. All fields are private and not assumed to be used outside.
1450 struct rmap_iterator
{
1451 /* private fields */
1452 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1453 int pos
; /* index of the sptep */
1457 * Iteration must be started by this function. This should also be used after
1458 * removing/dropping sptes from the rmap link because in such cases the
1459 * information in the iterator may not be valid.
1461 * Returns sptep if found, NULL otherwise.
1463 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1464 struct rmap_iterator
*iter
)
1468 if (!rmap_head
->val
)
1471 if (!(rmap_head
->val
& 1)) {
1473 sptep
= (u64
*)rmap_head
->val
;
1477 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1479 sptep
= iter
->desc
->sptes
[iter
->pos
];
1481 BUG_ON(!is_shadow_present_pte(*sptep
));
1486 * Must be used with a valid iterator: e.g. after rmap_get_first().
1488 * Returns sptep if found, NULL otherwise.
1490 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1495 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1497 sptep
= iter
->desc
->sptes
[iter
->pos
];
1502 iter
->desc
= iter
->desc
->more
;
1506 /* desc->sptes[0] cannot be NULL */
1507 sptep
= iter
->desc
->sptes
[iter
->pos
];
1514 BUG_ON(!is_shadow_present_pte(*sptep
));
1518 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1519 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1520 _spte_; _spte_ = rmap_get_next(_iter_))
1522 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1524 if (mmu_spte_clear_track_bits(sptep
))
1525 rmap_remove(kvm
, sptep
);
1529 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1531 if (is_large_pte(*sptep
)) {
1532 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1533 PT_PAGE_TABLE_LEVEL
);
1534 drop_spte(kvm
, sptep
);
1542 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1544 if (__drop_large_spte(vcpu
->kvm
, sptep
)) {
1545 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
1547 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1548 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1553 * Write-protect on the specified @sptep, @pt_protect indicates whether
1554 * spte write-protection is caused by protecting shadow page table.
1556 * Note: write protection is difference between dirty logging and spte
1558 * - for dirty logging, the spte can be set to writable at anytime if
1559 * its dirty bitmap is properly set.
1560 * - for spte protection, the spte can be writable only after unsync-ing
1563 * Return true if tlb need be flushed.
1565 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1569 if (!is_writable_pte(spte
) &&
1570 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1573 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1576 spte
&= ~SPTE_MMU_WRITEABLE
;
1577 spte
= spte
& ~PT_WRITABLE_MASK
;
1579 return mmu_spte_update(sptep
, spte
);
1582 static bool __rmap_write_protect(struct kvm
*kvm
,
1583 struct kvm_rmap_head
*rmap_head
,
1587 struct rmap_iterator iter
;
1590 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1591 flush
|= spte_write_protect(sptep
, pt_protect
);
1596 static bool spte_clear_dirty(u64
*sptep
)
1600 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1602 MMU_WARN_ON(!spte_ad_enabled(spte
));
1603 spte
&= ~shadow_dirty_mask
;
1604 return mmu_spte_update(sptep
, spte
);
1607 static bool spte_wrprot_for_clear_dirty(u64
*sptep
)
1609 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1610 (unsigned long *)sptep
);
1611 if (was_writable
&& !spte_ad_enabled(*sptep
))
1612 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1614 return was_writable
;
1618 * Gets the GFN ready for another round of dirty logging by clearing the
1619 * - D bit on ad-enabled SPTEs, and
1620 * - W bit on ad-disabled SPTEs.
1621 * Returns true iff any D or W bits were cleared.
1623 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1626 struct rmap_iterator iter
;
1629 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1630 if (spte_ad_need_write_protect(*sptep
))
1631 flush
|= spte_wrprot_for_clear_dirty(sptep
);
1633 flush
|= spte_clear_dirty(sptep
);
1638 static bool spte_set_dirty(u64
*sptep
)
1642 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1645 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1646 * do not bother adding back write access to pages marked
1647 * SPTE_AD_WRPROT_ONLY_MASK.
1649 spte
|= shadow_dirty_mask
;
1651 return mmu_spte_update(sptep
, spte
);
1654 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1657 struct rmap_iterator iter
;
1660 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1661 if (spte_ad_enabled(*sptep
))
1662 flush
|= spte_set_dirty(sptep
);
1668 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1669 * @kvm: kvm instance
1670 * @slot: slot to protect
1671 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1672 * @mask: indicates which pages we should protect
1674 * Used when we do not need to care about huge page mappings: e.g. during dirty
1675 * logging we do not have any such mappings.
1677 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1678 struct kvm_memory_slot
*slot
,
1679 gfn_t gfn_offset
, unsigned long mask
)
1681 struct kvm_rmap_head
*rmap_head
;
1684 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1685 PT_PAGE_TABLE_LEVEL
, slot
);
1686 __rmap_write_protect(kvm
, rmap_head
, false);
1688 /* clear the first set bit */
1694 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1695 * protect the page if the D-bit isn't supported.
1696 * @kvm: kvm instance
1697 * @slot: slot to clear D-bit
1698 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1699 * @mask: indicates which pages we should clear D-bit
1701 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1703 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1704 struct kvm_memory_slot
*slot
,
1705 gfn_t gfn_offset
, unsigned long mask
)
1707 struct kvm_rmap_head
*rmap_head
;
1710 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1711 PT_PAGE_TABLE_LEVEL
, slot
);
1712 __rmap_clear_dirty(kvm
, rmap_head
);
1714 /* clear the first set bit */
1718 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1721 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1724 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1725 * enable dirty logging for them.
1727 * Used when we do not need to care about huge page mappings: e.g. during dirty
1728 * logging we do not have any such mappings.
1730 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1731 struct kvm_memory_slot
*slot
,
1732 gfn_t gfn_offset
, unsigned long mask
)
1734 if (kvm_x86_ops
.enable_log_dirty_pt_masked
)
1735 kvm_x86_ops
.enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1738 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1742 * kvm_arch_write_log_dirty - emulate dirty page logging
1743 * @vcpu: Guest mode vcpu
1745 * Emulate arch specific page modification logging for the
1748 int kvm_arch_write_log_dirty(struct kvm_vcpu
*vcpu
)
1750 if (kvm_x86_ops
.write_log_dirty
)
1751 return kvm_x86_ops
.write_log_dirty(vcpu
);
1756 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1757 struct kvm_memory_slot
*slot
, u64 gfn
)
1759 struct kvm_rmap_head
*rmap_head
;
1761 bool write_protected
= false;
1763 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1764 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1765 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1768 return write_protected
;
1771 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1773 struct kvm_memory_slot
*slot
;
1775 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1776 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1779 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1782 struct rmap_iterator iter
;
1785 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1786 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1788 pte_list_remove(rmap_head
, sptep
);
1795 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1796 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1799 return kvm_zap_rmapp(kvm
, rmap_head
);
1802 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1803 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1807 struct rmap_iterator iter
;
1810 pte_t
*ptep
= (pte_t
*)data
;
1813 WARN_ON(pte_huge(*ptep
));
1814 new_pfn
= pte_pfn(*ptep
);
1817 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1818 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1819 sptep
, *sptep
, gfn
, level
);
1823 if (pte_write(*ptep
)) {
1824 pte_list_remove(rmap_head
, sptep
);
1827 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1828 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1830 new_spte
&= ~PT_WRITABLE_MASK
;
1831 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1833 new_spte
= mark_spte_for_access_track(new_spte
);
1835 mmu_spte_clear_track_bits(sptep
);
1836 mmu_spte_set(sptep
, new_spte
);
1840 if (need_flush
&& kvm_available_flush_tlb_with_range()) {
1841 kvm_flush_remote_tlbs_with_address(kvm
, gfn
, 1);
1848 struct slot_rmap_walk_iterator
{
1850 struct kvm_memory_slot
*slot
;
1856 /* output fields. */
1858 struct kvm_rmap_head
*rmap
;
1861 /* private field. */
1862 struct kvm_rmap_head
*end_rmap
;
1866 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1868 iterator
->level
= level
;
1869 iterator
->gfn
= iterator
->start_gfn
;
1870 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1871 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1876 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1877 struct kvm_memory_slot
*slot
, int start_level
,
1878 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1880 iterator
->slot
= slot
;
1881 iterator
->start_level
= start_level
;
1882 iterator
->end_level
= end_level
;
1883 iterator
->start_gfn
= start_gfn
;
1884 iterator
->end_gfn
= end_gfn
;
1886 rmap_walk_init_level(iterator
, iterator
->start_level
);
1889 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1891 return !!iterator
->rmap
;
1894 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1896 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1897 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1901 if (++iterator
->level
> iterator
->end_level
) {
1902 iterator
->rmap
= NULL
;
1906 rmap_walk_init_level(iterator
, iterator
->level
);
1909 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1910 _start_gfn, _end_gfn, _iter_) \
1911 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1912 _end_level_, _start_gfn, _end_gfn); \
1913 slot_rmap_walk_okay(_iter_); \
1914 slot_rmap_walk_next(_iter_))
1916 static int kvm_handle_hva_range(struct kvm
*kvm
,
1917 unsigned long start
,
1920 int (*handler
)(struct kvm
*kvm
,
1921 struct kvm_rmap_head
*rmap_head
,
1922 struct kvm_memory_slot
*slot
,
1925 unsigned long data
))
1927 struct kvm_memslots
*slots
;
1928 struct kvm_memory_slot
*memslot
;
1929 struct slot_rmap_walk_iterator iterator
;
1933 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1934 slots
= __kvm_memslots(kvm
, i
);
1935 kvm_for_each_memslot(memslot
, slots
) {
1936 unsigned long hva_start
, hva_end
;
1937 gfn_t gfn_start
, gfn_end
;
1939 hva_start
= max(start
, memslot
->userspace_addr
);
1940 hva_end
= min(end
, memslot
->userspace_addr
+
1941 (memslot
->npages
<< PAGE_SHIFT
));
1942 if (hva_start
>= hva_end
)
1945 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1946 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1948 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1949 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1951 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1952 PT_MAX_HUGEPAGE_LEVEL
,
1953 gfn_start
, gfn_end
- 1,
1955 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1956 iterator
.gfn
, iterator
.level
, data
);
1963 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1965 int (*handler
)(struct kvm
*kvm
,
1966 struct kvm_rmap_head
*rmap_head
,
1967 struct kvm_memory_slot
*slot
,
1968 gfn_t gfn
, int level
,
1969 unsigned long data
))
1971 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1974 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1976 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1979 int kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1981 return kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1984 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1985 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1989 struct rmap_iterator
uninitialized_var(iter
);
1992 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1993 young
|= mmu_spte_age(sptep
);
1995 trace_kvm_age_page(gfn
, level
, slot
, young
);
1999 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
2000 struct kvm_memory_slot
*slot
, gfn_t gfn
,
2001 int level
, unsigned long data
)
2004 struct rmap_iterator iter
;
2006 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
2007 if (is_accessed_spte(*sptep
))
2012 #define RMAP_RECYCLE_THRESHOLD 1000
2014 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
2016 struct kvm_rmap_head
*rmap_head
;
2017 struct kvm_mmu_page
*sp
;
2019 sp
= page_header(__pa(spte
));
2021 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
2023 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
2024 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
2025 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
2028 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
2030 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
2033 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
2035 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
2039 static int is_empty_shadow_page(u64
*spt
)
2044 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
2045 if (is_shadow_present_pte(*pos
)) {
2046 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
2055 * This value is the sum of all of the kvm instances's
2056 * kvm->arch.n_used_mmu_pages values. We need a global,
2057 * aggregate version in order to make the slab shrinker
2060 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, unsigned long nr
)
2062 kvm
->arch
.n_used_mmu_pages
+= nr
;
2063 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
2066 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
2068 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
2069 hlist_del(&sp
->hash_link
);
2070 list_del(&sp
->link
);
2071 free_page((unsigned long)sp
->spt
);
2072 if (!sp
->role
.direct
)
2073 free_page((unsigned long)sp
->gfns
);
2074 kmem_cache_free(mmu_page_header_cache
, sp
);
2077 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
2079 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
2082 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
2083 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
2088 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
2091 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
2094 __pte_list_remove(parent_pte
, &sp
->parent_ptes
);
2097 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
2100 mmu_page_remove_parent_pte(sp
, parent_pte
);
2101 mmu_spte_clear_no_track(parent_pte
);
2104 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
2106 struct kvm_mmu_page
*sp
;
2108 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
2109 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
2111 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
2112 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
2115 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
2116 * depends on valid pages being added to the head of the list. See
2117 * comments in kvm_zap_obsolete_pages().
2119 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2120 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
2121 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
2125 static void mark_unsync(u64
*spte
);
2126 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
2129 struct rmap_iterator iter
;
2131 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
2136 static void mark_unsync(u64
*spte
)
2138 struct kvm_mmu_page
*sp
;
2141 sp
= page_header(__pa(spte
));
2142 index
= spte
- sp
->spt
;
2143 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
2145 if (sp
->unsync_children
++)
2147 kvm_mmu_mark_parents_unsync(sp
);
2150 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
2151 struct kvm_mmu_page
*sp
)
2156 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
, hpa_t root
)
2160 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
2161 struct kvm_mmu_page
*sp
, u64
*spte
,
2167 #define KVM_PAGE_ARRAY_NR 16
2169 struct kvm_mmu_pages
{
2170 struct mmu_page_and_offset
{
2171 struct kvm_mmu_page
*sp
;
2173 } page
[KVM_PAGE_ARRAY_NR
];
2177 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
2183 for (i
=0; i
< pvec
->nr
; i
++)
2184 if (pvec
->page
[i
].sp
== sp
)
2187 pvec
->page
[pvec
->nr
].sp
= sp
;
2188 pvec
->page
[pvec
->nr
].idx
= idx
;
2190 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
2193 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
2195 --sp
->unsync_children
;
2196 WARN_ON((int)sp
->unsync_children
< 0);
2197 __clear_bit(idx
, sp
->unsync_child_bitmap
);
2200 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2201 struct kvm_mmu_pages
*pvec
)
2203 int i
, ret
, nr_unsync_leaf
= 0;
2205 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
2206 struct kvm_mmu_page
*child
;
2207 u64 ent
= sp
->spt
[i
];
2209 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
2210 clear_unsync_child_bit(sp
, i
);
2214 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
2216 if (child
->unsync_children
) {
2217 if (mmu_pages_add(pvec
, child
, i
))
2220 ret
= __mmu_unsync_walk(child
, pvec
);
2222 clear_unsync_child_bit(sp
, i
);
2224 } else if (ret
> 0) {
2225 nr_unsync_leaf
+= ret
;
2228 } else if (child
->unsync
) {
2230 if (mmu_pages_add(pvec
, child
, i
))
2233 clear_unsync_child_bit(sp
, i
);
2236 return nr_unsync_leaf
;
2239 #define INVALID_INDEX (-1)
2241 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2242 struct kvm_mmu_pages
*pvec
)
2245 if (!sp
->unsync_children
)
2248 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2249 return __mmu_unsync_walk(sp
, pvec
);
2252 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2254 WARN_ON(!sp
->unsync
);
2255 trace_kvm_mmu_sync_page(sp
);
2257 --kvm
->stat
.mmu_unsync
;
2260 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2261 struct list_head
*invalid_list
);
2262 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2263 struct list_head
*invalid_list
);
2266 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2267 hlist_for_each_entry(_sp, \
2268 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2269 if (is_obsolete_sp((_kvm), (_sp))) { \
2272 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2273 for_each_valid_sp(_kvm, _sp, _gfn) \
2274 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2276 static inline bool is_ept_sp(struct kvm_mmu_page
*sp
)
2278 return sp
->role
.cr0_wp
&& sp
->role
.smap_andnot_wp
;
2281 /* @sp->gfn should be write-protected at the call site */
2282 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2283 struct list_head
*invalid_list
)
2285 if ((!is_ept_sp(sp
) && sp
->role
.gpte_is_8_bytes
!= !!is_pae(vcpu
)) ||
2286 vcpu
->arch
.mmu
->sync_page(vcpu
, sp
) == 0) {
2287 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2294 static bool kvm_mmu_remote_flush_or_zap(struct kvm
*kvm
,
2295 struct list_head
*invalid_list
,
2298 if (!remote_flush
&& list_empty(invalid_list
))
2301 if (!list_empty(invalid_list
))
2302 kvm_mmu_commit_zap_page(kvm
, invalid_list
);
2304 kvm_flush_remote_tlbs(kvm
);
2308 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2309 struct list_head
*invalid_list
,
2310 bool remote_flush
, bool local_flush
)
2312 if (kvm_mmu_remote_flush_or_zap(vcpu
->kvm
, invalid_list
, remote_flush
))
2316 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2319 #ifdef CONFIG_KVM_MMU_AUDIT
2320 #include "mmu_audit.c"
2322 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2323 static void mmu_audit_disable(void) { }
2326 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2328 return sp
->role
.invalid
||
2329 unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2332 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2333 struct list_head
*invalid_list
)
2335 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2336 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2339 /* @gfn should be write-protected at the call site */
2340 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2341 struct list_head
*invalid_list
)
2343 struct kvm_mmu_page
*s
;
2346 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2350 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2351 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2357 struct mmu_page_path
{
2358 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
2359 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
2362 #define for_each_sp(pvec, sp, parents, i) \
2363 for (i = mmu_pages_first(&pvec, &parents); \
2364 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2365 i = mmu_pages_next(&pvec, &parents, i))
2367 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2368 struct mmu_page_path
*parents
,
2373 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2374 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2375 unsigned idx
= pvec
->page
[n
].idx
;
2376 int level
= sp
->role
.level
;
2378 parents
->idx
[level
-1] = idx
;
2379 if (level
== PT_PAGE_TABLE_LEVEL
)
2382 parents
->parent
[level
-2] = sp
;
2388 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2389 struct mmu_page_path
*parents
)
2391 struct kvm_mmu_page
*sp
;
2397 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2399 sp
= pvec
->page
[0].sp
;
2400 level
= sp
->role
.level
;
2401 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2403 parents
->parent
[level
-2] = sp
;
2405 /* Also set up a sentinel. Further entries in pvec are all
2406 * children of sp, so this element is never overwritten.
2408 parents
->parent
[level
-1] = NULL
;
2409 return mmu_pages_next(pvec
, parents
, 0);
2412 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2414 struct kvm_mmu_page
*sp
;
2415 unsigned int level
= 0;
2418 unsigned int idx
= parents
->idx
[level
];
2419 sp
= parents
->parent
[level
];
2423 WARN_ON(idx
== INVALID_INDEX
);
2424 clear_unsync_child_bit(sp
, idx
);
2426 } while (!sp
->unsync_children
);
2429 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2430 struct kvm_mmu_page
*parent
)
2433 struct kvm_mmu_page
*sp
;
2434 struct mmu_page_path parents
;
2435 struct kvm_mmu_pages pages
;
2436 LIST_HEAD(invalid_list
);
2439 while (mmu_unsync_walk(parent
, &pages
)) {
2440 bool protected = false;
2442 for_each_sp(pages
, sp
, parents
, i
)
2443 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2446 kvm_flush_remote_tlbs(vcpu
->kvm
);
2450 for_each_sp(pages
, sp
, parents
, i
) {
2451 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2452 mmu_pages_clear_parents(&parents
);
2454 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2455 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2456 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2461 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2464 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2466 atomic_set(&sp
->write_flooding_count
, 0);
2469 static void clear_sp_write_flooding_count(u64
*spte
)
2471 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2473 __clear_sp_write_flooding_count(sp
);
2476 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2481 unsigned int access
)
2483 union kvm_mmu_page_role role
;
2485 struct kvm_mmu_page
*sp
;
2486 bool need_sync
= false;
2489 LIST_HEAD(invalid_list
);
2491 role
= vcpu
->arch
.mmu
->mmu_role
.base
;
2493 role
.direct
= direct
;
2495 role
.gpte_is_8_bytes
= true;
2496 role
.access
= access
;
2497 if (!vcpu
->arch
.mmu
->direct_map
2498 && vcpu
->arch
.mmu
->root_level
<= PT32_ROOT_LEVEL
) {
2499 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2500 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2501 role
.quadrant
= quadrant
;
2503 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2504 if (sp
->gfn
!= gfn
) {
2509 if (!need_sync
&& sp
->unsync
)
2512 if (sp
->role
.word
!= role
.word
)
2516 /* The page is good, but __kvm_sync_page might still end
2517 * up zapping it. If so, break in order to rebuild it.
2519 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2522 WARN_ON(!list_empty(&invalid_list
));
2523 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2526 if (sp
->unsync_children
)
2527 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2529 __clear_sp_write_flooding_count(sp
);
2530 trace_kvm_mmu_get_page(sp
, false);
2534 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2536 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2540 hlist_add_head(&sp
->hash_link
,
2541 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2544 * we should do write protection before syncing pages
2545 * otherwise the content of the synced shadow page may
2546 * be inconsistent with guest page table.
2548 account_shadowed(vcpu
->kvm
, sp
);
2549 if (level
== PT_PAGE_TABLE_LEVEL
&&
2550 rmap_write_protect(vcpu
, gfn
))
2551 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
, 1);
2553 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2554 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2556 clear_page(sp
->spt
);
2557 trace_kvm_mmu_get_page(sp
, true);
2559 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2561 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2562 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2566 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator
*iterator
,
2567 struct kvm_vcpu
*vcpu
, hpa_t root
,
2570 iterator
->addr
= addr
;
2571 iterator
->shadow_addr
= root
;
2572 iterator
->level
= vcpu
->arch
.mmu
->shadow_root_level
;
2574 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2575 vcpu
->arch
.mmu
->root_level
< PT64_ROOT_4LEVEL
&&
2576 !vcpu
->arch
.mmu
->direct_map
)
2579 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2581 * prev_root is currently only used for 64-bit hosts. So only
2582 * the active root_hpa is valid here.
2584 BUG_ON(root
!= vcpu
->arch
.mmu
->root_hpa
);
2586 iterator
->shadow_addr
2587 = vcpu
->arch
.mmu
->pae_root
[(addr
>> 30) & 3];
2588 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2590 if (!iterator
->shadow_addr
)
2591 iterator
->level
= 0;
2595 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2596 struct kvm_vcpu
*vcpu
, u64 addr
)
2598 shadow_walk_init_using_root(iterator
, vcpu
, vcpu
->arch
.mmu
->root_hpa
,
2602 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2604 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2607 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2608 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2612 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2615 if (is_last_spte(spte
, iterator
->level
)) {
2616 iterator
->level
= 0;
2620 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2624 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2626 __shadow_walk_next(iterator
, *iterator
->sptep
);
2629 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2630 struct kvm_mmu_page
*sp
)
2634 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2636 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2637 shadow_user_mask
| shadow_x_mask
| shadow_me_mask
;
2639 if (sp_ad_disabled(sp
))
2640 spte
|= SPTE_AD_DISABLED_MASK
;
2642 spte
|= shadow_accessed_mask
;
2644 mmu_spte_set(sptep
, spte
);
2646 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2648 if (sp
->unsync_children
|| sp
->unsync
)
2652 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2653 unsigned direct_access
)
2655 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2656 struct kvm_mmu_page
*child
;
2659 * For the direct sp, if the guest pte's dirty bit
2660 * changed form clean to dirty, it will corrupt the
2661 * sp's access: allow writable in the read-only sp,
2662 * so we should update the spte at this point to get
2663 * a new sp with the correct access.
2665 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2666 if (child
->role
.access
== direct_access
)
2669 drop_parent_pte(child
, sptep
);
2670 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, child
->gfn
, 1);
2674 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2678 struct kvm_mmu_page
*child
;
2681 if (is_shadow_present_pte(pte
)) {
2682 if (is_last_spte(pte
, sp
->role
.level
)) {
2683 drop_spte(kvm
, spte
);
2684 if (is_large_pte(pte
))
2687 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2688 drop_parent_pte(child
, spte
);
2693 if (is_mmio_spte(pte
))
2694 mmu_spte_clear_no_track(spte
);
2699 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2700 struct kvm_mmu_page
*sp
)
2704 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2705 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2708 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2711 struct rmap_iterator iter
;
2713 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2714 drop_parent_pte(sp
, sptep
);
2717 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2718 struct kvm_mmu_page
*parent
,
2719 struct list_head
*invalid_list
)
2722 struct mmu_page_path parents
;
2723 struct kvm_mmu_pages pages
;
2725 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2728 while (mmu_unsync_walk(parent
, &pages
)) {
2729 struct kvm_mmu_page
*sp
;
2731 for_each_sp(pages
, sp
, parents
, i
) {
2732 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2733 mmu_pages_clear_parents(&parents
);
2741 static bool __kvm_mmu_prepare_zap_page(struct kvm
*kvm
,
2742 struct kvm_mmu_page
*sp
,
2743 struct list_head
*invalid_list
,
2748 trace_kvm_mmu_prepare_zap_page(sp
);
2749 ++kvm
->stat
.mmu_shadow_zapped
;
2750 *nr_zapped
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2751 kvm_mmu_page_unlink_children(kvm
, sp
);
2752 kvm_mmu_unlink_parents(kvm
, sp
);
2754 /* Zapping children means active_mmu_pages has become unstable. */
2755 list_unstable
= *nr_zapped
;
2757 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2758 unaccount_shadowed(kvm
, sp
);
2761 kvm_unlink_unsync_page(kvm
, sp
);
2762 if (!sp
->root_count
) {
2765 list_move(&sp
->link
, invalid_list
);
2766 kvm_mod_used_mmu_pages(kvm
, -1);
2768 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2771 * Obsolete pages cannot be used on any vCPUs, see the comment
2772 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2773 * treats invalid shadow pages as being obsolete.
2775 if (!is_obsolete_sp(kvm
, sp
))
2776 kvm_reload_remote_mmus(kvm
);
2779 if (sp
->lpage_disallowed
)
2780 unaccount_huge_nx_page(kvm
, sp
);
2782 sp
->role
.invalid
= 1;
2783 return list_unstable
;
2786 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2787 struct list_head
*invalid_list
)
2791 __kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
, &nr_zapped
);
2795 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2796 struct list_head
*invalid_list
)
2798 struct kvm_mmu_page
*sp
, *nsp
;
2800 if (list_empty(invalid_list
))
2804 * We need to make sure everyone sees our modifications to
2805 * the page tables and see changes to vcpu->mode here. The barrier
2806 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2807 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2809 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2810 * guest mode and/or lockless shadow page table walks.
2812 kvm_flush_remote_tlbs(kvm
);
2814 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2815 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2816 kvm_mmu_free_page(sp
);
2820 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2821 struct list_head
*invalid_list
)
2823 struct kvm_mmu_page
*sp
;
2825 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2828 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2829 struct kvm_mmu_page
, link
);
2830 return kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2833 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
2835 LIST_HEAD(invalid_list
);
2837 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
2840 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
2841 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
2844 ++vcpu
->kvm
->stat
.mmu_recycled
;
2846 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2848 if (!kvm_mmu_available_pages(vcpu
->kvm
))
2854 * Changing the number of mmu pages allocated to the vm
2855 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2857 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned long goal_nr_mmu_pages
)
2859 LIST_HEAD(invalid_list
);
2861 spin_lock(&kvm
->mmu_lock
);
2863 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2864 /* Need to free some mmu pages to achieve the goal. */
2865 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2866 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2869 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2870 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2873 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2875 spin_unlock(&kvm
->mmu_lock
);
2878 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2880 struct kvm_mmu_page
*sp
;
2881 LIST_HEAD(invalid_list
);
2884 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2886 spin_lock(&kvm
->mmu_lock
);
2887 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2888 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2891 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2893 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2894 spin_unlock(&kvm
->mmu_lock
);
2898 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2900 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2902 trace_kvm_mmu_unsync_page(sp
);
2903 ++vcpu
->kvm
->stat
.mmu_unsync
;
2906 kvm_mmu_mark_parents_unsync(sp
);
2909 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2912 struct kvm_mmu_page
*sp
;
2914 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2917 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2924 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2925 kvm_unsync_page(vcpu
, sp
);
2929 * We need to ensure that the marking of unsync pages is visible
2930 * before the SPTE is updated to allow writes because
2931 * kvm_mmu_sync_roots() checks the unsync flags without holding
2932 * the MMU lock and so can race with this. If the SPTE was updated
2933 * before the page had been marked as unsync-ed, something like the
2934 * following could happen:
2937 * ---------------------------------------------------------------------
2938 * 1.2 Host updates SPTE
2940 * 2.1 Guest writes a GPTE for GVA X.
2941 * (GPTE being in the guest page table shadowed
2942 * by the SP from CPU 1.)
2943 * This reads SPTE during the page table walk.
2944 * Since SPTE.W is read as 1, there is no
2947 * 2.2 Guest issues TLB flush.
2948 * That causes a VM Exit.
2950 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2951 * Since it is false, so it just returns.
2953 * 2.4 Guest accesses GVA X.
2954 * Since the mapping in the SP was not updated,
2955 * so the old mapping for GVA X incorrectly
2959 * (sp->unsync = true)
2961 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2962 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2963 * pairs with this write barrier.
2970 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2973 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
)) &&
2975 * Some reserved pages, such as those from NVDIMM
2976 * DAX devices, are not for MMIO, and can be mapped
2977 * with cached memory type for better performance.
2978 * However, the above check misconceives those pages
2979 * as MMIO, and results in KVM mapping them with UC
2980 * memory type, which would hurt the performance.
2981 * Therefore, we check the host memory type in addition
2982 * and only treat UC/UC-/WC pages as MMIO.
2984 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn
));
2986 return !e820__mapped_raw_any(pfn_to_hpa(pfn
),
2987 pfn_to_hpa(pfn
+ 1) - 1,
2991 /* Bits which may be returned by set_spte() */
2992 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2993 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2995 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2996 unsigned int pte_access
, int level
,
2997 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2998 bool can_unsync
, bool host_writable
)
3002 struct kvm_mmu_page
*sp
;
3004 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
3007 sp
= page_header(__pa(sptep
));
3008 if (sp_ad_disabled(sp
))
3009 spte
|= SPTE_AD_DISABLED_MASK
;
3010 else if (kvm_vcpu_ad_need_write_protect(vcpu
))
3011 spte
|= SPTE_AD_WRPROT_ONLY_MASK
;
3014 * For the EPT case, shadow_present_mask is 0 if hardware
3015 * supports exec-only page table entries. In that case,
3016 * ACC_USER_MASK and shadow_user_mask are used to represent
3017 * read access. See FNAME(gpte_access) in paging_tmpl.h.
3019 spte
|= shadow_present_mask
;
3021 spte
|= spte_shadow_accessed_mask(spte
);
3023 if (level
> PT_PAGE_TABLE_LEVEL
&& (pte_access
& ACC_EXEC_MASK
) &&
3024 is_nx_huge_page_enabled()) {
3025 pte_access
&= ~ACC_EXEC_MASK
;
3028 if (pte_access
& ACC_EXEC_MASK
)
3029 spte
|= shadow_x_mask
;
3031 spte
|= shadow_nx_mask
;
3033 if (pte_access
& ACC_USER_MASK
)
3034 spte
|= shadow_user_mask
;
3036 if (level
> PT_PAGE_TABLE_LEVEL
)
3037 spte
|= PT_PAGE_SIZE_MASK
;
3039 spte
|= kvm_x86_ops
.get_mt_mask(vcpu
, gfn
,
3040 kvm_is_mmio_pfn(pfn
));
3043 spte
|= SPTE_HOST_WRITEABLE
;
3045 pte_access
&= ~ACC_WRITE_MASK
;
3047 if (!kvm_is_mmio_pfn(pfn
))
3048 spte
|= shadow_me_mask
;
3050 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
3052 if (pte_access
& ACC_WRITE_MASK
) {
3053 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
3056 * Optimization: for pte sync, if spte was writable the hash
3057 * lookup is unnecessary (and expensive). Write protection
3058 * is responsibility of mmu_get_page / kvm_sync_page.
3059 * Same reasoning can be applied to dirty page accounting.
3061 if (!can_unsync
&& is_writable_pte(*sptep
))
3064 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
3065 pgprintk("%s: found shadow page for %llx, marking ro\n",
3067 ret
|= SET_SPTE_WRITE_PROTECTED_PT
;
3068 pte_access
&= ~ACC_WRITE_MASK
;
3069 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
3073 if (pte_access
& ACC_WRITE_MASK
) {
3074 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3075 spte
|= spte_shadow_dirty_mask(spte
);
3079 spte
= mark_spte_for_access_track(spte
);
3082 if (mmu_spte_update(sptep
, spte
))
3083 ret
|= SET_SPTE_NEED_REMOTE_TLB_FLUSH
;
3087 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
3088 unsigned int pte_access
, int write_fault
, int level
,
3089 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
3092 int was_rmapped
= 0;
3095 int ret
= RET_PF_RETRY
;
3098 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
3099 *sptep
, write_fault
, gfn
);
3101 if (is_shadow_present_pte(*sptep
)) {
3103 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
3104 * the parent of the now unreachable PTE.
3106 if (level
> PT_PAGE_TABLE_LEVEL
&&
3107 !is_large_pte(*sptep
)) {
3108 struct kvm_mmu_page
*child
;
3111 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
3112 drop_parent_pte(child
, sptep
);
3114 } else if (pfn
!= spte_to_pfn(*sptep
)) {
3115 pgprintk("hfn old %llx new %llx\n",
3116 spte_to_pfn(*sptep
), pfn
);
3117 drop_spte(vcpu
->kvm
, sptep
);
3123 set_spte_ret
= set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
,
3124 speculative
, true, host_writable
);
3125 if (set_spte_ret
& SET_SPTE_WRITE_PROTECTED_PT
) {
3127 ret
= RET_PF_EMULATE
;
3128 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3131 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
|| flush
)
3132 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
,
3133 KVM_PAGES_PER_HPAGE(level
));
3135 if (unlikely(is_mmio_spte(*sptep
)))
3136 ret
= RET_PF_EMULATE
;
3138 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
3139 trace_kvm_mmu_set_spte(level
, gfn
, sptep
);
3140 if (!was_rmapped
&& is_large_pte(*sptep
))
3141 ++vcpu
->kvm
->stat
.lpages
;
3143 if (is_shadow_present_pte(*sptep
)) {
3145 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
3146 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
3147 rmap_recycle(vcpu
, sptep
, gfn
);
3154 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
3157 struct kvm_memory_slot
*slot
;
3159 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
3161 return KVM_PFN_ERR_FAULT
;
3163 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
3166 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
3167 struct kvm_mmu_page
*sp
,
3168 u64
*start
, u64
*end
)
3170 struct page
*pages
[PTE_PREFETCH_NUM
];
3171 struct kvm_memory_slot
*slot
;
3172 unsigned int access
= sp
->role
.access
;
3176 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
3177 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
3181 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
3185 for (i
= 0; i
< ret
; i
++, gfn
++, start
++) {
3186 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
3187 page_to_pfn(pages
[i
]), true, true);
3194 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
3195 struct kvm_mmu_page
*sp
, u64
*sptep
)
3197 u64
*spte
, *start
= NULL
;
3200 WARN_ON(!sp
->role
.direct
);
3202 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
3205 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
3206 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
3209 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
3217 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
3219 struct kvm_mmu_page
*sp
;
3221 sp
= page_header(__pa(sptep
));
3224 * Without accessed bits, there's no way to distinguish between
3225 * actually accessed translations and prefetched, so disable pte
3226 * prefetch if accessed bits aren't available.
3228 if (sp_ad_disabled(sp
))
3231 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3234 __direct_pte_prefetch(vcpu
, sp
, sptep
);
3237 static int host_pfn_mapping_level(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
3238 kvm_pfn_t pfn
, struct kvm_memory_slot
*slot
)
3244 BUILD_BUG_ON(PT_PAGE_TABLE_LEVEL
!= (int)PG_LEVEL_4K
||
3245 PT_DIRECTORY_LEVEL
!= (int)PG_LEVEL_2M
||
3246 PT_PDPE_LEVEL
!= (int)PG_LEVEL_1G
);
3248 if (!PageCompound(pfn_to_page(pfn
)) && !kvm_is_zone_device_pfn(pfn
))
3249 return PT_PAGE_TABLE_LEVEL
;
3252 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
3253 * is not solely for performance, it's also necessary to avoid the
3254 * "writable" check in __gfn_to_hva_many(), which will always fail on
3255 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
3256 * page fault steps have already verified the guest isn't writing a
3257 * read-only memslot.
3259 hva
= __gfn_to_hva_memslot(slot
, gfn
);
3261 pte
= lookup_address_in_mm(vcpu
->kvm
->mm
, hva
, &level
);
3263 return PT_PAGE_TABLE_LEVEL
;
3268 static int kvm_mmu_hugepage_adjust(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
3269 int max_level
, kvm_pfn_t
*pfnp
)
3271 struct kvm_memory_slot
*slot
;
3272 struct kvm_lpage_info
*linfo
;
3273 kvm_pfn_t pfn
= *pfnp
;
3277 if (unlikely(max_level
== PT_PAGE_TABLE_LEVEL
))
3278 return PT_PAGE_TABLE_LEVEL
;
3280 if (is_error_noslot_pfn(pfn
) || kvm_is_reserved_pfn(pfn
))
3281 return PT_PAGE_TABLE_LEVEL
;
3283 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, true);
3285 return PT_PAGE_TABLE_LEVEL
;
3287 max_level
= min(max_level
, max_page_level
);
3288 for ( ; max_level
> PT_PAGE_TABLE_LEVEL
; max_level
--) {
3289 linfo
= lpage_info_slot(gfn
, slot
, max_level
);
3290 if (!linfo
->disallow_lpage
)
3294 if (max_level
== PT_PAGE_TABLE_LEVEL
)
3295 return PT_PAGE_TABLE_LEVEL
;
3297 level
= host_pfn_mapping_level(vcpu
, gfn
, pfn
, slot
);
3298 if (level
== PT_PAGE_TABLE_LEVEL
)
3301 level
= min(level
, max_level
);
3304 * mmu_notifier_retry() was successful and mmu_lock is held, so
3305 * the pmd can't be split from under us.
3307 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
3308 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
3309 *pfnp
= pfn
& ~mask
;
3314 static void disallowed_hugepage_adjust(struct kvm_shadow_walk_iterator it
,
3315 gfn_t gfn
, kvm_pfn_t
*pfnp
, int *levelp
)
3317 int level
= *levelp
;
3318 u64 spte
= *it
.sptep
;
3320 if (it
.level
== level
&& level
> PT_PAGE_TABLE_LEVEL
&&
3321 is_nx_huge_page_enabled() &&
3322 is_shadow_present_pte(spte
) &&
3323 !is_large_pte(spte
)) {
3325 * A small SPTE exists for this pfn, but FNAME(fetch)
3326 * and __direct_map would like to create a large PTE
3327 * instead: just force them to go down another level,
3328 * patching back for them into pfn the next 9 bits of
3331 u64 page_mask
= KVM_PAGES_PER_HPAGE(level
) - KVM_PAGES_PER_HPAGE(level
- 1);
3332 *pfnp
|= gfn
& page_mask
;
3337 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t gpa
, int write
,
3338 int map_writable
, int max_level
, kvm_pfn_t pfn
,
3339 bool prefault
, bool account_disallowed_nx_lpage
)
3341 struct kvm_shadow_walk_iterator it
;
3342 struct kvm_mmu_page
*sp
;
3344 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3345 gfn_t base_gfn
= gfn
;
3347 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
3348 return RET_PF_RETRY
;
3350 level
= kvm_mmu_hugepage_adjust(vcpu
, gfn
, max_level
, &pfn
);
3352 trace_kvm_mmu_spte_requested(gpa
, level
, pfn
);
3353 for_each_shadow_entry(vcpu
, gpa
, it
) {
3355 * We cannot overwrite existing page tables with an NX
3356 * large page, as the leaf could be executable.
3358 disallowed_hugepage_adjust(it
, gfn
, &pfn
, &level
);
3360 base_gfn
= gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
3361 if (it
.level
== level
)
3364 drop_large_spte(vcpu
, it
.sptep
);
3365 if (!is_shadow_present_pte(*it
.sptep
)) {
3366 sp
= kvm_mmu_get_page(vcpu
, base_gfn
, it
.addr
,
3367 it
.level
- 1, true, ACC_ALL
);
3369 link_shadow_page(vcpu
, it
.sptep
, sp
);
3370 if (account_disallowed_nx_lpage
)
3371 account_huge_nx_page(vcpu
->kvm
, sp
);
3375 ret
= mmu_set_spte(vcpu
, it
.sptep
, ACC_ALL
,
3376 write
, level
, base_gfn
, pfn
, prefault
,
3378 direct_pte_prefetch(vcpu
, it
.sptep
);
3379 ++vcpu
->stat
.pf_fixed
;
3383 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
3385 send_sig_mceerr(BUS_MCEERR_AR
, (void __user
*)address
, PAGE_SHIFT
, tsk
);
3388 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
3391 * Do not cache the mmio info caused by writing the readonly gfn
3392 * into the spte otherwise read access on readonly gfn also can
3393 * caused mmio page fault and treat it as mmio access.
3395 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3396 return RET_PF_EMULATE
;
3398 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3399 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3400 return RET_PF_RETRY
;
3406 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3407 kvm_pfn_t pfn
, unsigned int access
,
3410 /* The pfn is invalid, report the error! */
3411 if (unlikely(is_error_pfn(pfn
))) {
3412 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3416 if (unlikely(is_noslot_pfn(pfn
)))
3417 vcpu_cache_mmio_info(vcpu
, gva
, gfn
,
3418 access
& shadow_mmio_access_mask
);
3423 static bool page_fault_can_be_fast(u32 error_code
)
3426 * Do not fix the mmio spte with invalid generation number which
3427 * need to be updated by slow page fault path.
3429 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3432 /* See if the page fault is due to an NX violation */
3433 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3434 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3438 * #PF can be fast if:
3439 * 1. The shadow page table entry is not present, which could mean that
3440 * the fault is potentially caused by access tracking (if enabled).
3441 * 2. The shadow page table entry is present and the fault
3442 * is caused by write-protect, that means we just need change the W
3443 * bit of the spte which can be done out of mmu-lock.
3445 * However, if access tracking is disabled we know that a non-present
3446 * page must be a genuine page fault where we have to create a new SPTE.
3447 * So, if access tracking is disabled, we return true only for write
3448 * accesses to a present page.
3451 return shadow_acc_track_mask
!= 0 ||
3452 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3453 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3457 * Returns true if the SPTE was fixed successfully. Otherwise,
3458 * someone else modified the SPTE from its original value.
3461 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3462 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3466 WARN_ON(!sp
->role
.direct
);
3469 * Theoretically we could also set dirty bit (and flush TLB) here in
3470 * order to eliminate unnecessary PML logging. See comments in
3471 * set_spte. But fast_page_fault is very unlikely to happen with PML
3472 * enabled, so we do not do this. This might result in the same GPA
3473 * to be logged in PML buffer again when the write really happens, and
3474 * eventually to be called by mark_page_dirty twice. But it's also no
3475 * harm. This also avoids the TLB flush needed after setting dirty bit
3476 * so non-PML cases won't be impacted.
3478 * Compare with set_spte where instead shadow_dirty_mask is set.
3480 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3483 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3485 * The gfn of direct spte is stable since it is
3486 * calculated by sp->gfn.
3488 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3489 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3495 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3497 if (fault_err_code
& PFERR_FETCH_MASK
)
3498 return is_executable_pte(spte
);
3500 if (fault_err_code
& PFERR_WRITE_MASK
)
3501 return is_writable_pte(spte
);
3503 /* Fault was on Read access */
3504 return spte
& PT_PRESENT_MASK
;
3509 * - true: let the vcpu to access on the same address again.
3510 * - false: let the real page fault path to fix it.
3512 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3515 struct kvm_shadow_walk_iterator iterator
;
3516 struct kvm_mmu_page
*sp
;
3517 bool fault_handled
= false;
3519 uint retry_count
= 0;
3521 if (!page_fault_can_be_fast(error_code
))
3524 walk_shadow_page_lockless_begin(vcpu
);
3529 for_each_shadow_entry_lockless(vcpu
, cr2_or_gpa
, iterator
, spte
)
3530 if (!is_shadow_present_pte(spte
))
3533 sp
= page_header(__pa(iterator
.sptep
));
3534 if (!is_last_spte(spte
, sp
->role
.level
))
3538 * Check whether the memory access that caused the fault would
3539 * still cause it if it were to be performed right now. If not,
3540 * then this is a spurious fault caused by TLB lazily flushed,
3541 * or some other CPU has already fixed the PTE after the
3542 * current CPU took the fault.
3544 * Need not check the access of upper level table entries since
3545 * they are always ACC_ALL.
3547 if (is_access_allowed(error_code
, spte
)) {
3548 fault_handled
= true;
3554 if (is_access_track_spte(spte
))
3555 new_spte
= restore_acc_track_spte(new_spte
);
3558 * Currently, to simplify the code, write-protection can
3559 * be removed in the fast path only if the SPTE was
3560 * write-protected for dirty-logging or access tracking.
3562 if ((error_code
& PFERR_WRITE_MASK
) &&
3563 spte_can_locklessly_be_made_writable(spte
)) {
3564 new_spte
|= PT_WRITABLE_MASK
;
3567 * Do not fix write-permission on the large spte. Since
3568 * we only dirty the first page into the dirty-bitmap in
3569 * fast_pf_fix_direct_spte(), other pages are missed
3570 * if its slot has dirty logging enabled.
3572 * Instead, we let the slow page fault path create a
3573 * normal spte to fix the access.
3575 * See the comments in kvm_arch_commit_memory_region().
3577 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3581 /* Verify that the fault can be handled in the fast path */
3582 if (new_spte
== spte
||
3583 !is_access_allowed(error_code
, new_spte
))
3587 * Currently, fast page fault only works for direct mapping
3588 * since the gfn is not stable for indirect shadow page. See
3589 * Documentation/virt/kvm/locking.rst to get more detail.
3591 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3592 iterator
.sptep
, spte
,
3597 if (++retry_count
> 4) {
3598 printk_once(KERN_WARNING
3599 "kvm: Fast #PF retrying more than 4 times.\n");
3605 trace_fast_page_fault(vcpu
, cr2_or_gpa
, error_code
, iterator
.sptep
,
3606 spte
, fault_handled
);
3607 walk_shadow_page_lockless_end(vcpu
);
3609 return fault_handled
;
3612 static void mmu_free_root_page(struct kvm
*kvm
, hpa_t
*root_hpa
,
3613 struct list_head
*invalid_list
)
3615 struct kvm_mmu_page
*sp
;
3617 if (!VALID_PAGE(*root_hpa
))
3620 sp
= page_header(*root_hpa
& PT64_BASE_ADDR_MASK
);
3622 if (!sp
->root_count
&& sp
->role
.invalid
)
3623 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
3625 *root_hpa
= INVALID_PAGE
;
3628 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3629 void kvm_mmu_free_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3630 ulong roots_to_free
)
3633 LIST_HEAD(invalid_list
);
3634 bool free_active_root
= roots_to_free
& KVM_MMU_ROOT_CURRENT
;
3636 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS
>= BITS_PER_LONG
);
3638 /* Before acquiring the MMU lock, see if we need to do any real work. */
3639 if (!(free_active_root
&& VALID_PAGE(mmu
->root_hpa
))) {
3640 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3641 if ((roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
)) &&
3642 VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
3645 if (i
== KVM_MMU_NUM_PREV_ROOTS
)
3649 spin_lock(&vcpu
->kvm
->mmu_lock
);
3651 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3652 if (roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
))
3653 mmu_free_root_page(vcpu
->kvm
, &mmu
->prev_roots
[i
].hpa
,
3656 if (free_active_root
) {
3657 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3658 (mmu
->root_level
>= PT64_ROOT_4LEVEL
|| mmu
->direct_map
)) {
3659 mmu_free_root_page(vcpu
->kvm
, &mmu
->root_hpa
,
3662 for (i
= 0; i
< 4; ++i
)
3663 if (mmu
->pae_root
[i
] != 0)
3664 mmu_free_root_page(vcpu
->kvm
,
3667 mmu
->root_hpa
= INVALID_PAGE
;
3672 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3673 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3675 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots
);
3677 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3681 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3682 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3689 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3691 struct kvm_mmu_page
*sp
;
3694 if (vcpu
->arch
.mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3695 spin_lock(&vcpu
->kvm
->mmu_lock
);
3696 if(make_mmu_pages_available(vcpu
) < 0) {
3697 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3700 sp
= kvm_mmu_get_page(vcpu
, 0, 0,
3701 vcpu
->arch
.mmu
->shadow_root_level
, 1, ACC_ALL
);
3703 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3704 vcpu
->arch
.mmu
->root_hpa
= __pa(sp
->spt
);
3705 } else if (vcpu
->arch
.mmu
->shadow_root_level
== PT32E_ROOT_LEVEL
) {
3706 for (i
= 0; i
< 4; ++i
) {
3707 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3709 MMU_WARN_ON(VALID_PAGE(root
));
3710 spin_lock(&vcpu
->kvm
->mmu_lock
);
3711 if (make_mmu_pages_available(vcpu
) < 0) {
3712 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3715 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3716 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3717 root
= __pa(sp
->spt
);
3719 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3720 vcpu
->arch
.mmu
->pae_root
[i
] = root
| PT_PRESENT_MASK
;
3722 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->pae_root
);
3726 /* root_cr3 is ignored for direct MMUs. */
3727 vcpu
->arch
.mmu
->root_cr3
= 0;
3732 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3734 struct kvm_mmu_page
*sp
;
3736 gfn_t root_gfn
, root_cr3
;
3739 root_cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3740 root_gfn
= root_cr3
>> PAGE_SHIFT
;
3742 if (mmu_check_root(vcpu
, root_gfn
))
3746 * Do we shadow a long mode page table? If so we need to
3747 * write-protect the guests page table root.
3749 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3750 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3752 MMU_WARN_ON(VALID_PAGE(root
));
3754 spin_lock(&vcpu
->kvm
->mmu_lock
);
3755 if (make_mmu_pages_available(vcpu
) < 0) {
3756 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3759 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0,
3760 vcpu
->arch
.mmu
->shadow_root_level
, 0, ACC_ALL
);
3761 root
= __pa(sp
->spt
);
3763 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3764 vcpu
->arch
.mmu
->root_hpa
= root
;
3769 * We shadow a 32 bit page table. This may be a legacy 2-level
3770 * or a PAE 3-level page table. In either case we need to be aware that
3771 * the shadow page table may be a PAE or a long mode page table.
3773 pm_mask
= PT_PRESENT_MASK
;
3774 if (vcpu
->arch
.mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
)
3775 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3777 for (i
= 0; i
< 4; ++i
) {
3778 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3780 MMU_WARN_ON(VALID_PAGE(root
));
3781 if (vcpu
->arch
.mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3782 pdptr
= vcpu
->arch
.mmu
->get_pdptr(vcpu
, i
);
3783 if (!(pdptr
& PT_PRESENT_MASK
)) {
3784 vcpu
->arch
.mmu
->pae_root
[i
] = 0;
3787 root_gfn
= pdptr
>> PAGE_SHIFT
;
3788 if (mmu_check_root(vcpu
, root_gfn
))
3791 spin_lock(&vcpu
->kvm
->mmu_lock
);
3792 if (make_mmu_pages_available(vcpu
) < 0) {
3793 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3796 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3798 root
= __pa(sp
->spt
);
3800 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3802 vcpu
->arch
.mmu
->pae_root
[i
] = root
| pm_mask
;
3804 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->pae_root
);
3807 * If we shadow a 32 bit page table with a long mode page
3808 * table we enter this path.
3810 if (vcpu
->arch
.mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
) {
3811 if (vcpu
->arch
.mmu
->lm_root
== NULL
) {
3813 * The additional page necessary for this is only
3814 * allocated on demand.
3819 lm_root
= (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3820 if (lm_root
== NULL
)
3823 lm_root
[0] = __pa(vcpu
->arch
.mmu
->pae_root
) | pm_mask
;
3825 vcpu
->arch
.mmu
->lm_root
= lm_root
;
3828 vcpu
->arch
.mmu
->root_hpa
= __pa(vcpu
->arch
.mmu
->lm_root
);
3832 vcpu
->arch
.mmu
->root_cr3
= root_cr3
;
3837 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3839 if (vcpu
->arch
.mmu
->direct_map
)
3840 return mmu_alloc_direct_roots(vcpu
);
3842 return mmu_alloc_shadow_roots(vcpu
);
3845 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3848 struct kvm_mmu_page
*sp
;
3850 if (vcpu
->arch
.mmu
->direct_map
)
3853 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
3856 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3858 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3859 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3860 sp
= page_header(root
);
3863 * Even if another CPU was marking the SP as unsync-ed
3864 * simultaneously, any guest page table changes are not
3865 * guaranteed to be visible anyway until this VCPU issues a TLB
3866 * flush strictly after those changes are made. We only need to
3867 * ensure that the other CPU sets these flags before any actual
3868 * changes to the page tables are made. The comments in
3869 * mmu_need_write_protect() describe what could go wrong if this
3870 * requirement isn't satisfied.
3872 if (!smp_load_acquire(&sp
->unsync
) &&
3873 !smp_load_acquire(&sp
->unsync_children
))
3876 spin_lock(&vcpu
->kvm
->mmu_lock
);
3877 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3879 mmu_sync_children(vcpu
, sp
);
3881 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3882 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3886 spin_lock(&vcpu
->kvm
->mmu_lock
);
3887 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3889 for (i
= 0; i
< 4; ++i
) {
3890 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3892 if (root
&& VALID_PAGE(root
)) {
3893 root
&= PT64_BASE_ADDR_MASK
;
3894 sp
= page_header(root
);
3895 mmu_sync_children(vcpu
, sp
);
3899 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3900 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3902 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3904 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3905 u32 access
, struct x86_exception
*exception
)
3908 exception
->error_code
= 0;
3912 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3914 struct x86_exception
*exception
)
3917 exception
->error_code
= 0;
3918 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3922 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3924 int bit7
= (pte
>> 7) & 1;
3926 return pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1];
3929 static bool __is_bad_mt_xwr(struct rsvd_bits_validate
*rsvd_check
, u64 pte
)
3931 return rsvd_check
->bad_mt_xwr
& BIT_ULL(pte
& 0x3f);
3934 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3937 * A nested guest cannot use the MMIO cache if it is using nested
3938 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3940 if (mmu_is_nested(vcpu
))
3944 return vcpu_match_mmio_gpa(vcpu
, addr
);
3946 return vcpu_match_mmio_gva(vcpu
, addr
);
3949 /* return true if reserved bit is detected on spte. */
3951 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3953 struct kvm_shadow_walk_iterator iterator
;
3954 u64 sptes
[PT64_ROOT_MAX_LEVEL
], spte
= 0ull;
3955 struct rsvd_bits_validate
*rsvd_check
;
3957 bool reserved
= false;
3959 rsvd_check
= &vcpu
->arch
.mmu
->shadow_zero_check
;
3961 walk_shadow_page_lockless_begin(vcpu
);
3963 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3964 leaf
= root
= iterator
.level
;
3965 shadow_walk_okay(&iterator
);
3966 __shadow_walk_next(&iterator
, spte
)) {
3967 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3969 sptes
[leaf
- 1] = spte
;
3972 if (!is_shadow_present_pte(spte
))
3976 * Use a bitwise-OR instead of a logical-OR to aggregate the
3977 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3978 * adding a Jcc in the loop.
3980 reserved
|= __is_bad_mt_xwr(rsvd_check
, spte
) |
3981 __is_rsvd_bits_set(rsvd_check
, spte
, iterator
.level
);
3984 walk_shadow_page_lockless_end(vcpu
);
3987 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3989 while (root
> leaf
) {
3990 pr_err("------ spte 0x%llx level %d.\n",
3991 sptes
[root
- 1], root
);
4000 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
4005 if (mmio_info_in_cache(vcpu
, addr
, direct
))
4006 return RET_PF_EMULATE
;
4008 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
4009 if (WARN_ON(reserved
))
4012 if (is_mmio_spte(spte
)) {
4013 gfn_t gfn
= get_mmio_spte_gfn(spte
);
4014 unsigned int access
= get_mmio_spte_access(spte
);
4016 if (!check_mmio_spte(vcpu
, spte
))
4017 return RET_PF_INVALID
;
4022 trace_handle_mmio_page_fault(addr
, gfn
, access
);
4023 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
4024 return RET_PF_EMULATE
;
4028 * If the page table is zapped by other cpus, let CPU fault again on
4031 return RET_PF_RETRY
;
4034 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
4035 u32 error_code
, gfn_t gfn
)
4037 if (unlikely(error_code
& PFERR_RSVD_MASK
))
4040 if (!(error_code
& PFERR_PRESENT_MASK
) ||
4041 !(error_code
& PFERR_WRITE_MASK
))
4045 * guest is writing the page which is write tracked which can
4046 * not be fixed by page fault handler.
4048 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
4054 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
4056 struct kvm_shadow_walk_iterator iterator
;
4059 walk_shadow_page_lockless_begin(vcpu
);
4060 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4061 clear_sp_write_flooding_count(iterator
.sptep
);
4062 if (!is_shadow_present_pte(spte
))
4065 walk_shadow_page_lockless_end(vcpu
);
4068 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
4071 struct kvm_arch_async_pf arch
;
4073 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
4075 arch
.direct_map
= vcpu
->arch
.mmu
->direct_map
;
4076 arch
.cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
4078 return kvm_setup_async_pf(vcpu
, cr2_or_gpa
,
4079 kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
4082 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
4083 gpa_t cr2_or_gpa
, kvm_pfn_t
*pfn
, bool write
,
4086 struct kvm_memory_slot
*slot
;
4090 * Don't expose private memslots to L2.
4092 if (is_guest_mode(vcpu
) && !kvm_is_visible_gfn(vcpu
->kvm
, gfn
)) {
4093 *pfn
= KVM_PFN_NOSLOT
;
4097 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
4099 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
4101 return false; /* *pfn has correct page already */
4103 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
4104 trace_kvm_try_async_get_page(cr2_or_gpa
, gfn
);
4105 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
4106 trace_kvm_async_pf_doublefault(cr2_or_gpa
, gfn
);
4107 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
4109 } else if (kvm_arch_setup_async_pf(vcpu
, cr2_or_gpa
, gfn
))
4113 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
4117 static int direct_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
4118 bool prefault
, int max_level
, bool is_tdp
)
4120 bool write
= error_code
& PFERR_WRITE_MASK
;
4121 bool exec
= error_code
& PFERR_FETCH_MASK
;
4122 bool lpage_disallowed
= exec
&& is_nx_huge_page_enabled();
4125 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4126 unsigned long mmu_seq
;
4130 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
4131 return RET_PF_EMULATE
;
4133 r
= mmu_topup_memory_caches(vcpu
);
4137 if (lpage_disallowed
)
4138 max_level
= PT_PAGE_TABLE_LEVEL
;
4140 if (fast_page_fault(vcpu
, gpa
, error_code
))
4141 return RET_PF_RETRY
;
4143 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
4146 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
4147 return RET_PF_RETRY
;
4149 if (handle_abnormal_pfn(vcpu
, is_tdp
? 0 : gpa
, gfn
, pfn
, ACC_ALL
, &r
))
4153 spin_lock(&vcpu
->kvm
->mmu_lock
);
4154 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
4156 if (make_mmu_pages_available(vcpu
) < 0)
4158 r
= __direct_map(vcpu
, gpa
, write
, map_writable
, max_level
, pfn
,
4159 prefault
, is_tdp
&& lpage_disallowed
);
4162 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4163 kvm_release_pfn_clean(pfn
);
4167 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4168 u32 error_code
, bool prefault
)
4170 pgprintk("%s: gva %lx error %x\n", __func__
, gpa
, error_code
);
4172 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
4173 return direct_page_fault(vcpu
, gpa
& PAGE_MASK
, error_code
, prefault
,
4174 PT_DIRECTORY_LEVEL
, false);
4177 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
4178 u64 fault_address
, char *insn
, int insn_len
)
4182 #ifndef CONFIG_X86_64
4183 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4184 if (WARN_ON_ONCE(fault_address
>> 32))
4188 vcpu
->arch
.l1tf_flush_l1d
= true;
4189 switch (vcpu
->arch
.apf
.host_apf_reason
) {
4191 trace_kvm_page_fault(fault_address
, error_code
);
4193 if (kvm_event_needs_reinjection(vcpu
))
4194 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
4195 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
4198 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
4199 vcpu
->arch
.apf
.host_apf_reason
= 0;
4200 local_irq_disable();
4201 kvm_async_pf_task_wait(fault_address
, 0);
4204 case KVM_PV_REASON_PAGE_READY
:
4205 vcpu
->arch
.apf
.host_apf_reason
= 0;
4206 local_irq_disable();
4207 kvm_async_pf_task_wake(fault_address
);
4213 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
4215 int kvm_tdp_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
4220 for (max_level
= PT_MAX_HUGEPAGE_LEVEL
;
4221 max_level
> PT_PAGE_TABLE_LEVEL
;
4223 int page_num
= KVM_PAGES_PER_HPAGE(max_level
);
4224 gfn_t base
= (gpa
>> PAGE_SHIFT
) & ~(page_num
- 1);
4226 if (kvm_mtrr_check_gfn_range_consistency(vcpu
, base
, page_num
))
4230 return direct_page_fault(vcpu
, gpa
, error_code
, prefault
,
4234 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
4235 struct kvm_mmu
*context
)
4237 context
->page_fault
= nonpaging_page_fault
;
4238 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4239 context
->sync_page
= nonpaging_sync_page
;
4240 context
->invlpg
= nonpaging_invlpg
;
4241 context
->update_pte
= nonpaging_update_pte
;
4242 context
->root_level
= 0;
4243 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4244 context
->direct_map
= true;
4245 context
->nx
= false;
4248 static inline bool is_root_usable(struct kvm_mmu_root_info
*root
, gpa_t cr3
,
4249 union kvm_mmu_page_role role
)
4251 return (role
.direct
|| cr3
== root
->cr3
) &&
4252 VALID_PAGE(root
->hpa
) && page_header(root
->hpa
) &&
4253 role
.word
== page_header(root
->hpa
)->role
.word
;
4257 * Find out if a previously cached root matching the new CR3/role is available.
4258 * The current root is also inserted into the cache.
4259 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4261 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4262 * false is returned. This root should now be freed by the caller.
4264 static bool cached_root_available(struct kvm_vcpu
*vcpu
, gpa_t new_cr3
,
4265 union kvm_mmu_page_role new_role
)
4268 struct kvm_mmu_root_info root
;
4269 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4271 root
.cr3
= mmu
->root_cr3
;
4272 root
.hpa
= mmu
->root_hpa
;
4274 if (is_root_usable(&root
, new_cr3
, new_role
))
4277 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
4278 swap(root
, mmu
->prev_roots
[i
]);
4280 if (is_root_usable(&root
, new_cr3
, new_role
))
4284 mmu
->root_hpa
= root
.hpa
;
4285 mmu
->root_cr3
= root
.cr3
;
4287 return i
< KVM_MMU_NUM_PREV_ROOTS
;
4290 static bool fast_cr3_switch(struct kvm_vcpu
*vcpu
, gpa_t new_cr3
,
4291 union kvm_mmu_page_role new_role
,
4292 bool skip_tlb_flush
)
4294 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4297 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4298 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4299 * later if necessary.
4301 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
4302 mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
4303 if (mmu_check_root(vcpu
, new_cr3
>> PAGE_SHIFT
))
4306 if (cached_root_available(vcpu
, new_cr3
, new_role
)) {
4308 * It is possible that the cached previous root page is
4309 * obsolete because of a change in the MMU generation
4310 * number. However, changing the generation number is
4311 * accompanied by KVM_REQ_MMU_RELOAD, which will free
4312 * the root set here and allocate a new one.
4314 kvm_make_request(KVM_REQ_LOAD_MMU_PGD
, vcpu
);
4315 if (!skip_tlb_flush
) {
4316 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
4317 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4321 * The last MMIO access's GVA and GPA are cached in the
4322 * VCPU. When switching to a new CR3, that GVA->GPA
4323 * mapping may no longer be valid. So clear any cached
4324 * MMIO info even when we don't need to sync the shadow
4327 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
4329 __clear_sp_write_flooding_count(
4330 page_header(mmu
->root_hpa
));
4339 static void __kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
, gpa_t new_cr3
,
4340 union kvm_mmu_page_role new_role
,
4341 bool skip_tlb_flush
)
4343 if (!fast_cr3_switch(vcpu
, new_cr3
, new_role
, skip_tlb_flush
))
4344 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
,
4345 KVM_MMU_ROOT_CURRENT
);
4348 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
, gpa_t new_cr3
, bool skip_tlb_flush
)
4350 __kvm_mmu_new_cr3(vcpu
, new_cr3
, kvm_mmu_calc_root_page_role(vcpu
),
4353 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3
);
4355 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
4357 return kvm_read_cr3(vcpu
);
4360 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
4361 struct x86_exception
*fault
)
4363 vcpu
->arch
.mmu
->inject_page_fault(vcpu
, fault
);
4366 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
4367 unsigned int access
, int *nr_present
)
4369 if (unlikely(is_mmio_spte(*sptep
))) {
4370 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
4371 mmu_spte_clear_no_track(sptep
);
4376 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
4383 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
4384 unsigned level
, unsigned gpte
)
4387 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4388 * If it is clear, there are no large pages at this level, so clear
4389 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4391 gpte
&= level
- mmu
->last_nonleaf_level
;
4394 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4395 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4396 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4398 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
4400 return gpte
& PT_PAGE_SIZE_MASK
;
4403 #define PTTYPE_EPT 18 /* arbitrary */
4404 #define PTTYPE PTTYPE_EPT
4405 #include "paging_tmpl.h"
4409 #include "paging_tmpl.h"
4413 #include "paging_tmpl.h"
4417 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4418 struct rsvd_bits_validate
*rsvd_check
,
4419 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
4422 u64 exb_bit_rsvd
= 0;
4423 u64 gbpages_bit_rsvd
= 0;
4424 u64 nonleaf_bit8_rsvd
= 0;
4426 rsvd_check
->bad_mt_xwr
= 0;
4429 exb_bit_rsvd
= rsvd_bits(63, 63);
4431 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4434 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4435 * leaf entries) on AMD CPUs only.
4438 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4441 case PT32_ROOT_LEVEL
:
4442 /* no rsvd bits for 2 level 4K page table entries */
4443 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4444 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4445 rsvd_check
->rsvd_bits_mask
[1][0] =
4446 rsvd_check
->rsvd_bits_mask
[0][0];
4449 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4453 if (is_cpuid_PSE36())
4454 /* 36bits PSE 4MB page */
4455 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4457 /* 32 bits PSE 4MB page */
4458 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4460 case PT32E_ROOT_LEVEL
:
4461 rsvd_check
->rsvd_bits_mask
[0][2] =
4462 rsvd_bits(maxphyaddr
, 63) |
4463 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4464 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4465 rsvd_bits(maxphyaddr
, 62); /* PDE */
4466 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4467 rsvd_bits(maxphyaddr
, 62); /* PTE */
4468 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4469 rsvd_bits(maxphyaddr
, 62) |
4470 rsvd_bits(13, 20); /* large page */
4471 rsvd_check
->rsvd_bits_mask
[1][0] =
4472 rsvd_check
->rsvd_bits_mask
[0][0];
4474 case PT64_ROOT_5LEVEL
:
4475 rsvd_check
->rsvd_bits_mask
[0][4] = exb_bit_rsvd
|
4476 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4477 rsvd_bits(maxphyaddr
, 51);
4478 rsvd_check
->rsvd_bits_mask
[1][4] =
4479 rsvd_check
->rsvd_bits_mask
[0][4];
4481 case PT64_ROOT_4LEVEL
:
4482 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
4483 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4484 rsvd_bits(maxphyaddr
, 51);
4485 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
4486 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
4487 rsvd_bits(maxphyaddr
, 51);
4488 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4489 rsvd_bits(maxphyaddr
, 51);
4490 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4491 rsvd_bits(maxphyaddr
, 51);
4492 rsvd_check
->rsvd_bits_mask
[1][3] =
4493 rsvd_check
->rsvd_bits_mask
[0][3];
4494 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
4495 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
4497 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4498 rsvd_bits(maxphyaddr
, 51) |
4499 rsvd_bits(13, 20); /* large page */
4500 rsvd_check
->rsvd_bits_mask
[1][0] =
4501 rsvd_check
->rsvd_bits_mask
[0][0];
4506 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4507 struct kvm_mmu
*context
)
4509 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4510 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4512 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4514 guest_cpuid_is_amd_or_hygon(vcpu
));
4518 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4519 int maxphyaddr
, bool execonly
)
4523 rsvd_check
->rsvd_bits_mask
[0][4] =
4524 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4525 rsvd_check
->rsvd_bits_mask
[0][3] =
4526 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4527 rsvd_check
->rsvd_bits_mask
[0][2] =
4528 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4529 rsvd_check
->rsvd_bits_mask
[0][1] =
4530 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4531 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4534 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4535 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4536 rsvd_check
->rsvd_bits_mask
[1][2] =
4537 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4538 rsvd_check
->rsvd_bits_mask
[1][1] =
4539 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4540 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4542 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4543 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4544 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4545 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4546 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4548 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4549 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4551 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4554 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4555 struct kvm_mmu
*context
, bool execonly
)
4557 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4558 cpuid_maxphyaddr(vcpu
), execonly
);
4562 * the page table on host is the shadow page table for the page
4563 * table in guest or amd nested guest, its mmu features completely
4564 * follow the features in guest.
4567 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4569 bool uses_nx
= context
->nx
||
4570 context
->mmu_role
.base
.smep_andnot_wp
;
4571 struct rsvd_bits_validate
*shadow_zero_check
;
4575 * Passing "true" to the last argument is okay; it adds a check
4576 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4578 shadow_zero_check
= &context
->shadow_zero_check
;
4579 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4581 context
->shadow_root_level
, uses_nx
,
4582 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4583 is_pse(vcpu
), true);
4585 if (!shadow_me_mask
)
4588 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4589 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4590 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4594 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4596 static inline bool boot_cpu_is_amd(void)
4598 WARN_ON_ONCE(!tdp_enabled
);
4599 return shadow_x_mask
== 0;
4603 * the direct page table on host, use as much mmu features as
4604 * possible, however, kvm currently does not do execution-protection.
4607 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4608 struct kvm_mmu
*context
)
4610 struct rsvd_bits_validate
*shadow_zero_check
;
4613 shadow_zero_check
= &context
->shadow_zero_check
;
4615 if (boot_cpu_is_amd())
4616 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4618 context
->shadow_root_level
, false,
4619 boot_cpu_has(X86_FEATURE_GBPAGES
),
4622 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4626 if (!shadow_me_mask
)
4629 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4630 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4631 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4636 * as the comments in reset_shadow_zero_bits_mask() except it
4637 * is the shadow page table for intel nested guest.
4640 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4641 struct kvm_mmu
*context
, bool execonly
)
4643 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4644 shadow_phys_bits
, execonly
);
4647 #define BYTE_MASK(access) \
4648 ((1 & (access) ? 2 : 0) | \
4649 (2 & (access) ? 4 : 0) | \
4650 (3 & (access) ? 8 : 0) | \
4651 (4 & (access) ? 16 : 0) | \
4652 (5 & (access) ? 32 : 0) | \
4653 (6 & (access) ? 64 : 0) | \
4654 (7 & (access) ? 128 : 0))
4657 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4658 struct kvm_mmu
*mmu
, bool ept
)
4662 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4663 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4664 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4666 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4667 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4668 bool cr0_wp
= is_write_protection(vcpu
);
4670 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4671 unsigned pfec
= byte
<< 1;
4674 * Each "*f" variable has a 1 bit for each UWX value
4675 * that causes a fault with the given PFEC.
4678 /* Faults from writes to non-writable pages */
4679 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? (u8
)~w
: 0;
4680 /* Faults from user mode accesses to supervisor pages */
4681 u8 uf
= (pfec
& PFERR_USER_MASK
) ? (u8
)~u
: 0;
4682 /* Faults from fetches of non-executable pages*/
4683 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? (u8
)~x
: 0;
4684 /* Faults from kernel mode fetches of user pages */
4686 /* Faults from kernel mode accesses of user pages */
4690 /* Faults from kernel mode accesses to user pages */
4691 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4693 /* Not really needed: !nx will cause pte.nx to fault */
4697 /* Allow supervisor writes if !cr0.wp */
4699 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4701 /* Disallow supervisor fetches of user code if cr4.smep */
4703 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4706 * SMAP:kernel-mode data accesses from user-mode
4707 * mappings should fault. A fault is considered
4708 * as a SMAP violation if all of the following
4709 * conditions are true:
4710 * - X86_CR4_SMAP is set in CR4
4711 * - A user page is accessed
4712 * - The access is not a fetch
4713 * - Page fault in kernel mode
4714 * - if CPL = 3 or X86_EFLAGS_AC is clear
4716 * Here, we cover the first three conditions.
4717 * The fourth is computed dynamically in permission_fault();
4718 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4719 * *not* subject to SMAP restrictions.
4722 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4725 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4730 * PKU is an additional mechanism by which the paging controls access to
4731 * user-mode addresses based on the value in the PKRU register. Protection
4732 * key violations are reported through a bit in the page fault error code.
4733 * Unlike other bits of the error code, the PK bit is not known at the
4734 * call site of e.g. gva_to_gpa; it must be computed directly in
4735 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4736 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4738 * In particular the following conditions come from the error code, the
4739 * page tables and the machine state:
4740 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4741 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4742 * - PK is always zero if U=0 in the page tables
4743 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4745 * The PKRU bitmask caches the result of these four conditions. The error
4746 * code (minus the P bit) and the page table's U bit form an index into the
4747 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4748 * with the two bits of the PKRU register corresponding to the protection key.
4749 * For the first three conditions above the bits will be 00, thus masking
4750 * away both AD and WD. For all reads or if the last condition holds, WD
4751 * only will be masked away.
4753 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4764 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4765 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4770 wp
= is_write_protection(vcpu
);
4772 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4773 unsigned pfec
, pkey_bits
;
4774 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4777 ff
= pfec
& PFERR_FETCH_MASK
;
4778 uf
= pfec
& PFERR_USER_MASK
;
4779 wf
= pfec
& PFERR_WRITE_MASK
;
4781 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4782 pte_user
= pfec
& PFERR_RSVD_MASK
;
4785 * Only need to check the access which is not an
4786 * instruction fetch and is to a user page.
4788 check_pkey
= (!ff
&& pte_user
);
4790 * write access is controlled by PKRU if it is a
4791 * user access or CR0.WP = 1.
4793 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4795 /* PKRU.AD stops both read and write access. */
4796 pkey_bits
= !!check_pkey
;
4797 /* PKRU.WD stops write access. */
4798 pkey_bits
|= (!!check_write
) << 1;
4800 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4804 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4806 unsigned root_level
= mmu
->root_level
;
4808 mmu
->last_nonleaf_level
= root_level
;
4809 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4810 mmu
->last_nonleaf_level
++;
4813 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4814 struct kvm_mmu
*context
,
4817 context
->nx
= is_nx(vcpu
);
4818 context
->root_level
= level
;
4820 reset_rsvds_bits_mask(vcpu
, context
);
4821 update_permission_bitmask(vcpu
, context
, false);
4822 update_pkru_bitmask(vcpu
, context
, false);
4823 update_last_nonleaf_level(vcpu
, context
);
4825 MMU_WARN_ON(!is_pae(vcpu
));
4826 context
->page_fault
= paging64_page_fault
;
4827 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4828 context
->sync_page
= paging64_sync_page
;
4829 context
->invlpg
= paging64_invlpg
;
4830 context
->update_pte
= paging64_update_pte
;
4831 context
->shadow_root_level
= level
;
4832 context
->direct_map
= false;
4835 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4836 struct kvm_mmu
*context
)
4838 int root_level
= is_la57_mode(vcpu
) ?
4839 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4841 paging64_init_context_common(vcpu
, context
, root_level
);
4844 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4845 struct kvm_mmu
*context
)
4847 context
->nx
= false;
4848 context
->root_level
= PT32_ROOT_LEVEL
;
4850 reset_rsvds_bits_mask(vcpu
, context
);
4851 update_permission_bitmask(vcpu
, context
, false);
4852 update_pkru_bitmask(vcpu
, context
, false);
4853 update_last_nonleaf_level(vcpu
, context
);
4855 context
->page_fault
= paging32_page_fault
;
4856 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4857 context
->sync_page
= paging32_sync_page
;
4858 context
->invlpg
= paging32_invlpg
;
4859 context
->update_pte
= paging32_update_pte
;
4860 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4861 context
->direct_map
= false;
4864 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4865 struct kvm_mmu
*context
)
4867 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4870 static union kvm_mmu_extended_role
kvm_calc_mmu_role_ext(struct kvm_vcpu
*vcpu
)
4872 union kvm_mmu_extended_role ext
= {0};
4874 ext
.cr0_pg
= !!is_paging(vcpu
);
4875 ext
.cr4_pae
= !!is_pae(vcpu
);
4876 ext
.cr4_smep
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4877 ext
.cr4_smap
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4878 ext
.cr4_pse
= !!is_pse(vcpu
);
4879 ext
.cr4_pke
= !!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
);
4880 ext
.maxphyaddr
= cpuid_maxphyaddr(vcpu
);
4887 static union kvm_mmu_role
kvm_calc_mmu_role_common(struct kvm_vcpu
*vcpu
,
4890 union kvm_mmu_role role
= {0};
4892 role
.base
.access
= ACC_ALL
;
4893 role
.base
.nxe
= !!is_nx(vcpu
);
4894 role
.base
.cr0_wp
= is_write_protection(vcpu
);
4895 role
.base
.smm
= is_smm(vcpu
);
4896 role
.base
.guest_mode
= is_guest_mode(vcpu
);
4901 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
4906 static union kvm_mmu_role
4907 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4909 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4911 role
.base
.ad_disabled
= (shadow_accessed_mask
== 0);
4912 role
.base
.level
= kvm_x86_ops
.get_tdp_level(vcpu
);
4913 role
.base
.direct
= true;
4914 role
.base
.gpte_is_8_bytes
= true;
4919 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4921 struct kvm_mmu
*context
= vcpu
->arch
.mmu
;
4922 union kvm_mmu_role new_role
=
4923 kvm_calc_tdp_mmu_root_page_role(vcpu
, false);
4925 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4928 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4929 context
->page_fault
= kvm_tdp_page_fault
;
4930 context
->sync_page
= nonpaging_sync_page
;
4931 context
->invlpg
= nonpaging_invlpg
;
4932 context
->update_pte
= nonpaging_update_pte
;
4933 context
->shadow_root_level
= kvm_x86_ops
.get_tdp_level(vcpu
);
4934 context
->direct_map
= true;
4935 context
->get_guest_pgd
= get_cr3
;
4936 context
->get_pdptr
= kvm_pdptr_read
;
4937 context
->inject_page_fault
= kvm_inject_page_fault
;
4939 if (!is_paging(vcpu
)) {
4940 context
->nx
= false;
4941 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4942 context
->root_level
= 0;
4943 } else if (is_long_mode(vcpu
)) {
4944 context
->nx
= is_nx(vcpu
);
4945 context
->root_level
= is_la57_mode(vcpu
) ?
4946 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4947 reset_rsvds_bits_mask(vcpu
, context
);
4948 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4949 } else if (is_pae(vcpu
)) {
4950 context
->nx
= is_nx(vcpu
);
4951 context
->root_level
= PT32E_ROOT_LEVEL
;
4952 reset_rsvds_bits_mask(vcpu
, context
);
4953 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4955 context
->nx
= false;
4956 context
->root_level
= PT32_ROOT_LEVEL
;
4957 reset_rsvds_bits_mask(vcpu
, context
);
4958 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4961 update_permission_bitmask(vcpu
, context
, false);
4962 update_pkru_bitmask(vcpu
, context
, false);
4963 update_last_nonleaf_level(vcpu
, context
);
4964 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4967 static union kvm_mmu_role
4968 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu
*vcpu
, bool base_only
)
4970 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, base_only
);
4972 role
.base
.smep_andnot_wp
= role
.ext
.cr4_smep
&&
4973 !is_write_protection(vcpu
);
4974 role
.base
.smap_andnot_wp
= role
.ext
.cr4_smap
&&
4975 !is_write_protection(vcpu
);
4976 role
.base
.direct
= !is_paging(vcpu
);
4977 role
.base
.gpte_is_8_bytes
= !!is_pae(vcpu
);
4979 if (!is_long_mode(vcpu
))
4980 role
.base
.level
= PT32E_ROOT_LEVEL
;
4981 else if (is_la57_mode(vcpu
))
4982 role
.base
.level
= PT64_ROOT_5LEVEL
;
4984 role
.base
.level
= PT64_ROOT_4LEVEL
;
4989 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4991 struct kvm_mmu
*context
= vcpu
->arch
.mmu
;
4992 union kvm_mmu_role new_role
=
4993 kvm_calc_shadow_mmu_root_page_role(vcpu
, false);
4995 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4998 if (!is_paging(vcpu
))
4999 nonpaging_init_context(vcpu
, context
);
5000 else if (is_long_mode(vcpu
))
5001 paging64_init_context(vcpu
, context
);
5002 else if (is_pae(vcpu
))
5003 paging32E_init_context(vcpu
, context
);
5005 paging32_init_context(vcpu
, context
);
5007 context
->mmu_role
.as_u64
= new_role
.as_u64
;
5008 reset_shadow_zero_bits_mask(vcpu
, context
);
5010 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
5012 static union kvm_mmu_role
5013 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu
*vcpu
, bool accessed_dirty
,
5014 bool execonly
, u8 level
)
5016 union kvm_mmu_role role
= {0};
5018 /* SMM flag is inherited from root_mmu */
5019 role
.base
.smm
= vcpu
->arch
.root_mmu
.mmu_role
.base
.smm
;
5021 role
.base
.level
= level
;
5022 role
.base
.gpte_is_8_bytes
= true;
5023 role
.base
.direct
= false;
5024 role
.base
.ad_disabled
= !accessed_dirty
;
5025 role
.base
.guest_mode
= true;
5026 role
.base
.access
= ACC_ALL
;
5029 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
5030 * SMAP variation to denote shadow EPT entries.
5032 role
.base
.cr0_wp
= true;
5033 role
.base
.smap_andnot_wp
= true;
5035 role
.ext
= kvm_calc_mmu_role_ext(vcpu
);
5036 role
.ext
.execonly
= execonly
;
5041 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
5042 bool accessed_dirty
, gpa_t new_eptp
)
5044 struct kvm_mmu
*context
= vcpu
->arch
.mmu
;
5045 u8 level
= vmx_eptp_page_walk_level(new_eptp
);
5046 union kvm_mmu_role new_role
=
5047 kvm_calc_shadow_ept_root_page_role(vcpu
, accessed_dirty
,
5050 __kvm_mmu_new_cr3(vcpu
, new_eptp
, new_role
.base
, false);
5052 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
5055 context
->shadow_root_level
= level
;
5058 context
->ept_ad
= accessed_dirty
;
5059 context
->page_fault
= ept_page_fault
;
5060 context
->gva_to_gpa
= ept_gva_to_gpa
;
5061 context
->sync_page
= ept_sync_page
;
5062 context
->invlpg
= ept_invlpg
;
5063 context
->update_pte
= ept_update_pte
;
5064 context
->root_level
= level
;
5065 context
->direct_map
= false;
5066 context
->mmu_role
.as_u64
= new_role
.as_u64
;
5068 update_permission_bitmask(vcpu
, context
, true);
5069 update_pkru_bitmask(vcpu
, context
, true);
5070 update_last_nonleaf_level(vcpu
, context
);
5071 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
5072 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
5074 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
5076 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
5078 struct kvm_mmu
*context
= vcpu
->arch
.mmu
;
5080 kvm_init_shadow_mmu(vcpu
);
5081 context
->get_guest_pgd
= get_cr3
;
5082 context
->get_pdptr
= kvm_pdptr_read
;
5083 context
->inject_page_fault
= kvm_inject_page_fault
;
5086 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
5088 union kvm_mmu_role new_role
= kvm_calc_mmu_role_common(vcpu
, false);
5089 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
5091 if (new_role
.as_u64
== g_context
->mmu_role
.as_u64
)
5094 g_context
->mmu_role
.as_u64
= new_role
.as_u64
;
5095 g_context
->get_guest_pgd
= get_cr3
;
5096 g_context
->get_pdptr
= kvm_pdptr_read
;
5097 g_context
->inject_page_fault
= kvm_inject_page_fault
;
5100 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
5101 * L1's nested page tables (e.g. EPT12). The nested translation
5102 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
5103 * L2's page tables as the first level of translation and L1's
5104 * nested page tables as the second level of translation. Basically
5105 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
5107 if (!is_paging(vcpu
)) {
5108 g_context
->nx
= false;
5109 g_context
->root_level
= 0;
5110 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
5111 } else if (is_long_mode(vcpu
)) {
5112 g_context
->nx
= is_nx(vcpu
);
5113 g_context
->root_level
= is_la57_mode(vcpu
) ?
5114 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
5115 reset_rsvds_bits_mask(vcpu
, g_context
);
5116 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
5117 } else if (is_pae(vcpu
)) {
5118 g_context
->nx
= is_nx(vcpu
);
5119 g_context
->root_level
= PT32E_ROOT_LEVEL
;
5120 reset_rsvds_bits_mask(vcpu
, g_context
);
5121 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
5123 g_context
->nx
= false;
5124 g_context
->root_level
= PT32_ROOT_LEVEL
;
5125 reset_rsvds_bits_mask(vcpu
, g_context
);
5126 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
5129 update_permission_bitmask(vcpu
, g_context
, false);
5130 update_pkru_bitmask(vcpu
, g_context
, false);
5131 update_last_nonleaf_level(vcpu
, g_context
);
5134 void kvm_init_mmu(struct kvm_vcpu
*vcpu
, bool reset_roots
)
5139 vcpu
->arch
.mmu
->root_hpa
= INVALID_PAGE
;
5141 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5142 vcpu
->arch
.mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5145 if (mmu_is_nested(vcpu
))
5146 init_kvm_nested_mmu(vcpu
);
5147 else if (tdp_enabled
)
5148 init_kvm_tdp_mmu(vcpu
);
5150 init_kvm_softmmu(vcpu
);
5152 EXPORT_SYMBOL_GPL(kvm_init_mmu
);
5154 static union kvm_mmu_page_role
5155 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
)
5157 union kvm_mmu_role role
;
5160 role
= kvm_calc_tdp_mmu_root_page_role(vcpu
, true);
5162 role
= kvm_calc_shadow_mmu_root_page_role(vcpu
, true);
5167 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
5169 kvm_mmu_unload(vcpu
);
5170 kvm_init_mmu(vcpu
, true);
5172 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
5174 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
5178 r
= mmu_topup_memory_caches(vcpu
);
5181 r
= mmu_alloc_roots(vcpu
);
5182 kvm_mmu_sync_roots(vcpu
);
5185 kvm_mmu_load_pgd(vcpu
);
5186 kvm_x86_ops
.tlb_flush(vcpu
, true);
5190 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
5192 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
5194 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.root_mmu
, KVM_MMU_ROOTS_ALL
);
5195 WARN_ON(VALID_PAGE(vcpu
->arch
.root_mmu
.root_hpa
));
5196 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
5197 WARN_ON(VALID_PAGE(vcpu
->arch
.guest_mmu
.root_hpa
));
5199 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
5201 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
5202 struct kvm_mmu_page
*sp
, u64
*spte
,
5205 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
5206 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
5210 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
5211 vcpu
->arch
.mmu
->update_pte(vcpu
, sp
, spte
, new);
5214 static bool need_remote_flush(u64 old
, u64
new)
5216 if (!is_shadow_present_pte(old
))
5218 if (!is_shadow_present_pte(new))
5220 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
5222 old
^= shadow_nx_mask
;
5223 new ^= shadow_nx_mask
;
5224 return (old
& ~new & PT64_PERM_MASK
) != 0;
5227 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
5234 * Assume that the pte write on a page table of the same type
5235 * as the current vcpu paging mode since we update the sptes only
5236 * when they have the same mode.
5238 if (is_pae(vcpu
) && *bytes
== 4) {
5239 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5244 if (*bytes
== 4 || *bytes
== 8) {
5245 r
= kvm_vcpu_read_guest_atomic(vcpu
, *gpa
, &gentry
, *bytes
);
5254 * If we're seeing too many writes to a page, it may no longer be a page table,
5255 * or we may be forking, in which case it is better to unmap the page.
5257 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
5260 * Skip write-flooding detected for the sp whose level is 1, because
5261 * it can become unsync, then the guest page is not write-protected.
5263 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
5266 atomic_inc(&sp
->write_flooding_count
);
5267 return atomic_read(&sp
->write_flooding_count
) >= 3;
5271 * Misaligned accesses are too much trouble to fix up; also, they usually
5272 * indicate a page is not used as a page table.
5274 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
5277 unsigned offset
, pte_size
, misaligned
;
5279 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5280 gpa
, bytes
, sp
->role
.word
);
5282 offset
= offset_in_page(gpa
);
5283 pte_size
= sp
->role
.gpte_is_8_bytes
? 8 : 4;
5286 * Sometimes, the OS only writes the last one bytes to update status
5287 * bits, for example, in linux, andb instruction is used in clear_bit().
5289 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
5292 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
5293 misaligned
|= bytes
< 4;
5298 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
5300 unsigned page_offset
, quadrant
;
5304 page_offset
= offset_in_page(gpa
);
5305 level
= sp
->role
.level
;
5307 if (!sp
->role
.gpte_is_8_bytes
) {
5308 page_offset
<<= 1; /* 32->64 */
5310 * A 32-bit pde maps 4MB while the shadow pdes map
5311 * only 2MB. So we need to double the offset again
5312 * and zap two pdes instead of one.
5314 if (level
== PT32_ROOT_LEVEL
) {
5315 page_offset
&= ~7; /* kill rounding error */
5319 quadrant
= page_offset
>> PAGE_SHIFT
;
5320 page_offset
&= ~PAGE_MASK
;
5321 if (quadrant
!= sp
->role
.quadrant
)
5325 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
5330 * Ignore various flags when determining if a SPTE can be immediately
5331 * overwritten for the current MMU.
5332 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
5333 * match the current MMU role, as MMU's level tracks the root level.
5334 * - access: updated based on the new guest PTE
5335 * - quadrant: handled by get_written_sptes()
5336 * - invalid: always false (loop only walks valid shadow pages)
5338 static const union kvm_mmu_page_role role_ign
= {
5345 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
5346 const u8
*new, int bytes
,
5347 struct kvm_page_track_notifier_node
*node
)
5349 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
5350 struct kvm_mmu_page
*sp
;
5351 LIST_HEAD(invalid_list
);
5352 u64 entry
, gentry
, *spte
;
5354 bool remote_flush
, local_flush
;
5357 * If we don't have indirect shadow pages, it means no page is
5358 * write-protected, so we can exit simply.
5360 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
5363 remote_flush
= local_flush
= false;
5365 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
5368 * No need to care whether allocation memory is successful
5369 * or not since pte prefetch is skiped if it does not have
5370 * enough objects in the cache.
5372 mmu_topup_memory_caches(vcpu
);
5374 spin_lock(&vcpu
->kvm
->mmu_lock
);
5376 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, &bytes
);
5378 ++vcpu
->kvm
->stat
.mmu_pte_write
;
5379 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
5381 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
5382 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
5383 detect_write_flooding(sp
)) {
5384 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
5385 ++vcpu
->kvm
->stat
.mmu_flooded
;
5389 spte
= get_written_sptes(sp
, gpa
, &npte
);
5395 u32 base_role
= vcpu
->arch
.mmu
->mmu_role
.base
.word
;
5398 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
5400 !((sp
->role
.word
^ base_role
) & ~role_ign
.word
) &&
5402 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
5403 if (need_remote_flush(entry
, *spte
))
5404 remote_flush
= true;
5408 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
5409 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
5410 spin_unlock(&vcpu
->kvm
->mmu_lock
);
5413 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
5418 if (vcpu
->arch
.mmu
->direct_map
)
5421 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
5423 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
5427 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
5429 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
, u64 error_code
,
5430 void *insn
, int insn_len
)
5432 int r
, emulation_type
= EMULTYPE_PF
;
5433 bool direct
= vcpu
->arch
.mmu
->direct_map
;
5435 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
5436 return RET_PF_RETRY
;
5439 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
5440 r
= handle_mmio_page_fault(vcpu
, cr2_or_gpa
, direct
);
5441 if (r
== RET_PF_EMULATE
)
5445 if (r
== RET_PF_INVALID
) {
5446 r
= kvm_mmu_do_page_fault(vcpu
, cr2_or_gpa
,
5447 lower_32_bits(error_code
), false);
5448 WARN_ON(r
== RET_PF_INVALID
);
5451 if (r
== RET_PF_RETRY
)
5457 * Before emulating the instruction, check if the error code
5458 * was due to a RO violation while translating the guest page.
5459 * This can occur when using nested virtualization with nested
5460 * paging in both guests. If true, we simply unprotect the page
5461 * and resume the guest.
5463 if (vcpu
->arch
.mmu
->direct_map
&&
5464 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
5465 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2_or_gpa
));
5470 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5471 * optimistically try to just unprotect the page and let the processor
5472 * re-execute the instruction that caused the page fault. Do not allow
5473 * retrying MMIO emulation, as it's not only pointless but could also
5474 * cause us to enter an infinite loop because the processor will keep
5475 * faulting on the non-existent MMIO address. Retrying an instruction
5476 * from a nested guest is also pointless and dangerous as we are only
5477 * explicitly shadowing L1's page tables, i.e. unprotecting something
5478 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5480 if (!mmio_info_in_cache(vcpu
, cr2_or_gpa
, direct
) && !is_guest_mode(vcpu
))
5481 emulation_type
|= EMULTYPE_ALLOW_RETRY_PF
;
5484 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5485 * This can happen if a guest gets a page-fault on data access but the HW
5486 * table walker is not able to read the instruction page (e.g instruction
5487 * page is not present in memory). In those cases we simply restart the
5488 * guest, with the exception of AMD Erratum 1096 which is unrecoverable.
5490 if (unlikely(insn
&& !insn_len
)) {
5491 if (!kvm_x86_ops
.need_emulation_on_page_fault(vcpu
))
5495 return x86_emulate_instruction(vcpu
, cr2_or_gpa
, emulation_type
, insn
,
5498 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
5500 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
5502 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5505 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5506 if (is_noncanonical_address(gva
, vcpu
))
5509 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5512 * INVLPG is required to invalidate any global mappings for the VA,
5513 * irrespective of PCID. Since it would take us roughly similar amount
5514 * of work to determine whether any of the prev_root mappings of the VA
5515 * is marked global, or to just sync it blindly, so we might as well
5516 * just always sync it.
5518 * Mappings not reachable via the current cr3 or the prev_roots will be
5519 * synced when switching to that cr3, so nothing needs to be done here
5522 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5523 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
5524 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5526 kvm_x86_ops
.tlb_flush_gva(vcpu
, gva
);
5527 ++vcpu
->stat
.invlpg
;
5529 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
5531 void kvm_mmu_invpcid_gva(struct kvm_vcpu
*vcpu
, gva_t gva
, unsigned long pcid
)
5533 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5534 bool tlb_flush
= false;
5537 if (pcid
== kvm_get_active_pcid(vcpu
)) {
5538 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5542 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
5543 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
) &&
5544 pcid
== kvm_get_pcid(vcpu
, mmu
->prev_roots
[i
].cr3
)) {
5545 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5551 kvm_x86_ops
.tlb_flush_gva(vcpu
, gva
);
5553 ++vcpu
->stat
.invlpg
;
5556 * Mappings not reachable via the current cr3 or the prev_roots will be
5557 * synced when switching to that cr3, so nothing needs to be done here
5561 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva
);
5563 void kvm_configure_mmu(bool enable_tdp
, int tdp_page_level
)
5565 tdp_enabled
= enable_tdp
;
5568 * max_page_level reflects the capabilities of KVM's MMU irrespective
5569 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5570 * the kernel is not. But, KVM never creates a page size greater than
5571 * what is used by the kernel for any given HVA, i.e. the kernel's
5572 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5575 max_page_level
= tdp_page_level
;
5576 else if (boot_cpu_has(X86_FEATURE_GBPAGES
))
5577 max_page_level
= PT_PDPE_LEVEL
;
5579 max_page_level
= PT_DIRECTORY_LEVEL
;
5581 EXPORT_SYMBOL_GPL(kvm_configure_mmu
);
5583 /* The return value indicates if tlb flush on all vcpus is needed. */
5584 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
5586 /* The caller should hold mmu-lock before calling this function. */
5587 static __always_inline
bool
5588 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5589 slot_level_handler fn
, int start_level
, int end_level
,
5590 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5592 struct slot_rmap_walk_iterator iterator
;
5595 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5596 end_gfn
, &iterator
) {
5598 flush
|= fn(kvm
, iterator
.rmap
);
5600 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5601 if (flush
&& lock_flush_tlb
) {
5602 kvm_flush_remote_tlbs_with_address(kvm
,
5604 iterator
.gfn
- start_gfn
+ 1);
5607 cond_resched_lock(&kvm
->mmu_lock
);
5611 if (flush
&& lock_flush_tlb
) {
5612 kvm_flush_remote_tlbs_with_address(kvm
, start_gfn
,
5613 end_gfn
- start_gfn
+ 1);
5620 static __always_inline
bool
5621 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5622 slot_level_handler fn
, int start_level
, int end_level
,
5623 bool lock_flush_tlb
)
5625 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5626 end_level
, memslot
->base_gfn
,
5627 memslot
->base_gfn
+ memslot
->npages
- 1,
5631 static __always_inline
bool
5632 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5633 slot_level_handler fn
, bool lock_flush_tlb
)
5635 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5636 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5639 static __always_inline
bool
5640 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5641 slot_level_handler fn
, bool lock_flush_tlb
)
5643 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
5644 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5647 static __always_inline
bool
5648 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5649 slot_level_handler fn
, bool lock_flush_tlb
)
5651 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5652 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
5655 static void free_mmu_pages(struct kvm_mmu
*mmu
)
5657 free_page((unsigned long)mmu
->pae_root
);
5658 free_page((unsigned long)mmu
->lm_root
);
5661 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
5667 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5668 * while the PDP table is a per-vCPU construct that's allocated at MMU
5669 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5670 * x86_64. Therefore we need to allocate the PDP table in the first
5671 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5672 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5673 * skip allocating the PDP table.
5675 if (tdp_enabled
&& kvm_x86_ops
.get_tdp_level(vcpu
) > PT32E_ROOT_LEVEL
)
5678 page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_DMA32
);
5682 mmu
->pae_root
= page_address(page
);
5683 for (i
= 0; i
< 4; ++i
)
5684 mmu
->pae_root
[i
] = INVALID_PAGE
;
5689 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5694 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
5695 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
5697 vcpu
->arch
.root_mmu
.root_hpa
= INVALID_PAGE
;
5698 vcpu
->arch
.root_mmu
.root_cr3
= 0;
5699 vcpu
->arch
.root_mmu
.translate_gpa
= translate_gpa
;
5700 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5701 vcpu
->arch
.root_mmu
.prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5703 vcpu
->arch
.guest_mmu
.root_hpa
= INVALID_PAGE
;
5704 vcpu
->arch
.guest_mmu
.root_cr3
= 0;
5705 vcpu
->arch
.guest_mmu
.translate_gpa
= translate_gpa
;
5706 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5707 vcpu
->arch
.guest_mmu
.prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5709 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5711 ret
= alloc_mmu_pages(vcpu
, &vcpu
->arch
.guest_mmu
);
5715 ret
= alloc_mmu_pages(vcpu
, &vcpu
->arch
.root_mmu
);
5717 goto fail_allocate_root
;
5721 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5725 #define BATCH_ZAP_PAGES 10
5726 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5728 struct kvm_mmu_page
*sp
, *node
;
5729 int nr_zapped
, batch
= 0;
5732 list_for_each_entry_safe_reverse(sp
, node
,
5733 &kvm
->arch
.active_mmu_pages
, link
) {
5735 * No obsolete valid page exists before a newly created page
5736 * since active_mmu_pages is a FIFO list.
5738 if (!is_obsolete_sp(kvm
, sp
))
5742 * Skip invalid pages with a non-zero root count, zapping pages
5743 * with a non-zero root count will never succeed, i.e. the page
5744 * will get thrown back on active_mmu_pages and we'll get stuck
5745 * in an infinite loop.
5747 if (sp
->role
.invalid
&& sp
->root_count
)
5751 * No need to flush the TLB since we're only zapping shadow
5752 * pages with an obsolete generation number and all vCPUS have
5753 * loaded a new root, i.e. the shadow pages being zapped cannot
5754 * be in active use by the guest.
5756 if (batch
>= BATCH_ZAP_PAGES
&&
5757 cond_resched_lock(&kvm
->mmu_lock
)) {
5762 if (__kvm_mmu_prepare_zap_page(kvm
, sp
,
5763 &kvm
->arch
.zapped_obsolete_pages
, &nr_zapped
)) {
5770 * Trigger a remote TLB flush before freeing the page tables to ensure
5771 * KVM is not in the middle of a lockless shadow page table walk, which
5772 * may reference the pages.
5774 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5778 * Fast invalidate all shadow pages and use lock-break technique
5779 * to zap obsolete pages.
5781 * It's required when memslot is being deleted or VM is being
5782 * destroyed, in these cases, we should ensure that KVM MMU does
5783 * not use any resource of the being-deleted slot or all slots
5784 * after calling the function.
5786 static void kvm_mmu_zap_all_fast(struct kvm
*kvm
)
5788 lockdep_assert_held(&kvm
->slots_lock
);
5790 spin_lock(&kvm
->mmu_lock
);
5791 trace_kvm_mmu_zap_all_fast(kvm
);
5794 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5795 * held for the entire duration of zapping obsolete pages, it's
5796 * impossible for there to be multiple invalid generations associated
5797 * with *valid* shadow pages at any given time, i.e. there is exactly
5798 * one valid generation and (at most) one invalid generation.
5800 kvm
->arch
.mmu_valid_gen
= kvm
->arch
.mmu_valid_gen
? 0 : 1;
5803 * Notify all vcpus to reload its shadow page table and flush TLB.
5804 * Then all vcpus will switch to new shadow page table with the new
5807 * Note: we need to do this under the protection of mmu_lock,
5808 * otherwise, vcpu would purge shadow page but miss tlb flush.
5810 kvm_reload_remote_mmus(kvm
);
5812 kvm_zap_obsolete_pages(kvm
);
5813 spin_unlock(&kvm
->mmu_lock
);
5816 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5818 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5821 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5822 struct kvm_memory_slot
*slot
,
5823 struct kvm_page_track_notifier_node
*node
)
5825 kvm_mmu_zap_all_fast(kvm
);
5828 void kvm_mmu_init_vm(struct kvm
*kvm
)
5830 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5832 node
->track_write
= kvm_mmu_pte_write
;
5833 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5834 kvm_page_track_register_notifier(kvm
, node
);
5837 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5839 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5841 kvm_page_track_unregister_notifier(kvm
, node
);
5844 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5846 struct kvm_memslots
*slots
;
5847 struct kvm_memory_slot
*memslot
;
5850 spin_lock(&kvm
->mmu_lock
);
5851 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5852 slots
= __kvm_memslots(kvm
, i
);
5853 kvm_for_each_memslot(memslot
, slots
) {
5856 start
= max(gfn_start
, memslot
->base_gfn
);
5857 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5861 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5862 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
5863 start
, end
- 1, true);
5867 spin_unlock(&kvm
->mmu_lock
);
5870 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5871 struct kvm_rmap_head
*rmap_head
)
5873 return __rmap_write_protect(kvm
, rmap_head
, false);
5876 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5877 struct kvm_memory_slot
*memslot
,
5882 spin_lock(&kvm
->mmu_lock
);
5883 flush
= slot_handle_level(kvm
, memslot
, slot_rmap_write_protect
,
5884 start_level
, PT_MAX_HUGEPAGE_LEVEL
, false);
5885 spin_unlock(&kvm
->mmu_lock
);
5888 * We can flush all the TLBs out of the mmu lock without TLB
5889 * corruption since we just change the spte from writable to
5890 * readonly so that we only need to care the case of changing
5891 * spte from present to present (changing the spte from present
5892 * to nonpresent will flush all the TLBs immediately), in other
5893 * words, the only case we care is mmu_spte_update() where we
5894 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5895 * instead of PT_WRITABLE_MASK, that means it does not depend
5896 * on PT_WRITABLE_MASK anymore.
5899 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5902 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5903 struct kvm_rmap_head
*rmap_head
)
5906 struct rmap_iterator iter
;
5907 int need_tlb_flush
= 0;
5909 struct kvm_mmu_page
*sp
;
5912 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5913 sp
= page_header(__pa(sptep
));
5914 pfn
= spte_to_pfn(*sptep
);
5917 * We cannot do huge page mapping for indirect shadow pages,
5918 * which are found on the last rmap (level = 1) when not using
5919 * tdp; such shadow pages are synced with the page table in
5920 * the guest, and the guest page table is using 4K page size
5921 * mapping if the indirect sp has level = 1.
5923 if (sp
->role
.direct
&& !kvm_is_reserved_pfn(pfn
) &&
5924 (kvm_is_zone_device_pfn(pfn
) ||
5925 PageCompound(pfn_to_page(pfn
)))) {
5926 pte_list_remove(rmap_head
, sptep
);
5928 if (kvm_available_flush_tlb_with_range())
5929 kvm_flush_remote_tlbs_with_address(kvm
, sp
->gfn
,
5930 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
5938 return need_tlb_flush
;
5941 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5942 const struct kvm_memory_slot
*memslot
)
5944 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5945 spin_lock(&kvm
->mmu_lock
);
5946 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5947 kvm_mmu_zap_collapsible_spte
, true);
5948 spin_unlock(&kvm
->mmu_lock
);
5951 void kvm_arch_flush_remote_tlbs_memslot(struct kvm
*kvm
,
5952 struct kvm_memory_slot
*memslot
)
5955 * All current use cases for flushing the TLBs for a specific memslot
5956 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5957 * The interaction between the various operations on memslot must be
5958 * serialized by slots_locks to ensure the TLB flush from one operation
5959 * is observed by any other operation on the same memslot.
5961 lockdep_assert_held(&kvm
->slots_lock
);
5962 kvm_flush_remote_tlbs_with_address(kvm
, memslot
->base_gfn
,
5966 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5967 struct kvm_memory_slot
*memslot
)
5971 spin_lock(&kvm
->mmu_lock
);
5972 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5973 spin_unlock(&kvm
->mmu_lock
);
5976 * It's also safe to flush TLBs out of mmu lock here as currently this
5977 * function is only used for dirty logging, in which case flushing TLB
5978 * out of mmu lock also guarantees no dirty pages will be lost in
5982 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5984 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5986 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5987 struct kvm_memory_slot
*memslot
)
5991 spin_lock(&kvm
->mmu_lock
);
5992 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5994 spin_unlock(&kvm
->mmu_lock
);
5997 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5999 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
6001 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
6002 struct kvm_memory_slot
*memslot
)
6006 spin_lock(&kvm
->mmu_lock
);
6007 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
6008 spin_unlock(&kvm
->mmu_lock
);
6011 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
6013 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
6015 void kvm_mmu_zap_all(struct kvm
*kvm
)
6017 struct kvm_mmu_page
*sp
, *node
;
6018 LIST_HEAD(invalid_list
);
6021 spin_lock(&kvm
->mmu_lock
);
6023 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
6024 if (sp
->role
.invalid
&& sp
->root_count
)
6026 if (__kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
, &ign
))
6028 if (cond_resched_lock(&kvm
->mmu_lock
))
6032 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
6033 spin_unlock(&kvm
->mmu_lock
);
6036 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, u64 gen
)
6038 WARN_ON(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
);
6040 gen
&= MMIO_SPTE_GEN_MASK
;
6043 * Generation numbers are incremented in multiples of the number of
6044 * address spaces in order to provide unique generations across all
6045 * address spaces. Strip what is effectively the address space
6046 * modifier prior to checking for a wrap of the MMIO generation so
6047 * that a wrap in any address space is detected.
6049 gen
&= ~((u64
)KVM_ADDRESS_SPACE_NUM
- 1);
6052 * The very rare case: if the MMIO generation number has wrapped,
6053 * zap all shadow pages.
6055 if (unlikely(gen
== 0)) {
6056 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
6057 kvm_mmu_zap_all_fast(kvm
);
6061 static unsigned long
6062 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
6065 int nr_to_scan
= sc
->nr_to_scan
;
6066 unsigned long freed
= 0;
6068 mutex_lock(&kvm_lock
);
6070 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
6072 LIST_HEAD(invalid_list
);
6075 * Never scan more than sc->nr_to_scan VM instances.
6076 * Will not hit this condition practically since we do not try
6077 * to shrink more than one VM and it is very unlikely to see
6078 * !n_used_mmu_pages so many times.
6083 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
6084 * here. We may skip a VM instance errorneosly, but we do not
6085 * want to shrink a VM that only started to populate its MMU
6088 if (!kvm
->arch
.n_used_mmu_pages
&&
6089 !kvm_has_zapped_obsolete_pages(kvm
))
6092 idx
= srcu_read_lock(&kvm
->srcu
);
6093 spin_lock(&kvm
->mmu_lock
);
6095 if (kvm_has_zapped_obsolete_pages(kvm
)) {
6096 kvm_mmu_commit_zap_page(kvm
,
6097 &kvm
->arch
.zapped_obsolete_pages
);
6101 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
6103 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
6106 spin_unlock(&kvm
->mmu_lock
);
6107 srcu_read_unlock(&kvm
->srcu
, idx
);
6110 * unfair on small ones
6111 * per-vm shrinkers cry out
6112 * sadness comes quickly
6114 list_move_tail(&kvm
->vm_list
, &vm_list
);
6118 mutex_unlock(&kvm_lock
);
6122 static unsigned long
6123 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
6125 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
6128 static struct shrinker mmu_shrinker
= {
6129 .count_objects
= mmu_shrink_count
,
6130 .scan_objects
= mmu_shrink_scan
,
6131 .seeks
= DEFAULT_SEEKS
* 10,
6134 static void mmu_destroy_caches(void)
6136 kmem_cache_destroy(pte_list_desc_cache
);
6137 kmem_cache_destroy(mmu_page_header_cache
);
6140 static void kvm_set_mmio_spte_mask(void)
6145 * Set the reserved bits and the present bit of an paging-structure
6146 * entry to generate page fault with PFER.RSV = 1.
6150 * Mask the uppermost physical address bit, which would be reserved as
6151 * long as the supported physical address width is less than 52.
6155 /* Set the present bit. */
6159 * If reserved bit is not supported, clear the present bit to disable
6162 if (shadow_phys_bits
== 52)
6165 kvm_mmu_set_mmio_spte_mask(mask
, mask
, ACC_WRITE_MASK
| ACC_USER_MASK
);
6168 static bool get_nx_auto_mode(void)
6170 /* Return true when CPU has the bug, and mitigations are ON */
6171 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT
) && !cpu_mitigations_off();
6174 static void __set_nx_huge_pages(bool val
)
6176 nx_huge_pages
= itlb_multihit_kvm_mitigation
= val
;
6179 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
)
6181 bool old_val
= nx_huge_pages
;
6184 /* In "auto" mode deploy workaround only if CPU has the bug. */
6185 if (sysfs_streq(val
, "off"))
6187 else if (sysfs_streq(val
, "force"))
6189 else if (sysfs_streq(val
, "auto"))
6190 new_val
= get_nx_auto_mode();
6191 else if (strtobool(val
, &new_val
) < 0)
6194 __set_nx_huge_pages(new_val
);
6196 if (new_val
!= old_val
) {
6199 mutex_lock(&kvm_lock
);
6201 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
6202 mutex_lock(&kvm
->slots_lock
);
6203 kvm_mmu_zap_all_fast(kvm
);
6204 mutex_unlock(&kvm
->slots_lock
);
6206 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
6208 mutex_unlock(&kvm_lock
);
6214 int kvm_mmu_module_init(void)
6218 if (nx_huge_pages
== -1)
6219 __set_nx_huge_pages(get_nx_auto_mode());
6222 * MMU roles use union aliasing which is, generally speaking, an
6223 * undefined behavior. However, we supposedly know how compilers behave
6224 * and the current status quo is unlikely to change. Guardians below are
6225 * supposed to let us know if the assumption becomes false.
6227 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role
) != sizeof(u32
));
6228 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role
) != sizeof(u32
));
6229 BUILD_BUG_ON(sizeof(union kvm_mmu_role
) != sizeof(u64
));
6231 kvm_mmu_reset_all_pte_masks();
6233 kvm_set_mmio_spte_mask();
6235 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
6236 sizeof(struct pte_list_desc
),
6237 0, SLAB_ACCOUNT
, NULL
);
6238 if (!pte_list_desc_cache
)
6241 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
6242 sizeof(struct kvm_mmu_page
),
6243 0, SLAB_ACCOUNT
, NULL
);
6244 if (!mmu_page_header_cache
)
6247 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
6250 ret
= register_shrinker(&mmu_shrinker
);
6257 mmu_destroy_caches();
6262 * Calculate mmu pages needed for kvm.
6264 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm
*kvm
)
6266 unsigned long nr_mmu_pages
;
6267 unsigned long nr_pages
= 0;
6268 struct kvm_memslots
*slots
;
6269 struct kvm_memory_slot
*memslot
;
6272 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
6273 slots
= __kvm_memslots(kvm
, i
);
6275 kvm_for_each_memslot(memslot
, slots
)
6276 nr_pages
+= memslot
->npages
;
6279 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
6280 nr_mmu_pages
= max(nr_mmu_pages
, KVM_MIN_ALLOC_MMU_PAGES
);
6282 return nr_mmu_pages
;
6285 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
6287 kvm_mmu_unload(vcpu
);
6288 free_mmu_pages(&vcpu
->arch
.root_mmu
);
6289 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
6290 mmu_free_memory_caches(vcpu
);
6293 void kvm_mmu_module_exit(void)
6295 mmu_destroy_caches();
6296 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
6297 unregister_shrinker(&mmu_shrinker
);
6298 mmu_audit_disable();
6301 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
)
6303 unsigned int old_val
;
6306 old_val
= nx_huge_pages_recovery_ratio
;
6307 err
= param_set_uint(val
, kp
);
6311 if (READ_ONCE(nx_huge_pages
) &&
6312 !old_val
&& nx_huge_pages_recovery_ratio
) {
6315 mutex_lock(&kvm_lock
);
6317 list_for_each_entry(kvm
, &vm_list
, vm_list
)
6318 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
6320 mutex_unlock(&kvm_lock
);
6326 static void kvm_recover_nx_lpages(struct kvm
*kvm
)
6329 struct kvm_mmu_page
*sp
;
6331 LIST_HEAD(invalid_list
);
6334 rcu_idx
= srcu_read_lock(&kvm
->srcu
);
6335 spin_lock(&kvm
->mmu_lock
);
6337 ratio
= READ_ONCE(nx_huge_pages_recovery_ratio
);
6338 to_zap
= ratio
? DIV_ROUND_UP(kvm
->stat
.nx_lpage_splits
, ratio
) : 0;
6339 while (to_zap
&& !list_empty(&kvm
->arch
.lpage_disallowed_mmu_pages
)) {
6341 * We use a separate list instead of just using active_mmu_pages
6342 * because the number of lpage_disallowed pages is expected to
6343 * be relatively small compared to the total.
6345 sp
= list_first_entry(&kvm
->arch
.lpage_disallowed_mmu_pages
,
6346 struct kvm_mmu_page
,
6347 lpage_disallowed_link
);
6348 WARN_ON_ONCE(!sp
->lpage_disallowed
);
6349 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
6350 WARN_ON_ONCE(sp
->lpage_disallowed
);
6352 if (!--to_zap
|| need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
6353 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
6355 cond_resched_lock(&kvm
->mmu_lock
);
6359 spin_unlock(&kvm
->mmu_lock
);
6360 srcu_read_unlock(&kvm
->srcu
, rcu_idx
);
6363 static long get_nx_lpage_recovery_timeout(u64 start_time
)
6365 return READ_ONCE(nx_huge_pages
) && READ_ONCE(nx_huge_pages_recovery_ratio
)
6366 ? start_time
+ 60 * HZ
- get_jiffies_64()
6367 : MAX_SCHEDULE_TIMEOUT
;
6370 static int kvm_nx_lpage_recovery_worker(struct kvm
*kvm
, uintptr_t data
)
6373 long remaining_time
;
6376 start_time
= get_jiffies_64();
6377 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6379 set_current_state(TASK_INTERRUPTIBLE
);
6380 while (!kthread_should_stop() && remaining_time
> 0) {
6381 schedule_timeout(remaining_time
);
6382 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6383 set_current_state(TASK_INTERRUPTIBLE
);
6386 set_current_state(TASK_RUNNING
);
6388 if (kthread_should_stop())
6391 kvm_recover_nx_lpages(kvm
);
6395 int kvm_mmu_post_init_vm(struct kvm
*kvm
)
6399 err
= kvm_vm_create_worker_thread(kvm
, kvm_nx_lpage_recovery_worker
, 0,
6400 "kvm-nx-lpage-recovery",
6401 &kvm
->arch
.nx_lpage_recovery_thread
);
6403 kthread_unpark(kvm
->arch
.nx_lpage_recovery_thread
);
6408 void kvm_mmu_pre_destroy_vm(struct kvm
*kvm
)
6410 if (kvm
->arch
.nx_lpage_recovery_thread
)
6411 kthread_stop(kvm
->arch
.nx_lpage_recovery_thread
);