1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation
;
60 int __read_mostly nx_huge_pages
= -1;
61 #ifdef CONFIG_PREEMPT_RT
62 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63 static uint __read_mostly nx_huge_pages_recovery_ratio
= 0;
65 static uint __read_mostly nx_huge_pages_recovery_ratio
= 60;
68 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
);
69 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
);
71 static const struct kernel_param_ops nx_huge_pages_ops
= {
72 .set
= set_nx_huge_pages
,
73 .get
= param_get_bool
,
76 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops
= {
77 .set
= set_nx_huge_pages_recovery_ratio
,
78 .get
= param_get_uint
,
81 module_param_cb(nx_huge_pages
, &nx_huge_pages_ops
, &nx_huge_pages
, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages
, "bool");
83 module_param_cb(nx_huge_pages_recovery_ratio
, &nx_huge_pages_recovery_ratio_ops
,
84 &nx_huge_pages_recovery_ratio
, 0644);
85 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio
, "uint");
87 static bool __read_mostly force_flush_and_sync_on_reuse
;
88 module_param_named(flush_on_reuse
, force_flush_and_sync_on_reuse
, bool, 0644);
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
97 bool tdp_enabled
= false;
99 static int max_huge_page_level __read_mostly
;
100 static int max_tdp_level __read_mostly
;
103 AUDIT_PRE_PAGE_FAULT
,
104 AUDIT_POST_PAGE_FAULT
,
106 AUDIT_POST_PTE_WRITE
,
113 module_param(dbg
, bool, 0644);
116 #define PTE_PREFETCH_NUM 8
118 #define PT32_LEVEL_BITS 10
120 #define PT32_LEVEL_SHIFT(level) \
121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
123 #define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
131 #define PT32_BASE_ADDR_MASK PAGE_MASK
132 #define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
134 #define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
138 #include <trace/events/kvm.h>
140 /* make pte_list_desc fit well in cache lines */
141 #define PTE_LIST_EXT 14
144 * Slight optimization of cacheline layout, by putting `more' and `spte_count'
145 * at the start; then accessing it will only use one single cacheline for
146 * either full (entries==PTE_LIST_EXT) case or entries<=6.
148 struct pte_list_desc
{
149 struct pte_list_desc
*more
;
151 * Stores number of entries stored in the pte_list_desc. No need to be
152 * u64 but just for easier alignment. When PTE_LIST_EXT, means full.
155 u64
*sptes
[PTE_LIST_EXT
];
158 struct kvm_shadow_walk_iterator
{
166 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
167 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
169 shadow_walk_okay(&(_walker)); \
170 shadow_walk_next(&(_walker)))
172 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
177 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
178 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
179 shadow_walk_okay(&(_walker)) && \
180 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
181 __shadow_walk_next(&(_walker), spte))
183 static struct kmem_cache
*pte_list_desc_cache
;
184 struct kmem_cache
*mmu_page_header_cache
;
185 static struct percpu_counter kvm_total_used_mmu_pages
;
187 static void mmu_spte_set(u64
*sptep
, u64 spte
);
188 static union kvm_mmu_page_role
189 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
);
191 struct kvm_mmu_role_regs
{
192 const unsigned long cr0
;
193 const unsigned long cr4
;
197 #define CREATE_TRACE_POINTS
198 #include "mmutrace.h"
201 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
202 * reading from the role_regs. Once the mmu_role is constructed, it becomes
203 * the single source of truth for the MMU's state.
205 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
206 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
208 return !!(regs->reg & flag); \
210 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0
, pg
, X86_CR0_PG
);
211 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0
, wp
, X86_CR0_WP
);
212 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pse
, X86_CR4_PSE
);
213 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pae
, X86_CR4_PAE
);
214 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, smep
, X86_CR4_SMEP
);
215 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, smap
, X86_CR4_SMAP
);
216 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pke
, X86_CR4_PKE
);
217 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, la57
, X86_CR4_LA57
);
218 BUILD_MMU_ROLE_REGS_ACCESSOR(efer
, nx
, EFER_NX
);
219 BUILD_MMU_ROLE_REGS_ACCESSOR(efer
, lma
, EFER_LMA
);
222 * The MMU itself (with a valid role) is the single source of truth for the
223 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
224 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
225 * and the vCPU may be incorrect/irrelevant.
227 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
228 static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
230 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
232 BUILD_MMU_ROLE_ACCESSOR(ext
, cr0
, pg
);
233 BUILD_MMU_ROLE_ACCESSOR(base
, cr0
, wp
);
234 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pse
);
235 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pae
);
236 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, smep
);
237 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, smap
);
238 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pke
);
239 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, la57
);
240 BUILD_MMU_ROLE_ACCESSOR(base
, efer
, nx
);
242 static struct kvm_mmu_role_regs
vcpu_to_role_regs(struct kvm_vcpu
*vcpu
)
244 struct kvm_mmu_role_regs regs
= {
245 .cr0
= kvm_read_cr0_bits(vcpu
, KVM_MMU_CR0_ROLE_BITS
),
246 .cr4
= kvm_read_cr4_bits(vcpu
, KVM_MMU_CR4_ROLE_BITS
),
247 .efer
= vcpu
->arch
.efer
,
253 static int role_regs_to_root_level(struct kvm_mmu_role_regs
*regs
)
255 if (!____is_cr0_pg(regs
))
257 else if (____is_efer_lma(regs
))
258 return ____is_cr4_la57(regs
) ? PT64_ROOT_5LEVEL
:
260 else if (____is_cr4_pae(regs
))
261 return PT32E_ROOT_LEVEL
;
263 return PT32_ROOT_LEVEL
;
266 static inline bool kvm_available_flush_tlb_with_range(void)
268 return kvm_x86_ops
.tlb_remote_flush_with_range
;
271 static void kvm_flush_remote_tlbs_with_range(struct kvm
*kvm
,
272 struct kvm_tlb_range
*range
)
276 if (range
&& kvm_x86_ops
.tlb_remote_flush_with_range
)
277 ret
= static_call(kvm_x86_tlb_remote_flush_with_range
)(kvm
, range
);
280 kvm_flush_remote_tlbs(kvm
);
283 void kvm_flush_remote_tlbs_with_address(struct kvm
*kvm
,
284 u64 start_gfn
, u64 pages
)
286 struct kvm_tlb_range range
;
288 range
.start_gfn
= start_gfn
;
291 kvm_flush_remote_tlbs_with_range(kvm
, &range
);
294 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
297 u64 spte
= make_mmio_spte(vcpu
, gfn
, access
);
299 trace_mark_mmio_spte(sptep
, gfn
, spte
);
300 mmu_spte_set(sptep
, spte
);
303 static gfn_t
get_mmio_spte_gfn(u64 spte
)
305 u64 gpa
= spte
& shadow_nonpresent_or_rsvd_lower_gfn_mask
;
307 gpa
|= (spte
>> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN
)
308 & shadow_nonpresent_or_rsvd_mask
;
310 return gpa
>> PAGE_SHIFT
;
313 static unsigned get_mmio_spte_access(u64 spte
)
315 return spte
& shadow_mmio_access_mask
;
318 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
320 u64 kvm_gen
, spte_gen
, gen
;
322 gen
= kvm_vcpu_memslots(vcpu
)->generation
;
323 if (unlikely(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
))
326 kvm_gen
= gen
& MMIO_SPTE_GEN_MASK
;
327 spte_gen
= get_mmio_spte_generation(spte
);
329 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
330 return likely(kvm_gen
== spte_gen
);
333 static gpa_t
translate_gpa(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 access
,
334 struct x86_exception
*exception
)
336 /* Check if guest physical address doesn't exceed guest maximum */
337 if (kvm_vcpu_is_illegal_gpa(vcpu
, gpa
)) {
338 exception
->error_code
|= PFERR_RSVD_MASK
;
345 static int is_cpuid_PSE36(void)
350 static gfn_t
pse36_gfn_delta(u32 gpte
)
352 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
354 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
358 static void __set_spte(u64
*sptep
, u64 spte
)
360 WRITE_ONCE(*sptep
, spte
);
363 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
365 WRITE_ONCE(*sptep
, spte
);
368 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
370 return xchg(sptep
, spte
);
373 static u64
__get_spte_lockless(u64
*sptep
)
375 return READ_ONCE(*sptep
);
386 static void count_spte_clear(u64
*sptep
, u64 spte
)
388 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
390 if (is_shadow_present_pte(spte
))
393 /* Ensure the spte is completely set before we increase the count */
395 sp
->clear_spte_count
++;
398 static void __set_spte(u64
*sptep
, u64 spte
)
400 union split_spte
*ssptep
, sspte
;
402 ssptep
= (union split_spte
*)sptep
;
403 sspte
= (union split_spte
)spte
;
405 ssptep
->spte_high
= sspte
.spte_high
;
408 * If we map the spte from nonpresent to present, We should store
409 * the high bits firstly, then set present bit, so cpu can not
410 * fetch this spte while we are setting the spte.
414 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
417 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
419 union split_spte
*ssptep
, sspte
;
421 ssptep
= (union split_spte
*)sptep
;
422 sspte
= (union split_spte
)spte
;
424 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
427 * If we map the spte from present to nonpresent, we should clear
428 * present bit firstly to avoid vcpu fetch the old high bits.
432 ssptep
->spte_high
= sspte
.spte_high
;
433 count_spte_clear(sptep
, spte
);
436 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
438 union split_spte
*ssptep
, sspte
, orig
;
440 ssptep
= (union split_spte
*)sptep
;
441 sspte
= (union split_spte
)spte
;
443 /* xchg acts as a barrier before the setting of the high bits */
444 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
445 orig
.spte_high
= ssptep
->spte_high
;
446 ssptep
->spte_high
= sspte
.spte_high
;
447 count_spte_clear(sptep
, spte
);
453 * The idea using the light way get the spte on x86_32 guest is from
454 * gup_get_pte (mm/gup.c).
456 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
457 * coalesces them and we are running out of the MMU lock. Therefore
458 * we need to protect against in-progress updates of the spte.
460 * Reading the spte while an update is in progress may get the old value
461 * for the high part of the spte. The race is fine for a present->non-present
462 * change (because the high part of the spte is ignored for non-present spte),
463 * but for a present->present change we must reread the spte.
465 * All such changes are done in two steps (present->non-present and
466 * non-present->present), hence it is enough to count the number of
467 * present->non-present updates: if it changed while reading the spte,
468 * we might have hit the race. This is done using clear_spte_count.
470 static u64
__get_spte_lockless(u64
*sptep
)
472 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
473 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
477 count
= sp
->clear_spte_count
;
480 spte
.spte_low
= orig
->spte_low
;
483 spte
.spte_high
= orig
->spte_high
;
486 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
487 count
!= sp
->clear_spte_count
))
494 static bool spte_has_volatile_bits(u64 spte
)
496 if (!is_shadow_present_pte(spte
))
500 * Always atomically update spte if it can be updated
501 * out of mmu-lock, it can ensure dirty bit is not lost,
502 * also, it can help us to get a stable is_writable_pte()
503 * to ensure tlb flush is not missed.
505 if (spte_can_locklessly_be_made_writable(spte
) ||
506 is_access_track_spte(spte
))
509 if (spte_ad_enabled(spte
)) {
510 if ((spte
& shadow_accessed_mask
) == 0 ||
511 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
518 /* Rules for using mmu_spte_set:
519 * Set the sptep from nonpresent to present.
520 * Note: the sptep being assigned *must* be either not present
521 * or in a state where the hardware will not attempt to update
524 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
526 WARN_ON(is_shadow_present_pte(*sptep
));
527 __set_spte(sptep
, new_spte
);
531 * Update the SPTE (excluding the PFN), but do not track changes in its
532 * accessed/dirty status.
534 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
536 u64 old_spte
= *sptep
;
538 WARN_ON(!is_shadow_present_pte(new_spte
));
540 if (!is_shadow_present_pte(old_spte
)) {
541 mmu_spte_set(sptep
, new_spte
);
545 if (!spte_has_volatile_bits(old_spte
))
546 __update_clear_spte_fast(sptep
, new_spte
);
548 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
550 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
555 /* Rules for using mmu_spte_update:
556 * Update the state bits, it means the mapped pfn is not changed.
558 * Whenever we overwrite a writable spte with a read-only one we
559 * should flush remote TLBs. Otherwise rmap_write_protect
560 * will find a read-only spte, even though the writable spte
561 * might be cached on a CPU's TLB, the return value indicates this
564 * Returns true if the TLB needs to be flushed
566 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
569 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
571 if (!is_shadow_present_pte(old_spte
))
575 * For the spte updated out of mmu-lock is safe, since
576 * we always atomically update it, see the comments in
577 * spte_has_volatile_bits().
579 if (spte_can_locklessly_be_made_writable(old_spte
) &&
580 !is_writable_pte(new_spte
))
584 * Flush TLB when accessed/dirty states are changed in the page tables,
585 * to guarantee consistency between TLB and page tables.
588 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
590 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
593 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
595 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
602 * Rules for using mmu_spte_clear_track_bits:
603 * It sets the sptep from present to nonpresent, and track the
604 * state bits, it is used to clear the last level sptep.
605 * Returns the old PTE.
607 static u64
mmu_spte_clear_track_bits(u64
*sptep
)
610 u64 old_spte
= *sptep
;
612 if (!spte_has_volatile_bits(old_spte
))
613 __update_clear_spte_fast(sptep
, 0ull);
615 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
617 if (!is_shadow_present_pte(old_spte
))
620 pfn
= spte_to_pfn(old_spte
);
623 * KVM does not hold the refcount of the page used by
624 * kvm mmu, before reclaiming the page, we should
625 * unmap it from mmu first.
627 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
629 if (is_accessed_spte(old_spte
))
630 kvm_set_pfn_accessed(pfn
);
632 if (is_dirty_spte(old_spte
))
633 kvm_set_pfn_dirty(pfn
);
639 * Rules for using mmu_spte_clear_no_track:
640 * Directly clear spte without caring the state bits of sptep,
641 * it is used to set the upper level spte.
643 static void mmu_spte_clear_no_track(u64
*sptep
)
645 __update_clear_spte_fast(sptep
, 0ull);
648 static u64
mmu_spte_get_lockless(u64
*sptep
)
650 return __get_spte_lockless(sptep
);
653 /* Restore an acc-track PTE back to a regular PTE */
654 static u64
restore_acc_track_spte(u64 spte
)
657 u64 saved_bits
= (spte
>> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
)
658 & SHADOW_ACC_TRACK_SAVED_BITS_MASK
;
660 WARN_ON_ONCE(spte_ad_enabled(spte
));
661 WARN_ON_ONCE(!is_access_track_spte(spte
));
663 new_spte
&= ~shadow_acc_track_mask
;
664 new_spte
&= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK
<<
665 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
);
666 new_spte
|= saved_bits
;
671 /* Returns the Accessed status of the PTE and resets it at the same time. */
672 static bool mmu_spte_age(u64
*sptep
)
674 u64 spte
= mmu_spte_get_lockless(sptep
);
676 if (!is_accessed_spte(spte
))
679 if (spte_ad_enabled(spte
)) {
680 clear_bit((ffs(shadow_accessed_mask
) - 1),
681 (unsigned long *)sptep
);
684 * Capture the dirty status of the page, so that it doesn't get
685 * lost when the SPTE is marked for access tracking.
687 if (is_writable_pte(spte
))
688 kvm_set_pfn_dirty(spte_to_pfn(spte
));
690 spte
= mark_spte_for_access_track(spte
);
691 mmu_spte_update_no_track(sptep
, spte
);
697 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
699 if (is_tdp_mmu(vcpu
->arch
.mmu
)) {
700 kvm_tdp_mmu_walk_lockless_begin();
703 * Prevent page table teardown by making any free-er wait during
704 * kvm_flush_remote_tlbs() IPI to all active vcpus.
709 * Make sure a following spte read is not reordered ahead of the write
712 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
716 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
718 if (is_tdp_mmu(vcpu
->arch
.mmu
)) {
719 kvm_tdp_mmu_walk_lockless_end();
722 * Make sure the write to vcpu->mode is not reordered in front of
723 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
724 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
726 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
731 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
, bool maybe_indirect
)
735 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
736 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
737 1 + PT64_ROOT_MAX_LEVEL
+ PTE_PREFETCH_NUM
);
740 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
,
741 PT64_ROOT_MAX_LEVEL
);
744 if (maybe_indirect
) {
745 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
,
746 PT64_ROOT_MAX_LEVEL
);
750 return kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
751 PT64_ROOT_MAX_LEVEL
);
754 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
756 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
);
757 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
);
758 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
);
759 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
);
762 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
764 return kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
767 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
769 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
772 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
774 if (!sp
->role
.direct
)
775 return sp
->gfns
[index
];
777 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
780 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
782 if (!sp
->role
.direct
) {
783 sp
->gfns
[index
] = gfn
;
787 if (WARN_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
)))
788 pr_err_ratelimited("gfn mismatch under direct page %llx "
789 "(expected %llx, got %llx)\n",
791 kvm_mmu_page_get_gfn(sp
, index
), gfn
);
795 * Return the pointer to the large page information for a given gfn,
796 * handling slots that are not large page aligned.
798 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
799 const struct kvm_memory_slot
*slot
, int level
)
803 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
804 return &slot
->arch
.lpage_info
[level
- 2][idx
];
807 static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot
*slot
,
808 gfn_t gfn
, int count
)
810 struct kvm_lpage_info
*linfo
;
813 for (i
= PG_LEVEL_2M
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
814 linfo
= lpage_info_slot(gfn
, slot
, i
);
815 linfo
->disallow_lpage
+= count
;
816 WARN_ON(linfo
->disallow_lpage
< 0);
820 void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot
*slot
, gfn_t gfn
)
822 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
825 void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot
*slot
, gfn_t gfn
)
827 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
830 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
832 struct kvm_memslots
*slots
;
833 struct kvm_memory_slot
*slot
;
836 kvm
->arch
.indirect_shadow_pages
++;
838 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
839 slot
= __gfn_to_memslot(slots
, gfn
);
841 /* the non-leaf shadow pages are keeping readonly. */
842 if (sp
->role
.level
> PG_LEVEL_4K
)
843 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
844 KVM_PAGE_TRACK_WRITE
);
846 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
849 void account_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
851 if (sp
->lpage_disallowed
)
854 ++kvm
->stat
.nx_lpage_splits
;
855 list_add_tail(&sp
->lpage_disallowed_link
,
856 &kvm
->arch
.lpage_disallowed_mmu_pages
);
857 sp
->lpage_disallowed
= true;
860 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
862 struct kvm_memslots
*slots
;
863 struct kvm_memory_slot
*slot
;
866 kvm
->arch
.indirect_shadow_pages
--;
868 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
869 slot
= __gfn_to_memslot(slots
, gfn
);
870 if (sp
->role
.level
> PG_LEVEL_4K
)
871 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
872 KVM_PAGE_TRACK_WRITE
);
874 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
877 void unaccount_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
879 --kvm
->stat
.nx_lpage_splits
;
880 sp
->lpage_disallowed
= false;
881 list_del(&sp
->lpage_disallowed_link
);
884 static struct kvm_memory_slot
*
885 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
888 struct kvm_memory_slot
*slot
;
890 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
891 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
893 if (no_dirty_log
&& kvm_slot_dirty_track_enabled(slot
))
900 * About rmap_head encoding:
902 * If the bit zero of rmap_head->val is clear, then it points to the only spte
903 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
904 * pte_list_desc containing more mappings.
908 * Returns the number of pointers in the rmap chain, not counting the new one.
910 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
911 struct kvm_rmap_head
*rmap_head
)
913 struct pte_list_desc
*desc
;
916 if (!rmap_head
->val
) {
917 rmap_printk("%p %llx 0->1\n", spte
, *spte
);
918 rmap_head
->val
= (unsigned long)spte
;
919 } else if (!(rmap_head
->val
& 1)) {
920 rmap_printk("%p %llx 1->many\n", spte
, *spte
);
921 desc
= mmu_alloc_pte_list_desc(vcpu
);
922 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
923 desc
->sptes
[1] = spte
;
924 desc
->spte_count
= 2;
925 rmap_head
->val
= (unsigned long)desc
| 1;
928 rmap_printk("%p %llx many->many\n", spte
, *spte
);
929 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
930 while (desc
->spte_count
== PTE_LIST_EXT
) {
931 count
+= PTE_LIST_EXT
;
933 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
935 desc
->spte_count
= 0;
940 count
+= desc
->spte_count
;
941 desc
->sptes
[desc
->spte_count
++] = spte
;
947 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
948 struct pte_list_desc
*desc
, int i
,
949 struct pte_list_desc
*prev_desc
)
951 int j
= desc
->spte_count
- 1;
953 desc
->sptes
[i
] = desc
->sptes
[j
];
954 desc
->sptes
[j
] = NULL
;
956 if (desc
->spte_count
)
958 if (!prev_desc
&& !desc
->more
)
962 prev_desc
->more
= desc
->more
;
964 rmap_head
->val
= (unsigned long)desc
->more
| 1;
965 mmu_free_pte_list_desc(desc
);
968 static void __pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
970 struct pte_list_desc
*desc
;
971 struct pte_list_desc
*prev_desc
;
974 if (!rmap_head
->val
) {
975 pr_err("%s: %p 0->BUG\n", __func__
, spte
);
977 } else if (!(rmap_head
->val
& 1)) {
978 rmap_printk("%p 1->0\n", spte
);
979 if ((u64
*)rmap_head
->val
!= spte
) {
980 pr_err("%s: %p 1->BUG\n", __func__
, spte
);
985 rmap_printk("%p many->many\n", spte
);
986 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
989 for (i
= 0; i
< desc
->spte_count
; ++i
) {
990 if (desc
->sptes
[i
] == spte
) {
991 pte_list_desc_remove_entry(rmap_head
,
999 pr_err("%s: %p many->many\n", __func__
, spte
);
1004 static void pte_list_remove(struct kvm_rmap_head
*rmap_head
, u64
*sptep
)
1006 mmu_spte_clear_track_bits(sptep
);
1007 __pte_list_remove(sptep
, rmap_head
);
1010 /* Return true if rmap existed, false otherwise */
1011 static bool pte_list_destroy(struct kvm_rmap_head
*rmap_head
)
1013 struct pte_list_desc
*desc
, *next
;
1016 if (!rmap_head
->val
)
1019 if (!(rmap_head
->val
& 1)) {
1020 mmu_spte_clear_track_bits((u64
*)rmap_head
->val
);
1024 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1026 for (; desc
; desc
= next
) {
1027 for (i
= 0; i
< desc
->spte_count
; i
++)
1028 mmu_spte_clear_track_bits(desc
->sptes
[i
]);
1030 mmu_free_pte_list_desc(desc
);
1033 /* rmap_head is meaningless now, remember to reset it */
1038 static struct kvm_rmap_head
*gfn_to_rmap(gfn_t gfn
, int level
,
1039 const struct kvm_memory_slot
*slot
)
1043 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1044 return &slot
->arch
.rmap
[level
- PG_LEVEL_4K
][idx
];
1047 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1049 struct kvm_mmu_memory_cache
*mc
;
1051 mc
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1052 return kvm_mmu_memory_cache_nr_free_objects(mc
);
1055 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1057 struct kvm_memory_slot
*slot
;
1058 struct kvm_mmu_page
*sp
;
1059 struct kvm_rmap_head
*rmap_head
;
1061 sp
= sptep_to_sp(spte
);
1062 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1063 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1064 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1065 return pte_list_add(vcpu
, spte
, rmap_head
);
1069 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1071 struct kvm_memslots
*slots
;
1072 struct kvm_memory_slot
*slot
;
1073 struct kvm_mmu_page
*sp
;
1075 struct kvm_rmap_head
*rmap_head
;
1077 sp
= sptep_to_sp(spte
);
1078 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1081 * Unlike rmap_add and rmap_recycle, rmap_remove does not run in the
1082 * context of a vCPU so have to determine which memslots to use based
1083 * on context information in sp->role.
1085 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1087 slot
= __gfn_to_memslot(slots
, gfn
);
1088 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1090 __pte_list_remove(spte
, rmap_head
);
1094 * Used by the following functions to iterate through the sptes linked by a
1095 * rmap. All fields are private and not assumed to be used outside.
1097 struct rmap_iterator
{
1098 /* private fields */
1099 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1100 int pos
; /* index of the sptep */
1104 * Iteration must be started by this function. This should also be used after
1105 * removing/dropping sptes from the rmap link because in such cases the
1106 * information in the iterator may not be valid.
1108 * Returns sptep if found, NULL otherwise.
1110 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1111 struct rmap_iterator
*iter
)
1115 if (!rmap_head
->val
)
1118 if (!(rmap_head
->val
& 1)) {
1120 sptep
= (u64
*)rmap_head
->val
;
1124 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1126 sptep
= iter
->desc
->sptes
[iter
->pos
];
1128 BUG_ON(!is_shadow_present_pte(*sptep
));
1133 * Must be used with a valid iterator: e.g. after rmap_get_first().
1135 * Returns sptep if found, NULL otherwise.
1137 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1142 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1144 sptep
= iter
->desc
->sptes
[iter
->pos
];
1149 iter
->desc
= iter
->desc
->more
;
1153 /* desc->sptes[0] cannot be NULL */
1154 sptep
= iter
->desc
->sptes
[iter
->pos
];
1161 BUG_ON(!is_shadow_present_pte(*sptep
));
1165 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1166 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1167 _spte_; _spte_ = rmap_get_next(_iter_))
1169 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1171 u64 old_spte
= mmu_spte_clear_track_bits(sptep
);
1173 if (is_shadow_present_pte(old_spte
))
1174 rmap_remove(kvm
, sptep
);
1178 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1180 if (is_large_pte(*sptep
)) {
1181 WARN_ON(sptep_to_sp(sptep
)->role
.level
== PG_LEVEL_4K
);
1182 drop_spte(kvm
, sptep
);
1190 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1192 if (__drop_large_spte(vcpu
->kvm
, sptep
)) {
1193 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
1195 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1196 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1201 * Write-protect on the specified @sptep, @pt_protect indicates whether
1202 * spte write-protection is caused by protecting shadow page table.
1204 * Note: write protection is difference between dirty logging and spte
1206 * - for dirty logging, the spte can be set to writable at anytime if
1207 * its dirty bitmap is properly set.
1208 * - for spte protection, the spte can be writable only after unsync-ing
1211 * Return true if tlb need be flushed.
1213 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1217 if (!is_writable_pte(spte
) &&
1218 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1221 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1224 spte
&= ~shadow_mmu_writable_mask
;
1225 spte
= spte
& ~PT_WRITABLE_MASK
;
1227 return mmu_spte_update(sptep
, spte
);
1230 static bool __rmap_write_protect(struct kvm
*kvm
,
1231 struct kvm_rmap_head
*rmap_head
,
1235 struct rmap_iterator iter
;
1238 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1239 flush
|= spte_write_protect(sptep
, pt_protect
);
1244 static bool spte_clear_dirty(u64
*sptep
)
1248 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1250 MMU_WARN_ON(!spte_ad_enabled(spte
));
1251 spte
&= ~shadow_dirty_mask
;
1252 return mmu_spte_update(sptep
, spte
);
1255 static bool spte_wrprot_for_clear_dirty(u64
*sptep
)
1257 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1258 (unsigned long *)sptep
);
1259 if (was_writable
&& !spte_ad_enabled(*sptep
))
1260 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1262 return was_writable
;
1266 * Gets the GFN ready for another round of dirty logging by clearing the
1267 * - D bit on ad-enabled SPTEs, and
1268 * - W bit on ad-disabled SPTEs.
1269 * Returns true iff any D or W bits were cleared.
1271 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1272 const struct kvm_memory_slot
*slot
)
1275 struct rmap_iterator iter
;
1278 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1279 if (spte_ad_need_write_protect(*sptep
))
1280 flush
|= spte_wrprot_for_clear_dirty(sptep
);
1282 flush
|= spte_clear_dirty(sptep
);
1288 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1289 * @kvm: kvm instance
1290 * @slot: slot to protect
1291 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1292 * @mask: indicates which pages we should protect
1294 * Used when we do not need to care about huge page mappings.
1296 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1297 struct kvm_memory_slot
*slot
,
1298 gfn_t gfn_offset
, unsigned long mask
)
1300 struct kvm_rmap_head
*rmap_head
;
1302 if (is_tdp_mmu_enabled(kvm
))
1303 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1304 slot
->base_gfn
+ gfn_offset
, mask
, true);
1306 if (!kvm_memslots_have_rmaps(kvm
))
1310 rmap_head
= gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1312 __rmap_write_protect(kvm
, rmap_head
, false);
1314 /* clear the first set bit */
1320 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1321 * protect the page if the D-bit isn't supported.
1322 * @kvm: kvm instance
1323 * @slot: slot to clear D-bit
1324 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1325 * @mask: indicates which pages we should clear D-bit
1327 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1329 static void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1330 struct kvm_memory_slot
*slot
,
1331 gfn_t gfn_offset
, unsigned long mask
)
1333 struct kvm_rmap_head
*rmap_head
;
1335 if (is_tdp_mmu_enabled(kvm
))
1336 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1337 slot
->base_gfn
+ gfn_offset
, mask
, false);
1339 if (!kvm_memslots_have_rmaps(kvm
))
1343 rmap_head
= gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1345 __rmap_clear_dirty(kvm
, rmap_head
, slot
);
1347 /* clear the first set bit */
1353 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1356 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1357 * enable dirty logging for them.
1359 * We need to care about huge page mappings: e.g. during dirty logging we may
1360 * have such mappings.
1362 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1363 struct kvm_memory_slot
*slot
,
1364 gfn_t gfn_offset
, unsigned long mask
)
1367 * Huge pages are NOT write protected when we start dirty logging in
1368 * initially-all-set mode; must write protect them here so that they
1369 * are split to 4K on the first write.
1371 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1372 * of memslot has no such restriction, so the range can cross two large
1375 if (kvm_dirty_log_manual_protect_and_init_set(kvm
)) {
1376 gfn_t start
= slot
->base_gfn
+ gfn_offset
+ __ffs(mask
);
1377 gfn_t end
= slot
->base_gfn
+ gfn_offset
+ __fls(mask
);
1379 kvm_mmu_slot_gfn_write_protect(kvm
, slot
, start
, PG_LEVEL_2M
);
1381 /* Cross two large pages? */
1382 if (ALIGN(start
<< PAGE_SHIFT
, PMD_SIZE
) !=
1383 ALIGN(end
<< PAGE_SHIFT
, PMD_SIZE
))
1384 kvm_mmu_slot_gfn_write_protect(kvm
, slot
, end
,
1388 /* Now handle 4K PTEs. */
1389 if (kvm_x86_ops
.cpu_dirty_log_size
)
1390 kvm_mmu_clear_dirty_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1392 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1395 int kvm_cpu_dirty_log_size(void)
1397 return kvm_x86_ops
.cpu_dirty_log_size
;
1400 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1401 struct kvm_memory_slot
*slot
, u64 gfn
,
1404 struct kvm_rmap_head
*rmap_head
;
1406 bool write_protected
= false;
1408 if (kvm_memslots_have_rmaps(kvm
)) {
1409 for (i
= min_level
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
1410 rmap_head
= gfn_to_rmap(gfn
, i
, slot
);
1411 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1415 if (is_tdp_mmu_enabled(kvm
))
1417 kvm_tdp_mmu_write_protect_gfn(kvm
, slot
, gfn
, min_level
);
1419 return write_protected
;
1422 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1424 struct kvm_memory_slot
*slot
;
1426 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1427 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
, PG_LEVEL_4K
);
1430 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1431 const struct kvm_memory_slot
*slot
)
1433 return pte_list_destroy(rmap_head
);
1436 static bool kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1437 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1440 return kvm_zap_rmapp(kvm
, rmap_head
, slot
);
1443 static bool kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1444 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1448 struct rmap_iterator iter
;
1453 WARN_ON(pte_huge(pte
));
1454 new_pfn
= pte_pfn(pte
);
1457 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1458 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1459 sptep
, *sptep
, gfn
, level
);
1463 if (pte_write(pte
)) {
1464 pte_list_remove(rmap_head
, sptep
);
1467 new_spte
= kvm_mmu_changed_pte_notifier_make_spte(
1470 mmu_spte_clear_track_bits(sptep
);
1471 mmu_spte_set(sptep
, new_spte
);
1475 if (need_flush
&& kvm_available_flush_tlb_with_range()) {
1476 kvm_flush_remote_tlbs_with_address(kvm
, gfn
, 1);
1483 struct slot_rmap_walk_iterator
{
1485 const struct kvm_memory_slot
*slot
;
1491 /* output fields. */
1493 struct kvm_rmap_head
*rmap
;
1496 /* private field. */
1497 struct kvm_rmap_head
*end_rmap
;
1501 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1503 iterator
->level
= level
;
1504 iterator
->gfn
= iterator
->start_gfn
;
1505 iterator
->rmap
= gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1506 iterator
->end_rmap
= gfn_to_rmap(iterator
->end_gfn
, level
, iterator
->slot
);
1510 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1511 const struct kvm_memory_slot
*slot
, int start_level
,
1512 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1514 iterator
->slot
= slot
;
1515 iterator
->start_level
= start_level
;
1516 iterator
->end_level
= end_level
;
1517 iterator
->start_gfn
= start_gfn
;
1518 iterator
->end_gfn
= end_gfn
;
1520 rmap_walk_init_level(iterator
, iterator
->start_level
);
1523 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1525 return !!iterator
->rmap
;
1528 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1530 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1531 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1535 if (++iterator
->level
> iterator
->end_level
) {
1536 iterator
->rmap
= NULL
;
1540 rmap_walk_init_level(iterator
, iterator
->level
);
1543 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1544 _start_gfn, _end_gfn, _iter_) \
1545 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1546 _end_level_, _start_gfn, _end_gfn); \
1547 slot_rmap_walk_okay(_iter_); \
1548 slot_rmap_walk_next(_iter_))
1550 typedef bool (*rmap_handler_t
)(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1551 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1552 int level
, pte_t pte
);
1554 static __always_inline
bool kvm_handle_gfn_range(struct kvm
*kvm
,
1555 struct kvm_gfn_range
*range
,
1556 rmap_handler_t handler
)
1558 struct slot_rmap_walk_iterator iterator
;
1561 for_each_slot_rmap_range(range
->slot
, PG_LEVEL_4K
, KVM_MAX_HUGEPAGE_LEVEL
,
1562 range
->start
, range
->end
- 1, &iterator
)
1563 ret
|= handler(kvm
, iterator
.rmap
, range
->slot
, iterator
.gfn
,
1564 iterator
.level
, range
->pte
);
1569 bool kvm_unmap_gfn_range(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1573 if (kvm_memslots_have_rmaps(kvm
))
1574 flush
= kvm_handle_gfn_range(kvm
, range
, kvm_unmap_rmapp
);
1576 if (is_tdp_mmu_enabled(kvm
))
1577 flush
|= kvm_tdp_mmu_unmap_gfn_range(kvm
, range
, flush
);
1582 bool kvm_set_spte_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1586 if (kvm_memslots_have_rmaps(kvm
))
1587 flush
= kvm_handle_gfn_range(kvm
, range
, kvm_set_pte_rmapp
);
1589 if (is_tdp_mmu_enabled(kvm
))
1590 flush
|= kvm_tdp_mmu_set_spte_gfn(kvm
, range
);
1595 static bool kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1596 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1600 struct rmap_iterator iter
;
1603 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1604 young
|= mmu_spte_age(sptep
);
1609 static bool kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1610 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1611 int level
, pte_t unused
)
1614 struct rmap_iterator iter
;
1616 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1617 if (is_accessed_spte(*sptep
))
1622 #define RMAP_RECYCLE_THRESHOLD 1000
1624 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1626 struct kvm_memory_slot
*slot
;
1627 struct kvm_rmap_head
*rmap_head
;
1628 struct kvm_mmu_page
*sp
;
1630 sp
= sptep_to_sp(spte
);
1631 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1632 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1634 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, __pte(0));
1635 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1636 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1639 bool kvm_age_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1643 if (kvm_memslots_have_rmaps(kvm
))
1644 young
= kvm_handle_gfn_range(kvm
, range
, kvm_age_rmapp
);
1646 if (is_tdp_mmu_enabled(kvm
))
1647 young
|= kvm_tdp_mmu_age_gfn_range(kvm
, range
);
1652 bool kvm_test_age_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1656 if (kvm_memslots_have_rmaps(kvm
))
1657 young
= kvm_handle_gfn_range(kvm
, range
, kvm_test_age_rmapp
);
1659 if (is_tdp_mmu_enabled(kvm
))
1660 young
|= kvm_tdp_mmu_test_age_gfn(kvm
, range
);
1666 static int is_empty_shadow_page(u64
*spt
)
1671 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1672 if (is_shadow_present_pte(*pos
)) {
1673 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1682 * This value is the sum of all of the kvm instances's
1683 * kvm->arch.n_used_mmu_pages values. We need a global,
1684 * aggregate version in order to make the slab shrinker
1687 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, long nr
)
1689 kvm
->arch
.n_used_mmu_pages
+= nr
;
1690 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1693 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1695 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1696 hlist_del(&sp
->hash_link
);
1697 list_del(&sp
->link
);
1698 free_page((unsigned long)sp
->spt
);
1699 if (!sp
->role
.direct
)
1700 free_page((unsigned long)sp
->gfns
);
1701 kmem_cache_free(mmu_page_header_cache
, sp
);
1704 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1706 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1709 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1710 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1715 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1718 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1721 __pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1724 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1727 mmu_page_remove_parent_pte(sp
, parent_pte
);
1728 mmu_spte_clear_no_track(parent_pte
);
1731 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1733 struct kvm_mmu_page
*sp
;
1735 sp
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1736 sp
->spt
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_shadow_page_cache
);
1738 sp
->gfns
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_gfn_array_cache
);
1739 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1742 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1743 * depends on valid pages being added to the head of the list. See
1744 * comments in kvm_zap_obsolete_pages().
1746 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
1747 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1748 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1752 static void mark_unsync(u64
*spte
);
1753 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1756 struct rmap_iterator iter
;
1758 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1763 static void mark_unsync(u64
*spte
)
1765 struct kvm_mmu_page
*sp
;
1768 sp
= sptep_to_sp(spte
);
1769 index
= spte
- sp
->spt
;
1770 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1772 if (sp
->unsync_children
++)
1774 kvm_mmu_mark_parents_unsync(sp
);
1777 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1778 struct kvm_mmu_page
*sp
)
1783 #define KVM_PAGE_ARRAY_NR 16
1785 struct kvm_mmu_pages
{
1786 struct mmu_page_and_offset
{
1787 struct kvm_mmu_page
*sp
;
1789 } page
[KVM_PAGE_ARRAY_NR
];
1793 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1799 for (i
=0; i
< pvec
->nr
; i
++)
1800 if (pvec
->page
[i
].sp
== sp
)
1803 pvec
->page
[pvec
->nr
].sp
= sp
;
1804 pvec
->page
[pvec
->nr
].idx
= idx
;
1806 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1809 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1811 --sp
->unsync_children
;
1812 WARN_ON((int)sp
->unsync_children
< 0);
1813 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1816 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1817 struct kvm_mmu_pages
*pvec
)
1819 int i
, ret
, nr_unsync_leaf
= 0;
1821 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1822 struct kvm_mmu_page
*child
;
1823 u64 ent
= sp
->spt
[i
];
1825 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1826 clear_unsync_child_bit(sp
, i
);
1830 child
= to_shadow_page(ent
& PT64_BASE_ADDR_MASK
);
1832 if (child
->unsync_children
) {
1833 if (mmu_pages_add(pvec
, child
, i
))
1836 ret
= __mmu_unsync_walk(child
, pvec
);
1838 clear_unsync_child_bit(sp
, i
);
1840 } else if (ret
> 0) {
1841 nr_unsync_leaf
+= ret
;
1844 } else if (child
->unsync
) {
1846 if (mmu_pages_add(pvec
, child
, i
))
1849 clear_unsync_child_bit(sp
, i
);
1852 return nr_unsync_leaf
;
1855 #define INVALID_INDEX (-1)
1857 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1858 struct kvm_mmu_pages
*pvec
)
1861 if (!sp
->unsync_children
)
1864 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1865 return __mmu_unsync_walk(sp
, pvec
);
1868 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1870 WARN_ON(!sp
->unsync
);
1871 trace_kvm_mmu_sync_page(sp
);
1873 --kvm
->stat
.mmu_unsync
;
1876 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1877 struct list_head
*invalid_list
);
1878 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1879 struct list_head
*invalid_list
);
1881 #define for_each_valid_sp(_kvm, _sp, _list) \
1882 hlist_for_each_entry(_sp, _list, hash_link) \
1883 if (is_obsolete_sp((_kvm), (_sp))) { \
1886 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1887 for_each_valid_sp(_kvm, _sp, \
1888 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1889 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1891 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1892 struct list_head
*invalid_list
)
1894 if (vcpu
->arch
.mmu
->sync_page(vcpu
, sp
) == 0) {
1895 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1902 static bool kvm_mmu_remote_flush_or_zap(struct kvm
*kvm
,
1903 struct list_head
*invalid_list
,
1906 if (!remote_flush
&& list_empty(invalid_list
))
1909 if (!list_empty(invalid_list
))
1910 kvm_mmu_commit_zap_page(kvm
, invalid_list
);
1912 kvm_flush_remote_tlbs(kvm
);
1916 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1917 struct list_head
*invalid_list
,
1918 bool remote_flush
, bool local_flush
)
1920 if (kvm_mmu_remote_flush_or_zap(vcpu
->kvm
, invalid_list
, remote_flush
))
1924 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
1927 #ifdef CONFIG_KVM_MMU_AUDIT
1928 #include "mmu_audit.c"
1930 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1931 static void mmu_audit_disable(void) { }
1934 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1936 return sp
->role
.invalid
||
1937 unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1940 struct mmu_page_path
{
1941 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
1942 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
1945 #define for_each_sp(pvec, sp, parents, i) \
1946 for (i = mmu_pages_first(&pvec, &parents); \
1947 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1948 i = mmu_pages_next(&pvec, &parents, i))
1950 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1951 struct mmu_page_path
*parents
,
1956 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1957 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1958 unsigned idx
= pvec
->page
[n
].idx
;
1959 int level
= sp
->role
.level
;
1961 parents
->idx
[level
-1] = idx
;
1962 if (level
== PG_LEVEL_4K
)
1965 parents
->parent
[level
-2] = sp
;
1971 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
1972 struct mmu_page_path
*parents
)
1974 struct kvm_mmu_page
*sp
;
1980 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
1982 sp
= pvec
->page
[0].sp
;
1983 level
= sp
->role
.level
;
1984 WARN_ON(level
== PG_LEVEL_4K
);
1986 parents
->parent
[level
-2] = sp
;
1988 /* Also set up a sentinel. Further entries in pvec are all
1989 * children of sp, so this element is never overwritten.
1991 parents
->parent
[level
-1] = NULL
;
1992 return mmu_pages_next(pvec
, parents
, 0);
1995 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1997 struct kvm_mmu_page
*sp
;
1998 unsigned int level
= 0;
2001 unsigned int idx
= parents
->idx
[level
];
2002 sp
= parents
->parent
[level
];
2006 WARN_ON(idx
== INVALID_INDEX
);
2007 clear_unsync_child_bit(sp
, idx
);
2009 } while (!sp
->unsync_children
);
2012 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2013 struct kvm_mmu_page
*parent
)
2016 struct kvm_mmu_page
*sp
;
2017 struct mmu_page_path parents
;
2018 struct kvm_mmu_pages pages
;
2019 LIST_HEAD(invalid_list
);
2022 while (mmu_unsync_walk(parent
, &pages
)) {
2023 bool protected = false;
2025 for_each_sp(pages
, sp
, parents
, i
)
2026 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2029 kvm_flush_remote_tlbs(vcpu
->kvm
);
2033 for_each_sp(pages
, sp
, parents
, i
) {
2034 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2035 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2036 mmu_pages_clear_parents(&parents
);
2038 if (need_resched() || rwlock_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2039 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2040 cond_resched_rwlock_write(&vcpu
->kvm
->mmu_lock
);
2045 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2048 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2050 atomic_set(&sp
->write_flooding_count
, 0);
2053 static void clear_sp_write_flooding_count(u64
*spte
)
2055 __clear_sp_write_flooding_count(sptep_to_sp(spte
));
2058 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2063 unsigned int access
)
2065 bool direct_mmu
= vcpu
->arch
.mmu
->direct_map
;
2066 union kvm_mmu_page_role role
;
2067 struct hlist_head
*sp_list
;
2069 struct kvm_mmu_page
*sp
;
2071 LIST_HEAD(invalid_list
);
2073 role
= vcpu
->arch
.mmu
->mmu_role
.base
;
2075 role
.direct
= direct
;
2077 role
.gpte_is_8_bytes
= true;
2078 role
.access
= access
;
2079 if (!direct_mmu
&& vcpu
->arch
.mmu
->root_level
<= PT32_ROOT_LEVEL
) {
2080 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2081 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2082 role
.quadrant
= quadrant
;
2085 sp_list
= &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)];
2086 for_each_valid_sp(vcpu
->kvm
, sp
, sp_list
) {
2087 if (sp
->gfn
!= gfn
) {
2092 if (sp
->role
.word
!= role
.word
) {
2094 * If the guest is creating an upper-level page, zap
2095 * unsync pages for the same gfn. While it's possible
2096 * the guest is using recursive page tables, in all
2097 * likelihood the guest has stopped using the unsync
2098 * page and is installing a completely unrelated page.
2099 * Unsync pages must not be left as is, because the new
2100 * upper-level page will be write-protected.
2102 if (level
> PG_LEVEL_4K
&& sp
->unsync
)
2103 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2109 goto trace_get_page
;
2113 * The page is good, but is stale. kvm_sync_page does
2114 * get the latest guest state, but (unlike mmu_unsync_children)
2115 * it doesn't write-protect the page or mark it synchronized!
2116 * This way the validity of the mapping is ensured, but the
2117 * overhead of write protection is not incurred until the
2118 * guest invalidates the TLB mapping. This allows multiple
2119 * SPs for a single gfn to be unsync.
2121 * If the sync fails, the page is zapped. If so, break
2122 * in order to rebuild it.
2124 if (!kvm_sync_page(vcpu
, sp
, &invalid_list
))
2127 WARN_ON(!list_empty(&invalid_list
));
2128 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2131 if (sp
->unsync_children
)
2132 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2134 __clear_sp_write_flooding_count(sp
);
2137 trace_kvm_mmu_get_page(sp
, false);
2141 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2143 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2147 hlist_add_head(&sp
->hash_link
, sp_list
);
2149 account_shadowed(vcpu
->kvm
, sp
);
2150 if (level
== PG_LEVEL_4K
&& rmap_write_protect(vcpu
, gfn
))
2151 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
, 1);
2153 trace_kvm_mmu_get_page(sp
, true);
2155 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2157 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2158 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2162 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator
*iterator
,
2163 struct kvm_vcpu
*vcpu
, hpa_t root
,
2166 iterator
->addr
= addr
;
2167 iterator
->shadow_addr
= root
;
2168 iterator
->level
= vcpu
->arch
.mmu
->shadow_root_level
;
2170 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2171 vcpu
->arch
.mmu
->root_level
< PT64_ROOT_4LEVEL
&&
2172 !vcpu
->arch
.mmu
->direct_map
)
2175 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2177 * prev_root is currently only used for 64-bit hosts. So only
2178 * the active root_hpa is valid here.
2180 BUG_ON(root
!= vcpu
->arch
.mmu
->root_hpa
);
2182 iterator
->shadow_addr
2183 = vcpu
->arch
.mmu
->pae_root
[(addr
>> 30) & 3];
2184 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2186 if (!iterator
->shadow_addr
)
2187 iterator
->level
= 0;
2191 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2192 struct kvm_vcpu
*vcpu
, u64 addr
)
2194 shadow_walk_init_using_root(iterator
, vcpu
, vcpu
->arch
.mmu
->root_hpa
,
2198 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2200 if (iterator
->level
< PG_LEVEL_4K
)
2203 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2204 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2208 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2211 if (is_last_spte(spte
, iterator
->level
)) {
2212 iterator
->level
= 0;
2216 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2220 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2222 __shadow_walk_next(iterator
, *iterator
->sptep
);
2225 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2226 struct kvm_mmu_page
*sp
)
2230 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2232 spte
= make_nonleaf_spte(sp
->spt
, sp_ad_disabled(sp
));
2234 mmu_spte_set(sptep
, spte
);
2236 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2238 if (sp
->unsync_children
|| sp
->unsync
)
2242 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2243 unsigned direct_access
)
2245 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2246 struct kvm_mmu_page
*child
;
2249 * For the direct sp, if the guest pte's dirty bit
2250 * changed form clean to dirty, it will corrupt the
2251 * sp's access: allow writable in the read-only sp,
2252 * so we should update the spte at this point to get
2253 * a new sp with the correct access.
2255 child
= to_shadow_page(*sptep
& PT64_BASE_ADDR_MASK
);
2256 if (child
->role
.access
== direct_access
)
2259 drop_parent_pte(child
, sptep
);
2260 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, child
->gfn
, 1);
2264 /* Returns the number of zapped non-leaf child shadow pages. */
2265 static int mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2266 u64
*spte
, struct list_head
*invalid_list
)
2269 struct kvm_mmu_page
*child
;
2272 if (is_shadow_present_pte(pte
)) {
2273 if (is_last_spte(pte
, sp
->role
.level
)) {
2274 drop_spte(kvm
, spte
);
2275 if (is_large_pte(pte
))
2278 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2279 drop_parent_pte(child
, spte
);
2282 * Recursively zap nested TDP SPs, parentless SPs are
2283 * unlikely to be used again in the near future. This
2284 * avoids retaining a large number of stale nested SPs.
2286 if (tdp_enabled
&& invalid_list
&&
2287 child
->role
.guest_mode
&& !child
->parent_ptes
.val
)
2288 return kvm_mmu_prepare_zap_page(kvm
, child
,
2291 } else if (is_mmio_spte(pte
)) {
2292 mmu_spte_clear_no_track(spte
);
2297 static int kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2298 struct kvm_mmu_page
*sp
,
2299 struct list_head
*invalid_list
)
2304 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2305 zapped
+= mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
, invalid_list
);
2310 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2313 struct rmap_iterator iter
;
2315 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2316 drop_parent_pte(sp
, sptep
);
2319 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2320 struct kvm_mmu_page
*parent
,
2321 struct list_head
*invalid_list
)
2324 struct mmu_page_path parents
;
2325 struct kvm_mmu_pages pages
;
2327 if (parent
->role
.level
== PG_LEVEL_4K
)
2330 while (mmu_unsync_walk(parent
, &pages
)) {
2331 struct kvm_mmu_page
*sp
;
2333 for_each_sp(pages
, sp
, parents
, i
) {
2334 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2335 mmu_pages_clear_parents(&parents
);
2343 static bool __kvm_mmu_prepare_zap_page(struct kvm
*kvm
,
2344 struct kvm_mmu_page
*sp
,
2345 struct list_head
*invalid_list
,
2350 trace_kvm_mmu_prepare_zap_page(sp
);
2351 ++kvm
->stat
.mmu_shadow_zapped
;
2352 *nr_zapped
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2353 *nr_zapped
+= kvm_mmu_page_unlink_children(kvm
, sp
, invalid_list
);
2354 kvm_mmu_unlink_parents(kvm
, sp
);
2356 /* Zapping children means active_mmu_pages has become unstable. */
2357 list_unstable
= *nr_zapped
;
2359 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2360 unaccount_shadowed(kvm
, sp
);
2363 kvm_unlink_unsync_page(kvm
, sp
);
2364 if (!sp
->root_count
) {
2369 * Already invalid pages (previously active roots) are not on
2370 * the active page list. See list_del() in the "else" case of
2373 if (sp
->role
.invalid
)
2374 list_add(&sp
->link
, invalid_list
);
2376 list_move(&sp
->link
, invalid_list
);
2377 kvm_mod_used_mmu_pages(kvm
, -1);
2380 * Remove the active root from the active page list, the root
2381 * will be explicitly freed when the root_count hits zero.
2383 list_del(&sp
->link
);
2386 * Obsolete pages cannot be used on any vCPUs, see the comment
2387 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2388 * treats invalid shadow pages as being obsolete.
2390 if (!is_obsolete_sp(kvm
, sp
))
2391 kvm_reload_remote_mmus(kvm
);
2394 if (sp
->lpage_disallowed
)
2395 unaccount_huge_nx_page(kvm
, sp
);
2397 sp
->role
.invalid
= 1;
2398 return list_unstable
;
2401 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2402 struct list_head
*invalid_list
)
2406 __kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
, &nr_zapped
);
2410 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2411 struct list_head
*invalid_list
)
2413 struct kvm_mmu_page
*sp
, *nsp
;
2415 if (list_empty(invalid_list
))
2419 * We need to make sure everyone sees our modifications to
2420 * the page tables and see changes to vcpu->mode here. The barrier
2421 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2422 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2424 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2425 * guest mode and/or lockless shadow page table walks.
2427 kvm_flush_remote_tlbs(kvm
);
2429 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2430 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2431 kvm_mmu_free_page(sp
);
2435 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm
*kvm
,
2436 unsigned long nr_to_zap
)
2438 unsigned long total_zapped
= 0;
2439 struct kvm_mmu_page
*sp
, *tmp
;
2440 LIST_HEAD(invalid_list
);
2444 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2448 list_for_each_entry_safe_reverse(sp
, tmp
, &kvm
->arch
.active_mmu_pages
, link
) {
2450 * Don't zap active root pages, the page itself can't be freed
2451 * and zapping it will just force vCPUs to realloc and reload.
2456 unstable
= __kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
,
2458 total_zapped
+= nr_zapped
;
2459 if (total_zapped
>= nr_to_zap
)
2466 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2468 kvm
->stat
.mmu_recycled
+= total_zapped
;
2469 return total_zapped
;
2472 static inline unsigned long kvm_mmu_available_pages(struct kvm
*kvm
)
2474 if (kvm
->arch
.n_max_mmu_pages
> kvm
->arch
.n_used_mmu_pages
)
2475 return kvm
->arch
.n_max_mmu_pages
-
2476 kvm
->arch
.n_used_mmu_pages
;
2481 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
2483 unsigned long avail
= kvm_mmu_available_pages(vcpu
->kvm
);
2485 if (likely(avail
>= KVM_MIN_FREE_MMU_PAGES
))
2488 kvm_mmu_zap_oldest_mmu_pages(vcpu
->kvm
, KVM_REFILL_PAGES
- avail
);
2491 * Note, this check is intentionally soft, it only guarantees that one
2492 * page is available, while the caller may end up allocating as many as
2493 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2494 * exceeding the (arbitrary by default) limit will not harm the host,
2495 * being too aggressive may unnecessarily kill the guest, and getting an
2496 * exact count is far more trouble than it's worth, especially in the
2499 if (!kvm_mmu_available_pages(vcpu
->kvm
))
2505 * Changing the number of mmu pages allocated to the vm
2506 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2508 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned long goal_nr_mmu_pages
)
2510 write_lock(&kvm
->mmu_lock
);
2512 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2513 kvm_mmu_zap_oldest_mmu_pages(kvm
, kvm
->arch
.n_used_mmu_pages
-
2516 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2519 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2521 write_unlock(&kvm
->mmu_lock
);
2524 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2526 struct kvm_mmu_page
*sp
;
2527 LIST_HEAD(invalid_list
);
2530 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2532 write_lock(&kvm
->mmu_lock
);
2533 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2534 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2537 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2539 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2540 write_unlock(&kvm
->mmu_lock
);
2545 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
2550 if (vcpu
->arch
.mmu
->direct_map
)
2553 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
2555 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
2560 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2562 trace_kvm_mmu_unsync_page(sp
);
2563 ++vcpu
->kvm
->stat
.mmu_unsync
;
2566 kvm_mmu_mark_parents_unsync(sp
);
2570 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2571 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2572 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2573 * be write-protected.
2575 int mmu_try_to_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool can_unsync
)
2577 struct kvm_mmu_page
*sp
;
2580 * Force write-protection if the page is being tracked. Note, the page
2581 * track machinery is used to write-protect upper-level shadow pages,
2582 * i.e. this guards the role.level == 4K assertion below!
2584 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2588 * The page is not write-tracked, mark existing shadow pages unsync
2589 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2590 * that case, KVM must complete emulation of the guest TLB flush before
2591 * allowing shadow pages to become unsync (writable by the guest).
2593 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2600 WARN_ON(sp
->role
.level
!= PG_LEVEL_4K
);
2601 kvm_unsync_page(vcpu
, sp
);
2605 * We need to ensure that the marking of unsync pages is visible
2606 * before the SPTE is updated to allow writes because
2607 * kvm_mmu_sync_roots() checks the unsync flags without holding
2608 * the MMU lock and so can race with this. If the SPTE was updated
2609 * before the page had been marked as unsync-ed, something like the
2610 * following could happen:
2613 * ---------------------------------------------------------------------
2614 * 1.2 Host updates SPTE
2616 * 2.1 Guest writes a GPTE for GVA X.
2617 * (GPTE being in the guest page table shadowed
2618 * by the SP from CPU 1.)
2619 * This reads SPTE during the page table walk.
2620 * Since SPTE.W is read as 1, there is no
2623 * 2.2 Guest issues TLB flush.
2624 * That causes a VM Exit.
2626 * 2.3 Walking of unsync pages sees sp->unsync is
2627 * false and skips the page.
2629 * 2.4 Guest accesses GVA X.
2630 * Since the mapping in the SP was not updated,
2631 * so the old mapping for GVA X incorrectly
2635 * (sp->unsync = true)
2637 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2638 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2639 * pairs with this write barrier.
2646 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2647 unsigned int pte_access
, int level
,
2648 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2649 bool can_unsync
, bool host_writable
)
2652 struct kvm_mmu_page
*sp
;
2655 sp
= sptep_to_sp(sptep
);
2657 ret
= make_spte(vcpu
, pte_access
, level
, gfn
, pfn
, *sptep
, speculative
,
2658 can_unsync
, host_writable
, sp_ad_disabled(sp
), &spte
);
2660 if (spte
& PT_WRITABLE_MASK
)
2661 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2664 ret
|= SET_SPTE_SPURIOUS
;
2665 else if (mmu_spte_update(sptep
, spte
))
2666 ret
|= SET_SPTE_NEED_REMOTE_TLB_FLUSH
;
2670 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2671 unsigned int pte_access
, bool write_fault
, int level
,
2672 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2675 int was_rmapped
= 0;
2678 int ret
= RET_PF_FIXED
;
2681 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2682 *sptep
, write_fault
, gfn
);
2684 if (unlikely(is_noslot_pfn(pfn
))) {
2685 mark_mmio_spte(vcpu
, sptep
, gfn
, pte_access
);
2686 return RET_PF_EMULATE
;
2689 if (is_shadow_present_pte(*sptep
)) {
2691 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2692 * the parent of the now unreachable PTE.
2694 if (level
> PG_LEVEL_4K
&& !is_large_pte(*sptep
)) {
2695 struct kvm_mmu_page
*child
;
2698 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2699 drop_parent_pte(child
, sptep
);
2701 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2702 pgprintk("hfn old %llx new %llx\n",
2703 spte_to_pfn(*sptep
), pfn
);
2704 drop_spte(vcpu
->kvm
, sptep
);
2710 set_spte_ret
= set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
,
2711 speculative
, true, host_writable
);
2712 if (set_spte_ret
& SET_SPTE_WRITE_PROTECTED_PT
) {
2714 ret
= RET_PF_EMULATE
;
2715 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2718 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
|| flush
)
2719 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
,
2720 KVM_PAGES_PER_HPAGE(level
));
2723 * The fault is fully spurious if and only if the new SPTE and old SPTE
2724 * are identical, and emulation is not required.
2726 if ((set_spte_ret
& SET_SPTE_SPURIOUS
) && ret
== RET_PF_FIXED
) {
2727 WARN_ON_ONCE(!was_rmapped
);
2728 return RET_PF_SPURIOUS
;
2731 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2732 trace_kvm_mmu_set_spte(level
, gfn
, sptep
);
2733 if (!was_rmapped
&& is_large_pte(*sptep
))
2734 ++vcpu
->kvm
->stat
.lpages
;
2736 if (is_shadow_present_pte(*sptep
)) {
2738 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2739 if (rmap_count
> vcpu
->kvm
->stat
.max_mmu_rmap_size
)
2740 vcpu
->kvm
->stat
.max_mmu_rmap_size
= rmap_count
;
2741 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2742 rmap_recycle(vcpu
, sptep
, gfn
);
2749 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2752 struct kvm_memory_slot
*slot
;
2754 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2756 return KVM_PFN_ERR_FAULT
;
2758 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2761 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2762 struct kvm_mmu_page
*sp
,
2763 u64
*start
, u64
*end
)
2765 struct page
*pages
[PTE_PREFETCH_NUM
];
2766 struct kvm_memory_slot
*slot
;
2767 unsigned int access
= sp
->role
.access
;
2771 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2772 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2776 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2780 for (i
= 0; i
< ret
; i
++, gfn
++, start
++) {
2781 mmu_set_spte(vcpu
, start
, access
, false, sp
->role
.level
, gfn
,
2782 page_to_pfn(pages
[i
]), true, true);
2789 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2790 struct kvm_mmu_page
*sp
, u64
*sptep
)
2792 u64
*spte
, *start
= NULL
;
2795 WARN_ON(!sp
->role
.direct
);
2797 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2800 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2801 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2804 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2812 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2814 struct kvm_mmu_page
*sp
;
2816 sp
= sptep_to_sp(sptep
);
2819 * Without accessed bits, there's no way to distinguish between
2820 * actually accessed translations and prefetched, so disable pte
2821 * prefetch if accessed bits aren't available.
2823 if (sp_ad_disabled(sp
))
2826 if (sp
->role
.level
> PG_LEVEL_4K
)
2830 * If addresses are being invalidated, skip prefetching to avoid
2831 * accidentally prefetching those addresses.
2833 if (unlikely(vcpu
->kvm
->mmu_notifier_count
))
2836 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2839 static int host_pfn_mapping_level(struct kvm
*kvm
, gfn_t gfn
, kvm_pfn_t pfn
,
2840 const struct kvm_memory_slot
*slot
)
2846 if (!PageCompound(pfn_to_page(pfn
)) && !kvm_is_zone_device_pfn(pfn
))
2850 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2851 * is not solely for performance, it's also necessary to avoid the
2852 * "writable" check in __gfn_to_hva_many(), which will always fail on
2853 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2854 * page fault steps have already verified the guest isn't writing a
2855 * read-only memslot.
2857 hva
= __gfn_to_hva_memslot(slot
, gfn
);
2859 pte
= lookup_address_in_mm(kvm
->mm
, hva
, &level
);
2866 int kvm_mmu_max_mapping_level(struct kvm
*kvm
,
2867 const struct kvm_memory_slot
*slot
, gfn_t gfn
,
2868 kvm_pfn_t pfn
, int max_level
)
2870 struct kvm_lpage_info
*linfo
;
2872 max_level
= min(max_level
, max_huge_page_level
);
2873 for ( ; max_level
> PG_LEVEL_4K
; max_level
--) {
2874 linfo
= lpage_info_slot(gfn
, slot
, max_level
);
2875 if (!linfo
->disallow_lpage
)
2879 if (max_level
== PG_LEVEL_4K
)
2882 return host_pfn_mapping_level(kvm
, gfn
, pfn
, slot
);
2885 int kvm_mmu_hugepage_adjust(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2886 int max_level
, kvm_pfn_t
*pfnp
,
2887 bool huge_page_disallowed
, int *req_level
)
2889 struct kvm_memory_slot
*slot
;
2890 kvm_pfn_t pfn
= *pfnp
;
2894 *req_level
= PG_LEVEL_4K
;
2896 if (unlikely(max_level
== PG_LEVEL_4K
))
2899 if (is_error_noslot_pfn(pfn
) || kvm_is_reserved_pfn(pfn
))
2902 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, true);
2906 level
= kvm_mmu_max_mapping_level(vcpu
->kvm
, slot
, gfn
, pfn
, max_level
);
2907 if (level
== PG_LEVEL_4K
)
2910 *req_level
= level
= min(level
, max_level
);
2913 * Enforce the iTLB multihit workaround after capturing the requested
2914 * level, which will be used to do precise, accurate accounting.
2916 if (huge_page_disallowed
)
2920 * mmu_notifier_retry() was successful and mmu_lock is held, so
2921 * the pmd can't be split from under us.
2923 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2924 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2925 *pfnp
= pfn
& ~mask
;
2930 void disallowed_hugepage_adjust(u64 spte
, gfn_t gfn
, int cur_level
,
2931 kvm_pfn_t
*pfnp
, int *goal_levelp
)
2933 int level
= *goal_levelp
;
2935 if (cur_level
== level
&& level
> PG_LEVEL_4K
&&
2936 is_shadow_present_pte(spte
) &&
2937 !is_large_pte(spte
)) {
2939 * A small SPTE exists for this pfn, but FNAME(fetch)
2940 * and __direct_map would like to create a large PTE
2941 * instead: just force them to go down another level,
2942 * patching back for them into pfn the next 9 bits of
2945 u64 page_mask
= KVM_PAGES_PER_HPAGE(level
) -
2946 KVM_PAGES_PER_HPAGE(level
- 1);
2947 *pfnp
|= gfn
& page_mask
;
2952 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
2953 int map_writable
, int max_level
, kvm_pfn_t pfn
,
2954 bool prefault
, bool is_tdp
)
2956 bool nx_huge_page_workaround_enabled
= is_nx_huge_page_enabled();
2957 bool write
= error_code
& PFERR_WRITE_MASK
;
2958 bool exec
= error_code
& PFERR_FETCH_MASK
;
2959 bool huge_page_disallowed
= exec
&& nx_huge_page_workaround_enabled
;
2960 struct kvm_shadow_walk_iterator it
;
2961 struct kvm_mmu_page
*sp
;
2962 int level
, req_level
, ret
;
2963 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
2964 gfn_t base_gfn
= gfn
;
2966 level
= kvm_mmu_hugepage_adjust(vcpu
, gfn
, max_level
, &pfn
,
2967 huge_page_disallowed
, &req_level
);
2969 trace_kvm_mmu_spte_requested(gpa
, level
, pfn
);
2970 for_each_shadow_entry(vcpu
, gpa
, it
) {
2972 * We cannot overwrite existing page tables with an NX
2973 * large page, as the leaf could be executable.
2975 if (nx_huge_page_workaround_enabled
)
2976 disallowed_hugepage_adjust(*it
.sptep
, gfn
, it
.level
,
2979 base_gfn
= gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
2980 if (it
.level
== level
)
2983 drop_large_spte(vcpu
, it
.sptep
);
2984 if (is_shadow_present_pte(*it
.sptep
))
2987 sp
= kvm_mmu_get_page(vcpu
, base_gfn
, it
.addr
,
2988 it
.level
- 1, true, ACC_ALL
);
2990 link_shadow_page(vcpu
, it
.sptep
, sp
);
2991 if (is_tdp
&& huge_page_disallowed
&&
2992 req_level
>= it
.level
)
2993 account_huge_nx_page(vcpu
->kvm
, sp
);
2996 ret
= mmu_set_spte(vcpu
, it
.sptep
, ACC_ALL
,
2997 write
, level
, base_gfn
, pfn
, prefault
,
2999 if (ret
== RET_PF_SPURIOUS
)
3002 direct_pte_prefetch(vcpu
, it
.sptep
);
3003 ++vcpu
->stat
.pf_fixed
;
3007 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
3009 send_sig_mceerr(BUS_MCEERR_AR
, (void __user
*)address
, PAGE_SHIFT
, tsk
);
3012 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
3015 * Do not cache the mmio info caused by writing the readonly gfn
3016 * into the spte otherwise read access on readonly gfn also can
3017 * caused mmio page fault and treat it as mmio access.
3019 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3020 return RET_PF_EMULATE
;
3022 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3023 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3024 return RET_PF_RETRY
;
3030 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3031 kvm_pfn_t pfn
, unsigned int access
,
3034 /* The pfn is invalid, report the error! */
3035 if (unlikely(is_error_pfn(pfn
))) {
3036 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3040 if (unlikely(is_noslot_pfn(pfn
))) {
3041 vcpu_cache_mmio_info(vcpu
, gva
, gfn
,
3042 access
& shadow_mmio_access_mask
);
3044 * If MMIO caching is disabled, emulate immediately without
3045 * touching the shadow page tables as attempting to install an
3046 * MMIO SPTE will just be an expensive nop.
3048 if (unlikely(!shadow_mmio_value
)) {
3049 *ret_val
= RET_PF_EMULATE
;
3057 static bool page_fault_can_be_fast(u32 error_code
)
3060 * Do not fix the mmio spte with invalid generation number which
3061 * need to be updated by slow page fault path.
3063 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3066 /* See if the page fault is due to an NX violation */
3067 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3068 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3072 * #PF can be fast if:
3073 * 1. The shadow page table entry is not present, which could mean that
3074 * the fault is potentially caused by access tracking (if enabled).
3075 * 2. The shadow page table entry is present and the fault
3076 * is caused by write-protect, that means we just need change the W
3077 * bit of the spte which can be done out of mmu-lock.
3079 * However, if access tracking is disabled we know that a non-present
3080 * page must be a genuine page fault where we have to create a new SPTE.
3081 * So, if access tracking is disabled, we return true only for write
3082 * accesses to a present page.
3085 return shadow_acc_track_mask
!= 0 ||
3086 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3087 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3091 * Returns true if the SPTE was fixed successfully. Otherwise,
3092 * someone else modified the SPTE from its original value.
3095 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3096 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3100 WARN_ON(!sp
->role
.direct
);
3103 * Theoretically we could also set dirty bit (and flush TLB) here in
3104 * order to eliminate unnecessary PML logging. See comments in
3105 * set_spte. But fast_page_fault is very unlikely to happen with PML
3106 * enabled, so we do not do this. This might result in the same GPA
3107 * to be logged in PML buffer again when the write really happens, and
3108 * eventually to be called by mark_page_dirty twice. But it's also no
3109 * harm. This also avoids the TLB flush needed after setting dirty bit
3110 * so non-PML cases won't be impacted.
3112 * Compare with set_spte where instead shadow_dirty_mask is set.
3114 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3117 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3119 * The gfn of direct spte is stable since it is
3120 * calculated by sp->gfn.
3122 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3123 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3129 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3131 if (fault_err_code
& PFERR_FETCH_MASK
)
3132 return is_executable_pte(spte
);
3134 if (fault_err_code
& PFERR_WRITE_MASK
)
3135 return is_writable_pte(spte
);
3137 /* Fault was on Read access */
3138 return spte
& PT_PRESENT_MASK
;
3142 * Returns the last level spte pointer of the shadow page walk for the given
3143 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3144 * walk could be performed, returns NULL and *spte does not contain valid data.
3147 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3148 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3150 static u64
*fast_pf_get_last_sptep(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u64
*spte
)
3152 struct kvm_shadow_walk_iterator iterator
;
3156 for_each_shadow_entry_lockless(vcpu
, gpa
, iterator
, old_spte
) {
3157 sptep
= iterator
.sptep
;
3160 if (!is_shadow_present_pte(old_spte
))
3168 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3170 static int fast_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
)
3172 struct kvm_mmu_page
*sp
;
3173 int ret
= RET_PF_INVALID
;
3176 uint retry_count
= 0;
3178 if (!page_fault_can_be_fast(error_code
))
3181 walk_shadow_page_lockless_begin(vcpu
);
3186 if (is_tdp_mmu(vcpu
->arch
.mmu
))
3187 sptep
= kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu
, gpa
, &spte
);
3189 sptep
= fast_pf_get_last_sptep(vcpu
, gpa
, &spte
);
3191 if (!is_shadow_present_pte(spte
))
3194 sp
= sptep_to_sp(sptep
);
3195 if (!is_last_spte(spte
, sp
->role
.level
))
3199 * Check whether the memory access that caused the fault would
3200 * still cause it if it were to be performed right now. If not,
3201 * then this is a spurious fault caused by TLB lazily flushed,
3202 * or some other CPU has already fixed the PTE after the
3203 * current CPU took the fault.
3205 * Need not check the access of upper level table entries since
3206 * they are always ACC_ALL.
3208 if (is_access_allowed(error_code
, spte
)) {
3209 ret
= RET_PF_SPURIOUS
;
3215 if (is_access_track_spte(spte
))
3216 new_spte
= restore_acc_track_spte(new_spte
);
3219 * Currently, to simplify the code, write-protection can
3220 * be removed in the fast path only if the SPTE was
3221 * write-protected for dirty-logging or access tracking.
3223 if ((error_code
& PFERR_WRITE_MASK
) &&
3224 spte_can_locklessly_be_made_writable(spte
)) {
3225 new_spte
|= PT_WRITABLE_MASK
;
3228 * Do not fix write-permission on the large spte. Since
3229 * we only dirty the first page into the dirty-bitmap in
3230 * fast_pf_fix_direct_spte(), other pages are missed
3231 * if its slot has dirty logging enabled.
3233 * Instead, we let the slow page fault path create a
3234 * normal spte to fix the access.
3236 * See the comments in kvm_arch_commit_memory_region().
3238 if (sp
->role
.level
> PG_LEVEL_4K
)
3242 /* Verify that the fault can be handled in the fast path */
3243 if (new_spte
== spte
||
3244 !is_access_allowed(error_code
, new_spte
))
3248 * Currently, fast page fault only works for direct mapping
3249 * since the gfn is not stable for indirect shadow page. See
3250 * Documentation/virt/kvm/locking.rst to get more detail.
3252 if (fast_pf_fix_direct_spte(vcpu
, sp
, sptep
, spte
, new_spte
)) {
3257 if (++retry_count
> 4) {
3258 printk_once(KERN_WARNING
3259 "kvm: Fast #PF retrying more than 4 times.\n");
3265 trace_fast_page_fault(vcpu
, gpa
, error_code
, sptep
, spte
, ret
);
3266 walk_shadow_page_lockless_end(vcpu
);
3271 static void mmu_free_root_page(struct kvm
*kvm
, hpa_t
*root_hpa
,
3272 struct list_head
*invalid_list
)
3274 struct kvm_mmu_page
*sp
;
3276 if (!VALID_PAGE(*root_hpa
))
3279 sp
= to_shadow_page(*root_hpa
& PT64_BASE_ADDR_MASK
);
3281 if (is_tdp_mmu_page(sp
))
3282 kvm_tdp_mmu_put_root(kvm
, sp
, false);
3283 else if (!--sp
->root_count
&& sp
->role
.invalid
)
3284 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
3286 *root_hpa
= INVALID_PAGE
;
3289 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3290 void kvm_mmu_free_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3291 ulong roots_to_free
)
3293 struct kvm
*kvm
= vcpu
->kvm
;
3295 LIST_HEAD(invalid_list
);
3296 bool free_active_root
= roots_to_free
& KVM_MMU_ROOT_CURRENT
;
3298 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS
>= BITS_PER_LONG
);
3300 /* Before acquiring the MMU lock, see if we need to do any real work. */
3301 if (!(free_active_root
&& VALID_PAGE(mmu
->root_hpa
))) {
3302 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3303 if ((roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
)) &&
3304 VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
3307 if (i
== KVM_MMU_NUM_PREV_ROOTS
)
3311 write_lock(&kvm
->mmu_lock
);
3313 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3314 if (roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
))
3315 mmu_free_root_page(kvm
, &mmu
->prev_roots
[i
].hpa
,
3318 if (free_active_root
) {
3319 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3320 (mmu
->root_level
>= PT64_ROOT_4LEVEL
|| mmu
->direct_map
)) {
3321 mmu_free_root_page(kvm
, &mmu
->root_hpa
, &invalid_list
);
3322 } else if (mmu
->pae_root
) {
3323 for (i
= 0; i
< 4; ++i
) {
3324 if (!IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]))
3327 mmu_free_root_page(kvm
, &mmu
->pae_root
[i
],
3329 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3332 mmu
->root_hpa
= INVALID_PAGE
;
3336 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3337 write_unlock(&kvm
->mmu_lock
);
3339 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots
);
3341 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3343 unsigned long roots_to_free
= 0;
3348 * This should not be called while L2 is active, L2 can't invalidate
3349 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3351 WARN_ON_ONCE(mmu
->mmu_role
.base
.guest_mode
);
3353 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
3354 root_hpa
= mmu
->prev_roots
[i
].hpa
;
3355 if (!VALID_PAGE(root_hpa
))
3358 if (!to_shadow_page(root_hpa
) ||
3359 to_shadow_page(root_hpa
)->role
.guest_mode
)
3360 roots_to_free
|= KVM_MMU_ROOT_PREVIOUS(i
);
3363 kvm_mmu_free_roots(vcpu
, mmu
, roots_to_free
);
3365 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots
);
3368 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3372 if (!kvm_vcpu_is_visible_gfn(vcpu
, root_gfn
)) {
3373 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3380 static hpa_t
mmu_alloc_root(struct kvm_vcpu
*vcpu
, gfn_t gfn
, gva_t gva
,
3381 u8 level
, bool direct
)
3383 struct kvm_mmu_page
*sp
;
3385 sp
= kvm_mmu_get_page(vcpu
, gfn
, gva
, level
, direct
, ACC_ALL
);
3388 return __pa(sp
->spt
);
3391 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3393 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3394 u8 shadow_root_level
= mmu
->shadow_root_level
;
3399 write_lock(&vcpu
->kvm
->mmu_lock
);
3400 r
= make_mmu_pages_available(vcpu
);
3404 if (is_tdp_mmu_enabled(vcpu
->kvm
)) {
3405 root
= kvm_tdp_mmu_get_vcpu_root_hpa(vcpu
);
3406 mmu
->root_hpa
= root
;
3407 } else if (shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3408 root
= mmu_alloc_root(vcpu
, 0, 0, shadow_root_level
, true);
3409 mmu
->root_hpa
= root
;
3410 } else if (shadow_root_level
== PT32E_ROOT_LEVEL
) {
3411 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3416 for (i
= 0; i
< 4; ++i
) {
3417 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3419 root
= mmu_alloc_root(vcpu
, i
<< (30 - PAGE_SHIFT
),
3420 i
<< 30, PT32_ROOT_LEVEL
, true);
3421 mmu
->pae_root
[i
] = root
| PT_PRESENT_MASK
|
3424 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3426 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level
);
3431 /* root_pgd is ignored for direct MMUs. */
3434 write_unlock(&vcpu
->kvm
->mmu_lock
);
3438 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3440 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3441 u64 pdptrs
[4], pm_mask
;
3442 gfn_t root_gfn
, root_pgd
;
3447 root_pgd
= mmu
->get_guest_pgd(vcpu
);
3448 root_gfn
= root_pgd
>> PAGE_SHIFT
;
3450 if (mmu_check_root(vcpu
, root_gfn
))
3454 * On SVM, reading PDPTRs might access guest memory, which might fault
3455 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3457 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3458 for (i
= 0; i
< 4; ++i
) {
3459 pdptrs
[i
] = mmu
->get_pdptr(vcpu
, i
);
3460 if (!(pdptrs
[i
] & PT_PRESENT_MASK
))
3463 if (mmu_check_root(vcpu
, pdptrs
[i
] >> PAGE_SHIFT
))
3468 r
= alloc_all_memslots_rmaps(vcpu
->kvm
);
3472 write_lock(&vcpu
->kvm
->mmu_lock
);
3473 r
= make_mmu_pages_available(vcpu
);
3478 * Do we shadow a long mode page table? If so we need to
3479 * write-protect the guests page table root.
3481 if (mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3482 root
= mmu_alloc_root(vcpu
, root_gfn
, 0,
3483 mmu
->shadow_root_level
, false);
3484 mmu
->root_hpa
= root
;
3488 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3494 * We shadow a 32 bit page table. This may be a legacy 2-level
3495 * or a PAE 3-level page table. In either case we need to be aware that
3496 * the shadow page table may be a PAE or a long mode page table.
3498 pm_mask
= PT_PRESENT_MASK
| shadow_me_mask
;
3499 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
) {
3500 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3502 if (WARN_ON_ONCE(!mmu
->pml4_root
)) {
3507 mmu
->pml4_root
[0] = __pa(mmu
->pae_root
) | pm_mask
;
3510 for (i
= 0; i
< 4; ++i
) {
3511 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3513 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3514 if (!(pdptrs
[i
] & PT_PRESENT_MASK
)) {
3515 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3518 root_gfn
= pdptrs
[i
] >> PAGE_SHIFT
;
3521 root
= mmu_alloc_root(vcpu
, root_gfn
, i
<< 30,
3522 PT32_ROOT_LEVEL
, false);
3523 mmu
->pae_root
[i
] = root
| pm_mask
;
3526 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
)
3527 mmu
->root_hpa
= __pa(mmu
->pml4_root
);
3529 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3532 mmu
->root_pgd
= root_pgd
;
3534 write_unlock(&vcpu
->kvm
->mmu_lock
);
3539 static int mmu_alloc_special_roots(struct kvm_vcpu
*vcpu
)
3541 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3542 u64
*pml4_root
, *pae_root
;
3545 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3546 * tables are allocated and initialized at root creation as there is no
3547 * equivalent level in the guest's NPT to shadow. Allocate the tables
3548 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3550 if (mmu
->direct_map
|| mmu
->root_level
>= PT64_ROOT_4LEVEL
||
3551 mmu
->shadow_root_level
< PT64_ROOT_4LEVEL
)
3555 * This mess only works with 4-level paging and needs to be updated to
3556 * work with 5-level paging.
3558 if (WARN_ON_ONCE(mmu
->shadow_root_level
!= PT64_ROOT_4LEVEL
))
3561 if (mmu
->pae_root
&& mmu
->pml4_root
)
3565 * The special roots should always be allocated in concert. Yell and
3566 * bail if KVM ends up in a state where only one of the roots is valid.
3568 if (WARN_ON_ONCE(!tdp_enabled
|| mmu
->pae_root
|| mmu
->pml4_root
))
3572 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3573 * doesn't need to be decrypted.
3575 pae_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3579 pml4_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3581 free_page((unsigned long)pae_root
);
3585 mmu
->pae_root
= pae_root
;
3586 mmu
->pml4_root
= pml4_root
;
3591 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3594 struct kvm_mmu_page
*sp
;
3596 if (vcpu
->arch
.mmu
->direct_map
)
3599 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
3602 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3604 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3605 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3606 sp
= to_shadow_page(root
);
3609 * Even if another CPU was marking the SP as unsync-ed
3610 * simultaneously, any guest page table changes are not
3611 * guaranteed to be visible anyway until this VCPU issues a TLB
3612 * flush strictly after those changes are made. We only need to
3613 * ensure that the other CPU sets these flags before any actual
3614 * changes to the page tables are made. The comments in
3615 * mmu_try_to_unsync_pages() describe what could go wrong if
3616 * this requirement isn't satisfied.
3618 if (!smp_load_acquire(&sp
->unsync
) &&
3619 !smp_load_acquire(&sp
->unsync_children
))
3622 write_lock(&vcpu
->kvm
->mmu_lock
);
3623 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3625 mmu_sync_children(vcpu
, sp
);
3627 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3628 write_unlock(&vcpu
->kvm
->mmu_lock
);
3632 write_lock(&vcpu
->kvm
->mmu_lock
);
3633 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3635 for (i
= 0; i
< 4; ++i
) {
3636 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3638 if (IS_VALID_PAE_ROOT(root
)) {
3639 root
&= PT64_BASE_ADDR_MASK
;
3640 sp
= to_shadow_page(root
);
3641 mmu_sync_children(vcpu
, sp
);
3645 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3646 write_unlock(&vcpu
->kvm
->mmu_lock
);
3649 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3650 u32 access
, struct x86_exception
*exception
)
3653 exception
->error_code
= 0;
3657 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3659 struct x86_exception
*exception
)
3662 exception
->error_code
= 0;
3663 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3666 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3669 * A nested guest cannot use the MMIO cache if it is using nested
3670 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3672 if (mmu_is_nested(vcpu
))
3676 return vcpu_match_mmio_gpa(vcpu
, addr
);
3678 return vcpu_match_mmio_gva(vcpu
, addr
);
3682 * Return the level of the lowest level SPTE added to sptes.
3683 * That SPTE may be non-present.
3685 * Must be called between walk_shadow_page_lockless_{begin,end}.
3687 static int get_walk(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptes
, int *root_level
)
3689 struct kvm_shadow_walk_iterator iterator
;
3693 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3694 *root_level
= iterator
.level
;
3695 shadow_walk_okay(&iterator
);
3696 __shadow_walk_next(&iterator
, spte
)) {
3697 leaf
= iterator
.level
;
3698 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3702 if (!is_shadow_present_pte(spte
))
3709 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3710 static bool get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3712 u64 sptes
[PT64_ROOT_MAX_LEVEL
+ 1];
3713 struct rsvd_bits_validate
*rsvd_check
;
3714 int root
, leaf
, level
;
3715 bool reserved
= false;
3717 walk_shadow_page_lockless_begin(vcpu
);
3719 if (is_tdp_mmu(vcpu
->arch
.mmu
))
3720 leaf
= kvm_tdp_mmu_get_walk(vcpu
, addr
, sptes
, &root
);
3722 leaf
= get_walk(vcpu
, addr
, sptes
, &root
);
3724 walk_shadow_page_lockless_end(vcpu
);
3726 if (unlikely(leaf
< 0)) {
3731 *sptep
= sptes
[leaf
];
3734 * Skip reserved bits checks on the terminal leaf if it's not a valid
3735 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3736 * design, always have reserved bits set. The purpose of the checks is
3737 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3739 if (!is_shadow_present_pte(sptes
[leaf
]))
3742 rsvd_check
= &vcpu
->arch
.mmu
->shadow_zero_check
;
3744 for (level
= root
; level
>= leaf
; level
--)
3745 reserved
|= is_rsvd_spte(rsvd_check
, sptes
[level
], level
);
3748 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3750 for (level
= root
; level
>= leaf
; level
--)
3751 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3752 sptes
[level
], level
,
3753 get_rsvd_bits(rsvd_check
, sptes
[level
], level
));
3759 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3764 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3765 return RET_PF_EMULATE
;
3767 reserved
= get_mmio_spte(vcpu
, addr
, &spte
);
3768 if (WARN_ON(reserved
))
3771 if (is_mmio_spte(spte
)) {
3772 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3773 unsigned int access
= get_mmio_spte_access(spte
);
3775 if (!check_mmio_spte(vcpu
, spte
))
3776 return RET_PF_INVALID
;
3781 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3782 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3783 return RET_PF_EMULATE
;
3787 * If the page table is zapped by other cpus, let CPU fault again on
3790 return RET_PF_RETRY
;
3793 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3794 u32 error_code
, gfn_t gfn
)
3796 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3799 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3800 !(error_code
& PFERR_WRITE_MASK
))
3804 * guest is writing the page which is write tracked which can
3805 * not be fixed by page fault handler.
3807 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3813 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3815 struct kvm_shadow_walk_iterator iterator
;
3818 walk_shadow_page_lockless_begin(vcpu
);
3819 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3820 clear_sp_write_flooding_count(iterator
.sptep
);
3821 if (!is_shadow_present_pte(spte
))
3824 walk_shadow_page_lockless_end(vcpu
);
3827 static bool kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3830 struct kvm_arch_async_pf arch
;
3832 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3834 arch
.direct_map
= vcpu
->arch
.mmu
->direct_map
;
3835 arch
.cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3837 return kvm_setup_async_pf(vcpu
, cr2_or_gpa
,
3838 kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3841 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3842 gpa_t cr2_or_gpa
, kvm_pfn_t
*pfn
, hva_t
*hva
,
3843 bool write
, bool *writable
)
3845 struct kvm_memory_slot
*slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3849 * Retry the page fault if the gfn hit a memslot that is being deleted
3850 * or moved. This ensures any existing SPTEs for the old memslot will
3851 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3853 if (slot
&& (slot
->flags
& KVM_MEMSLOT_INVALID
))
3856 /* Don't expose private memslots to L2. */
3857 if (is_guest_mode(vcpu
) && !kvm_is_visible_memslot(slot
)) {
3858 *pfn
= KVM_PFN_NOSLOT
;
3864 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
,
3865 write
, writable
, hva
);
3867 return false; /* *pfn has correct page already */
3869 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3870 trace_kvm_try_async_get_page(cr2_or_gpa
, gfn
);
3871 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3872 trace_kvm_async_pf_doublefault(cr2_or_gpa
, gfn
);
3873 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3875 } else if (kvm_arch_setup_async_pf(vcpu
, cr2_or_gpa
, gfn
))
3879 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
,
3880 write
, writable
, hva
);
3884 static int direct_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3885 bool prefault
, int max_level
, bool is_tdp
)
3887 bool is_tdp_mmu_fault
= is_tdp_mmu(vcpu
->arch
.mmu
);
3888 bool write
= error_code
& PFERR_WRITE_MASK
;
3891 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3892 unsigned long mmu_seq
;
3897 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3898 return RET_PF_EMULATE
;
3900 r
= fast_page_fault(vcpu
, gpa
, error_code
);
3901 if (r
!= RET_PF_INVALID
)
3904 r
= mmu_topup_memory_caches(vcpu
, false);
3908 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3911 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, &hva
,
3912 write
, &map_writable
))
3913 return RET_PF_RETRY
;
3915 if (handle_abnormal_pfn(vcpu
, is_tdp
? 0 : gpa
, gfn
, pfn
, ACC_ALL
, &r
))
3920 if (is_tdp_mmu_fault
)
3921 read_lock(&vcpu
->kvm
->mmu_lock
);
3923 write_lock(&vcpu
->kvm
->mmu_lock
);
3925 if (!is_noslot_pfn(pfn
) && mmu_notifier_retry_hva(vcpu
->kvm
, mmu_seq
, hva
))
3927 r
= make_mmu_pages_available(vcpu
);
3931 if (is_tdp_mmu_fault
)
3932 r
= kvm_tdp_mmu_map(vcpu
, gpa
, error_code
, map_writable
, max_level
,
3935 r
= __direct_map(vcpu
, gpa
, error_code
, map_writable
, max_level
, pfn
,
3939 if (is_tdp_mmu_fault
)
3940 read_unlock(&vcpu
->kvm
->mmu_lock
);
3942 write_unlock(&vcpu
->kvm
->mmu_lock
);
3943 kvm_release_pfn_clean(pfn
);
3947 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3948 u32 error_code
, bool prefault
)
3950 pgprintk("%s: gva %lx error %x\n", __func__
, gpa
, error_code
);
3952 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3953 return direct_page_fault(vcpu
, gpa
& PAGE_MASK
, error_code
, prefault
,
3954 PG_LEVEL_2M
, false);
3957 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3958 u64 fault_address
, char *insn
, int insn_len
)
3961 u32 flags
= vcpu
->arch
.apf
.host_apf_flags
;
3963 #ifndef CONFIG_X86_64
3964 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3965 if (WARN_ON_ONCE(fault_address
>> 32))
3969 vcpu
->arch
.l1tf_flush_l1d
= true;
3971 trace_kvm_page_fault(fault_address
, error_code
);
3973 if (kvm_event_needs_reinjection(vcpu
))
3974 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3975 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3977 } else if (flags
& KVM_PV_REASON_PAGE_NOT_PRESENT
) {
3978 vcpu
->arch
.apf
.host_apf_flags
= 0;
3979 local_irq_disable();
3980 kvm_async_pf_task_wait_schedule(fault_address
);
3983 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags
);
3988 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3990 int kvm_tdp_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3995 for (max_level
= KVM_MAX_HUGEPAGE_LEVEL
;
3996 max_level
> PG_LEVEL_4K
;
3998 int page_num
= KVM_PAGES_PER_HPAGE(max_level
);
3999 gfn_t base
= (gpa
>> PAGE_SHIFT
) & ~(page_num
- 1);
4001 if (kvm_mtrr_check_gfn_range_consistency(vcpu
, base
, page_num
))
4005 return direct_page_fault(vcpu
, gpa
, error_code
, prefault
,
4009 static void nonpaging_init_context(struct kvm_mmu
*context
)
4011 context
->page_fault
= nonpaging_page_fault
;
4012 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4013 context
->sync_page
= nonpaging_sync_page
;
4014 context
->invlpg
= NULL
;
4015 context
->direct_map
= true;
4018 static inline bool is_root_usable(struct kvm_mmu_root_info
*root
, gpa_t pgd
,
4019 union kvm_mmu_page_role role
)
4021 return (role
.direct
|| pgd
== root
->pgd
) &&
4022 VALID_PAGE(root
->hpa
) && to_shadow_page(root
->hpa
) &&
4023 role
.word
== to_shadow_page(root
->hpa
)->role
.word
;
4027 * Find out if a previously cached root matching the new pgd/role is available.
4028 * The current root is also inserted into the cache.
4029 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4031 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4032 * false is returned. This root should now be freed by the caller.
4034 static bool cached_root_available(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4035 union kvm_mmu_page_role new_role
)
4038 struct kvm_mmu_root_info root
;
4039 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4041 root
.pgd
= mmu
->root_pgd
;
4042 root
.hpa
= mmu
->root_hpa
;
4044 if (is_root_usable(&root
, new_pgd
, new_role
))
4047 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
4048 swap(root
, mmu
->prev_roots
[i
]);
4050 if (is_root_usable(&root
, new_pgd
, new_role
))
4054 mmu
->root_hpa
= root
.hpa
;
4055 mmu
->root_pgd
= root
.pgd
;
4057 return i
< KVM_MMU_NUM_PREV_ROOTS
;
4060 static bool fast_pgd_switch(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4061 union kvm_mmu_page_role new_role
)
4063 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4066 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4067 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4068 * later if necessary.
4070 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
4071 mmu
->root_level
>= PT64_ROOT_4LEVEL
)
4072 return cached_root_available(vcpu
, new_pgd
, new_role
);
4077 static void __kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4078 union kvm_mmu_page_role new_role
)
4080 if (!fast_pgd_switch(vcpu
, new_pgd
, new_role
)) {
4081 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
, KVM_MMU_ROOT_CURRENT
);
4086 * It's possible that the cached previous root page is obsolete because
4087 * of a change in the MMU generation number. However, changing the
4088 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4089 * free the root set here and allocate a new one.
4091 kvm_make_request(KVM_REQ_LOAD_MMU_PGD
, vcpu
);
4093 if (force_flush_and_sync_on_reuse
) {
4094 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
4095 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
4099 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4100 * switching to a new CR3, that GVA->GPA mapping may no longer be
4101 * valid. So clear any cached MMIO info even when we don't need to sync
4102 * the shadow page tables.
4104 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
4107 * If this is a direct root page, it doesn't have a write flooding
4108 * count. Otherwise, clear the write flooding count.
4110 if (!new_role
.direct
)
4111 __clear_sp_write_flooding_count(
4112 to_shadow_page(vcpu
->arch
.mmu
->root_hpa
));
4115 void kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
)
4117 __kvm_mmu_new_pgd(vcpu
, new_pgd
, kvm_mmu_calc_root_page_role(vcpu
));
4119 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd
);
4121 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
4123 return kvm_read_cr3(vcpu
);
4126 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
4127 unsigned int access
, int *nr_present
)
4129 if (unlikely(is_mmio_spte(*sptep
))) {
4130 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
4131 mmu_spte_clear_no_track(sptep
);
4136 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
4143 #define PTTYPE_EPT 18 /* arbitrary */
4144 #define PTTYPE PTTYPE_EPT
4145 #include "paging_tmpl.h"
4149 #include "paging_tmpl.h"
4153 #include "paging_tmpl.h"
4157 __reset_rsvds_bits_mask(struct rsvd_bits_validate
*rsvd_check
,
4158 u64 pa_bits_rsvd
, int level
, bool nx
, bool gbpages
,
4161 u64 gbpages_bit_rsvd
= 0;
4162 u64 nonleaf_bit8_rsvd
= 0;
4165 rsvd_check
->bad_mt_xwr
= 0;
4168 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4170 if (level
== PT32E_ROOT_LEVEL
)
4171 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 62);
4173 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4175 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4177 high_bits_rsvd
|= rsvd_bits(63, 63);
4180 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4181 * leaf entries) on AMD CPUs only.
4184 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4187 case PT32_ROOT_LEVEL
:
4188 /* no rsvd bits for 2 level 4K page table entries */
4189 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4190 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4191 rsvd_check
->rsvd_bits_mask
[1][0] =
4192 rsvd_check
->rsvd_bits_mask
[0][0];
4195 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4199 if (is_cpuid_PSE36())
4200 /* 36bits PSE 4MB page */
4201 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4203 /* 32 bits PSE 4MB page */
4204 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4206 case PT32E_ROOT_LEVEL
:
4207 rsvd_check
->rsvd_bits_mask
[0][2] = rsvd_bits(63, 63) |
4210 rsvd_bits(1, 2); /* PDPTE */
4211 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
; /* PDE */
4212 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
; /* PTE */
4213 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4214 rsvd_bits(13, 20); /* large page */
4215 rsvd_check
->rsvd_bits_mask
[1][0] =
4216 rsvd_check
->rsvd_bits_mask
[0][0];
4218 case PT64_ROOT_5LEVEL
:
4219 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
|
4222 rsvd_check
->rsvd_bits_mask
[1][4] =
4223 rsvd_check
->rsvd_bits_mask
[0][4];
4225 case PT64_ROOT_4LEVEL
:
4226 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
|
4229 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
|
4231 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
;
4232 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4233 rsvd_check
->rsvd_bits_mask
[1][3] =
4234 rsvd_check
->rsvd_bits_mask
[0][3];
4235 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
|
4238 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4239 rsvd_bits(13, 20); /* large page */
4240 rsvd_check
->rsvd_bits_mask
[1][0] =
4241 rsvd_check
->rsvd_bits_mask
[0][0];
4246 static bool guest_can_use_gbpages(struct kvm_vcpu
*vcpu
)
4249 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4250 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4251 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4252 * walk for performance and complexity reasons. Not to mention KVM
4253 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4254 * KVM once a TDP translation is installed. Mimic hardware behavior so
4255 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4257 return tdp_enabled
? boot_cpu_has(X86_FEATURE_GBPAGES
) :
4258 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
);
4261 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4262 struct kvm_mmu
*context
)
4264 __reset_rsvds_bits_mask(&context
->guest_rsvd_check
,
4265 vcpu
->arch
.reserved_gpa_bits
,
4266 context
->root_level
, is_efer_nx(context
),
4267 guest_can_use_gbpages(vcpu
),
4268 is_cr4_pse(context
),
4269 guest_cpuid_is_amd_or_hygon(vcpu
));
4273 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4274 u64 pa_bits_rsvd
, bool execonly
)
4276 u64 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4279 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
| rsvd_bits(3, 7);
4280 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
| rsvd_bits(3, 7);
4281 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
| rsvd_bits(3, 6);
4282 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
| rsvd_bits(3, 6);
4283 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4286 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4287 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4288 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
| rsvd_bits(12, 29);
4289 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
| rsvd_bits(12, 20);
4290 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4292 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4293 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4294 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4295 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4296 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4298 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4299 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4301 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4304 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4305 struct kvm_mmu
*context
, bool execonly
)
4307 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4308 vcpu
->arch
.reserved_gpa_bits
, execonly
);
4311 static inline u64
reserved_hpa_bits(void)
4313 return rsvd_bits(shadow_phys_bits
, 63);
4317 * the page table on host is the shadow page table for the page
4318 * table in guest or amd nested guest, its mmu features completely
4319 * follow the features in guest.
4321 static void reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4322 struct kvm_mmu
*context
)
4325 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4326 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4327 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4328 * The iTLB multi-hit workaround can be toggled at any time, so assume
4329 * NX can be used by any non-nested shadow MMU to avoid having to reset
4330 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4332 bool uses_nx
= is_efer_nx(context
) || !tdp_enabled
;
4334 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4336 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4337 bool is_pse
= false;
4338 struct rsvd_bits_validate
*shadow_zero_check
;
4341 WARN_ON_ONCE(context
->shadow_root_level
< PT32E_ROOT_LEVEL
);
4343 shadow_zero_check
= &context
->shadow_zero_check
;
4344 __reset_rsvds_bits_mask(shadow_zero_check
, reserved_hpa_bits(),
4345 context
->shadow_root_level
, uses_nx
,
4346 guest_can_use_gbpages(vcpu
), is_pse
, is_amd
);
4348 if (!shadow_me_mask
)
4351 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4352 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4353 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4358 static inline bool boot_cpu_is_amd(void)
4360 WARN_ON_ONCE(!tdp_enabled
);
4361 return shadow_x_mask
== 0;
4365 * the direct page table on host, use as much mmu features as
4366 * possible, however, kvm currently does not do execution-protection.
4369 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4370 struct kvm_mmu
*context
)
4372 struct rsvd_bits_validate
*shadow_zero_check
;
4375 shadow_zero_check
= &context
->shadow_zero_check
;
4377 if (boot_cpu_is_amd())
4378 __reset_rsvds_bits_mask(shadow_zero_check
, reserved_hpa_bits(),
4379 context
->shadow_root_level
, false,
4380 boot_cpu_has(X86_FEATURE_GBPAGES
),
4383 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4384 reserved_hpa_bits(), false);
4386 if (!shadow_me_mask
)
4389 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4390 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4391 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4396 * as the comments in reset_shadow_zero_bits_mask() except it
4397 * is the shadow page table for intel nested guest.
4400 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4401 struct kvm_mmu
*context
, bool execonly
)
4403 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4404 reserved_hpa_bits(), execonly
);
4407 #define BYTE_MASK(access) \
4408 ((1 & (access) ? 2 : 0) | \
4409 (2 & (access) ? 4 : 0) | \
4410 (3 & (access) ? 8 : 0) | \
4411 (4 & (access) ? 16 : 0) | \
4412 (5 & (access) ? 32 : 0) | \
4413 (6 & (access) ? 64 : 0) | \
4414 (7 & (access) ? 128 : 0))
4417 static void update_permission_bitmask(struct kvm_mmu
*mmu
, bool ept
)
4421 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4422 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4423 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4425 bool cr4_smep
= is_cr4_smep(mmu
);
4426 bool cr4_smap
= is_cr4_smap(mmu
);
4427 bool cr0_wp
= is_cr0_wp(mmu
);
4428 bool efer_nx
= is_efer_nx(mmu
);
4430 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4431 unsigned pfec
= byte
<< 1;
4434 * Each "*f" variable has a 1 bit for each UWX value
4435 * that causes a fault with the given PFEC.
4438 /* Faults from writes to non-writable pages */
4439 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? (u8
)~w
: 0;
4440 /* Faults from user mode accesses to supervisor pages */
4441 u8 uf
= (pfec
& PFERR_USER_MASK
) ? (u8
)~u
: 0;
4442 /* Faults from fetches of non-executable pages*/
4443 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? (u8
)~x
: 0;
4444 /* Faults from kernel mode fetches of user pages */
4446 /* Faults from kernel mode accesses of user pages */
4450 /* Faults from kernel mode accesses to user pages */
4451 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4453 /* Not really needed: !nx will cause pte.nx to fault */
4457 /* Allow supervisor writes if !cr0.wp */
4459 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4461 /* Disallow supervisor fetches of user code if cr4.smep */
4463 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4466 * SMAP:kernel-mode data accesses from user-mode
4467 * mappings should fault. A fault is considered
4468 * as a SMAP violation if all of the following
4469 * conditions are true:
4470 * - X86_CR4_SMAP is set in CR4
4471 * - A user page is accessed
4472 * - The access is not a fetch
4473 * - Page fault in kernel mode
4474 * - if CPL = 3 or X86_EFLAGS_AC is clear
4476 * Here, we cover the first three conditions.
4477 * The fourth is computed dynamically in permission_fault();
4478 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4479 * *not* subject to SMAP restrictions.
4482 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4485 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4490 * PKU is an additional mechanism by which the paging controls access to
4491 * user-mode addresses based on the value in the PKRU register. Protection
4492 * key violations are reported through a bit in the page fault error code.
4493 * Unlike other bits of the error code, the PK bit is not known at the
4494 * call site of e.g. gva_to_gpa; it must be computed directly in
4495 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4496 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4498 * In particular the following conditions come from the error code, the
4499 * page tables and the machine state:
4500 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4501 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4502 * - PK is always zero if U=0 in the page tables
4503 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4505 * The PKRU bitmask caches the result of these four conditions. The error
4506 * code (minus the P bit) and the page table's U bit form an index into the
4507 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4508 * with the two bits of the PKRU register corresponding to the protection key.
4509 * For the first three conditions above the bits will be 00, thus masking
4510 * away both AD and WD. For all reads or if the last condition holds, WD
4511 * only will be masked away.
4513 static void update_pkru_bitmask(struct kvm_mmu
*mmu
)
4518 if (!is_cr4_pke(mmu
)) {
4523 wp
= is_cr0_wp(mmu
);
4525 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4526 unsigned pfec
, pkey_bits
;
4527 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4530 ff
= pfec
& PFERR_FETCH_MASK
;
4531 uf
= pfec
& PFERR_USER_MASK
;
4532 wf
= pfec
& PFERR_WRITE_MASK
;
4534 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4535 pte_user
= pfec
& PFERR_RSVD_MASK
;
4538 * Only need to check the access which is not an
4539 * instruction fetch and is to a user page.
4541 check_pkey
= (!ff
&& pte_user
);
4543 * write access is controlled by PKRU if it is a
4544 * user access or CR0.WP = 1.
4546 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4548 /* PKRU.AD stops both read and write access. */
4549 pkey_bits
= !!check_pkey
;
4550 /* PKRU.WD stops write access. */
4551 pkey_bits
|= (!!check_write
) << 1;
4553 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4557 static void reset_guest_paging_metadata(struct kvm_vcpu
*vcpu
,
4558 struct kvm_mmu
*mmu
)
4560 if (!is_cr0_pg(mmu
))
4563 reset_rsvds_bits_mask(vcpu
, mmu
);
4564 update_permission_bitmask(mmu
, false);
4565 update_pkru_bitmask(mmu
);
4568 static void paging64_init_context(struct kvm_mmu
*context
)
4570 context
->page_fault
= paging64_page_fault
;
4571 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4572 context
->sync_page
= paging64_sync_page
;
4573 context
->invlpg
= paging64_invlpg
;
4574 context
->direct_map
= false;
4577 static void paging32_init_context(struct kvm_mmu
*context
)
4579 context
->page_fault
= paging32_page_fault
;
4580 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4581 context
->sync_page
= paging32_sync_page
;
4582 context
->invlpg
= paging32_invlpg
;
4583 context
->direct_map
= false;
4586 static union kvm_mmu_extended_role
kvm_calc_mmu_role_ext(struct kvm_vcpu
*vcpu
,
4587 struct kvm_mmu_role_regs
*regs
)
4589 union kvm_mmu_extended_role ext
= {0};
4591 if (____is_cr0_pg(regs
)) {
4593 ext
.cr4_pae
= ____is_cr4_pae(regs
);
4594 ext
.cr4_smep
= ____is_cr4_smep(regs
);
4595 ext
.cr4_smap
= ____is_cr4_smap(regs
);
4596 ext
.cr4_pse
= ____is_cr4_pse(regs
);
4598 /* PKEY and LA57 are active iff long mode is active. */
4599 ext
.cr4_pke
= ____is_efer_lma(regs
) && ____is_cr4_pke(regs
);
4600 ext
.cr4_la57
= ____is_efer_lma(regs
) && ____is_cr4_la57(regs
);
4608 static union kvm_mmu_role
kvm_calc_mmu_role_common(struct kvm_vcpu
*vcpu
,
4609 struct kvm_mmu_role_regs
*regs
,
4612 union kvm_mmu_role role
= {0};
4614 role
.base
.access
= ACC_ALL
;
4615 if (____is_cr0_pg(regs
)) {
4616 role
.base
.efer_nx
= ____is_efer_nx(regs
);
4617 role
.base
.cr0_wp
= ____is_cr0_wp(regs
);
4619 role
.base
.smm
= is_smm(vcpu
);
4620 role
.base
.guest_mode
= is_guest_mode(vcpu
);
4625 role
.ext
= kvm_calc_mmu_role_ext(vcpu
, regs
);
4630 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu
*vcpu
)
4632 /* Use 5-level TDP if and only if it's useful/necessary. */
4633 if (max_tdp_level
== 5 && cpuid_maxphyaddr(vcpu
) <= 48)
4636 return max_tdp_level
;
4639 static union kvm_mmu_role
4640 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu
*vcpu
,
4641 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4643 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, regs
, base_only
);
4645 role
.base
.ad_disabled
= (shadow_accessed_mask
== 0);
4646 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4647 role
.base
.direct
= true;
4648 role
.base
.gpte_is_8_bytes
= true;
4653 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4655 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4656 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4657 union kvm_mmu_role new_role
=
4658 kvm_calc_tdp_mmu_root_page_role(vcpu
, ®s
, false);
4660 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4663 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4664 context
->page_fault
= kvm_tdp_page_fault
;
4665 context
->sync_page
= nonpaging_sync_page
;
4666 context
->invlpg
= NULL
;
4667 context
->shadow_root_level
= kvm_mmu_get_tdp_level(vcpu
);
4668 context
->direct_map
= true;
4669 context
->get_guest_pgd
= get_cr3
;
4670 context
->get_pdptr
= kvm_pdptr_read
;
4671 context
->inject_page_fault
= kvm_inject_page_fault
;
4672 context
->root_level
= role_regs_to_root_level(®s
);
4674 if (!is_cr0_pg(context
))
4675 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4676 else if (is_cr4_pae(context
))
4677 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4679 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4681 reset_guest_paging_metadata(vcpu
, context
);
4682 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4685 static union kvm_mmu_role
4686 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu
*vcpu
,
4687 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4689 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, regs
, base_only
);
4691 role
.base
.smep_andnot_wp
= role
.ext
.cr4_smep
&& !____is_cr0_wp(regs
);
4692 role
.base
.smap_andnot_wp
= role
.ext
.cr4_smap
&& !____is_cr0_wp(regs
);
4693 role
.base
.gpte_is_8_bytes
= ____is_cr0_pg(regs
) && ____is_cr4_pae(regs
);
4698 static union kvm_mmu_role
4699 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu
*vcpu
,
4700 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4702 union kvm_mmu_role role
=
4703 kvm_calc_shadow_root_page_role_common(vcpu
, regs
, base_only
);
4705 role
.base
.direct
= !____is_cr0_pg(regs
);
4707 if (!____is_efer_lma(regs
))
4708 role
.base
.level
= PT32E_ROOT_LEVEL
;
4709 else if (____is_cr4_la57(regs
))
4710 role
.base
.level
= PT64_ROOT_5LEVEL
;
4712 role
.base
.level
= PT64_ROOT_4LEVEL
;
4717 static void shadow_mmu_init_context(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
,
4718 struct kvm_mmu_role_regs
*regs
,
4719 union kvm_mmu_role new_role
)
4721 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4724 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4726 if (!is_cr0_pg(context
))
4727 nonpaging_init_context(context
);
4728 else if (is_cr4_pae(context
))
4729 paging64_init_context(context
);
4731 paging32_init_context(context
);
4732 context
->root_level
= role_regs_to_root_level(regs
);
4734 reset_guest_paging_metadata(vcpu
, context
);
4735 context
->shadow_root_level
= new_role
.base
.level
;
4737 reset_shadow_zero_bits_mask(vcpu
, context
);
4740 static void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
,
4741 struct kvm_mmu_role_regs
*regs
)
4743 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4744 union kvm_mmu_role new_role
=
4745 kvm_calc_shadow_mmu_root_page_role(vcpu
, regs
, false);
4747 shadow_mmu_init_context(vcpu
, context
, regs
, new_role
);
4750 static union kvm_mmu_role
4751 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu
*vcpu
,
4752 struct kvm_mmu_role_regs
*regs
)
4754 union kvm_mmu_role role
=
4755 kvm_calc_shadow_root_page_role_common(vcpu
, regs
, false);
4757 role
.base
.direct
= false;
4758 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4763 void kvm_init_shadow_npt_mmu(struct kvm_vcpu
*vcpu
, unsigned long cr0
,
4764 unsigned long cr4
, u64 efer
, gpa_t nested_cr3
)
4766 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4767 struct kvm_mmu_role_regs regs
= {
4772 union kvm_mmu_role new_role
;
4774 new_role
= kvm_calc_shadow_npt_root_page_role(vcpu
, ®s
);
4776 __kvm_mmu_new_pgd(vcpu
, nested_cr3
, new_role
.base
);
4778 shadow_mmu_init_context(vcpu
, context
, ®s
, new_role
);
4780 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu
);
4782 static union kvm_mmu_role
4783 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu
*vcpu
, bool accessed_dirty
,
4784 bool execonly
, u8 level
)
4786 union kvm_mmu_role role
= {0};
4788 /* SMM flag is inherited from root_mmu */
4789 role
.base
.smm
= vcpu
->arch
.root_mmu
.mmu_role
.base
.smm
;
4791 role
.base
.level
= level
;
4792 role
.base
.gpte_is_8_bytes
= true;
4793 role
.base
.direct
= false;
4794 role
.base
.ad_disabled
= !accessed_dirty
;
4795 role
.base
.guest_mode
= true;
4796 role
.base
.access
= ACC_ALL
;
4798 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4800 role
.ext
.execonly
= execonly
;
4806 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4807 bool accessed_dirty
, gpa_t new_eptp
)
4809 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4810 u8 level
= vmx_eptp_page_walk_level(new_eptp
);
4811 union kvm_mmu_role new_role
=
4812 kvm_calc_shadow_ept_root_page_role(vcpu
, accessed_dirty
,
4815 __kvm_mmu_new_pgd(vcpu
, new_eptp
, new_role
.base
);
4817 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4820 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4822 context
->shadow_root_level
= level
;
4824 context
->ept_ad
= accessed_dirty
;
4825 context
->page_fault
= ept_page_fault
;
4826 context
->gva_to_gpa
= ept_gva_to_gpa
;
4827 context
->sync_page
= ept_sync_page
;
4828 context
->invlpg
= ept_invlpg
;
4829 context
->root_level
= level
;
4830 context
->direct_map
= false;
4832 update_permission_bitmask(context
, true);
4833 update_pkru_bitmask(context
);
4834 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4835 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4837 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4839 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4841 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4842 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4844 kvm_init_shadow_mmu(vcpu
, ®s
);
4846 context
->get_guest_pgd
= get_cr3
;
4847 context
->get_pdptr
= kvm_pdptr_read
;
4848 context
->inject_page_fault
= kvm_inject_page_fault
;
4851 static union kvm_mmu_role
4852 kvm_calc_nested_mmu_role(struct kvm_vcpu
*vcpu
, struct kvm_mmu_role_regs
*regs
)
4854 union kvm_mmu_role role
;
4856 role
= kvm_calc_shadow_root_page_role_common(vcpu
, regs
, false);
4859 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4860 * shadow pages of their own and so "direct" has no meaning. Set it
4861 * to "true" to try to detect bogus usage of the nested MMU.
4863 role
.base
.direct
= true;
4864 role
.base
.level
= role_regs_to_root_level(regs
);
4868 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4870 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4871 union kvm_mmu_role new_role
= kvm_calc_nested_mmu_role(vcpu
, ®s
);
4872 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4874 if (new_role
.as_u64
== g_context
->mmu_role
.as_u64
)
4877 g_context
->mmu_role
.as_u64
= new_role
.as_u64
;
4878 g_context
->get_guest_pgd
= get_cr3
;
4879 g_context
->get_pdptr
= kvm_pdptr_read
;
4880 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4881 g_context
->root_level
= new_role
.base
.level
;
4884 * L2 page tables are never shadowed, so there is no need to sync
4887 g_context
->invlpg
= NULL
;
4890 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4891 * L1's nested page tables (e.g. EPT12). The nested translation
4892 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4893 * L2's page tables as the first level of translation and L1's
4894 * nested page tables as the second level of translation. Basically
4895 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4897 if (!is_paging(vcpu
))
4898 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4899 else if (is_long_mode(vcpu
))
4900 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4901 else if (is_pae(vcpu
))
4902 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4904 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4906 reset_guest_paging_metadata(vcpu
, g_context
);
4909 void kvm_init_mmu(struct kvm_vcpu
*vcpu
)
4911 if (mmu_is_nested(vcpu
))
4912 init_kvm_nested_mmu(vcpu
);
4913 else if (tdp_enabled
)
4914 init_kvm_tdp_mmu(vcpu
);
4916 init_kvm_softmmu(vcpu
);
4918 EXPORT_SYMBOL_GPL(kvm_init_mmu
);
4920 static union kvm_mmu_page_role
4921 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
)
4923 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4924 union kvm_mmu_role role
;
4927 role
= kvm_calc_tdp_mmu_root_page_role(vcpu
, ®s
, true);
4929 role
= kvm_calc_shadow_mmu_root_page_role(vcpu
, ®s
, true);
4934 void kvm_mmu_after_set_cpuid(struct kvm_vcpu
*vcpu
)
4937 * Invalidate all MMU roles to force them to reinitialize as CPUID
4938 * information is factored into reserved bit calculations.
4940 vcpu
->arch
.root_mmu
.mmu_role
.ext
.valid
= 0;
4941 vcpu
->arch
.guest_mmu
.mmu_role
.ext
.valid
= 0;
4942 vcpu
->arch
.nested_mmu
.mmu_role
.ext
.valid
= 0;
4943 kvm_mmu_reset_context(vcpu
);
4946 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4947 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4948 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4949 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4950 * sweep the problem under the rug.
4952 * KVM's horrific CPUID ABI makes the problem all but impossible to
4953 * solve, as correctly handling multiple vCPU models (with respect to
4954 * paging and physical address properties) in a single VM would require
4955 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4956 * is very undesirable as it would double the memory requirements for
4957 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4958 * no sane VMM mucks with the core vCPU model on the fly.
4960 if (vcpu
->arch
.last_vmentry_cpu
!= -1) {
4961 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4962 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4966 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4968 kvm_mmu_unload(vcpu
);
4971 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4973 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4977 r
= mmu_topup_memory_caches(vcpu
, !vcpu
->arch
.mmu
->direct_map
);
4980 r
= mmu_alloc_special_roots(vcpu
);
4983 if (vcpu
->arch
.mmu
->direct_map
)
4984 r
= mmu_alloc_direct_roots(vcpu
);
4986 r
= mmu_alloc_shadow_roots(vcpu
);
4990 kvm_mmu_sync_roots(vcpu
);
4992 kvm_mmu_load_pgd(vcpu
);
4993 static_call(kvm_x86_tlb_flush_current
)(vcpu
);
4998 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
5000 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.root_mmu
, KVM_MMU_ROOTS_ALL
);
5001 WARN_ON(VALID_PAGE(vcpu
->arch
.root_mmu
.root_hpa
));
5002 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
5003 WARN_ON(VALID_PAGE(vcpu
->arch
.guest_mmu
.root_hpa
));
5006 static bool need_remote_flush(u64 old
, u64
new)
5008 if (!is_shadow_present_pte(old
))
5010 if (!is_shadow_present_pte(new))
5012 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
5014 old
^= shadow_nx_mask
;
5015 new ^= shadow_nx_mask
;
5016 return (old
& ~new & PT64_PERM_MASK
) != 0;
5019 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
5026 * Assume that the pte write on a page table of the same type
5027 * as the current vcpu paging mode since we update the sptes only
5028 * when they have the same mode.
5030 if (is_pae(vcpu
) && *bytes
== 4) {
5031 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5036 if (*bytes
== 4 || *bytes
== 8) {
5037 r
= kvm_vcpu_read_guest_atomic(vcpu
, *gpa
, &gentry
, *bytes
);
5046 * If we're seeing too many writes to a page, it may no longer be a page table,
5047 * or we may be forking, in which case it is better to unmap the page.
5049 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
5052 * Skip write-flooding detected for the sp whose level is 1, because
5053 * it can become unsync, then the guest page is not write-protected.
5055 if (sp
->role
.level
== PG_LEVEL_4K
)
5058 atomic_inc(&sp
->write_flooding_count
);
5059 return atomic_read(&sp
->write_flooding_count
) >= 3;
5063 * Misaligned accesses are too much trouble to fix up; also, they usually
5064 * indicate a page is not used as a page table.
5066 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
5069 unsigned offset
, pte_size
, misaligned
;
5071 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5072 gpa
, bytes
, sp
->role
.word
);
5074 offset
= offset_in_page(gpa
);
5075 pte_size
= sp
->role
.gpte_is_8_bytes
? 8 : 4;
5078 * Sometimes, the OS only writes the last one bytes to update status
5079 * bits, for example, in linux, andb instruction is used in clear_bit().
5081 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
5084 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
5085 misaligned
|= bytes
< 4;
5090 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
5092 unsigned page_offset
, quadrant
;
5096 page_offset
= offset_in_page(gpa
);
5097 level
= sp
->role
.level
;
5099 if (!sp
->role
.gpte_is_8_bytes
) {
5100 page_offset
<<= 1; /* 32->64 */
5102 * A 32-bit pde maps 4MB while the shadow pdes map
5103 * only 2MB. So we need to double the offset again
5104 * and zap two pdes instead of one.
5106 if (level
== PT32_ROOT_LEVEL
) {
5107 page_offset
&= ~7; /* kill rounding error */
5111 quadrant
= page_offset
>> PAGE_SHIFT
;
5112 page_offset
&= ~PAGE_MASK
;
5113 if (quadrant
!= sp
->role
.quadrant
)
5117 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
5121 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
5122 const u8
*new, int bytes
,
5123 struct kvm_page_track_notifier_node
*node
)
5125 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
5126 struct kvm_mmu_page
*sp
;
5127 LIST_HEAD(invalid_list
);
5128 u64 entry
, gentry
, *spte
;
5130 bool remote_flush
, local_flush
;
5133 * If we don't have indirect shadow pages, it means no page is
5134 * write-protected, so we can exit simply.
5136 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
5139 remote_flush
= local_flush
= false;
5141 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
5144 * No need to care whether allocation memory is successful
5145 * or not since pte prefetch is skipped if it does not have
5146 * enough objects in the cache.
5148 mmu_topup_memory_caches(vcpu
, true);
5150 write_lock(&vcpu
->kvm
->mmu_lock
);
5152 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, &bytes
);
5154 ++vcpu
->kvm
->stat
.mmu_pte_write
;
5155 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
5157 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
5158 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
5159 detect_write_flooding(sp
)) {
5160 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
5161 ++vcpu
->kvm
->stat
.mmu_flooded
;
5165 spte
= get_written_sptes(sp
, gpa
, &npte
);
5172 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
, NULL
);
5173 if (gentry
&& sp
->role
.level
!= PG_LEVEL_4K
)
5174 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
5175 if (need_remote_flush(entry
, *spte
))
5176 remote_flush
= true;
5180 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
5181 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
5182 write_unlock(&vcpu
->kvm
->mmu_lock
);
5185 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
, u64 error_code
,
5186 void *insn
, int insn_len
)
5188 int r
, emulation_type
= EMULTYPE_PF
;
5189 bool direct
= vcpu
->arch
.mmu
->direct_map
;
5191 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
5192 return RET_PF_RETRY
;
5195 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
5196 r
= handle_mmio_page_fault(vcpu
, cr2_or_gpa
, direct
);
5197 if (r
== RET_PF_EMULATE
)
5201 if (r
== RET_PF_INVALID
) {
5202 r
= kvm_mmu_do_page_fault(vcpu
, cr2_or_gpa
,
5203 lower_32_bits(error_code
), false);
5204 if (KVM_BUG_ON(r
== RET_PF_INVALID
, vcpu
->kvm
))
5210 if (r
!= RET_PF_EMULATE
)
5214 * Before emulating the instruction, check if the error code
5215 * was due to a RO violation while translating the guest page.
5216 * This can occur when using nested virtualization with nested
5217 * paging in both guests. If true, we simply unprotect the page
5218 * and resume the guest.
5220 if (vcpu
->arch
.mmu
->direct_map
&&
5221 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
5222 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2_or_gpa
));
5227 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5228 * optimistically try to just unprotect the page and let the processor
5229 * re-execute the instruction that caused the page fault. Do not allow
5230 * retrying MMIO emulation, as it's not only pointless but could also
5231 * cause us to enter an infinite loop because the processor will keep
5232 * faulting on the non-existent MMIO address. Retrying an instruction
5233 * from a nested guest is also pointless and dangerous as we are only
5234 * explicitly shadowing L1's page tables, i.e. unprotecting something
5235 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5237 if (!mmio_info_in_cache(vcpu
, cr2_or_gpa
, direct
) && !is_guest_mode(vcpu
))
5238 emulation_type
|= EMULTYPE_ALLOW_RETRY_PF
;
5240 return x86_emulate_instruction(vcpu
, cr2_or_gpa
, emulation_type
, insn
,
5243 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
5245 void kvm_mmu_invalidate_gva(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
5246 gva_t gva
, hpa_t root_hpa
)
5250 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5251 if (mmu
!= &vcpu
->arch
.guest_mmu
) {
5252 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5253 if (is_noncanonical_address(gva
, vcpu
))
5256 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5262 if (root_hpa
== INVALID_PAGE
) {
5263 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5266 * INVLPG is required to invalidate any global mappings for the VA,
5267 * irrespective of PCID. Since it would take us roughly similar amount
5268 * of work to determine whether any of the prev_root mappings of the VA
5269 * is marked global, or to just sync it blindly, so we might as well
5270 * just always sync it.
5272 * Mappings not reachable via the current cr3 or the prev_roots will be
5273 * synced when switching to that cr3, so nothing needs to be done here
5276 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5277 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
5278 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5280 mmu
->invlpg(vcpu
, gva
, root_hpa
);
5284 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
5286 kvm_mmu_invalidate_gva(vcpu
, vcpu
->arch
.mmu
, gva
, INVALID_PAGE
);
5287 ++vcpu
->stat
.invlpg
;
5289 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
5292 void kvm_mmu_invpcid_gva(struct kvm_vcpu
*vcpu
, gva_t gva
, unsigned long pcid
)
5294 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5295 bool tlb_flush
= false;
5298 if (pcid
== kvm_get_active_pcid(vcpu
)) {
5299 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5303 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
5304 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
) &&
5305 pcid
== kvm_get_pcid(vcpu
, mmu
->prev_roots
[i
].pgd
)) {
5306 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5312 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5314 ++vcpu
->stat
.invlpg
;
5317 * Mappings not reachable via the current cr3 or the prev_roots will be
5318 * synced when switching to that cr3, so nothing needs to be done here
5323 void kvm_configure_mmu(bool enable_tdp
, int tdp_max_root_level
,
5324 int tdp_huge_page_level
)
5326 tdp_enabled
= enable_tdp
;
5327 max_tdp_level
= tdp_max_root_level
;
5330 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5331 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5332 * the kernel is not. But, KVM never creates a page size greater than
5333 * what is used by the kernel for any given HVA, i.e. the kernel's
5334 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5337 max_huge_page_level
= tdp_huge_page_level
;
5338 else if (boot_cpu_has(X86_FEATURE_GBPAGES
))
5339 max_huge_page_level
= PG_LEVEL_1G
;
5341 max_huge_page_level
= PG_LEVEL_2M
;
5343 EXPORT_SYMBOL_GPL(kvm_configure_mmu
);
5345 /* The return value indicates if tlb flush on all vcpus is needed. */
5346 typedef bool (*slot_level_handler
) (struct kvm
*kvm
,
5347 struct kvm_rmap_head
*rmap_head
,
5348 const struct kvm_memory_slot
*slot
);
5350 /* The caller should hold mmu-lock before calling this function. */
5351 static __always_inline
bool
5352 slot_handle_level_range(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5353 slot_level_handler fn
, int start_level
, int end_level
,
5354 gfn_t start_gfn
, gfn_t end_gfn
, bool flush_on_yield
,
5357 struct slot_rmap_walk_iterator iterator
;
5359 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5360 end_gfn
, &iterator
) {
5362 flush
|= fn(kvm
, iterator
.rmap
, memslot
);
5364 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
5365 if (flush
&& flush_on_yield
) {
5366 kvm_flush_remote_tlbs_with_address(kvm
,
5368 iterator
.gfn
- start_gfn
+ 1);
5371 cond_resched_rwlock_write(&kvm
->mmu_lock
);
5378 static __always_inline
bool
5379 slot_handle_level(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5380 slot_level_handler fn
, int start_level
, int end_level
,
5381 bool flush_on_yield
)
5383 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5384 end_level
, memslot
->base_gfn
,
5385 memslot
->base_gfn
+ memslot
->npages
- 1,
5386 flush_on_yield
, false);
5389 static __always_inline
bool
5390 slot_handle_leaf(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5391 slot_level_handler fn
, bool flush_on_yield
)
5393 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
,
5394 PG_LEVEL_4K
, flush_on_yield
);
5397 static void free_mmu_pages(struct kvm_mmu
*mmu
)
5399 if (!tdp_enabled
&& mmu
->pae_root
)
5400 set_memory_encrypted((unsigned long)mmu
->pae_root
, 1);
5401 free_page((unsigned long)mmu
->pae_root
);
5402 free_page((unsigned long)mmu
->pml4_root
);
5405 static int __kvm_mmu_create(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
5410 mmu
->root_hpa
= INVALID_PAGE
;
5412 mmu
->translate_gpa
= translate_gpa
;
5413 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5414 mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5417 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5418 * while the PDP table is a per-vCPU construct that's allocated at MMU
5419 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5420 * x86_64. Therefore we need to allocate the PDP table in the first
5421 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5422 * generally doesn't use PAE paging and can skip allocating the PDP
5423 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5424 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5425 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5427 if (tdp_enabled
&& kvm_mmu_get_tdp_level(vcpu
) > PT32E_ROOT_LEVEL
)
5430 page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_DMA32
);
5434 mmu
->pae_root
= page_address(page
);
5437 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5438 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5439 * that KVM's writes and the CPU's reads get along. Note, this is
5440 * only necessary when using shadow paging, as 64-bit NPT can get at
5441 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5442 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5445 set_memory_decrypted((unsigned long)mmu
->pae_root
, 1);
5447 WARN_ON_ONCE(shadow_me_mask
);
5449 for (i
= 0; i
< 4; ++i
)
5450 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
5455 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5459 vcpu
->arch
.mmu_pte_list_desc_cache
.kmem_cache
= pte_list_desc_cache
;
5460 vcpu
->arch
.mmu_pte_list_desc_cache
.gfp_zero
= __GFP_ZERO
;
5462 vcpu
->arch
.mmu_page_header_cache
.kmem_cache
= mmu_page_header_cache
;
5463 vcpu
->arch
.mmu_page_header_cache
.gfp_zero
= __GFP_ZERO
;
5465 vcpu
->arch
.mmu_shadow_page_cache
.gfp_zero
= __GFP_ZERO
;
5467 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
5468 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
5470 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5472 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.guest_mmu
);
5476 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.root_mmu
);
5478 goto fail_allocate_root
;
5482 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5486 #define BATCH_ZAP_PAGES 10
5487 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5489 struct kvm_mmu_page
*sp
, *node
;
5490 int nr_zapped
, batch
= 0;
5493 list_for_each_entry_safe_reverse(sp
, node
,
5494 &kvm
->arch
.active_mmu_pages
, link
) {
5496 * No obsolete valid page exists before a newly created page
5497 * since active_mmu_pages is a FIFO list.
5499 if (!is_obsolete_sp(kvm
, sp
))
5503 * Invalid pages should never land back on the list of active
5504 * pages. Skip the bogus page, otherwise we'll get stuck in an
5505 * infinite loop if the page gets put back on the list (again).
5507 if (WARN_ON(sp
->role
.invalid
))
5511 * No need to flush the TLB since we're only zapping shadow
5512 * pages with an obsolete generation number and all vCPUS have
5513 * loaded a new root, i.e. the shadow pages being zapped cannot
5514 * be in active use by the guest.
5516 if (batch
>= BATCH_ZAP_PAGES
&&
5517 cond_resched_rwlock_write(&kvm
->mmu_lock
)) {
5522 if (__kvm_mmu_prepare_zap_page(kvm
, sp
,
5523 &kvm
->arch
.zapped_obsolete_pages
, &nr_zapped
)) {
5530 * Trigger a remote TLB flush before freeing the page tables to ensure
5531 * KVM is not in the middle of a lockless shadow page table walk, which
5532 * may reference the pages.
5534 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5538 * Fast invalidate all shadow pages and use lock-break technique
5539 * to zap obsolete pages.
5541 * It's required when memslot is being deleted or VM is being
5542 * destroyed, in these cases, we should ensure that KVM MMU does
5543 * not use any resource of the being-deleted slot or all slots
5544 * after calling the function.
5546 static void kvm_mmu_zap_all_fast(struct kvm
*kvm
)
5548 lockdep_assert_held(&kvm
->slots_lock
);
5550 write_lock(&kvm
->mmu_lock
);
5551 trace_kvm_mmu_zap_all_fast(kvm
);
5554 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5555 * held for the entire duration of zapping obsolete pages, it's
5556 * impossible for there to be multiple invalid generations associated
5557 * with *valid* shadow pages at any given time, i.e. there is exactly
5558 * one valid generation and (at most) one invalid generation.
5560 kvm
->arch
.mmu_valid_gen
= kvm
->arch
.mmu_valid_gen
? 0 : 1;
5562 /* In order to ensure all threads see this change when
5563 * handling the MMU reload signal, this must happen in the
5564 * same critical section as kvm_reload_remote_mmus, and
5565 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5566 * could drop the MMU lock and yield.
5568 if (is_tdp_mmu_enabled(kvm
))
5569 kvm_tdp_mmu_invalidate_all_roots(kvm
);
5572 * Notify all vcpus to reload its shadow page table and flush TLB.
5573 * Then all vcpus will switch to new shadow page table with the new
5576 * Note: we need to do this under the protection of mmu_lock,
5577 * otherwise, vcpu would purge shadow page but miss tlb flush.
5579 kvm_reload_remote_mmus(kvm
);
5581 kvm_zap_obsolete_pages(kvm
);
5583 write_unlock(&kvm
->mmu_lock
);
5585 if (is_tdp_mmu_enabled(kvm
)) {
5586 read_lock(&kvm
->mmu_lock
);
5587 kvm_tdp_mmu_zap_invalidated_roots(kvm
);
5588 read_unlock(&kvm
->mmu_lock
);
5592 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5594 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5597 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5598 struct kvm_memory_slot
*slot
,
5599 struct kvm_page_track_notifier_node
*node
)
5601 kvm_mmu_zap_all_fast(kvm
);
5604 void kvm_mmu_init_vm(struct kvm
*kvm
)
5606 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5608 if (!kvm_mmu_init_tdp_mmu(kvm
))
5610 * No smp_load/store wrappers needed here as we are in
5611 * VM init and there cannot be any memslots / other threads
5612 * accessing this struct kvm yet.
5614 kvm
->arch
.memslots_have_rmaps
= true;
5616 node
->track_write
= kvm_mmu_pte_write
;
5617 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5618 kvm_page_track_register_notifier(kvm
, node
);
5621 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5623 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5625 kvm_page_track_unregister_notifier(kvm
, node
);
5627 kvm_mmu_uninit_tdp_mmu(kvm
);
5630 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5632 struct kvm_memslots
*slots
;
5633 struct kvm_memory_slot
*memslot
;
5637 if (kvm_memslots_have_rmaps(kvm
)) {
5638 write_lock(&kvm
->mmu_lock
);
5639 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5640 slots
= __kvm_memslots(kvm
, i
);
5641 kvm_for_each_memslot(memslot
, slots
) {
5644 start
= max(gfn_start
, memslot
->base_gfn
);
5645 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5649 flush
= slot_handle_level_range(kvm
,
5650 (const struct kvm_memory_slot
*) memslot
,
5651 kvm_zap_rmapp
, PG_LEVEL_4K
,
5652 KVM_MAX_HUGEPAGE_LEVEL
, start
,
5653 end
- 1, true, flush
);
5657 kvm_flush_remote_tlbs_with_address(kvm
, gfn_start
, gfn_end
);
5658 write_unlock(&kvm
->mmu_lock
);
5661 if (is_tdp_mmu_enabled(kvm
)) {
5664 read_lock(&kvm
->mmu_lock
);
5665 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++)
5666 flush
= kvm_tdp_mmu_zap_gfn_range(kvm
, i
, gfn_start
,
5667 gfn_end
, flush
, true);
5669 kvm_flush_remote_tlbs_with_address(kvm
, gfn_start
,
5672 read_unlock(&kvm
->mmu_lock
);
5676 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5677 struct kvm_rmap_head
*rmap_head
,
5678 const struct kvm_memory_slot
*slot
)
5680 return __rmap_write_protect(kvm
, rmap_head
, false);
5683 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5684 const struct kvm_memory_slot
*memslot
,
5689 if (kvm_memslots_have_rmaps(kvm
)) {
5690 write_lock(&kvm
->mmu_lock
);
5691 flush
= slot_handle_level(kvm
, memslot
, slot_rmap_write_protect
,
5692 start_level
, KVM_MAX_HUGEPAGE_LEVEL
,
5694 write_unlock(&kvm
->mmu_lock
);
5697 if (is_tdp_mmu_enabled(kvm
)) {
5698 read_lock(&kvm
->mmu_lock
);
5699 flush
|= kvm_tdp_mmu_wrprot_slot(kvm
, memslot
, start_level
);
5700 read_unlock(&kvm
->mmu_lock
);
5704 * We can flush all the TLBs out of the mmu lock without TLB
5705 * corruption since we just change the spte from writable to
5706 * readonly so that we only need to care the case of changing
5707 * spte from present to present (changing the spte from present
5708 * to nonpresent will flush all the TLBs immediately), in other
5709 * words, the only case we care is mmu_spte_update() where we
5710 * have checked Host-writable | MMU-writable instead of
5711 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5715 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5718 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5719 struct kvm_rmap_head
*rmap_head
,
5720 const struct kvm_memory_slot
*slot
)
5723 struct rmap_iterator iter
;
5724 int need_tlb_flush
= 0;
5726 struct kvm_mmu_page
*sp
;
5729 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5730 sp
= sptep_to_sp(sptep
);
5731 pfn
= spte_to_pfn(*sptep
);
5734 * We cannot do huge page mapping for indirect shadow pages,
5735 * which are found on the last rmap (level = 1) when not using
5736 * tdp; such shadow pages are synced with the page table in
5737 * the guest, and the guest page table is using 4K page size
5738 * mapping if the indirect sp has level = 1.
5740 if (sp
->role
.direct
&& !kvm_is_reserved_pfn(pfn
) &&
5741 sp
->role
.level
< kvm_mmu_max_mapping_level(kvm
, slot
, sp
->gfn
,
5742 pfn
, PG_LEVEL_NUM
)) {
5743 pte_list_remove(rmap_head
, sptep
);
5745 if (kvm_available_flush_tlb_with_range())
5746 kvm_flush_remote_tlbs_with_address(kvm
, sp
->gfn
,
5747 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
5755 return need_tlb_flush
;
5758 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5759 const struct kvm_memory_slot
*slot
)
5763 if (kvm_memslots_have_rmaps(kvm
)) {
5764 write_lock(&kvm
->mmu_lock
);
5765 flush
= slot_handle_leaf(kvm
, slot
, kvm_mmu_zap_collapsible_spte
, true);
5767 kvm_arch_flush_remote_tlbs_memslot(kvm
, slot
);
5768 write_unlock(&kvm
->mmu_lock
);
5771 if (is_tdp_mmu_enabled(kvm
)) {
5772 read_lock(&kvm
->mmu_lock
);
5773 flush
= kvm_tdp_mmu_zap_collapsible_sptes(kvm
, slot
, flush
);
5775 kvm_arch_flush_remote_tlbs_memslot(kvm
, slot
);
5776 read_unlock(&kvm
->mmu_lock
);
5780 void kvm_arch_flush_remote_tlbs_memslot(struct kvm
*kvm
,
5781 const struct kvm_memory_slot
*memslot
)
5784 * All current use cases for flushing the TLBs for a specific memslot
5785 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5786 * The interaction between the various operations on memslot must be
5787 * serialized by slots_locks to ensure the TLB flush from one operation
5788 * is observed by any other operation on the same memslot.
5790 lockdep_assert_held(&kvm
->slots_lock
);
5791 kvm_flush_remote_tlbs_with_address(kvm
, memslot
->base_gfn
,
5795 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5796 const struct kvm_memory_slot
*memslot
)
5800 if (kvm_memslots_have_rmaps(kvm
)) {
5801 write_lock(&kvm
->mmu_lock
);
5802 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
,
5804 write_unlock(&kvm
->mmu_lock
);
5807 if (is_tdp_mmu_enabled(kvm
)) {
5808 read_lock(&kvm
->mmu_lock
);
5809 flush
|= kvm_tdp_mmu_clear_dirty_slot(kvm
, memslot
);
5810 read_unlock(&kvm
->mmu_lock
);
5814 * It's also safe to flush TLBs out of mmu lock here as currently this
5815 * function is only used for dirty logging, in which case flushing TLB
5816 * out of mmu lock also guarantees no dirty pages will be lost in
5820 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5823 void kvm_mmu_zap_all(struct kvm
*kvm
)
5825 struct kvm_mmu_page
*sp
, *node
;
5826 LIST_HEAD(invalid_list
);
5829 write_lock(&kvm
->mmu_lock
);
5831 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
5832 if (WARN_ON(sp
->role
.invalid
))
5834 if (__kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
, &ign
))
5836 if (cond_resched_rwlock_write(&kvm
->mmu_lock
))
5840 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5842 if (is_tdp_mmu_enabled(kvm
))
5843 kvm_tdp_mmu_zap_all(kvm
);
5845 write_unlock(&kvm
->mmu_lock
);
5848 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, u64 gen
)
5850 WARN_ON(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
);
5852 gen
&= MMIO_SPTE_GEN_MASK
;
5855 * Generation numbers are incremented in multiples of the number of
5856 * address spaces in order to provide unique generations across all
5857 * address spaces. Strip what is effectively the address space
5858 * modifier prior to checking for a wrap of the MMIO generation so
5859 * that a wrap in any address space is detected.
5861 gen
&= ~((u64
)KVM_ADDRESS_SPACE_NUM
- 1);
5864 * The very rare case: if the MMIO generation number has wrapped,
5865 * zap all shadow pages.
5867 if (unlikely(gen
== 0)) {
5868 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5869 kvm_mmu_zap_all_fast(kvm
);
5873 static unsigned long
5874 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5877 int nr_to_scan
= sc
->nr_to_scan
;
5878 unsigned long freed
= 0;
5880 mutex_lock(&kvm_lock
);
5882 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5884 LIST_HEAD(invalid_list
);
5887 * Never scan more than sc->nr_to_scan VM instances.
5888 * Will not hit this condition practically since we do not try
5889 * to shrink more than one VM and it is very unlikely to see
5890 * !n_used_mmu_pages so many times.
5895 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5896 * here. We may skip a VM instance errorneosly, but we do not
5897 * want to shrink a VM that only started to populate its MMU
5900 if (!kvm
->arch
.n_used_mmu_pages
&&
5901 !kvm_has_zapped_obsolete_pages(kvm
))
5904 idx
= srcu_read_lock(&kvm
->srcu
);
5905 write_lock(&kvm
->mmu_lock
);
5907 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5908 kvm_mmu_commit_zap_page(kvm
,
5909 &kvm
->arch
.zapped_obsolete_pages
);
5913 freed
= kvm_mmu_zap_oldest_mmu_pages(kvm
, sc
->nr_to_scan
);
5916 write_unlock(&kvm
->mmu_lock
);
5917 srcu_read_unlock(&kvm
->srcu
, idx
);
5920 * unfair on small ones
5921 * per-vm shrinkers cry out
5922 * sadness comes quickly
5924 list_move_tail(&kvm
->vm_list
, &vm_list
);
5928 mutex_unlock(&kvm_lock
);
5932 static unsigned long
5933 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5935 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5938 static struct shrinker mmu_shrinker
= {
5939 .count_objects
= mmu_shrink_count
,
5940 .scan_objects
= mmu_shrink_scan
,
5941 .seeks
= DEFAULT_SEEKS
* 10,
5944 static void mmu_destroy_caches(void)
5946 kmem_cache_destroy(pte_list_desc_cache
);
5947 kmem_cache_destroy(mmu_page_header_cache
);
5950 static bool get_nx_auto_mode(void)
5952 /* Return true when CPU has the bug, and mitigations are ON */
5953 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT
) && !cpu_mitigations_off();
5956 static void __set_nx_huge_pages(bool val
)
5958 nx_huge_pages
= itlb_multihit_kvm_mitigation
= val
;
5961 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
)
5963 bool old_val
= nx_huge_pages
;
5966 /* In "auto" mode deploy workaround only if CPU has the bug. */
5967 if (sysfs_streq(val
, "off"))
5969 else if (sysfs_streq(val
, "force"))
5971 else if (sysfs_streq(val
, "auto"))
5972 new_val
= get_nx_auto_mode();
5973 else if (strtobool(val
, &new_val
) < 0)
5976 __set_nx_huge_pages(new_val
);
5978 if (new_val
!= old_val
) {
5981 mutex_lock(&kvm_lock
);
5983 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5984 mutex_lock(&kvm
->slots_lock
);
5985 kvm_mmu_zap_all_fast(kvm
);
5986 mutex_unlock(&kvm
->slots_lock
);
5988 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
5990 mutex_unlock(&kvm_lock
);
5996 int kvm_mmu_module_init(void)
6000 if (nx_huge_pages
== -1)
6001 __set_nx_huge_pages(get_nx_auto_mode());
6004 * MMU roles use union aliasing which is, generally speaking, an
6005 * undefined behavior. However, we supposedly know how compilers behave
6006 * and the current status quo is unlikely to change. Guardians below are
6007 * supposed to let us know if the assumption becomes false.
6009 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role
) != sizeof(u32
));
6010 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role
) != sizeof(u32
));
6011 BUILD_BUG_ON(sizeof(union kvm_mmu_role
) != sizeof(u64
));
6013 kvm_mmu_reset_all_pte_masks();
6015 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
6016 sizeof(struct pte_list_desc
),
6017 0, SLAB_ACCOUNT
, NULL
);
6018 if (!pte_list_desc_cache
)
6021 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
6022 sizeof(struct kvm_mmu_page
),
6023 0, SLAB_ACCOUNT
, NULL
);
6024 if (!mmu_page_header_cache
)
6027 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
6030 ret
= register_shrinker(&mmu_shrinker
);
6037 mmu_destroy_caches();
6042 * Calculate mmu pages needed for kvm.
6044 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm
*kvm
)
6046 unsigned long nr_mmu_pages
;
6047 unsigned long nr_pages
= 0;
6048 struct kvm_memslots
*slots
;
6049 struct kvm_memory_slot
*memslot
;
6052 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
6053 slots
= __kvm_memslots(kvm
, i
);
6055 kvm_for_each_memslot(memslot
, slots
)
6056 nr_pages
+= memslot
->npages
;
6059 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
6060 nr_mmu_pages
= max(nr_mmu_pages
, KVM_MIN_ALLOC_MMU_PAGES
);
6062 return nr_mmu_pages
;
6065 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
6067 kvm_mmu_unload(vcpu
);
6068 free_mmu_pages(&vcpu
->arch
.root_mmu
);
6069 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
6070 mmu_free_memory_caches(vcpu
);
6073 void kvm_mmu_module_exit(void)
6075 mmu_destroy_caches();
6076 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
6077 unregister_shrinker(&mmu_shrinker
);
6078 mmu_audit_disable();
6081 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
)
6083 unsigned int old_val
;
6086 old_val
= nx_huge_pages_recovery_ratio
;
6087 err
= param_set_uint(val
, kp
);
6091 if (READ_ONCE(nx_huge_pages
) &&
6092 !old_val
&& nx_huge_pages_recovery_ratio
) {
6095 mutex_lock(&kvm_lock
);
6097 list_for_each_entry(kvm
, &vm_list
, vm_list
)
6098 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
6100 mutex_unlock(&kvm_lock
);
6106 static void kvm_recover_nx_lpages(struct kvm
*kvm
)
6108 unsigned long nx_lpage_splits
= kvm
->stat
.nx_lpage_splits
;
6110 struct kvm_mmu_page
*sp
;
6112 LIST_HEAD(invalid_list
);
6116 rcu_idx
= srcu_read_lock(&kvm
->srcu
);
6117 write_lock(&kvm
->mmu_lock
);
6119 ratio
= READ_ONCE(nx_huge_pages_recovery_ratio
);
6120 to_zap
= ratio
? DIV_ROUND_UP(nx_lpage_splits
, ratio
) : 0;
6121 for ( ; to_zap
; --to_zap
) {
6122 if (list_empty(&kvm
->arch
.lpage_disallowed_mmu_pages
))
6126 * We use a separate list instead of just using active_mmu_pages
6127 * because the number of lpage_disallowed pages is expected to
6128 * be relatively small compared to the total.
6130 sp
= list_first_entry(&kvm
->arch
.lpage_disallowed_mmu_pages
,
6131 struct kvm_mmu_page
,
6132 lpage_disallowed_link
);
6133 WARN_ON_ONCE(!sp
->lpage_disallowed
);
6134 if (is_tdp_mmu_page(sp
)) {
6135 flush
|= kvm_tdp_mmu_zap_sp(kvm
, sp
);
6137 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
6138 WARN_ON_ONCE(sp
->lpage_disallowed
);
6141 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
6142 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
6143 cond_resched_rwlock_write(&kvm
->mmu_lock
);
6147 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
6149 write_unlock(&kvm
->mmu_lock
);
6150 srcu_read_unlock(&kvm
->srcu
, rcu_idx
);
6153 static long get_nx_lpage_recovery_timeout(u64 start_time
)
6155 return READ_ONCE(nx_huge_pages
) && READ_ONCE(nx_huge_pages_recovery_ratio
)
6156 ? start_time
+ 60 * HZ
- get_jiffies_64()
6157 : MAX_SCHEDULE_TIMEOUT
;
6160 static int kvm_nx_lpage_recovery_worker(struct kvm
*kvm
, uintptr_t data
)
6163 long remaining_time
;
6166 start_time
= get_jiffies_64();
6167 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6169 set_current_state(TASK_INTERRUPTIBLE
);
6170 while (!kthread_should_stop() && remaining_time
> 0) {
6171 schedule_timeout(remaining_time
);
6172 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6173 set_current_state(TASK_INTERRUPTIBLE
);
6176 set_current_state(TASK_RUNNING
);
6178 if (kthread_should_stop())
6181 kvm_recover_nx_lpages(kvm
);
6185 int kvm_mmu_post_init_vm(struct kvm
*kvm
)
6189 err
= kvm_vm_create_worker_thread(kvm
, kvm_nx_lpage_recovery_worker
, 0,
6190 "kvm-nx-lpage-recovery",
6191 &kvm
->arch
.nx_lpage_recovery_thread
);
6193 kthread_unpark(kvm
->arch
.nx_lpage_recovery_thread
);
6198 void kvm_mmu_pre_destroy_vm(struct kvm
*kvm
)
6200 if (kvm
->arch
.nx_lpage_recovery_thread
)
6201 kthread_stop(kvm
->arch
.nx_lpage_recovery_thread
);