1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
58 extern bool itlb_multihit_kvm_mitigation
;
60 int __read_mostly nx_huge_pages
= -1;
61 #ifdef CONFIG_PREEMPT_RT
62 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
63 static uint __read_mostly nx_huge_pages_recovery_ratio
= 0;
65 static uint __read_mostly nx_huge_pages_recovery_ratio
= 60;
68 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
);
69 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
);
71 static const struct kernel_param_ops nx_huge_pages_ops
= {
72 .set
= set_nx_huge_pages
,
73 .get
= param_get_bool
,
76 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops
= {
77 .set
= set_nx_huge_pages_recovery_ratio
,
78 .get
= param_get_uint
,
81 module_param_cb(nx_huge_pages
, &nx_huge_pages_ops
, &nx_huge_pages
, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages
, "bool");
83 module_param_cb(nx_huge_pages_recovery_ratio
, &nx_huge_pages_recovery_ratio_ops
,
84 &nx_huge_pages_recovery_ratio
, 0644);
85 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio
, "uint");
87 static bool __read_mostly force_flush_and_sync_on_reuse
;
88 module_param_named(flush_on_reuse
, force_flush_and_sync_on_reuse
, bool, 0644);
91 * When setting this variable to true it enables Two-Dimensional-Paging
92 * where the hardware walks 2 page tables:
93 * 1. the guest-virtual to guest-physical
94 * 2. while doing 1. it walks guest-physical to host-physical
95 * If the hardware supports that we don't need to do shadow paging.
97 bool tdp_enabled
= false;
99 static int max_huge_page_level __read_mostly
;
100 static int max_tdp_level __read_mostly
;
103 AUDIT_PRE_PAGE_FAULT
,
104 AUDIT_POST_PAGE_FAULT
,
106 AUDIT_POST_PTE_WRITE
,
113 module_param(dbg
, bool, 0644);
116 #define PTE_PREFETCH_NUM 8
118 #define PT32_LEVEL_BITS 10
120 #define PT32_LEVEL_SHIFT(level) \
121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
123 #define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
131 #define PT32_BASE_ADDR_MASK PAGE_MASK
132 #define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
134 #define PT32_LVL_ADDR_MASK(level) \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT32_LEVEL_BITS))) - 1))
138 #include <trace/events/kvm.h>
140 /* make pte_list_desc fit well in cache lines */
141 #define PTE_LIST_EXT 14
144 * Slight optimization of cacheline layout, by putting `more' and `spte_count'
145 * at the start; then accessing it will only use one single cacheline for
146 * either full (entries==PTE_LIST_EXT) case or entries<=6.
148 struct pte_list_desc
{
149 struct pte_list_desc
*more
;
151 * Stores number of entries stored in the pte_list_desc. No need to be
152 * u64 but just for easier alignment. When PTE_LIST_EXT, means full.
155 u64
*sptes
[PTE_LIST_EXT
];
158 struct kvm_shadow_walk_iterator
{
166 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
167 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
169 shadow_walk_okay(&(_walker)); \
170 shadow_walk_next(&(_walker)))
172 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
177 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
178 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
179 shadow_walk_okay(&(_walker)) && \
180 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
181 __shadow_walk_next(&(_walker), spte))
183 static struct kmem_cache
*pte_list_desc_cache
;
184 struct kmem_cache
*mmu_page_header_cache
;
185 static struct percpu_counter kvm_total_used_mmu_pages
;
187 static void mmu_spte_set(u64
*sptep
, u64 spte
);
188 static union kvm_mmu_page_role
189 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
);
191 struct kvm_mmu_role_regs
{
192 const unsigned long cr0
;
193 const unsigned long cr4
;
197 #define CREATE_TRACE_POINTS
198 #include "mmutrace.h"
201 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
202 * reading from the role_regs. Once the mmu_role is constructed, it becomes
203 * the single source of truth for the MMU's state.
205 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
206 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
208 return !!(regs->reg & flag); \
210 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0
, pg
, X86_CR0_PG
);
211 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0
, wp
, X86_CR0_WP
);
212 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pse
, X86_CR4_PSE
);
213 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pae
, X86_CR4_PAE
);
214 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, smep
, X86_CR4_SMEP
);
215 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, smap
, X86_CR4_SMAP
);
216 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, pke
, X86_CR4_PKE
);
217 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4
, la57
, X86_CR4_LA57
);
218 BUILD_MMU_ROLE_REGS_ACCESSOR(efer
, nx
, EFER_NX
);
219 BUILD_MMU_ROLE_REGS_ACCESSOR(efer
, lma
, EFER_LMA
);
222 * The MMU itself (with a valid role) is the single source of truth for the
223 * MMU. Do not use the regs used to build the MMU/role, nor the vCPU. The
224 * regs don't account for dependencies, e.g. clearing CR4 bits if CR0.PG=1,
225 * and the vCPU may be incorrect/irrelevant.
227 #define BUILD_MMU_ROLE_ACCESSOR(base_or_ext, reg, name) \
228 static inline bool is_##reg##_##name(struct kvm_mmu *mmu) \
230 return !!(mmu->mmu_role. base_or_ext . reg##_##name); \
232 BUILD_MMU_ROLE_ACCESSOR(ext
, cr0
, pg
);
233 BUILD_MMU_ROLE_ACCESSOR(base
, cr0
, wp
);
234 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pse
);
235 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pae
);
236 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, smep
);
237 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, smap
);
238 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, pke
);
239 BUILD_MMU_ROLE_ACCESSOR(ext
, cr4
, la57
);
240 BUILD_MMU_ROLE_ACCESSOR(base
, efer
, nx
);
242 static struct kvm_mmu_role_regs
vcpu_to_role_regs(struct kvm_vcpu
*vcpu
)
244 struct kvm_mmu_role_regs regs
= {
245 .cr0
= kvm_read_cr0_bits(vcpu
, KVM_MMU_CR0_ROLE_BITS
),
246 .cr4
= kvm_read_cr4_bits(vcpu
, KVM_MMU_CR4_ROLE_BITS
),
247 .efer
= vcpu
->arch
.efer
,
253 static int role_regs_to_root_level(struct kvm_mmu_role_regs
*regs
)
255 if (!____is_cr0_pg(regs
))
257 else if (____is_efer_lma(regs
))
258 return ____is_cr4_la57(regs
) ? PT64_ROOT_5LEVEL
:
260 else if (____is_cr4_pae(regs
))
261 return PT32E_ROOT_LEVEL
;
263 return PT32_ROOT_LEVEL
;
266 static inline bool kvm_available_flush_tlb_with_range(void)
268 return kvm_x86_ops
.tlb_remote_flush_with_range
;
271 static void kvm_flush_remote_tlbs_with_range(struct kvm
*kvm
,
272 struct kvm_tlb_range
*range
)
276 if (range
&& kvm_x86_ops
.tlb_remote_flush_with_range
)
277 ret
= static_call(kvm_x86_tlb_remote_flush_with_range
)(kvm
, range
);
280 kvm_flush_remote_tlbs(kvm
);
283 void kvm_flush_remote_tlbs_with_address(struct kvm
*kvm
,
284 u64 start_gfn
, u64 pages
)
286 struct kvm_tlb_range range
;
288 range
.start_gfn
= start_gfn
;
291 kvm_flush_remote_tlbs_with_range(kvm
, &range
);
294 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
297 u64 spte
= make_mmio_spte(vcpu
, gfn
, access
);
299 trace_mark_mmio_spte(sptep
, gfn
, spte
);
300 mmu_spte_set(sptep
, spte
);
303 static gfn_t
get_mmio_spte_gfn(u64 spte
)
305 u64 gpa
= spte
& shadow_nonpresent_or_rsvd_lower_gfn_mask
;
307 gpa
|= (spte
>> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN
)
308 & shadow_nonpresent_or_rsvd_mask
;
310 return gpa
>> PAGE_SHIFT
;
313 static unsigned get_mmio_spte_access(u64 spte
)
315 return spte
& shadow_mmio_access_mask
;
318 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
320 u64 kvm_gen
, spte_gen
, gen
;
322 gen
= kvm_vcpu_memslots(vcpu
)->generation
;
323 if (unlikely(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
))
326 kvm_gen
= gen
& MMIO_SPTE_GEN_MASK
;
327 spte_gen
= get_mmio_spte_generation(spte
);
329 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
330 return likely(kvm_gen
== spte_gen
);
333 static gpa_t
translate_gpa(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 access
,
334 struct x86_exception
*exception
)
336 /* Check if guest physical address doesn't exceed guest maximum */
337 if (kvm_vcpu_is_illegal_gpa(vcpu
, gpa
)) {
338 exception
->error_code
|= PFERR_RSVD_MASK
;
345 static int is_cpuid_PSE36(void)
350 static gfn_t
pse36_gfn_delta(u32 gpte
)
352 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
354 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
358 static void __set_spte(u64
*sptep
, u64 spte
)
360 WRITE_ONCE(*sptep
, spte
);
363 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
365 WRITE_ONCE(*sptep
, spte
);
368 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
370 return xchg(sptep
, spte
);
373 static u64
__get_spte_lockless(u64
*sptep
)
375 return READ_ONCE(*sptep
);
386 static void count_spte_clear(u64
*sptep
, u64 spte
)
388 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
390 if (is_shadow_present_pte(spte
))
393 /* Ensure the spte is completely set before we increase the count */
395 sp
->clear_spte_count
++;
398 static void __set_spte(u64
*sptep
, u64 spte
)
400 union split_spte
*ssptep
, sspte
;
402 ssptep
= (union split_spte
*)sptep
;
403 sspte
= (union split_spte
)spte
;
405 ssptep
->spte_high
= sspte
.spte_high
;
408 * If we map the spte from nonpresent to present, We should store
409 * the high bits firstly, then set present bit, so cpu can not
410 * fetch this spte while we are setting the spte.
414 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
417 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
419 union split_spte
*ssptep
, sspte
;
421 ssptep
= (union split_spte
*)sptep
;
422 sspte
= (union split_spte
)spte
;
424 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
427 * If we map the spte from present to nonpresent, we should clear
428 * present bit firstly to avoid vcpu fetch the old high bits.
432 ssptep
->spte_high
= sspte
.spte_high
;
433 count_spte_clear(sptep
, spte
);
436 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
438 union split_spte
*ssptep
, sspte
, orig
;
440 ssptep
= (union split_spte
*)sptep
;
441 sspte
= (union split_spte
)spte
;
443 /* xchg acts as a barrier before the setting of the high bits */
444 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
445 orig
.spte_high
= ssptep
->spte_high
;
446 ssptep
->spte_high
= sspte
.spte_high
;
447 count_spte_clear(sptep
, spte
);
453 * The idea using the light way get the spte on x86_32 guest is from
454 * gup_get_pte (mm/gup.c).
456 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
457 * coalesces them and we are running out of the MMU lock. Therefore
458 * we need to protect against in-progress updates of the spte.
460 * Reading the spte while an update is in progress may get the old value
461 * for the high part of the spte. The race is fine for a present->non-present
462 * change (because the high part of the spte is ignored for non-present spte),
463 * but for a present->present change we must reread the spte.
465 * All such changes are done in two steps (present->non-present and
466 * non-present->present), hence it is enough to count the number of
467 * present->non-present updates: if it changed while reading the spte,
468 * we might have hit the race. This is done using clear_spte_count.
470 static u64
__get_spte_lockless(u64
*sptep
)
472 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
473 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
477 count
= sp
->clear_spte_count
;
480 spte
.spte_low
= orig
->spte_low
;
483 spte
.spte_high
= orig
->spte_high
;
486 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
487 count
!= sp
->clear_spte_count
))
494 static bool spte_has_volatile_bits(u64 spte
)
496 if (!is_shadow_present_pte(spte
))
500 * Always atomically update spte if it can be updated
501 * out of mmu-lock, it can ensure dirty bit is not lost,
502 * also, it can help us to get a stable is_writable_pte()
503 * to ensure tlb flush is not missed.
505 if (spte_can_locklessly_be_made_writable(spte
) ||
506 is_access_track_spte(spte
))
509 if (spte_ad_enabled(spte
)) {
510 if ((spte
& shadow_accessed_mask
) == 0 ||
511 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
518 /* Rules for using mmu_spte_set:
519 * Set the sptep from nonpresent to present.
520 * Note: the sptep being assigned *must* be either not present
521 * or in a state where the hardware will not attempt to update
524 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
526 WARN_ON(is_shadow_present_pte(*sptep
));
527 __set_spte(sptep
, new_spte
);
531 * Update the SPTE (excluding the PFN), but do not track changes in its
532 * accessed/dirty status.
534 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
536 u64 old_spte
= *sptep
;
538 WARN_ON(!is_shadow_present_pte(new_spte
));
540 if (!is_shadow_present_pte(old_spte
)) {
541 mmu_spte_set(sptep
, new_spte
);
545 if (!spte_has_volatile_bits(old_spte
))
546 __update_clear_spte_fast(sptep
, new_spte
);
548 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
550 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
555 /* Rules for using mmu_spte_update:
556 * Update the state bits, it means the mapped pfn is not changed.
558 * Whenever we overwrite a writable spte with a read-only one we
559 * should flush remote TLBs. Otherwise rmap_write_protect
560 * will find a read-only spte, even though the writable spte
561 * might be cached on a CPU's TLB, the return value indicates this
564 * Returns true if the TLB needs to be flushed
566 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
569 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
571 if (!is_shadow_present_pte(old_spte
))
575 * For the spte updated out of mmu-lock is safe, since
576 * we always atomically update it, see the comments in
577 * spte_has_volatile_bits().
579 if (spte_can_locklessly_be_made_writable(old_spte
) &&
580 !is_writable_pte(new_spte
))
584 * Flush TLB when accessed/dirty states are changed in the page tables,
585 * to guarantee consistency between TLB and page tables.
588 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
590 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
593 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
595 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
602 * Rules for using mmu_spte_clear_track_bits:
603 * It sets the sptep from present to nonpresent, and track the
604 * state bits, it is used to clear the last level sptep.
605 * Returns the old PTE.
607 static u64
mmu_spte_clear_track_bits(u64
*sptep
)
610 u64 old_spte
= *sptep
;
612 if (!spte_has_volatile_bits(old_spte
))
613 __update_clear_spte_fast(sptep
, 0ull);
615 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
617 if (!is_shadow_present_pte(old_spte
))
620 pfn
= spte_to_pfn(old_spte
);
623 * KVM does not hold the refcount of the page used by
624 * kvm mmu, before reclaiming the page, we should
625 * unmap it from mmu first.
627 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
629 if (is_accessed_spte(old_spte
))
630 kvm_set_pfn_accessed(pfn
);
632 if (is_dirty_spte(old_spte
))
633 kvm_set_pfn_dirty(pfn
);
639 * Rules for using mmu_spte_clear_no_track:
640 * Directly clear spte without caring the state bits of sptep,
641 * it is used to set the upper level spte.
643 static void mmu_spte_clear_no_track(u64
*sptep
)
645 __update_clear_spte_fast(sptep
, 0ull);
648 static u64
mmu_spte_get_lockless(u64
*sptep
)
650 return __get_spte_lockless(sptep
);
653 /* Restore an acc-track PTE back to a regular PTE */
654 static u64
restore_acc_track_spte(u64 spte
)
657 u64 saved_bits
= (spte
>> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
)
658 & SHADOW_ACC_TRACK_SAVED_BITS_MASK
;
660 WARN_ON_ONCE(spte_ad_enabled(spte
));
661 WARN_ON_ONCE(!is_access_track_spte(spte
));
663 new_spte
&= ~shadow_acc_track_mask
;
664 new_spte
&= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK
<<
665 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT
);
666 new_spte
|= saved_bits
;
671 /* Returns the Accessed status of the PTE and resets it at the same time. */
672 static bool mmu_spte_age(u64
*sptep
)
674 u64 spte
= mmu_spte_get_lockless(sptep
);
676 if (!is_accessed_spte(spte
))
679 if (spte_ad_enabled(spte
)) {
680 clear_bit((ffs(shadow_accessed_mask
) - 1),
681 (unsigned long *)sptep
);
684 * Capture the dirty status of the page, so that it doesn't get
685 * lost when the SPTE is marked for access tracking.
687 if (is_writable_pte(spte
))
688 kvm_set_pfn_dirty(spte_to_pfn(spte
));
690 spte
= mark_spte_for_access_track(spte
);
691 mmu_spte_update_no_track(sptep
, spte
);
697 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
699 if (is_tdp_mmu(vcpu
->arch
.mmu
)) {
700 kvm_tdp_mmu_walk_lockless_begin();
703 * Prevent page table teardown by making any free-er wait during
704 * kvm_flush_remote_tlbs() IPI to all active vcpus.
709 * Make sure a following spte read is not reordered ahead of the write
712 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
716 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
718 if (is_tdp_mmu(vcpu
->arch
.mmu
)) {
719 kvm_tdp_mmu_walk_lockless_end();
722 * Make sure the write to vcpu->mode is not reordered in front of
723 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
724 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
726 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
731 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
, bool maybe_indirect
)
735 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
736 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
737 1 + PT64_ROOT_MAX_LEVEL
+ PTE_PREFETCH_NUM
);
740 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
,
741 PT64_ROOT_MAX_LEVEL
);
744 if (maybe_indirect
) {
745 r
= kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
,
746 PT64_ROOT_MAX_LEVEL
);
750 return kvm_mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
751 PT64_ROOT_MAX_LEVEL
);
754 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
756 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
);
757 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_shadow_page_cache
);
758 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_gfn_array_cache
);
759 kvm_mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
);
762 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
764 return kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
767 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
769 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
772 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
774 if (!sp
->role
.direct
)
775 return sp
->gfns
[index
];
777 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
780 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
782 if (!sp
->role
.direct
) {
783 sp
->gfns
[index
] = gfn
;
787 if (WARN_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
)))
788 pr_err_ratelimited("gfn mismatch under direct page %llx "
789 "(expected %llx, got %llx)\n",
791 kvm_mmu_page_get_gfn(sp
, index
), gfn
);
795 * Return the pointer to the large page information for a given gfn,
796 * handling slots that are not large page aligned.
798 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
799 const struct kvm_memory_slot
*slot
, int level
)
803 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
804 return &slot
->arch
.lpage_info
[level
- 2][idx
];
807 static void update_gfn_disallow_lpage_count(const struct kvm_memory_slot
*slot
,
808 gfn_t gfn
, int count
)
810 struct kvm_lpage_info
*linfo
;
813 for (i
= PG_LEVEL_2M
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
814 linfo
= lpage_info_slot(gfn
, slot
, i
);
815 linfo
->disallow_lpage
+= count
;
816 WARN_ON(linfo
->disallow_lpage
< 0);
820 void kvm_mmu_gfn_disallow_lpage(const struct kvm_memory_slot
*slot
, gfn_t gfn
)
822 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
825 void kvm_mmu_gfn_allow_lpage(const struct kvm_memory_slot
*slot
, gfn_t gfn
)
827 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
830 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
832 struct kvm_memslots
*slots
;
833 struct kvm_memory_slot
*slot
;
836 kvm
->arch
.indirect_shadow_pages
++;
838 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
839 slot
= __gfn_to_memslot(slots
, gfn
);
841 /* the non-leaf shadow pages are keeping readonly. */
842 if (sp
->role
.level
> PG_LEVEL_4K
)
843 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
844 KVM_PAGE_TRACK_WRITE
);
846 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
849 void account_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
851 if (sp
->lpage_disallowed
)
854 ++kvm
->stat
.nx_lpage_splits
;
855 list_add_tail(&sp
->lpage_disallowed_link
,
856 &kvm
->arch
.lpage_disallowed_mmu_pages
);
857 sp
->lpage_disallowed
= true;
860 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
862 struct kvm_memslots
*slots
;
863 struct kvm_memory_slot
*slot
;
866 kvm
->arch
.indirect_shadow_pages
--;
868 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
869 slot
= __gfn_to_memslot(slots
, gfn
);
870 if (sp
->role
.level
> PG_LEVEL_4K
)
871 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
872 KVM_PAGE_TRACK_WRITE
);
874 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
877 void unaccount_huge_nx_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
879 --kvm
->stat
.nx_lpage_splits
;
880 sp
->lpage_disallowed
= false;
881 list_del(&sp
->lpage_disallowed_link
);
884 static struct kvm_memory_slot
*
885 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
888 struct kvm_memory_slot
*slot
;
890 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
891 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
893 if (no_dirty_log
&& kvm_slot_dirty_track_enabled(slot
))
900 * About rmap_head encoding:
902 * If the bit zero of rmap_head->val is clear, then it points to the only spte
903 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
904 * pte_list_desc containing more mappings.
908 * Returns the number of pointers in the rmap chain, not counting the new one.
910 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
911 struct kvm_rmap_head
*rmap_head
)
913 struct pte_list_desc
*desc
;
916 if (!rmap_head
->val
) {
917 rmap_printk("%p %llx 0->1\n", spte
, *spte
);
918 rmap_head
->val
= (unsigned long)spte
;
919 } else if (!(rmap_head
->val
& 1)) {
920 rmap_printk("%p %llx 1->many\n", spte
, *spte
);
921 desc
= mmu_alloc_pte_list_desc(vcpu
);
922 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
923 desc
->sptes
[1] = spte
;
924 desc
->spte_count
= 2;
925 rmap_head
->val
= (unsigned long)desc
| 1;
928 rmap_printk("%p %llx many->many\n", spte
, *spte
);
929 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
930 while (desc
->spte_count
== PTE_LIST_EXT
) {
931 count
+= PTE_LIST_EXT
;
933 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
935 desc
->spte_count
= 0;
940 count
+= desc
->spte_count
;
941 desc
->sptes
[desc
->spte_count
++] = spte
;
947 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
948 struct pte_list_desc
*desc
, int i
,
949 struct pte_list_desc
*prev_desc
)
951 int j
= desc
->spte_count
- 1;
953 desc
->sptes
[i
] = desc
->sptes
[j
];
954 desc
->sptes
[j
] = NULL
;
956 if (desc
->spte_count
)
958 if (!prev_desc
&& !desc
->more
)
962 prev_desc
->more
= desc
->more
;
964 rmap_head
->val
= (unsigned long)desc
->more
| 1;
965 mmu_free_pte_list_desc(desc
);
968 static void __pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
970 struct pte_list_desc
*desc
;
971 struct pte_list_desc
*prev_desc
;
974 if (!rmap_head
->val
) {
975 pr_err("%s: %p 0->BUG\n", __func__
, spte
);
977 } else if (!(rmap_head
->val
& 1)) {
978 rmap_printk("%p 1->0\n", spte
);
979 if ((u64
*)rmap_head
->val
!= spte
) {
980 pr_err("%s: %p 1->BUG\n", __func__
, spte
);
985 rmap_printk("%p many->many\n", spte
);
986 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
989 for (i
= 0; i
< desc
->spte_count
; ++i
) {
990 if (desc
->sptes
[i
] == spte
) {
991 pte_list_desc_remove_entry(rmap_head
,
999 pr_err("%s: %p many->many\n", __func__
, spte
);
1004 static void pte_list_remove(struct kvm_rmap_head
*rmap_head
, u64
*sptep
)
1006 mmu_spte_clear_track_bits(sptep
);
1007 __pte_list_remove(sptep
, rmap_head
);
1010 /* Return true if rmap existed, false otherwise */
1011 static bool pte_list_destroy(struct kvm_rmap_head
*rmap_head
)
1013 struct pte_list_desc
*desc
, *next
;
1016 if (!rmap_head
->val
)
1019 if (!(rmap_head
->val
& 1)) {
1020 mmu_spte_clear_track_bits((u64
*)rmap_head
->val
);
1024 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1026 for (; desc
; desc
= next
) {
1027 for (i
= 0; i
< desc
->spte_count
; i
++)
1028 mmu_spte_clear_track_bits(desc
->sptes
[i
]);
1030 mmu_free_pte_list_desc(desc
);
1033 /* rmap_head is meaningless now, remember to reset it */
1038 unsigned int pte_list_count(struct kvm_rmap_head
*rmap_head
)
1040 struct pte_list_desc
*desc
;
1041 unsigned int count
= 0;
1043 if (!rmap_head
->val
)
1045 else if (!(rmap_head
->val
& 1))
1048 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1051 count
+= desc
->spte_count
;
1058 static struct kvm_rmap_head
*gfn_to_rmap(gfn_t gfn
, int level
,
1059 const struct kvm_memory_slot
*slot
)
1063 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1064 return &slot
->arch
.rmap
[level
- PG_LEVEL_4K
][idx
];
1067 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1069 struct kvm_mmu_memory_cache
*mc
;
1071 mc
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1072 return kvm_mmu_memory_cache_nr_free_objects(mc
);
1075 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1077 struct kvm_memory_slot
*slot
;
1078 struct kvm_mmu_page
*sp
;
1079 struct kvm_rmap_head
*rmap_head
;
1081 sp
= sptep_to_sp(spte
);
1082 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1083 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1084 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1085 return pte_list_add(vcpu
, spte
, rmap_head
);
1089 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1091 struct kvm_memslots
*slots
;
1092 struct kvm_memory_slot
*slot
;
1093 struct kvm_mmu_page
*sp
;
1095 struct kvm_rmap_head
*rmap_head
;
1097 sp
= sptep_to_sp(spte
);
1098 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1101 * Unlike rmap_add and rmap_recycle, rmap_remove does not run in the
1102 * context of a vCPU so have to determine which memslots to use based
1103 * on context information in sp->role.
1105 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1107 slot
= __gfn_to_memslot(slots
, gfn
);
1108 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1110 __pte_list_remove(spte
, rmap_head
);
1114 * Used by the following functions to iterate through the sptes linked by a
1115 * rmap. All fields are private and not assumed to be used outside.
1117 struct rmap_iterator
{
1118 /* private fields */
1119 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1120 int pos
; /* index of the sptep */
1124 * Iteration must be started by this function. This should also be used after
1125 * removing/dropping sptes from the rmap link because in such cases the
1126 * information in the iterator may not be valid.
1128 * Returns sptep if found, NULL otherwise.
1130 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1131 struct rmap_iterator
*iter
)
1135 if (!rmap_head
->val
)
1138 if (!(rmap_head
->val
& 1)) {
1140 sptep
= (u64
*)rmap_head
->val
;
1144 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1146 sptep
= iter
->desc
->sptes
[iter
->pos
];
1148 BUG_ON(!is_shadow_present_pte(*sptep
));
1153 * Must be used with a valid iterator: e.g. after rmap_get_first().
1155 * Returns sptep if found, NULL otherwise.
1157 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1162 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1164 sptep
= iter
->desc
->sptes
[iter
->pos
];
1169 iter
->desc
= iter
->desc
->more
;
1173 /* desc->sptes[0] cannot be NULL */
1174 sptep
= iter
->desc
->sptes
[iter
->pos
];
1181 BUG_ON(!is_shadow_present_pte(*sptep
));
1185 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1186 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1187 _spte_; _spte_ = rmap_get_next(_iter_))
1189 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1191 u64 old_spte
= mmu_spte_clear_track_bits(sptep
);
1193 if (is_shadow_present_pte(old_spte
))
1194 rmap_remove(kvm
, sptep
);
1198 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1200 if (is_large_pte(*sptep
)) {
1201 WARN_ON(sptep_to_sp(sptep
)->role
.level
== PG_LEVEL_4K
);
1202 drop_spte(kvm
, sptep
);
1210 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1212 if (__drop_large_spte(vcpu
->kvm
, sptep
)) {
1213 struct kvm_mmu_page
*sp
= sptep_to_sp(sptep
);
1215 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1216 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1221 * Write-protect on the specified @sptep, @pt_protect indicates whether
1222 * spte write-protection is caused by protecting shadow page table.
1224 * Note: write protection is difference between dirty logging and spte
1226 * - for dirty logging, the spte can be set to writable at anytime if
1227 * its dirty bitmap is properly set.
1228 * - for spte protection, the spte can be writable only after unsync-ing
1231 * Return true if tlb need be flushed.
1233 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1237 if (!is_writable_pte(spte
) &&
1238 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1241 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1244 spte
&= ~shadow_mmu_writable_mask
;
1245 spte
= spte
& ~PT_WRITABLE_MASK
;
1247 return mmu_spte_update(sptep
, spte
);
1250 static bool __rmap_write_protect(struct kvm
*kvm
,
1251 struct kvm_rmap_head
*rmap_head
,
1255 struct rmap_iterator iter
;
1258 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1259 flush
|= spte_write_protect(sptep
, pt_protect
);
1264 static bool spte_clear_dirty(u64
*sptep
)
1268 rmap_printk("spte %p %llx\n", sptep
, *sptep
);
1270 MMU_WARN_ON(!spte_ad_enabled(spte
));
1271 spte
&= ~shadow_dirty_mask
;
1272 return mmu_spte_update(sptep
, spte
);
1275 static bool spte_wrprot_for_clear_dirty(u64
*sptep
)
1277 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1278 (unsigned long *)sptep
);
1279 if (was_writable
&& !spte_ad_enabled(*sptep
))
1280 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1282 return was_writable
;
1286 * Gets the GFN ready for another round of dirty logging by clearing the
1287 * - D bit on ad-enabled SPTEs, and
1288 * - W bit on ad-disabled SPTEs.
1289 * Returns true iff any D or W bits were cleared.
1291 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1292 const struct kvm_memory_slot
*slot
)
1295 struct rmap_iterator iter
;
1298 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1299 if (spte_ad_need_write_protect(*sptep
))
1300 flush
|= spte_wrprot_for_clear_dirty(sptep
);
1302 flush
|= spte_clear_dirty(sptep
);
1308 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1309 * @kvm: kvm instance
1310 * @slot: slot to protect
1311 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1312 * @mask: indicates which pages we should protect
1314 * Used when we do not need to care about huge page mappings.
1316 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1317 struct kvm_memory_slot
*slot
,
1318 gfn_t gfn_offset
, unsigned long mask
)
1320 struct kvm_rmap_head
*rmap_head
;
1322 if (is_tdp_mmu_enabled(kvm
))
1323 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1324 slot
->base_gfn
+ gfn_offset
, mask
, true);
1326 if (!kvm_memslots_have_rmaps(kvm
))
1330 rmap_head
= gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1332 __rmap_write_protect(kvm
, rmap_head
, false);
1334 /* clear the first set bit */
1340 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1341 * protect the page if the D-bit isn't supported.
1342 * @kvm: kvm instance
1343 * @slot: slot to clear D-bit
1344 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1345 * @mask: indicates which pages we should clear D-bit
1347 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1349 static void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1350 struct kvm_memory_slot
*slot
,
1351 gfn_t gfn_offset
, unsigned long mask
)
1353 struct kvm_rmap_head
*rmap_head
;
1355 if (is_tdp_mmu_enabled(kvm
))
1356 kvm_tdp_mmu_clear_dirty_pt_masked(kvm
, slot
,
1357 slot
->base_gfn
+ gfn_offset
, mask
, false);
1359 if (!kvm_memslots_have_rmaps(kvm
))
1363 rmap_head
= gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1365 __rmap_clear_dirty(kvm
, rmap_head
, slot
);
1367 /* clear the first set bit */
1373 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1376 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1377 * enable dirty logging for them.
1379 * We need to care about huge page mappings: e.g. during dirty logging we may
1380 * have such mappings.
1382 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1383 struct kvm_memory_slot
*slot
,
1384 gfn_t gfn_offset
, unsigned long mask
)
1387 * Huge pages are NOT write protected when we start dirty logging in
1388 * initially-all-set mode; must write protect them here so that they
1389 * are split to 4K on the first write.
1391 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1392 * of memslot has no such restriction, so the range can cross two large
1395 if (kvm_dirty_log_manual_protect_and_init_set(kvm
)) {
1396 gfn_t start
= slot
->base_gfn
+ gfn_offset
+ __ffs(mask
);
1397 gfn_t end
= slot
->base_gfn
+ gfn_offset
+ __fls(mask
);
1399 kvm_mmu_slot_gfn_write_protect(kvm
, slot
, start
, PG_LEVEL_2M
);
1401 /* Cross two large pages? */
1402 if (ALIGN(start
<< PAGE_SHIFT
, PMD_SIZE
) !=
1403 ALIGN(end
<< PAGE_SHIFT
, PMD_SIZE
))
1404 kvm_mmu_slot_gfn_write_protect(kvm
, slot
, end
,
1408 /* Now handle 4K PTEs. */
1409 if (kvm_x86_ops
.cpu_dirty_log_size
)
1410 kvm_mmu_clear_dirty_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1412 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1415 int kvm_cpu_dirty_log_size(void)
1417 return kvm_x86_ops
.cpu_dirty_log_size
;
1420 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1421 struct kvm_memory_slot
*slot
, u64 gfn
,
1424 struct kvm_rmap_head
*rmap_head
;
1426 bool write_protected
= false;
1428 if (kvm_memslots_have_rmaps(kvm
)) {
1429 for (i
= min_level
; i
<= KVM_MAX_HUGEPAGE_LEVEL
; ++i
) {
1430 rmap_head
= gfn_to_rmap(gfn
, i
, slot
);
1431 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1435 if (is_tdp_mmu_enabled(kvm
))
1437 kvm_tdp_mmu_write_protect_gfn(kvm
, slot
, gfn
, min_level
);
1439 return write_protected
;
1442 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1444 struct kvm_memory_slot
*slot
;
1446 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1447 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
, PG_LEVEL_4K
);
1450 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1451 const struct kvm_memory_slot
*slot
)
1453 return pte_list_destroy(rmap_head
);
1456 static bool kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1457 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1460 return kvm_zap_rmapp(kvm
, rmap_head
, slot
);
1463 static bool kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1464 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1468 struct rmap_iterator iter
;
1473 WARN_ON(pte_huge(pte
));
1474 new_pfn
= pte_pfn(pte
);
1477 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1478 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1479 sptep
, *sptep
, gfn
, level
);
1483 if (pte_write(pte
)) {
1484 pte_list_remove(rmap_head
, sptep
);
1487 new_spte
= kvm_mmu_changed_pte_notifier_make_spte(
1490 mmu_spte_clear_track_bits(sptep
);
1491 mmu_spte_set(sptep
, new_spte
);
1495 if (need_flush
&& kvm_available_flush_tlb_with_range()) {
1496 kvm_flush_remote_tlbs_with_address(kvm
, gfn
, 1);
1503 struct slot_rmap_walk_iterator
{
1505 const struct kvm_memory_slot
*slot
;
1511 /* output fields. */
1513 struct kvm_rmap_head
*rmap
;
1516 /* private field. */
1517 struct kvm_rmap_head
*end_rmap
;
1521 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1523 iterator
->level
= level
;
1524 iterator
->gfn
= iterator
->start_gfn
;
1525 iterator
->rmap
= gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1526 iterator
->end_rmap
= gfn_to_rmap(iterator
->end_gfn
, level
, iterator
->slot
);
1530 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1531 const struct kvm_memory_slot
*slot
, int start_level
,
1532 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1534 iterator
->slot
= slot
;
1535 iterator
->start_level
= start_level
;
1536 iterator
->end_level
= end_level
;
1537 iterator
->start_gfn
= start_gfn
;
1538 iterator
->end_gfn
= end_gfn
;
1540 rmap_walk_init_level(iterator
, iterator
->start_level
);
1543 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1545 return !!iterator
->rmap
;
1548 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1550 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1551 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1555 if (++iterator
->level
> iterator
->end_level
) {
1556 iterator
->rmap
= NULL
;
1560 rmap_walk_init_level(iterator
, iterator
->level
);
1563 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1564 _start_gfn, _end_gfn, _iter_) \
1565 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1566 _end_level_, _start_gfn, _end_gfn); \
1567 slot_rmap_walk_okay(_iter_); \
1568 slot_rmap_walk_next(_iter_))
1570 typedef bool (*rmap_handler_t
)(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1571 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1572 int level
, pte_t pte
);
1574 static __always_inline
bool kvm_handle_gfn_range(struct kvm
*kvm
,
1575 struct kvm_gfn_range
*range
,
1576 rmap_handler_t handler
)
1578 struct slot_rmap_walk_iterator iterator
;
1581 for_each_slot_rmap_range(range
->slot
, PG_LEVEL_4K
, KVM_MAX_HUGEPAGE_LEVEL
,
1582 range
->start
, range
->end
- 1, &iterator
)
1583 ret
|= handler(kvm
, iterator
.rmap
, range
->slot
, iterator
.gfn
,
1584 iterator
.level
, range
->pte
);
1589 bool kvm_unmap_gfn_range(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1593 if (kvm_memslots_have_rmaps(kvm
))
1594 flush
= kvm_handle_gfn_range(kvm
, range
, kvm_unmap_rmapp
);
1596 if (is_tdp_mmu_enabled(kvm
))
1597 flush
|= kvm_tdp_mmu_unmap_gfn_range(kvm
, range
, flush
);
1602 bool kvm_set_spte_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1606 if (kvm_memslots_have_rmaps(kvm
))
1607 flush
= kvm_handle_gfn_range(kvm
, range
, kvm_set_pte_rmapp
);
1609 if (is_tdp_mmu_enabled(kvm
))
1610 flush
|= kvm_tdp_mmu_set_spte_gfn(kvm
, range
);
1615 static bool kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1616 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1620 struct rmap_iterator iter
;
1623 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1624 young
|= mmu_spte_age(sptep
);
1629 static bool kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1630 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1631 int level
, pte_t unused
)
1634 struct rmap_iterator iter
;
1636 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1637 if (is_accessed_spte(*sptep
))
1642 #define RMAP_RECYCLE_THRESHOLD 1000
1644 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1646 struct kvm_memory_slot
*slot
;
1647 struct kvm_rmap_head
*rmap_head
;
1648 struct kvm_mmu_page
*sp
;
1650 sp
= sptep_to_sp(spte
);
1651 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1652 rmap_head
= gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1654 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, __pte(0));
1655 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, sp
->gfn
,
1656 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
1659 bool kvm_age_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1663 if (kvm_memslots_have_rmaps(kvm
))
1664 young
= kvm_handle_gfn_range(kvm
, range
, kvm_age_rmapp
);
1666 if (is_tdp_mmu_enabled(kvm
))
1667 young
|= kvm_tdp_mmu_age_gfn_range(kvm
, range
);
1672 bool kvm_test_age_gfn(struct kvm
*kvm
, struct kvm_gfn_range
*range
)
1676 if (kvm_memslots_have_rmaps(kvm
))
1677 young
= kvm_handle_gfn_range(kvm
, range
, kvm_test_age_rmapp
);
1679 if (is_tdp_mmu_enabled(kvm
))
1680 young
|= kvm_tdp_mmu_test_age_gfn(kvm
, range
);
1686 static int is_empty_shadow_page(u64
*spt
)
1691 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1692 if (is_shadow_present_pte(*pos
)) {
1693 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1702 * This value is the sum of all of the kvm instances's
1703 * kvm->arch.n_used_mmu_pages values. We need a global,
1704 * aggregate version in order to make the slab shrinker
1707 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, long nr
)
1709 kvm
->arch
.n_used_mmu_pages
+= nr
;
1710 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1713 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1715 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1716 hlist_del(&sp
->hash_link
);
1717 list_del(&sp
->link
);
1718 free_page((unsigned long)sp
->spt
);
1719 if (!sp
->role
.direct
)
1720 free_page((unsigned long)sp
->gfns
);
1721 kmem_cache_free(mmu_page_header_cache
, sp
);
1724 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1726 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1729 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1730 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1735 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1738 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1741 __pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1744 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1747 mmu_page_remove_parent_pte(sp
, parent_pte
);
1748 mmu_spte_clear_no_track(parent_pte
);
1751 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1753 struct kvm_mmu_page
*sp
;
1755 sp
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1756 sp
->spt
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_shadow_page_cache
);
1758 sp
->gfns
= kvm_mmu_memory_cache_alloc(&vcpu
->arch
.mmu_gfn_array_cache
);
1759 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1762 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1763 * depends on valid pages being added to the head of the list. See
1764 * comments in kvm_zap_obsolete_pages().
1766 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
1767 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1768 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1772 static void mark_unsync(u64
*spte
);
1773 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1776 struct rmap_iterator iter
;
1778 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1783 static void mark_unsync(u64
*spte
)
1785 struct kvm_mmu_page
*sp
;
1788 sp
= sptep_to_sp(spte
);
1789 index
= spte
- sp
->spt
;
1790 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1792 if (sp
->unsync_children
++)
1794 kvm_mmu_mark_parents_unsync(sp
);
1797 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1798 struct kvm_mmu_page
*sp
)
1803 #define KVM_PAGE_ARRAY_NR 16
1805 struct kvm_mmu_pages
{
1806 struct mmu_page_and_offset
{
1807 struct kvm_mmu_page
*sp
;
1809 } page
[KVM_PAGE_ARRAY_NR
];
1813 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1819 for (i
=0; i
< pvec
->nr
; i
++)
1820 if (pvec
->page
[i
].sp
== sp
)
1823 pvec
->page
[pvec
->nr
].sp
= sp
;
1824 pvec
->page
[pvec
->nr
].idx
= idx
;
1826 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1829 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1831 --sp
->unsync_children
;
1832 WARN_ON((int)sp
->unsync_children
< 0);
1833 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1836 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1837 struct kvm_mmu_pages
*pvec
)
1839 int i
, ret
, nr_unsync_leaf
= 0;
1841 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1842 struct kvm_mmu_page
*child
;
1843 u64 ent
= sp
->spt
[i
];
1845 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1846 clear_unsync_child_bit(sp
, i
);
1850 child
= to_shadow_page(ent
& PT64_BASE_ADDR_MASK
);
1852 if (child
->unsync_children
) {
1853 if (mmu_pages_add(pvec
, child
, i
))
1856 ret
= __mmu_unsync_walk(child
, pvec
);
1858 clear_unsync_child_bit(sp
, i
);
1860 } else if (ret
> 0) {
1861 nr_unsync_leaf
+= ret
;
1864 } else if (child
->unsync
) {
1866 if (mmu_pages_add(pvec
, child
, i
))
1869 clear_unsync_child_bit(sp
, i
);
1872 return nr_unsync_leaf
;
1875 #define INVALID_INDEX (-1)
1877 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1878 struct kvm_mmu_pages
*pvec
)
1881 if (!sp
->unsync_children
)
1884 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1885 return __mmu_unsync_walk(sp
, pvec
);
1888 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1890 WARN_ON(!sp
->unsync
);
1891 trace_kvm_mmu_sync_page(sp
);
1893 --kvm
->stat
.mmu_unsync
;
1896 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1897 struct list_head
*invalid_list
);
1898 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1899 struct list_head
*invalid_list
);
1901 #define for_each_valid_sp(_kvm, _sp, _list) \
1902 hlist_for_each_entry(_sp, _list, hash_link) \
1903 if (is_obsolete_sp((_kvm), (_sp))) { \
1906 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1907 for_each_valid_sp(_kvm, _sp, \
1908 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1909 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1911 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1912 struct list_head
*invalid_list
)
1914 if (vcpu
->arch
.mmu
->sync_page(vcpu
, sp
) == 0) {
1915 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1922 static bool kvm_mmu_remote_flush_or_zap(struct kvm
*kvm
,
1923 struct list_head
*invalid_list
,
1926 if (!remote_flush
&& list_empty(invalid_list
))
1929 if (!list_empty(invalid_list
))
1930 kvm_mmu_commit_zap_page(kvm
, invalid_list
);
1932 kvm_flush_remote_tlbs(kvm
);
1936 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1937 struct list_head
*invalid_list
,
1938 bool remote_flush
, bool local_flush
)
1940 if (kvm_mmu_remote_flush_or_zap(vcpu
->kvm
, invalid_list
, remote_flush
))
1944 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
1947 #ifdef CONFIG_KVM_MMU_AUDIT
1948 #include "mmu_audit.c"
1950 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1951 static void mmu_audit_disable(void) { }
1954 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1956 return sp
->role
.invalid
||
1957 unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1960 struct mmu_page_path
{
1961 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
1962 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
1965 #define for_each_sp(pvec, sp, parents, i) \
1966 for (i = mmu_pages_first(&pvec, &parents); \
1967 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1968 i = mmu_pages_next(&pvec, &parents, i))
1970 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1971 struct mmu_page_path
*parents
,
1976 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1977 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1978 unsigned idx
= pvec
->page
[n
].idx
;
1979 int level
= sp
->role
.level
;
1981 parents
->idx
[level
-1] = idx
;
1982 if (level
== PG_LEVEL_4K
)
1985 parents
->parent
[level
-2] = sp
;
1991 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
1992 struct mmu_page_path
*parents
)
1994 struct kvm_mmu_page
*sp
;
2000 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2002 sp
= pvec
->page
[0].sp
;
2003 level
= sp
->role
.level
;
2004 WARN_ON(level
== PG_LEVEL_4K
);
2006 parents
->parent
[level
-2] = sp
;
2008 /* Also set up a sentinel. Further entries in pvec are all
2009 * children of sp, so this element is never overwritten.
2011 parents
->parent
[level
-1] = NULL
;
2012 return mmu_pages_next(pvec
, parents
, 0);
2015 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2017 struct kvm_mmu_page
*sp
;
2018 unsigned int level
= 0;
2021 unsigned int idx
= parents
->idx
[level
];
2022 sp
= parents
->parent
[level
];
2026 WARN_ON(idx
== INVALID_INDEX
);
2027 clear_unsync_child_bit(sp
, idx
);
2029 } while (!sp
->unsync_children
);
2032 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2033 struct kvm_mmu_page
*parent
)
2036 struct kvm_mmu_page
*sp
;
2037 struct mmu_page_path parents
;
2038 struct kvm_mmu_pages pages
;
2039 LIST_HEAD(invalid_list
);
2042 while (mmu_unsync_walk(parent
, &pages
)) {
2043 bool protected = false;
2045 for_each_sp(pages
, sp
, parents
, i
)
2046 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2049 kvm_flush_remote_tlbs(vcpu
->kvm
);
2053 for_each_sp(pages
, sp
, parents
, i
) {
2054 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2055 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2056 mmu_pages_clear_parents(&parents
);
2058 if (need_resched() || rwlock_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2059 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2060 cond_resched_rwlock_write(&vcpu
->kvm
->mmu_lock
);
2065 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2068 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2070 atomic_set(&sp
->write_flooding_count
, 0);
2073 static void clear_sp_write_flooding_count(u64
*spte
)
2075 __clear_sp_write_flooding_count(sptep_to_sp(spte
));
2078 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2083 unsigned int access
)
2085 bool direct_mmu
= vcpu
->arch
.mmu
->direct_map
;
2086 union kvm_mmu_page_role role
;
2087 struct hlist_head
*sp_list
;
2089 struct kvm_mmu_page
*sp
;
2091 LIST_HEAD(invalid_list
);
2093 role
= vcpu
->arch
.mmu
->mmu_role
.base
;
2095 role
.direct
= direct
;
2097 role
.gpte_is_8_bytes
= true;
2098 role
.access
= access
;
2099 if (!direct_mmu
&& vcpu
->arch
.mmu
->root_level
<= PT32_ROOT_LEVEL
) {
2100 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2101 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2102 role
.quadrant
= quadrant
;
2105 sp_list
= &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)];
2106 for_each_valid_sp(vcpu
->kvm
, sp
, sp_list
) {
2107 if (sp
->gfn
!= gfn
) {
2112 if (sp
->role
.word
!= role
.word
) {
2114 * If the guest is creating an upper-level page, zap
2115 * unsync pages for the same gfn. While it's possible
2116 * the guest is using recursive page tables, in all
2117 * likelihood the guest has stopped using the unsync
2118 * page and is installing a completely unrelated page.
2119 * Unsync pages must not be left as is, because the new
2120 * upper-level page will be write-protected.
2122 if (level
> PG_LEVEL_4K
&& sp
->unsync
)
2123 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2129 goto trace_get_page
;
2133 * The page is good, but is stale. kvm_sync_page does
2134 * get the latest guest state, but (unlike mmu_unsync_children)
2135 * it doesn't write-protect the page or mark it synchronized!
2136 * This way the validity of the mapping is ensured, but the
2137 * overhead of write protection is not incurred until the
2138 * guest invalidates the TLB mapping. This allows multiple
2139 * SPs for a single gfn to be unsync.
2141 * If the sync fails, the page is zapped. If so, break
2142 * in order to rebuild it.
2144 if (!kvm_sync_page(vcpu
, sp
, &invalid_list
))
2147 WARN_ON(!list_empty(&invalid_list
));
2148 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2151 if (sp
->unsync_children
)
2152 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2154 __clear_sp_write_flooding_count(sp
);
2157 trace_kvm_mmu_get_page(sp
, false);
2161 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2163 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2167 hlist_add_head(&sp
->hash_link
, sp_list
);
2169 account_shadowed(vcpu
->kvm
, sp
);
2170 if (level
== PG_LEVEL_4K
&& rmap_write_protect(vcpu
, gfn
))
2171 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
, 1);
2173 trace_kvm_mmu_get_page(sp
, true);
2175 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2177 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2178 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2182 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator
*iterator
,
2183 struct kvm_vcpu
*vcpu
, hpa_t root
,
2186 iterator
->addr
= addr
;
2187 iterator
->shadow_addr
= root
;
2188 iterator
->level
= vcpu
->arch
.mmu
->shadow_root_level
;
2190 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2191 vcpu
->arch
.mmu
->root_level
< PT64_ROOT_4LEVEL
&&
2192 !vcpu
->arch
.mmu
->direct_map
)
2195 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2197 * prev_root is currently only used for 64-bit hosts. So only
2198 * the active root_hpa is valid here.
2200 BUG_ON(root
!= vcpu
->arch
.mmu
->root_hpa
);
2202 iterator
->shadow_addr
2203 = vcpu
->arch
.mmu
->pae_root
[(addr
>> 30) & 3];
2204 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2206 if (!iterator
->shadow_addr
)
2207 iterator
->level
= 0;
2211 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2212 struct kvm_vcpu
*vcpu
, u64 addr
)
2214 shadow_walk_init_using_root(iterator
, vcpu
, vcpu
->arch
.mmu
->root_hpa
,
2218 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2220 if (iterator
->level
< PG_LEVEL_4K
)
2223 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2224 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2228 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2231 if (is_last_spte(spte
, iterator
->level
)) {
2232 iterator
->level
= 0;
2236 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2240 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2242 __shadow_walk_next(iterator
, *iterator
->sptep
);
2245 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2246 struct kvm_mmu_page
*sp
)
2250 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2252 spte
= make_nonleaf_spte(sp
->spt
, sp_ad_disabled(sp
));
2254 mmu_spte_set(sptep
, spte
);
2256 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2258 if (sp
->unsync_children
|| sp
->unsync
)
2262 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2263 unsigned direct_access
)
2265 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2266 struct kvm_mmu_page
*child
;
2269 * For the direct sp, if the guest pte's dirty bit
2270 * changed form clean to dirty, it will corrupt the
2271 * sp's access: allow writable in the read-only sp,
2272 * so we should update the spte at this point to get
2273 * a new sp with the correct access.
2275 child
= to_shadow_page(*sptep
& PT64_BASE_ADDR_MASK
);
2276 if (child
->role
.access
== direct_access
)
2279 drop_parent_pte(child
, sptep
);
2280 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, child
->gfn
, 1);
2284 /* Returns the number of zapped non-leaf child shadow pages. */
2285 static int mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2286 u64
*spte
, struct list_head
*invalid_list
)
2289 struct kvm_mmu_page
*child
;
2292 if (is_shadow_present_pte(pte
)) {
2293 if (is_last_spte(pte
, sp
->role
.level
)) {
2294 drop_spte(kvm
, spte
);
2295 if (is_large_pte(pte
))
2298 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2299 drop_parent_pte(child
, spte
);
2302 * Recursively zap nested TDP SPs, parentless SPs are
2303 * unlikely to be used again in the near future. This
2304 * avoids retaining a large number of stale nested SPs.
2306 if (tdp_enabled
&& invalid_list
&&
2307 child
->role
.guest_mode
&& !child
->parent_ptes
.val
)
2308 return kvm_mmu_prepare_zap_page(kvm
, child
,
2311 } else if (is_mmio_spte(pte
)) {
2312 mmu_spte_clear_no_track(spte
);
2317 static int kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2318 struct kvm_mmu_page
*sp
,
2319 struct list_head
*invalid_list
)
2324 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2325 zapped
+= mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
, invalid_list
);
2330 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2333 struct rmap_iterator iter
;
2335 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2336 drop_parent_pte(sp
, sptep
);
2339 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2340 struct kvm_mmu_page
*parent
,
2341 struct list_head
*invalid_list
)
2344 struct mmu_page_path parents
;
2345 struct kvm_mmu_pages pages
;
2347 if (parent
->role
.level
== PG_LEVEL_4K
)
2350 while (mmu_unsync_walk(parent
, &pages
)) {
2351 struct kvm_mmu_page
*sp
;
2353 for_each_sp(pages
, sp
, parents
, i
) {
2354 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2355 mmu_pages_clear_parents(&parents
);
2363 static bool __kvm_mmu_prepare_zap_page(struct kvm
*kvm
,
2364 struct kvm_mmu_page
*sp
,
2365 struct list_head
*invalid_list
,
2370 trace_kvm_mmu_prepare_zap_page(sp
);
2371 ++kvm
->stat
.mmu_shadow_zapped
;
2372 *nr_zapped
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2373 *nr_zapped
+= kvm_mmu_page_unlink_children(kvm
, sp
, invalid_list
);
2374 kvm_mmu_unlink_parents(kvm
, sp
);
2376 /* Zapping children means active_mmu_pages has become unstable. */
2377 list_unstable
= *nr_zapped
;
2379 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2380 unaccount_shadowed(kvm
, sp
);
2383 kvm_unlink_unsync_page(kvm
, sp
);
2384 if (!sp
->root_count
) {
2389 * Already invalid pages (previously active roots) are not on
2390 * the active page list. See list_del() in the "else" case of
2393 if (sp
->role
.invalid
)
2394 list_add(&sp
->link
, invalid_list
);
2396 list_move(&sp
->link
, invalid_list
);
2397 kvm_mod_used_mmu_pages(kvm
, -1);
2400 * Remove the active root from the active page list, the root
2401 * will be explicitly freed when the root_count hits zero.
2403 list_del(&sp
->link
);
2406 * Obsolete pages cannot be used on any vCPUs, see the comment
2407 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2408 * treats invalid shadow pages as being obsolete.
2410 if (!is_obsolete_sp(kvm
, sp
))
2411 kvm_reload_remote_mmus(kvm
);
2414 if (sp
->lpage_disallowed
)
2415 unaccount_huge_nx_page(kvm
, sp
);
2417 sp
->role
.invalid
= 1;
2418 return list_unstable
;
2421 static bool kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2422 struct list_head
*invalid_list
)
2426 __kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
, &nr_zapped
);
2430 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2431 struct list_head
*invalid_list
)
2433 struct kvm_mmu_page
*sp
, *nsp
;
2435 if (list_empty(invalid_list
))
2439 * We need to make sure everyone sees our modifications to
2440 * the page tables and see changes to vcpu->mode here. The barrier
2441 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2442 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2444 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2445 * guest mode and/or lockless shadow page table walks.
2447 kvm_flush_remote_tlbs(kvm
);
2449 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2450 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2451 kvm_mmu_free_page(sp
);
2455 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm
*kvm
,
2456 unsigned long nr_to_zap
)
2458 unsigned long total_zapped
= 0;
2459 struct kvm_mmu_page
*sp
, *tmp
;
2460 LIST_HEAD(invalid_list
);
2464 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2468 list_for_each_entry_safe_reverse(sp
, tmp
, &kvm
->arch
.active_mmu_pages
, link
) {
2470 * Don't zap active root pages, the page itself can't be freed
2471 * and zapping it will just force vCPUs to realloc and reload.
2476 unstable
= __kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
,
2478 total_zapped
+= nr_zapped
;
2479 if (total_zapped
>= nr_to_zap
)
2486 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2488 kvm
->stat
.mmu_recycled
+= total_zapped
;
2489 return total_zapped
;
2492 static inline unsigned long kvm_mmu_available_pages(struct kvm
*kvm
)
2494 if (kvm
->arch
.n_max_mmu_pages
> kvm
->arch
.n_used_mmu_pages
)
2495 return kvm
->arch
.n_max_mmu_pages
-
2496 kvm
->arch
.n_used_mmu_pages
;
2501 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
2503 unsigned long avail
= kvm_mmu_available_pages(vcpu
->kvm
);
2505 if (likely(avail
>= KVM_MIN_FREE_MMU_PAGES
))
2508 kvm_mmu_zap_oldest_mmu_pages(vcpu
->kvm
, KVM_REFILL_PAGES
- avail
);
2511 * Note, this check is intentionally soft, it only guarantees that one
2512 * page is available, while the caller may end up allocating as many as
2513 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2514 * exceeding the (arbitrary by default) limit will not harm the host,
2515 * being too aggressive may unnecessarily kill the guest, and getting an
2516 * exact count is far more trouble than it's worth, especially in the
2519 if (!kvm_mmu_available_pages(vcpu
->kvm
))
2525 * Changing the number of mmu pages allocated to the vm
2526 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2528 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned long goal_nr_mmu_pages
)
2530 write_lock(&kvm
->mmu_lock
);
2532 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2533 kvm_mmu_zap_oldest_mmu_pages(kvm
, kvm
->arch
.n_used_mmu_pages
-
2536 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2539 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2541 write_unlock(&kvm
->mmu_lock
);
2544 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2546 struct kvm_mmu_page
*sp
;
2547 LIST_HEAD(invalid_list
);
2550 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2552 write_lock(&kvm
->mmu_lock
);
2553 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2554 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2557 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2559 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2560 write_unlock(&kvm
->mmu_lock
);
2565 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
2570 if (vcpu
->arch
.mmu
->direct_map
)
2573 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
2575 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
2580 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2582 trace_kvm_mmu_unsync_page(sp
);
2583 ++vcpu
->kvm
->stat
.mmu_unsync
;
2586 kvm_mmu_mark_parents_unsync(sp
);
2590 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2591 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2592 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2593 * be write-protected.
2595 int mmu_try_to_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool can_unsync
)
2597 struct kvm_mmu_page
*sp
;
2598 bool locked
= false;
2601 * Force write-protection if the page is being tracked. Note, the page
2602 * track machinery is used to write-protect upper-level shadow pages,
2603 * i.e. this guards the role.level == 4K assertion below!
2605 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2609 * The page is not write-tracked, mark existing shadow pages unsync
2610 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2611 * that case, KVM must complete emulation of the guest TLB flush before
2612 * allowing shadow pages to become unsync (writable by the guest).
2614 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2622 * TDP MMU page faults require an additional spinlock as they
2623 * run with mmu_lock held for read, not write, and the unsync
2624 * logic is not thread safe. Take the spinklock regardless of
2625 * the MMU type to avoid extra conditionals/parameters, there's
2626 * no meaningful penalty if mmu_lock is held for write.
2630 spin_lock(&vcpu
->kvm
->arch
.mmu_unsync_pages_lock
);
2633 * Recheck after taking the spinlock, a different vCPU
2634 * may have since marked the page unsync. A false
2635 * positive on the unprotected check above is not
2636 * possible as clearing sp->unsync _must_ hold mmu_lock
2637 * for write, i.e. unsync cannot transition from 0->1
2638 * while this CPU holds mmu_lock for read (or write).
2640 if (READ_ONCE(sp
->unsync
))
2644 WARN_ON(sp
->role
.level
!= PG_LEVEL_4K
);
2645 kvm_unsync_page(vcpu
, sp
);
2648 spin_unlock(&vcpu
->kvm
->arch
.mmu_unsync_pages_lock
);
2651 * We need to ensure that the marking of unsync pages is visible
2652 * before the SPTE is updated to allow writes because
2653 * kvm_mmu_sync_roots() checks the unsync flags without holding
2654 * the MMU lock and so can race with this. If the SPTE was updated
2655 * before the page had been marked as unsync-ed, something like the
2656 * following could happen:
2659 * ---------------------------------------------------------------------
2660 * 1.2 Host updates SPTE
2662 * 2.1 Guest writes a GPTE for GVA X.
2663 * (GPTE being in the guest page table shadowed
2664 * by the SP from CPU 1.)
2665 * This reads SPTE during the page table walk.
2666 * Since SPTE.W is read as 1, there is no
2669 * 2.2 Guest issues TLB flush.
2670 * That causes a VM Exit.
2672 * 2.3 Walking of unsync pages sees sp->unsync is
2673 * false and skips the page.
2675 * 2.4 Guest accesses GVA X.
2676 * Since the mapping in the SP was not updated,
2677 * so the old mapping for GVA X incorrectly
2681 * (sp->unsync = true)
2683 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2684 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2685 * pairs with this write barrier.
2692 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2693 unsigned int pte_access
, int level
,
2694 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2695 bool can_unsync
, bool host_writable
)
2698 struct kvm_mmu_page
*sp
;
2701 sp
= sptep_to_sp(sptep
);
2703 ret
= make_spte(vcpu
, pte_access
, level
, gfn
, pfn
, *sptep
, speculative
,
2704 can_unsync
, host_writable
, sp_ad_disabled(sp
), &spte
);
2706 if (spte
& PT_WRITABLE_MASK
)
2707 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2710 ret
|= SET_SPTE_SPURIOUS
;
2711 else if (mmu_spte_update(sptep
, spte
))
2712 ret
|= SET_SPTE_NEED_REMOTE_TLB_FLUSH
;
2716 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2717 unsigned int pte_access
, bool write_fault
, int level
,
2718 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2721 int was_rmapped
= 0;
2724 int ret
= RET_PF_FIXED
;
2727 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2728 *sptep
, write_fault
, gfn
);
2730 if (unlikely(is_noslot_pfn(pfn
))) {
2731 mark_mmio_spte(vcpu
, sptep
, gfn
, pte_access
);
2732 return RET_PF_EMULATE
;
2735 if (is_shadow_present_pte(*sptep
)) {
2737 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2738 * the parent of the now unreachable PTE.
2740 if (level
> PG_LEVEL_4K
&& !is_large_pte(*sptep
)) {
2741 struct kvm_mmu_page
*child
;
2744 child
= to_shadow_page(pte
& PT64_BASE_ADDR_MASK
);
2745 drop_parent_pte(child
, sptep
);
2747 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2748 pgprintk("hfn old %llx new %llx\n",
2749 spte_to_pfn(*sptep
), pfn
);
2750 drop_spte(vcpu
->kvm
, sptep
);
2756 set_spte_ret
= set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
,
2757 speculative
, true, host_writable
);
2758 if (set_spte_ret
& SET_SPTE_WRITE_PROTECTED_PT
) {
2760 ret
= RET_PF_EMULATE
;
2761 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
2764 if (set_spte_ret
& SET_SPTE_NEED_REMOTE_TLB_FLUSH
|| flush
)
2765 kvm_flush_remote_tlbs_with_address(vcpu
->kvm
, gfn
,
2766 KVM_PAGES_PER_HPAGE(level
));
2769 * The fault is fully spurious if and only if the new SPTE and old SPTE
2770 * are identical, and emulation is not required.
2772 if ((set_spte_ret
& SET_SPTE_SPURIOUS
) && ret
== RET_PF_FIXED
) {
2773 WARN_ON_ONCE(!was_rmapped
);
2774 return RET_PF_SPURIOUS
;
2777 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2778 trace_kvm_mmu_set_spte(level
, gfn
, sptep
);
2779 if (!was_rmapped
&& is_large_pte(*sptep
))
2780 ++vcpu
->kvm
->stat
.lpages
;
2782 if (is_shadow_present_pte(*sptep
)) {
2784 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2785 if (rmap_count
> vcpu
->kvm
->stat
.max_mmu_rmap_size
)
2786 vcpu
->kvm
->stat
.max_mmu_rmap_size
= rmap_count
;
2787 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2788 rmap_recycle(vcpu
, sptep
, gfn
);
2795 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2798 struct kvm_memory_slot
*slot
;
2800 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2802 return KVM_PFN_ERR_FAULT
;
2804 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2807 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2808 struct kvm_mmu_page
*sp
,
2809 u64
*start
, u64
*end
)
2811 struct page
*pages
[PTE_PREFETCH_NUM
];
2812 struct kvm_memory_slot
*slot
;
2813 unsigned int access
= sp
->role
.access
;
2817 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2818 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2822 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2826 for (i
= 0; i
< ret
; i
++, gfn
++, start
++) {
2827 mmu_set_spte(vcpu
, start
, access
, false, sp
->role
.level
, gfn
,
2828 page_to_pfn(pages
[i
]), true, true);
2835 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2836 struct kvm_mmu_page
*sp
, u64
*sptep
)
2838 u64
*spte
, *start
= NULL
;
2841 WARN_ON(!sp
->role
.direct
);
2843 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2846 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2847 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2850 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2858 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2860 struct kvm_mmu_page
*sp
;
2862 sp
= sptep_to_sp(sptep
);
2865 * Without accessed bits, there's no way to distinguish between
2866 * actually accessed translations and prefetched, so disable pte
2867 * prefetch if accessed bits aren't available.
2869 if (sp_ad_disabled(sp
))
2872 if (sp
->role
.level
> PG_LEVEL_4K
)
2876 * If addresses are being invalidated, skip prefetching to avoid
2877 * accidentally prefetching those addresses.
2879 if (unlikely(vcpu
->kvm
->mmu_notifier_count
))
2882 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2885 static int host_pfn_mapping_level(struct kvm
*kvm
, gfn_t gfn
, kvm_pfn_t pfn
,
2886 const struct kvm_memory_slot
*slot
)
2892 if (!PageCompound(pfn_to_page(pfn
)) && !kvm_is_zone_device_pfn(pfn
))
2896 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2897 * is not solely for performance, it's also necessary to avoid the
2898 * "writable" check in __gfn_to_hva_many(), which will always fail on
2899 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2900 * page fault steps have already verified the guest isn't writing a
2901 * read-only memslot.
2903 hva
= __gfn_to_hva_memslot(slot
, gfn
);
2905 pte
= lookup_address_in_mm(kvm
->mm
, hva
, &level
);
2912 int kvm_mmu_max_mapping_level(struct kvm
*kvm
,
2913 const struct kvm_memory_slot
*slot
, gfn_t gfn
,
2914 kvm_pfn_t pfn
, int max_level
)
2916 struct kvm_lpage_info
*linfo
;
2918 max_level
= min(max_level
, max_huge_page_level
);
2919 for ( ; max_level
> PG_LEVEL_4K
; max_level
--) {
2920 linfo
= lpage_info_slot(gfn
, slot
, max_level
);
2921 if (!linfo
->disallow_lpage
)
2925 if (max_level
== PG_LEVEL_4K
)
2928 return host_pfn_mapping_level(kvm
, gfn
, pfn
, slot
);
2931 int kvm_mmu_hugepage_adjust(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2932 int max_level
, kvm_pfn_t
*pfnp
,
2933 bool huge_page_disallowed
, int *req_level
)
2935 struct kvm_memory_slot
*slot
;
2936 kvm_pfn_t pfn
= *pfnp
;
2940 *req_level
= PG_LEVEL_4K
;
2942 if (unlikely(max_level
== PG_LEVEL_4K
))
2945 if (is_error_noslot_pfn(pfn
) || kvm_is_reserved_pfn(pfn
))
2948 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, true);
2952 level
= kvm_mmu_max_mapping_level(vcpu
->kvm
, slot
, gfn
, pfn
, max_level
);
2953 if (level
== PG_LEVEL_4K
)
2956 *req_level
= level
= min(level
, max_level
);
2959 * Enforce the iTLB multihit workaround after capturing the requested
2960 * level, which will be used to do precise, accurate accounting.
2962 if (huge_page_disallowed
)
2966 * mmu_notifier_retry() was successful and mmu_lock is held, so
2967 * the pmd can't be split from under us.
2969 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2970 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2971 *pfnp
= pfn
& ~mask
;
2976 void disallowed_hugepage_adjust(u64 spte
, gfn_t gfn
, int cur_level
,
2977 kvm_pfn_t
*pfnp
, int *goal_levelp
)
2979 int level
= *goal_levelp
;
2981 if (cur_level
== level
&& level
> PG_LEVEL_4K
&&
2982 is_shadow_present_pte(spte
) &&
2983 !is_large_pte(spte
)) {
2985 * A small SPTE exists for this pfn, but FNAME(fetch)
2986 * and __direct_map would like to create a large PTE
2987 * instead: just force them to go down another level,
2988 * patching back for them into pfn the next 9 bits of
2991 u64 page_mask
= KVM_PAGES_PER_HPAGE(level
) -
2992 KVM_PAGES_PER_HPAGE(level
- 1);
2993 *pfnp
|= gfn
& page_mask
;
2998 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
2999 int map_writable
, int max_level
, kvm_pfn_t pfn
,
3000 bool prefault
, bool is_tdp
)
3002 bool nx_huge_page_workaround_enabled
= is_nx_huge_page_enabled();
3003 bool write
= error_code
& PFERR_WRITE_MASK
;
3004 bool exec
= error_code
& PFERR_FETCH_MASK
;
3005 bool huge_page_disallowed
= exec
&& nx_huge_page_workaround_enabled
;
3006 struct kvm_shadow_walk_iterator it
;
3007 struct kvm_mmu_page
*sp
;
3008 int level
, req_level
, ret
;
3009 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3010 gfn_t base_gfn
= gfn
;
3012 level
= kvm_mmu_hugepage_adjust(vcpu
, gfn
, max_level
, &pfn
,
3013 huge_page_disallowed
, &req_level
);
3015 trace_kvm_mmu_spte_requested(gpa
, level
, pfn
);
3016 for_each_shadow_entry(vcpu
, gpa
, it
) {
3018 * We cannot overwrite existing page tables with an NX
3019 * large page, as the leaf could be executable.
3021 if (nx_huge_page_workaround_enabled
)
3022 disallowed_hugepage_adjust(*it
.sptep
, gfn
, it
.level
,
3025 base_gfn
= gfn
& ~(KVM_PAGES_PER_HPAGE(it
.level
) - 1);
3026 if (it
.level
== level
)
3029 drop_large_spte(vcpu
, it
.sptep
);
3030 if (is_shadow_present_pte(*it
.sptep
))
3033 sp
= kvm_mmu_get_page(vcpu
, base_gfn
, it
.addr
,
3034 it
.level
- 1, true, ACC_ALL
);
3036 link_shadow_page(vcpu
, it
.sptep
, sp
);
3037 if (is_tdp
&& huge_page_disallowed
&&
3038 req_level
>= it
.level
)
3039 account_huge_nx_page(vcpu
->kvm
, sp
);
3042 ret
= mmu_set_spte(vcpu
, it
.sptep
, ACC_ALL
,
3043 write
, level
, base_gfn
, pfn
, prefault
,
3045 if (ret
== RET_PF_SPURIOUS
)
3048 direct_pte_prefetch(vcpu
, it
.sptep
);
3049 ++vcpu
->stat
.pf_fixed
;
3053 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
3055 send_sig_mceerr(BUS_MCEERR_AR
, (void __user
*)address
, PAGE_SHIFT
, tsk
);
3058 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
3061 * Do not cache the mmio info caused by writing the readonly gfn
3062 * into the spte otherwise read access on readonly gfn also can
3063 * caused mmio page fault and treat it as mmio access.
3065 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3066 return RET_PF_EMULATE
;
3068 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3069 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3070 return RET_PF_RETRY
;
3076 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3077 kvm_pfn_t pfn
, unsigned int access
,
3080 /* The pfn is invalid, report the error! */
3081 if (unlikely(is_error_pfn(pfn
))) {
3082 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3086 if (unlikely(is_noslot_pfn(pfn
))) {
3087 vcpu_cache_mmio_info(vcpu
, gva
, gfn
,
3088 access
& shadow_mmio_access_mask
);
3090 * If MMIO caching is disabled, emulate immediately without
3091 * touching the shadow page tables as attempting to install an
3092 * MMIO SPTE will just be an expensive nop.
3094 if (unlikely(!shadow_mmio_value
)) {
3095 *ret_val
= RET_PF_EMULATE
;
3103 static bool page_fault_can_be_fast(u32 error_code
)
3106 * Do not fix the mmio spte with invalid generation number which
3107 * need to be updated by slow page fault path.
3109 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3112 /* See if the page fault is due to an NX violation */
3113 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3114 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3118 * #PF can be fast if:
3119 * 1. The shadow page table entry is not present, which could mean that
3120 * the fault is potentially caused by access tracking (if enabled).
3121 * 2. The shadow page table entry is present and the fault
3122 * is caused by write-protect, that means we just need change the W
3123 * bit of the spte which can be done out of mmu-lock.
3125 * However, if access tracking is disabled we know that a non-present
3126 * page must be a genuine page fault where we have to create a new SPTE.
3127 * So, if access tracking is disabled, we return true only for write
3128 * accesses to a present page.
3131 return shadow_acc_track_mask
!= 0 ||
3132 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3133 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3137 * Returns true if the SPTE was fixed successfully. Otherwise,
3138 * someone else modified the SPTE from its original value.
3141 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3142 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3146 WARN_ON(!sp
->role
.direct
);
3149 * Theoretically we could also set dirty bit (and flush TLB) here in
3150 * order to eliminate unnecessary PML logging. See comments in
3151 * set_spte. But fast_page_fault is very unlikely to happen with PML
3152 * enabled, so we do not do this. This might result in the same GPA
3153 * to be logged in PML buffer again when the write really happens, and
3154 * eventually to be called by mark_page_dirty twice. But it's also no
3155 * harm. This also avoids the TLB flush needed after setting dirty bit
3156 * so non-PML cases won't be impacted.
3158 * Compare with set_spte where instead shadow_dirty_mask is set.
3160 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3163 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3165 * The gfn of direct spte is stable since it is
3166 * calculated by sp->gfn.
3168 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3169 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3175 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3177 if (fault_err_code
& PFERR_FETCH_MASK
)
3178 return is_executable_pte(spte
);
3180 if (fault_err_code
& PFERR_WRITE_MASK
)
3181 return is_writable_pte(spte
);
3183 /* Fault was on Read access */
3184 return spte
& PT_PRESENT_MASK
;
3188 * Returns the last level spte pointer of the shadow page walk for the given
3189 * gpa, and sets *spte to the spte value. This spte may be non-preset. If no
3190 * walk could be performed, returns NULL and *spte does not contain valid data.
3193 * - Must be called between walk_shadow_page_lockless_{begin,end}.
3194 * - The returned sptep must not be used after walk_shadow_page_lockless_end.
3196 static u64
*fast_pf_get_last_sptep(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u64
*spte
)
3198 struct kvm_shadow_walk_iterator iterator
;
3202 for_each_shadow_entry_lockless(vcpu
, gpa
, iterator
, old_spte
) {
3203 sptep
= iterator
.sptep
;
3206 if (!is_shadow_present_pte(old_spte
))
3214 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3216 static int fast_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
)
3218 struct kvm_mmu_page
*sp
;
3219 int ret
= RET_PF_INVALID
;
3222 uint retry_count
= 0;
3224 if (!page_fault_can_be_fast(error_code
))
3227 walk_shadow_page_lockless_begin(vcpu
);
3232 if (is_tdp_mmu(vcpu
->arch
.mmu
))
3233 sptep
= kvm_tdp_mmu_fast_pf_get_last_sptep(vcpu
, gpa
, &spte
);
3235 sptep
= fast_pf_get_last_sptep(vcpu
, gpa
, &spte
);
3237 if (!is_shadow_present_pte(spte
))
3240 sp
= sptep_to_sp(sptep
);
3241 if (!is_last_spte(spte
, sp
->role
.level
))
3245 * Check whether the memory access that caused the fault would
3246 * still cause it if it were to be performed right now. If not,
3247 * then this is a spurious fault caused by TLB lazily flushed,
3248 * or some other CPU has already fixed the PTE after the
3249 * current CPU took the fault.
3251 * Need not check the access of upper level table entries since
3252 * they are always ACC_ALL.
3254 if (is_access_allowed(error_code
, spte
)) {
3255 ret
= RET_PF_SPURIOUS
;
3261 if (is_access_track_spte(spte
))
3262 new_spte
= restore_acc_track_spte(new_spte
);
3265 * Currently, to simplify the code, write-protection can
3266 * be removed in the fast path only if the SPTE was
3267 * write-protected for dirty-logging or access tracking.
3269 if ((error_code
& PFERR_WRITE_MASK
) &&
3270 spte_can_locklessly_be_made_writable(spte
)) {
3271 new_spte
|= PT_WRITABLE_MASK
;
3274 * Do not fix write-permission on the large spte. Since
3275 * we only dirty the first page into the dirty-bitmap in
3276 * fast_pf_fix_direct_spte(), other pages are missed
3277 * if its slot has dirty logging enabled.
3279 * Instead, we let the slow page fault path create a
3280 * normal spte to fix the access.
3282 * See the comments in kvm_arch_commit_memory_region().
3284 if (sp
->role
.level
> PG_LEVEL_4K
)
3288 /* Verify that the fault can be handled in the fast path */
3289 if (new_spte
== spte
||
3290 !is_access_allowed(error_code
, new_spte
))
3294 * Currently, fast page fault only works for direct mapping
3295 * since the gfn is not stable for indirect shadow page. See
3296 * Documentation/virt/kvm/locking.rst to get more detail.
3298 if (fast_pf_fix_direct_spte(vcpu
, sp
, sptep
, spte
, new_spte
)) {
3303 if (++retry_count
> 4) {
3304 printk_once(KERN_WARNING
3305 "kvm: Fast #PF retrying more than 4 times.\n");
3311 trace_fast_page_fault(vcpu
, gpa
, error_code
, sptep
, spte
, ret
);
3312 walk_shadow_page_lockless_end(vcpu
);
3317 static void mmu_free_root_page(struct kvm
*kvm
, hpa_t
*root_hpa
,
3318 struct list_head
*invalid_list
)
3320 struct kvm_mmu_page
*sp
;
3322 if (!VALID_PAGE(*root_hpa
))
3325 sp
= to_shadow_page(*root_hpa
& PT64_BASE_ADDR_MASK
);
3327 if (is_tdp_mmu_page(sp
))
3328 kvm_tdp_mmu_put_root(kvm
, sp
, false);
3329 else if (!--sp
->root_count
&& sp
->role
.invalid
)
3330 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
3332 *root_hpa
= INVALID_PAGE
;
3335 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3336 void kvm_mmu_free_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3337 ulong roots_to_free
)
3339 struct kvm
*kvm
= vcpu
->kvm
;
3341 LIST_HEAD(invalid_list
);
3342 bool free_active_root
= roots_to_free
& KVM_MMU_ROOT_CURRENT
;
3344 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS
>= BITS_PER_LONG
);
3346 /* Before acquiring the MMU lock, see if we need to do any real work. */
3347 if (!(free_active_root
&& VALID_PAGE(mmu
->root_hpa
))) {
3348 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3349 if ((roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
)) &&
3350 VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
3353 if (i
== KVM_MMU_NUM_PREV_ROOTS
)
3357 write_lock(&kvm
->mmu_lock
);
3359 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
3360 if (roots_to_free
& KVM_MMU_ROOT_PREVIOUS(i
))
3361 mmu_free_root_page(kvm
, &mmu
->prev_roots
[i
].hpa
,
3364 if (free_active_root
) {
3365 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3366 (mmu
->root_level
>= PT64_ROOT_4LEVEL
|| mmu
->direct_map
)) {
3367 mmu_free_root_page(kvm
, &mmu
->root_hpa
, &invalid_list
);
3368 } else if (mmu
->pae_root
) {
3369 for (i
= 0; i
< 4; ++i
) {
3370 if (!IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]))
3373 mmu_free_root_page(kvm
, &mmu
->pae_root
[i
],
3375 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3378 mmu
->root_hpa
= INVALID_PAGE
;
3382 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3383 write_unlock(&kvm
->mmu_lock
);
3385 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots
);
3387 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3389 unsigned long roots_to_free
= 0;
3394 * This should not be called while L2 is active, L2 can't invalidate
3395 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3397 WARN_ON_ONCE(mmu
->mmu_role
.base
.guest_mode
);
3399 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
3400 root_hpa
= mmu
->prev_roots
[i
].hpa
;
3401 if (!VALID_PAGE(root_hpa
))
3404 if (!to_shadow_page(root_hpa
) ||
3405 to_shadow_page(root_hpa
)->role
.guest_mode
)
3406 roots_to_free
|= KVM_MMU_ROOT_PREVIOUS(i
);
3409 kvm_mmu_free_roots(vcpu
, mmu
, roots_to_free
);
3411 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots
);
3414 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3418 if (!kvm_vcpu_is_visible_gfn(vcpu
, root_gfn
)) {
3419 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3426 static hpa_t
mmu_alloc_root(struct kvm_vcpu
*vcpu
, gfn_t gfn
, gva_t gva
,
3427 u8 level
, bool direct
)
3429 struct kvm_mmu_page
*sp
;
3431 sp
= kvm_mmu_get_page(vcpu
, gfn
, gva
, level
, direct
, ACC_ALL
);
3434 return __pa(sp
->spt
);
3437 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3439 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3440 u8 shadow_root_level
= mmu
->shadow_root_level
;
3445 write_lock(&vcpu
->kvm
->mmu_lock
);
3446 r
= make_mmu_pages_available(vcpu
);
3450 if (is_tdp_mmu_enabled(vcpu
->kvm
)) {
3451 root
= kvm_tdp_mmu_get_vcpu_root_hpa(vcpu
);
3452 mmu
->root_hpa
= root
;
3453 } else if (shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3454 root
= mmu_alloc_root(vcpu
, 0, 0, shadow_root_level
, true);
3455 mmu
->root_hpa
= root
;
3456 } else if (shadow_root_level
== PT32E_ROOT_LEVEL
) {
3457 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3462 for (i
= 0; i
< 4; ++i
) {
3463 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3465 root
= mmu_alloc_root(vcpu
, i
<< (30 - PAGE_SHIFT
),
3466 i
<< 30, PT32_ROOT_LEVEL
, true);
3467 mmu
->pae_root
[i
] = root
| PT_PRESENT_MASK
|
3470 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3472 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level
);
3477 /* root_pgd is ignored for direct MMUs. */
3480 write_unlock(&vcpu
->kvm
->mmu_lock
);
3484 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3486 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3487 u64 pdptrs
[4], pm_mask
;
3488 gfn_t root_gfn
, root_pgd
;
3493 root_pgd
= mmu
->get_guest_pgd(vcpu
);
3494 root_gfn
= root_pgd
>> PAGE_SHIFT
;
3496 if (mmu_check_root(vcpu
, root_gfn
))
3500 * On SVM, reading PDPTRs might access guest memory, which might fault
3501 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3503 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3504 for (i
= 0; i
< 4; ++i
) {
3505 pdptrs
[i
] = mmu
->get_pdptr(vcpu
, i
);
3506 if (!(pdptrs
[i
] & PT_PRESENT_MASK
))
3509 if (mmu_check_root(vcpu
, pdptrs
[i
] >> PAGE_SHIFT
))
3514 r
= alloc_all_memslots_rmaps(vcpu
->kvm
);
3518 write_lock(&vcpu
->kvm
->mmu_lock
);
3519 r
= make_mmu_pages_available(vcpu
);
3524 * Do we shadow a long mode page table? If so we need to
3525 * write-protect the guests page table root.
3527 if (mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3528 root
= mmu_alloc_root(vcpu
, root_gfn
, 0,
3529 mmu
->shadow_root_level
, false);
3530 mmu
->root_hpa
= root
;
3534 if (WARN_ON_ONCE(!mmu
->pae_root
)) {
3540 * We shadow a 32 bit page table. This may be a legacy 2-level
3541 * or a PAE 3-level page table. In either case we need to be aware that
3542 * the shadow page table may be a PAE or a long mode page table.
3544 pm_mask
= PT_PRESENT_MASK
| shadow_me_mask
;
3545 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
) {
3546 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3548 if (WARN_ON_ONCE(!mmu
->pml4_root
)) {
3553 mmu
->pml4_root
[0] = __pa(mmu
->pae_root
) | pm_mask
;
3556 for (i
= 0; i
< 4; ++i
) {
3557 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu
->pae_root
[i
]));
3559 if (mmu
->root_level
== PT32E_ROOT_LEVEL
) {
3560 if (!(pdptrs
[i
] & PT_PRESENT_MASK
)) {
3561 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
3564 root_gfn
= pdptrs
[i
] >> PAGE_SHIFT
;
3567 root
= mmu_alloc_root(vcpu
, root_gfn
, i
<< 30,
3568 PT32_ROOT_LEVEL
, false);
3569 mmu
->pae_root
[i
] = root
| pm_mask
;
3572 if (mmu
->shadow_root_level
== PT64_ROOT_4LEVEL
)
3573 mmu
->root_hpa
= __pa(mmu
->pml4_root
);
3575 mmu
->root_hpa
= __pa(mmu
->pae_root
);
3578 mmu
->root_pgd
= root_pgd
;
3580 write_unlock(&vcpu
->kvm
->mmu_lock
);
3585 static int mmu_alloc_special_roots(struct kvm_vcpu
*vcpu
)
3587 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
3588 u64
*pml4_root
, *pae_root
;
3591 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3592 * tables are allocated and initialized at root creation as there is no
3593 * equivalent level in the guest's NPT to shadow. Allocate the tables
3594 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3596 if (mmu
->direct_map
|| mmu
->root_level
>= PT64_ROOT_4LEVEL
||
3597 mmu
->shadow_root_level
< PT64_ROOT_4LEVEL
)
3601 * This mess only works with 4-level paging and needs to be updated to
3602 * work with 5-level paging.
3604 if (WARN_ON_ONCE(mmu
->shadow_root_level
!= PT64_ROOT_4LEVEL
))
3607 if (mmu
->pae_root
&& mmu
->pml4_root
)
3611 * The special roots should always be allocated in concert. Yell and
3612 * bail if KVM ends up in a state where only one of the roots is valid.
3614 if (WARN_ON_ONCE(!tdp_enabled
|| mmu
->pae_root
|| mmu
->pml4_root
))
3618 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3619 * doesn't need to be decrypted.
3621 pae_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3625 pml4_root
= (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT
);
3627 free_page((unsigned long)pae_root
);
3631 mmu
->pae_root
= pae_root
;
3632 mmu
->pml4_root
= pml4_root
;
3637 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3640 struct kvm_mmu_page
*sp
;
3642 if (vcpu
->arch
.mmu
->direct_map
)
3645 if (!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
))
3648 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3650 if (vcpu
->arch
.mmu
->root_level
>= PT64_ROOT_4LEVEL
) {
3651 hpa_t root
= vcpu
->arch
.mmu
->root_hpa
;
3652 sp
= to_shadow_page(root
);
3655 * Even if another CPU was marking the SP as unsync-ed
3656 * simultaneously, any guest page table changes are not
3657 * guaranteed to be visible anyway until this VCPU issues a TLB
3658 * flush strictly after those changes are made. We only need to
3659 * ensure that the other CPU sets these flags before any actual
3660 * changes to the page tables are made. The comments in
3661 * mmu_try_to_unsync_pages() describe what could go wrong if
3662 * this requirement isn't satisfied.
3664 if (!smp_load_acquire(&sp
->unsync
) &&
3665 !smp_load_acquire(&sp
->unsync_children
))
3668 write_lock(&vcpu
->kvm
->mmu_lock
);
3669 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3671 mmu_sync_children(vcpu
, sp
);
3673 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3674 write_unlock(&vcpu
->kvm
->mmu_lock
);
3678 write_lock(&vcpu
->kvm
->mmu_lock
);
3679 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3681 for (i
= 0; i
< 4; ++i
) {
3682 hpa_t root
= vcpu
->arch
.mmu
->pae_root
[i
];
3684 if (IS_VALID_PAE_ROOT(root
)) {
3685 root
&= PT64_BASE_ADDR_MASK
;
3686 sp
= to_shadow_page(root
);
3687 mmu_sync_children(vcpu
, sp
);
3691 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3692 write_unlock(&vcpu
->kvm
->mmu_lock
);
3695 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3696 u32 access
, struct x86_exception
*exception
)
3699 exception
->error_code
= 0;
3703 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gpa_t vaddr
,
3705 struct x86_exception
*exception
)
3708 exception
->error_code
= 0;
3709 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3712 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3715 * A nested guest cannot use the MMIO cache if it is using nested
3716 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3718 if (mmu_is_nested(vcpu
))
3722 return vcpu_match_mmio_gpa(vcpu
, addr
);
3724 return vcpu_match_mmio_gva(vcpu
, addr
);
3728 * Return the level of the lowest level SPTE added to sptes.
3729 * That SPTE may be non-present.
3731 * Must be called between walk_shadow_page_lockless_{begin,end}.
3733 static int get_walk(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptes
, int *root_level
)
3735 struct kvm_shadow_walk_iterator iterator
;
3739 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3740 *root_level
= iterator
.level
;
3741 shadow_walk_okay(&iterator
);
3742 __shadow_walk_next(&iterator
, spte
)) {
3743 leaf
= iterator
.level
;
3744 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3748 if (!is_shadow_present_pte(spte
))
3755 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3756 static bool get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3758 u64 sptes
[PT64_ROOT_MAX_LEVEL
+ 1];
3759 struct rsvd_bits_validate
*rsvd_check
;
3760 int root
, leaf
, level
;
3761 bool reserved
= false;
3763 walk_shadow_page_lockless_begin(vcpu
);
3765 if (is_tdp_mmu(vcpu
->arch
.mmu
))
3766 leaf
= kvm_tdp_mmu_get_walk(vcpu
, addr
, sptes
, &root
);
3768 leaf
= get_walk(vcpu
, addr
, sptes
, &root
);
3770 walk_shadow_page_lockless_end(vcpu
);
3772 if (unlikely(leaf
< 0)) {
3777 *sptep
= sptes
[leaf
];
3780 * Skip reserved bits checks on the terminal leaf if it's not a valid
3781 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3782 * design, always have reserved bits set. The purpose of the checks is
3783 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3785 if (!is_shadow_present_pte(sptes
[leaf
]))
3788 rsvd_check
= &vcpu
->arch
.mmu
->shadow_zero_check
;
3790 for (level
= root
; level
>= leaf
; level
--)
3791 reserved
|= is_rsvd_spte(rsvd_check
, sptes
[level
], level
);
3794 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3796 for (level
= root
; level
>= leaf
; level
--)
3797 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3798 sptes
[level
], level
,
3799 get_rsvd_bits(rsvd_check
, sptes
[level
], level
));
3805 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3810 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3811 return RET_PF_EMULATE
;
3813 reserved
= get_mmio_spte(vcpu
, addr
, &spte
);
3814 if (WARN_ON(reserved
))
3817 if (is_mmio_spte(spte
)) {
3818 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3819 unsigned int access
= get_mmio_spte_access(spte
);
3821 if (!check_mmio_spte(vcpu
, spte
))
3822 return RET_PF_INVALID
;
3827 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3828 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3829 return RET_PF_EMULATE
;
3833 * If the page table is zapped by other cpus, let CPU fault again on
3836 return RET_PF_RETRY
;
3839 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3840 u32 error_code
, gfn_t gfn
)
3842 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3845 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3846 !(error_code
& PFERR_WRITE_MASK
))
3850 * guest is writing the page which is write tracked which can
3851 * not be fixed by page fault handler.
3853 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3859 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3861 struct kvm_shadow_walk_iterator iterator
;
3864 walk_shadow_page_lockless_begin(vcpu
);
3865 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3866 clear_sp_write_flooding_count(iterator
.sptep
);
3867 if (!is_shadow_present_pte(spte
))
3870 walk_shadow_page_lockless_end(vcpu
);
3873 static bool kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
,
3876 struct kvm_arch_async_pf arch
;
3878 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3880 arch
.direct_map
= vcpu
->arch
.mmu
->direct_map
;
3881 arch
.cr3
= vcpu
->arch
.mmu
->get_guest_pgd(vcpu
);
3883 return kvm_setup_async_pf(vcpu
, cr2_or_gpa
,
3884 kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3887 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3888 gpa_t cr2_or_gpa
, kvm_pfn_t
*pfn
, hva_t
*hva
,
3889 bool write
, bool *writable
)
3891 struct kvm_memory_slot
*slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3895 * Retry the page fault if the gfn hit a memslot that is being deleted
3896 * or moved. This ensures any existing SPTEs for the old memslot will
3897 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3899 if (slot
&& (slot
->flags
& KVM_MEMSLOT_INVALID
))
3902 /* Don't expose private memslots to L2. */
3903 if (is_guest_mode(vcpu
) && !kvm_is_visible_memslot(slot
)) {
3904 *pfn
= KVM_PFN_NOSLOT
;
3910 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
,
3911 write
, writable
, hva
);
3913 return false; /* *pfn has correct page already */
3915 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3916 trace_kvm_try_async_get_page(cr2_or_gpa
, gfn
);
3917 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3918 trace_kvm_async_pf_doublefault(cr2_or_gpa
, gfn
);
3919 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3921 } else if (kvm_arch_setup_async_pf(vcpu
, cr2_or_gpa
, gfn
))
3925 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
,
3926 write
, writable
, hva
);
3930 static int direct_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
3931 bool prefault
, int max_level
, bool is_tdp
)
3933 bool is_tdp_mmu_fault
= is_tdp_mmu(vcpu
->arch
.mmu
);
3934 bool write
= error_code
& PFERR_WRITE_MASK
;
3937 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3938 unsigned long mmu_seq
;
3943 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3944 return RET_PF_EMULATE
;
3946 r
= fast_page_fault(vcpu
, gpa
, error_code
);
3947 if (r
!= RET_PF_INVALID
)
3950 r
= mmu_topup_memory_caches(vcpu
, false);
3954 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3957 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, &hva
,
3958 write
, &map_writable
))
3959 return RET_PF_RETRY
;
3961 if (handle_abnormal_pfn(vcpu
, is_tdp
? 0 : gpa
, gfn
, pfn
, ACC_ALL
, &r
))
3966 if (is_tdp_mmu_fault
)
3967 read_lock(&vcpu
->kvm
->mmu_lock
);
3969 write_lock(&vcpu
->kvm
->mmu_lock
);
3971 if (!is_noslot_pfn(pfn
) && mmu_notifier_retry_hva(vcpu
->kvm
, mmu_seq
, hva
))
3973 r
= make_mmu_pages_available(vcpu
);
3977 if (is_tdp_mmu_fault
)
3978 r
= kvm_tdp_mmu_map(vcpu
, gpa
, error_code
, map_writable
, max_level
,
3981 r
= __direct_map(vcpu
, gpa
, error_code
, map_writable
, max_level
, pfn
,
3985 if (is_tdp_mmu_fault
)
3986 read_unlock(&vcpu
->kvm
->mmu_lock
);
3988 write_unlock(&vcpu
->kvm
->mmu_lock
);
3989 kvm_release_pfn_clean(pfn
);
3993 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3994 u32 error_code
, bool prefault
)
3996 pgprintk("%s: gva %lx error %x\n", __func__
, gpa
, error_code
);
3998 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3999 return direct_page_fault(vcpu
, gpa
& PAGE_MASK
, error_code
, prefault
,
4000 PG_LEVEL_2M
, false);
4003 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
4004 u64 fault_address
, char *insn
, int insn_len
)
4007 u32 flags
= vcpu
->arch
.apf
.host_apf_flags
;
4009 #ifndef CONFIG_X86_64
4010 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
4011 if (WARN_ON_ONCE(fault_address
>> 32))
4015 vcpu
->arch
.l1tf_flush_l1d
= true;
4017 trace_kvm_page_fault(fault_address
, error_code
);
4019 if (kvm_event_needs_reinjection(vcpu
))
4020 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
4021 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
4023 } else if (flags
& KVM_PV_REASON_PAGE_NOT_PRESENT
) {
4024 vcpu
->arch
.apf
.host_apf_flags
= 0;
4025 local_irq_disable();
4026 kvm_async_pf_task_wait_schedule(fault_address
);
4029 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags
);
4034 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
4036 int kvm_tdp_page_fault(struct kvm_vcpu
*vcpu
, gpa_t gpa
, u32 error_code
,
4041 for (max_level
= KVM_MAX_HUGEPAGE_LEVEL
;
4042 max_level
> PG_LEVEL_4K
;
4044 int page_num
= KVM_PAGES_PER_HPAGE(max_level
);
4045 gfn_t base
= (gpa
>> PAGE_SHIFT
) & ~(page_num
- 1);
4047 if (kvm_mtrr_check_gfn_range_consistency(vcpu
, base
, page_num
))
4051 return direct_page_fault(vcpu
, gpa
, error_code
, prefault
,
4055 static void nonpaging_init_context(struct kvm_mmu
*context
)
4057 context
->page_fault
= nonpaging_page_fault
;
4058 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4059 context
->sync_page
= nonpaging_sync_page
;
4060 context
->invlpg
= NULL
;
4061 context
->direct_map
= true;
4064 static inline bool is_root_usable(struct kvm_mmu_root_info
*root
, gpa_t pgd
,
4065 union kvm_mmu_page_role role
)
4067 return (role
.direct
|| pgd
== root
->pgd
) &&
4068 VALID_PAGE(root
->hpa
) && to_shadow_page(root
->hpa
) &&
4069 role
.word
== to_shadow_page(root
->hpa
)->role
.word
;
4073 * Find out if a previously cached root matching the new pgd/role is available.
4074 * The current root is also inserted into the cache.
4075 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4077 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4078 * false is returned. This root should now be freed by the caller.
4080 static bool cached_root_available(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4081 union kvm_mmu_page_role new_role
)
4084 struct kvm_mmu_root_info root
;
4085 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4087 root
.pgd
= mmu
->root_pgd
;
4088 root
.hpa
= mmu
->root_hpa
;
4090 if (is_root_usable(&root
, new_pgd
, new_role
))
4093 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
4094 swap(root
, mmu
->prev_roots
[i
]);
4096 if (is_root_usable(&root
, new_pgd
, new_role
))
4100 mmu
->root_hpa
= root
.hpa
;
4101 mmu
->root_pgd
= root
.pgd
;
4103 return i
< KVM_MMU_NUM_PREV_ROOTS
;
4106 static bool fast_pgd_switch(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4107 union kvm_mmu_page_role new_role
)
4109 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
4112 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4113 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4114 * later if necessary.
4116 if (mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
&&
4117 mmu
->root_level
>= PT64_ROOT_4LEVEL
)
4118 return cached_root_available(vcpu
, new_pgd
, new_role
);
4123 static void __kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
,
4124 union kvm_mmu_page_role new_role
)
4126 if (!fast_pgd_switch(vcpu
, new_pgd
, new_role
)) {
4127 kvm_mmu_free_roots(vcpu
, vcpu
->arch
.mmu
, KVM_MMU_ROOT_CURRENT
);
4132 * It's possible that the cached previous root page is obsolete because
4133 * of a change in the MMU generation number. However, changing the
4134 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4135 * free the root set here and allocate a new one.
4137 kvm_make_request(KVM_REQ_LOAD_MMU_PGD
, vcpu
);
4139 if (force_flush_and_sync_on_reuse
) {
4140 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
4141 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
4145 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4146 * switching to a new CR3, that GVA->GPA mapping may no longer be
4147 * valid. So clear any cached MMIO info even when we don't need to sync
4148 * the shadow page tables.
4150 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
4153 * If this is a direct root page, it doesn't have a write flooding
4154 * count. Otherwise, clear the write flooding count.
4156 if (!new_role
.direct
)
4157 __clear_sp_write_flooding_count(
4158 to_shadow_page(vcpu
->arch
.mmu
->root_hpa
));
4161 void kvm_mmu_new_pgd(struct kvm_vcpu
*vcpu
, gpa_t new_pgd
)
4163 __kvm_mmu_new_pgd(vcpu
, new_pgd
, kvm_mmu_calc_root_page_role(vcpu
));
4165 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd
);
4167 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
4169 return kvm_read_cr3(vcpu
);
4172 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
4173 unsigned int access
, int *nr_present
)
4175 if (unlikely(is_mmio_spte(*sptep
))) {
4176 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
4177 mmu_spte_clear_no_track(sptep
);
4182 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
4189 #define PTTYPE_EPT 18 /* arbitrary */
4190 #define PTTYPE PTTYPE_EPT
4191 #include "paging_tmpl.h"
4195 #include "paging_tmpl.h"
4199 #include "paging_tmpl.h"
4203 __reset_rsvds_bits_mask(struct rsvd_bits_validate
*rsvd_check
,
4204 u64 pa_bits_rsvd
, int level
, bool nx
, bool gbpages
,
4207 u64 gbpages_bit_rsvd
= 0;
4208 u64 nonleaf_bit8_rsvd
= 0;
4211 rsvd_check
->bad_mt_xwr
= 0;
4214 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4216 if (level
== PT32E_ROOT_LEVEL
)
4217 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 62);
4219 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4221 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4223 high_bits_rsvd
|= rsvd_bits(63, 63);
4226 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4227 * leaf entries) on AMD CPUs only.
4230 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4233 case PT32_ROOT_LEVEL
:
4234 /* no rsvd bits for 2 level 4K page table entries */
4235 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4236 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4237 rsvd_check
->rsvd_bits_mask
[1][0] =
4238 rsvd_check
->rsvd_bits_mask
[0][0];
4241 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4245 if (is_cpuid_PSE36())
4246 /* 36bits PSE 4MB page */
4247 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4249 /* 32 bits PSE 4MB page */
4250 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4252 case PT32E_ROOT_LEVEL
:
4253 rsvd_check
->rsvd_bits_mask
[0][2] = rsvd_bits(63, 63) |
4256 rsvd_bits(1, 2); /* PDPTE */
4257 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
; /* PDE */
4258 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
; /* PTE */
4259 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4260 rsvd_bits(13, 20); /* large page */
4261 rsvd_check
->rsvd_bits_mask
[1][0] =
4262 rsvd_check
->rsvd_bits_mask
[0][0];
4264 case PT64_ROOT_5LEVEL
:
4265 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
|
4268 rsvd_check
->rsvd_bits_mask
[1][4] =
4269 rsvd_check
->rsvd_bits_mask
[0][4];
4271 case PT64_ROOT_4LEVEL
:
4272 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
|
4275 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
|
4277 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
;
4278 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4279 rsvd_check
->rsvd_bits_mask
[1][3] =
4280 rsvd_check
->rsvd_bits_mask
[0][3];
4281 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
|
4284 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
|
4285 rsvd_bits(13, 20); /* large page */
4286 rsvd_check
->rsvd_bits_mask
[1][0] =
4287 rsvd_check
->rsvd_bits_mask
[0][0];
4292 static bool guest_can_use_gbpages(struct kvm_vcpu
*vcpu
)
4295 * If TDP is enabled, let the guest use GBPAGES if they're supported in
4296 * hardware. The hardware page walker doesn't let KVM disable GBPAGES,
4297 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA
4298 * walk for performance and complexity reasons. Not to mention KVM
4299 * _can't_ solve the problem because GVA->GPA walks aren't visible to
4300 * KVM once a TDP translation is installed. Mimic hardware behavior so
4301 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF.
4303 return tdp_enabled
? boot_cpu_has(X86_FEATURE_GBPAGES
) :
4304 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
);
4307 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4308 struct kvm_mmu
*context
)
4310 __reset_rsvds_bits_mask(&context
->guest_rsvd_check
,
4311 vcpu
->arch
.reserved_gpa_bits
,
4312 context
->root_level
, is_efer_nx(context
),
4313 guest_can_use_gbpages(vcpu
),
4314 is_cr4_pse(context
),
4315 guest_cpuid_is_amd_or_hygon(vcpu
));
4319 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4320 u64 pa_bits_rsvd
, bool execonly
)
4322 u64 high_bits_rsvd
= pa_bits_rsvd
& rsvd_bits(0, 51);
4325 rsvd_check
->rsvd_bits_mask
[0][4] = high_bits_rsvd
| rsvd_bits(3, 7);
4326 rsvd_check
->rsvd_bits_mask
[0][3] = high_bits_rsvd
| rsvd_bits(3, 7);
4327 rsvd_check
->rsvd_bits_mask
[0][2] = high_bits_rsvd
| rsvd_bits(3, 6);
4328 rsvd_check
->rsvd_bits_mask
[0][1] = high_bits_rsvd
| rsvd_bits(3, 6);
4329 rsvd_check
->rsvd_bits_mask
[0][0] = high_bits_rsvd
;
4332 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4333 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4334 rsvd_check
->rsvd_bits_mask
[1][2] = high_bits_rsvd
| rsvd_bits(12, 29);
4335 rsvd_check
->rsvd_bits_mask
[1][1] = high_bits_rsvd
| rsvd_bits(12, 20);
4336 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4338 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4339 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4340 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4341 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4342 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4344 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4345 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4347 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4350 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4351 struct kvm_mmu
*context
, bool execonly
)
4353 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4354 vcpu
->arch
.reserved_gpa_bits
, execonly
);
4357 static inline u64
reserved_hpa_bits(void)
4359 return rsvd_bits(shadow_phys_bits
, 63);
4363 * the page table on host is the shadow page table for the page
4364 * table in guest or amd nested guest, its mmu features completely
4365 * follow the features in guest.
4367 static void reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4368 struct kvm_mmu
*context
)
4371 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4372 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4373 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4374 * The iTLB multi-hit workaround can be toggled at any time, so assume
4375 * NX can be used by any non-nested shadow MMU to avoid having to reset
4376 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4378 bool uses_nx
= is_efer_nx(context
) || !tdp_enabled
;
4380 /* @amd adds a check on bit of SPTEs, which KVM shouldn't use anyways. */
4382 /* KVM doesn't use 2-level page tables for the shadow MMU. */
4383 bool is_pse
= false;
4384 struct rsvd_bits_validate
*shadow_zero_check
;
4387 WARN_ON_ONCE(context
->shadow_root_level
< PT32E_ROOT_LEVEL
);
4389 shadow_zero_check
= &context
->shadow_zero_check
;
4390 __reset_rsvds_bits_mask(shadow_zero_check
, reserved_hpa_bits(),
4391 context
->shadow_root_level
, uses_nx
,
4392 guest_can_use_gbpages(vcpu
), is_pse
, is_amd
);
4394 if (!shadow_me_mask
)
4397 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4398 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4399 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4404 static inline bool boot_cpu_is_amd(void)
4406 WARN_ON_ONCE(!tdp_enabled
);
4407 return shadow_x_mask
== 0;
4411 * the direct page table on host, use as much mmu features as
4412 * possible, however, kvm currently does not do execution-protection.
4415 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4416 struct kvm_mmu
*context
)
4418 struct rsvd_bits_validate
*shadow_zero_check
;
4421 shadow_zero_check
= &context
->shadow_zero_check
;
4423 if (boot_cpu_is_amd())
4424 __reset_rsvds_bits_mask(shadow_zero_check
, reserved_hpa_bits(),
4425 context
->shadow_root_level
, false,
4426 boot_cpu_has(X86_FEATURE_GBPAGES
),
4429 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4430 reserved_hpa_bits(), false);
4432 if (!shadow_me_mask
)
4435 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4436 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4437 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4442 * as the comments in reset_shadow_zero_bits_mask() except it
4443 * is the shadow page table for intel nested guest.
4446 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4447 struct kvm_mmu
*context
, bool execonly
)
4449 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4450 reserved_hpa_bits(), execonly
);
4453 #define BYTE_MASK(access) \
4454 ((1 & (access) ? 2 : 0) | \
4455 (2 & (access) ? 4 : 0) | \
4456 (3 & (access) ? 8 : 0) | \
4457 (4 & (access) ? 16 : 0) | \
4458 (5 & (access) ? 32 : 0) | \
4459 (6 & (access) ? 64 : 0) | \
4460 (7 & (access) ? 128 : 0))
4463 static void update_permission_bitmask(struct kvm_mmu
*mmu
, bool ept
)
4467 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4468 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4469 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4471 bool cr4_smep
= is_cr4_smep(mmu
);
4472 bool cr4_smap
= is_cr4_smap(mmu
);
4473 bool cr0_wp
= is_cr0_wp(mmu
);
4474 bool efer_nx
= is_efer_nx(mmu
);
4476 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4477 unsigned pfec
= byte
<< 1;
4480 * Each "*f" variable has a 1 bit for each UWX value
4481 * that causes a fault with the given PFEC.
4484 /* Faults from writes to non-writable pages */
4485 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? (u8
)~w
: 0;
4486 /* Faults from user mode accesses to supervisor pages */
4487 u8 uf
= (pfec
& PFERR_USER_MASK
) ? (u8
)~u
: 0;
4488 /* Faults from fetches of non-executable pages*/
4489 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? (u8
)~x
: 0;
4490 /* Faults from kernel mode fetches of user pages */
4492 /* Faults from kernel mode accesses of user pages */
4496 /* Faults from kernel mode accesses to user pages */
4497 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4499 /* Not really needed: !nx will cause pte.nx to fault */
4503 /* Allow supervisor writes if !cr0.wp */
4505 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4507 /* Disallow supervisor fetches of user code if cr4.smep */
4509 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4512 * SMAP:kernel-mode data accesses from user-mode
4513 * mappings should fault. A fault is considered
4514 * as a SMAP violation if all of the following
4515 * conditions are true:
4516 * - X86_CR4_SMAP is set in CR4
4517 * - A user page is accessed
4518 * - The access is not a fetch
4519 * - Page fault in kernel mode
4520 * - if CPL = 3 or X86_EFLAGS_AC is clear
4522 * Here, we cover the first three conditions.
4523 * The fourth is computed dynamically in permission_fault();
4524 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4525 * *not* subject to SMAP restrictions.
4528 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4531 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4536 * PKU is an additional mechanism by which the paging controls access to
4537 * user-mode addresses based on the value in the PKRU register. Protection
4538 * key violations are reported through a bit in the page fault error code.
4539 * Unlike other bits of the error code, the PK bit is not known at the
4540 * call site of e.g. gva_to_gpa; it must be computed directly in
4541 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4542 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4544 * In particular the following conditions come from the error code, the
4545 * page tables and the machine state:
4546 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4547 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4548 * - PK is always zero if U=0 in the page tables
4549 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4551 * The PKRU bitmask caches the result of these four conditions. The error
4552 * code (minus the P bit) and the page table's U bit form an index into the
4553 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4554 * with the two bits of the PKRU register corresponding to the protection key.
4555 * For the first three conditions above the bits will be 00, thus masking
4556 * away both AD and WD. For all reads or if the last condition holds, WD
4557 * only will be masked away.
4559 static void update_pkru_bitmask(struct kvm_mmu
*mmu
)
4564 if (!is_cr4_pke(mmu
)) {
4569 wp
= is_cr0_wp(mmu
);
4571 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4572 unsigned pfec
, pkey_bits
;
4573 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4576 ff
= pfec
& PFERR_FETCH_MASK
;
4577 uf
= pfec
& PFERR_USER_MASK
;
4578 wf
= pfec
& PFERR_WRITE_MASK
;
4580 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4581 pte_user
= pfec
& PFERR_RSVD_MASK
;
4584 * Only need to check the access which is not an
4585 * instruction fetch and is to a user page.
4587 check_pkey
= (!ff
&& pte_user
);
4589 * write access is controlled by PKRU if it is a
4590 * user access or CR0.WP = 1.
4592 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4594 /* PKRU.AD stops both read and write access. */
4595 pkey_bits
= !!check_pkey
;
4596 /* PKRU.WD stops write access. */
4597 pkey_bits
|= (!!check_write
) << 1;
4599 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4603 static void reset_guest_paging_metadata(struct kvm_vcpu
*vcpu
,
4604 struct kvm_mmu
*mmu
)
4606 if (!is_cr0_pg(mmu
))
4609 reset_rsvds_bits_mask(vcpu
, mmu
);
4610 update_permission_bitmask(mmu
, false);
4611 update_pkru_bitmask(mmu
);
4614 static void paging64_init_context(struct kvm_mmu
*context
)
4616 context
->page_fault
= paging64_page_fault
;
4617 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4618 context
->sync_page
= paging64_sync_page
;
4619 context
->invlpg
= paging64_invlpg
;
4620 context
->direct_map
= false;
4623 static void paging32_init_context(struct kvm_mmu
*context
)
4625 context
->page_fault
= paging32_page_fault
;
4626 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4627 context
->sync_page
= paging32_sync_page
;
4628 context
->invlpg
= paging32_invlpg
;
4629 context
->direct_map
= false;
4632 static union kvm_mmu_extended_role
kvm_calc_mmu_role_ext(struct kvm_vcpu
*vcpu
,
4633 struct kvm_mmu_role_regs
*regs
)
4635 union kvm_mmu_extended_role ext
= {0};
4637 if (____is_cr0_pg(regs
)) {
4639 ext
.cr4_pae
= ____is_cr4_pae(regs
);
4640 ext
.cr4_smep
= ____is_cr4_smep(regs
);
4641 ext
.cr4_smap
= ____is_cr4_smap(regs
);
4642 ext
.cr4_pse
= ____is_cr4_pse(regs
);
4644 /* PKEY and LA57 are active iff long mode is active. */
4645 ext
.cr4_pke
= ____is_efer_lma(regs
) && ____is_cr4_pke(regs
);
4646 ext
.cr4_la57
= ____is_efer_lma(regs
) && ____is_cr4_la57(regs
);
4654 static union kvm_mmu_role
kvm_calc_mmu_role_common(struct kvm_vcpu
*vcpu
,
4655 struct kvm_mmu_role_regs
*regs
,
4658 union kvm_mmu_role role
= {0};
4660 role
.base
.access
= ACC_ALL
;
4661 if (____is_cr0_pg(regs
)) {
4662 role
.base
.efer_nx
= ____is_efer_nx(regs
);
4663 role
.base
.cr0_wp
= ____is_cr0_wp(regs
);
4665 role
.base
.smm
= is_smm(vcpu
);
4666 role
.base
.guest_mode
= is_guest_mode(vcpu
);
4671 role
.ext
= kvm_calc_mmu_role_ext(vcpu
, regs
);
4676 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu
*vcpu
)
4678 /* Use 5-level TDP if and only if it's useful/necessary. */
4679 if (max_tdp_level
== 5 && cpuid_maxphyaddr(vcpu
) <= 48)
4682 return max_tdp_level
;
4685 static union kvm_mmu_role
4686 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu
*vcpu
,
4687 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4689 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, regs
, base_only
);
4691 role
.base
.ad_disabled
= (shadow_accessed_mask
== 0);
4692 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4693 role
.base
.direct
= true;
4694 role
.base
.gpte_is_8_bytes
= true;
4699 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4701 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4702 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4703 union kvm_mmu_role new_role
=
4704 kvm_calc_tdp_mmu_root_page_role(vcpu
, ®s
, false);
4706 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4709 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4710 context
->page_fault
= kvm_tdp_page_fault
;
4711 context
->sync_page
= nonpaging_sync_page
;
4712 context
->invlpg
= NULL
;
4713 context
->shadow_root_level
= kvm_mmu_get_tdp_level(vcpu
);
4714 context
->direct_map
= true;
4715 context
->get_guest_pgd
= get_cr3
;
4716 context
->get_pdptr
= kvm_pdptr_read
;
4717 context
->inject_page_fault
= kvm_inject_page_fault
;
4718 context
->root_level
= role_regs_to_root_level(®s
);
4720 if (!is_cr0_pg(context
))
4721 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4722 else if (is_cr4_pae(context
))
4723 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4725 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4727 reset_guest_paging_metadata(vcpu
, context
);
4728 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4731 static union kvm_mmu_role
4732 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu
*vcpu
,
4733 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4735 union kvm_mmu_role role
= kvm_calc_mmu_role_common(vcpu
, regs
, base_only
);
4737 role
.base
.smep_andnot_wp
= role
.ext
.cr4_smep
&& !____is_cr0_wp(regs
);
4738 role
.base
.smap_andnot_wp
= role
.ext
.cr4_smap
&& !____is_cr0_wp(regs
);
4739 role
.base
.gpte_is_8_bytes
= ____is_cr0_pg(regs
) && ____is_cr4_pae(regs
);
4744 static union kvm_mmu_role
4745 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu
*vcpu
,
4746 struct kvm_mmu_role_regs
*regs
, bool base_only
)
4748 union kvm_mmu_role role
=
4749 kvm_calc_shadow_root_page_role_common(vcpu
, regs
, base_only
);
4751 role
.base
.direct
= !____is_cr0_pg(regs
);
4753 if (!____is_efer_lma(regs
))
4754 role
.base
.level
= PT32E_ROOT_LEVEL
;
4755 else if (____is_cr4_la57(regs
))
4756 role
.base
.level
= PT64_ROOT_5LEVEL
;
4758 role
.base
.level
= PT64_ROOT_4LEVEL
;
4763 static void shadow_mmu_init_context(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
,
4764 struct kvm_mmu_role_regs
*regs
,
4765 union kvm_mmu_role new_role
)
4767 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4770 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4772 if (!is_cr0_pg(context
))
4773 nonpaging_init_context(context
);
4774 else if (is_cr4_pae(context
))
4775 paging64_init_context(context
);
4777 paging32_init_context(context
);
4778 context
->root_level
= role_regs_to_root_level(regs
);
4780 reset_guest_paging_metadata(vcpu
, context
);
4781 context
->shadow_root_level
= new_role
.base
.level
;
4783 reset_shadow_zero_bits_mask(vcpu
, context
);
4786 static void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
,
4787 struct kvm_mmu_role_regs
*regs
)
4789 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4790 union kvm_mmu_role new_role
=
4791 kvm_calc_shadow_mmu_root_page_role(vcpu
, regs
, false);
4793 shadow_mmu_init_context(vcpu
, context
, regs
, new_role
);
4796 static union kvm_mmu_role
4797 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu
*vcpu
,
4798 struct kvm_mmu_role_regs
*regs
)
4800 union kvm_mmu_role role
=
4801 kvm_calc_shadow_root_page_role_common(vcpu
, regs
, false);
4803 role
.base
.direct
= false;
4804 role
.base
.level
= kvm_mmu_get_tdp_level(vcpu
);
4809 void kvm_init_shadow_npt_mmu(struct kvm_vcpu
*vcpu
, unsigned long cr0
,
4810 unsigned long cr4
, u64 efer
, gpa_t nested_cr3
)
4812 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4813 struct kvm_mmu_role_regs regs
= {
4818 union kvm_mmu_role new_role
;
4820 new_role
= kvm_calc_shadow_npt_root_page_role(vcpu
, ®s
);
4822 __kvm_mmu_new_pgd(vcpu
, nested_cr3
, new_role
.base
);
4824 shadow_mmu_init_context(vcpu
, context
, ®s
, new_role
);
4826 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu
);
4828 static union kvm_mmu_role
4829 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu
*vcpu
, bool accessed_dirty
,
4830 bool execonly
, u8 level
)
4832 union kvm_mmu_role role
= {0};
4834 /* SMM flag is inherited from root_mmu */
4835 role
.base
.smm
= vcpu
->arch
.root_mmu
.mmu_role
.base
.smm
;
4837 role
.base
.level
= level
;
4838 role
.base
.gpte_is_8_bytes
= true;
4839 role
.base
.direct
= false;
4840 role
.base
.ad_disabled
= !accessed_dirty
;
4841 role
.base
.guest_mode
= true;
4842 role
.base
.access
= ACC_ALL
;
4844 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4846 role
.ext
.execonly
= execonly
;
4852 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4853 bool accessed_dirty
, gpa_t new_eptp
)
4855 struct kvm_mmu
*context
= &vcpu
->arch
.guest_mmu
;
4856 u8 level
= vmx_eptp_page_walk_level(new_eptp
);
4857 union kvm_mmu_role new_role
=
4858 kvm_calc_shadow_ept_root_page_role(vcpu
, accessed_dirty
,
4861 __kvm_mmu_new_pgd(vcpu
, new_eptp
, new_role
.base
);
4863 if (new_role
.as_u64
== context
->mmu_role
.as_u64
)
4866 context
->mmu_role
.as_u64
= new_role
.as_u64
;
4868 context
->shadow_root_level
= level
;
4870 context
->ept_ad
= accessed_dirty
;
4871 context
->page_fault
= ept_page_fault
;
4872 context
->gva_to_gpa
= ept_gva_to_gpa
;
4873 context
->sync_page
= ept_sync_page
;
4874 context
->invlpg
= ept_invlpg
;
4875 context
->root_level
= level
;
4876 context
->direct_map
= false;
4878 update_permission_bitmask(context
, true);
4879 update_pkru_bitmask(context
);
4880 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4881 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4883 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4885 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4887 struct kvm_mmu
*context
= &vcpu
->arch
.root_mmu
;
4888 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4890 kvm_init_shadow_mmu(vcpu
, ®s
);
4892 context
->get_guest_pgd
= get_cr3
;
4893 context
->get_pdptr
= kvm_pdptr_read
;
4894 context
->inject_page_fault
= kvm_inject_page_fault
;
4897 static union kvm_mmu_role
4898 kvm_calc_nested_mmu_role(struct kvm_vcpu
*vcpu
, struct kvm_mmu_role_regs
*regs
)
4900 union kvm_mmu_role role
;
4902 role
= kvm_calc_shadow_root_page_role_common(vcpu
, regs
, false);
4905 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4906 * shadow pages of their own and so "direct" has no meaning. Set it
4907 * to "true" to try to detect bogus usage of the nested MMU.
4909 role
.base
.direct
= true;
4910 role
.base
.level
= role_regs_to_root_level(regs
);
4914 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4916 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4917 union kvm_mmu_role new_role
= kvm_calc_nested_mmu_role(vcpu
, ®s
);
4918 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4920 if (new_role
.as_u64
== g_context
->mmu_role
.as_u64
)
4923 g_context
->mmu_role
.as_u64
= new_role
.as_u64
;
4924 g_context
->get_guest_pgd
= get_cr3
;
4925 g_context
->get_pdptr
= kvm_pdptr_read
;
4926 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4927 g_context
->root_level
= new_role
.base
.level
;
4930 * L2 page tables are never shadowed, so there is no need to sync
4933 g_context
->invlpg
= NULL
;
4936 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4937 * L1's nested page tables (e.g. EPT12). The nested translation
4938 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4939 * L2's page tables as the first level of translation and L1's
4940 * nested page tables as the second level of translation. Basically
4941 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4943 if (!is_paging(vcpu
))
4944 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4945 else if (is_long_mode(vcpu
))
4946 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4947 else if (is_pae(vcpu
))
4948 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4950 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4952 reset_guest_paging_metadata(vcpu
, g_context
);
4955 void kvm_init_mmu(struct kvm_vcpu
*vcpu
)
4957 if (mmu_is_nested(vcpu
))
4958 init_kvm_nested_mmu(vcpu
);
4959 else if (tdp_enabled
)
4960 init_kvm_tdp_mmu(vcpu
);
4962 init_kvm_softmmu(vcpu
);
4964 EXPORT_SYMBOL_GPL(kvm_init_mmu
);
4966 static union kvm_mmu_page_role
4967 kvm_mmu_calc_root_page_role(struct kvm_vcpu
*vcpu
)
4969 struct kvm_mmu_role_regs regs
= vcpu_to_role_regs(vcpu
);
4970 union kvm_mmu_role role
;
4973 role
= kvm_calc_tdp_mmu_root_page_role(vcpu
, ®s
, true);
4975 role
= kvm_calc_shadow_mmu_root_page_role(vcpu
, ®s
, true);
4980 void kvm_mmu_after_set_cpuid(struct kvm_vcpu
*vcpu
)
4983 * Invalidate all MMU roles to force them to reinitialize as CPUID
4984 * information is factored into reserved bit calculations.
4986 vcpu
->arch
.root_mmu
.mmu_role
.ext
.valid
= 0;
4987 vcpu
->arch
.guest_mmu
.mmu_role
.ext
.valid
= 0;
4988 vcpu
->arch
.nested_mmu
.mmu_role
.ext
.valid
= 0;
4989 kvm_mmu_reset_context(vcpu
);
4992 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4993 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4994 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4995 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4996 * sweep the problem under the rug.
4998 * KVM's horrific CPUID ABI makes the problem all but impossible to
4999 * solve, as correctly handling multiple vCPU models (with respect to
5000 * paging and physical address properties) in a single VM would require
5001 * tracking all relevant CPUID information in kvm_mmu_page_role. That
5002 * is very undesirable as it would double the memory requirements for
5003 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
5004 * no sane VMM mucks with the core vCPU model on the fly.
5006 if (vcpu
->arch
.last_vmentry_cpu
!= -1) {
5007 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
5008 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
5012 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
5014 kvm_mmu_unload(vcpu
);
5017 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
5019 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
5023 r
= mmu_topup_memory_caches(vcpu
, !vcpu
->arch
.mmu
->direct_map
);
5026 r
= mmu_alloc_special_roots(vcpu
);
5029 if (vcpu
->arch
.mmu
->direct_map
)
5030 r
= mmu_alloc_direct_roots(vcpu
);
5032 r
= mmu_alloc_shadow_roots(vcpu
);
5036 kvm_mmu_sync_roots(vcpu
);
5038 kvm_mmu_load_pgd(vcpu
);
5039 static_call(kvm_x86_tlb_flush_current
)(vcpu
);
5044 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
5046 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.root_mmu
, KVM_MMU_ROOTS_ALL
);
5047 WARN_ON(VALID_PAGE(vcpu
->arch
.root_mmu
.root_hpa
));
5048 kvm_mmu_free_roots(vcpu
, &vcpu
->arch
.guest_mmu
, KVM_MMU_ROOTS_ALL
);
5049 WARN_ON(VALID_PAGE(vcpu
->arch
.guest_mmu
.root_hpa
));
5052 static bool need_remote_flush(u64 old
, u64
new)
5054 if (!is_shadow_present_pte(old
))
5056 if (!is_shadow_present_pte(new))
5058 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
5060 old
^= shadow_nx_mask
;
5061 new ^= shadow_nx_mask
;
5062 return (old
& ~new & PT64_PERM_MASK
) != 0;
5065 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
5072 * Assume that the pte write on a page table of the same type
5073 * as the current vcpu paging mode since we update the sptes only
5074 * when they have the same mode.
5076 if (is_pae(vcpu
) && *bytes
== 4) {
5077 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5082 if (*bytes
== 4 || *bytes
== 8) {
5083 r
= kvm_vcpu_read_guest_atomic(vcpu
, *gpa
, &gentry
, *bytes
);
5092 * If we're seeing too many writes to a page, it may no longer be a page table,
5093 * or we may be forking, in which case it is better to unmap the page.
5095 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
5098 * Skip write-flooding detected for the sp whose level is 1, because
5099 * it can become unsync, then the guest page is not write-protected.
5101 if (sp
->role
.level
== PG_LEVEL_4K
)
5104 atomic_inc(&sp
->write_flooding_count
);
5105 return atomic_read(&sp
->write_flooding_count
) >= 3;
5109 * Misaligned accesses are too much trouble to fix up; also, they usually
5110 * indicate a page is not used as a page table.
5112 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
5115 unsigned offset
, pte_size
, misaligned
;
5117 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5118 gpa
, bytes
, sp
->role
.word
);
5120 offset
= offset_in_page(gpa
);
5121 pte_size
= sp
->role
.gpte_is_8_bytes
? 8 : 4;
5124 * Sometimes, the OS only writes the last one bytes to update status
5125 * bits, for example, in linux, andb instruction is used in clear_bit().
5127 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
5130 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
5131 misaligned
|= bytes
< 4;
5136 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
5138 unsigned page_offset
, quadrant
;
5142 page_offset
= offset_in_page(gpa
);
5143 level
= sp
->role
.level
;
5145 if (!sp
->role
.gpte_is_8_bytes
) {
5146 page_offset
<<= 1; /* 32->64 */
5148 * A 32-bit pde maps 4MB while the shadow pdes map
5149 * only 2MB. So we need to double the offset again
5150 * and zap two pdes instead of one.
5152 if (level
== PT32_ROOT_LEVEL
) {
5153 page_offset
&= ~7; /* kill rounding error */
5157 quadrant
= page_offset
>> PAGE_SHIFT
;
5158 page_offset
&= ~PAGE_MASK
;
5159 if (quadrant
!= sp
->role
.quadrant
)
5163 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
5167 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
5168 const u8
*new, int bytes
,
5169 struct kvm_page_track_notifier_node
*node
)
5171 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
5172 struct kvm_mmu_page
*sp
;
5173 LIST_HEAD(invalid_list
);
5174 u64 entry
, gentry
, *spte
;
5176 bool remote_flush
, local_flush
;
5179 * If we don't have indirect shadow pages, it means no page is
5180 * write-protected, so we can exit simply.
5182 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
5185 remote_flush
= local_flush
= false;
5187 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
5190 * No need to care whether allocation memory is successful
5191 * or not since pte prefetch is skipped if it does not have
5192 * enough objects in the cache.
5194 mmu_topup_memory_caches(vcpu
, true);
5196 write_lock(&vcpu
->kvm
->mmu_lock
);
5198 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, &bytes
);
5200 ++vcpu
->kvm
->stat
.mmu_pte_write
;
5201 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
5203 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
5204 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
5205 detect_write_flooding(sp
)) {
5206 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
5207 ++vcpu
->kvm
->stat
.mmu_flooded
;
5211 spte
= get_written_sptes(sp
, gpa
, &npte
);
5218 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
, NULL
);
5219 if (gentry
&& sp
->role
.level
!= PG_LEVEL_4K
)
5220 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
5221 if (need_remote_flush(entry
, *spte
))
5222 remote_flush
= true;
5226 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
5227 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
5228 write_unlock(&vcpu
->kvm
->mmu_lock
);
5231 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gpa_t cr2_or_gpa
, u64 error_code
,
5232 void *insn
, int insn_len
)
5234 int r
, emulation_type
= EMULTYPE_PF
;
5235 bool direct
= vcpu
->arch
.mmu
->direct_map
;
5237 if (WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
->root_hpa
)))
5238 return RET_PF_RETRY
;
5241 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
5242 r
= handle_mmio_page_fault(vcpu
, cr2_or_gpa
, direct
);
5243 if (r
== RET_PF_EMULATE
)
5247 if (r
== RET_PF_INVALID
) {
5248 r
= kvm_mmu_do_page_fault(vcpu
, cr2_or_gpa
,
5249 lower_32_bits(error_code
), false);
5250 if (KVM_BUG_ON(r
== RET_PF_INVALID
, vcpu
->kvm
))
5256 if (r
!= RET_PF_EMULATE
)
5260 * Before emulating the instruction, check if the error code
5261 * was due to a RO violation while translating the guest page.
5262 * This can occur when using nested virtualization with nested
5263 * paging in both guests. If true, we simply unprotect the page
5264 * and resume the guest.
5266 if (vcpu
->arch
.mmu
->direct_map
&&
5267 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
5268 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2_or_gpa
));
5273 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5274 * optimistically try to just unprotect the page and let the processor
5275 * re-execute the instruction that caused the page fault. Do not allow
5276 * retrying MMIO emulation, as it's not only pointless but could also
5277 * cause us to enter an infinite loop because the processor will keep
5278 * faulting on the non-existent MMIO address. Retrying an instruction
5279 * from a nested guest is also pointless and dangerous as we are only
5280 * explicitly shadowing L1's page tables, i.e. unprotecting something
5281 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5283 if (!mmio_info_in_cache(vcpu
, cr2_or_gpa
, direct
) && !is_guest_mode(vcpu
))
5284 emulation_type
|= EMULTYPE_ALLOW_RETRY_PF
;
5286 return x86_emulate_instruction(vcpu
, cr2_or_gpa
, emulation_type
, insn
,
5289 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
5291 void kvm_mmu_invalidate_gva(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
5292 gva_t gva
, hpa_t root_hpa
)
5296 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5297 if (mmu
!= &vcpu
->arch
.guest_mmu
) {
5298 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5299 if (is_noncanonical_address(gva
, vcpu
))
5302 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5308 if (root_hpa
== INVALID_PAGE
) {
5309 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5312 * INVLPG is required to invalidate any global mappings for the VA,
5313 * irrespective of PCID. Since it would take us roughly similar amount
5314 * of work to determine whether any of the prev_root mappings of the VA
5315 * is marked global, or to just sync it blindly, so we might as well
5316 * just always sync it.
5318 * Mappings not reachable via the current cr3 or the prev_roots will be
5319 * synced when switching to that cr3, so nothing needs to be done here
5322 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5323 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
))
5324 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5326 mmu
->invlpg(vcpu
, gva
, root_hpa
);
5330 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
5332 kvm_mmu_invalidate_gva(vcpu
, vcpu
->arch
.mmu
, gva
, INVALID_PAGE
);
5333 ++vcpu
->stat
.invlpg
;
5335 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
5338 void kvm_mmu_invpcid_gva(struct kvm_vcpu
*vcpu
, gva_t gva
, unsigned long pcid
)
5340 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
5341 bool tlb_flush
= false;
5344 if (pcid
== kvm_get_active_pcid(vcpu
)) {
5345 mmu
->invlpg(vcpu
, gva
, mmu
->root_hpa
);
5349 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++) {
5350 if (VALID_PAGE(mmu
->prev_roots
[i
].hpa
) &&
5351 pcid
== kvm_get_pcid(vcpu
, mmu
->prev_roots
[i
].pgd
)) {
5352 mmu
->invlpg(vcpu
, gva
, mmu
->prev_roots
[i
].hpa
);
5358 static_call(kvm_x86_tlb_flush_gva
)(vcpu
, gva
);
5360 ++vcpu
->stat
.invlpg
;
5363 * Mappings not reachable via the current cr3 or the prev_roots will be
5364 * synced when switching to that cr3, so nothing needs to be done here
5369 void kvm_configure_mmu(bool enable_tdp
, int tdp_max_root_level
,
5370 int tdp_huge_page_level
)
5372 tdp_enabled
= enable_tdp
;
5373 max_tdp_level
= tdp_max_root_level
;
5376 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5377 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5378 * the kernel is not. But, KVM never creates a page size greater than
5379 * what is used by the kernel for any given HVA, i.e. the kernel's
5380 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5383 max_huge_page_level
= tdp_huge_page_level
;
5384 else if (boot_cpu_has(X86_FEATURE_GBPAGES
))
5385 max_huge_page_level
= PG_LEVEL_1G
;
5387 max_huge_page_level
= PG_LEVEL_2M
;
5389 EXPORT_SYMBOL_GPL(kvm_configure_mmu
);
5391 /* The return value indicates if tlb flush on all vcpus is needed. */
5392 typedef bool (*slot_level_handler
) (struct kvm
*kvm
,
5393 struct kvm_rmap_head
*rmap_head
,
5394 const struct kvm_memory_slot
*slot
);
5396 /* The caller should hold mmu-lock before calling this function. */
5397 static __always_inline
bool
5398 slot_handle_level_range(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5399 slot_level_handler fn
, int start_level
, int end_level
,
5400 gfn_t start_gfn
, gfn_t end_gfn
, bool flush_on_yield
,
5403 struct slot_rmap_walk_iterator iterator
;
5405 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5406 end_gfn
, &iterator
) {
5408 flush
|= fn(kvm
, iterator
.rmap
, memslot
);
5410 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
5411 if (flush
&& flush_on_yield
) {
5412 kvm_flush_remote_tlbs_with_address(kvm
,
5414 iterator
.gfn
- start_gfn
+ 1);
5417 cond_resched_rwlock_write(&kvm
->mmu_lock
);
5424 static __always_inline
bool
5425 slot_handle_level(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5426 slot_level_handler fn
, int start_level
, int end_level
,
5427 bool flush_on_yield
)
5429 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5430 end_level
, memslot
->base_gfn
,
5431 memslot
->base_gfn
+ memslot
->npages
- 1,
5432 flush_on_yield
, false);
5435 static __always_inline
bool
5436 slot_handle_leaf(struct kvm
*kvm
, const struct kvm_memory_slot
*memslot
,
5437 slot_level_handler fn
, bool flush_on_yield
)
5439 return slot_handle_level(kvm
, memslot
, fn
, PG_LEVEL_4K
,
5440 PG_LEVEL_4K
, flush_on_yield
);
5443 static void free_mmu_pages(struct kvm_mmu
*mmu
)
5445 if (!tdp_enabled
&& mmu
->pae_root
)
5446 set_memory_encrypted((unsigned long)mmu
->pae_root
, 1);
5447 free_page((unsigned long)mmu
->pae_root
);
5448 free_page((unsigned long)mmu
->pml4_root
);
5451 static int __kvm_mmu_create(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
5456 mmu
->root_hpa
= INVALID_PAGE
;
5458 mmu
->translate_gpa
= translate_gpa
;
5459 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
5460 mmu
->prev_roots
[i
] = KVM_MMU_ROOT_INFO_INVALID
;
5463 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5464 * while the PDP table is a per-vCPU construct that's allocated at MMU
5465 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5466 * x86_64. Therefore we need to allocate the PDP table in the first
5467 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5468 * generally doesn't use PAE paging and can skip allocating the PDP
5469 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5470 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5471 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5473 if (tdp_enabled
&& kvm_mmu_get_tdp_level(vcpu
) > PT32E_ROOT_LEVEL
)
5476 page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_DMA32
);
5480 mmu
->pae_root
= page_address(page
);
5483 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5484 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5485 * that KVM's writes and the CPU's reads get along. Note, this is
5486 * only necessary when using shadow paging, as 64-bit NPT can get at
5487 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5488 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5491 set_memory_decrypted((unsigned long)mmu
->pae_root
, 1);
5493 WARN_ON_ONCE(shadow_me_mask
);
5495 for (i
= 0; i
< 4; ++i
)
5496 mmu
->pae_root
[i
] = INVALID_PAE_ROOT
;
5501 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5505 vcpu
->arch
.mmu_pte_list_desc_cache
.kmem_cache
= pte_list_desc_cache
;
5506 vcpu
->arch
.mmu_pte_list_desc_cache
.gfp_zero
= __GFP_ZERO
;
5508 vcpu
->arch
.mmu_page_header_cache
.kmem_cache
= mmu_page_header_cache
;
5509 vcpu
->arch
.mmu_page_header_cache
.gfp_zero
= __GFP_ZERO
;
5511 vcpu
->arch
.mmu_shadow_page_cache
.gfp_zero
= __GFP_ZERO
;
5513 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
5514 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
5516 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5518 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.guest_mmu
);
5522 ret
= __kvm_mmu_create(vcpu
, &vcpu
->arch
.root_mmu
);
5524 goto fail_allocate_root
;
5528 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
5532 #define BATCH_ZAP_PAGES 10
5533 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5535 struct kvm_mmu_page
*sp
, *node
;
5536 int nr_zapped
, batch
= 0;
5539 list_for_each_entry_safe_reverse(sp
, node
,
5540 &kvm
->arch
.active_mmu_pages
, link
) {
5542 * No obsolete valid page exists before a newly created page
5543 * since active_mmu_pages is a FIFO list.
5545 if (!is_obsolete_sp(kvm
, sp
))
5549 * Invalid pages should never land back on the list of active
5550 * pages. Skip the bogus page, otherwise we'll get stuck in an
5551 * infinite loop if the page gets put back on the list (again).
5553 if (WARN_ON(sp
->role
.invalid
))
5557 * No need to flush the TLB since we're only zapping shadow
5558 * pages with an obsolete generation number and all vCPUS have
5559 * loaded a new root, i.e. the shadow pages being zapped cannot
5560 * be in active use by the guest.
5562 if (batch
>= BATCH_ZAP_PAGES
&&
5563 cond_resched_rwlock_write(&kvm
->mmu_lock
)) {
5568 if (__kvm_mmu_prepare_zap_page(kvm
, sp
,
5569 &kvm
->arch
.zapped_obsolete_pages
, &nr_zapped
)) {
5576 * Trigger a remote TLB flush before freeing the page tables to ensure
5577 * KVM is not in the middle of a lockless shadow page table walk, which
5578 * may reference the pages.
5580 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5584 * Fast invalidate all shadow pages and use lock-break technique
5585 * to zap obsolete pages.
5587 * It's required when memslot is being deleted or VM is being
5588 * destroyed, in these cases, we should ensure that KVM MMU does
5589 * not use any resource of the being-deleted slot or all slots
5590 * after calling the function.
5592 static void kvm_mmu_zap_all_fast(struct kvm
*kvm
)
5594 lockdep_assert_held(&kvm
->slots_lock
);
5596 write_lock(&kvm
->mmu_lock
);
5597 trace_kvm_mmu_zap_all_fast(kvm
);
5600 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5601 * held for the entire duration of zapping obsolete pages, it's
5602 * impossible for there to be multiple invalid generations associated
5603 * with *valid* shadow pages at any given time, i.e. there is exactly
5604 * one valid generation and (at most) one invalid generation.
5606 kvm
->arch
.mmu_valid_gen
= kvm
->arch
.mmu_valid_gen
? 0 : 1;
5608 /* In order to ensure all threads see this change when
5609 * handling the MMU reload signal, this must happen in the
5610 * same critical section as kvm_reload_remote_mmus, and
5611 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5612 * could drop the MMU lock and yield.
5614 if (is_tdp_mmu_enabled(kvm
))
5615 kvm_tdp_mmu_invalidate_all_roots(kvm
);
5618 * Notify all vcpus to reload its shadow page table and flush TLB.
5619 * Then all vcpus will switch to new shadow page table with the new
5622 * Note: we need to do this under the protection of mmu_lock,
5623 * otherwise, vcpu would purge shadow page but miss tlb flush.
5625 kvm_reload_remote_mmus(kvm
);
5627 kvm_zap_obsolete_pages(kvm
);
5629 write_unlock(&kvm
->mmu_lock
);
5631 if (is_tdp_mmu_enabled(kvm
)) {
5632 read_lock(&kvm
->mmu_lock
);
5633 kvm_tdp_mmu_zap_invalidated_roots(kvm
);
5634 read_unlock(&kvm
->mmu_lock
);
5638 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5640 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5643 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5644 struct kvm_memory_slot
*slot
,
5645 struct kvm_page_track_notifier_node
*node
)
5647 kvm_mmu_zap_all_fast(kvm
);
5650 void kvm_mmu_init_vm(struct kvm
*kvm
)
5652 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5654 spin_lock_init(&kvm
->arch
.mmu_unsync_pages_lock
);
5656 if (!kvm_mmu_init_tdp_mmu(kvm
))
5658 * No smp_load/store wrappers needed here as we are in
5659 * VM init and there cannot be any memslots / other threads
5660 * accessing this struct kvm yet.
5662 kvm
->arch
.memslots_have_rmaps
= true;
5664 node
->track_write
= kvm_mmu_pte_write
;
5665 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5666 kvm_page_track_register_notifier(kvm
, node
);
5669 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5671 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5673 kvm_page_track_unregister_notifier(kvm
, node
);
5675 kvm_mmu_uninit_tdp_mmu(kvm
);
5679 * Invalidate (zap) SPTEs that cover GFNs from gfn_start and up to gfn_end
5680 * (not including it)
5682 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5684 struct kvm_memslots
*slots
;
5685 struct kvm_memory_slot
*memslot
;
5689 write_lock(&kvm
->mmu_lock
);
5691 kvm_inc_notifier_count(kvm
, gfn_start
, gfn_end
);
5693 if (kvm_memslots_have_rmaps(kvm
)) {
5694 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5695 slots
= __kvm_memslots(kvm
, i
);
5696 kvm_for_each_memslot(memslot
, slots
) {
5699 start
= max(gfn_start
, memslot
->base_gfn
);
5700 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5704 flush
= slot_handle_level_range(kvm
,
5705 (const struct kvm_memory_slot
*) memslot
,
5706 kvm_zap_rmapp
, PG_LEVEL_4K
,
5707 KVM_MAX_HUGEPAGE_LEVEL
, start
,
5708 end
- 1, true, flush
);
5712 kvm_flush_remote_tlbs_with_address(kvm
, gfn_start
,
5713 gfn_end
- gfn_start
);
5716 if (is_tdp_mmu_enabled(kvm
)) {
5717 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++)
5718 flush
= kvm_tdp_mmu_zap_gfn_range(kvm
, i
, gfn_start
,
5721 kvm_flush_remote_tlbs_with_address(kvm
, gfn_start
,
5722 gfn_end
- gfn_start
);
5726 kvm_flush_remote_tlbs_with_address(kvm
, gfn_start
, gfn_end
);
5728 kvm_dec_notifier_count(kvm
, gfn_start
, gfn_end
);
5730 write_unlock(&kvm
->mmu_lock
);
5733 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5734 struct kvm_rmap_head
*rmap_head
,
5735 const struct kvm_memory_slot
*slot
)
5737 return __rmap_write_protect(kvm
, rmap_head
, false);
5740 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5741 const struct kvm_memory_slot
*memslot
,
5746 if (kvm_memslots_have_rmaps(kvm
)) {
5747 write_lock(&kvm
->mmu_lock
);
5748 flush
= slot_handle_level(kvm
, memslot
, slot_rmap_write_protect
,
5749 start_level
, KVM_MAX_HUGEPAGE_LEVEL
,
5751 write_unlock(&kvm
->mmu_lock
);
5754 if (is_tdp_mmu_enabled(kvm
)) {
5755 read_lock(&kvm
->mmu_lock
);
5756 flush
|= kvm_tdp_mmu_wrprot_slot(kvm
, memslot
, start_level
);
5757 read_unlock(&kvm
->mmu_lock
);
5761 * We can flush all the TLBs out of the mmu lock without TLB
5762 * corruption since we just change the spte from writable to
5763 * readonly so that we only need to care the case of changing
5764 * spte from present to present (changing the spte from present
5765 * to nonpresent will flush all the TLBs immediately), in other
5766 * words, the only case we care is mmu_spte_update() where we
5767 * have checked Host-writable | MMU-writable instead of
5768 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5772 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5775 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5776 struct kvm_rmap_head
*rmap_head
,
5777 const struct kvm_memory_slot
*slot
)
5780 struct rmap_iterator iter
;
5781 int need_tlb_flush
= 0;
5783 struct kvm_mmu_page
*sp
;
5786 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5787 sp
= sptep_to_sp(sptep
);
5788 pfn
= spte_to_pfn(*sptep
);
5791 * We cannot do huge page mapping for indirect shadow pages,
5792 * which are found on the last rmap (level = 1) when not using
5793 * tdp; such shadow pages are synced with the page table in
5794 * the guest, and the guest page table is using 4K page size
5795 * mapping if the indirect sp has level = 1.
5797 if (sp
->role
.direct
&& !kvm_is_reserved_pfn(pfn
) &&
5798 sp
->role
.level
< kvm_mmu_max_mapping_level(kvm
, slot
, sp
->gfn
,
5799 pfn
, PG_LEVEL_NUM
)) {
5800 pte_list_remove(rmap_head
, sptep
);
5802 if (kvm_available_flush_tlb_with_range())
5803 kvm_flush_remote_tlbs_with_address(kvm
, sp
->gfn
,
5804 KVM_PAGES_PER_HPAGE(sp
->role
.level
));
5812 return need_tlb_flush
;
5815 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5816 const struct kvm_memory_slot
*slot
)
5820 if (kvm_memslots_have_rmaps(kvm
)) {
5821 write_lock(&kvm
->mmu_lock
);
5822 flush
= slot_handle_leaf(kvm
, slot
, kvm_mmu_zap_collapsible_spte
, true);
5824 kvm_arch_flush_remote_tlbs_memslot(kvm
, slot
);
5825 write_unlock(&kvm
->mmu_lock
);
5828 if (is_tdp_mmu_enabled(kvm
)) {
5829 read_lock(&kvm
->mmu_lock
);
5830 flush
= kvm_tdp_mmu_zap_collapsible_sptes(kvm
, slot
, flush
);
5832 kvm_arch_flush_remote_tlbs_memslot(kvm
, slot
);
5833 read_unlock(&kvm
->mmu_lock
);
5837 void kvm_arch_flush_remote_tlbs_memslot(struct kvm
*kvm
,
5838 const struct kvm_memory_slot
*memslot
)
5841 * All current use cases for flushing the TLBs for a specific memslot
5842 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5843 * The interaction between the various operations on memslot must be
5844 * serialized by slots_locks to ensure the TLB flush from one operation
5845 * is observed by any other operation on the same memslot.
5847 lockdep_assert_held(&kvm
->slots_lock
);
5848 kvm_flush_remote_tlbs_with_address(kvm
, memslot
->base_gfn
,
5852 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5853 const struct kvm_memory_slot
*memslot
)
5857 if (kvm_memslots_have_rmaps(kvm
)) {
5858 write_lock(&kvm
->mmu_lock
);
5859 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
,
5861 write_unlock(&kvm
->mmu_lock
);
5864 if (is_tdp_mmu_enabled(kvm
)) {
5865 read_lock(&kvm
->mmu_lock
);
5866 flush
|= kvm_tdp_mmu_clear_dirty_slot(kvm
, memslot
);
5867 read_unlock(&kvm
->mmu_lock
);
5871 * It's also safe to flush TLBs out of mmu lock here as currently this
5872 * function is only used for dirty logging, in which case flushing TLB
5873 * out of mmu lock also guarantees no dirty pages will be lost in
5877 kvm_arch_flush_remote_tlbs_memslot(kvm
, memslot
);
5880 void kvm_mmu_zap_all(struct kvm
*kvm
)
5882 struct kvm_mmu_page
*sp
, *node
;
5883 LIST_HEAD(invalid_list
);
5886 write_lock(&kvm
->mmu_lock
);
5888 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
5889 if (WARN_ON(sp
->role
.invalid
))
5891 if (__kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
, &ign
))
5893 if (cond_resched_rwlock_write(&kvm
->mmu_lock
))
5897 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5899 if (is_tdp_mmu_enabled(kvm
))
5900 kvm_tdp_mmu_zap_all(kvm
);
5902 write_unlock(&kvm
->mmu_lock
);
5905 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, u64 gen
)
5907 WARN_ON(gen
& KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS
);
5909 gen
&= MMIO_SPTE_GEN_MASK
;
5912 * Generation numbers are incremented in multiples of the number of
5913 * address spaces in order to provide unique generations across all
5914 * address spaces. Strip what is effectively the address space
5915 * modifier prior to checking for a wrap of the MMIO generation so
5916 * that a wrap in any address space is detected.
5918 gen
&= ~((u64
)KVM_ADDRESS_SPACE_NUM
- 1);
5921 * The very rare case: if the MMIO generation number has wrapped,
5922 * zap all shadow pages.
5924 if (unlikely(gen
== 0)) {
5925 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5926 kvm_mmu_zap_all_fast(kvm
);
5930 static unsigned long
5931 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5934 int nr_to_scan
= sc
->nr_to_scan
;
5935 unsigned long freed
= 0;
5937 mutex_lock(&kvm_lock
);
5939 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5941 LIST_HEAD(invalid_list
);
5944 * Never scan more than sc->nr_to_scan VM instances.
5945 * Will not hit this condition practically since we do not try
5946 * to shrink more than one VM and it is very unlikely to see
5947 * !n_used_mmu_pages so many times.
5952 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5953 * here. We may skip a VM instance errorneosly, but we do not
5954 * want to shrink a VM that only started to populate its MMU
5957 if (!kvm
->arch
.n_used_mmu_pages
&&
5958 !kvm_has_zapped_obsolete_pages(kvm
))
5961 idx
= srcu_read_lock(&kvm
->srcu
);
5962 write_lock(&kvm
->mmu_lock
);
5964 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5965 kvm_mmu_commit_zap_page(kvm
,
5966 &kvm
->arch
.zapped_obsolete_pages
);
5970 freed
= kvm_mmu_zap_oldest_mmu_pages(kvm
, sc
->nr_to_scan
);
5973 write_unlock(&kvm
->mmu_lock
);
5974 srcu_read_unlock(&kvm
->srcu
, idx
);
5977 * unfair on small ones
5978 * per-vm shrinkers cry out
5979 * sadness comes quickly
5981 list_move_tail(&kvm
->vm_list
, &vm_list
);
5985 mutex_unlock(&kvm_lock
);
5989 static unsigned long
5990 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5992 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5995 static struct shrinker mmu_shrinker
= {
5996 .count_objects
= mmu_shrink_count
,
5997 .scan_objects
= mmu_shrink_scan
,
5998 .seeks
= DEFAULT_SEEKS
* 10,
6001 static void mmu_destroy_caches(void)
6003 kmem_cache_destroy(pte_list_desc_cache
);
6004 kmem_cache_destroy(mmu_page_header_cache
);
6007 static bool get_nx_auto_mode(void)
6009 /* Return true when CPU has the bug, and mitigations are ON */
6010 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT
) && !cpu_mitigations_off();
6013 static void __set_nx_huge_pages(bool val
)
6015 nx_huge_pages
= itlb_multihit_kvm_mitigation
= val
;
6018 static int set_nx_huge_pages(const char *val
, const struct kernel_param
*kp
)
6020 bool old_val
= nx_huge_pages
;
6023 /* In "auto" mode deploy workaround only if CPU has the bug. */
6024 if (sysfs_streq(val
, "off"))
6026 else if (sysfs_streq(val
, "force"))
6028 else if (sysfs_streq(val
, "auto"))
6029 new_val
= get_nx_auto_mode();
6030 else if (strtobool(val
, &new_val
) < 0)
6033 __set_nx_huge_pages(new_val
);
6035 if (new_val
!= old_val
) {
6038 mutex_lock(&kvm_lock
);
6040 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
6041 mutex_lock(&kvm
->slots_lock
);
6042 kvm_mmu_zap_all_fast(kvm
);
6043 mutex_unlock(&kvm
->slots_lock
);
6045 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
6047 mutex_unlock(&kvm_lock
);
6053 int kvm_mmu_module_init(void)
6057 if (nx_huge_pages
== -1)
6058 __set_nx_huge_pages(get_nx_auto_mode());
6061 * MMU roles use union aliasing which is, generally speaking, an
6062 * undefined behavior. However, we supposedly know how compilers behave
6063 * and the current status quo is unlikely to change. Guardians below are
6064 * supposed to let us know if the assumption becomes false.
6066 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role
) != sizeof(u32
));
6067 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role
) != sizeof(u32
));
6068 BUILD_BUG_ON(sizeof(union kvm_mmu_role
) != sizeof(u64
));
6070 kvm_mmu_reset_all_pte_masks();
6072 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
6073 sizeof(struct pte_list_desc
),
6074 0, SLAB_ACCOUNT
, NULL
);
6075 if (!pte_list_desc_cache
)
6078 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
6079 sizeof(struct kvm_mmu_page
),
6080 0, SLAB_ACCOUNT
, NULL
);
6081 if (!mmu_page_header_cache
)
6084 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
6087 ret
= register_shrinker(&mmu_shrinker
);
6094 mmu_destroy_caches();
6099 * Calculate mmu pages needed for kvm.
6101 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm
*kvm
)
6103 unsigned long nr_mmu_pages
;
6104 unsigned long nr_pages
= 0;
6105 struct kvm_memslots
*slots
;
6106 struct kvm_memory_slot
*memslot
;
6109 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
6110 slots
= __kvm_memslots(kvm
, i
);
6112 kvm_for_each_memslot(memslot
, slots
)
6113 nr_pages
+= memslot
->npages
;
6116 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
6117 nr_mmu_pages
= max(nr_mmu_pages
, KVM_MIN_ALLOC_MMU_PAGES
);
6119 return nr_mmu_pages
;
6122 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
6124 kvm_mmu_unload(vcpu
);
6125 free_mmu_pages(&vcpu
->arch
.root_mmu
);
6126 free_mmu_pages(&vcpu
->arch
.guest_mmu
);
6127 mmu_free_memory_caches(vcpu
);
6130 void kvm_mmu_module_exit(void)
6132 mmu_destroy_caches();
6133 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
6134 unregister_shrinker(&mmu_shrinker
);
6135 mmu_audit_disable();
6138 static int set_nx_huge_pages_recovery_ratio(const char *val
, const struct kernel_param
*kp
)
6140 unsigned int old_val
;
6143 old_val
= nx_huge_pages_recovery_ratio
;
6144 err
= param_set_uint(val
, kp
);
6148 if (READ_ONCE(nx_huge_pages
) &&
6149 !old_val
&& nx_huge_pages_recovery_ratio
) {
6152 mutex_lock(&kvm_lock
);
6154 list_for_each_entry(kvm
, &vm_list
, vm_list
)
6155 wake_up_process(kvm
->arch
.nx_lpage_recovery_thread
);
6157 mutex_unlock(&kvm_lock
);
6163 static void kvm_recover_nx_lpages(struct kvm
*kvm
)
6165 unsigned long nx_lpage_splits
= kvm
->stat
.nx_lpage_splits
;
6167 struct kvm_mmu_page
*sp
;
6169 LIST_HEAD(invalid_list
);
6173 rcu_idx
= srcu_read_lock(&kvm
->srcu
);
6174 write_lock(&kvm
->mmu_lock
);
6176 ratio
= READ_ONCE(nx_huge_pages_recovery_ratio
);
6177 to_zap
= ratio
? DIV_ROUND_UP(nx_lpage_splits
, ratio
) : 0;
6178 for ( ; to_zap
; --to_zap
) {
6179 if (list_empty(&kvm
->arch
.lpage_disallowed_mmu_pages
))
6183 * We use a separate list instead of just using active_mmu_pages
6184 * because the number of lpage_disallowed pages is expected to
6185 * be relatively small compared to the total.
6187 sp
= list_first_entry(&kvm
->arch
.lpage_disallowed_mmu_pages
,
6188 struct kvm_mmu_page
,
6189 lpage_disallowed_link
);
6190 WARN_ON_ONCE(!sp
->lpage_disallowed
);
6191 if (is_tdp_mmu_page(sp
)) {
6192 flush
|= kvm_tdp_mmu_zap_sp(kvm
, sp
);
6194 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
6195 WARN_ON_ONCE(sp
->lpage_disallowed
);
6198 if (need_resched() || rwlock_needbreak(&kvm
->mmu_lock
)) {
6199 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
6200 cond_resched_rwlock_write(&kvm
->mmu_lock
);
6204 kvm_mmu_remote_flush_or_zap(kvm
, &invalid_list
, flush
);
6206 write_unlock(&kvm
->mmu_lock
);
6207 srcu_read_unlock(&kvm
->srcu
, rcu_idx
);
6210 static long get_nx_lpage_recovery_timeout(u64 start_time
)
6212 return READ_ONCE(nx_huge_pages
) && READ_ONCE(nx_huge_pages_recovery_ratio
)
6213 ? start_time
+ 60 * HZ
- get_jiffies_64()
6214 : MAX_SCHEDULE_TIMEOUT
;
6217 static int kvm_nx_lpage_recovery_worker(struct kvm
*kvm
, uintptr_t data
)
6220 long remaining_time
;
6223 start_time
= get_jiffies_64();
6224 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6226 set_current_state(TASK_INTERRUPTIBLE
);
6227 while (!kthread_should_stop() && remaining_time
> 0) {
6228 schedule_timeout(remaining_time
);
6229 remaining_time
= get_nx_lpage_recovery_timeout(start_time
);
6230 set_current_state(TASK_INTERRUPTIBLE
);
6233 set_current_state(TASK_RUNNING
);
6235 if (kthread_should_stop())
6238 kvm_recover_nx_lpages(kvm
);
6242 int kvm_mmu_post_init_vm(struct kvm
*kvm
)
6246 err
= kvm_vm_create_worker_thread(kvm
, kvm_nx_lpage_recovery_worker
, 0,
6247 "kvm-nx-lpage-recovery",
6248 &kvm
->arch
.nx_lpage_recovery_thread
);
6250 kthread_unpark(kvm
->arch
.nx_lpage_recovery_thread
);
6255 void kvm_mmu_pre_destroy_vm(struct kvm
*kvm
)
6257 if (kvm
->arch
.nx_lpage_recovery_thread
)
6258 kthread_stop(kvm
->arch
.nx_lpage_recovery_thread
);