2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
44 #include <asm/kvm_page_track.h>
47 * When setting this variable to true it enables Two-Dimensional-Paging
48 * where the hardware walks 2 page tables:
49 * 1. the guest-virtual to guest-physical
50 * 2. while doing 1. it walks guest-physical to host-physical
51 * If the hardware supports that we don't need to do shadow paging.
53 bool tdp_enabled
= false;
57 AUDIT_POST_PAGE_FAULT
,
68 module_param(dbg
, bool, 0644);
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define MMU_WARN_ON(x) WARN_ON(x)
74 #define pgprintk(x...) do { } while (0)
75 #define rmap_printk(x...) do { } while (0)
76 #define MMU_WARN_ON(x) do { } while (0)
79 #define PTE_PREFETCH_NUM 8
81 #define PT_FIRST_AVAIL_BITS_SHIFT 10
82 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
84 #define PT64_LEVEL_BITS 9
86 #define PT64_LEVEL_SHIFT(level) \
87 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
89 #define PT64_INDEX(address, level)\
90 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
93 #define PT32_LEVEL_BITS 10
95 #define PT32_LEVEL_SHIFT(level) \
96 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
98 #define PT32_LVL_OFFSET_MASK(level) \
99 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
100 * PT32_LEVEL_BITS))) - 1))
102 #define PT32_INDEX(address, level)\
103 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
106 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
107 #define PT64_DIR_BASE_ADDR_MASK \
108 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
109 #define PT64_LVL_ADDR_MASK(level) \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
111 * PT64_LEVEL_BITS))) - 1))
112 #define PT64_LVL_OFFSET_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
116 #define PT32_BASE_ADDR_MASK PAGE_MASK
117 #define PT32_DIR_BASE_ADDR_MASK \
118 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
119 #define PT32_LVL_ADDR_MASK(level) \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
121 * PT32_LEVEL_BITS))) - 1))
123 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
124 | shadow_x_mask | shadow_nx_mask)
126 #define ACC_EXEC_MASK 1
127 #define ACC_WRITE_MASK PT_WRITABLE_MASK
128 #define ACC_USER_MASK PT_USER_MASK
129 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
131 #include <trace/events/kvm.h>
133 #define CREATE_TRACE_POINTS
134 #include "mmutrace.h"
136 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
137 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
139 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
141 /* make pte_list_desc fit well in cache line */
142 #define PTE_LIST_EXT 3
144 struct pte_list_desc
{
145 u64
*sptes
[PTE_LIST_EXT
];
146 struct pte_list_desc
*more
;
149 struct kvm_shadow_walk_iterator
{
157 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)) && \
165 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
166 __shadow_walk_next(&(_walker), spte))
168 static struct kmem_cache
*pte_list_desc_cache
;
169 static struct kmem_cache
*mmu_page_header_cache
;
170 static struct percpu_counter kvm_total_used_mmu_pages
;
172 static u64 __read_mostly shadow_nx_mask
;
173 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
174 static u64 __read_mostly shadow_user_mask
;
175 static u64 __read_mostly shadow_accessed_mask
;
176 static u64 __read_mostly shadow_dirty_mask
;
177 static u64 __read_mostly shadow_mmio_mask
;
178 static u64 __read_mostly shadow_present_mask
;
180 static void mmu_spte_set(u64
*sptep
, u64 spte
);
181 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
183 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
185 shadow_mmio_mask
= mmio_mask
;
187 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
190 * the low bit of the generation number is always presumed to be zero.
191 * This disables mmio caching during memslot updates. The concept is
192 * similar to a seqcount but instead of retrying the access we just punt
193 * and ignore the cache.
195 * spte bits 3-11 are used as bits 1-9 of the generation number,
196 * the bits 52-61 are used as bits 10-19 of the generation number.
198 #define MMIO_SPTE_GEN_LOW_SHIFT 2
199 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
201 #define MMIO_GEN_SHIFT 20
202 #define MMIO_GEN_LOW_SHIFT 10
203 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
204 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
206 static u64
generation_mmio_spte_mask(unsigned int gen
)
210 WARN_ON(gen
& ~MMIO_GEN_MASK
);
212 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
213 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
217 static unsigned int get_mmio_spte_generation(u64 spte
)
221 spte
&= ~shadow_mmio_mask
;
223 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
224 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
228 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
230 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
233 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
236 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
237 u64 mask
= generation_mmio_spte_mask(gen
);
239 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
240 mask
|= shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
;
242 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
243 mmu_spte_set(sptep
, mask
);
246 static bool is_mmio_spte(u64 spte
)
248 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
251 static gfn_t
get_mmio_spte_gfn(u64 spte
)
253 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
254 return (spte
& ~mask
) >> PAGE_SHIFT
;
257 static unsigned get_mmio_spte_access(u64 spte
)
259 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
260 return (spte
& ~mask
) & ~PAGE_MASK
;
263 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
264 kvm_pfn_t pfn
, unsigned access
)
266 if (unlikely(is_noslot_pfn(pfn
))) {
267 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
274 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
276 unsigned int kvm_gen
, spte_gen
;
278 kvm_gen
= kvm_current_mmio_generation(vcpu
);
279 spte_gen
= get_mmio_spte_generation(spte
);
281 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
282 return likely(kvm_gen
== spte_gen
);
285 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
286 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
)
288 shadow_user_mask
= user_mask
;
289 shadow_accessed_mask
= accessed_mask
;
290 shadow_dirty_mask
= dirty_mask
;
291 shadow_nx_mask
= nx_mask
;
292 shadow_x_mask
= x_mask
;
293 shadow_present_mask
= p_mask
;
295 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
297 static int is_cpuid_PSE36(void)
302 static int is_nx(struct kvm_vcpu
*vcpu
)
304 return vcpu
->arch
.efer
& EFER_NX
;
307 static int is_shadow_present_pte(u64 pte
)
309 return (pte
& 0xFFFFFFFFull
) && !is_mmio_spte(pte
);
312 static int is_large_pte(u64 pte
)
314 return pte
& PT_PAGE_SIZE_MASK
;
317 static int is_last_spte(u64 pte
, int level
)
319 if (level
== PT_PAGE_TABLE_LEVEL
)
321 if (is_large_pte(pte
))
326 static kvm_pfn_t
spte_to_pfn(u64 pte
)
328 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
331 static gfn_t
pse36_gfn_delta(u32 gpte
)
333 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
335 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
339 static void __set_spte(u64
*sptep
, u64 spte
)
341 WRITE_ONCE(*sptep
, spte
);
344 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
346 WRITE_ONCE(*sptep
, spte
);
349 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
351 return xchg(sptep
, spte
);
354 static u64
__get_spte_lockless(u64
*sptep
)
356 return ACCESS_ONCE(*sptep
);
367 static void count_spte_clear(u64
*sptep
, u64 spte
)
369 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
371 if (is_shadow_present_pte(spte
))
374 /* Ensure the spte is completely set before we increase the count */
376 sp
->clear_spte_count
++;
379 static void __set_spte(u64
*sptep
, u64 spte
)
381 union split_spte
*ssptep
, sspte
;
383 ssptep
= (union split_spte
*)sptep
;
384 sspte
= (union split_spte
)spte
;
386 ssptep
->spte_high
= sspte
.spte_high
;
389 * If we map the spte from nonpresent to present, We should store
390 * the high bits firstly, then set present bit, so cpu can not
391 * fetch this spte while we are setting the spte.
395 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
398 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
400 union split_spte
*ssptep
, sspte
;
402 ssptep
= (union split_spte
*)sptep
;
403 sspte
= (union split_spte
)spte
;
405 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
408 * If we map the spte from present to nonpresent, we should clear
409 * present bit firstly to avoid vcpu fetch the old high bits.
413 ssptep
->spte_high
= sspte
.spte_high
;
414 count_spte_clear(sptep
, spte
);
417 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
419 union split_spte
*ssptep
, sspte
, orig
;
421 ssptep
= (union split_spte
*)sptep
;
422 sspte
= (union split_spte
)spte
;
424 /* xchg acts as a barrier before the setting of the high bits */
425 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
426 orig
.spte_high
= ssptep
->spte_high
;
427 ssptep
->spte_high
= sspte
.spte_high
;
428 count_spte_clear(sptep
, spte
);
434 * The idea using the light way get the spte on x86_32 guest is from
435 * gup_get_pte(arch/x86/mm/gup.c).
437 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
438 * coalesces them and we are running out of the MMU lock. Therefore
439 * we need to protect against in-progress updates of the spte.
441 * Reading the spte while an update is in progress may get the old value
442 * for the high part of the spte. The race is fine for a present->non-present
443 * change (because the high part of the spte is ignored for non-present spte),
444 * but for a present->present change we must reread the spte.
446 * All such changes are done in two steps (present->non-present and
447 * non-present->present), hence it is enough to count the number of
448 * present->non-present updates: if it changed while reading the spte,
449 * we might have hit the race. This is done using clear_spte_count.
451 static u64
__get_spte_lockless(u64
*sptep
)
453 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
454 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
458 count
= sp
->clear_spte_count
;
461 spte
.spte_low
= orig
->spte_low
;
464 spte
.spte_high
= orig
->spte_high
;
467 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
468 count
!= sp
->clear_spte_count
))
475 static bool spte_is_locklessly_modifiable(u64 spte
)
477 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
478 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
481 static bool spte_has_volatile_bits(u64 spte
)
484 * Always atomically update spte if it can be updated
485 * out of mmu-lock, it can ensure dirty bit is not lost,
486 * also, it can help us to get a stable is_writable_pte()
487 * to ensure tlb flush is not missed.
489 if (spte_is_locklessly_modifiable(spte
))
492 if (!shadow_accessed_mask
)
495 if (!is_shadow_present_pte(spte
))
498 if ((spte
& shadow_accessed_mask
) &&
499 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
505 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
507 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
510 static bool spte_is_bit_changed(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
512 return (old_spte
& bit_mask
) != (new_spte
& bit_mask
);
515 /* Rules for using mmu_spte_set:
516 * Set the sptep from nonpresent to present.
517 * Note: the sptep being assigned *must* be either not present
518 * or in a state where the hardware will not attempt to update
521 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
523 WARN_ON(is_shadow_present_pte(*sptep
));
524 __set_spte(sptep
, new_spte
);
527 /* Rules for using mmu_spte_update:
528 * Update the state bits, it means the mapped pfn is not changed.
530 * Whenever we overwrite a writable spte with a read-only one we
531 * should flush remote TLBs. Otherwise rmap_write_protect
532 * will find a read-only spte, even though the writable spte
533 * might be cached on a CPU's TLB, the return value indicates this
536 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
538 u64 old_spte
= *sptep
;
541 WARN_ON(!is_shadow_present_pte(new_spte
));
543 if (!is_shadow_present_pte(old_spte
)) {
544 mmu_spte_set(sptep
, new_spte
);
548 if (!spte_has_volatile_bits(old_spte
))
549 __update_clear_spte_fast(sptep
, new_spte
);
551 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
554 * For the spte updated out of mmu-lock is safe, since
555 * we always atomically update it, see the comments in
556 * spte_has_volatile_bits().
558 if (spte_is_locklessly_modifiable(old_spte
) &&
559 !is_writable_pte(new_spte
))
562 if (!shadow_accessed_mask
) {
564 * We don't set page dirty when dropping non-writable spte.
565 * So do it now if the new spte is becoming non-writable.
568 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
573 * Flush TLB when accessed/dirty bits are changed in the page tables,
574 * to guarantee consistency between TLB and page tables.
576 if (spte_is_bit_changed(old_spte
, new_spte
,
577 shadow_accessed_mask
| shadow_dirty_mask
))
580 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
581 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
582 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
583 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
589 * Rules for using mmu_spte_clear_track_bits:
590 * It sets the sptep from present to nonpresent, and track the
591 * state bits, it is used to clear the last level sptep.
593 static int mmu_spte_clear_track_bits(u64
*sptep
)
596 u64 old_spte
= *sptep
;
598 if (!spte_has_volatile_bits(old_spte
))
599 __update_clear_spte_fast(sptep
, 0ull);
601 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
603 if (!is_shadow_present_pte(old_spte
))
606 pfn
= spte_to_pfn(old_spte
);
609 * KVM does not hold the refcount of the page used by
610 * kvm mmu, before reclaiming the page, we should
611 * unmap it from mmu first.
613 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
615 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
616 kvm_set_pfn_accessed(pfn
);
617 if (old_spte
& (shadow_dirty_mask
? shadow_dirty_mask
:
619 kvm_set_pfn_dirty(pfn
);
624 * Rules for using mmu_spte_clear_no_track:
625 * Directly clear spte without caring the state bits of sptep,
626 * it is used to set the upper level spte.
628 static void mmu_spte_clear_no_track(u64
*sptep
)
630 __update_clear_spte_fast(sptep
, 0ull);
633 static u64
mmu_spte_get_lockless(u64
*sptep
)
635 return __get_spte_lockless(sptep
);
638 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
641 * Prevent page table teardown by making any free-er wait during
642 * kvm_flush_remote_tlbs() IPI to all active vcpus.
647 * Make sure a following spte read is not reordered ahead of the write
650 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
653 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
656 * Make sure the write to vcpu->mode is not reordered in front of
657 * reads to sptes. If it does, kvm_commit_zap_page() can see us
658 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
660 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
664 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
665 struct kmem_cache
*base_cache
, int min
)
669 if (cache
->nobjs
>= min
)
671 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
672 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
675 cache
->objects
[cache
->nobjs
++] = obj
;
680 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
685 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
686 struct kmem_cache
*cache
)
689 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
692 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
697 if (cache
->nobjs
>= min
)
699 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
700 page
= (void *)__get_free_page(GFP_KERNEL
);
703 cache
->objects
[cache
->nobjs
++] = page
;
708 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
711 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
714 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
718 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
719 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
722 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
725 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
726 mmu_page_header_cache
, 4);
731 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
733 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
734 pte_list_desc_cache
);
735 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
736 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
737 mmu_page_header_cache
);
740 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
745 p
= mc
->objects
[--mc
->nobjs
];
749 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
751 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
754 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
756 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
759 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
761 if (!sp
->role
.direct
)
762 return sp
->gfns
[index
];
764 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
767 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
770 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
772 sp
->gfns
[index
] = gfn
;
776 * Return the pointer to the large page information for a given gfn,
777 * handling slots that are not large page aligned.
779 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
780 struct kvm_memory_slot
*slot
,
785 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
786 return &slot
->arch
.lpage_info
[level
- 2][idx
];
789 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
790 gfn_t gfn
, int count
)
792 struct kvm_lpage_info
*linfo
;
795 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
796 linfo
= lpage_info_slot(gfn
, slot
, i
);
797 linfo
->disallow_lpage
+= count
;
798 WARN_ON(linfo
->disallow_lpage
< 0);
802 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
804 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
807 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
809 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
812 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
814 struct kvm_memslots
*slots
;
815 struct kvm_memory_slot
*slot
;
818 kvm
->arch
.indirect_shadow_pages
++;
820 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
821 slot
= __gfn_to_memslot(slots
, gfn
);
823 /* the non-leaf shadow pages are keeping readonly. */
824 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
825 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
826 KVM_PAGE_TRACK_WRITE
);
828 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
831 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
833 struct kvm_memslots
*slots
;
834 struct kvm_memory_slot
*slot
;
837 kvm
->arch
.indirect_shadow_pages
--;
839 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
840 slot
= __gfn_to_memslot(slots
, gfn
);
841 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
842 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
843 KVM_PAGE_TRACK_WRITE
);
845 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
848 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
849 struct kvm_memory_slot
*slot
)
851 struct kvm_lpage_info
*linfo
;
854 linfo
= lpage_info_slot(gfn
, slot
, level
);
855 return !!linfo
->disallow_lpage
;
861 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
864 struct kvm_memory_slot
*slot
;
866 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
867 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
870 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
872 unsigned long page_size
;
875 page_size
= kvm_host_page_size(kvm
, gfn
);
877 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
878 if (page_size
>= KVM_HPAGE_SIZE(i
))
887 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
890 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
892 if (no_dirty_log
&& slot
->dirty_bitmap
)
898 static struct kvm_memory_slot
*
899 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
902 struct kvm_memory_slot
*slot
;
904 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
905 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
911 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
912 bool *force_pt_level
)
914 int host_level
, level
, max_level
;
915 struct kvm_memory_slot
*slot
;
917 if (unlikely(*force_pt_level
))
918 return PT_PAGE_TABLE_LEVEL
;
920 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
921 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
922 if (unlikely(*force_pt_level
))
923 return PT_PAGE_TABLE_LEVEL
;
925 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
927 if (host_level
== PT_PAGE_TABLE_LEVEL
)
930 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
932 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
933 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
940 * About rmap_head encoding:
942 * If the bit zero of rmap_head->val is clear, then it points to the only spte
943 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
944 * pte_list_desc containing more mappings.
948 * Returns the number of pointers in the rmap chain, not counting the new one.
950 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
951 struct kvm_rmap_head
*rmap_head
)
953 struct pte_list_desc
*desc
;
956 if (!rmap_head
->val
) {
957 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
958 rmap_head
->val
= (unsigned long)spte
;
959 } else if (!(rmap_head
->val
& 1)) {
960 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
961 desc
= mmu_alloc_pte_list_desc(vcpu
);
962 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
963 desc
->sptes
[1] = spte
;
964 rmap_head
->val
= (unsigned long)desc
| 1;
967 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
968 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
969 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
971 count
+= PTE_LIST_EXT
;
973 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
974 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
977 for (i
= 0; desc
->sptes
[i
]; ++i
)
979 desc
->sptes
[i
] = spte
;
985 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
986 struct pte_list_desc
*desc
, int i
,
987 struct pte_list_desc
*prev_desc
)
991 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
993 desc
->sptes
[i
] = desc
->sptes
[j
];
994 desc
->sptes
[j
] = NULL
;
997 if (!prev_desc
&& !desc
->more
)
998 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1001 prev_desc
->more
= desc
->more
;
1003 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1004 mmu_free_pte_list_desc(desc
);
1007 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1009 struct pte_list_desc
*desc
;
1010 struct pte_list_desc
*prev_desc
;
1013 if (!rmap_head
->val
) {
1014 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1016 } else if (!(rmap_head
->val
& 1)) {
1017 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1018 if ((u64
*)rmap_head
->val
!= spte
) {
1019 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1024 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1025 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1028 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1029 if (desc
->sptes
[i
] == spte
) {
1030 pte_list_desc_remove_entry(rmap_head
,
1031 desc
, i
, prev_desc
);
1038 pr_err("pte_list_remove: %p many->many\n", spte
);
1043 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1044 struct kvm_memory_slot
*slot
)
1048 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1049 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1052 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1053 struct kvm_mmu_page
*sp
)
1055 struct kvm_memslots
*slots
;
1056 struct kvm_memory_slot
*slot
;
1058 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1059 slot
= __gfn_to_memslot(slots
, gfn
);
1060 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1063 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1065 struct kvm_mmu_memory_cache
*cache
;
1067 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1068 return mmu_memory_cache_free_objects(cache
);
1071 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1073 struct kvm_mmu_page
*sp
;
1074 struct kvm_rmap_head
*rmap_head
;
1076 sp
= page_header(__pa(spte
));
1077 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1078 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1079 return pte_list_add(vcpu
, spte
, rmap_head
);
1082 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1084 struct kvm_mmu_page
*sp
;
1086 struct kvm_rmap_head
*rmap_head
;
1088 sp
= page_header(__pa(spte
));
1089 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1090 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1091 pte_list_remove(spte
, rmap_head
);
1095 * Used by the following functions to iterate through the sptes linked by a
1096 * rmap. All fields are private and not assumed to be used outside.
1098 struct rmap_iterator
{
1099 /* private fields */
1100 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1101 int pos
; /* index of the sptep */
1105 * Iteration must be started by this function. This should also be used after
1106 * removing/dropping sptes from the rmap link because in such cases the
1107 * information in the itererator may not be valid.
1109 * Returns sptep if found, NULL otherwise.
1111 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1112 struct rmap_iterator
*iter
)
1116 if (!rmap_head
->val
)
1119 if (!(rmap_head
->val
& 1)) {
1121 sptep
= (u64
*)rmap_head
->val
;
1125 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1127 sptep
= iter
->desc
->sptes
[iter
->pos
];
1129 BUG_ON(!is_shadow_present_pte(*sptep
));
1134 * Must be used with a valid iterator: e.g. after rmap_get_first().
1136 * Returns sptep if found, NULL otherwise.
1138 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1143 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1145 sptep
= iter
->desc
->sptes
[iter
->pos
];
1150 iter
->desc
= iter
->desc
->more
;
1154 /* desc->sptes[0] cannot be NULL */
1155 sptep
= iter
->desc
->sptes
[iter
->pos
];
1162 BUG_ON(!is_shadow_present_pte(*sptep
));
1166 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1167 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1168 _spte_; _spte_ = rmap_get_next(_iter_))
1170 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1172 if (mmu_spte_clear_track_bits(sptep
))
1173 rmap_remove(kvm
, sptep
);
1177 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1179 if (is_large_pte(*sptep
)) {
1180 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1181 PT_PAGE_TABLE_LEVEL
);
1182 drop_spte(kvm
, sptep
);
1190 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1192 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1193 kvm_flush_remote_tlbs(vcpu
->kvm
);
1197 * Write-protect on the specified @sptep, @pt_protect indicates whether
1198 * spte write-protection is caused by protecting shadow page table.
1200 * Note: write protection is difference between dirty logging and spte
1202 * - for dirty logging, the spte can be set to writable at anytime if
1203 * its dirty bitmap is properly set.
1204 * - for spte protection, the spte can be writable only after unsync-ing
1207 * Return true if tlb need be flushed.
1209 static bool spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool pt_protect
)
1213 if (!is_writable_pte(spte
) &&
1214 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1217 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1220 spte
&= ~SPTE_MMU_WRITEABLE
;
1221 spte
= spte
& ~PT_WRITABLE_MASK
;
1223 return mmu_spte_update(sptep
, spte
);
1226 static bool __rmap_write_protect(struct kvm
*kvm
,
1227 struct kvm_rmap_head
*rmap_head
,
1231 struct rmap_iterator iter
;
1234 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1235 flush
|= spte_write_protect(kvm
, sptep
, pt_protect
);
1240 static bool spte_clear_dirty(struct kvm
*kvm
, u64
*sptep
)
1244 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1246 spte
&= ~shadow_dirty_mask
;
1248 return mmu_spte_update(sptep
, spte
);
1251 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1254 struct rmap_iterator iter
;
1257 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1258 flush
|= spte_clear_dirty(kvm
, sptep
);
1263 static bool spte_set_dirty(struct kvm
*kvm
, u64
*sptep
)
1267 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1269 spte
|= shadow_dirty_mask
;
1271 return mmu_spte_update(sptep
, spte
);
1274 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1277 struct rmap_iterator iter
;
1280 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1281 flush
|= spte_set_dirty(kvm
, sptep
);
1287 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1288 * @kvm: kvm instance
1289 * @slot: slot to protect
1290 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1291 * @mask: indicates which pages we should protect
1293 * Used when we do not need to care about huge page mappings: e.g. during dirty
1294 * logging we do not have any such mappings.
1296 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1297 struct kvm_memory_slot
*slot
,
1298 gfn_t gfn_offset
, unsigned long mask
)
1300 struct kvm_rmap_head
*rmap_head
;
1303 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1304 PT_PAGE_TABLE_LEVEL
, slot
);
1305 __rmap_write_protect(kvm
, rmap_head
, false);
1307 /* clear the first set bit */
1313 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1314 * @kvm: kvm instance
1315 * @slot: slot to clear D-bit
1316 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1317 * @mask: indicates which pages we should clear D-bit
1319 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1321 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1322 struct kvm_memory_slot
*slot
,
1323 gfn_t gfn_offset
, unsigned long mask
)
1325 struct kvm_rmap_head
*rmap_head
;
1328 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1329 PT_PAGE_TABLE_LEVEL
, slot
);
1330 __rmap_clear_dirty(kvm
, rmap_head
);
1332 /* clear the first set bit */
1336 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1339 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1342 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1343 * enable dirty logging for them.
1345 * Used when we do not need to care about huge page mappings: e.g. during dirty
1346 * logging we do not have any such mappings.
1348 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1349 struct kvm_memory_slot
*slot
,
1350 gfn_t gfn_offset
, unsigned long mask
)
1352 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1353 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1356 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1359 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1360 struct kvm_memory_slot
*slot
, u64 gfn
)
1362 struct kvm_rmap_head
*rmap_head
;
1364 bool write_protected
= false;
1366 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1367 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1368 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1371 return write_protected
;
1374 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1376 struct kvm_memory_slot
*slot
;
1378 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1379 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1382 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1385 struct rmap_iterator iter
;
1388 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1389 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1391 drop_spte(kvm
, sptep
);
1398 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1399 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1402 return kvm_zap_rmapp(kvm
, rmap_head
);
1405 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1406 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1410 struct rmap_iterator iter
;
1413 pte_t
*ptep
= (pte_t
*)data
;
1416 WARN_ON(pte_huge(*ptep
));
1417 new_pfn
= pte_pfn(*ptep
);
1420 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1421 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1422 sptep
, *sptep
, gfn
, level
);
1426 if (pte_write(*ptep
)) {
1427 drop_spte(kvm
, sptep
);
1430 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1431 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1433 new_spte
&= ~PT_WRITABLE_MASK
;
1434 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1435 new_spte
&= ~shadow_accessed_mask
;
1437 mmu_spte_clear_track_bits(sptep
);
1438 mmu_spte_set(sptep
, new_spte
);
1443 kvm_flush_remote_tlbs(kvm
);
1448 struct slot_rmap_walk_iterator
{
1450 struct kvm_memory_slot
*slot
;
1456 /* output fields. */
1458 struct kvm_rmap_head
*rmap
;
1461 /* private field. */
1462 struct kvm_rmap_head
*end_rmap
;
1466 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1468 iterator
->level
= level
;
1469 iterator
->gfn
= iterator
->start_gfn
;
1470 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1471 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1476 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1477 struct kvm_memory_slot
*slot
, int start_level
,
1478 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1480 iterator
->slot
= slot
;
1481 iterator
->start_level
= start_level
;
1482 iterator
->end_level
= end_level
;
1483 iterator
->start_gfn
= start_gfn
;
1484 iterator
->end_gfn
= end_gfn
;
1486 rmap_walk_init_level(iterator
, iterator
->start_level
);
1489 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1491 return !!iterator
->rmap
;
1494 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1496 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1497 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1501 if (++iterator
->level
> iterator
->end_level
) {
1502 iterator
->rmap
= NULL
;
1506 rmap_walk_init_level(iterator
, iterator
->level
);
1509 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1510 _start_gfn, _end_gfn, _iter_) \
1511 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1512 _end_level_, _start_gfn, _end_gfn); \
1513 slot_rmap_walk_okay(_iter_); \
1514 slot_rmap_walk_next(_iter_))
1516 static int kvm_handle_hva_range(struct kvm
*kvm
,
1517 unsigned long start
,
1520 int (*handler
)(struct kvm
*kvm
,
1521 struct kvm_rmap_head
*rmap_head
,
1522 struct kvm_memory_slot
*slot
,
1525 unsigned long data
))
1527 struct kvm_memslots
*slots
;
1528 struct kvm_memory_slot
*memslot
;
1529 struct slot_rmap_walk_iterator iterator
;
1533 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1534 slots
= __kvm_memslots(kvm
, i
);
1535 kvm_for_each_memslot(memslot
, slots
) {
1536 unsigned long hva_start
, hva_end
;
1537 gfn_t gfn_start
, gfn_end
;
1539 hva_start
= max(start
, memslot
->userspace_addr
);
1540 hva_end
= min(end
, memslot
->userspace_addr
+
1541 (memslot
->npages
<< PAGE_SHIFT
));
1542 if (hva_start
>= hva_end
)
1545 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1546 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1548 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1549 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1551 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1552 PT_MAX_HUGEPAGE_LEVEL
,
1553 gfn_start
, gfn_end
- 1,
1555 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1556 iterator
.gfn
, iterator
.level
, data
);
1563 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1565 int (*handler
)(struct kvm
*kvm
,
1566 struct kvm_rmap_head
*rmap_head
,
1567 struct kvm_memory_slot
*slot
,
1568 gfn_t gfn
, int level
,
1569 unsigned long data
))
1571 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1574 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1576 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1579 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1581 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1584 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1586 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1589 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1590 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1594 struct rmap_iterator
uninitialized_var(iter
);
1597 BUG_ON(!shadow_accessed_mask
);
1599 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1600 if (*sptep
& shadow_accessed_mask
) {
1602 clear_bit((ffs(shadow_accessed_mask
) - 1),
1603 (unsigned long *)sptep
);
1607 trace_kvm_age_page(gfn
, level
, slot
, young
);
1611 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1612 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1613 int level
, unsigned long data
)
1616 struct rmap_iterator iter
;
1620 * If there's no access bit in the secondary pte set by the
1621 * hardware it's up to gup-fast/gup to set the access bit in
1622 * the primary pte or in the page structure.
1624 if (!shadow_accessed_mask
)
1627 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1628 if (*sptep
& shadow_accessed_mask
) {
1637 #define RMAP_RECYCLE_THRESHOLD 1000
1639 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1641 struct kvm_rmap_head
*rmap_head
;
1642 struct kvm_mmu_page
*sp
;
1644 sp
= page_header(__pa(spte
));
1646 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1648 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1649 kvm_flush_remote_tlbs(vcpu
->kvm
);
1652 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1655 * In case of absence of EPT Access and Dirty Bits supports,
1656 * emulate the accessed bit for EPT, by checking if this page has
1657 * an EPT mapping, and clearing it if it does. On the next access,
1658 * a new EPT mapping will be established.
1659 * This has some overhead, but not as much as the cost of swapping
1660 * out actively used pages or breaking up actively used hugepages.
1662 if (!shadow_accessed_mask
) {
1664 * We are holding the kvm->mmu_lock, and we are blowing up
1665 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1666 * This is correct as long as we don't decouple the mmu_lock
1667 * protected regions (like invalidate_range_start|end does).
1669 kvm
->mmu_notifier_seq
++;
1670 return kvm_handle_hva_range(kvm
, start
, end
, 0,
1674 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1677 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1679 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1683 static int is_empty_shadow_page(u64
*spt
)
1688 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1689 if (is_shadow_present_pte(*pos
)) {
1690 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1699 * This value is the sum of all of the kvm instances's
1700 * kvm->arch.n_used_mmu_pages values. We need a global,
1701 * aggregate version in order to make the slab shrinker
1704 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1706 kvm
->arch
.n_used_mmu_pages
+= nr
;
1707 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1710 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1712 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1713 hlist_del(&sp
->hash_link
);
1714 list_del(&sp
->link
);
1715 free_page((unsigned long)sp
->spt
);
1716 if (!sp
->role
.direct
)
1717 free_page((unsigned long)sp
->gfns
);
1718 kmem_cache_free(mmu_page_header_cache
, sp
);
1721 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1723 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1726 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1727 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1732 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1735 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1738 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1741 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1744 mmu_page_remove_parent_pte(sp
, parent_pte
);
1745 mmu_spte_clear_no_track(parent_pte
);
1748 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1750 struct kvm_mmu_page
*sp
;
1752 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1753 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1755 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1756 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1759 * The active_mmu_pages list is the FIFO list, do not move the
1760 * page until it is zapped. kvm_zap_obsolete_pages depends on
1761 * this feature. See the comments in kvm_zap_obsolete_pages().
1763 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1764 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1768 static void mark_unsync(u64
*spte
);
1769 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1772 struct rmap_iterator iter
;
1774 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1779 static void mark_unsync(u64
*spte
)
1781 struct kvm_mmu_page
*sp
;
1784 sp
= page_header(__pa(spte
));
1785 index
= spte
- sp
->spt
;
1786 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1788 if (sp
->unsync_children
++)
1790 kvm_mmu_mark_parents_unsync(sp
);
1793 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1794 struct kvm_mmu_page
*sp
)
1799 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1803 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1804 struct kvm_mmu_page
*sp
, u64
*spte
,
1810 #define KVM_PAGE_ARRAY_NR 16
1812 struct kvm_mmu_pages
{
1813 struct mmu_page_and_offset
{
1814 struct kvm_mmu_page
*sp
;
1816 } page
[KVM_PAGE_ARRAY_NR
];
1820 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1826 for (i
=0; i
< pvec
->nr
; i
++)
1827 if (pvec
->page
[i
].sp
== sp
)
1830 pvec
->page
[pvec
->nr
].sp
= sp
;
1831 pvec
->page
[pvec
->nr
].idx
= idx
;
1833 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1836 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1838 --sp
->unsync_children
;
1839 WARN_ON((int)sp
->unsync_children
< 0);
1840 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1843 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1844 struct kvm_mmu_pages
*pvec
)
1846 int i
, ret
, nr_unsync_leaf
= 0;
1848 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1849 struct kvm_mmu_page
*child
;
1850 u64 ent
= sp
->spt
[i
];
1852 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1853 clear_unsync_child_bit(sp
, i
);
1857 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1859 if (child
->unsync_children
) {
1860 if (mmu_pages_add(pvec
, child
, i
))
1863 ret
= __mmu_unsync_walk(child
, pvec
);
1865 clear_unsync_child_bit(sp
, i
);
1867 } else if (ret
> 0) {
1868 nr_unsync_leaf
+= ret
;
1871 } else if (child
->unsync
) {
1873 if (mmu_pages_add(pvec
, child
, i
))
1876 clear_unsync_child_bit(sp
, i
);
1879 return nr_unsync_leaf
;
1882 #define INVALID_INDEX (-1)
1884 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1885 struct kvm_mmu_pages
*pvec
)
1888 if (!sp
->unsync_children
)
1891 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1892 return __mmu_unsync_walk(sp
, pvec
);
1895 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1897 WARN_ON(!sp
->unsync
);
1898 trace_kvm_mmu_sync_page(sp
);
1900 --kvm
->stat
.mmu_unsync
;
1903 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1904 struct list_head
*invalid_list
);
1905 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1906 struct list_head
*invalid_list
);
1909 * NOTE: we should pay more attention on the zapped-obsolete page
1910 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1911 * since it has been deleted from active_mmu_pages but still can be found
1914 * for_each_gfn_valid_sp() has skipped that kind of pages.
1916 #define for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1917 hlist_for_each_entry(_sp, \
1918 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1919 if ((_sp)->gfn != (_gfn) || is_obsolete_sp((_kvm), (_sp)) \
1920 || (_sp)->role.invalid) {} else
1922 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1923 for_each_gfn_valid_sp(_kvm, _sp, _gfn) \
1924 if ((_sp)->role.direct) {} else
1926 /* @sp->gfn should be write-protected at the call site */
1927 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1928 struct list_head
*invalid_list
)
1930 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1931 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1935 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
1936 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1943 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1944 struct list_head
*invalid_list
,
1945 bool remote_flush
, bool local_flush
)
1947 if (!list_empty(invalid_list
)) {
1948 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
1953 kvm_flush_remote_tlbs(vcpu
->kvm
);
1954 else if (local_flush
)
1955 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1958 #ifdef CONFIG_KVM_MMU_AUDIT
1959 #include "mmu_audit.c"
1961 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1962 static void mmu_audit_disable(void) { }
1965 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1967 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1970 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1971 struct list_head
*invalid_list
)
1973 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1974 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
1977 /* @gfn should be write-protected at the call site */
1978 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1979 struct list_head
*invalid_list
)
1981 struct kvm_mmu_page
*s
;
1984 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
1988 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1989 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
1995 struct mmu_page_path
{
1996 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
];
1997 unsigned int idx
[PT64_ROOT_LEVEL
];
2000 #define for_each_sp(pvec, sp, parents, i) \
2001 for (i = mmu_pages_first(&pvec, &parents); \
2002 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2003 i = mmu_pages_next(&pvec, &parents, i))
2005 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2006 struct mmu_page_path
*parents
,
2011 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2012 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2013 unsigned idx
= pvec
->page
[n
].idx
;
2014 int level
= sp
->role
.level
;
2016 parents
->idx
[level
-1] = idx
;
2017 if (level
== PT_PAGE_TABLE_LEVEL
)
2020 parents
->parent
[level
-2] = sp
;
2026 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2027 struct mmu_page_path
*parents
)
2029 struct kvm_mmu_page
*sp
;
2035 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2037 sp
= pvec
->page
[0].sp
;
2038 level
= sp
->role
.level
;
2039 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2041 parents
->parent
[level
-2] = sp
;
2043 /* Also set up a sentinel. Further entries in pvec are all
2044 * children of sp, so this element is never overwritten.
2046 parents
->parent
[level
-1] = NULL
;
2047 return mmu_pages_next(pvec
, parents
, 0);
2050 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2052 struct kvm_mmu_page
*sp
;
2053 unsigned int level
= 0;
2056 unsigned int idx
= parents
->idx
[level
];
2057 sp
= parents
->parent
[level
];
2061 WARN_ON(idx
== INVALID_INDEX
);
2062 clear_unsync_child_bit(sp
, idx
);
2064 } while (!sp
->unsync_children
);
2067 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2068 struct kvm_mmu_page
*parent
)
2071 struct kvm_mmu_page
*sp
;
2072 struct mmu_page_path parents
;
2073 struct kvm_mmu_pages pages
;
2074 LIST_HEAD(invalid_list
);
2077 while (mmu_unsync_walk(parent
, &pages
)) {
2078 bool protected = false;
2080 for_each_sp(pages
, sp
, parents
, i
)
2081 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2084 kvm_flush_remote_tlbs(vcpu
->kvm
);
2088 for_each_sp(pages
, sp
, parents
, i
) {
2089 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2090 mmu_pages_clear_parents(&parents
);
2092 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2093 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2094 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2099 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2102 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2104 atomic_set(&sp
->write_flooding_count
, 0);
2107 static void clear_sp_write_flooding_count(u64
*spte
)
2109 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2111 __clear_sp_write_flooding_count(sp
);
2114 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2121 union kvm_mmu_page_role role
;
2123 struct kvm_mmu_page
*sp
;
2124 bool need_sync
= false;
2126 LIST_HEAD(invalid_list
);
2128 role
= vcpu
->arch
.mmu
.base_role
;
2130 role
.direct
= direct
;
2133 role
.access
= access
;
2134 if (!vcpu
->arch
.mmu
.direct_map
2135 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2136 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2137 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2138 role
.quadrant
= quadrant
;
2140 for_each_gfn_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2141 if (!need_sync
&& sp
->unsync
)
2144 if (sp
->role
.word
!= role
.word
)
2148 /* The page is good, but __kvm_sync_page might still end
2149 * up zapping it. If so, break in order to rebuild it.
2151 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2154 WARN_ON(!list_empty(&invalid_list
));
2155 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2158 if (sp
->unsync_children
)
2159 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2161 __clear_sp_write_flooding_count(sp
);
2162 trace_kvm_mmu_get_page(sp
, false);
2166 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2168 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2172 hlist_add_head(&sp
->hash_link
,
2173 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2176 * we should do write protection before syncing pages
2177 * otherwise the content of the synced shadow page may
2178 * be inconsistent with guest page table.
2180 account_shadowed(vcpu
->kvm
, sp
);
2181 if (level
== PT_PAGE_TABLE_LEVEL
&&
2182 rmap_write_protect(vcpu
, gfn
))
2183 kvm_flush_remote_tlbs(vcpu
->kvm
);
2185 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2186 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2188 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2189 clear_page(sp
->spt
);
2190 trace_kvm_mmu_get_page(sp
, true);
2192 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2196 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2197 struct kvm_vcpu
*vcpu
, u64 addr
)
2199 iterator
->addr
= addr
;
2200 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2201 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2203 if (iterator
->level
== PT64_ROOT_LEVEL
&&
2204 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
2205 !vcpu
->arch
.mmu
.direct_map
)
2208 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2209 iterator
->shadow_addr
2210 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2211 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2213 if (!iterator
->shadow_addr
)
2214 iterator
->level
= 0;
2218 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2220 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2223 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2224 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2228 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2231 if (is_last_spte(spte
, iterator
->level
)) {
2232 iterator
->level
= 0;
2236 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2240 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2242 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2245 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2246 struct kvm_mmu_page
*sp
)
2250 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2252 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2253 shadow_user_mask
| shadow_x_mask
| shadow_accessed_mask
;
2255 mmu_spte_set(sptep
, spte
);
2257 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2259 if (sp
->unsync_children
|| sp
->unsync
)
2263 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2264 unsigned direct_access
)
2266 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2267 struct kvm_mmu_page
*child
;
2270 * For the direct sp, if the guest pte's dirty bit
2271 * changed form clean to dirty, it will corrupt the
2272 * sp's access: allow writable in the read-only sp,
2273 * so we should update the spte at this point to get
2274 * a new sp with the correct access.
2276 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2277 if (child
->role
.access
== direct_access
)
2280 drop_parent_pte(child
, sptep
);
2281 kvm_flush_remote_tlbs(vcpu
->kvm
);
2285 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2289 struct kvm_mmu_page
*child
;
2292 if (is_shadow_present_pte(pte
)) {
2293 if (is_last_spte(pte
, sp
->role
.level
)) {
2294 drop_spte(kvm
, spte
);
2295 if (is_large_pte(pte
))
2298 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2299 drop_parent_pte(child
, spte
);
2304 if (is_mmio_spte(pte
))
2305 mmu_spte_clear_no_track(spte
);
2310 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2311 struct kvm_mmu_page
*sp
)
2315 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2316 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2319 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2322 struct rmap_iterator iter
;
2324 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2325 drop_parent_pte(sp
, sptep
);
2328 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2329 struct kvm_mmu_page
*parent
,
2330 struct list_head
*invalid_list
)
2333 struct mmu_page_path parents
;
2334 struct kvm_mmu_pages pages
;
2336 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2339 while (mmu_unsync_walk(parent
, &pages
)) {
2340 struct kvm_mmu_page
*sp
;
2342 for_each_sp(pages
, sp
, parents
, i
) {
2343 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2344 mmu_pages_clear_parents(&parents
);
2352 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2353 struct list_head
*invalid_list
)
2357 trace_kvm_mmu_prepare_zap_page(sp
);
2358 ++kvm
->stat
.mmu_shadow_zapped
;
2359 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2360 kvm_mmu_page_unlink_children(kvm
, sp
);
2361 kvm_mmu_unlink_parents(kvm
, sp
);
2363 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2364 unaccount_shadowed(kvm
, sp
);
2367 kvm_unlink_unsync_page(kvm
, sp
);
2368 if (!sp
->root_count
) {
2371 list_move(&sp
->link
, invalid_list
);
2372 kvm_mod_used_mmu_pages(kvm
, -1);
2374 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2377 * The obsolete pages can not be used on any vcpus.
2378 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2380 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2381 kvm_reload_remote_mmus(kvm
);
2384 sp
->role
.invalid
= 1;
2388 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2389 struct list_head
*invalid_list
)
2391 struct kvm_mmu_page
*sp
, *nsp
;
2393 if (list_empty(invalid_list
))
2397 * We need to make sure everyone sees our modifications to
2398 * the page tables and see changes to vcpu->mode here. The barrier
2399 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2400 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2402 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2403 * guest mode and/or lockless shadow page table walks.
2405 kvm_flush_remote_tlbs(kvm
);
2407 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2408 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2409 kvm_mmu_free_page(sp
);
2413 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2414 struct list_head
*invalid_list
)
2416 struct kvm_mmu_page
*sp
;
2418 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2421 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2422 struct kvm_mmu_page
, link
);
2423 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2429 * Changing the number of mmu pages allocated to the vm
2430 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2432 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2434 LIST_HEAD(invalid_list
);
2436 spin_lock(&kvm
->mmu_lock
);
2438 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2439 /* Need to free some mmu pages to achieve the goal. */
2440 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2441 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2444 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2445 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2448 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2450 spin_unlock(&kvm
->mmu_lock
);
2453 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2455 struct kvm_mmu_page
*sp
;
2456 LIST_HEAD(invalid_list
);
2459 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2461 spin_lock(&kvm
->mmu_lock
);
2462 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2463 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2466 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2468 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2469 spin_unlock(&kvm
->mmu_lock
);
2473 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2475 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2477 trace_kvm_mmu_unsync_page(sp
);
2478 ++vcpu
->kvm
->stat
.mmu_unsync
;
2481 kvm_mmu_mark_parents_unsync(sp
);
2484 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2487 struct kvm_mmu_page
*sp
;
2489 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2492 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2499 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2500 kvm_unsync_page(vcpu
, sp
);
2506 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2509 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2514 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2515 unsigned pte_access
, int level
,
2516 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2517 bool can_unsync
, bool host_writable
)
2522 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2526 * For the EPT case, shadow_present_mask is 0 if hardware
2527 * supports exec-only page table entries. In that case,
2528 * ACC_USER_MASK and shadow_user_mask are used to represent
2529 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2531 spte
|= shadow_present_mask
;
2533 spte
|= shadow_accessed_mask
;
2535 if (pte_access
& ACC_EXEC_MASK
)
2536 spte
|= shadow_x_mask
;
2538 spte
|= shadow_nx_mask
;
2540 if (pte_access
& ACC_USER_MASK
)
2541 spte
|= shadow_user_mask
;
2543 if (level
> PT_PAGE_TABLE_LEVEL
)
2544 spte
|= PT_PAGE_SIZE_MASK
;
2546 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2547 kvm_is_mmio_pfn(pfn
));
2550 spte
|= SPTE_HOST_WRITEABLE
;
2552 pte_access
&= ~ACC_WRITE_MASK
;
2554 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2556 if (pte_access
& ACC_WRITE_MASK
) {
2559 * Other vcpu creates new sp in the window between
2560 * mapping_level() and acquiring mmu-lock. We can
2561 * allow guest to retry the access, the mapping can
2562 * be fixed if guest refault.
2564 if (level
> PT_PAGE_TABLE_LEVEL
&&
2565 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2568 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2571 * Optimization: for pte sync, if spte was writable the hash
2572 * lookup is unnecessary (and expensive). Write protection
2573 * is responsibility of mmu_get_page / kvm_sync_page.
2574 * Same reasoning can be applied to dirty page accounting.
2576 if (!can_unsync
&& is_writable_pte(*sptep
))
2579 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2580 pgprintk("%s: found shadow page for %llx, marking ro\n",
2583 pte_access
&= ~ACC_WRITE_MASK
;
2584 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2588 if (pte_access
& ACC_WRITE_MASK
) {
2589 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2590 spte
|= shadow_dirty_mask
;
2594 if (mmu_spte_update(sptep
, spte
))
2595 kvm_flush_remote_tlbs(vcpu
->kvm
);
2600 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2601 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2602 bool speculative
, bool host_writable
)
2604 int was_rmapped
= 0;
2606 bool emulate
= false;
2608 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2609 *sptep
, write_fault
, gfn
);
2611 if (is_shadow_present_pte(*sptep
)) {
2613 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2614 * the parent of the now unreachable PTE.
2616 if (level
> PT_PAGE_TABLE_LEVEL
&&
2617 !is_large_pte(*sptep
)) {
2618 struct kvm_mmu_page
*child
;
2621 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2622 drop_parent_pte(child
, sptep
);
2623 kvm_flush_remote_tlbs(vcpu
->kvm
);
2624 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2625 pgprintk("hfn old %llx new %llx\n",
2626 spte_to_pfn(*sptep
), pfn
);
2627 drop_spte(vcpu
->kvm
, sptep
);
2628 kvm_flush_remote_tlbs(vcpu
->kvm
);
2633 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2634 true, host_writable
)) {
2637 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2640 if (unlikely(is_mmio_spte(*sptep
)))
2643 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2644 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2645 is_large_pte(*sptep
)? "2MB" : "4kB",
2646 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2648 if (!was_rmapped
&& is_large_pte(*sptep
))
2649 ++vcpu
->kvm
->stat
.lpages
;
2651 if (is_shadow_present_pte(*sptep
)) {
2653 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2654 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2655 rmap_recycle(vcpu
, sptep
, gfn
);
2659 kvm_release_pfn_clean(pfn
);
2664 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2667 struct kvm_memory_slot
*slot
;
2669 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2671 return KVM_PFN_ERR_FAULT
;
2673 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2676 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2677 struct kvm_mmu_page
*sp
,
2678 u64
*start
, u64
*end
)
2680 struct page
*pages
[PTE_PREFETCH_NUM
];
2681 struct kvm_memory_slot
*slot
;
2682 unsigned access
= sp
->role
.access
;
2686 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2687 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2691 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2695 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2696 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2697 page_to_pfn(pages
[i
]), true, true);
2702 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2703 struct kvm_mmu_page
*sp
, u64
*sptep
)
2705 u64
*spte
, *start
= NULL
;
2708 WARN_ON(!sp
->role
.direct
);
2710 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2713 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2714 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2717 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2725 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2727 struct kvm_mmu_page
*sp
;
2730 * Since it's no accessed bit on EPT, it's no way to
2731 * distinguish between actually accessed translations
2732 * and prefetched, so disable pte prefetch if EPT is
2735 if (!shadow_accessed_mask
)
2738 sp
= page_header(__pa(sptep
));
2739 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2742 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2745 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2746 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2748 struct kvm_shadow_walk_iterator iterator
;
2749 struct kvm_mmu_page
*sp
;
2753 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2756 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2757 if (iterator
.level
== level
) {
2758 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2759 write
, level
, gfn
, pfn
, prefault
,
2761 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2762 ++vcpu
->stat
.pf_fixed
;
2766 drop_large_spte(vcpu
, iterator
.sptep
);
2767 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2768 u64 base_addr
= iterator
.addr
;
2770 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2771 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2772 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2773 iterator
.level
- 1, 1, ACC_ALL
);
2775 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2781 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2785 info
.si_signo
= SIGBUS
;
2787 info
.si_code
= BUS_MCEERR_AR
;
2788 info
.si_addr
= (void __user
*)address
;
2789 info
.si_addr_lsb
= PAGE_SHIFT
;
2791 send_sig_info(SIGBUS
, &info
, tsk
);
2794 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2797 * Do not cache the mmio info caused by writing the readonly gfn
2798 * into the spte otherwise read access on readonly gfn also can
2799 * caused mmio page fault and treat it as mmio access.
2800 * Return 1 to tell kvm to emulate it.
2802 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2805 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2806 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
2813 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2814 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
2817 kvm_pfn_t pfn
= *pfnp
;
2819 int level
= *levelp
;
2822 * Check if it's a transparent hugepage. If this would be an
2823 * hugetlbfs page, level wouldn't be set to
2824 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2827 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
2828 level
== PT_PAGE_TABLE_LEVEL
&&
2829 PageTransCompoundMap(pfn_to_page(pfn
)) &&
2830 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
2833 * mmu_notifier_retry was successful and we hold the
2834 * mmu_lock here, so the pmd can't become splitting
2835 * from under us, and in turn
2836 * __split_huge_page_refcount() can't run from under
2837 * us and we can safely transfer the refcount from
2838 * PG_tail to PG_head as we switch the pfn to tail to
2841 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2842 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2843 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2847 kvm_release_pfn_clean(pfn
);
2855 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2856 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
2858 /* The pfn is invalid, report the error! */
2859 if (unlikely(is_error_pfn(pfn
))) {
2860 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2864 if (unlikely(is_noslot_pfn(pfn
)))
2865 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2870 static bool page_fault_can_be_fast(u32 error_code
)
2873 * Do not fix the mmio spte with invalid generation number which
2874 * need to be updated by slow page fault path.
2876 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2880 * #PF can be fast only if the shadow page table is present and it
2881 * is caused by write-protect, that means we just need change the
2882 * W bit of the spte which can be done out of mmu-lock.
2884 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2885 !(error_code
& PFERR_WRITE_MASK
))
2892 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2893 u64
*sptep
, u64 spte
)
2897 WARN_ON(!sp
->role
.direct
);
2900 * The gfn of direct spte is stable since it is calculated
2903 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2906 * Theoretically we could also set dirty bit (and flush TLB) here in
2907 * order to eliminate unnecessary PML logging. See comments in
2908 * set_spte. But fast_page_fault is very unlikely to happen with PML
2909 * enabled, so we do not do this. This might result in the same GPA
2910 * to be logged in PML buffer again when the write really happens, and
2911 * eventually to be called by mark_page_dirty twice. But it's also no
2912 * harm. This also avoids the TLB flush needed after setting dirty bit
2913 * so non-PML cases won't be impacted.
2915 * Compare with set_spte where instead shadow_dirty_mask is set.
2917 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2918 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2925 * - true: let the vcpu to access on the same address again.
2926 * - false: let the real page fault path to fix it.
2928 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2931 struct kvm_shadow_walk_iterator iterator
;
2932 struct kvm_mmu_page
*sp
;
2936 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2939 if (!page_fault_can_be_fast(error_code
))
2942 walk_shadow_page_lockless_begin(vcpu
);
2943 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2944 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2948 * If the mapping has been changed, let the vcpu fault on the
2949 * same address again.
2951 if (!is_shadow_present_pte(spte
)) {
2956 sp
= page_header(__pa(iterator
.sptep
));
2957 if (!is_last_spte(spte
, sp
->role
.level
))
2961 * Check if it is a spurious fault caused by TLB lazily flushed.
2963 * Need not check the access of upper level table entries since
2964 * they are always ACC_ALL.
2966 if (is_writable_pte(spte
)) {
2972 * Currently, to simplify the code, only the spte write-protected
2973 * by dirty-log can be fast fixed.
2975 if (!spte_is_locklessly_modifiable(spte
))
2979 * Do not fix write-permission on the large spte since we only dirty
2980 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2981 * that means other pages are missed if its slot is dirty-logged.
2983 * Instead, we let the slow page fault path create a normal spte to
2986 * See the comments in kvm_arch_commit_memory_region().
2988 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2992 * Currently, fast page fault only works for direct mapping since
2993 * the gfn is not stable for indirect shadow page.
2994 * See Documentation/virtual/kvm/locking.txt to get more detail.
2996 ret
= fast_pf_fix_direct_spte(vcpu
, sp
, iterator
.sptep
, spte
);
2998 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3000 walk_shadow_page_lockless_end(vcpu
);
3005 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3006 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3007 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3009 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3010 gfn_t gfn
, bool prefault
)
3014 bool force_pt_level
= false;
3016 unsigned long mmu_seq
;
3017 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3019 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3020 if (likely(!force_pt_level
)) {
3022 * This path builds a PAE pagetable - so we can map
3023 * 2mb pages at maximum. Therefore check if the level
3024 * is larger than that.
3026 if (level
> PT_DIRECTORY_LEVEL
)
3027 level
= PT_DIRECTORY_LEVEL
;
3029 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3032 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3035 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3038 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3041 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3044 spin_lock(&vcpu
->kvm
->mmu_lock
);
3045 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3047 make_mmu_pages_available(vcpu
);
3048 if (likely(!force_pt_level
))
3049 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3050 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3051 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3056 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3057 kvm_release_pfn_clean(pfn
);
3062 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3065 struct kvm_mmu_page
*sp
;
3066 LIST_HEAD(invalid_list
);
3068 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3071 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
3072 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
3073 vcpu
->arch
.mmu
.direct_map
)) {
3074 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3076 spin_lock(&vcpu
->kvm
->mmu_lock
);
3077 sp
= page_header(root
);
3079 if (!sp
->root_count
&& sp
->role
.invalid
) {
3080 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3081 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3083 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3084 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3088 spin_lock(&vcpu
->kvm
->mmu_lock
);
3089 for (i
= 0; i
< 4; ++i
) {
3090 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3093 root
&= PT64_BASE_ADDR_MASK
;
3094 sp
= page_header(root
);
3096 if (!sp
->root_count
&& sp
->role
.invalid
)
3097 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3100 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3102 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3103 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3104 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3107 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3111 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3112 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3119 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3121 struct kvm_mmu_page
*sp
;
3124 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3125 spin_lock(&vcpu
->kvm
->mmu_lock
);
3126 make_mmu_pages_available(vcpu
);
3127 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
, 1, ACC_ALL
);
3129 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3130 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3131 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3132 for (i
= 0; i
< 4; ++i
) {
3133 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3135 MMU_WARN_ON(VALID_PAGE(root
));
3136 spin_lock(&vcpu
->kvm
->mmu_lock
);
3137 make_mmu_pages_available(vcpu
);
3138 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3139 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3140 root
= __pa(sp
->spt
);
3142 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3143 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3145 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3152 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3154 struct kvm_mmu_page
*sp
;
3159 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3161 if (mmu_check_root(vcpu
, root_gfn
))
3165 * Do we shadow a long mode page table? If so we need to
3166 * write-protect the guests page table root.
3168 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3169 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3171 MMU_WARN_ON(VALID_PAGE(root
));
3173 spin_lock(&vcpu
->kvm
->mmu_lock
);
3174 make_mmu_pages_available(vcpu
);
3175 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3177 root
= __pa(sp
->spt
);
3179 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3180 vcpu
->arch
.mmu
.root_hpa
= root
;
3185 * We shadow a 32 bit page table. This may be a legacy 2-level
3186 * or a PAE 3-level page table. In either case we need to be aware that
3187 * the shadow page table may be a PAE or a long mode page table.
3189 pm_mask
= PT_PRESENT_MASK
;
3190 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3191 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3193 for (i
= 0; i
< 4; ++i
) {
3194 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3196 MMU_WARN_ON(VALID_PAGE(root
));
3197 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3198 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3199 if (!(pdptr
& PT_PRESENT_MASK
)) {
3200 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3203 root_gfn
= pdptr
>> PAGE_SHIFT
;
3204 if (mmu_check_root(vcpu
, root_gfn
))
3207 spin_lock(&vcpu
->kvm
->mmu_lock
);
3208 make_mmu_pages_available(vcpu
);
3209 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3211 root
= __pa(sp
->spt
);
3213 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3215 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3217 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3220 * If we shadow a 32 bit page table with a long mode page
3221 * table we enter this path.
3223 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3224 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3226 * The additional page necessary for this is only
3227 * allocated on demand.
3232 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3233 if (lm_root
== NULL
)
3236 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3238 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3241 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3247 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3249 if (vcpu
->arch
.mmu
.direct_map
)
3250 return mmu_alloc_direct_roots(vcpu
);
3252 return mmu_alloc_shadow_roots(vcpu
);
3255 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3258 struct kvm_mmu_page
*sp
;
3260 if (vcpu
->arch
.mmu
.direct_map
)
3263 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3266 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3267 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3268 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3269 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3270 sp
= page_header(root
);
3271 mmu_sync_children(vcpu
, sp
);
3272 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3275 for (i
= 0; i
< 4; ++i
) {
3276 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3278 if (root
&& VALID_PAGE(root
)) {
3279 root
&= PT64_BASE_ADDR_MASK
;
3280 sp
= page_header(root
);
3281 mmu_sync_children(vcpu
, sp
);
3284 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3287 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3289 spin_lock(&vcpu
->kvm
->mmu_lock
);
3290 mmu_sync_roots(vcpu
);
3291 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3293 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3295 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3296 u32 access
, struct x86_exception
*exception
)
3299 exception
->error_code
= 0;
3303 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3305 struct x86_exception
*exception
)
3308 exception
->error_code
= 0;
3309 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3313 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3315 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3317 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3318 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3321 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3323 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3326 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3328 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3331 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3334 return vcpu_match_mmio_gpa(vcpu
, addr
);
3336 return vcpu_match_mmio_gva(vcpu
, addr
);
3339 /* return true if reserved bit is detected on spte. */
3341 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3343 struct kvm_shadow_walk_iterator iterator
;
3344 u64 sptes
[PT64_ROOT_LEVEL
], spte
= 0ull;
3346 bool reserved
= false;
3348 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3351 walk_shadow_page_lockless_begin(vcpu
);
3353 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3354 leaf
= root
= iterator
.level
;
3355 shadow_walk_okay(&iterator
);
3356 __shadow_walk_next(&iterator
, spte
)) {
3357 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3359 sptes
[leaf
- 1] = spte
;
3362 if (!is_shadow_present_pte(spte
))
3365 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3369 walk_shadow_page_lockless_end(vcpu
);
3372 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3374 while (root
> leaf
) {
3375 pr_err("------ spte 0x%llx level %d.\n",
3376 sptes
[root
- 1], root
);
3385 int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3390 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3391 return RET_MMIO_PF_EMULATE
;
3393 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3394 if (WARN_ON(reserved
))
3395 return RET_MMIO_PF_BUG
;
3397 if (is_mmio_spte(spte
)) {
3398 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3399 unsigned access
= get_mmio_spte_access(spte
);
3401 if (!check_mmio_spte(vcpu
, spte
))
3402 return RET_MMIO_PF_INVALID
;
3407 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3408 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3409 return RET_MMIO_PF_EMULATE
;
3413 * If the page table is zapped by other cpus, let CPU fault again on
3416 return RET_MMIO_PF_RETRY
;
3418 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3420 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3421 u32 error_code
, gfn_t gfn
)
3423 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3426 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3427 !(error_code
& PFERR_WRITE_MASK
))
3431 * guest is writing the page which is write tracked which can
3432 * not be fixed by page fault handler.
3434 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3440 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3442 struct kvm_shadow_walk_iterator iterator
;
3445 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3448 walk_shadow_page_lockless_begin(vcpu
);
3449 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3450 clear_sp_write_flooding_count(iterator
.sptep
);
3451 if (!is_shadow_present_pte(spte
))
3454 walk_shadow_page_lockless_end(vcpu
);
3457 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3458 u32 error_code
, bool prefault
)
3460 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3463 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3465 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3468 r
= mmu_topup_memory_caches(vcpu
);
3472 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3475 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3476 error_code
, gfn
, prefault
);
3479 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3481 struct kvm_arch_async_pf arch
;
3483 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3485 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3486 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3488 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3491 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3493 if (unlikely(!lapic_in_kernel(vcpu
) ||
3494 kvm_event_needs_reinjection(vcpu
)))
3497 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3500 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3501 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3503 struct kvm_memory_slot
*slot
;
3506 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3508 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3510 return false; /* *pfn has correct page already */
3512 if (!prefault
&& can_do_async_pf(vcpu
)) {
3513 trace_kvm_try_async_get_page(gva
, gfn
);
3514 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3515 trace_kvm_async_pf_doublefault(gva
, gfn
);
3516 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3518 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3522 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3527 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3529 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3531 gfn
&= ~(page_num
- 1);
3533 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3536 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3542 bool force_pt_level
;
3543 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3544 unsigned long mmu_seq
;
3545 int write
= error_code
& PFERR_WRITE_MASK
;
3548 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3550 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3553 r
= mmu_topup_memory_caches(vcpu
);
3557 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3558 PT_DIRECTORY_LEVEL
);
3559 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3560 if (likely(!force_pt_level
)) {
3561 if (level
> PT_DIRECTORY_LEVEL
&&
3562 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3563 level
= PT_DIRECTORY_LEVEL
;
3564 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3567 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3570 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3573 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3576 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3579 spin_lock(&vcpu
->kvm
->mmu_lock
);
3580 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3582 make_mmu_pages_available(vcpu
);
3583 if (likely(!force_pt_level
))
3584 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3585 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3586 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3591 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3592 kvm_release_pfn_clean(pfn
);
3596 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3597 struct kvm_mmu
*context
)
3599 context
->page_fault
= nonpaging_page_fault
;
3600 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3601 context
->sync_page
= nonpaging_sync_page
;
3602 context
->invlpg
= nonpaging_invlpg
;
3603 context
->update_pte
= nonpaging_update_pte
;
3604 context
->root_level
= 0;
3605 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3606 context
->root_hpa
= INVALID_PAGE
;
3607 context
->direct_map
= true;
3608 context
->nx
= false;
3611 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3613 mmu_free_roots(vcpu
);
3616 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3618 return kvm_read_cr3(vcpu
);
3621 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3622 struct x86_exception
*fault
)
3624 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3627 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3628 unsigned access
, int *nr_present
)
3630 if (unlikely(is_mmio_spte(*sptep
))) {
3631 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3632 mmu_spte_clear_no_track(sptep
);
3637 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3644 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3645 unsigned level
, unsigned gpte
)
3648 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3649 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3650 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3652 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3655 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3656 * If it is clear, there are no large pages at this level, so clear
3657 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3659 gpte
&= level
- mmu
->last_nonleaf_level
;
3661 return gpte
& PT_PAGE_SIZE_MASK
;
3664 #define PTTYPE_EPT 18 /* arbitrary */
3665 #define PTTYPE PTTYPE_EPT
3666 #include "paging_tmpl.h"
3670 #include "paging_tmpl.h"
3674 #include "paging_tmpl.h"
3678 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3679 struct rsvd_bits_validate
*rsvd_check
,
3680 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
3683 u64 exb_bit_rsvd
= 0;
3684 u64 gbpages_bit_rsvd
= 0;
3685 u64 nonleaf_bit8_rsvd
= 0;
3687 rsvd_check
->bad_mt_xwr
= 0;
3690 exb_bit_rsvd
= rsvd_bits(63, 63);
3692 gbpages_bit_rsvd
= rsvd_bits(7, 7);
3695 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3696 * leaf entries) on AMD CPUs only.
3699 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
3702 case PT32_ROOT_LEVEL
:
3703 /* no rsvd bits for 2 level 4K page table entries */
3704 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
3705 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
3706 rsvd_check
->rsvd_bits_mask
[1][0] =
3707 rsvd_check
->rsvd_bits_mask
[0][0];
3710 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
3714 if (is_cpuid_PSE36())
3715 /* 36bits PSE 4MB page */
3716 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3718 /* 32 bits PSE 4MB page */
3719 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3721 case PT32E_ROOT_LEVEL
:
3722 rsvd_check
->rsvd_bits_mask
[0][2] =
3723 rsvd_bits(maxphyaddr
, 63) |
3724 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3725 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3726 rsvd_bits(maxphyaddr
, 62); /* PDE */
3727 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3728 rsvd_bits(maxphyaddr
, 62); /* PTE */
3729 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3730 rsvd_bits(maxphyaddr
, 62) |
3731 rsvd_bits(13, 20); /* large page */
3732 rsvd_check
->rsvd_bits_mask
[1][0] =
3733 rsvd_check
->rsvd_bits_mask
[0][0];
3735 case PT64_ROOT_LEVEL
:
3736 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3737 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3738 rsvd_bits(maxphyaddr
, 51);
3739 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3740 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
3741 rsvd_bits(maxphyaddr
, 51);
3742 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3743 rsvd_bits(maxphyaddr
, 51);
3744 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3745 rsvd_bits(maxphyaddr
, 51);
3746 rsvd_check
->rsvd_bits_mask
[1][3] =
3747 rsvd_check
->rsvd_bits_mask
[0][3];
3748 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3749 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
3751 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3752 rsvd_bits(maxphyaddr
, 51) |
3753 rsvd_bits(13, 20); /* large page */
3754 rsvd_check
->rsvd_bits_mask
[1][0] =
3755 rsvd_check
->rsvd_bits_mask
[0][0];
3760 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3761 struct kvm_mmu
*context
)
3763 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
3764 cpuid_maxphyaddr(vcpu
), context
->root_level
,
3765 context
->nx
, guest_cpuid_has_gbpages(vcpu
),
3766 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
3770 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
3771 int maxphyaddr
, bool execonly
)
3775 rsvd_check
->rsvd_bits_mask
[0][3] =
3776 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
3777 rsvd_check
->rsvd_bits_mask
[0][2] =
3778 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3779 rsvd_check
->rsvd_bits_mask
[0][1] =
3780 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3781 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
3784 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
3785 rsvd_check
->rsvd_bits_mask
[1][2] =
3786 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
3787 rsvd_check
->rsvd_bits_mask
[1][1] =
3788 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
3789 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
3791 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
3792 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
3793 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
3794 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3795 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3797 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3798 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
3800 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
3803 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
3804 struct kvm_mmu
*context
, bool execonly
)
3806 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
3807 cpuid_maxphyaddr(vcpu
), execonly
);
3811 * the page table on host is the shadow page table for the page
3812 * table in guest or amd nested guest, its mmu features completely
3813 * follow the features in guest.
3816 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3818 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
3821 * Passing "true" to the last argument is okay; it adds a check
3822 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3824 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
3825 boot_cpu_data
.x86_phys_bits
,
3826 context
->shadow_root_level
, uses_nx
,
3827 guest_cpuid_has_gbpages(vcpu
), is_pse(vcpu
),
3830 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
3832 static inline bool boot_cpu_is_amd(void)
3834 WARN_ON_ONCE(!tdp_enabled
);
3835 return shadow_x_mask
== 0;
3839 * the direct page table on host, use as much mmu features as
3840 * possible, however, kvm currently does not do execution-protection.
3843 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
3844 struct kvm_mmu
*context
)
3846 if (boot_cpu_is_amd())
3847 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
3848 boot_cpu_data
.x86_phys_bits
,
3849 context
->shadow_root_level
, false,
3850 boot_cpu_has(X86_FEATURE_GBPAGES
),
3853 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
3854 boot_cpu_data
.x86_phys_bits
,
3860 * as the comments in reset_shadow_zero_bits_mask() except it
3861 * is the shadow page table for intel nested guest.
3864 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
3865 struct kvm_mmu
*context
, bool execonly
)
3867 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
3868 boot_cpu_data
.x86_phys_bits
, execonly
);
3871 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
3872 struct kvm_mmu
*mmu
, bool ept
)
3874 unsigned bit
, byte
, pfec
;
3876 bool fault
, x
, w
, u
, wf
, uf
, ff
, smapf
, cr4_smap
, cr4_smep
, smap
= 0;
3878 cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3879 cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
3880 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
3883 wf
= pfec
& PFERR_WRITE_MASK
;
3884 uf
= pfec
& PFERR_USER_MASK
;
3885 ff
= pfec
& PFERR_FETCH_MASK
;
3887 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3888 * subject to SMAP restrictions, and cleared otherwise. The
3889 * bit is only meaningful if the SMAP bit is set in CR4.
3891 smapf
= !(pfec
& PFERR_RSVD_MASK
);
3892 for (bit
= 0; bit
< 8; ++bit
) {
3893 x
= bit
& ACC_EXEC_MASK
;
3894 w
= bit
& ACC_WRITE_MASK
;
3895 u
= bit
& ACC_USER_MASK
;
3898 /* Not really needed: !nx will cause pte.nx to fault */
3900 /* Allow supervisor writes if !cr0.wp */
3901 w
|= !is_write_protection(vcpu
) && !uf
;
3902 /* Disallow supervisor fetches of user code if cr4.smep */
3903 x
&= !(cr4_smep
&& u
&& !uf
);
3906 * SMAP:kernel-mode data accesses from user-mode
3907 * mappings should fault. A fault is considered
3908 * as a SMAP violation if all of the following
3909 * conditions are ture:
3910 * - X86_CR4_SMAP is set in CR4
3911 * - An user page is accessed
3912 * - Page fault in kernel mode
3913 * - if CPL = 3 or X86_EFLAGS_AC is clear
3915 * Here, we cover the first three conditions.
3916 * The fourth is computed dynamically in
3917 * permission_fault() and is in smapf.
3919 * Also, SMAP does not affect instruction
3920 * fetches, add the !ff check here to make it
3923 smap
= cr4_smap
&& u
&& !uf
&& !ff
;
3926 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
) ||
3928 map
|= fault
<< bit
;
3930 mmu
->permissions
[byte
] = map
;
3935 * PKU is an additional mechanism by which the paging controls access to
3936 * user-mode addresses based on the value in the PKRU register. Protection
3937 * key violations are reported through a bit in the page fault error code.
3938 * Unlike other bits of the error code, the PK bit is not known at the
3939 * call site of e.g. gva_to_gpa; it must be computed directly in
3940 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3941 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3943 * In particular the following conditions come from the error code, the
3944 * page tables and the machine state:
3945 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3946 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3947 * - PK is always zero if U=0 in the page tables
3948 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3950 * The PKRU bitmask caches the result of these four conditions. The error
3951 * code (minus the P bit) and the page table's U bit form an index into the
3952 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3953 * with the two bits of the PKRU register corresponding to the protection key.
3954 * For the first three conditions above the bits will be 00, thus masking
3955 * away both AD and WD. For all reads or if the last condition holds, WD
3956 * only will be masked away.
3958 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3969 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3970 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
3975 wp
= is_write_protection(vcpu
);
3977 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
3978 unsigned pfec
, pkey_bits
;
3979 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
3982 ff
= pfec
& PFERR_FETCH_MASK
;
3983 uf
= pfec
& PFERR_USER_MASK
;
3984 wf
= pfec
& PFERR_WRITE_MASK
;
3986 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3987 pte_user
= pfec
& PFERR_RSVD_MASK
;
3990 * Only need to check the access which is not an
3991 * instruction fetch and is to a user page.
3993 check_pkey
= (!ff
&& pte_user
);
3995 * write access is controlled by PKRU if it is a
3996 * user access or CR0.WP = 1.
3998 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4000 /* PKRU.AD stops both read and write access. */
4001 pkey_bits
= !!check_pkey
;
4002 /* PKRU.WD stops write access. */
4003 pkey_bits
|= (!!check_write
) << 1;
4005 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4009 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4011 unsigned root_level
= mmu
->root_level
;
4013 mmu
->last_nonleaf_level
= root_level
;
4014 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4015 mmu
->last_nonleaf_level
++;
4018 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4019 struct kvm_mmu
*context
,
4022 context
->nx
= is_nx(vcpu
);
4023 context
->root_level
= level
;
4025 reset_rsvds_bits_mask(vcpu
, context
);
4026 update_permission_bitmask(vcpu
, context
, false);
4027 update_pkru_bitmask(vcpu
, context
, false);
4028 update_last_nonleaf_level(vcpu
, context
);
4030 MMU_WARN_ON(!is_pae(vcpu
));
4031 context
->page_fault
= paging64_page_fault
;
4032 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4033 context
->sync_page
= paging64_sync_page
;
4034 context
->invlpg
= paging64_invlpg
;
4035 context
->update_pte
= paging64_update_pte
;
4036 context
->shadow_root_level
= level
;
4037 context
->root_hpa
= INVALID_PAGE
;
4038 context
->direct_map
= false;
4041 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4042 struct kvm_mmu
*context
)
4044 paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
4047 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4048 struct kvm_mmu
*context
)
4050 context
->nx
= false;
4051 context
->root_level
= PT32_ROOT_LEVEL
;
4053 reset_rsvds_bits_mask(vcpu
, context
);
4054 update_permission_bitmask(vcpu
, context
, false);
4055 update_pkru_bitmask(vcpu
, context
, false);
4056 update_last_nonleaf_level(vcpu
, context
);
4058 context
->page_fault
= paging32_page_fault
;
4059 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4060 context
->sync_page
= paging32_sync_page
;
4061 context
->invlpg
= paging32_invlpg
;
4062 context
->update_pte
= paging32_update_pte
;
4063 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4064 context
->root_hpa
= INVALID_PAGE
;
4065 context
->direct_map
= false;
4068 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4069 struct kvm_mmu
*context
)
4071 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4074 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4076 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4078 context
->base_role
.word
= 0;
4079 context
->base_role
.smm
= is_smm(vcpu
);
4080 context
->page_fault
= tdp_page_fault
;
4081 context
->sync_page
= nonpaging_sync_page
;
4082 context
->invlpg
= nonpaging_invlpg
;
4083 context
->update_pte
= nonpaging_update_pte
;
4084 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4085 context
->root_hpa
= INVALID_PAGE
;
4086 context
->direct_map
= true;
4087 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4088 context
->get_cr3
= get_cr3
;
4089 context
->get_pdptr
= kvm_pdptr_read
;
4090 context
->inject_page_fault
= kvm_inject_page_fault
;
4092 if (!is_paging(vcpu
)) {
4093 context
->nx
= false;
4094 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4095 context
->root_level
= 0;
4096 } else if (is_long_mode(vcpu
)) {
4097 context
->nx
= is_nx(vcpu
);
4098 context
->root_level
= PT64_ROOT_LEVEL
;
4099 reset_rsvds_bits_mask(vcpu
, context
);
4100 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4101 } else if (is_pae(vcpu
)) {
4102 context
->nx
= is_nx(vcpu
);
4103 context
->root_level
= PT32E_ROOT_LEVEL
;
4104 reset_rsvds_bits_mask(vcpu
, context
);
4105 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4107 context
->nx
= false;
4108 context
->root_level
= PT32_ROOT_LEVEL
;
4109 reset_rsvds_bits_mask(vcpu
, context
);
4110 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4113 update_permission_bitmask(vcpu
, context
, false);
4114 update_pkru_bitmask(vcpu
, context
, false);
4115 update_last_nonleaf_level(vcpu
, context
);
4116 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4119 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4121 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4122 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4123 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4125 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4127 if (!is_paging(vcpu
))
4128 nonpaging_init_context(vcpu
, context
);
4129 else if (is_long_mode(vcpu
))
4130 paging64_init_context(vcpu
, context
);
4131 else if (is_pae(vcpu
))
4132 paging32E_init_context(vcpu
, context
);
4134 paging32_init_context(vcpu
, context
);
4136 context
->base_role
.nxe
= is_nx(vcpu
);
4137 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4138 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4139 context
->base_role
.smep_andnot_wp
4140 = smep
&& !is_write_protection(vcpu
);
4141 context
->base_role
.smap_andnot_wp
4142 = smap
&& !is_write_protection(vcpu
);
4143 context
->base_role
.smm
= is_smm(vcpu
);
4144 reset_shadow_zero_bits_mask(vcpu
, context
);
4146 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4148 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
)
4150 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4152 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4154 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4157 context
->page_fault
= ept_page_fault
;
4158 context
->gva_to_gpa
= ept_gva_to_gpa
;
4159 context
->sync_page
= ept_sync_page
;
4160 context
->invlpg
= ept_invlpg
;
4161 context
->update_pte
= ept_update_pte
;
4162 context
->root_level
= context
->shadow_root_level
;
4163 context
->root_hpa
= INVALID_PAGE
;
4164 context
->direct_map
= false;
4166 update_permission_bitmask(vcpu
, context
, true);
4167 update_pkru_bitmask(vcpu
, context
, true);
4168 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4169 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4171 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4173 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4175 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4177 kvm_init_shadow_mmu(vcpu
);
4178 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4179 context
->get_cr3
= get_cr3
;
4180 context
->get_pdptr
= kvm_pdptr_read
;
4181 context
->inject_page_fault
= kvm_inject_page_fault
;
4184 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4186 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4188 g_context
->get_cr3
= get_cr3
;
4189 g_context
->get_pdptr
= kvm_pdptr_read
;
4190 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4193 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4194 * L1's nested page tables (e.g. EPT12). The nested translation
4195 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4196 * L2's page tables as the first level of translation and L1's
4197 * nested page tables as the second level of translation. Basically
4198 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4200 if (!is_paging(vcpu
)) {
4201 g_context
->nx
= false;
4202 g_context
->root_level
= 0;
4203 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4204 } else if (is_long_mode(vcpu
)) {
4205 g_context
->nx
= is_nx(vcpu
);
4206 g_context
->root_level
= PT64_ROOT_LEVEL
;
4207 reset_rsvds_bits_mask(vcpu
, g_context
);
4208 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4209 } else if (is_pae(vcpu
)) {
4210 g_context
->nx
= is_nx(vcpu
);
4211 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4212 reset_rsvds_bits_mask(vcpu
, g_context
);
4213 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4215 g_context
->nx
= false;
4216 g_context
->root_level
= PT32_ROOT_LEVEL
;
4217 reset_rsvds_bits_mask(vcpu
, g_context
);
4218 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4221 update_permission_bitmask(vcpu
, g_context
, false);
4222 update_pkru_bitmask(vcpu
, g_context
, false);
4223 update_last_nonleaf_level(vcpu
, g_context
);
4226 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4228 if (mmu_is_nested(vcpu
))
4229 init_kvm_nested_mmu(vcpu
);
4230 else if (tdp_enabled
)
4231 init_kvm_tdp_mmu(vcpu
);
4233 init_kvm_softmmu(vcpu
);
4236 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4238 kvm_mmu_unload(vcpu
);
4241 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4243 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4247 r
= mmu_topup_memory_caches(vcpu
);
4250 r
= mmu_alloc_roots(vcpu
);
4251 kvm_mmu_sync_roots(vcpu
);
4254 /* set_cr3() should ensure TLB has been flushed */
4255 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4259 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4261 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4263 mmu_free_roots(vcpu
);
4264 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4266 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4268 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4269 struct kvm_mmu_page
*sp
, u64
*spte
,
4272 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4273 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4277 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4278 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4281 static bool need_remote_flush(u64 old
, u64
new)
4283 if (!is_shadow_present_pte(old
))
4285 if (!is_shadow_present_pte(new))
4287 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4289 old
^= shadow_nx_mask
;
4290 new ^= shadow_nx_mask
;
4291 return (old
& ~new & PT64_PERM_MASK
) != 0;
4294 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4295 const u8
*new, int *bytes
)
4301 * Assume that the pte write on a page table of the same type
4302 * as the current vcpu paging mode since we update the sptes only
4303 * when they have the same mode.
4305 if (is_pae(vcpu
) && *bytes
== 4) {
4306 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4309 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4312 new = (const u8
*)&gentry
;
4317 gentry
= *(const u32
*)new;
4320 gentry
= *(const u64
*)new;
4331 * If we're seeing too many writes to a page, it may no longer be a page table,
4332 * or we may be forking, in which case it is better to unmap the page.
4334 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4337 * Skip write-flooding detected for the sp whose level is 1, because
4338 * it can become unsync, then the guest page is not write-protected.
4340 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4343 atomic_inc(&sp
->write_flooding_count
);
4344 return atomic_read(&sp
->write_flooding_count
) >= 3;
4348 * Misaligned accesses are too much trouble to fix up; also, they usually
4349 * indicate a page is not used as a page table.
4351 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4354 unsigned offset
, pte_size
, misaligned
;
4356 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4357 gpa
, bytes
, sp
->role
.word
);
4359 offset
= offset_in_page(gpa
);
4360 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4363 * Sometimes, the OS only writes the last one bytes to update status
4364 * bits, for example, in linux, andb instruction is used in clear_bit().
4366 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4369 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4370 misaligned
|= bytes
< 4;
4375 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4377 unsigned page_offset
, quadrant
;
4381 page_offset
= offset_in_page(gpa
);
4382 level
= sp
->role
.level
;
4384 if (!sp
->role
.cr4_pae
) {
4385 page_offset
<<= 1; /* 32->64 */
4387 * A 32-bit pde maps 4MB while the shadow pdes map
4388 * only 2MB. So we need to double the offset again
4389 * and zap two pdes instead of one.
4391 if (level
== PT32_ROOT_LEVEL
) {
4392 page_offset
&= ~7; /* kill rounding error */
4396 quadrant
= page_offset
>> PAGE_SHIFT
;
4397 page_offset
&= ~PAGE_MASK
;
4398 if (quadrant
!= sp
->role
.quadrant
)
4402 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4406 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4407 const u8
*new, int bytes
)
4409 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4410 struct kvm_mmu_page
*sp
;
4411 LIST_HEAD(invalid_list
);
4412 u64 entry
, gentry
, *spte
;
4414 bool remote_flush
, local_flush
;
4415 union kvm_mmu_page_role mask
= { };
4420 mask
.smep_andnot_wp
= 1;
4421 mask
.smap_andnot_wp
= 1;
4425 * If we don't have indirect shadow pages, it means no page is
4426 * write-protected, so we can exit simply.
4428 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4431 remote_flush
= local_flush
= false;
4433 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4435 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4438 * No need to care whether allocation memory is successful
4439 * or not since pte prefetch is skiped if it does not have
4440 * enough objects in the cache.
4442 mmu_topup_memory_caches(vcpu
);
4444 spin_lock(&vcpu
->kvm
->mmu_lock
);
4445 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4446 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4448 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4449 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4450 detect_write_flooding(sp
)) {
4451 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4452 ++vcpu
->kvm
->stat
.mmu_flooded
;
4456 spte
= get_written_sptes(sp
, gpa
, &npte
);
4463 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4465 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4466 & mask
.word
) && rmap_can_add(vcpu
))
4467 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4468 if (need_remote_flush(entry
, *spte
))
4469 remote_flush
= true;
4473 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4474 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4475 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4478 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4483 if (vcpu
->arch
.mmu
.direct_map
)
4486 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4488 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4492 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4494 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4496 LIST_HEAD(invalid_list
);
4498 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4501 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4502 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4505 ++vcpu
->kvm
->stat
.mmu_recycled
;
4507 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4510 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
4511 void *insn
, int insn_len
)
4513 int r
, emulation_type
= EMULTYPE_RETRY
;
4514 enum emulation_result er
;
4515 bool direct
= vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
);
4517 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4518 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4519 if (r
== RET_MMIO_PF_EMULATE
) {
4523 if (r
== RET_MMIO_PF_RETRY
)
4529 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
4535 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4538 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4543 case EMULATE_USER_EXIT
:
4544 ++vcpu
->stat
.mmio_exits
;
4552 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4554 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4556 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4557 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4558 ++vcpu
->stat
.invlpg
;
4560 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4562 void kvm_enable_tdp(void)
4566 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4568 void kvm_disable_tdp(void)
4570 tdp_enabled
= false;
4572 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4574 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4576 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4577 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4578 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4581 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4587 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4588 * Therefore we need to allocate shadow page tables in the first
4589 * 4GB of memory, which happens to fit the DMA32 zone.
4591 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4595 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4596 for (i
= 0; i
< 4; ++i
)
4597 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4602 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4604 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4605 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4606 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4607 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4609 return alloc_mmu_pages(vcpu
);
4612 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4614 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4619 void kvm_mmu_init_vm(struct kvm
*kvm
)
4621 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4623 node
->track_write
= kvm_mmu_pte_write
;
4624 kvm_page_track_register_notifier(kvm
, node
);
4627 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
4629 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4631 kvm_page_track_unregister_notifier(kvm
, node
);
4634 /* The return value indicates if tlb flush on all vcpus is needed. */
4635 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
4637 /* The caller should hold mmu-lock before calling this function. */
4639 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4640 slot_level_handler fn
, int start_level
, int end_level
,
4641 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
4643 struct slot_rmap_walk_iterator iterator
;
4646 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
4647 end_gfn
, &iterator
) {
4649 flush
|= fn(kvm
, iterator
.rmap
);
4651 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
4652 if (flush
&& lock_flush_tlb
) {
4653 kvm_flush_remote_tlbs(kvm
);
4656 cond_resched_lock(&kvm
->mmu_lock
);
4660 if (flush
&& lock_flush_tlb
) {
4661 kvm_flush_remote_tlbs(kvm
);
4669 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4670 slot_level_handler fn
, int start_level
, int end_level
,
4671 bool lock_flush_tlb
)
4673 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
4674 end_level
, memslot
->base_gfn
,
4675 memslot
->base_gfn
+ memslot
->npages
- 1,
4680 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4681 slot_level_handler fn
, bool lock_flush_tlb
)
4683 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4684 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4688 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4689 slot_level_handler fn
, bool lock_flush_tlb
)
4691 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
4692 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4696 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4697 slot_level_handler fn
, bool lock_flush_tlb
)
4699 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4700 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
4703 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
4705 struct kvm_memslots
*slots
;
4706 struct kvm_memory_slot
*memslot
;
4709 spin_lock(&kvm
->mmu_lock
);
4710 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
4711 slots
= __kvm_memslots(kvm
, i
);
4712 kvm_for_each_memslot(memslot
, slots
) {
4715 start
= max(gfn_start
, memslot
->base_gfn
);
4716 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
4720 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
4721 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
4722 start
, end
- 1, true);
4726 spin_unlock(&kvm
->mmu_lock
);
4729 static bool slot_rmap_write_protect(struct kvm
*kvm
,
4730 struct kvm_rmap_head
*rmap_head
)
4732 return __rmap_write_protect(kvm
, rmap_head
, false);
4735 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
4736 struct kvm_memory_slot
*memslot
)
4740 spin_lock(&kvm
->mmu_lock
);
4741 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
4743 spin_unlock(&kvm
->mmu_lock
);
4746 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4747 * which do tlb flush out of mmu-lock should be serialized by
4748 * kvm->slots_lock otherwise tlb flush would be missed.
4750 lockdep_assert_held(&kvm
->slots_lock
);
4753 * We can flush all the TLBs out of the mmu lock without TLB
4754 * corruption since we just change the spte from writable to
4755 * readonly so that we only need to care the case of changing
4756 * spte from present to present (changing the spte from present
4757 * to nonpresent will flush all the TLBs immediately), in other
4758 * words, the only case we care is mmu_spte_update() where we
4759 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4760 * instead of PT_WRITABLE_MASK, that means it does not depend
4761 * on PT_WRITABLE_MASK anymore.
4764 kvm_flush_remote_tlbs(kvm
);
4767 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
4768 struct kvm_rmap_head
*rmap_head
)
4771 struct rmap_iterator iter
;
4772 int need_tlb_flush
= 0;
4774 struct kvm_mmu_page
*sp
;
4777 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
4778 sp
= page_header(__pa(sptep
));
4779 pfn
= spte_to_pfn(*sptep
);
4782 * We cannot do huge page mapping for indirect shadow pages,
4783 * which are found on the last rmap (level = 1) when not using
4784 * tdp; such shadow pages are synced with the page table in
4785 * the guest, and the guest page table is using 4K page size
4786 * mapping if the indirect sp has level = 1.
4788 if (sp
->role
.direct
&&
4789 !kvm_is_reserved_pfn(pfn
) &&
4790 PageTransCompoundMap(pfn_to_page(pfn
))) {
4791 drop_spte(kvm
, sptep
);
4797 return need_tlb_flush
;
4800 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
4801 const struct kvm_memory_slot
*memslot
)
4803 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4804 spin_lock(&kvm
->mmu_lock
);
4805 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
4806 kvm_mmu_zap_collapsible_spte
, true);
4807 spin_unlock(&kvm
->mmu_lock
);
4810 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
4811 struct kvm_memory_slot
*memslot
)
4815 spin_lock(&kvm
->mmu_lock
);
4816 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
4817 spin_unlock(&kvm
->mmu_lock
);
4819 lockdep_assert_held(&kvm
->slots_lock
);
4822 * It's also safe to flush TLBs out of mmu lock here as currently this
4823 * function is only used for dirty logging, in which case flushing TLB
4824 * out of mmu lock also guarantees no dirty pages will be lost in
4828 kvm_flush_remote_tlbs(kvm
);
4830 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
4832 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
4833 struct kvm_memory_slot
*memslot
)
4837 spin_lock(&kvm
->mmu_lock
);
4838 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
4840 spin_unlock(&kvm
->mmu_lock
);
4842 /* see kvm_mmu_slot_remove_write_access */
4843 lockdep_assert_held(&kvm
->slots_lock
);
4846 kvm_flush_remote_tlbs(kvm
);
4848 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
4850 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
4851 struct kvm_memory_slot
*memslot
)
4855 spin_lock(&kvm
->mmu_lock
);
4856 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
4857 spin_unlock(&kvm
->mmu_lock
);
4859 lockdep_assert_held(&kvm
->slots_lock
);
4861 /* see kvm_mmu_slot_leaf_clear_dirty */
4863 kvm_flush_remote_tlbs(kvm
);
4865 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
4867 #define BATCH_ZAP_PAGES 10
4868 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
4870 struct kvm_mmu_page
*sp
, *node
;
4874 list_for_each_entry_safe_reverse(sp
, node
,
4875 &kvm
->arch
.active_mmu_pages
, link
) {
4879 * No obsolete page exists before new created page since
4880 * active_mmu_pages is the FIFO list.
4882 if (!is_obsolete_sp(kvm
, sp
))
4886 * Since we are reversely walking the list and the invalid
4887 * list will be moved to the head, skip the invalid page
4888 * can help us to avoid the infinity list walking.
4890 if (sp
->role
.invalid
)
4894 * Need not flush tlb since we only zap the sp with invalid
4895 * generation number.
4897 if (batch
>= BATCH_ZAP_PAGES
&&
4898 cond_resched_lock(&kvm
->mmu_lock
)) {
4903 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
4904 &kvm
->arch
.zapped_obsolete_pages
);
4912 * Should flush tlb before free page tables since lockless-walking
4913 * may use the pages.
4915 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
4919 * Fast invalidate all shadow pages and use lock-break technique
4920 * to zap obsolete pages.
4922 * It's required when memslot is being deleted or VM is being
4923 * destroyed, in these cases, we should ensure that KVM MMU does
4924 * not use any resource of the being-deleted slot or all slots
4925 * after calling the function.
4927 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
4929 spin_lock(&kvm
->mmu_lock
);
4930 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
4931 kvm
->arch
.mmu_valid_gen
++;
4934 * Notify all vcpus to reload its shadow page table
4935 * and flush TLB. Then all vcpus will switch to new
4936 * shadow page table with the new mmu_valid_gen.
4938 * Note: we should do this under the protection of
4939 * mmu-lock, otherwise, vcpu would purge shadow page
4940 * but miss tlb flush.
4942 kvm_reload_remote_mmus(kvm
);
4944 kvm_zap_obsolete_pages(kvm
);
4945 spin_unlock(&kvm
->mmu_lock
);
4948 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
4950 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
4953 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
4956 * The very rare case: if the generation-number is round,
4957 * zap all shadow pages.
4959 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
4960 printk_ratelimited(KERN_DEBUG
"kvm: zapping shadow pages for mmio generation wraparound\n");
4961 kvm_mmu_invalidate_zap_all_pages(kvm
);
4965 static unsigned long
4966 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
4969 int nr_to_scan
= sc
->nr_to_scan
;
4970 unsigned long freed
= 0;
4972 spin_lock(&kvm_lock
);
4974 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4976 LIST_HEAD(invalid_list
);
4979 * Never scan more than sc->nr_to_scan VM instances.
4980 * Will not hit this condition practically since we do not try
4981 * to shrink more than one VM and it is very unlikely to see
4982 * !n_used_mmu_pages so many times.
4987 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4988 * here. We may skip a VM instance errorneosly, but we do not
4989 * want to shrink a VM that only started to populate its MMU
4992 if (!kvm
->arch
.n_used_mmu_pages
&&
4993 !kvm_has_zapped_obsolete_pages(kvm
))
4996 idx
= srcu_read_lock(&kvm
->srcu
);
4997 spin_lock(&kvm
->mmu_lock
);
4999 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5000 kvm_mmu_commit_zap_page(kvm
,
5001 &kvm
->arch
.zapped_obsolete_pages
);
5005 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5007 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5010 spin_unlock(&kvm
->mmu_lock
);
5011 srcu_read_unlock(&kvm
->srcu
, idx
);
5014 * unfair on small ones
5015 * per-vm shrinkers cry out
5016 * sadness comes quickly
5018 list_move_tail(&kvm
->vm_list
, &vm_list
);
5022 spin_unlock(&kvm_lock
);
5026 static unsigned long
5027 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5029 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5032 static struct shrinker mmu_shrinker
= {
5033 .count_objects
= mmu_shrink_count
,
5034 .scan_objects
= mmu_shrink_scan
,
5035 .seeks
= DEFAULT_SEEKS
* 10,
5038 static void mmu_destroy_caches(void)
5040 if (pte_list_desc_cache
)
5041 kmem_cache_destroy(pte_list_desc_cache
);
5042 if (mmu_page_header_cache
)
5043 kmem_cache_destroy(mmu_page_header_cache
);
5046 int kvm_mmu_module_init(void)
5048 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5049 sizeof(struct pte_list_desc
),
5051 if (!pte_list_desc_cache
)
5054 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5055 sizeof(struct kvm_mmu_page
),
5057 if (!mmu_page_header_cache
)
5060 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5063 register_shrinker(&mmu_shrinker
);
5068 mmu_destroy_caches();
5073 * Caculate mmu pages needed for kvm.
5075 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5077 unsigned int nr_mmu_pages
;
5078 unsigned int nr_pages
= 0;
5079 struct kvm_memslots
*slots
;
5080 struct kvm_memory_slot
*memslot
;
5083 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5084 slots
= __kvm_memslots(kvm
, i
);
5086 kvm_for_each_memslot(memslot
, slots
)
5087 nr_pages
+= memslot
->npages
;
5090 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5091 nr_mmu_pages
= max(nr_mmu_pages
,
5092 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5094 return nr_mmu_pages
;
5097 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5099 kvm_mmu_unload(vcpu
);
5100 free_mmu_pages(vcpu
);
5101 mmu_free_memory_caches(vcpu
);
5104 void kvm_mmu_module_exit(void)
5106 mmu_destroy_caches();
5107 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5108 unregister_shrinker(&mmu_shrinker
);
5109 mmu_audit_disable();