2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg
, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc
{
157 u64
*sptes
[PTE_LIST_EXT
];
158 struct pte_list_desc
*more
;
161 struct kvm_shadow_walk_iterator
{
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache
*pte_list_desc_cache
;
181 static struct kmem_cache
*mmu_page_header_cache
;
182 static struct percpu_counter kvm_total_used_mmu_pages
;
184 static u64 __read_mostly shadow_nx_mask
;
185 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask
;
187 static u64 __read_mostly shadow_accessed_mask
;
188 static u64 __read_mostly shadow_dirty_mask
;
189 static u64 __read_mostly shadow_mmio_mask
;
191 static void mmu_spte_set(u64
*sptep
, u64 spte
);
192 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
196 shadow_mmio_mask
= mmio_mask
;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
200 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
202 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
204 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
206 sp
->mmio_cached
= true;
207 trace_mark_mmio_spte(sptep
, gfn
, access
);
208 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
211 static bool is_mmio_spte(u64 spte
)
213 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
216 static gfn_t
get_mmio_spte_gfn(u64 spte
)
218 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
221 static unsigned get_mmio_spte_access(u64 spte
)
223 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
226 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
228 if (unlikely(is_noslot_pfn(pfn
))) {
229 mark_mmio_spte(sptep
, gfn
, access
);
236 static inline u64
rsvd_bits(int s
, int e
)
238 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
241 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
242 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
244 shadow_user_mask
= user_mask
;
245 shadow_accessed_mask
= accessed_mask
;
246 shadow_dirty_mask
= dirty_mask
;
247 shadow_nx_mask
= nx_mask
;
248 shadow_x_mask
= x_mask
;
250 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
252 static int is_cpuid_PSE36(void)
257 static int is_nx(struct kvm_vcpu
*vcpu
)
259 return vcpu
->arch
.efer
& EFER_NX
;
262 static int is_shadow_present_pte(u64 pte
)
264 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
267 static int is_large_pte(u64 pte
)
269 return pte
& PT_PAGE_SIZE_MASK
;
272 static int is_dirty_gpte(unsigned long pte
)
274 return pte
& PT_DIRTY_MASK
;
277 static int is_rmap_spte(u64 pte
)
279 return is_shadow_present_pte(pte
);
282 static int is_last_spte(u64 pte
, int level
)
284 if (level
== PT_PAGE_TABLE_LEVEL
)
286 if (is_large_pte(pte
))
291 static pfn_t
spte_to_pfn(u64 pte
)
293 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
296 static gfn_t
pse36_gfn_delta(u32 gpte
)
298 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
300 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
304 static void __set_spte(u64
*sptep
, u64 spte
)
309 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
314 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
316 return xchg(sptep
, spte
);
319 static u64
__get_spte_lockless(u64
*sptep
)
321 return ACCESS_ONCE(*sptep
);
324 static bool __check_direct_spte_mmio_pf(u64 spte
)
326 /* It is valid if the spte is zapped. */
338 static void count_spte_clear(u64
*sptep
, u64 spte
)
340 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
342 if (is_shadow_present_pte(spte
))
345 /* Ensure the spte is completely set before we increase the count */
347 sp
->clear_spte_count
++;
350 static void __set_spte(u64
*sptep
, u64 spte
)
352 union split_spte
*ssptep
, sspte
;
354 ssptep
= (union split_spte
*)sptep
;
355 sspte
= (union split_spte
)spte
;
357 ssptep
->spte_high
= sspte
.spte_high
;
360 * If we map the spte from nonpresent to present, We should store
361 * the high bits firstly, then set present bit, so cpu can not
362 * fetch this spte while we are setting the spte.
366 ssptep
->spte_low
= sspte
.spte_low
;
369 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
371 union split_spte
*ssptep
, sspte
;
373 ssptep
= (union split_spte
*)sptep
;
374 sspte
= (union split_spte
)spte
;
376 ssptep
->spte_low
= sspte
.spte_low
;
379 * If we map the spte from present to nonpresent, we should clear
380 * present bit firstly to avoid vcpu fetch the old high bits.
384 ssptep
->spte_high
= sspte
.spte_high
;
385 count_spte_clear(sptep
, spte
);
388 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
390 union split_spte
*ssptep
, sspte
, orig
;
392 ssptep
= (union split_spte
*)sptep
;
393 sspte
= (union split_spte
)spte
;
395 /* xchg acts as a barrier before the setting of the high bits */
396 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
397 orig
.spte_high
= ssptep
->spte_high
;
398 ssptep
->spte_high
= sspte
.spte_high
;
399 count_spte_clear(sptep
, spte
);
405 * The idea using the light way get the spte on x86_32 guest is from
406 * gup_get_pte(arch/x86/mm/gup.c).
407 * The difference is we can not catch the spte tlb flush if we leave
408 * guest mode, so we emulate it by increase clear_spte_count when spte
411 static u64
__get_spte_lockless(u64
*sptep
)
413 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
414 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
418 count
= sp
->clear_spte_count
;
421 spte
.spte_low
= orig
->spte_low
;
424 spte
.spte_high
= orig
->spte_high
;
427 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
428 count
!= sp
->clear_spte_count
))
434 static bool __check_direct_spte_mmio_pf(u64 spte
)
436 union split_spte sspte
= (union split_spte
)spte
;
437 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
439 /* It is valid if the spte is zapped. */
443 /* It is valid if the spte is being zapped. */
444 if (sspte
.spte_low
== 0ull &&
445 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
452 static bool spte_is_locklessly_modifiable(u64 spte
)
454 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
455 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
458 static bool spte_has_volatile_bits(u64 spte
)
461 * Always atomicly update spte if it can be updated
462 * out of mmu-lock, it can ensure dirty bit is not lost,
463 * also, it can help us to get a stable is_writable_pte()
464 * to ensure tlb flush is not missed.
466 if (spte_is_locklessly_modifiable(spte
))
469 if (!shadow_accessed_mask
)
472 if (!is_shadow_present_pte(spte
))
475 if ((spte
& shadow_accessed_mask
) &&
476 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
482 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
484 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
487 /* Rules for using mmu_spte_set:
488 * Set the sptep from nonpresent to present.
489 * Note: the sptep being assigned *must* be either not present
490 * or in a state where the hardware will not attempt to update
493 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
495 WARN_ON(is_shadow_present_pte(*sptep
));
496 __set_spte(sptep
, new_spte
);
499 /* Rules for using mmu_spte_update:
500 * Update the state bits, it means the mapped pfn is not changged.
502 * Whenever we overwrite a writable spte with a read-only one we
503 * should flush remote TLBs. Otherwise rmap_write_protect
504 * will find a read-only spte, even though the writable spte
505 * might be cached on a CPU's TLB, the return value indicates this
508 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
510 u64 old_spte
= *sptep
;
513 WARN_ON(!is_rmap_spte(new_spte
));
515 if (!is_shadow_present_pte(old_spte
)) {
516 mmu_spte_set(sptep
, new_spte
);
520 if (!spte_has_volatile_bits(old_spte
))
521 __update_clear_spte_fast(sptep
, new_spte
);
523 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
526 * For the spte updated out of mmu-lock is safe, since
527 * we always atomicly update it, see the comments in
528 * spte_has_volatile_bits().
530 if (is_writable_pte(old_spte
) && !is_writable_pte(new_spte
))
533 if (!shadow_accessed_mask
)
536 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
537 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
538 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
539 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
545 * Rules for using mmu_spte_clear_track_bits:
546 * It sets the sptep from present to nonpresent, and track the
547 * state bits, it is used to clear the last level sptep.
549 static int mmu_spte_clear_track_bits(u64
*sptep
)
552 u64 old_spte
= *sptep
;
554 if (!spte_has_volatile_bits(old_spte
))
555 __update_clear_spte_fast(sptep
, 0ull);
557 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
559 if (!is_rmap_spte(old_spte
))
562 pfn
= spte_to_pfn(old_spte
);
565 * KVM does not hold the refcount of the page used by
566 * kvm mmu, before reclaiming the page, we should
567 * unmap it from mmu first.
569 WARN_ON(!kvm_is_mmio_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
571 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
572 kvm_set_pfn_accessed(pfn
);
573 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
574 kvm_set_pfn_dirty(pfn
);
579 * Rules for using mmu_spte_clear_no_track:
580 * Directly clear spte without caring the state bits of sptep,
581 * it is used to set the upper level spte.
583 static void mmu_spte_clear_no_track(u64
*sptep
)
585 __update_clear_spte_fast(sptep
, 0ull);
588 static u64
mmu_spte_get_lockless(u64
*sptep
)
590 return __get_spte_lockless(sptep
);
593 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
596 * Prevent page table teardown by making any free-er wait during
597 * kvm_flush_remote_tlbs() IPI to all active vcpus.
600 vcpu
->mode
= READING_SHADOW_PAGE_TABLES
;
602 * Make sure a following spte read is not reordered ahead of the write
608 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
611 * Make sure the write to vcpu->mode is not reordered in front of
612 * reads to sptes. If it does, kvm_commit_zap_page() can see us
613 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
616 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
620 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
621 struct kmem_cache
*base_cache
, int min
)
625 if (cache
->nobjs
>= min
)
627 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
628 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
631 cache
->objects
[cache
->nobjs
++] = obj
;
636 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
641 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
642 struct kmem_cache
*cache
)
645 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
648 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
653 if (cache
->nobjs
>= min
)
655 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
656 page
= (void *)__get_free_page(GFP_KERNEL
);
659 cache
->objects
[cache
->nobjs
++] = page
;
664 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
667 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
670 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
674 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
675 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
678 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
681 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
682 mmu_page_header_cache
, 4);
687 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
689 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
690 pte_list_desc_cache
);
691 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
692 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
693 mmu_page_header_cache
);
696 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
701 p
= mc
->objects
[--mc
->nobjs
];
705 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
707 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
710 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
712 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
715 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
717 if (!sp
->role
.direct
)
718 return sp
->gfns
[index
];
720 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
723 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
726 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
728 sp
->gfns
[index
] = gfn
;
732 * Return the pointer to the large page information for a given gfn,
733 * handling slots that are not large page aligned.
735 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
736 struct kvm_memory_slot
*slot
,
741 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
742 return &slot
->arch
.lpage_info
[level
- 2][idx
];
745 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
747 struct kvm_memory_slot
*slot
;
748 struct kvm_lpage_info
*linfo
;
751 slot
= gfn_to_memslot(kvm
, gfn
);
752 for (i
= PT_DIRECTORY_LEVEL
;
753 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
754 linfo
= lpage_info_slot(gfn
, slot
, i
);
755 linfo
->write_count
+= 1;
757 kvm
->arch
.indirect_shadow_pages
++;
760 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
762 struct kvm_memory_slot
*slot
;
763 struct kvm_lpage_info
*linfo
;
766 slot
= gfn_to_memslot(kvm
, gfn
);
767 for (i
= PT_DIRECTORY_LEVEL
;
768 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
769 linfo
= lpage_info_slot(gfn
, slot
, i
);
770 linfo
->write_count
-= 1;
771 WARN_ON(linfo
->write_count
< 0);
773 kvm
->arch
.indirect_shadow_pages
--;
776 static int has_wrprotected_page(struct kvm
*kvm
,
780 struct kvm_memory_slot
*slot
;
781 struct kvm_lpage_info
*linfo
;
783 slot
= gfn_to_memslot(kvm
, gfn
);
785 linfo
= lpage_info_slot(gfn
, slot
, level
);
786 return linfo
->write_count
;
792 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
794 unsigned long page_size
;
797 page_size
= kvm_host_page_size(kvm
, gfn
);
799 for (i
= PT_PAGE_TABLE_LEVEL
;
800 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
801 if (page_size
>= KVM_HPAGE_SIZE(i
))
810 static struct kvm_memory_slot
*
811 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
814 struct kvm_memory_slot
*slot
;
816 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
817 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
818 (no_dirty_log
&& slot
->dirty_bitmap
))
824 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
826 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
829 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
831 int host_level
, level
, max_level
;
833 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
835 if (host_level
== PT_PAGE_TABLE_LEVEL
)
838 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
840 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
841 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
848 * Pte mapping structures:
850 * If pte_list bit zero is zero, then pte_list point to the spte.
852 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
853 * pte_list_desc containing more mappings.
855 * Returns the number of pte entries before the spte was added or zero if
856 * the spte was not added.
859 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
860 unsigned long *pte_list
)
862 struct pte_list_desc
*desc
;
866 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
867 *pte_list
= (unsigned long)spte
;
868 } else if (!(*pte_list
& 1)) {
869 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
870 desc
= mmu_alloc_pte_list_desc(vcpu
);
871 desc
->sptes
[0] = (u64
*)*pte_list
;
872 desc
->sptes
[1] = spte
;
873 *pte_list
= (unsigned long)desc
| 1;
876 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
877 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
878 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
880 count
+= PTE_LIST_EXT
;
882 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
883 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
886 for (i
= 0; desc
->sptes
[i
]; ++i
)
888 desc
->sptes
[i
] = spte
;
894 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
895 int i
, struct pte_list_desc
*prev_desc
)
899 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
901 desc
->sptes
[i
] = desc
->sptes
[j
];
902 desc
->sptes
[j
] = NULL
;
905 if (!prev_desc
&& !desc
->more
)
906 *pte_list
= (unsigned long)desc
->sptes
[0];
909 prev_desc
->more
= desc
->more
;
911 *pte_list
= (unsigned long)desc
->more
| 1;
912 mmu_free_pte_list_desc(desc
);
915 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
917 struct pte_list_desc
*desc
;
918 struct pte_list_desc
*prev_desc
;
922 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
924 } else if (!(*pte_list
& 1)) {
925 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
926 if ((u64
*)*pte_list
!= spte
) {
927 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
932 rmap_printk("pte_list_remove: %p many->many\n", spte
);
933 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
936 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
937 if (desc
->sptes
[i
] == spte
) {
938 pte_list_desc_remove_entry(pte_list
,
946 pr_err("pte_list_remove: %p many->many\n", spte
);
951 typedef void (*pte_list_walk_fn
) (u64
*spte
);
952 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
954 struct pte_list_desc
*desc
;
960 if (!(*pte_list
& 1))
961 return fn((u64
*)*pte_list
);
963 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
965 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
971 static unsigned long *__gfn_to_rmap(gfn_t gfn
, int level
,
972 struct kvm_memory_slot
*slot
)
976 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
977 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
981 * Take gfn and return the reverse mapping to it.
983 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
985 struct kvm_memory_slot
*slot
;
987 slot
= gfn_to_memslot(kvm
, gfn
);
988 return __gfn_to_rmap(gfn
, level
, slot
);
991 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
993 struct kvm_mmu_memory_cache
*cache
;
995 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
996 return mmu_memory_cache_free_objects(cache
);
999 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1001 struct kvm_mmu_page
*sp
;
1002 unsigned long *rmapp
;
1004 sp
= page_header(__pa(spte
));
1005 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1006 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1007 return pte_list_add(vcpu
, spte
, rmapp
);
1010 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1012 struct kvm_mmu_page
*sp
;
1014 unsigned long *rmapp
;
1016 sp
= page_header(__pa(spte
));
1017 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1018 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
1019 pte_list_remove(spte
, rmapp
);
1023 * Used by the following functions to iterate through the sptes linked by a
1024 * rmap. All fields are private and not assumed to be used outside.
1026 struct rmap_iterator
{
1027 /* private fields */
1028 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1029 int pos
; /* index of the sptep */
1033 * Iteration must be started by this function. This should also be used after
1034 * removing/dropping sptes from the rmap link because in such cases the
1035 * information in the itererator may not be valid.
1037 * Returns sptep if found, NULL otherwise.
1039 static u64
*rmap_get_first(unsigned long rmap
, struct rmap_iterator
*iter
)
1049 iter
->desc
= (struct pte_list_desc
*)(rmap
& ~1ul);
1051 return iter
->desc
->sptes
[iter
->pos
];
1055 * Must be used with a valid iterator: e.g. after rmap_get_first().
1057 * Returns sptep if found, NULL otherwise.
1059 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1062 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1066 sptep
= iter
->desc
->sptes
[iter
->pos
];
1071 iter
->desc
= iter
->desc
->more
;
1075 /* desc->sptes[0] cannot be NULL */
1076 return iter
->desc
->sptes
[iter
->pos
];
1083 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1085 if (mmu_spte_clear_track_bits(sptep
))
1086 rmap_remove(kvm
, sptep
);
1090 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1092 if (is_large_pte(*sptep
)) {
1093 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1094 PT_PAGE_TABLE_LEVEL
);
1095 drop_spte(kvm
, sptep
);
1103 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1105 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1106 kvm_flush_remote_tlbs(vcpu
->kvm
);
1110 * Write-protect on the specified @sptep, @pt_protect indicates whether
1111 * spte writ-protection is caused by protecting shadow page table.
1112 * @flush indicates whether tlb need be flushed.
1114 * Note: write protection is difference between drity logging and spte
1116 * - for dirty logging, the spte can be set to writable at anytime if
1117 * its dirty bitmap is properly set.
1118 * - for spte protection, the spte can be writable only after unsync-ing
1121 * Return true if the spte is dropped.
1124 spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool *flush
, bool pt_protect
)
1128 if (!is_writable_pte(spte
) &&
1129 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1132 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1134 if (__drop_large_spte(kvm
, sptep
)) {
1140 spte
&= ~SPTE_MMU_WRITEABLE
;
1141 spte
= spte
& ~PT_WRITABLE_MASK
;
1143 *flush
|= mmu_spte_update(sptep
, spte
);
1147 static bool __rmap_write_protect(struct kvm
*kvm
, unsigned long *rmapp
,
1151 struct rmap_iterator iter
;
1154 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1155 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1156 if (spte_write_protect(kvm
, sptep
, &flush
, pt_protect
)) {
1157 sptep
= rmap_get_first(*rmapp
, &iter
);
1161 sptep
= rmap_get_next(&iter
);
1168 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1169 * @kvm: kvm instance
1170 * @slot: slot to protect
1171 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1172 * @mask: indicates which pages we should protect
1174 * Used when we do not need to care about huge page mappings: e.g. during dirty
1175 * logging we do not have any such mappings.
1177 void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1178 struct kvm_memory_slot
*slot
,
1179 gfn_t gfn_offset
, unsigned long mask
)
1181 unsigned long *rmapp
;
1184 rmapp
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1185 PT_PAGE_TABLE_LEVEL
, slot
);
1186 __rmap_write_protect(kvm
, rmapp
, false);
1188 /* clear the first set bit */
1193 static bool rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1195 struct kvm_memory_slot
*slot
;
1196 unsigned long *rmapp
;
1198 bool write_protected
= false;
1200 slot
= gfn_to_memslot(kvm
, gfn
);
1202 for (i
= PT_PAGE_TABLE_LEVEL
;
1203 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1204 rmapp
= __gfn_to_rmap(gfn
, i
, slot
);
1205 write_protected
|= __rmap_write_protect(kvm
, rmapp
, true);
1208 return write_protected
;
1211 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1212 struct kvm_memory_slot
*slot
, unsigned long data
)
1215 struct rmap_iterator iter
;
1216 int need_tlb_flush
= 0;
1218 while ((sptep
= rmap_get_first(*rmapp
, &iter
))) {
1219 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1220 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep
, *sptep
);
1222 drop_spte(kvm
, sptep
);
1226 return need_tlb_flush
;
1229 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1230 struct kvm_memory_slot
*slot
, unsigned long data
)
1233 struct rmap_iterator iter
;
1236 pte_t
*ptep
= (pte_t
*)data
;
1239 WARN_ON(pte_huge(*ptep
));
1240 new_pfn
= pte_pfn(*ptep
);
1242 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1243 BUG_ON(!is_shadow_present_pte(*sptep
));
1244 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep
, *sptep
);
1248 if (pte_write(*ptep
)) {
1249 drop_spte(kvm
, sptep
);
1250 sptep
= rmap_get_first(*rmapp
, &iter
);
1252 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1253 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1255 new_spte
&= ~PT_WRITABLE_MASK
;
1256 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1257 new_spte
&= ~shadow_accessed_mask
;
1259 mmu_spte_clear_track_bits(sptep
);
1260 mmu_spte_set(sptep
, new_spte
);
1261 sptep
= rmap_get_next(&iter
);
1266 kvm_flush_remote_tlbs(kvm
);
1271 static int kvm_handle_hva_range(struct kvm
*kvm
,
1272 unsigned long start
,
1275 int (*handler
)(struct kvm
*kvm
,
1276 unsigned long *rmapp
,
1277 struct kvm_memory_slot
*slot
,
1278 unsigned long data
))
1282 struct kvm_memslots
*slots
;
1283 struct kvm_memory_slot
*memslot
;
1285 slots
= kvm_memslots(kvm
);
1287 kvm_for_each_memslot(memslot
, slots
) {
1288 unsigned long hva_start
, hva_end
;
1289 gfn_t gfn_start
, gfn_end
;
1291 hva_start
= max(start
, memslot
->userspace_addr
);
1292 hva_end
= min(end
, memslot
->userspace_addr
+
1293 (memslot
->npages
<< PAGE_SHIFT
));
1294 if (hva_start
>= hva_end
)
1297 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1298 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1300 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1301 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1303 for (j
= PT_PAGE_TABLE_LEVEL
;
1304 j
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++j
) {
1305 unsigned long idx
, idx_end
;
1306 unsigned long *rmapp
;
1309 * {idx(page_j) | page_j intersects with
1310 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1312 idx
= gfn_to_index(gfn_start
, memslot
->base_gfn
, j
);
1313 idx_end
= gfn_to_index(gfn_end
- 1, memslot
->base_gfn
, j
);
1315 rmapp
= __gfn_to_rmap(gfn_start
, j
, memslot
);
1317 for (; idx
<= idx_end
; ++idx
)
1318 ret
|= handler(kvm
, rmapp
++, memslot
, data
);
1325 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1327 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1328 struct kvm_memory_slot
*slot
,
1329 unsigned long data
))
1331 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1334 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1336 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1339 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1341 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1344 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1346 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1349 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1350 struct kvm_memory_slot
*slot
, unsigned long data
)
1353 struct rmap_iterator
uninitialized_var(iter
);
1357 * In case of absence of EPT Access and Dirty Bits supports,
1358 * emulate the accessed bit for EPT, by checking if this page has
1359 * an EPT mapping, and clearing it if it does. On the next access,
1360 * a new EPT mapping will be established.
1361 * This has some overhead, but not as much as the cost of swapping
1362 * out actively used pages or breaking up actively used hugepages.
1364 if (!shadow_accessed_mask
) {
1365 young
= kvm_unmap_rmapp(kvm
, rmapp
, slot
, data
);
1369 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1370 sptep
= rmap_get_next(&iter
)) {
1371 BUG_ON(!is_shadow_present_pte(*sptep
));
1373 if (*sptep
& shadow_accessed_mask
) {
1375 clear_bit((ffs(shadow_accessed_mask
) - 1),
1376 (unsigned long *)sptep
);
1380 /* @data has hva passed to kvm_age_hva(). */
1381 trace_kvm_age_page(data
, slot
, young
);
1385 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1386 struct kvm_memory_slot
*slot
, unsigned long data
)
1389 struct rmap_iterator iter
;
1393 * If there's no access bit in the secondary pte set by the
1394 * hardware it's up to gup-fast/gup to set the access bit in
1395 * the primary pte or in the page structure.
1397 if (!shadow_accessed_mask
)
1400 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1401 sptep
= rmap_get_next(&iter
)) {
1402 BUG_ON(!is_shadow_present_pte(*sptep
));
1404 if (*sptep
& shadow_accessed_mask
) {
1413 #define RMAP_RECYCLE_THRESHOLD 1000
1415 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1417 unsigned long *rmapp
;
1418 struct kvm_mmu_page
*sp
;
1420 sp
= page_header(__pa(spte
));
1422 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1424 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, NULL
, 0);
1425 kvm_flush_remote_tlbs(vcpu
->kvm
);
1428 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1430 return kvm_handle_hva(kvm
, hva
, hva
, kvm_age_rmapp
);
1433 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1435 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1439 static int is_empty_shadow_page(u64
*spt
)
1444 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1445 if (is_shadow_present_pte(*pos
)) {
1446 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1455 * This value is the sum of all of the kvm instances's
1456 * kvm->arch.n_used_mmu_pages values. We need a global,
1457 * aggregate version in order to make the slab shrinker
1460 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1462 kvm
->arch
.n_used_mmu_pages
+= nr
;
1463 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1466 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1468 ASSERT(is_empty_shadow_page(sp
->spt
));
1469 hlist_del(&sp
->hash_link
);
1470 list_del(&sp
->link
);
1471 free_page((unsigned long)sp
->spt
);
1472 if (!sp
->role
.direct
)
1473 free_page((unsigned long)sp
->gfns
);
1474 kmem_cache_free(mmu_page_header_cache
, sp
);
1477 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1479 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1482 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1483 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1488 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1491 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1494 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1497 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1500 mmu_page_remove_parent_pte(sp
, parent_pte
);
1501 mmu_spte_clear_no_track(parent_pte
);
1504 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1505 u64
*parent_pte
, int direct
)
1507 struct kvm_mmu_page
*sp
;
1509 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1510 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1512 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1513 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1516 * The active_mmu_pages list is the FIFO list, do not move the
1517 * page until it is zapped. kvm_zap_obsolete_pages depends on
1518 * this feature. See the comments in kvm_zap_obsolete_pages().
1520 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1521 sp
->parent_ptes
= 0;
1522 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1523 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1527 static void mark_unsync(u64
*spte
);
1528 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1530 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1533 static void mark_unsync(u64
*spte
)
1535 struct kvm_mmu_page
*sp
;
1538 sp
= page_header(__pa(spte
));
1539 index
= spte
- sp
->spt
;
1540 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1542 if (sp
->unsync_children
++)
1544 kvm_mmu_mark_parents_unsync(sp
);
1547 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1548 struct kvm_mmu_page
*sp
)
1553 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1557 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1558 struct kvm_mmu_page
*sp
, u64
*spte
,
1564 #define KVM_PAGE_ARRAY_NR 16
1566 struct kvm_mmu_pages
{
1567 struct mmu_page_and_offset
{
1568 struct kvm_mmu_page
*sp
;
1570 } page
[KVM_PAGE_ARRAY_NR
];
1574 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1580 for (i
=0; i
< pvec
->nr
; i
++)
1581 if (pvec
->page
[i
].sp
== sp
)
1584 pvec
->page
[pvec
->nr
].sp
= sp
;
1585 pvec
->page
[pvec
->nr
].idx
= idx
;
1587 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1590 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1591 struct kvm_mmu_pages
*pvec
)
1593 int i
, ret
, nr_unsync_leaf
= 0;
1595 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1596 struct kvm_mmu_page
*child
;
1597 u64 ent
= sp
->spt
[i
];
1599 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1600 goto clear_child_bitmap
;
1602 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1604 if (child
->unsync_children
) {
1605 if (mmu_pages_add(pvec
, child
, i
))
1608 ret
= __mmu_unsync_walk(child
, pvec
);
1610 goto clear_child_bitmap
;
1612 nr_unsync_leaf
+= ret
;
1615 } else if (child
->unsync
) {
1617 if (mmu_pages_add(pvec
, child
, i
))
1620 goto clear_child_bitmap
;
1625 __clear_bit(i
, sp
->unsync_child_bitmap
);
1626 sp
->unsync_children
--;
1627 WARN_ON((int)sp
->unsync_children
< 0);
1631 return nr_unsync_leaf
;
1634 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1635 struct kvm_mmu_pages
*pvec
)
1637 if (!sp
->unsync_children
)
1640 mmu_pages_add(pvec
, sp
, 0);
1641 return __mmu_unsync_walk(sp
, pvec
);
1644 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1646 WARN_ON(!sp
->unsync
);
1647 trace_kvm_mmu_sync_page(sp
);
1649 --kvm
->stat
.mmu_unsync
;
1652 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1653 struct list_head
*invalid_list
);
1654 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1655 struct list_head
*invalid_list
);
1658 * NOTE: we should pay more attention on the zapped-obsolete page
1659 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1660 * since it has been deleted from active_mmu_pages but still can be found
1663 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1664 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1665 * all the obsolete pages.
1667 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1668 hlist_for_each_entry(_sp, \
1669 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1670 if ((_sp)->gfn != (_gfn)) {} else
1672 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1673 for_each_gfn_sp(_kvm, _sp, _gfn) \
1674 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1676 /* @sp->gfn should be write-protected at the call site */
1677 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1678 struct list_head
*invalid_list
, bool clear_unsync
)
1680 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1681 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1686 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1688 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1689 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1693 kvm_mmu_flush_tlb(vcpu
);
1697 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1698 struct kvm_mmu_page
*sp
)
1700 LIST_HEAD(invalid_list
);
1703 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1705 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1710 #ifdef CONFIG_KVM_MMU_AUDIT
1711 #include "mmu_audit.c"
1713 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1714 static void mmu_audit_disable(void) { }
1717 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1718 struct list_head
*invalid_list
)
1720 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1723 /* @gfn should be write-protected at the call site */
1724 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1726 struct kvm_mmu_page
*s
;
1727 LIST_HEAD(invalid_list
);
1730 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
1734 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1735 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1736 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1737 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1738 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1744 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1746 kvm_mmu_flush_tlb(vcpu
);
1749 struct mmu_page_path
{
1750 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1751 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1754 #define for_each_sp(pvec, sp, parents, i) \
1755 for (i = mmu_pages_next(&pvec, &parents, -1), \
1756 sp = pvec.page[i].sp; \
1757 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1758 i = mmu_pages_next(&pvec, &parents, i))
1760 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1761 struct mmu_page_path
*parents
,
1766 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1767 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1769 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1770 parents
->idx
[0] = pvec
->page
[n
].idx
;
1774 parents
->parent
[sp
->role
.level
-2] = sp
;
1775 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1781 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1783 struct kvm_mmu_page
*sp
;
1784 unsigned int level
= 0;
1787 unsigned int idx
= parents
->idx
[level
];
1789 sp
= parents
->parent
[level
];
1793 --sp
->unsync_children
;
1794 WARN_ON((int)sp
->unsync_children
< 0);
1795 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1797 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1800 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1801 struct mmu_page_path
*parents
,
1802 struct kvm_mmu_pages
*pvec
)
1804 parents
->parent
[parent
->role
.level
-1] = NULL
;
1808 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1809 struct kvm_mmu_page
*parent
)
1812 struct kvm_mmu_page
*sp
;
1813 struct mmu_page_path parents
;
1814 struct kvm_mmu_pages pages
;
1815 LIST_HEAD(invalid_list
);
1817 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1818 while (mmu_unsync_walk(parent
, &pages
)) {
1819 bool protected = false;
1821 for_each_sp(pages
, sp
, parents
, i
)
1822 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1825 kvm_flush_remote_tlbs(vcpu
->kvm
);
1827 for_each_sp(pages
, sp
, parents
, i
) {
1828 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1829 mmu_pages_clear_parents(&parents
);
1831 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1832 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1833 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1837 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1841 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1845 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1847 sp
->write_flooding_count
= 0;
1850 static void clear_sp_write_flooding_count(u64
*spte
)
1852 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
1854 __clear_sp_write_flooding_count(sp
);
1857 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1859 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
1862 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1870 union kvm_mmu_page_role role
;
1872 struct kvm_mmu_page
*sp
;
1873 bool need_sync
= false;
1875 role
= vcpu
->arch
.mmu
.base_role
;
1877 role
.direct
= direct
;
1880 role
.access
= access
;
1881 if (!vcpu
->arch
.mmu
.direct_map
1882 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1883 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1884 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1885 role
.quadrant
= quadrant
;
1887 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
) {
1888 if (is_obsolete_sp(vcpu
->kvm
, sp
))
1891 if (!need_sync
&& sp
->unsync
)
1894 if (sp
->role
.word
!= role
.word
)
1897 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1900 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1901 if (sp
->unsync_children
) {
1902 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1903 kvm_mmu_mark_parents_unsync(sp
);
1904 } else if (sp
->unsync
)
1905 kvm_mmu_mark_parents_unsync(sp
);
1907 __clear_sp_write_flooding_count(sp
);
1908 trace_kvm_mmu_get_page(sp
, false);
1911 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1912 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1917 hlist_add_head(&sp
->hash_link
,
1918 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1920 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1921 kvm_flush_remote_tlbs(vcpu
->kvm
);
1922 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1923 kvm_sync_pages(vcpu
, gfn
);
1925 account_shadowed(vcpu
->kvm
, gfn
);
1927 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
1928 init_shadow_page_table(sp
);
1929 trace_kvm_mmu_get_page(sp
, true);
1933 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1934 struct kvm_vcpu
*vcpu
, u64 addr
)
1936 iterator
->addr
= addr
;
1937 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1938 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1940 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1941 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1942 !vcpu
->arch
.mmu
.direct_map
)
1945 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1946 iterator
->shadow_addr
1947 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1948 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1950 if (!iterator
->shadow_addr
)
1951 iterator
->level
= 0;
1955 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1957 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1960 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1961 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1965 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1968 if (is_last_spte(spte
, iterator
->level
)) {
1969 iterator
->level
= 0;
1973 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1977 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1979 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1982 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1986 spte
= __pa(sp
->spt
) | PT_PRESENT_MASK
| PT_WRITABLE_MASK
|
1987 shadow_user_mask
| shadow_x_mask
| shadow_accessed_mask
;
1989 mmu_spte_set(sptep
, spte
);
1992 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1993 unsigned direct_access
)
1995 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1996 struct kvm_mmu_page
*child
;
1999 * For the direct sp, if the guest pte's dirty bit
2000 * changed form clean to dirty, it will corrupt the
2001 * sp's access: allow writable in the read-only sp,
2002 * so we should update the spte at this point to get
2003 * a new sp with the correct access.
2005 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2006 if (child
->role
.access
== direct_access
)
2009 drop_parent_pte(child
, sptep
);
2010 kvm_flush_remote_tlbs(vcpu
->kvm
);
2014 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2018 struct kvm_mmu_page
*child
;
2021 if (is_shadow_present_pte(pte
)) {
2022 if (is_last_spte(pte
, sp
->role
.level
)) {
2023 drop_spte(kvm
, spte
);
2024 if (is_large_pte(pte
))
2027 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2028 drop_parent_pte(child
, spte
);
2033 if (is_mmio_spte(pte
))
2034 mmu_spte_clear_no_track(spte
);
2039 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2040 struct kvm_mmu_page
*sp
)
2044 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2045 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2048 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
2050 mmu_page_remove_parent_pte(sp
, parent_pte
);
2053 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2056 struct rmap_iterator iter
;
2058 while ((sptep
= rmap_get_first(sp
->parent_ptes
, &iter
)))
2059 drop_parent_pte(sp
, sptep
);
2062 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2063 struct kvm_mmu_page
*parent
,
2064 struct list_head
*invalid_list
)
2067 struct mmu_page_path parents
;
2068 struct kvm_mmu_pages pages
;
2070 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2073 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2074 while (mmu_unsync_walk(parent
, &pages
)) {
2075 struct kvm_mmu_page
*sp
;
2077 for_each_sp(pages
, sp
, parents
, i
) {
2078 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2079 mmu_pages_clear_parents(&parents
);
2082 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2088 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2089 struct list_head
*invalid_list
)
2093 trace_kvm_mmu_prepare_zap_page(sp
);
2094 ++kvm
->stat
.mmu_shadow_zapped
;
2095 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2096 kvm_mmu_page_unlink_children(kvm
, sp
);
2097 kvm_mmu_unlink_parents(kvm
, sp
);
2099 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2100 unaccount_shadowed(kvm
, sp
->gfn
);
2103 kvm_unlink_unsync_page(kvm
, sp
);
2104 if (!sp
->root_count
) {
2107 list_move(&sp
->link
, invalid_list
);
2108 kvm_mod_used_mmu_pages(kvm
, -1);
2110 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2111 kvm_reload_remote_mmus(kvm
);
2114 sp
->role
.invalid
= 1;
2118 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2119 struct list_head
*invalid_list
)
2121 struct kvm_mmu_page
*sp
, *nsp
;
2123 if (list_empty(invalid_list
))
2127 * wmb: make sure everyone sees our modifications to the page tables
2128 * rmb: make sure we see changes to vcpu->mode
2133 * Wait for all vcpus to exit guest mode and/or lockless shadow
2136 kvm_flush_remote_tlbs(kvm
);
2138 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2139 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2140 kvm_mmu_free_page(sp
);
2144 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2145 struct list_head
*invalid_list
)
2147 struct kvm_mmu_page
*sp
;
2149 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2152 sp
= list_entry(kvm
->arch
.active_mmu_pages
.prev
,
2153 struct kvm_mmu_page
, link
);
2154 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2160 * Changing the number of mmu pages allocated to the vm
2161 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2163 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2165 LIST_HEAD(invalid_list
);
2167 spin_lock(&kvm
->mmu_lock
);
2169 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2170 /* Need to free some mmu pages to achieve the goal. */
2171 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2172 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2175 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2176 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2179 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2181 spin_unlock(&kvm
->mmu_lock
);
2184 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2186 struct kvm_mmu_page
*sp
;
2187 LIST_HEAD(invalid_list
);
2190 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2192 spin_lock(&kvm
->mmu_lock
);
2193 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2194 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2197 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2199 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2200 spin_unlock(&kvm
->mmu_lock
);
2204 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2207 * The function is based on mtrr_type_lookup() in
2208 * arch/x86/kernel/cpu/mtrr/generic.c
2210 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2215 u8 prev_match
, curr_match
;
2216 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2218 if (!mtrr_state
->enabled
)
2221 /* Make end inclusive end, instead of exclusive */
2224 /* Look in fixed ranges. Just return the type as per start */
2225 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2228 if (start
< 0x80000) {
2230 idx
+= (start
>> 16);
2231 return mtrr_state
->fixed_ranges
[idx
];
2232 } else if (start
< 0xC0000) {
2234 idx
+= ((start
- 0x80000) >> 14);
2235 return mtrr_state
->fixed_ranges
[idx
];
2236 } else if (start
< 0x1000000) {
2238 idx
+= ((start
- 0xC0000) >> 12);
2239 return mtrr_state
->fixed_ranges
[idx
];
2244 * Look in variable ranges
2245 * Look of multiple ranges matching this address and pick type
2246 * as per MTRR precedence
2248 if (!(mtrr_state
->enabled
& 2))
2249 return mtrr_state
->def_type
;
2252 for (i
= 0; i
< num_var_ranges
; ++i
) {
2253 unsigned short start_state
, end_state
;
2255 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2258 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2259 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2260 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2261 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2263 start_state
= ((start
& mask
) == (base
& mask
));
2264 end_state
= ((end
& mask
) == (base
& mask
));
2265 if (start_state
!= end_state
)
2268 if ((start
& mask
) != (base
& mask
))
2271 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2272 if (prev_match
== 0xFF) {
2273 prev_match
= curr_match
;
2277 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2278 curr_match
== MTRR_TYPE_UNCACHABLE
)
2279 return MTRR_TYPE_UNCACHABLE
;
2281 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2282 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2283 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2284 curr_match
== MTRR_TYPE_WRBACK
)) {
2285 prev_match
= MTRR_TYPE_WRTHROUGH
;
2286 curr_match
= MTRR_TYPE_WRTHROUGH
;
2289 if (prev_match
!= curr_match
)
2290 return MTRR_TYPE_UNCACHABLE
;
2293 if (prev_match
!= 0xFF)
2296 return mtrr_state
->def_type
;
2299 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2303 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2304 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2305 if (mtrr
== 0xfe || mtrr
== 0xff)
2306 mtrr
= MTRR_TYPE_WRBACK
;
2309 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2311 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2313 trace_kvm_mmu_unsync_page(sp
);
2314 ++vcpu
->kvm
->stat
.mmu_unsync
;
2317 kvm_mmu_mark_parents_unsync(sp
);
2320 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2322 struct kvm_mmu_page
*s
;
2324 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2327 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2328 __kvm_unsync_page(vcpu
, s
);
2332 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2335 struct kvm_mmu_page
*s
;
2336 bool need_unsync
= false;
2338 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2342 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2349 kvm_unsync_pages(vcpu
, gfn
);
2353 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2354 unsigned pte_access
, int level
,
2355 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2356 bool can_unsync
, bool host_writable
)
2361 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2364 spte
= PT_PRESENT_MASK
;
2366 spte
|= shadow_accessed_mask
;
2368 if (pte_access
& ACC_EXEC_MASK
)
2369 spte
|= shadow_x_mask
;
2371 spte
|= shadow_nx_mask
;
2373 if (pte_access
& ACC_USER_MASK
)
2374 spte
|= shadow_user_mask
;
2376 if (level
> PT_PAGE_TABLE_LEVEL
)
2377 spte
|= PT_PAGE_SIZE_MASK
;
2379 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2380 kvm_is_mmio_pfn(pfn
));
2383 spte
|= SPTE_HOST_WRITEABLE
;
2385 pte_access
&= ~ACC_WRITE_MASK
;
2387 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2389 if (pte_access
& ACC_WRITE_MASK
) {
2392 * Other vcpu creates new sp in the window between
2393 * mapping_level() and acquiring mmu-lock. We can
2394 * allow guest to retry the access, the mapping can
2395 * be fixed if guest refault.
2397 if (level
> PT_PAGE_TABLE_LEVEL
&&
2398 has_wrprotected_page(vcpu
->kvm
, gfn
, level
))
2401 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2404 * Optimization: for pte sync, if spte was writable the hash
2405 * lookup is unnecessary (and expensive). Write protection
2406 * is responsibility of mmu_get_page / kvm_sync_page.
2407 * Same reasoning can be applied to dirty page accounting.
2409 if (!can_unsync
&& is_writable_pte(*sptep
))
2412 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2413 pgprintk("%s: found shadow page for %llx, marking ro\n",
2416 pte_access
&= ~ACC_WRITE_MASK
;
2417 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2421 if (pte_access
& ACC_WRITE_MASK
)
2422 mark_page_dirty(vcpu
->kvm
, gfn
);
2425 if (mmu_spte_update(sptep
, spte
))
2426 kvm_flush_remote_tlbs(vcpu
->kvm
);
2431 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2432 unsigned pte_access
, int write_fault
, int *emulate
,
2433 int level
, gfn_t gfn
, pfn_t pfn
, bool speculative
,
2436 int was_rmapped
= 0;
2439 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2440 *sptep
, write_fault
, gfn
);
2442 if (is_rmap_spte(*sptep
)) {
2444 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2445 * the parent of the now unreachable PTE.
2447 if (level
> PT_PAGE_TABLE_LEVEL
&&
2448 !is_large_pte(*sptep
)) {
2449 struct kvm_mmu_page
*child
;
2452 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2453 drop_parent_pte(child
, sptep
);
2454 kvm_flush_remote_tlbs(vcpu
->kvm
);
2455 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2456 pgprintk("hfn old %llx new %llx\n",
2457 spte_to_pfn(*sptep
), pfn
);
2458 drop_spte(vcpu
->kvm
, sptep
);
2459 kvm_flush_remote_tlbs(vcpu
->kvm
);
2464 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2465 true, host_writable
)) {
2468 kvm_mmu_flush_tlb(vcpu
);
2471 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2474 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2475 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2476 is_large_pte(*sptep
)? "2MB" : "4kB",
2477 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2479 if (!was_rmapped
&& is_large_pte(*sptep
))
2480 ++vcpu
->kvm
->stat
.lpages
;
2482 if (is_shadow_present_pte(*sptep
)) {
2484 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2485 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2486 rmap_recycle(vcpu
, sptep
, gfn
);
2490 kvm_release_pfn_clean(pfn
);
2493 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2495 mmu_free_roots(vcpu
);
2498 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
2502 bit7
= (gpte
>> 7) & 1;
2503 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
2506 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2509 struct kvm_memory_slot
*slot
;
2511 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2513 return KVM_PFN_ERR_FAULT
;
2515 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2518 static bool prefetch_invalid_gpte(struct kvm_vcpu
*vcpu
,
2519 struct kvm_mmu_page
*sp
, u64
*spte
,
2522 if (is_rsvd_bits_set(&vcpu
->arch
.mmu
, gpte
, PT_PAGE_TABLE_LEVEL
))
2525 if (!is_present_gpte(gpte
))
2528 if (!(gpte
& PT_ACCESSED_MASK
))
2534 drop_spte(vcpu
->kvm
, spte
);
2538 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2539 struct kvm_mmu_page
*sp
,
2540 u64
*start
, u64
*end
)
2542 struct page
*pages
[PTE_PREFETCH_NUM
];
2543 unsigned access
= sp
->role
.access
;
2547 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2548 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2551 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2555 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2556 mmu_set_spte(vcpu
, start
, access
, 0, NULL
,
2557 sp
->role
.level
, gfn
, page_to_pfn(pages
[i
]),
2563 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2564 struct kvm_mmu_page
*sp
, u64
*sptep
)
2566 u64
*spte
, *start
= NULL
;
2569 WARN_ON(!sp
->role
.direct
);
2571 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2574 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2575 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2578 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2586 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2588 struct kvm_mmu_page
*sp
;
2591 * Since it's no accessed bit on EPT, it's no way to
2592 * distinguish between actually accessed translations
2593 * and prefetched, so disable pte prefetch if EPT is
2596 if (!shadow_accessed_mask
)
2599 sp
= page_header(__pa(sptep
));
2600 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2603 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2606 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2607 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2610 struct kvm_shadow_walk_iterator iterator
;
2611 struct kvm_mmu_page
*sp
;
2615 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2616 if (iterator
.level
== level
) {
2617 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2618 write
, &emulate
, level
, gfn
, pfn
,
2619 prefault
, map_writable
);
2620 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2621 ++vcpu
->stat
.pf_fixed
;
2625 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2626 u64 base_addr
= iterator
.addr
;
2628 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2629 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2630 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2632 1, ACC_ALL
, iterator
.sptep
);
2634 link_shadow_page(iterator
.sptep
, sp
);
2640 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2644 info
.si_signo
= SIGBUS
;
2646 info
.si_code
= BUS_MCEERR_AR
;
2647 info
.si_addr
= (void __user
*)address
;
2648 info
.si_addr_lsb
= PAGE_SHIFT
;
2650 send_sig_info(SIGBUS
, &info
, tsk
);
2653 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2656 * Do not cache the mmio info caused by writing the readonly gfn
2657 * into the spte otherwise read access on readonly gfn also can
2658 * caused mmio page fault and treat it as mmio access.
2659 * Return 1 to tell kvm to emulate it.
2661 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2664 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2665 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2672 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2673 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2677 int level
= *levelp
;
2680 * Check if it's a transparent hugepage. If this would be an
2681 * hugetlbfs page, level wouldn't be set to
2682 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2685 if (!is_error_noslot_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2686 level
== PT_PAGE_TABLE_LEVEL
&&
2687 PageTransCompound(pfn_to_page(pfn
)) &&
2688 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2691 * mmu_notifier_retry was successful and we hold the
2692 * mmu_lock here, so the pmd can't become splitting
2693 * from under us, and in turn
2694 * __split_huge_page_refcount() can't run from under
2695 * us and we can safely transfer the refcount from
2696 * PG_tail to PG_head as we switch the pfn to tail to
2699 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2700 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2701 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2705 kvm_release_pfn_clean(pfn
);
2713 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2714 pfn_t pfn
, unsigned access
, int *ret_val
)
2718 /* The pfn is invalid, report the error! */
2719 if (unlikely(is_error_pfn(pfn
))) {
2720 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2724 if (unlikely(is_noslot_pfn(pfn
)))
2725 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2732 static bool page_fault_can_be_fast(struct kvm_vcpu
*vcpu
, u32 error_code
)
2735 * #PF can be fast only if the shadow page table is present and it
2736 * is caused by write-protect, that means we just need change the
2737 * W bit of the spte which can be done out of mmu-lock.
2739 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2740 !(error_code
& PFERR_WRITE_MASK
))
2747 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 spte
)
2749 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
2752 WARN_ON(!sp
->role
.direct
);
2755 * The gfn of direct spte is stable since it is calculated
2758 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2760 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2761 mark_page_dirty(vcpu
->kvm
, gfn
);
2768 * - true: let the vcpu to access on the same address again.
2769 * - false: let the real page fault path to fix it.
2771 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2774 struct kvm_shadow_walk_iterator iterator
;
2778 if (!page_fault_can_be_fast(vcpu
, error_code
))
2781 walk_shadow_page_lockless_begin(vcpu
);
2782 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2783 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2787 * If the mapping has been changed, let the vcpu fault on the
2788 * same address again.
2790 if (!is_rmap_spte(spte
)) {
2795 if (!is_last_spte(spte
, level
))
2799 * Check if it is a spurious fault caused by TLB lazily flushed.
2801 * Need not check the access of upper level table entries since
2802 * they are always ACC_ALL.
2804 if (is_writable_pte(spte
)) {
2810 * Currently, to simplify the code, only the spte write-protected
2811 * by dirty-log can be fast fixed.
2813 if (!spte_is_locklessly_modifiable(spte
))
2817 * Currently, fast page fault only works for direct mapping since
2818 * the gfn is not stable for indirect shadow page.
2819 * See Documentation/virtual/kvm/locking.txt to get more detail.
2821 ret
= fast_pf_fix_direct_spte(vcpu
, iterator
.sptep
, spte
);
2823 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
2825 walk_shadow_page_lockless_end(vcpu
);
2830 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2831 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2832 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
2834 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
2835 gfn_t gfn
, bool prefault
)
2841 unsigned long mmu_seq
;
2842 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
2844 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2845 if (likely(!force_pt_level
)) {
2846 level
= mapping_level(vcpu
, gfn
);
2848 * This path builds a PAE pagetable - so we can map
2849 * 2mb pages at maximum. Therefore check if the level
2850 * is larger than that.
2852 if (level
> PT_DIRECTORY_LEVEL
)
2853 level
= PT_DIRECTORY_LEVEL
;
2855 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2857 level
= PT_PAGE_TABLE_LEVEL
;
2859 if (fast_page_fault(vcpu
, v
, level
, error_code
))
2862 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2865 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2868 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2871 spin_lock(&vcpu
->kvm
->mmu_lock
);
2872 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
2874 make_mmu_pages_available(vcpu
);
2875 if (likely(!force_pt_level
))
2876 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2877 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2879 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2885 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2886 kvm_release_pfn_clean(pfn
);
2891 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2894 struct kvm_mmu_page
*sp
;
2895 LIST_HEAD(invalid_list
);
2897 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2900 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2901 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2902 vcpu
->arch
.mmu
.direct_map
)) {
2903 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2905 spin_lock(&vcpu
->kvm
->mmu_lock
);
2906 sp
= page_header(root
);
2908 if (!sp
->root_count
&& sp
->role
.invalid
) {
2909 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2910 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2912 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2913 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2917 spin_lock(&vcpu
->kvm
->mmu_lock
);
2918 for (i
= 0; i
< 4; ++i
) {
2919 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2922 root
&= PT64_BASE_ADDR_MASK
;
2923 sp
= page_header(root
);
2925 if (!sp
->root_count
&& sp
->role
.invalid
)
2926 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2929 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2931 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2932 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2933 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2936 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2940 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2941 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2948 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2950 struct kvm_mmu_page
*sp
;
2953 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2954 spin_lock(&vcpu
->kvm
->mmu_lock
);
2955 make_mmu_pages_available(vcpu
);
2956 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2959 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2960 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2961 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2962 for (i
= 0; i
< 4; ++i
) {
2963 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2965 ASSERT(!VALID_PAGE(root
));
2966 spin_lock(&vcpu
->kvm
->mmu_lock
);
2967 make_mmu_pages_available(vcpu
);
2968 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2970 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2972 root
= __pa(sp
->spt
);
2974 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2975 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2977 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2984 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2986 struct kvm_mmu_page
*sp
;
2991 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2993 if (mmu_check_root(vcpu
, root_gfn
))
2997 * Do we shadow a long mode page table? If so we need to
2998 * write-protect the guests page table root.
3000 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3001 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3003 ASSERT(!VALID_PAGE(root
));
3005 spin_lock(&vcpu
->kvm
->mmu_lock
);
3006 make_mmu_pages_available(vcpu
);
3007 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3009 root
= __pa(sp
->spt
);
3011 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3012 vcpu
->arch
.mmu
.root_hpa
= root
;
3017 * We shadow a 32 bit page table. This may be a legacy 2-level
3018 * or a PAE 3-level page table. In either case we need to be aware that
3019 * the shadow page table may be a PAE or a long mode page table.
3021 pm_mask
= PT_PRESENT_MASK
;
3022 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3023 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3025 for (i
= 0; i
< 4; ++i
) {
3026 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3028 ASSERT(!VALID_PAGE(root
));
3029 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3030 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3031 if (!is_present_gpte(pdptr
)) {
3032 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3035 root_gfn
= pdptr
>> PAGE_SHIFT
;
3036 if (mmu_check_root(vcpu
, root_gfn
))
3039 spin_lock(&vcpu
->kvm
->mmu_lock
);
3040 make_mmu_pages_available(vcpu
);
3041 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
3044 root
= __pa(sp
->spt
);
3046 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3048 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3050 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3053 * If we shadow a 32 bit page table with a long mode page
3054 * table we enter this path.
3056 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3057 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3059 * The additional page necessary for this is only
3060 * allocated on demand.
3065 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3066 if (lm_root
== NULL
)
3069 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3071 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3074 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3080 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3082 if (vcpu
->arch
.mmu
.direct_map
)
3083 return mmu_alloc_direct_roots(vcpu
);
3085 return mmu_alloc_shadow_roots(vcpu
);
3088 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3091 struct kvm_mmu_page
*sp
;
3093 if (vcpu
->arch
.mmu
.direct_map
)
3096 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3099 vcpu_clear_mmio_info(vcpu
, ~0ul);
3100 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3101 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3102 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3103 sp
= page_header(root
);
3104 mmu_sync_children(vcpu
, sp
);
3105 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3108 for (i
= 0; i
< 4; ++i
) {
3109 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3111 if (root
&& VALID_PAGE(root
)) {
3112 root
&= PT64_BASE_ADDR_MASK
;
3113 sp
= page_header(root
);
3114 mmu_sync_children(vcpu
, sp
);
3117 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3120 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3122 spin_lock(&vcpu
->kvm
->mmu_lock
);
3123 mmu_sync_roots(vcpu
);
3124 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3127 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3128 u32 access
, struct x86_exception
*exception
)
3131 exception
->error_code
= 0;
3135 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3137 struct x86_exception
*exception
)
3140 exception
->error_code
= 0;
3141 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
3144 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3147 return vcpu_match_mmio_gpa(vcpu
, addr
);
3149 return vcpu_match_mmio_gva(vcpu
, addr
);
3154 * On direct hosts, the last spte is only allows two states
3155 * for mmio page fault:
3156 * - It is the mmio spte
3157 * - It is zapped or it is being zapped.
3159 * This function completely checks the spte when the last spte
3160 * is not the mmio spte.
3162 static bool check_direct_spte_mmio_pf(u64 spte
)
3164 return __check_direct_spte_mmio_pf(spte
);
3167 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
3169 struct kvm_shadow_walk_iterator iterator
;
3172 walk_shadow_page_lockless_begin(vcpu
);
3173 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
3174 if (!is_shadow_present_pte(spte
))
3176 walk_shadow_page_lockless_end(vcpu
);
3182 * If it is a real mmio page fault, return 1 and emulat the instruction
3183 * directly, return 0 to let CPU fault again on the address, -1 is
3184 * returned if bug is detected.
3186 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3190 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
3193 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
3195 if (is_mmio_spte(spte
)) {
3196 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3197 unsigned access
= get_mmio_spte_access(spte
);
3202 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3203 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3208 * It's ok if the gva is remapped by other cpus on shadow guest,
3209 * it's a BUG if the gfn is not a mmio page.
3211 if (direct
&& !check_direct_spte_mmio_pf(spte
))
3215 * If the page table is zapped by other cpus, let CPU fault again on
3220 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
3222 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
3223 u32 error_code
, bool direct
)
3227 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
3232 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3233 u32 error_code
, bool prefault
)
3238 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3240 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3241 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
3243 r
= mmu_topup_memory_caches(vcpu
);
3248 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3250 gfn
= gva
>> PAGE_SHIFT
;
3252 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3253 error_code
, gfn
, prefault
);
3256 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3258 struct kvm_arch_async_pf arch
;
3260 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3262 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3263 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3265 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3268 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3270 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3271 kvm_event_needs_reinjection(vcpu
)))
3274 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3277 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3278 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3282 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3285 return false; /* *pfn has correct page already */
3287 if (!prefault
&& can_do_async_pf(vcpu
)) {
3288 trace_kvm_try_async_get_page(gva
, gfn
);
3289 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3290 trace_kvm_async_pf_doublefault(gva
, gfn
);
3291 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3293 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3297 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3302 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3309 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3310 unsigned long mmu_seq
;
3311 int write
= error_code
& PFERR_WRITE_MASK
;
3315 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3317 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3318 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3320 r
= mmu_topup_memory_caches(vcpu
);
3324 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3325 if (likely(!force_pt_level
)) {
3326 level
= mapping_level(vcpu
, gfn
);
3327 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3329 level
= PT_PAGE_TABLE_LEVEL
;
3331 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3334 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3337 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3340 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3343 spin_lock(&vcpu
->kvm
->mmu_lock
);
3344 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3346 make_mmu_pages_available(vcpu
);
3347 if (likely(!force_pt_level
))
3348 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3349 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3350 level
, gfn
, pfn
, prefault
);
3351 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3356 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3357 kvm_release_pfn_clean(pfn
);
3361 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3363 mmu_free_roots(vcpu
);
3366 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3367 struct kvm_mmu
*context
)
3369 context
->new_cr3
= nonpaging_new_cr3
;
3370 context
->page_fault
= nonpaging_page_fault
;
3371 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3372 context
->free
= nonpaging_free
;
3373 context
->sync_page
= nonpaging_sync_page
;
3374 context
->invlpg
= nonpaging_invlpg
;
3375 context
->update_pte
= nonpaging_update_pte
;
3376 context
->root_level
= 0;
3377 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3378 context
->root_hpa
= INVALID_PAGE
;
3379 context
->direct_map
= true;
3380 context
->nx
= false;
3384 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3386 ++vcpu
->stat
.tlb_flush
;
3387 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3390 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3392 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3393 mmu_free_roots(vcpu
);
3396 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3398 return kvm_read_cr3(vcpu
);
3401 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3402 struct x86_exception
*fault
)
3404 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3407 static void paging_free(struct kvm_vcpu
*vcpu
)
3409 nonpaging_free(vcpu
);
3412 static inline void protect_clean_gpte(unsigned *access
, unsigned gpte
)
3416 BUILD_BUG_ON(PT_WRITABLE_MASK
!= ACC_WRITE_MASK
);
3418 mask
= (unsigned)~ACC_WRITE_MASK
;
3419 /* Allow write access to dirty gptes */
3420 mask
|= (gpte
>> (PT_DIRTY_SHIFT
- PT_WRITABLE_SHIFT
)) & PT_WRITABLE_MASK
;
3424 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3427 if (unlikely(is_mmio_spte(*sptep
))) {
3428 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3429 mmu_spte_clear_no_track(sptep
);
3434 mark_mmio_spte(sptep
, gfn
, access
);
3441 static inline unsigned gpte_access(struct kvm_vcpu
*vcpu
, u64 gpte
)
3445 access
= (gpte
& (PT_WRITABLE_MASK
| PT_USER_MASK
)) | ACC_EXEC_MASK
;
3446 access
&= ~(gpte
>> PT64_NX_SHIFT
);
3451 static inline bool is_last_gpte(struct kvm_mmu
*mmu
, unsigned level
, unsigned gpte
)
3456 index
|= (gpte
& PT_PAGE_SIZE_MASK
) >> (PT_PAGE_SIZE_SHIFT
- 2);
3457 return mmu
->last_pte_bitmap
& (1 << index
);
3461 #include "paging_tmpl.h"
3465 #include "paging_tmpl.h"
3468 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3469 struct kvm_mmu
*context
)
3471 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3472 u64 exb_bit_rsvd
= 0;
3475 exb_bit_rsvd
= rsvd_bits(63, 63);
3476 switch (context
->root_level
) {
3477 case PT32_ROOT_LEVEL
:
3478 /* no rsvd bits for 2 level 4K page table entries */
3479 context
->rsvd_bits_mask
[0][1] = 0;
3480 context
->rsvd_bits_mask
[0][0] = 0;
3481 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3483 if (!is_pse(vcpu
)) {
3484 context
->rsvd_bits_mask
[1][1] = 0;
3488 if (is_cpuid_PSE36())
3489 /* 36bits PSE 4MB page */
3490 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3492 /* 32 bits PSE 4MB page */
3493 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3495 case PT32E_ROOT_LEVEL
:
3496 context
->rsvd_bits_mask
[0][2] =
3497 rsvd_bits(maxphyaddr
, 63) |
3498 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3499 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3500 rsvd_bits(maxphyaddr
, 62); /* PDE */
3501 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3502 rsvd_bits(maxphyaddr
, 62); /* PTE */
3503 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3504 rsvd_bits(maxphyaddr
, 62) |
3505 rsvd_bits(13, 20); /* large page */
3506 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3508 case PT64_ROOT_LEVEL
:
3509 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3510 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3511 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3512 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3513 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3514 rsvd_bits(maxphyaddr
, 51);
3515 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3516 rsvd_bits(maxphyaddr
, 51);
3517 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3518 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3519 rsvd_bits(maxphyaddr
, 51) |
3521 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3522 rsvd_bits(maxphyaddr
, 51) |
3523 rsvd_bits(13, 20); /* large page */
3524 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3529 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3531 unsigned bit
, byte
, pfec
;
3533 bool fault
, x
, w
, u
, wf
, uf
, ff
, smep
;
3535 smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3536 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
3539 wf
= pfec
& PFERR_WRITE_MASK
;
3540 uf
= pfec
& PFERR_USER_MASK
;
3541 ff
= pfec
& PFERR_FETCH_MASK
;
3542 for (bit
= 0; bit
< 8; ++bit
) {
3543 x
= bit
& ACC_EXEC_MASK
;
3544 w
= bit
& ACC_WRITE_MASK
;
3545 u
= bit
& ACC_USER_MASK
;
3547 /* Not really needed: !nx will cause pte.nx to fault */
3549 /* Allow supervisor writes if !cr0.wp */
3550 w
|= !is_write_protection(vcpu
) && !uf
;
3551 /* Disallow supervisor fetches of user code if cr4.smep */
3552 x
&= !(smep
&& u
&& !uf
);
3554 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
);
3555 map
|= fault
<< bit
;
3557 mmu
->permissions
[byte
] = map
;
3561 static void update_last_pte_bitmap(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3564 unsigned level
, root_level
= mmu
->root_level
;
3565 const unsigned ps_set_index
= 1 << 2; /* bit 2 of index: ps */
3567 if (root_level
== PT32E_ROOT_LEVEL
)
3569 /* PT_PAGE_TABLE_LEVEL always terminates */
3570 map
= 1 | (1 << ps_set_index
);
3571 for (level
= PT_DIRECTORY_LEVEL
; level
<= root_level
; ++level
) {
3572 if (level
<= PT_PDPE_LEVEL
3573 && (mmu
->root_level
>= PT32E_ROOT_LEVEL
|| is_pse(vcpu
)))
3574 map
|= 1 << (ps_set_index
| (level
- 1));
3576 mmu
->last_pte_bitmap
= map
;
3579 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3580 struct kvm_mmu
*context
,
3583 context
->nx
= is_nx(vcpu
);
3584 context
->root_level
= level
;
3586 reset_rsvds_bits_mask(vcpu
, context
);
3587 update_permission_bitmask(vcpu
, context
);
3588 update_last_pte_bitmap(vcpu
, context
);
3590 ASSERT(is_pae(vcpu
));
3591 context
->new_cr3
= paging_new_cr3
;
3592 context
->page_fault
= paging64_page_fault
;
3593 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3594 context
->sync_page
= paging64_sync_page
;
3595 context
->invlpg
= paging64_invlpg
;
3596 context
->update_pte
= paging64_update_pte
;
3597 context
->free
= paging_free
;
3598 context
->shadow_root_level
= level
;
3599 context
->root_hpa
= INVALID_PAGE
;
3600 context
->direct_map
= false;
3604 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3605 struct kvm_mmu
*context
)
3607 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3610 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3611 struct kvm_mmu
*context
)
3613 context
->nx
= false;
3614 context
->root_level
= PT32_ROOT_LEVEL
;
3616 reset_rsvds_bits_mask(vcpu
, context
);
3617 update_permission_bitmask(vcpu
, context
);
3618 update_last_pte_bitmap(vcpu
, context
);
3620 context
->new_cr3
= paging_new_cr3
;
3621 context
->page_fault
= paging32_page_fault
;
3622 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3623 context
->free
= paging_free
;
3624 context
->sync_page
= paging32_sync_page
;
3625 context
->invlpg
= paging32_invlpg
;
3626 context
->update_pte
= paging32_update_pte
;
3627 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3628 context
->root_hpa
= INVALID_PAGE
;
3629 context
->direct_map
= false;
3633 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3634 struct kvm_mmu
*context
)
3636 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3639 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3641 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3643 context
->base_role
.word
= 0;
3644 context
->new_cr3
= nonpaging_new_cr3
;
3645 context
->page_fault
= tdp_page_fault
;
3646 context
->free
= nonpaging_free
;
3647 context
->sync_page
= nonpaging_sync_page
;
3648 context
->invlpg
= nonpaging_invlpg
;
3649 context
->update_pte
= nonpaging_update_pte
;
3650 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3651 context
->root_hpa
= INVALID_PAGE
;
3652 context
->direct_map
= true;
3653 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3654 context
->get_cr3
= get_cr3
;
3655 context
->get_pdptr
= kvm_pdptr_read
;
3656 context
->inject_page_fault
= kvm_inject_page_fault
;
3658 if (!is_paging(vcpu
)) {
3659 context
->nx
= false;
3660 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3661 context
->root_level
= 0;
3662 } else if (is_long_mode(vcpu
)) {
3663 context
->nx
= is_nx(vcpu
);
3664 context
->root_level
= PT64_ROOT_LEVEL
;
3665 reset_rsvds_bits_mask(vcpu
, context
);
3666 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3667 } else if (is_pae(vcpu
)) {
3668 context
->nx
= is_nx(vcpu
);
3669 context
->root_level
= PT32E_ROOT_LEVEL
;
3670 reset_rsvds_bits_mask(vcpu
, context
);
3671 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3673 context
->nx
= false;
3674 context
->root_level
= PT32_ROOT_LEVEL
;
3675 reset_rsvds_bits_mask(vcpu
, context
);
3676 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3679 update_permission_bitmask(vcpu
, context
);
3680 update_last_pte_bitmap(vcpu
, context
);
3685 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3688 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3690 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3692 if (!is_paging(vcpu
))
3693 r
= nonpaging_init_context(vcpu
, context
);
3694 else if (is_long_mode(vcpu
))
3695 r
= paging64_init_context(vcpu
, context
);
3696 else if (is_pae(vcpu
))
3697 r
= paging32E_init_context(vcpu
, context
);
3699 r
= paging32_init_context(vcpu
, context
);
3701 vcpu
->arch
.mmu
.base_role
.nxe
= is_nx(vcpu
);
3702 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3703 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3704 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3705 = smep
&& !is_write_protection(vcpu
);
3709 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3711 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3713 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3715 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3716 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3717 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3718 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3723 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3725 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3727 g_context
->get_cr3
= get_cr3
;
3728 g_context
->get_pdptr
= kvm_pdptr_read
;
3729 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3732 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3733 * translation of l2_gpa to l1_gpa addresses is done using the
3734 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3735 * functions between mmu and nested_mmu are swapped.
3737 if (!is_paging(vcpu
)) {
3738 g_context
->nx
= false;
3739 g_context
->root_level
= 0;
3740 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3741 } else if (is_long_mode(vcpu
)) {
3742 g_context
->nx
= is_nx(vcpu
);
3743 g_context
->root_level
= PT64_ROOT_LEVEL
;
3744 reset_rsvds_bits_mask(vcpu
, g_context
);
3745 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3746 } else if (is_pae(vcpu
)) {
3747 g_context
->nx
= is_nx(vcpu
);
3748 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3749 reset_rsvds_bits_mask(vcpu
, g_context
);
3750 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3752 g_context
->nx
= false;
3753 g_context
->root_level
= PT32_ROOT_LEVEL
;
3754 reset_rsvds_bits_mask(vcpu
, g_context
);
3755 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3758 update_permission_bitmask(vcpu
, g_context
);
3759 update_last_pte_bitmap(vcpu
, g_context
);
3764 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3766 if (mmu_is_nested(vcpu
))
3767 return init_kvm_nested_mmu(vcpu
);
3768 else if (tdp_enabled
)
3769 return init_kvm_tdp_mmu(vcpu
);
3771 return init_kvm_softmmu(vcpu
);
3774 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3777 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3778 /* mmu.free() should set root_hpa = INVALID_PAGE */
3779 vcpu
->arch
.mmu
.free(vcpu
);
3782 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3784 destroy_kvm_mmu(vcpu
);
3785 return init_kvm_mmu(vcpu
);
3787 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3789 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3793 r
= mmu_topup_memory_caches(vcpu
);
3796 r
= mmu_alloc_roots(vcpu
);
3797 kvm_mmu_sync_roots(vcpu
);
3800 /* set_cr3() should ensure TLB has been flushed */
3801 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3805 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3807 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3809 mmu_free_roots(vcpu
);
3811 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3813 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3814 struct kvm_mmu_page
*sp
, u64
*spte
,
3817 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3818 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3822 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3823 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3826 static bool need_remote_flush(u64 old
, u64
new)
3828 if (!is_shadow_present_pte(old
))
3830 if (!is_shadow_present_pte(new))
3832 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3834 old
^= PT64_NX_MASK
;
3835 new ^= PT64_NX_MASK
;
3836 return (old
& ~new & PT64_PERM_MASK
) != 0;
3839 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3840 bool remote_flush
, bool local_flush
)
3846 kvm_flush_remote_tlbs(vcpu
->kvm
);
3847 else if (local_flush
)
3848 kvm_mmu_flush_tlb(vcpu
);
3851 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
3852 const u8
*new, int *bytes
)
3858 * Assume that the pte write on a page table of the same type
3859 * as the current vcpu paging mode since we update the sptes only
3860 * when they have the same mode.
3862 if (is_pae(vcpu
) && *bytes
== 4) {
3863 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3866 r
= kvm_read_guest(vcpu
->kvm
, *gpa
, &gentry
, 8);
3869 new = (const u8
*)&gentry
;
3874 gentry
= *(const u32
*)new;
3877 gentry
= *(const u64
*)new;
3888 * If we're seeing too many writes to a page, it may no longer be a page table,
3889 * or we may be forking, in which case it is better to unmap the page.
3891 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
3894 * Skip write-flooding detected for the sp whose level is 1, because
3895 * it can become unsync, then the guest page is not write-protected.
3897 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
3900 return ++sp
->write_flooding_count
>= 3;
3904 * Misaligned accesses are too much trouble to fix up; also, they usually
3905 * indicate a page is not used as a page table.
3907 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
3910 unsigned offset
, pte_size
, misaligned
;
3912 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3913 gpa
, bytes
, sp
->role
.word
);
3915 offset
= offset_in_page(gpa
);
3916 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3919 * Sometimes, the OS only writes the last one bytes to update status
3920 * bits, for example, in linux, andb instruction is used in clear_bit().
3922 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
3925 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3926 misaligned
|= bytes
< 4;
3931 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
3933 unsigned page_offset
, quadrant
;
3937 page_offset
= offset_in_page(gpa
);
3938 level
= sp
->role
.level
;
3940 if (!sp
->role
.cr4_pae
) {
3941 page_offset
<<= 1; /* 32->64 */
3943 * A 32-bit pde maps 4MB while the shadow pdes map
3944 * only 2MB. So we need to double the offset again
3945 * and zap two pdes instead of one.
3947 if (level
== PT32_ROOT_LEVEL
) {
3948 page_offset
&= ~7; /* kill rounding error */
3952 quadrant
= page_offset
>> PAGE_SHIFT
;
3953 page_offset
&= ~PAGE_MASK
;
3954 if (quadrant
!= sp
->role
.quadrant
)
3958 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3962 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3963 const u8
*new, int bytes
)
3965 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3966 union kvm_mmu_page_role mask
= { .word
= 0 };
3967 struct kvm_mmu_page
*sp
;
3968 LIST_HEAD(invalid_list
);
3969 u64 entry
, gentry
, *spte
;
3971 bool remote_flush
, local_flush
, zap_page
;
3974 * If we don't have indirect shadow pages, it means no page is
3975 * write-protected, so we can exit simply.
3977 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3980 zap_page
= remote_flush
= local_flush
= false;
3982 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3984 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
3987 * No need to care whether allocation memory is successful
3988 * or not since pte prefetch is skiped if it does not have
3989 * enough objects in the cache.
3991 mmu_topup_memory_caches(vcpu
);
3993 spin_lock(&vcpu
->kvm
->mmu_lock
);
3994 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3995 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3997 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3998 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
3999 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4000 detect_write_flooding(sp
)) {
4001 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
4003 ++vcpu
->kvm
->stat
.mmu_flooded
;
4007 spte
= get_written_sptes(sp
, gpa
, &npte
);
4014 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4016 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4017 & mask
.word
) && rmap_can_add(vcpu
))
4018 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4019 if (need_remote_flush(entry
, *spte
))
4020 remote_flush
= true;
4024 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
4025 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4026 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4027 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4030 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4035 if (vcpu
->arch
.mmu
.direct_map
)
4038 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4040 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4044 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4046 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4048 LIST_HEAD(invalid_list
);
4050 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4053 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4054 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4057 ++vcpu
->kvm
->stat
.mmu_recycled
;
4059 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4062 static bool is_mmio_page_fault(struct kvm_vcpu
*vcpu
, gva_t addr
)
4064 if (vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
))
4065 return vcpu_match_mmio_gpa(vcpu
, addr
);
4067 return vcpu_match_mmio_gva(vcpu
, addr
);
4070 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
4071 void *insn
, int insn_len
)
4073 int r
, emulation_type
= EMULTYPE_RETRY
;
4074 enum emulation_result er
;
4076 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
4085 if (is_mmio_page_fault(vcpu
, cr2
))
4088 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4093 case EMULATE_DO_MMIO
:
4094 ++vcpu
->stat
.mmio_exits
;
4104 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4106 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4108 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4109 kvm_mmu_flush_tlb(vcpu
);
4110 ++vcpu
->stat
.invlpg
;
4112 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4114 void kvm_enable_tdp(void)
4118 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4120 void kvm_disable_tdp(void)
4122 tdp_enabled
= false;
4124 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4126 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4128 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4129 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4130 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4133 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4141 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4142 * Therefore we need to allocate shadow page tables in the first
4143 * 4GB of memory, which happens to fit the DMA32 zone.
4145 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4149 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4150 for (i
= 0; i
< 4; ++i
)
4151 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4156 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4160 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4161 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4162 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4163 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4165 return alloc_mmu_pages(vcpu
);
4168 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4171 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4173 return init_kvm_mmu(vcpu
);
4176 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
4178 struct kvm_memory_slot
*memslot
;
4182 memslot
= id_to_memslot(kvm
->memslots
, slot
);
4183 last_gfn
= memslot
->base_gfn
+ memslot
->npages
- 1;
4185 spin_lock(&kvm
->mmu_lock
);
4187 for (i
= PT_PAGE_TABLE_LEVEL
;
4188 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
4189 unsigned long *rmapp
;
4190 unsigned long last_index
, index
;
4192 rmapp
= memslot
->arch
.rmap
[i
- PT_PAGE_TABLE_LEVEL
];
4193 last_index
= gfn_to_index(last_gfn
, memslot
->base_gfn
, i
);
4195 for (index
= 0; index
<= last_index
; ++index
, ++rmapp
) {
4197 __rmap_write_protect(kvm
, rmapp
, false);
4199 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
4200 kvm_flush_remote_tlbs(kvm
);
4201 cond_resched_lock(&kvm
->mmu_lock
);
4206 kvm_flush_remote_tlbs(kvm
);
4207 spin_unlock(&kvm
->mmu_lock
);
4210 #define BATCH_ZAP_PAGES 10
4211 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
4213 struct kvm_mmu_page
*sp
, *node
;
4217 list_for_each_entry_safe_reverse(sp
, node
,
4218 &kvm
->arch
.active_mmu_pages
, link
) {
4222 * No obsolete page exists before new created page since
4223 * active_mmu_pages is the FIFO list.
4225 if (!is_obsolete_sp(kvm
, sp
))
4229 * Since we are reversely walking the list and the invalid
4230 * list will be moved to the head, skip the invalid page
4231 * can help us to avoid the infinity list walking.
4233 if (sp
->role
.invalid
)
4237 * Need not flush tlb since we only zap the sp with invalid
4238 * generation number.
4240 if (batch
>= BATCH_ZAP_PAGES
&&
4241 cond_resched_lock(&kvm
->mmu_lock
)) {
4246 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
4247 &kvm
->arch
.zapped_obsolete_pages
);
4255 * Should flush tlb before free page tables since lockless-walking
4256 * may use the pages.
4258 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
4262 * Fast invalidate all shadow pages and use lock-break technique
4263 * to zap obsolete pages.
4265 * It's required when memslot is being deleted or VM is being
4266 * destroyed, in these cases, we should ensure that KVM MMU does
4267 * not use any resource of the being-deleted slot or all slots
4268 * after calling the function.
4270 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
4272 spin_lock(&kvm
->mmu_lock
);
4273 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
4274 kvm
->arch
.mmu_valid_gen
++;
4277 * Notify all vcpus to reload its shadow page table
4278 * and flush TLB. Then all vcpus will switch to new
4279 * shadow page table with the new mmu_valid_gen.
4281 * Note: we should do this under the protection of
4282 * mmu-lock, otherwise, vcpu would purge shadow page
4283 * but miss tlb flush.
4285 kvm_reload_remote_mmus(kvm
);
4287 kvm_zap_obsolete_pages(kvm
);
4288 spin_unlock(&kvm
->mmu_lock
);
4291 void kvm_mmu_zap_mmio_sptes(struct kvm
*kvm
)
4293 struct kvm_mmu_page
*sp
, *node
;
4294 LIST_HEAD(invalid_list
);
4296 spin_lock(&kvm
->mmu_lock
);
4298 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
) {
4299 if (!sp
->mmio_cached
)
4301 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
4305 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4306 spin_unlock(&kvm
->mmu_lock
);
4309 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
4311 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
4314 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
4317 int nr_to_scan
= sc
->nr_to_scan
;
4319 if (nr_to_scan
== 0)
4322 raw_spin_lock(&kvm_lock
);
4324 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4326 LIST_HEAD(invalid_list
);
4329 * Never scan more than sc->nr_to_scan VM instances.
4330 * Will not hit this condition practically since we do not try
4331 * to shrink more than one VM and it is very unlikely to see
4332 * !n_used_mmu_pages so many times.
4337 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4338 * here. We may skip a VM instance errorneosly, but we do not
4339 * want to shrink a VM that only started to populate its MMU
4342 if (!kvm
->arch
.n_used_mmu_pages
&&
4343 !kvm_has_zapped_obsolete_pages(kvm
))
4346 idx
= srcu_read_lock(&kvm
->srcu
);
4347 spin_lock(&kvm
->mmu_lock
);
4349 if (kvm_has_zapped_obsolete_pages(kvm
)) {
4350 kvm_mmu_commit_zap_page(kvm
,
4351 &kvm
->arch
.zapped_obsolete_pages
);
4355 prepare_zap_oldest_mmu_page(kvm
, &invalid_list
);
4356 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4359 spin_unlock(&kvm
->mmu_lock
);
4360 srcu_read_unlock(&kvm
->srcu
, idx
);
4362 list_move_tail(&kvm
->vm_list
, &vm_list
);
4366 raw_spin_unlock(&kvm_lock
);
4369 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
4372 static struct shrinker mmu_shrinker
= {
4373 .shrink
= mmu_shrink
,
4374 .seeks
= DEFAULT_SEEKS
* 10,
4377 static void mmu_destroy_caches(void)
4379 if (pte_list_desc_cache
)
4380 kmem_cache_destroy(pte_list_desc_cache
);
4381 if (mmu_page_header_cache
)
4382 kmem_cache_destroy(mmu_page_header_cache
);
4385 int kvm_mmu_module_init(void)
4387 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
4388 sizeof(struct pte_list_desc
),
4390 if (!pte_list_desc_cache
)
4393 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
4394 sizeof(struct kvm_mmu_page
),
4396 if (!mmu_page_header_cache
)
4399 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
4402 register_shrinker(&mmu_shrinker
);
4407 mmu_destroy_caches();
4412 * Caculate mmu pages needed for kvm.
4414 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
4416 unsigned int nr_mmu_pages
;
4417 unsigned int nr_pages
= 0;
4418 struct kvm_memslots
*slots
;
4419 struct kvm_memory_slot
*memslot
;
4421 slots
= kvm_memslots(kvm
);
4423 kvm_for_each_memslot(memslot
, slots
)
4424 nr_pages
+= memslot
->npages
;
4426 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
4427 nr_mmu_pages
= max(nr_mmu_pages
,
4428 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
4430 return nr_mmu_pages
;
4433 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4435 struct kvm_shadow_walk_iterator iterator
;
4439 walk_shadow_page_lockless_begin(vcpu
);
4440 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4441 sptes
[iterator
.level
-1] = spte
;
4443 if (!is_shadow_present_pte(spte
))
4446 walk_shadow_page_lockless_end(vcpu
);
4450 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4452 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4456 destroy_kvm_mmu(vcpu
);
4457 free_mmu_pages(vcpu
);
4458 mmu_free_memory_caches(vcpu
);
4461 void kvm_mmu_module_exit(void)
4463 mmu_destroy_caches();
4464 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4465 unregister_shrinker(&mmu_shrinker
);
4466 mmu_audit_disable();