2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
51 * When setting this variable to true it enables Two-Dimensional-Paging
52 * where the hardware walks 2 page tables:
53 * 1. the guest-virtual to guest-physical
54 * 2. while doing 1. it walks guest-physical to host-physical
55 * If the hardware supports that we don't need to do shadow paging.
57 bool tdp_enabled
= false;
61 AUDIT_POST_PAGE_FAULT
,
72 module_param(dbg
, bool, 0644);
74 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
75 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
76 #define MMU_WARN_ON(x) WARN_ON(x)
78 #define pgprintk(x...) do { } while (0)
79 #define rmap_printk(x...) do { } while (0)
80 #define MMU_WARN_ON(x) do { } while (0)
83 #define PTE_PREFETCH_NUM 8
85 #define PT_FIRST_AVAIL_BITS_SHIFT 10
86 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
88 #define PT64_LEVEL_BITS 9
90 #define PT64_LEVEL_SHIFT(level) \
91 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
93 #define PT64_INDEX(address, level)\
94 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
97 #define PT32_LEVEL_BITS 10
99 #define PT32_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
102 #define PT32_LVL_OFFSET_MASK(level) \
103 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
104 * PT32_LEVEL_BITS))) - 1))
106 #define PT32_INDEX(address, level)\
107 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
110 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
111 #define PT64_DIR_BASE_ADDR_MASK \
112 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
113 #define PT64_LVL_ADDR_MASK(level) \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT64_LEVEL_BITS))) - 1))
116 #define PT64_LVL_OFFSET_MASK(level) \
117 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
118 * PT64_LEVEL_BITS))) - 1))
120 #define PT32_BASE_ADDR_MASK PAGE_MASK
121 #define PT32_DIR_BASE_ADDR_MASK \
122 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
123 #define PT32_LVL_ADDR_MASK(level) \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
128 | shadow_x_mask | shadow_nx_mask)
130 #define ACC_EXEC_MASK 1
131 #define ACC_WRITE_MASK PT_WRITABLE_MASK
132 #define ACC_USER_MASK PT_USER_MASK
133 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
135 /* The mask for the R/X bits in EPT PTEs */
136 #define PT64_EPT_READABLE_MASK 0x1ull
137 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
139 #include <trace/events/kvm.h>
141 #define CREATE_TRACE_POINTS
142 #include "mmutrace.h"
144 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
145 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
147 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
149 /* make pte_list_desc fit well in cache line */
150 #define PTE_LIST_EXT 3
152 struct pte_list_desc
{
153 u64
*sptes
[PTE_LIST_EXT
];
154 struct pte_list_desc
*more
;
157 struct kvm_shadow_walk_iterator
{
165 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)); \
168 shadow_walk_next(&(_walker)))
170 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
171 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
172 shadow_walk_okay(&(_walker)) && \
173 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
174 __shadow_walk_next(&(_walker), spte))
176 static struct kmem_cache
*pte_list_desc_cache
;
177 static struct kmem_cache
*mmu_page_header_cache
;
178 static struct percpu_counter kvm_total_used_mmu_pages
;
180 static u64 __read_mostly shadow_nx_mask
;
181 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
182 static u64 __read_mostly shadow_user_mask
;
183 static u64 __read_mostly shadow_accessed_mask
;
184 static u64 __read_mostly shadow_dirty_mask
;
185 static u64 __read_mostly shadow_mmio_mask
;
186 static u64 __read_mostly shadow_present_mask
;
189 * The mask/value to distinguish a PTE that has been marked not-present for
190 * access tracking purposes.
191 * The mask would be either 0 if access tracking is disabled, or
192 * SPTE_SPECIAL_MASK|VMX_EPT_RWX_MASK if access tracking is enabled.
194 static u64 __read_mostly shadow_acc_track_mask
;
195 static const u64 shadow_acc_track_value
= SPTE_SPECIAL_MASK
;
198 * The mask/shift to use for saving the original R/X bits when marking the PTE
199 * as not-present for access tracking purposes. We do not save the W bit as the
200 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
201 * restored only when a write is attempted to the page.
203 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
204 PT64_EPT_EXECUTABLE_MASK
;
205 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
207 static void mmu_spte_set(u64
*sptep
, u64 spte
);
208 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
210 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
212 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
214 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
216 static inline bool is_access_track_spte(u64 spte
)
218 /* Always false if shadow_acc_track_mask is zero. */
219 return (spte
& shadow_acc_track_mask
) == shadow_acc_track_value
;
223 * the low bit of the generation number is always presumed to be zero.
224 * This disables mmio caching during memslot updates. The concept is
225 * similar to a seqcount but instead of retrying the access we just punt
226 * and ignore the cache.
228 * spte bits 3-11 are used as bits 1-9 of the generation number,
229 * the bits 52-61 are used as bits 10-19 of the generation number.
231 #define MMIO_SPTE_GEN_LOW_SHIFT 2
232 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
234 #define MMIO_GEN_SHIFT 20
235 #define MMIO_GEN_LOW_SHIFT 10
236 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
237 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
239 static u64
generation_mmio_spte_mask(unsigned int gen
)
243 WARN_ON(gen
& ~MMIO_GEN_MASK
);
245 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
246 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
250 static unsigned int get_mmio_spte_generation(u64 spte
)
254 spte
&= ~shadow_mmio_mask
;
256 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
257 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
261 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
263 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
266 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
269 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
270 u64 mask
= generation_mmio_spte_mask(gen
);
272 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
273 mask
|= shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
;
275 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
276 mmu_spte_set(sptep
, mask
);
279 static bool is_mmio_spte(u64 spte
)
281 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
284 static gfn_t
get_mmio_spte_gfn(u64 spte
)
286 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
287 return (spte
& ~mask
) >> PAGE_SHIFT
;
290 static unsigned get_mmio_spte_access(u64 spte
)
292 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
293 return (spte
& ~mask
) & ~PAGE_MASK
;
296 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
297 kvm_pfn_t pfn
, unsigned access
)
299 if (unlikely(is_noslot_pfn(pfn
))) {
300 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
307 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
309 unsigned int kvm_gen
, spte_gen
;
311 kvm_gen
= kvm_current_mmio_generation(vcpu
);
312 spte_gen
= get_mmio_spte_generation(spte
);
314 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
315 return likely(kvm_gen
== spte_gen
);
318 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
319 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
322 if (acc_track_mask
!= 0)
323 acc_track_mask
|= SPTE_SPECIAL_MASK
;
325 shadow_user_mask
= user_mask
;
326 shadow_accessed_mask
= accessed_mask
;
327 shadow_dirty_mask
= dirty_mask
;
328 shadow_nx_mask
= nx_mask
;
329 shadow_x_mask
= x_mask
;
330 shadow_present_mask
= p_mask
;
331 shadow_acc_track_mask
= acc_track_mask
;
332 WARN_ON(shadow_accessed_mask
!= 0 && shadow_acc_track_mask
!= 0);
334 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
336 void kvm_mmu_clear_all_pte_masks(void)
338 shadow_user_mask
= 0;
339 shadow_accessed_mask
= 0;
340 shadow_dirty_mask
= 0;
343 shadow_mmio_mask
= 0;
344 shadow_present_mask
= 0;
345 shadow_acc_track_mask
= 0;
348 static int is_cpuid_PSE36(void)
353 static int is_nx(struct kvm_vcpu
*vcpu
)
355 return vcpu
->arch
.efer
& EFER_NX
;
358 static int is_shadow_present_pte(u64 pte
)
360 return (pte
!= 0) && !is_mmio_spte(pte
);
363 static int is_large_pte(u64 pte
)
365 return pte
& PT_PAGE_SIZE_MASK
;
368 static int is_last_spte(u64 pte
, int level
)
370 if (level
== PT_PAGE_TABLE_LEVEL
)
372 if (is_large_pte(pte
))
377 static bool is_executable_pte(u64 spte
)
379 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
382 static kvm_pfn_t
spte_to_pfn(u64 pte
)
384 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
387 static gfn_t
pse36_gfn_delta(u32 gpte
)
389 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
391 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
395 static void __set_spte(u64
*sptep
, u64 spte
)
397 WRITE_ONCE(*sptep
, spte
);
400 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
402 WRITE_ONCE(*sptep
, spte
);
405 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
407 return xchg(sptep
, spte
);
410 static u64
__get_spte_lockless(u64
*sptep
)
412 return ACCESS_ONCE(*sptep
);
423 static void count_spte_clear(u64
*sptep
, u64 spte
)
425 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
427 if (is_shadow_present_pte(spte
))
430 /* Ensure the spte is completely set before we increase the count */
432 sp
->clear_spte_count
++;
435 static void __set_spte(u64
*sptep
, u64 spte
)
437 union split_spte
*ssptep
, sspte
;
439 ssptep
= (union split_spte
*)sptep
;
440 sspte
= (union split_spte
)spte
;
442 ssptep
->spte_high
= sspte
.spte_high
;
445 * If we map the spte from nonpresent to present, We should store
446 * the high bits firstly, then set present bit, so cpu can not
447 * fetch this spte while we are setting the spte.
451 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
454 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
456 union split_spte
*ssptep
, sspte
;
458 ssptep
= (union split_spte
*)sptep
;
459 sspte
= (union split_spte
)spte
;
461 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
464 * If we map the spte from present to nonpresent, we should clear
465 * present bit firstly to avoid vcpu fetch the old high bits.
469 ssptep
->spte_high
= sspte
.spte_high
;
470 count_spte_clear(sptep
, spte
);
473 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
475 union split_spte
*ssptep
, sspte
, orig
;
477 ssptep
= (union split_spte
*)sptep
;
478 sspte
= (union split_spte
)spte
;
480 /* xchg acts as a barrier before the setting of the high bits */
481 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
482 orig
.spte_high
= ssptep
->spte_high
;
483 ssptep
->spte_high
= sspte
.spte_high
;
484 count_spte_clear(sptep
, spte
);
490 * The idea using the light way get the spte on x86_32 guest is from
491 * gup_get_pte(arch/x86/mm/gup.c).
493 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
494 * coalesces them and we are running out of the MMU lock. Therefore
495 * we need to protect against in-progress updates of the spte.
497 * Reading the spte while an update is in progress may get the old value
498 * for the high part of the spte. The race is fine for a present->non-present
499 * change (because the high part of the spte is ignored for non-present spte),
500 * but for a present->present change we must reread the spte.
502 * All such changes are done in two steps (present->non-present and
503 * non-present->present), hence it is enough to count the number of
504 * present->non-present updates: if it changed while reading the spte,
505 * we might have hit the race. This is done using clear_spte_count.
507 static u64
__get_spte_lockless(u64
*sptep
)
509 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
510 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
514 count
= sp
->clear_spte_count
;
517 spte
.spte_low
= orig
->spte_low
;
520 spte
.spte_high
= orig
->spte_high
;
523 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
524 count
!= sp
->clear_spte_count
))
531 static bool spte_can_locklessly_be_made_writable(u64 spte
)
533 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
534 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
537 static bool spte_has_volatile_bits(u64 spte
)
539 if (!is_shadow_present_pte(spte
))
543 * Always atomically update spte if it can be updated
544 * out of mmu-lock, it can ensure dirty bit is not lost,
545 * also, it can help us to get a stable is_writable_pte()
546 * to ensure tlb flush is not missed.
548 if (spte_can_locklessly_be_made_writable(spte
) ||
549 is_access_track_spte(spte
))
552 if (shadow_accessed_mask
) {
553 if ((spte
& shadow_accessed_mask
) == 0 ||
554 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
561 static bool is_accessed_spte(u64 spte
)
563 return shadow_accessed_mask
? spte
& shadow_accessed_mask
564 : !is_access_track_spte(spte
);
567 static bool is_dirty_spte(u64 spte
)
569 return shadow_dirty_mask
? spte
& shadow_dirty_mask
570 : spte
& PT_WRITABLE_MASK
;
573 /* Rules for using mmu_spte_set:
574 * Set the sptep from nonpresent to present.
575 * Note: the sptep being assigned *must* be either not present
576 * or in a state where the hardware will not attempt to update
579 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
581 WARN_ON(is_shadow_present_pte(*sptep
));
582 __set_spte(sptep
, new_spte
);
586 * Update the SPTE (excluding the PFN), but do not track changes in its
587 * accessed/dirty status.
589 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
591 u64 old_spte
= *sptep
;
593 WARN_ON(!is_shadow_present_pte(new_spte
));
595 if (!is_shadow_present_pte(old_spte
)) {
596 mmu_spte_set(sptep
, new_spte
);
600 if (!spte_has_volatile_bits(old_spte
))
601 __update_clear_spte_fast(sptep
, new_spte
);
603 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
605 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
610 /* Rules for using mmu_spte_update:
611 * Update the state bits, it means the mapped pfn is not changed.
613 * Whenever we overwrite a writable spte with a read-only one we
614 * should flush remote TLBs. Otherwise rmap_write_protect
615 * will find a read-only spte, even though the writable spte
616 * might be cached on a CPU's TLB, the return value indicates this
619 * Returns true if the TLB needs to be flushed
621 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
624 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
626 if (!is_shadow_present_pte(old_spte
))
630 * For the spte updated out of mmu-lock is safe, since
631 * we always atomically update it, see the comments in
632 * spte_has_volatile_bits().
634 if (spte_can_locklessly_be_made_writable(old_spte
) &&
635 !is_writable_pte(new_spte
))
639 * Flush TLB when accessed/dirty states are changed in the page tables,
640 * to guarantee consistency between TLB and page tables.
643 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
645 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
648 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
650 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
657 * Rules for using mmu_spte_clear_track_bits:
658 * It sets the sptep from present to nonpresent, and track the
659 * state bits, it is used to clear the last level sptep.
660 * Returns non-zero if the PTE was previously valid.
662 static int mmu_spte_clear_track_bits(u64
*sptep
)
665 u64 old_spte
= *sptep
;
667 if (!spte_has_volatile_bits(old_spte
))
668 __update_clear_spte_fast(sptep
, 0ull);
670 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
672 if (!is_shadow_present_pte(old_spte
))
675 pfn
= spte_to_pfn(old_spte
);
678 * KVM does not hold the refcount of the page used by
679 * kvm mmu, before reclaiming the page, we should
680 * unmap it from mmu first.
682 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
684 if (is_accessed_spte(old_spte
))
685 kvm_set_pfn_accessed(pfn
);
687 if (is_dirty_spte(old_spte
))
688 kvm_set_pfn_dirty(pfn
);
694 * Rules for using mmu_spte_clear_no_track:
695 * Directly clear spte without caring the state bits of sptep,
696 * it is used to set the upper level spte.
698 static void mmu_spte_clear_no_track(u64
*sptep
)
700 __update_clear_spte_fast(sptep
, 0ull);
703 static u64
mmu_spte_get_lockless(u64
*sptep
)
705 return __get_spte_lockless(sptep
);
708 static u64
mark_spte_for_access_track(u64 spte
)
710 if (shadow_accessed_mask
!= 0)
711 return spte
& ~shadow_accessed_mask
;
713 if (shadow_acc_track_mask
== 0 || is_access_track_spte(spte
))
717 * Making an Access Tracking PTE will result in removal of write access
718 * from the PTE. So, verify that we will be able to restore the write
719 * access in the fast page fault path later on.
721 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
722 !spte_can_locklessly_be_made_writable(spte
),
723 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
725 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
726 shadow_acc_track_saved_bits_shift
),
727 "kvm: Access Tracking saved bit locations are not zero\n");
729 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
730 shadow_acc_track_saved_bits_shift
;
731 spte
&= ~shadow_acc_track_mask
;
732 spte
|= shadow_acc_track_value
;
737 /* Restore an acc-track PTE back to a regular PTE */
738 static u64
restore_acc_track_spte(u64 spte
)
741 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
742 & shadow_acc_track_saved_bits_mask
;
744 WARN_ON_ONCE(!is_access_track_spte(spte
));
746 new_spte
&= ~shadow_acc_track_mask
;
747 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
748 shadow_acc_track_saved_bits_shift
);
749 new_spte
|= saved_bits
;
754 /* Returns the Accessed status of the PTE and resets it at the same time. */
755 static bool mmu_spte_age(u64
*sptep
)
757 u64 spte
= mmu_spte_get_lockless(sptep
);
759 if (!is_accessed_spte(spte
))
762 if (shadow_accessed_mask
) {
763 clear_bit((ffs(shadow_accessed_mask
) - 1),
764 (unsigned long *)sptep
);
767 * Capture the dirty status of the page, so that it doesn't get
768 * lost when the SPTE is marked for access tracking.
770 if (is_writable_pte(spte
))
771 kvm_set_pfn_dirty(spte_to_pfn(spte
));
773 spte
= mark_spte_for_access_track(spte
);
774 mmu_spte_update_no_track(sptep
, spte
);
780 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
783 * Prevent page table teardown by making any free-er wait during
784 * kvm_flush_remote_tlbs() IPI to all active vcpus.
789 * Make sure a following spte read is not reordered ahead of the write
792 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
795 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
798 * Make sure the write to vcpu->mode is not reordered in front of
799 * reads to sptes. If it does, kvm_commit_zap_page() can see us
800 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
802 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
806 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
807 struct kmem_cache
*base_cache
, int min
)
811 if (cache
->nobjs
>= min
)
813 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
814 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
817 cache
->objects
[cache
->nobjs
++] = obj
;
822 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
827 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
828 struct kmem_cache
*cache
)
831 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
834 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
839 if (cache
->nobjs
>= min
)
841 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
842 page
= (void *)__get_free_page(GFP_KERNEL
);
845 cache
->objects
[cache
->nobjs
++] = page
;
850 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
853 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
856 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
860 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
861 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
864 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
867 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
868 mmu_page_header_cache
, 4);
873 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
875 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
876 pte_list_desc_cache
);
877 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
878 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
879 mmu_page_header_cache
);
882 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
887 p
= mc
->objects
[--mc
->nobjs
];
891 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
893 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
896 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
898 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
901 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
903 if (!sp
->role
.direct
)
904 return sp
->gfns
[index
];
906 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
909 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
912 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
914 sp
->gfns
[index
] = gfn
;
918 * Return the pointer to the large page information for a given gfn,
919 * handling slots that are not large page aligned.
921 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
922 struct kvm_memory_slot
*slot
,
927 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
928 return &slot
->arch
.lpage_info
[level
- 2][idx
];
931 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
932 gfn_t gfn
, int count
)
934 struct kvm_lpage_info
*linfo
;
937 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
938 linfo
= lpage_info_slot(gfn
, slot
, i
);
939 linfo
->disallow_lpage
+= count
;
940 WARN_ON(linfo
->disallow_lpage
< 0);
944 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
946 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
949 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
951 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
954 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
956 struct kvm_memslots
*slots
;
957 struct kvm_memory_slot
*slot
;
960 kvm
->arch
.indirect_shadow_pages
++;
962 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
963 slot
= __gfn_to_memslot(slots
, gfn
);
965 /* the non-leaf shadow pages are keeping readonly. */
966 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
967 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
968 KVM_PAGE_TRACK_WRITE
);
970 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
973 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
975 struct kvm_memslots
*slots
;
976 struct kvm_memory_slot
*slot
;
979 kvm
->arch
.indirect_shadow_pages
--;
981 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
982 slot
= __gfn_to_memslot(slots
, gfn
);
983 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
984 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
985 KVM_PAGE_TRACK_WRITE
);
987 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
990 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
991 struct kvm_memory_slot
*slot
)
993 struct kvm_lpage_info
*linfo
;
996 linfo
= lpage_info_slot(gfn
, slot
, level
);
997 return !!linfo
->disallow_lpage
;
1003 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1006 struct kvm_memory_slot
*slot
;
1008 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1009 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
1012 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
1014 unsigned long page_size
;
1017 page_size
= kvm_host_page_size(kvm
, gfn
);
1019 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1020 if (page_size
>= KVM_HPAGE_SIZE(i
))
1029 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
1032 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1034 if (no_dirty_log
&& slot
->dirty_bitmap
)
1040 static struct kvm_memory_slot
*
1041 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1044 struct kvm_memory_slot
*slot
;
1046 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1047 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
1053 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
1054 bool *force_pt_level
)
1056 int host_level
, level
, max_level
;
1057 struct kvm_memory_slot
*slot
;
1059 if (unlikely(*force_pt_level
))
1060 return PT_PAGE_TABLE_LEVEL
;
1062 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
1063 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
1064 if (unlikely(*force_pt_level
))
1065 return PT_PAGE_TABLE_LEVEL
;
1067 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
1069 if (host_level
== PT_PAGE_TABLE_LEVEL
)
1072 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
1074 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
1075 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
1082 * About rmap_head encoding:
1084 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1085 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1086 * pte_list_desc containing more mappings.
1090 * Returns the number of pointers in the rmap chain, not counting the new one.
1092 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1093 struct kvm_rmap_head
*rmap_head
)
1095 struct pte_list_desc
*desc
;
1098 if (!rmap_head
->val
) {
1099 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1100 rmap_head
->val
= (unsigned long)spte
;
1101 } else if (!(rmap_head
->val
& 1)) {
1102 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1103 desc
= mmu_alloc_pte_list_desc(vcpu
);
1104 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1105 desc
->sptes
[1] = spte
;
1106 rmap_head
->val
= (unsigned long)desc
| 1;
1109 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1110 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1111 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1113 count
+= PTE_LIST_EXT
;
1115 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1116 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1119 for (i
= 0; desc
->sptes
[i
]; ++i
)
1121 desc
->sptes
[i
] = spte
;
1127 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1128 struct pte_list_desc
*desc
, int i
,
1129 struct pte_list_desc
*prev_desc
)
1133 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1135 desc
->sptes
[i
] = desc
->sptes
[j
];
1136 desc
->sptes
[j
] = NULL
;
1139 if (!prev_desc
&& !desc
->more
)
1140 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1143 prev_desc
->more
= desc
->more
;
1145 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1146 mmu_free_pte_list_desc(desc
);
1149 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1151 struct pte_list_desc
*desc
;
1152 struct pte_list_desc
*prev_desc
;
1155 if (!rmap_head
->val
) {
1156 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1158 } else if (!(rmap_head
->val
& 1)) {
1159 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1160 if ((u64
*)rmap_head
->val
!= spte
) {
1161 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1166 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1167 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1170 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1171 if (desc
->sptes
[i
] == spte
) {
1172 pte_list_desc_remove_entry(rmap_head
,
1173 desc
, i
, prev_desc
);
1180 pr_err("pte_list_remove: %p many->many\n", spte
);
1185 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1186 struct kvm_memory_slot
*slot
)
1190 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1191 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1194 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1195 struct kvm_mmu_page
*sp
)
1197 struct kvm_memslots
*slots
;
1198 struct kvm_memory_slot
*slot
;
1200 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1201 slot
= __gfn_to_memslot(slots
, gfn
);
1202 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1205 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1207 struct kvm_mmu_memory_cache
*cache
;
1209 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1210 return mmu_memory_cache_free_objects(cache
);
1213 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1215 struct kvm_mmu_page
*sp
;
1216 struct kvm_rmap_head
*rmap_head
;
1218 sp
= page_header(__pa(spte
));
1219 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1220 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1221 return pte_list_add(vcpu
, spte
, rmap_head
);
1224 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1226 struct kvm_mmu_page
*sp
;
1228 struct kvm_rmap_head
*rmap_head
;
1230 sp
= page_header(__pa(spte
));
1231 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1232 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1233 pte_list_remove(spte
, rmap_head
);
1237 * Used by the following functions to iterate through the sptes linked by a
1238 * rmap. All fields are private and not assumed to be used outside.
1240 struct rmap_iterator
{
1241 /* private fields */
1242 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1243 int pos
; /* index of the sptep */
1247 * Iteration must be started by this function. This should also be used after
1248 * removing/dropping sptes from the rmap link because in such cases the
1249 * information in the itererator may not be valid.
1251 * Returns sptep if found, NULL otherwise.
1253 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1254 struct rmap_iterator
*iter
)
1258 if (!rmap_head
->val
)
1261 if (!(rmap_head
->val
& 1)) {
1263 sptep
= (u64
*)rmap_head
->val
;
1267 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1269 sptep
= iter
->desc
->sptes
[iter
->pos
];
1271 BUG_ON(!is_shadow_present_pte(*sptep
));
1276 * Must be used with a valid iterator: e.g. after rmap_get_first().
1278 * Returns sptep if found, NULL otherwise.
1280 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1285 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1287 sptep
= iter
->desc
->sptes
[iter
->pos
];
1292 iter
->desc
= iter
->desc
->more
;
1296 /* desc->sptes[0] cannot be NULL */
1297 sptep
= iter
->desc
->sptes
[iter
->pos
];
1304 BUG_ON(!is_shadow_present_pte(*sptep
));
1308 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1309 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1310 _spte_; _spte_ = rmap_get_next(_iter_))
1312 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1314 if (mmu_spte_clear_track_bits(sptep
))
1315 rmap_remove(kvm
, sptep
);
1319 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1321 if (is_large_pte(*sptep
)) {
1322 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1323 PT_PAGE_TABLE_LEVEL
);
1324 drop_spte(kvm
, sptep
);
1332 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1334 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1335 kvm_flush_remote_tlbs(vcpu
->kvm
);
1339 * Write-protect on the specified @sptep, @pt_protect indicates whether
1340 * spte write-protection is caused by protecting shadow page table.
1342 * Note: write protection is difference between dirty logging and spte
1344 * - for dirty logging, the spte can be set to writable at anytime if
1345 * its dirty bitmap is properly set.
1346 * - for spte protection, the spte can be writable only after unsync-ing
1349 * Return true if tlb need be flushed.
1351 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1355 if (!is_writable_pte(spte
) &&
1356 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1359 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1362 spte
&= ~SPTE_MMU_WRITEABLE
;
1363 spte
= spte
& ~PT_WRITABLE_MASK
;
1365 return mmu_spte_update(sptep
, spte
);
1368 static bool __rmap_write_protect(struct kvm
*kvm
,
1369 struct kvm_rmap_head
*rmap_head
,
1373 struct rmap_iterator iter
;
1376 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1377 flush
|= spte_write_protect(sptep
, pt_protect
);
1382 static bool spte_clear_dirty(u64
*sptep
)
1386 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1388 spte
&= ~shadow_dirty_mask
;
1390 return mmu_spte_update(sptep
, spte
);
1393 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1396 struct rmap_iterator iter
;
1399 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1400 flush
|= spte_clear_dirty(sptep
);
1405 static bool spte_set_dirty(u64
*sptep
)
1409 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1411 spte
|= shadow_dirty_mask
;
1413 return mmu_spte_update(sptep
, spte
);
1416 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1419 struct rmap_iterator iter
;
1422 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1423 flush
|= spte_set_dirty(sptep
);
1429 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1430 * @kvm: kvm instance
1431 * @slot: slot to protect
1432 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1433 * @mask: indicates which pages we should protect
1435 * Used when we do not need to care about huge page mappings: e.g. during dirty
1436 * logging we do not have any such mappings.
1438 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1439 struct kvm_memory_slot
*slot
,
1440 gfn_t gfn_offset
, unsigned long mask
)
1442 struct kvm_rmap_head
*rmap_head
;
1445 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1446 PT_PAGE_TABLE_LEVEL
, slot
);
1447 __rmap_write_protect(kvm
, rmap_head
, false);
1449 /* clear the first set bit */
1455 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1456 * @kvm: kvm instance
1457 * @slot: slot to clear D-bit
1458 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1459 * @mask: indicates which pages we should clear D-bit
1461 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1463 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1464 struct kvm_memory_slot
*slot
,
1465 gfn_t gfn_offset
, unsigned long mask
)
1467 struct kvm_rmap_head
*rmap_head
;
1470 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1471 PT_PAGE_TABLE_LEVEL
, slot
);
1472 __rmap_clear_dirty(kvm
, rmap_head
);
1474 /* clear the first set bit */
1478 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1481 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1484 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1485 * enable dirty logging for them.
1487 * Used when we do not need to care about huge page mappings: e.g. during dirty
1488 * logging we do not have any such mappings.
1490 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1491 struct kvm_memory_slot
*slot
,
1492 gfn_t gfn_offset
, unsigned long mask
)
1494 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1495 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1498 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1501 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1502 struct kvm_memory_slot
*slot
, u64 gfn
)
1504 struct kvm_rmap_head
*rmap_head
;
1506 bool write_protected
= false;
1508 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1509 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1510 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1513 return write_protected
;
1516 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1518 struct kvm_memory_slot
*slot
;
1520 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1521 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1524 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1527 struct rmap_iterator iter
;
1530 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1531 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1533 drop_spte(kvm
, sptep
);
1540 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1541 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1544 return kvm_zap_rmapp(kvm
, rmap_head
);
1547 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1548 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1552 struct rmap_iterator iter
;
1555 pte_t
*ptep
= (pte_t
*)data
;
1558 WARN_ON(pte_huge(*ptep
));
1559 new_pfn
= pte_pfn(*ptep
);
1562 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1563 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1564 sptep
, *sptep
, gfn
, level
);
1568 if (pte_write(*ptep
)) {
1569 drop_spte(kvm
, sptep
);
1572 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1573 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1575 new_spte
&= ~PT_WRITABLE_MASK
;
1576 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1578 new_spte
= mark_spte_for_access_track(new_spte
);
1580 mmu_spte_clear_track_bits(sptep
);
1581 mmu_spte_set(sptep
, new_spte
);
1586 kvm_flush_remote_tlbs(kvm
);
1591 struct slot_rmap_walk_iterator
{
1593 struct kvm_memory_slot
*slot
;
1599 /* output fields. */
1601 struct kvm_rmap_head
*rmap
;
1604 /* private field. */
1605 struct kvm_rmap_head
*end_rmap
;
1609 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1611 iterator
->level
= level
;
1612 iterator
->gfn
= iterator
->start_gfn
;
1613 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1614 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1619 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1620 struct kvm_memory_slot
*slot
, int start_level
,
1621 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1623 iterator
->slot
= slot
;
1624 iterator
->start_level
= start_level
;
1625 iterator
->end_level
= end_level
;
1626 iterator
->start_gfn
= start_gfn
;
1627 iterator
->end_gfn
= end_gfn
;
1629 rmap_walk_init_level(iterator
, iterator
->start_level
);
1632 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1634 return !!iterator
->rmap
;
1637 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1639 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1640 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1644 if (++iterator
->level
> iterator
->end_level
) {
1645 iterator
->rmap
= NULL
;
1649 rmap_walk_init_level(iterator
, iterator
->level
);
1652 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1653 _start_gfn, _end_gfn, _iter_) \
1654 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1655 _end_level_, _start_gfn, _end_gfn); \
1656 slot_rmap_walk_okay(_iter_); \
1657 slot_rmap_walk_next(_iter_))
1659 static int kvm_handle_hva_range(struct kvm
*kvm
,
1660 unsigned long start
,
1663 int (*handler
)(struct kvm
*kvm
,
1664 struct kvm_rmap_head
*rmap_head
,
1665 struct kvm_memory_slot
*slot
,
1668 unsigned long data
))
1670 struct kvm_memslots
*slots
;
1671 struct kvm_memory_slot
*memslot
;
1672 struct slot_rmap_walk_iterator iterator
;
1676 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1677 slots
= __kvm_memslots(kvm
, i
);
1678 kvm_for_each_memslot(memslot
, slots
) {
1679 unsigned long hva_start
, hva_end
;
1680 gfn_t gfn_start
, gfn_end
;
1682 hva_start
= max(start
, memslot
->userspace_addr
);
1683 hva_end
= min(end
, memslot
->userspace_addr
+
1684 (memslot
->npages
<< PAGE_SHIFT
));
1685 if (hva_start
>= hva_end
)
1688 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1689 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1691 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1692 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1694 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1695 PT_MAX_HUGEPAGE_LEVEL
,
1696 gfn_start
, gfn_end
- 1,
1698 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1699 iterator
.gfn
, iterator
.level
, data
);
1706 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1708 int (*handler
)(struct kvm
*kvm
,
1709 struct kvm_rmap_head
*rmap_head
,
1710 struct kvm_memory_slot
*slot
,
1711 gfn_t gfn
, int level
,
1712 unsigned long data
))
1714 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1717 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1719 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1722 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1724 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1727 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1729 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1732 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1733 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1737 struct rmap_iterator
uninitialized_var(iter
);
1740 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1741 young
|= mmu_spte_age(sptep
);
1743 trace_kvm_age_page(gfn
, level
, slot
, young
);
1747 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1748 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1749 int level
, unsigned long data
)
1752 struct rmap_iterator iter
;
1755 * If there's no access bit in the secondary pte set by the hardware and
1756 * fast access tracking is also not enabled, it's up to gup-fast/gup to
1757 * set the access bit in the primary pte or in the page structure.
1759 if (!shadow_accessed_mask
&& !shadow_acc_track_mask
)
1762 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1763 if (is_accessed_spte(*sptep
))
1769 #define RMAP_RECYCLE_THRESHOLD 1000
1771 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1773 struct kvm_rmap_head
*rmap_head
;
1774 struct kvm_mmu_page
*sp
;
1776 sp
= page_header(__pa(spte
));
1778 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1780 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1781 kvm_flush_remote_tlbs(vcpu
->kvm
);
1784 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1787 * In case of absence of EPT Access and Dirty Bits supports,
1788 * emulate the accessed bit for EPT, by checking if this page has
1789 * an EPT mapping, and clearing it if it does. On the next access,
1790 * a new EPT mapping will be established.
1791 * This has some overhead, but not as much as the cost of swapping
1792 * out actively used pages or breaking up actively used hugepages.
1794 if (!shadow_accessed_mask
&& !shadow_acc_track_mask
)
1795 return kvm_handle_hva_range(kvm
, start
, end
, 0,
1798 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1801 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1803 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1807 static int is_empty_shadow_page(u64
*spt
)
1812 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1813 if (is_shadow_present_pte(*pos
)) {
1814 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1823 * This value is the sum of all of the kvm instances's
1824 * kvm->arch.n_used_mmu_pages values. We need a global,
1825 * aggregate version in order to make the slab shrinker
1828 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1830 kvm
->arch
.n_used_mmu_pages
+= nr
;
1831 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1834 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1836 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1837 hlist_del(&sp
->hash_link
);
1838 list_del(&sp
->link
);
1839 free_page((unsigned long)sp
->spt
);
1840 if (!sp
->role
.direct
)
1841 free_page((unsigned long)sp
->gfns
);
1842 kmem_cache_free(mmu_page_header_cache
, sp
);
1845 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1847 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1850 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1851 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1856 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1859 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1862 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1865 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1868 mmu_page_remove_parent_pte(sp
, parent_pte
);
1869 mmu_spte_clear_no_track(parent_pte
);
1872 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1874 struct kvm_mmu_page
*sp
;
1876 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1877 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1879 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1880 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1883 * The active_mmu_pages list is the FIFO list, do not move the
1884 * page until it is zapped. kvm_zap_obsolete_pages depends on
1885 * this feature. See the comments in kvm_zap_obsolete_pages().
1887 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1888 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1892 static void mark_unsync(u64
*spte
);
1893 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1896 struct rmap_iterator iter
;
1898 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1903 static void mark_unsync(u64
*spte
)
1905 struct kvm_mmu_page
*sp
;
1908 sp
= page_header(__pa(spte
));
1909 index
= spte
- sp
->spt
;
1910 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1912 if (sp
->unsync_children
++)
1914 kvm_mmu_mark_parents_unsync(sp
);
1917 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1918 struct kvm_mmu_page
*sp
)
1923 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1927 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1928 struct kvm_mmu_page
*sp
, u64
*spte
,
1934 #define KVM_PAGE_ARRAY_NR 16
1936 struct kvm_mmu_pages
{
1937 struct mmu_page_and_offset
{
1938 struct kvm_mmu_page
*sp
;
1940 } page
[KVM_PAGE_ARRAY_NR
];
1944 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1950 for (i
=0; i
< pvec
->nr
; i
++)
1951 if (pvec
->page
[i
].sp
== sp
)
1954 pvec
->page
[pvec
->nr
].sp
= sp
;
1955 pvec
->page
[pvec
->nr
].idx
= idx
;
1957 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1960 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1962 --sp
->unsync_children
;
1963 WARN_ON((int)sp
->unsync_children
< 0);
1964 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1967 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1968 struct kvm_mmu_pages
*pvec
)
1970 int i
, ret
, nr_unsync_leaf
= 0;
1972 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1973 struct kvm_mmu_page
*child
;
1974 u64 ent
= sp
->spt
[i
];
1976 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1977 clear_unsync_child_bit(sp
, i
);
1981 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1983 if (child
->unsync_children
) {
1984 if (mmu_pages_add(pvec
, child
, i
))
1987 ret
= __mmu_unsync_walk(child
, pvec
);
1989 clear_unsync_child_bit(sp
, i
);
1991 } else if (ret
> 0) {
1992 nr_unsync_leaf
+= ret
;
1995 } else if (child
->unsync
) {
1997 if (mmu_pages_add(pvec
, child
, i
))
2000 clear_unsync_child_bit(sp
, i
);
2003 return nr_unsync_leaf
;
2006 #define INVALID_INDEX (-1)
2008 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2009 struct kvm_mmu_pages
*pvec
)
2012 if (!sp
->unsync_children
)
2015 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2016 return __mmu_unsync_walk(sp
, pvec
);
2019 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2021 WARN_ON(!sp
->unsync
);
2022 trace_kvm_mmu_sync_page(sp
);
2024 --kvm
->stat
.mmu_unsync
;
2027 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2028 struct list_head
*invalid_list
);
2029 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2030 struct list_head
*invalid_list
);
2033 * NOTE: we should pay more attention on the zapped-obsolete page
2034 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2035 * since it has been deleted from active_mmu_pages but still can be found
2038 * for_each_valid_sp() has skipped that kind of pages.
2040 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2041 hlist_for_each_entry(_sp, \
2042 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2043 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2046 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2047 for_each_valid_sp(_kvm, _sp, _gfn) \
2048 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2050 /* @sp->gfn should be write-protected at the call site */
2051 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2052 struct list_head
*invalid_list
)
2054 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
2055 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2059 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
2060 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2067 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2068 struct list_head
*invalid_list
,
2069 bool remote_flush
, bool local_flush
)
2071 if (!list_empty(invalid_list
)) {
2072 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
2077 kvm_flush_remote_tlbs(vcpu
->kvm
);
2078 else if (local_flush
)
2079 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2082 #ifdef CONFIG_KVM_MMU_AUDIT
2083 #include "mmu_audit.c"
2085 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2086 static void mmu_audit_disable(void) { }
2089 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2091 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2094 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2095 struct list_head
*invalid_list
)
2097 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2098 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2101 /* @gfn should be write-protected at the call site */
2102 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2103 struct list_head
*invalid_list
)
2105 struct kvm_mmu_page
*s
;
2108 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2112 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2113 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2119 struct mmu_page_path
{
2120 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
];
2121 unsigned int idx
[PT64_ROOT_LEVEL
];
2124 #define for_each_sp(pvec, sp, parents, i) \
2125 for (i = mmu_pages_first(&pvec, &parents); \
2126 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2127 i = mmu_pages_next(&pvec, &parents, i))
2129 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2130 struct mmu_page_path
*parents
,
2135 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2136 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2137 unsigned idx
= pvec
->page
[n
].idx
;
2138 int level
= sp
->role
.level
;
2140 parents
->idx
[level
-1] = idx
;
2141 if (level
== PT_PAGE_TABLE_LEVEL
)
2144 parents
->parent
[level
-2] = sp
;
2150 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2151 struct mmu_page_path
*parents
)
2153 struct kvm_mmu_page
*sp
;
2159 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2161 sp
= pvec
->page
[0].sp
;
2162 level
= sp
->role
.level
;
2163 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2165 parents
->parent
[level
-2] = sp
;
2167 /* Also set up a sentinel. Further entries in pvec are all
2168 * children of sp, so this element is never overwritten.
2170 parents
->parent
[level
-1] = NULL
;
2171 return mmu_pages_next(pvec
, parents
, 0);
2174 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2176 struct kvm_mmu_page
*sp
;
2177 unsigned int level
= 0;
2180 unsigned int idx
= parents
->idx
[level
];
2181 sp
= parents
->parent
[level
];
2185 WARN_ON(idx
== INVALID_INDEX
);
2186 clear_unsync_child_bit(sp
, idx
);
2188 } while (!sp
->unsync_children
);
2191 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2192 struct kvm_mmu_page
*parent
)
2195 struct kvm_mmu_page
*sp
;
2196 struct mmu_page_path parents
;
2197 struct kvm_mmu_pages pages
;
2198 LIST_HEAD(invalid_list
);
2201 while (mmu_unsync_walk(parent
, &pages
)) {
2202 bool protected = false;
2204 for_each_sp(pages
, sp
, parents
, i
)
2205 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2208 kvm_flush_remote_tlbs(vcpu
->kvm
);
2212 for_each_sp(pages
, sp
, parents
, i
) {
2213 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2214 mmu_pages_clear_parents(&parents
);
2216 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2217 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2218 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2223 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2226 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2228 atomic_set(&sp
->write_flooding_count
, 0);
2231 static void clear_sp_write_flooding_count(u64
*spte
)
2233 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2235 __clear_sp_write_flooding_count(sp
);
2238 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2245 union kvm_mmu_page_role role
;
2247 struct kvm_mmu_page
*sp
;
2248 bool need_sync
= false;
2251 LIST_HEAD(invalid_list
);
2253 role
= vcpu
->arch
.mmu
.base_role
;
2255 role
.direct
= direct
;
2258 role
.access
= access
;
2259 if (!vcpu
->arch
.mmu
.direct_map
2260 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2261 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2262 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2263 role
.quadrant
= quadrant
;
2265 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2266 if (sp
->gfn
!= gfn
) {
2271 if (!need_sync
&& sp
->unsync
)
2274 if (sp
->role
.word
!= role
.word
)
2278 /* The page is good, but __kvm_sync_page might still end
2279 * up zapping it. If so, break in order to rebuild it.
2281 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2284 WARN_ON(!list_empty(&invalid_list
));
2285 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2288 if (sp
->unsync_children
)
2289 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2291 __clear_sp_write_flooding_count(sp
);
2292 trace_kvm_mmu_get_page(sp
, false);
2296 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2298 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2302 hlist_add_head(&sp
->hash_link
,
2303 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2306 * we should do write protection before syncing pages
2307 * otherwise the content of the synced shadow page may
2308 * be inconsistent with guest page table.
2310 account_shadowed(vcpu
->kvm
, sp
);
2311 if (level
== PT_PAGE_TABLE_LEVEL
&&
2312 rmap_write_protect(vcpu
, gfn
))
2313 kvm_flush_remote_tlbs(vcpu
->kvm
);
2315 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2316 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2318 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2319 clear_page(sp
->spt
);
2320 trace_kvm_mmu_get_page(sp
, true);
2322 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2324 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2325 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2329 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2330 struct kvm_vcpu
*vcpu
, u64 addr
)
2332 iterator
->addr
= addr
;
2333 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2334 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2336 if (iterator
->level
== PT64_ROOT_LEVEL
&&
2337 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
2338 !vcpu
->arch
.mmu
.direct_map
)
2341 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2342 iterator
->shadow_addr
2343 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2344 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2346 if (!iterator
->shadow_addr
)
2347 iterator
->level
= 0;
2351 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2353 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2356 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2357 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2361 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2364 if (is_last_spte(spte
, iterator
->level
)) {
2365 iterator
->level
= 0;
2369 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2373 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2375 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2378 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2379 struct kvm_mmu_page
*sp
)
2383 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2385 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2386 shadow_user_mask
| shadow_x_mask
| shadow_accessed_mask
;
2388 mmu_spte_set(sptep
, spte
);
2390 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2392 if (sp
->unsync_children
|| sp
->unsync
)
2396 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2397 unsigned direct_access
)
2399 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2400 struct kvm_mmu_page
*child
;
2403 * For the direct sp, if the guest pte's dirty bit
2404 * changed form clean to dirty, it will corrupt the
2405 * sp's access: allow writable in the read-only sp,
2406 * so we should update the spte at this point to get
2407 * a new sp with the correct access.
2409 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2410 if (child
->role
.access
== direct_access
)
2413 drop_parent_pte(child
, sptep
);
2414 kvm_flush_remote_tlbs(vcpu
->kvm
);
2418 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2422 struct kvm_mmu_page
*child
;
2425 if (is_shadow_present_pte(pte
)) {
2426 if (is_last_spte(pte
, sp
->role
.level
)) {
2427 drop_spte(kvm
, spte
);
2428 if (is_large_pte(pte
))
2431 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2432 drop_parent_pte(child
, spte
);
2437 if (is_mmio_spte(pte
))
2438 mmu_spte_clear_no_track(spte
);
2443 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2444 struct kvm_mmu_page
*sp
)
2448 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2449 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2452 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2455 struct rmap_iterator iter
;
2457 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2458 drop_parent_pte(sp
, sptep
);
2461 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2462 struct kvm_mmu_page
*parent
,
2463 struct list_head
*invalid_list
)
2466 struct mmu_page_path parents
;
2467 struct kvm_mmu_pages pages
;
2469 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2472 while (mmu_unsync_walk(parent
, &pages
)) {
2473 struct kvm_mmu_page
*sp
;
2475 for_each_sp(pages
, sp
, parents
, i
) {
2476 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2477 mmu_pages_clear_parents(&parents
);
2485 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2486 struct list_head
*invalid_list
)
2490 trace_kvm_mmu_prepare_zap_page(sp
);
2491 ++kvm
->stat
.mmu_shadow_zapped
;
2492 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2493 kvm_mmu_page_unlink_children(kvm
, sp
);
2494 kvm_mmu_unlink_parents(kvm
, sp
);
2496 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2497 unaccount_shadowed(kvm
, sp
);
2500 kvm_unlink_unsync_page(kvm
, sp
);
2501 if (!sp
->root_count
) {
2504 list_move(&sp
->link
, invalid_list
);
2505 kvm_mod_used_mmu_pages(kvm
, -1);
2507 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2510 * The obsolete pages can not be used on any vcpus.
2511 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2513 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2514 kvm_reload_remote_mmus(kvm
);
2517 sp
->role
.invalid
= 1;
2521 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2522 struct list_head
*invalid_list
)
2524 struct kvm_mmu_page
*sp
, *nsp
;
2526 if (list_empty(invalid_list
))
2530 * We need to make sure everyone sees our modifications to
2531 * the page tables and see changes to vcpu->mode here. The barrier
2532 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2533 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2535 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2536 * guest mode and/or lockless shadow page table walks.
2538 kvm_flush_remote_tlbs(kvm
);
2540 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2541 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2542 kvm_mmu_free_page(sp
);
2546 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2547 struct list_head
*invalid_list
)
2549 struct kvm_mmu_page
*sp
;
2551 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2554 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2555 struct kvm_mmu_page
, link
);
2556 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2562 * Changing the number of mmu pages allocated to the vm
2563 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2565 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2567 LIST_HEAD(invalid_list
);
2569 spin_lock(&kvm
->mmu_lock
);
2571 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2572 /* Need to free some mmu pages to achieve the goal. */
2573 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2574 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2577 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2578 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2581 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2583 spin_unlock(&kvm
->mmu_lock
);
2586 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2588 struct kvm_mmu_page
*sp
;
2589 LIST_HEAD(invalid_list
);
2592 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2594 spin_lock(&kvm
->mmu_lock
);
2595 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2596 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2599 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2601 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2602 spin_unlock(&kvm
->mmu_lock
);
2606 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2608 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2610 trace_kvm_mmu_unsync_page(sp
);
2611 ++vcpu
->kvm
->stat
.mmu_unsync
;
2614 kvm_mmu_mark_parents_unsync(sp
);
2617 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2620 struct kvm_mmu_page
*sp
;
2622 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2625 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2632 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2633 kvm_unsync_page(vcpu
, sp
);
2639 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2642 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2647 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2648 unsigned pte_access
, int level
,
2649 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2650 bool can_unsync
, bool host_writable
)
2655 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2659 * For the EPT case, shadow_present_mask is 0 if hardware
2660 * supports exec-only page table entries. In that case,
2661 * ACC_USER_MASK and shadow_user_mask are used to represent
2662 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2664 spte
|= shadow_present_mask
;
2666 spte
|= shadow_accessed_mask
;
2668 if (pte_access
& ACC_EXEC_MASK
)
2669 spte
|= shadow_x_mask
;
2671 spte
|= shadow_nx_mask
;
2673 if (pte_access
& ACC_USER_MASK
)
2674 spte
|= shadow_user_mask
;
2676 if (level
> PT_PAGE_TABLE_LEVEL
)
2677 spte
|= PT_PAGE_SIZE_MASK
;
2679 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2680 kvm_is_mmio_pfn(pfn
));
2683 spte
|= SPTE_HOST_WRITEABLE
;
2685 pte_access
&= ~ACC_WRITE_MASK
;
2687 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2689 if (pte_access
& ACC_WRITE_MASK
) {
2692 * Other vcpu creates new sp in the window between
2693 * mapping_level() and acquiring mmu-lock. We can
2694 * allow guest to retry the access, the mapping can
2695 * be fixed if guest refault.
2697 if (level
> PT_PAGE_TABLE_LEVEL
&&
2698 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2701 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2704 * Optimization: for pte sync, if spte was writable the hash
2705 * lookup is unnecessary (and expensive). Write protection
2706 * is responsibility of mmu_get_page / kvm_sync_page.
2707 * Same reasoning can be applied to dirty page accounting.
2709 if (!can_unsync
&& is_writable_pte(*sptep
))
2712 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2713 pgprintk("%s: found shadow page for %llx, marking ro\n",
2716 pte_access
&= ~ACC_WRITE_MASK
;
2717 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2721 if (pte_access
& ACC_WRITE_MASK
) {
2722 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2723 spte
|= shadow_dirty_mask
;
2727 spte
= mark_spte_for_access_track(spte
);
2730 if (mmu_spte_update(sptep
, spte
))
2731 kvm_flush_remote_tlbs(vcpu
->kvm
);
2736 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2737 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2738 bool speculative
, bool host_writable
)
2740 int was_rmapped
= 0;
2742 bool emulate
= false;
2744 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2745 *sptep
, write_fault
, gfn
);
2747 if (is_shadow_present_pte(*sptep
)) {
2749 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2750 * the parent of the now unreachable PTE.
2752 if (level
> PT_PAGE_TABLE_LEVEL
&&
2753 !is_large_pte(*sptep
)) {
2754 struct kvm_mmu_page
*child
;
2757 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2758 drop_parent_pte(child
, sptep
);
2759 kvm_flush_remote_tlbs(vcpu
->kvm
);
2760 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2761 pgprintk("hfn old %llx new %llx\n",
2762 spte_to_pfn(*sptep
), pfn
);
2763 drop_spte(vcpu
->kvm
, sptep
);
2764 kvm_flush_remote_tlbs(vcpu
->kvm
);
2769 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2770 true, host_writable
)) {
2773 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2776 if (unlikely(is_mmio_spte(*sptep
)))
2779 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2780 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2781 is_large_pte(*sptep
)? "2MB" : "4kB",
2782 *sptep
& PT_WRITABLE_MASK
? "RW" : "R", gfn
,
2784 if (!was_rmapped
&& is_large_pte(*sptep
))
2785 ++vcpu
->kvm
->stat
.lpages
;
2787 if (is_shadow_present_pte(*sptep
)) {
2789 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2790 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2791 rmap_recycle(vcpu
, sptep
, gfn
);
2795 kvm_release_pfn_clean(pfn
);
2800 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2803 struct kvm_memory_slot
*slot
;
2805 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2807 return KVM_PFN_ERR_FAULT
;
2809 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2812 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2813 struct kvm_mmu_page
*sp
,
2814 u64
*start
, u64
*end
)
2816 struct page
*pages
[PTE_PREFETCH_NUM
];
2817 struct kvm_memory_slot
*slot
;
2818 unsigned access
= sp
->role
.access
;
2822 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2823 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2827 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2831 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2832 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2833 page_to_pfn(pages
[i
]), true, true);
2838 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2839 struct kvm_mmu_page
*sp
, u64
*sptep
)
2841 u64
*spte
, *start
= NULL
;
2844 WARN_ON(!sp
->role
.direct
);
2846 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2849 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2850 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2853 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2861 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2863 struct kvm_mmu_page
*sp
;
2866 * Since it's no accessed bit on EPT, it's no way to
2867 * distinguish between actually accessed translations
2868 * and prefetched, so disable pte prefetch if EPT is
2871 if (!shadow_accessed_mask
)
2874 sp
= page_header(__pa(sptep
));
2875 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2878 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2881 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2882 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2884 struct kvm_shadow_walk_iterator iterator
;
2885 struct kvm_mmu_page
*sp
;
2889 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2892 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2893 if (iterator
.level
== level
) {
2894 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2895 write
, level
, gfn
, pfn
, prefault
,
2897 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2898 ++vcpu
->stat
.pf_fixed
;
2902 drop_large_spte(vcpu
, iterator
.sptep
);
2903 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2904 u64 base_addr
= iterator
.addr
;
2906 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2907 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2908 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2909 iterator
.level
- 1, 1, ACC_ALL
);
2911 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2917 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2921 info
.si_signo
= SIGBUS
;
2923 info
.si_code
= BUS_MCEERR_AR
;
2924 info
.si_addr
= (void __user
*)address
;
2925 info
.si_addr_lsb
= PAGE_SHIFT
;
2927 send_sig_info(SIGBUS
, &info
, tsk
);
2930 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2933 * Do not cache the mmio info caused by writing the readonly gfn
2934 * into the spte otherwise read access on readonly gfn also can
2935 * caused mmio page fault and treat it as mmio access.
2936 * Return 1 to tell kvm to emulate it.
2938 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2941 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2942 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
2949 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2950 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
2953 kvm_pfn_t pfn
= *pfnp
;
2955 int level
= *levelp
;
2958 * Check if it's a transparent hugepage. If this would be an
2959 * hugetlbfs page, level wouldn't be set to
2960 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2963 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
2964 level
== PT_PAGE_TABLE_LEVEL
&&
2965 PageTransCompoundMap(pfn_to_page(pfn
)) &&
2966 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
2969 * mmu_notifier_retry was successful and we hold the
2970 * mmu_lock here, so the pmd can't become splitting
2971 * from under us, and in turn
2972 * __split_huge_page_refcount() can't run from under
2973 * us and we can safely transfer the refcount from
2974 * PG_tail to PG_head as we switch the pfn to tail to
2977 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2978 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2979 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2983 kvm_release_pfn_clean(pfn
);
2991 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2992 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
2994 /* The pfn is invalid, report the error! */
2995 if (unlikely(is_error_pfn(pfn
))) {
2996 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3000 if (unlikely(is_noslot_pfn(pfn
)))
3001 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
3006 static bool page_fault_can_be_fast(u32 error_code
)
3009 * Do not fix the mmio spte with invalid generation number which
3010 * need to be updated by slow page fault path.
3012 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3015 /* See if the page fault is due to an NX violation */
3016 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3017 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3021 * #PF can be fast if:
3022 * 1. The shadow page table entry is not present, which could mean that
3023 * the fault is potentially caused by access tracking (if enabled).
3024 * 2. The shadow page table entry is present and the fault
3025 * is caused by write-protect, that means we just need change the W
3026 * bit of the spte which can be done out of mmu-lock.
3028 * However, if access tracking is disabled we know that a non-present
3029 * page must be a genuine page fault where we have to create a new SPTE.
3030 * So, if access tracking is disabled, we return true only for write
3031 * accesses to a present page.
3034 return shadow_acc_track_mask
!= 0 ||
3035 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3036 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3040 * Returns true if the SPTE was fixed successfully. Otherwise,
3041 * someone else modified the SPTE from its original value.
3044 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3045 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3049 WARN_ON(!sp
->role
.direct
);
3052 * Theoretically we could also set dirty bit (and flush TLB) here in
3053 * order to eliminate unnecessary PML logging. See comments in
3054 * set_spte. But fast_page_fault is very unlikely to happen with PML
3055 * enabled, so we do not do this. This might result in the same GPA
3056 * to be logged in PML buffer again when the write really happens, and
3057 * eventually to be called by mark_page_dirty twice. But it's also no
3058 * harm. This also avoids the TLB flush needed after setting dirty bit
3059 * so non-PML cases won't be impacted.
3061 * Compare with set_spte where instead shadow_dirty_mask is set.
3063 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3066 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3068 * The gfn of direct spte is stable since it is
3069 * calculated by sp->gfn.
3071 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3072 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3078 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3080 if (fault_err_code
& PFERR_FETCH_MASK
)
3081 return is_executable_pte(spte
);
3083 if (fault_err_code
& PFERR_WRITE_MASK
)
3084 return is_writable_pte(spte
);
3086 /* Fault was on Read access */
3087 return spte
& PT_PRESENT_MASK
;
3092 * - true: let the vcpu to access on the same address again.
3093 * - false: let the real page fault path to fix it.
3095 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
3098 struct kvm_shadow_walk_iterator iterator
;
3099 struct kvm_mmu_page
*sp
;
3100 bool fault_handled
= false;
3102 uint retry_count
= 0;
3104 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3107 if (!page_fault_can_be_fast(error_code
))
3110 walk_shadow_page_lockless_begin(vcpu
);
3115 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
3116 if (!is_shadow_present_pte(spte
) ||
3117 iterator
.level
< level
)
3120 sp
= page_header(__pa(iterator
.sptep
));
3121 if (!is_last_spte(spte
, sp
->role
.level
))
3125 * Check whether the memory access that caused the fault would
3126 * still cause it if it were to be performed right now. If not,
3127 * then this is a spurious fault caused by TLB lazily flushed,
3128 * or some other CPU has already fixed the PTE after the
3129 * current CPU took the fault.
3131 * Need not check the access of upper level table entries since
3132 * they are always ACC_ALL.
3134 if (is_access_allowed(error_code
, spte
)) {
3135 fault_handled
= true;
3141 if (is_access_track_spte(spte
))
3142 new_spte
= restore_acc_track_spte(new_spte
);
3145 * Currently, to simplify the code, write-protection can
3146 * be removed in the fast path only if the SPTE was
3147 * write-protected for dirty-logging or access tracking.
3149 if ((error_code
& PFERR_WRITE_MASK
) &&
3150 spte_can_locklessly_be_made_writable(spte
))
3152 new_spte
|= PT_WRITABLE_MASK
;
3155 * Do not fix write-permission on the large spte. Since
3156 * we only dirty the first page into the dirty-bitmap in
3157 * fast_pf_fix_direct_spte(), other pages are missed
3158 * if its slot has dirty logging enabled.
3160 * Instead, we let the slow page fault path create a
3161 * normal spte to fix the access.
3163 * See the comments in kvm_arch_commit_memory_region().
3165 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3169 /* Verify that the fault can be handled in the fast path */
3170 if (new_spte
== spte
||
3171 !is_access_allowed(error_code
, new_spte
))
3175 * Currently, fast page fault only works for direct mapping
3176 * since the gfn is not stable for indirect shadow page. See
3177 * Documentation/virtual/kvm/locking.txt to get more detail.
3179 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3180 iterator
.sptep
, spte
,
3185 if (++retry_count
> 4) {
3186 printk_once(KERN_WARNING
3187 "kvm: Fast #PF retrying more than 4 times.\n");
3193 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3194 spte
, fault_handled
);
3195 walk_shadow_page_lockless_end(vcpu
);
3197 return fault_handled
;
3200 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3201 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3202 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3204 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3205 gfn_t gfn
, bool prefault
)
3209 bool force_pt_level
= false;
3211 unsigned long mmu_seq
;
3212 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3214 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3215 if (likely(!force_pt_level
)) {
3217 * This path builds a PAE pagetable - so we can map
3218 * 2mb pages at maximum. Therefore check if the level
3219 * is larger than that.
3221 if (level
> PT_DIRECTORY_LEVEL
)
3222 level
= PT_DIRECTORY_LEVEL
;
3224 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3227 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3230 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3233 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3236 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3239 spin_lock(&vcpu
->kvm
->mmu_lock
);
3240 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3242 make_mmu_pages_available(vcpu
);
3243 if (likely(!force_pt_level
))
3244 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3245 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3246 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3251 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3252 kvm_release_pfn_clean(pfn
);
3257 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3260 struct kvm_mmu_page
*sp
;
3261 LIST_HEAD(invalid_list
);
3263 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3266 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
3267 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
3268 vcpu
->arch
.mmu
.direct_map
)) {
3269 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3271 spin_lock(&vcpu
->kvm
->mmu_lock
);
3272 sp
= page_header(root
);
3274 if (!sp
->root_count
&& sp
->role
.invalid
) {
3275 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3276 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3278 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3279 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3283 spin_lock(&vcpu
->kvm
->mmu_lock
);
3284 for (i
= 0; i
< 4; ++i
) {
3285 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3288 root
&= PT64_BASE_ADDR_MASK
;
3289 sp
= page_header(root
);
3291 if (!sp
->root_count
&& sp
->role
.invalid
)
3292 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3295 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3297 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3298 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3299 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3302 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3306 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3307 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3314 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3316 struct kvm_mmu_page
*sp
;
3319 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3320 spin_lock(&vcpu
->kvm
->mmu_lock
);
3321 make_mmu_pages_available(vcpu
);
3322 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
, 1, ACC_ALL
);
3324 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3325 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3326 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3327 for (i
= 0; i
< 4; ++i
) {
3328 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3330 MMU_WARN_ON(VALID_PAGE(root
));
3331 spin_lock(&vcpu
->kvm
->mmu_lock
);
3332 make_mmu_pages_available(vcpu
);
3333 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3334 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3335 root
= __pa(sp
->spt
);
3337 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3338 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3340 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3347 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3349 struct kvm_mmu_page
*sp
;
3354 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3356 if (mmu_check_root(vcpu
, root_gfn
))
3360 * Do we shadow a long mode page table? If so we need to
3361 * write-protect the guests page table root.
3363 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3364 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3366 MMU_WARN_ON(VALID_PAGE(root
));
3368 spin_lock(&vcpu
->kvm
->mmu_lock
);
3369 make_mmu_pages_available(vcpu
);
3370 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3372 root
= __pa(sp
->spt
);
3374 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3375 vcpu
->arch
.mmu
.root_hpa
= root
;
3380 * We shadow a 32 bit page table. This may be a legacy 2-level
3381 * or a PAE 3-level page table. In either case we need to be aware that
3382 * the shadow page table may be a PAE or a long mode page table.
3384 pm_mask
= PT_PRESENT_MASK
;
3385 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3386 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3388 for (i
= 0; i
< 4; ++i
) {
3389 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3391 MMU_WARN_ON(VALID_PAGE(root
));
3392 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3393 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3394 if (!(pdptr
& PT_PRESENT_MASK
)) {
3395 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3398 root_gfn
= pdptr
>> PAGE_SHIFT
;
3399 if (mmu_check_root(vcpu
, root_gfn
))
3402 spin_lock(&vcpu
->kvm
->mmu_lock
);
3403 make_mmu_pages_available(vcpu
);
3404 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3406 root
= __pa(sp
->spt
);
3408 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3410 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3412 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3415 * If we shadow a 32 bit page table with a long mode page
3416 * table we enter this path.
3418 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3419 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3421 * The additional page necessary for this is only
3422 * allocated on demand.
3427 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3428 if (lm_root
== NULL
)
3431 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3433 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3436 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3442 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3444 if (vcpu
->arch
.mmu
.direct_map
)
3445 return mmu_alloc_direct_roots(vcpu
);
3447 return mmu_alloc_shadow_roots(vcpu
);
3450 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3453 struct kvm_mmu_page
*sp
;
3455 if (vcpu
->arch
.mmu
.direct_map
)
3458 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3461 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3462 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3463 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3464 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3465 sp
= page_header(root
);
3466 mmu_sync_children(vcpu
, sp
);
3467 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3470 for (i
= 0; i
< 4; ++i
) {
3471 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3473 if (root
&& VALID_PAGE(root
)) {
3474 root
&= PT64_BASE_ADDR_MASK
;
3475 sp
= page_header(root
);
3476 mmu_sync_children(vcpu
, sp
);
3479 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3482 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3484 spin_lock(&vcpu
->kvm
->mmu_lock
);
3485 mmu_sync_roots(vcpu
);
3486 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3488 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3490 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3491 u32 access
, struct x86_exception
*exception
)
3494 exception
->error_code
= 0;
3498 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3500 struct x86_exception
*exception
)
3503 exception
->error_code
= 0;
3504 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3508 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3510 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3512 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3513 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3516 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3518 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3521 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3523 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3526 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3529 return vcpu_match_mmio_gpa(vcpu
, addr
);
3531 return vcpu_match_mmio_gva(vcpu
, addr
);
3534 /* return true if reserved bit is detected on spte. */
3536 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3538 struct kvm_shadow_walk_iterator iterator
;
3539 u64 sptes
[PT64_ROOT_LEVEL
], spte
= 0ull;
3541 bool reserved
= false;
3543 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3546 walk_shadow_page_lockless_begin(vcpu
);
3548 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3549 leaf
= root
= iterator
.level
;
3550 shadow_walk_okay(&iterator
);
3551 __shadow_walk_next(&iterator
, spte
)) {
3552 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3554 sptes
[leaf
- 1] = spte
;
3557 if (!is_shadow_present_pte(spte
))
3560 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3564 walk_shadow_page_lockless_end(vcpu
);
3567 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3569 while (root
> leaf
) {
3570 pr_err("------ spte 0x%llx level %d.\n",
3571 sptes
[root
- 1], root
);
3580 int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3585 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3586 return RET_MMIO_PF_EMULATE
;
3588 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3589 if (WARN_ON(reserved
))
3590 return RET_MMIO_PF_BUG
;
3592 if (is_mmio_spte(spte
)) {
3593 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3594 unsigned access
= get_mmio_spte_access(spte
);
3596 if (!check_mmio_spte(vcpu
, spte
))
3597 return RET_MMIO_PF_INVALID
;
3602 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3603 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3604 return RET_MMIO_PF_EMULATE
;
3608 * If the page table is zapped by other cpus, let CPU fault again on
3611 return RET_MMIO_PF_RETRY
;
3613 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3615 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3616 u32 error_code
, gfn_t gfn
)
3618 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3621 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3622 !(error_code
& PFERR_WRITE_MASK
))
3626 * guest is writing the page which is write tracked which can
3627 * not be fixed by page fault handler.
3629 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3635 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3637 struct kvm_shadow_walk_iterator iterator
;
3640 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3643 walk_shadow_page_lockless_begin(vcpu
);
3644 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3645 clear_sp_write_flooding_count(iterator
.sptep
);
3646 if (!is_shadow_present_pte(spte
))
3649 walk_shadow_page_lockless_end(vcpu
);
3652 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3653 u32 error_code
, bool prefault
)
3655 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3658 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3660 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3663 r
= mmu_topup_memory_caches(vcpu
);
3667 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3670 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3671 error_code
, gfn
, prefault
);
3674 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3676 struct kvm_arch_async_pf arch
;
3678 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3680 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3681 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3683 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3686 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3688 if (unlikely(!lapic_in_kernel(vcpu
) ||
3689 kvm_event_needs_reinjection(vcpu
)))
3692 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3695 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3696 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3698 struct kvm_memory_slot
*slot
;
3701 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3703 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3705 return false; /* *pfn has correct page already */
3707 if (!prefault
&& can_do_async_pf(vcpu
)) {
3708 trace_kvm_try_async_get_page(gva
, gfn
);
3709 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3710 trace_kvm_async_pf_doublefault(gva
, gfn
);
3711 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3713 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3717 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3722 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3724 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3726 gfn
&= ~(page_num
- 1);
3728 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3731 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3737 bool force_pt_level
;
3738 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3739 unsigned long mmu_seq
;
3740 int write
= error_code
& PFERR_WRITE_MASK
;
3743 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3745 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3748 r
= mmu_topup_memory_caches(vcpu
);
3752 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3753 PT_DIRECTORY_LEVEL
);
3754 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3755 if (likely(!force_pt_level
)) {
3756 if (level
> PT_DIRECTORY_LEVEL
&&
3757 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3758 level
= PT_DIRECTORY_LEVEL
;
3759 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3762 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3765 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3768 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3771 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3774 spin_lock(&vcpu
->kvm
->mmu_lock
);
3775 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3777 make_mmu_pages_available(vcpu
);
3778 if (likely(!force_pt_level
))
3779 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3780 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3781 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3786 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3787 kvm_release_pfn_clean(pfn
);
3791 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3792 struct kvm_mmu
*context
)
3794 context
->page_fault
= nonpaging_page_fault
;
3795 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3796 context
->sync_page
= nonpaging_sync_page
;
3797 context
->invlpg
= nonpaging_invlpg
;
3798 context
->update_pte
= nonpaging_update_pte
;
3799 context
->root_level
= 0;
3800 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3801 context
->root_hpa
= INVALID_PAGE
;
3802 context
->direct_map
= true;
3803 context
->nx
= false;
3806 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3808 mmu_free_roots(vcpu
);
3811 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3813 return kvm_read_cr3(vcpu
);
3816 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3817 struct x86_exception
*fault
)
3819 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3822 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3823 unsigned access
, int *nr_present
)
3825 if (unlikely(is_mmio_spte(*sptep
))) {
3826 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3827 mmu_spte_clear_no_track(sptep
);
3832 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3839 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3840 unsigned level
, unsigned gpte
)
3843 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3844 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3845 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3847 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3850 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3851 * If it is clear, there are no large pages at this level, so clear
3852 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3854 gpte
&= level
- mmu
->last_nonleaf_level
;
3856 return gpte
& PT_PAGE_SIZE_MASK
;
3859 #define PTTYPE_EPT 18 /* arbitrary */
3860 #define PTTYPE PTTYPE_EPT
3861 #include "paging_tmpl.h"
3865 #include "paging_tmpl.h"
3869 #include "paging_tmpl.h"
3873 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3874 struct rsvd_bits_validate
*rsvd_check
,
3875 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
3878 u64 exb_bit_rsvd
= 0;
3879 u64 gbpages_bit_rsvd
= 0;
3880 u64 nonleaf_bit8_rsvd
= 0;
3882 rsvd_check
->bad_mt_xwr
= 0;
3885 exb_bit_rsvd
= rsvd_bits(63, 63);
3887 gbpages_bit_rsvd
= rsvd_bits(7, 7);
3890 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3891 * leaf entries) on AMD CPUs only.
3894 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
3897 case PT32_ROOT_LEVEL
:
3898 /* no rsvd bits for 2 level 4K page table entries */
3899 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
3900 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
3901 rsvd_check
->rsvd_bits_mask
[1][0] =
3902 rsvd_check
->rsvd_bits_mask
[0][0];
3905 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
3909 if (is_cpuid_PSE36())
3910 /* 36bits PSE 4MB page */
3911 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3913 /* 32 bits PSE 4MB page */
3914 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3916 case PT32E_ROOT_LEVEL
:
3917 rsvd_check
->rsvd_bits_mask
[0][2] =
3918 rsvd_bits(maxphyaddr
, 63) |
3919 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3920 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3921 rsvd_bits(maxphyaddr
, 62); /* PDE */
3922 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3923 rsvd_bits(maxphyaddr
, 62); /* PTE */
3924 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3925 rsvd_bits(maxphyaddr
, 62) |
3926 rsvd_bits(13, 20); /* large page */
3927 rsvd_check
->rsvd_bits_mask
[1][0] =
3928 rsvd_check
->rsvd_bits_mask
[0][0];
3930 case PT64_ROOT_LEVEL
:
3931 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3932 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3933 rsvd_bits(maxphyaddr
, 51);
3934 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3935 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
3936 rsvd_bits(maxphyaddr
, 51);
3937 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3938 rsvd_bits(maxphyaddr
, 51);
3939 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3940 rsvd_bits(maxphyaddr
, 51);
3941 rsvd_check
->rsvd_bits_mask
[1][3] =
3942 rsvd_check
->rsvd_bits_mask
[0][3];
3943 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3944 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
3946 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3947 rsvd_bits(maxphyaddr
, 51) |
3948 rsvd_bits(13, 20); /* large page */
3949 rsvd_check
->rsvd_bits_mask
[1][0] =
3950 rsvd_check
->rsvd_bits_mask
[0][0];
3955 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3956 struct kvm_mmu
*context
)
3958 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
3959 cpuid_maxphyaddr(vcpu
), context
->root_level
,
3960 context
->nx
, guest_cpuid_has_gbpages(vcpu
),
3961 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
3965 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
3966 int maxphyaddr
, bool execonly
)
3970 rsvd_check
->rsvd_bits_mask
[0][3] =
3971 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
3972 rsvd_check
->rsvd_bits_mask
[0][2] =
3973 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3974 rsvd_check
->rsvd_bits_mask
[0][1] =
3975 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3976 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
3979 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
3980 rsvd_check
->rsvd_bits_mask
[1][2] =
3981 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
3982 rsvd_check
->rsvd_bits_mask
[1][1] =
3983 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
3984 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
3986 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
3987 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
3988 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
3989 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3990 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3992 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3993 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
3995 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
3998 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
3999 struct kvm_mmu
*context
, bool execonly
)
4001 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4002 cpuid_maxphyaddr(vcpu
), execonly
);
4006 * the page table on host is the shadow page table for the page
4007 * table in guest or amd nested guest, its mmu features completely
4008 * follow the features in guest.
4011 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4013 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
4016 * Passing "true" to the last argument is okay; it adds a check
4017 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4019 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4020 boot_cpu_data
.x86_phys_bits
,
4021 context
->shadow_root_level
, uses_nx
,
4022 guest_cpuid_has_gbpages(vcpu
), is_pse(vcpu
),
4025 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4027 static inline bool boot_cpu_is_amd(void)
4029 WARN_ON_ONCE(!tdp_enabled
);
4030 return shadow_x_mask
== 0;
4034 * the direct page table on host, use as much mmu features as
4035 * possible, however, kvm currently does not do execution-protection.
4038 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4039 struct kvm_mmu
*context
)
4041 if (boot_cpu_is_amd())
4042 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4043 boot_cpu_data
.x86_phys_bits
,
4044 context
->shadow_root_level
, false,
4045 boot_cpu_has(X86_FEATURE_GBPAGES
),
4048 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4049 boot_cpu_data
.x86_phys_bits
,
4055 * as the comments in reset_shadow_zero_bits_mask() except it
4056 * is the shadow page table for intel nested guest.
4059 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4060 struct kvm_mmu
*context
, bool execonly
)
4062 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4063 boot_cpu_data
.x86_phys_bits
, execonly
);
4066 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4067 struct kvm_mmu
*mmu
, bool ept
)
4069 unsigned bit
, byte
, pfec
;
4071 bool fault
, x
, w
, u
, wf
, uf
, ff
, smapf
, cr4_smap
, cr4_smep
, smap
= 0;
4073 cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4074 cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4075 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4078 wf
= pfec
& PFERR_WRITE_MASK
;
4079 uf
= pfec
& PFERR_USER_MASK
;
4080 ff
= pfec
& PFERR_FETCH_MASK
;
4082 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
4083 * subject to SMAP restrictions, and cleared otherwise. The
4084 * bit is only meaningful if the SMAP bit is set in CR4.
4086 smapf
= !(pfec
& PFERR_RSVD_MASK
);
4087 for (bit
= 0; bit
< 8; ++bit
) {
4088 x
= bit
& ACC_EXEC_MASK
;
4089 w
= bit
& ACC_WRITE_MASK
;
4090 u
= bit
& ACC_USER_MASK
;
4093 /* Not really needed: !nx will cause pte.nx to fault */
4095 /* Allow supervisor writes if !cr0.wp */
4096 w
|= !is_write_protection(vcpu
) && !uf
;
4097 /* Disallow supervisor fetches of user code if cr4.smep */
4098 x
&= !(cr4_smep
&& u
&& !uf
);
4101 * SMAP:kernel-mode data accesses from user-mode
4102 * mappings should fault. A fault is considered
4103 * as a SMAP violation if all of the following
4104 * conditions are ture:
4105 * - X86_CR4_SMAP is set in CR4
4106 * - A user page is accessed
4107 * - Page fault in kernel mode
4108 * - if CPL = 3 or X86_EFLAGS_AC is clear
4110 * Here, we cover the first three conditions.
4111 * The fourth is computed dynamically in
4112 * permission_fault() and is in smapf.
4114 * Also, SMAP does not affect instruction
4115 * fetches, add the !ff check here to make it
4118 smap
= cr4_smap
&& u
&& !uf
&& !ff
;
4121 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
) ||
4123 map
|= fault
<< bit
;
4125 mmu
->permissions
[byte
] = map
;
4130 * PKU is an additional mechanism by which the paging controls access to
4131 * user-mode addresses based on the value in the PKRU register. Protection
4132 * key violations are reported through a bit in the page fault error code.
4133 * Unlike other bits of the error code, the PK bit is not known at the
4134 * call site of e.g. gva_to_gpa; it must be computed directly in
4135 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4136 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4138 * In particular the following conditions come from the error code, the
4139 * page tables and the machine state:
4140 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4141 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4142 * - PK is always zero if U=0 in the page tables
4143 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4145 * The PKRU bitmask caches the result of these four conditions. The error
4146 * code (minus the P bit) and the page table's U bit form an index into the
4147 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4148 * with the two bits of the PKRU register corresponding to the protection key.
4149 * For the first three conditions above the bits will be 00, thus masking
4150 * away both AD and WD. For all reads or if the last condition holds, WD
4151 * only will be masked away.
4153 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4164 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4165 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4170 wp
= is_write_protection(vcpu
);
4172 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4173 unsigned pfec
, pkey_bits
;
4174 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4177 ff
= pfec
& PFERR_FETCH_MASK
;
4178 uf
= pfec
& PFERR_USER_MASK
;
4179 wf
= pfec
& PFERR_WRITE_MASK
;
4181 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4182 pte_user
= pfec
& PFERR_RSVD_MASK
;
4185 * Only need to check the access which is not an
4186 * instruction fetch and is to a user page.
4188 check_pkey
= (!ff
&& pte_user
);
4190 * write access is controlled by PKRU if it is a
4191 * user access or CR0.WP = 1.
4193 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4195 /* PKRU.AD stops both read and write access. */
4196 pkey_bits
= !!check_pkey
;
4197 /* PKRU.WD stops write access. */
4198 pkey_bits
|= (!!check_write
) << 1;
4200 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4204 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4206 unsigned root_level
= mmu
->root_level
;
4208 mmu
->last_nonleaf_level
= root_level
;
4209 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4210 mmu
->last_nonleaf_level
++;
4213 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4214 struct kvm_mmu
*context
,
4217 context
->nx
= is_nx(vcpu
);
4218 context
->root_level
= level
;
4220 reset_rsvds_bits_mask(vcpu
, context
);
4221 update_permission_bitmask(vcpu
, context
, false);
4222 update_pkru_bitmask(vcpu
, context
, false);
4223 update_last_nonleaf_level(vcpu
, context
);
4225 MMU_WARN_ON(!is_pae(vcpu
));
4226 context
->page_fault
= paging64_page_fault
;
4227 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4228 context
->sync_page
= paging64_sync_page
;
4229 context
->invlpg
= paging64_invlpg
;
4230 context
->update_pte
= paging64_update_pte
;
4231 context
->shadow_root_level
= level
;
4232 context
->root_hpa
= INVALID_PAGE
;
4233 context
->direct_map
= false;
4236 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4237 struct kvm_mmu
*context
)
4239 paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
4242 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4243 struct kvm_mmu
*context
)
4245 context
->nx
= false;
4246 context
->root_level
= PT32_ROOT_LEVEL
;
4248 reset_rsvds_bits_mask(vcpu
, context
);
4249 update_permission_bitmask(vcpu
, context
, false);
4250 update_pkru_bitmask(vcpu
, context
, false);
4251 update_last_nonleaf_level(vcpu
, context
);
4253 context
->page_fault
= paging32_page_fault
;
4254 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4255 context
->sync_page
= paging32_sync_page
;
4256 context
->invlpg
= paging32_invlpg
;
4257 context
->update_pte
= paging32_update_pte
;
4258 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4259 context
->root_hpa
= INVALID_PAGE
;
4260 context
->direct_map
= false;
4263 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4264 struct kvm_mmu
*context
)
4266 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4269 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4271 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4273 context
->base_role
.word
= 0;
4274 context
->base_role
.smm
= is_smm(vcpu
);
4275 context
->page_fault
= tdp_page_fault
;
4276 context
->sync_page
= nonpaging_sync_page
;
4277 context
->invlpg
= nonpaging_invlpg
;
4278 context
->update_pte
= nonpaging_update_pte
;
4279 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4280 context
->root_hpa
= INVALID_PAGE
;
4281 context
->direct_map
= true;
4282 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4283 context
->get_cr3
= get_cr3
;
4284 context
->get_pdptr
= kvm_pdptr_read
;
4285 context
->inject_page_fault
= kvm_inject_page_fault
;
4287 if (!is_paging(vcpu
)) {
4288 context
->nx
= false;
4289 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4290 context
->root_level
= 0;
4291 } else if (is_long_mode(vcpu
)) {
4292 context
->nx
= is_nx(vcpu
);
4293 context
->root_level
= PT64_ROOT_LEVEL
;
4294 reset_rsvds_bits_mask(vcpu
, context
);
4295 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4296 } else if (is_pae(vcpu
)) {
4297 context
->nx
= is_nx(vcpu
);
4298 context
->root_level
= PT32E_ROOT_LEVEL
;
4299 reset_rsvds_bits_mask(vcpu
, context
);
4300 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4302 context
->nx
= false;
4303 context
->root_level
= PT32_ROOT_LEVEL
;
4304 reset_rsvds_bits_mask(vcpu
, context
);
4305 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4308 update_permission_bitmask(vcpu
, context
, false);
4309 update_pkru_bitmask(vcpu
, context
, false);
4310 update_last_nonleaf_level(vcpu
, context
);
4311 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4314 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4316 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4317 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4318 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4320 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4322 if (!is_paging(vcpu
))
4323 nonpaging_init_context(vcpu
, context
);
4324 else if (is_long_mode(vcpu
))
4325 paging64_init_context(vcpu
, context
);
4326 else if (is_pae(vcpu
))
4327 paging32E_init_context(vcpu
, context
);
4329 paging32_init_context(vcpu
, context
);
4331 context
->base_role
.nxe
= is_nx(vcpu
);
4332 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4333 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4334 context
->base_role
.smep_andnot_wp
4335 = smep
&& !is_write_protection(vcpu
);
4336 context
->base_role
.smap_andnot_wp
4337 = smap
&& !is_write_protection(vcpu
);
4338 context
->base_role
.smm
= is_smm(vcpu
);
4339 reset_shadow_zero_bits_mask(vcpu
, context
);
4341 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4343 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
)
4345 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4347 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4349 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4352 context
->page_fault
= ept_page_fault
;
4353 context
->gva_to_gpa
= ept_gva_to_gpa
;
4354 context
->sync_page
= ept_sync_page
;
4355 context
->invlpg
= ept_invlpg
;
4356 context
->update_pte
= ept_update_pte
;
4357 context
->root_level
= context
->shadow_root_level
;
4358 context
->root_hpa
= INVALID_PAGE
;
4359 context
->direct_map
= false;
4361 update_permission_bitmask(vcpu
, context
, true);
4362 update_pkru_bitmask(vcpu
, context
, true);
4363 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4364 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4366 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4368 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4370 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4372 kvm_init_shadow_mmu(vcpu
);
4373 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4374 context
->get_cr3
= get_cr3
;
4375 context
->get_pdptr
= kvm_pdptr_read
;
4376 context
->inject_page_fault
= kvm_inject_page_fault
;
4379 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4381 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4383 g_context
->get_cr3
= get_cr3
;
4384 g_context
->get_pdptr
= kvm_pdptr_read
;
4385 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4388 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4389 * L1's nested page tables (e.g. EPT12). The nested translation
4390 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4391 * L2's page tables as the first level of translation and L1's
4392 * nested page tables as the second level of translation. Basically
4393 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4395 if (!is_paging(vcpu
)) {
4396 g_context
->nx
= false;
4397 g_context
->root_level
= 0;
4398 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4399 } else if (is_long_mode(vcpu
)) {
4400 g_context
->nx
= is_nx(vcpu
);
4401 g_context
->root_level
= PT64_ROOT_LEVEL
;
4402 reset_rsvds_bits_mask(vcpu
, g_context
);
4403 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4404 } else if (is_pae(vcpu
)) {
4405 g_context
->nx
= is_nx(vcpu
);
4406 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4407 reset_rsvds_bits_mask(vcpu
, g_context
);
4408 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4410 g_context
->nx
= false;
4411 g_context
->root_level
= PT32_ROOT_LEVEL
;
4412 reset_rsvds_bits_mask(vcpu
, g_context
);
4413 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4416 update_permission_bitmask(vcpu
, g_context
, false);
4417 update_pkru_bitmask(vcpu
, g_context
, false);
4418 update_last_nonleaf_level(vcpu
, g_context
);
4421 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4423 if (mmu_is_nested(vcpu
))
4424 init_kvm_nested_mmu(vcpu
);
4425 else if (tdp_enabled
)
4426 init_kvm_tdp_mmu(vcpu
);
4428 init_kvm_softmmu(vcpu
);
4431 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4433 kvm_mmu_unload(vcpu
);
4436 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4438 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4442 r
= mmu_topup_memory_caches(vcpu
);
4445 r
= mmu_alloc_roots(vcpu
);
4446 kvm_mmu_sync_roots(vcpu
);
4449 /* set_cr3() should ensure TLB has been flushed */
4450 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4454 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4456 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4458 mmu_free_roots(vcpu
);
4459 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4461 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4463 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4464 struct kvm_mmu_page
*sp
, u64
*spte
,
4467 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4468 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4472 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4473 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4476 static bool need_remote_flush(u64 old
, u64
new)
4478 if (!is_shadow_present_pte(old
))
4480 if (!is_shadow_present_pte(new))
4482 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4484 old
^= shadow_nx_mask
;
4485 new ^= shadow_nx_mask
;
4486 return (old
& ~new & PT64_PERM_MASK
) != 0;
4489 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4490 const u8
*new, int *bytes
)
4496 * Assume that the pte write on a page table of the same type
4497 * as the current vcpu paging mode since we update the sptes only
4498 * when they have the same mode.
4500 if (is_pae(vcpu
) && *bytes
== 4) {
4501 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4504 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4507 new = (const u8
*)&gentry
;
4512 gentry
= *(const u32
*)new;
4515 gentry
= *(const u64
*)new;
4526 * If we're seeing too many writes to a page, it may no longer be a page table,
4527 * or we may be forking, in which case it is better to unmap the page.
4529 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4532 * Skip write-flooding detected for the sp whose level is 1, because
4533 * it can become unsync, then the guest page is not write-protected.
4535 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4538 atomic_inc(&sp
->write_flooding_count
);
4539 return atomic_read(&sp
->write_flooding_count
) >= 3;
4543 * Misaligned accesses are too much trouble to fix up; also, they usually
4544 * indicate a page is not used as a page table.
4546 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4549 unsigned offset
, pte_size
, misaligned
;
4551 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4552 gpa
, bytes
, sp
->role
.word
);
4554 offset
= offset_in_page(gpa
);
4555 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4558 * Sometimes, the OS only writes the last one bytes to update status
4559 * bits, for example, in linux, andb instruction is used in clear_bit().
4561 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4564 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4565 misaligned
|= bytes
< 4;
4570 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4572 unsigned page_offset
, quadrant
;
4576 page_offset
= offset_in_page(gpa
);
4577 level
= sp
->role
.level
;
4579 if (!sp
->role
.cr4_pae
) {
4580 page_offset
<<= 1; /* 32->64 */
4582 * A 32-bit pde maps 4MB while the shadow pdes map
4583 * only 2MB. So we need to double the offset again
4584 * and zap two pdes instead of one.
4586 if (level
== PT32_ROOT_LEVEL
) {
4587 page_offset
&= ~7; /* kill rounding error */
4591 quadrant
= page_offset
>> PAGE_SHIFT
;
4592 page_offset
&= ~PAGE_MASK
;
4593 if (quadrant
!= sp
->role
.quadrant
)
4597 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4601 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4602 const u8
*new, int bytes
,
4603 struct kvm_page_track_notifier_node
*node
)
4605 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4606 struct kvm_mmu_page
*sp
;
4607 LIST_HEAD(invalid_list
);
4608 u64 entry
, gentry
, *spte
;
4610 bool remote_flush
, local_flush
;
4611 union kvm_mmu_page_role mask
= { };
4616 mask
.smep_andnot_wp
= 1;
4617 mask
.smap_andnot_wp
= 1;
4621 * If we don't have indirect shadow pages, it means no page is
4622 * write-protected, so we can exit simply.
4624 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4627 remote_flush
= local_flush
= false;
4629 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4631 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4634 * No need to care whether allocation memory is successful
4635 * or not since pte prefetch is skiped if it does not have
4636 * enough objects in the cache.
4638 mmu_topup_memory_caches(vcpu
);
4640 spin_lock(&vcpu
->kvm
->mmu_lock
);
4641 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4642 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4644 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4645 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4646 detect_write_flooding(sp
)) {
4647 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4648 ++vcpu
->kvm
->stat
.mmu_flooded
;
4652 spte
= get_written_sptes(sp
, gpa
, &npte
);
4659 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4661 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4662 & mask
.word
) && rmap_can_add(vcpu
))
4663 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4664 if (need_remote_flush(entry
, *spte
))
4665 remote_flush
= true;
4669 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4670 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4671 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4674 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4679 if (vcpu
->arch
.mmu
.direct_map
)
4682 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4684 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4688 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4690 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4692 LIST_HEAD(invalid_list
);
4694 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4697 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4698 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4701 ++vcpu
->kvm
->stat
.mmu_recycled
;
4703 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4706 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u64 error_code
,
4707 void *insn
, int insn_len
)
4709 int r
, emulation_type
= EMULTYPE_RETRY
;
4710 enum emulation_result er
;
4711 bool direct
= vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
);
4713 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4714 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4715 if (r
== RET_MMIO_PF_EMULATE
) {
4719 if (r
== RET_MMIO_PF_RETRY
)
4725 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, lower_32_bits(error_code
),
4733 * Before emulating the instruction, check if the error code
4734 * was due to a RO violation while translating the guest page.
4735 * This can occur when using nested virtualization with nested
4736 * paging in both guests. If true, we simply unprotect the page
4737 * and resume the guest.
4739 * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4740 * in PFERR_NEXT_GUEST_PAGE)
4742 if (error_code
== PFERR_NESTED_GUEST_PAGE
) {
4743 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2
));
4747 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4750 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4755 case EMULATE_USER_EXIT
:
4756 ++vcpu
->stat
.mmio_exits
;
4764 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4766 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4768 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4769 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4770 ++vcpu
->stat
.invlpg
;
4772 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4774 void kvm_enable_tdp(void)
4778 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4780 void kvm_disable_tdp(void)
4782 tdp_enabled
= false;
4784 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4786 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4788 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4789 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4790 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4793 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4799 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4800 * Therefore we need to allocate shadow page tables in the first
4801 * 4GB of memory, which happens to fit the DMA32 zone.
4803 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4807 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4808 for (i
= 0; i
< 4; ++i
)
4809 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4814 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4816 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4817 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4818 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4819 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4821 return alloc_mmu_pages(vcpu
);
4824 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4826 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4831 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
4832 struct kvm_memory_slot
*slot
,
4833 struct kvm_page_track_notifier_node
*node
)
4835 kvm_mmu_invalidate_zap_all_pages(kvm
);
4838 void kvm_mmu_init_vm(struct kvm
*kvm
)
4840 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4842 node
->track_write
= kvm_mmu_pte_write
;
4843 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
4844 kvm_page_track_register_notifier(kvm
, node
);
4847 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
4849 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4851 kvm_page_track_unregister_notifier(kvm
, node
);
4854 /* The return value indicates if tlb flush on all vcpus is needed. */
4855 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
4857 /* The caller should hold mmu-lock before calling this function. */
4859 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4860 slot_level_handler fn
, int start_level
, int end_level
,
4861 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
4863 struct slot_rmap_walk_iterator iterator
;
4866 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
4867 end_gfn
, &iterator
) {
4869 flush
|= fn(kvm
, iterator
.rmap
);
4871 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
4872 if (flush
&& lock_flush_tlb
) {
4873 kvm_flush_remote_tlbs(kvm
);
4876 cond_resched_lock(&kvm
->mmu_lock
);
4880 if (flush
&& lock_flush_tlb
) {
4881 kvm_flush_remote_tlbs(kvm
);
4889 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4890 slot_level_handler fn
, int start_level
, int end_level
,
4891 bool lock_flush_tlb
)
4893 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
4894 end_level
, memslot
->base_gfn
,
4895 memslot
->base_gfn
+ memslot
->npages
- 1,
4900 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4901 slot_level_handler fn
, bool lock_flush_tlb
)
4903 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4904 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4908 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4909 slot_level_handler fn
, bool lock_flush_tlb
)
4911 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
4912 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4916 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4917 slot_level_handler fn
, bool lock_flush_tlb
)
4919 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4920 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
4923 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
4925 struct kvm_memslots
*slots
;
4926 struct kvm_memory_slot
*memslot
;
4929 spin_lock(&kvm
->mmu_lock
);
4930 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
4931 slots
= __kvm_memslots(kvm
, i
);
4932 kvm_for_each_memslot(memslot
, slots
) {
4935 start
= max(gfn_start
, memslot
->base_gfn
);
4936 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
4940 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
4941 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
4942 start
, end
- 1, true);
4946 spin_unlock(&kvm
->mmu_lock
);
4949 static bool slot_rmap_write_protect(struct kvm
*kvm
,
4950 struct kvm_rmap_head
*rmap_head
)
4952 return __rmap_write_protect(kvm
, rmap_head
, false);
4955 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
4956 struct kvm_memory_slot
*memslot
)
4960 spin_lock(&kvm
->mmu_lock
);
4961 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
4963 spin_unlock(&kvm
->mmu_lock
);
4966 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4967 * which do tlb flush out of mmu-lock should be serialized by
4968 * kvm->slots_lock otherwise tlb flush would be missed.
4970 lockdep_assert_held(&kvm
->slots_lock
);
4973 * We can flush all the TLBs out of the mmu lock without TLB
4974 * corruption since we just change the spte from writable to
4975 * readonly so that we only need to care the case of changing
4976 * spte from present to present (changing the spte from present
4977 * to nonpresent will flush all the TLBs immediately), in other
4978 * words, the only case we care is mmu_spte_update() where we
4979 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4980 * instead of PT_WRITABLE_MASK, that means it does not depend
4981 * on PT_WRITABLE_MASK anymore.
4984 kvm_flush_remote_tlbs(kvm
);
4987 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
4988 struct kvm_rmap_head
*rmap_head
)
4991 struct rmap_iterator iter
;
4992 int need_tlb_flush
= 0;
4994 struct kvm_mmu_page
*sp
;
4997 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
4998 sp
= page_header(__pa(sptep
));
4999 pfn
= spte_to_pfn(*sptep
);
5002 * We cannot do huge page mapping for indirect shadow pages,
5003 * which are found on the last rmap (level = 1) when not using
5004 * tdp; such shadow pages are synced with the page table in
5005 * the guest, and the guest page table is using 4K page size
5006 * mapping if the indirect sp has level = 1.
5008 if (sp
->role
.direct
&&
5009 !kvm_is_reserved_pfn(pfn
) &&
5010 PageTransCompoundMap(pfn_to_page(pfn
))) {
5011 drop_spte(kvm
, sptep
);
5017 return need_tlb_flush
;
5020 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5021 const struct kvm_memory_slot
*memslot
)
5023 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5024 spin_lock(&kvm
->mmu_lock
);
5025 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5026 kvm_mmu_zap_collapsible_spte
, true);
5027 spin_unlock(&kvm
->mmu_lock
);
5030 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5031 struct kvm_memory_slot
*memslot
)
5035 spin_lock(&kvm
->mmu_lock
);
5036 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5037 spin_unlock(&kvm
->mmu_lock
);
5039 lockdep_assert_held(&kvm
->slots_lock
);
5042 * It's also safe to flush TLBs out of mmu lock here as currently this
5043 * function is only used for dirty logging, in which case flushing TLB
5044 * out of mmu lock also guarantees no dirty pages will be lost in
5048 kvm_flush_remote_tlbs(kvm
);
5050 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5052 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5053 struct kvm_memory_slot
*memslot
)
5057 spin_lock(&kvm
->mmu_lock
);
5058 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5060 spin_unlock(&kvm
->mmu_lock
);
5062 /* see kvm_mmu_slot_remove_write_access */
5063 lockdep_assert_held(&kvm
->slots_lock
);
5066 kvm_flush_remote_tlbs(kvm
);
5068 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5070 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5071 struct kvm_memory_slot
*memslot
)
5075 spin_lock(&kvm
->mmu_lock
);
5076 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5077 spin_unlock(&kvm
->mmu_lock
);
5079 lockdep_assert_held(&kvm
->slots_lock
);
5081 /* see kvm_mmu_slot_leaf_clear_dirty */
5083 kvm_flush_remote_tlbs(kvm
);
5085 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5087 #define BATCH_ZAP_PAGES 10
5088 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5090 struct kvm_mmu_page
*sp
, *node
;
5094 list_for_each_entry_safe_reverse(sp
, node
,
5095 &kvm
->arch
.active_mmu_pages
, link
) {
5099 * No obsolete page exists before new created page since
5100 * active_mmu_pages is the FIFO list.
5102 if (!is_obsolete_sp(kvm
, sp
))
5106 * Since we are reversely walking the list and the invalid
5107 * list will be moved to the head, skip the invalid page
5108 * can help us to avoid the infinity list walking.
5110 if (sp
->role
.invalid
)
5114 * Need not flush tlb since we only zap the sp with invalid
5115 * generation number.
5117 if (batch
>= BATCH_ZAP_PAGES
&&
5118 cond_resched_lock(&kvm
->mmu_lock
)) {
5123 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
5124 &kvm
->arch
.zapped_obsolete_pages
);
5132 * Should flush tlb before free page tables since lockless-walking
5133 * may use the pages.
5135 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5139 * Fast invalidate all shadow pages and use lock-break technique
5140 * to zap obsolete pages.
5142 * It's required when memslot is being deleted or VM is being
5143 * destroyed, in these cases, we should ensure that KVM MMU does
5144 * not use any resource of the being-deleted slot or all slots
5145 * after calling the function.
5147 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
5149 spin_lock(&kvm
->mmu_lock
);
5150 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
5151 kvm
->arch
.mmu_valid_gen
++;
5154 * Notify all vcpus to reload its shadow page table
5155 * and flush TLB. Then all vcpus will switch to new
5156 * shadow page table with the new mmu_valid_gen.
5158 * Note: we should do this under the protection of
5159 * mmu-lock, otherwise, vcpu would purge shadow page
5160 * but miss tlb flush.
5162 kvm_reload_remote_mmus(kvm
);
5164 kvm_zap_obsolete_pages(kvm
);
5165 spin_unlock(&kvm
->mmu_lock
);
5168 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5170 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5173 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
5176 * The very rare case: if the generation-number is round,
5177 * zap all shadow pages.
5179 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
5180 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5181 kvm_mmu_invalidate_zap_all_pages(kvm
);
5185 static unsigned long
5186 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5189 int nr_to_scan
= sc
->nr_to_scan
;
5190 unsigned long freed
= 0;
5192 spin_lock(&kvm_lock
);
5194 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5196 LIST_HEAD(invalid_list
);
5199 * Never scan more than sc->nr_to_scan VM instances.
5200 * Will not hit this condition practically since we do not try
5201 * to shrink more than one VM and it is very unlikely to see
5202 * !n_used_mmu_pages so many times.
5207 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5208 * here. We may skip a VM instance errorneosly, but we do not
5209 * want to shrink a VM that only started to populate its MMU
5212 if (!kvm
->arch
.n_used_mmu_pages
&&
5213 !kvm_has_zapped_obsolete_pages(kvm
))
5216 idx
= srcu_read_lock(&kvm
->srcu
);
5217 spin_lock(&kvm
->mmu_lock
);
5219 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5220 kvm_mmu_commit_zap_page(kvm
,
5221 &kvm
->arch
.zapped_obsolete_pages
);
5225 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5227 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5230 spin_unlock(&kvm
->mmu_lock
);
5231 srcu_read_unlock(&kvm
->srcu
, idx
);
5234 * unfair on small ones
5235 * per-vm shrinkers cry out
5236 * sadness comes quickly
5238 list_move_tail(&kvm
->vm_list
, &vm_list
);
5242 spin_unlock(&kvm_lock
);
5246 static unsigned long
5247 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5249 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5252 static struct shrinker mmu_shrinker
= {
5253 .count_objects
= mmu_shrink_count
,
5254 .scan_objects
= mmu_shrink_scan
,
5255 .seeks
= DEFAULT_SEEKS
* 10,
5258 static void mmu_destroy_caches(void)
5260 if (pte_list_desc_cache
)
5261 kmem_cache_destroy(pte_list_desc_cache
);
5262 if (mmu_page_header_cache
)
5263 kmem_cache_destroy(mmu_page_header_cache
);
5266 int kvm_mmu_module_init(void)
5268 kvm_mmu_clear_all_pte_masks();
5270 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5271 sizeof(struct pte_list_desc
),
5273 if (!pte_list_desc_cache
)
5276 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5277 sizeof(struct kvm_mmu_page
),
5279 if (!mmu_page_header_cache
)
5282 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5285 register_shrinker(&mmu_shrinker
);
5290 mmu_destroy_caches();
5295 * Caculate mmu pages needed for kvm.
5297 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5299 unsigned int nr_mmu_pages
;
5300 unsigned int nr_pages
= 0;
5301 struct kvm_memslots
*slots
;
5302 struct kvm_memory_slot
*memslot
;
5305 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5306 slots
= __kvm_memslots(kvm
, i
);
5308 kvm_for_each_memslot(memslot
, slots
)
5309 nr_pages
+= memslot
->npages
;
5312 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5313 nr_mmu_pages
= max(nr_mmu_pages
,
5314 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5316 return nr_mmu_pages
;
5319 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5321 kvm_mmu_unload(vcpu
);
5322 free_mmu_pages(vcpu
);
5323 mmu_free_memory_caches(vcpu
);
5326 void kvm_mmu_module_exit(void)
5328 mmu_destroy_caches();
5329 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5330 unregister_shrinker(&mmu_shrinker
);
5331 mmu_audit_disable();