2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
52 * When setting this variable to true it enables Two-Dimensional-Paging
53 * where the hardware walks 2 page tables:
54 * 1. the guest-virtual to guest-physical
55 * 2. while doing 1. it walks guest-physical to host-physical
56 * If the hardware supports that we don't need to do shadow paging.
58 bool tdp_enabled
= false;
62 AUDIT_POST_PAGE_FAULT
,
73 module_param(dbg
, bool, 0644);
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
77 #define MMU_WARN_ON(x) WARN_ON(x)
79 #define pgprintk(x...) do { } while (0)
80 #define rmap_printk(x...) do { } while (0)
81 #define MMU_WARN_ON(x) do { } while (0)
84 #define PTE_PREFETCH_NUM 8
86 #define PT_FIRST_AVAIL_BITS_SHIFT 10
87 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
89 #define PT64_LEVEL_BITS 9
91 #define PT64_LEVEL_SHIFT(level) \
92 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
94 #define PT64_INDEX(address, level)\
95 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
98 #define PT32_LEVEL_BITS 10
100 #define PT32_LEVEL_SHIFT(level) \
101 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
103 #define PT32_LVL_OFFSET_MASK(level) \
104 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
105 * PT32_LEVEL_BITS))) - 1))
107 #define PT32_INDEX(address, level)\
108 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
111 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
112 #define PT64_DIR_BASE_ADDR_MASK \
113 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
114 #define PT64_LVL_ADDR_MASK(level) \
115 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT64_LEVEL_BITS))) - 1))
117 #define PT64_LVL_OFFSET_MASK(level) \
118 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
119 * PT64_LEVEL_BITS))) - 1))
121 #define PT32_BASE_ADDR_MASK PAGE_MASK
122 #define PT32_DIR_BASE_ADDR_MASK \
123 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
124 #define PT32_LVL_ADDR_MASK(level) \
125 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT32_LEVEL_BITS))) - 1))
128 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
129 | shadow_x_mask | shadow_nx_mask)
131 #define ACC_EXEC_MASK 1
132 #define ACC_WRITE_MASK PT_WRITABLE_MASK
133 #define ACC_USER_MASK PT_USER_MASK
134 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
136 /* The mask for the R/X bits in EPT PTEs */
137 #define PT64_EPT_READABLE_MASK 0x1ull
138 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
140 #include <trace/events/kvm.h>
142 #define CREATE_TRACE_POINTS
143 #include "mmutrace.h"
145 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
146 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
148 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
150 /* make pte_list_desc fit well in cache line */
151 #define PTE_LIST_EXT 3
153 struct pte_list_desc
{
154 u64
*sptes
[PTE_LIST_EXT
];
155 struct pte_list_desc
*more
;
158 struct kvm_shadow_walk_iterator
{
166 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
167 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
168 shadow_walk_okay(&(_walker)); \
169 shadow_walk_next(&(_walker)))
171 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
172 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
173 shadow_walk_okay(&(_walker)) && \
174 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
175 __shadow_walk_next(&(_walker), spte))
177 static struct kmem_cache
*pte_list_desc_cache
;
178 static struct kmem_cache
*mmu_page_header_cache
;
179 static struct percpu_counter kvm_total_used_mmu_pages
;
181 static u64 __read_mostly shadow_nx_mask
;
182 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
183 static u64 __read_mostly shadow_user_mask
;
184 static u64 __read_mostly shadow_accessed_mask
;
185 static u64 __read_mostly shadow_dirty_mask
;
186 static u64 __read_mostly shadow_mmio_mask
;
187 static u64 __read_mostly shadow_mmio_value
;
188 static u64 __read_mostly shadow_present_mask
;
191 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
192 * Non-present SPTEs with shadow_acc_track_value set are in place for access
195 static u64 __read_mostly shadow_acc_track_mask
;
196 static const u64 shadow_acc_track_value
= SPTE_SPECIAL_MASK
;
199 * The mask/shift to use for saving the original R/X bits when marking the PTE
200 * as not-present for access tracking purposes. We do not save the W bit as the
201 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
202 * restored only when a write is attempted to the page.
204 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
205 PT64_EPT_EXECUTABLE_MASK
;
206 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
208 static void mmu_spte_set(u64
*sptep
, u64 spte
);
209 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
211 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
, u64 mmio_value
)
213 BUG_ON((mmio_mask
& mmio_value
) != mmio_value
);
214 shadow_mmio_value
= mmio_value
| SPTE_SPECIAL_MASK
;
215 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
217 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
219 static inline bool sp_ad_disabled(struct kvm_mmu_page
*sp
)
221 return sp
->role
.ad_disabled
;
224 static inline bool spte_ad_enabled(u64 spte
)
226 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
227 return !(spte
& shadow_acc_track_value
);
230 static inline u64
spte_shadow_accessed_mask(u64 spte
)
232 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
233 return spte_ad_enabled(spte
) ? shadow_accessed_mask
: 0;
236 static inline u64
spte_shadow_dirty_mask(u64 spte
)
238 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
239 return spte_ad_enabled(spte
) ? shadow_dirty_mask
: 0;
242 static inline bool is_access_track_spte(u64 spte
)
244 return !spte_ad_enabled(spte
) && (spte
& shadow_acc_track_mask
) == 0;
248 * the low bit of the generation number is always presumed to be zero.
249 * This disables mmio caching during memslot updates. The concept is
250 * similar to a seqcount but instead of retrying the access we just punt
251 * and ignore the cache.
253 * spte bits 3-11 are used as bits 1-9 of the generation number,
254 * the bits 52-61 are used as bits 10-19 of the generation number.
256 #define MMIO_SPTE_GEN_LOW_SHIFT 2
257 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
259 #define MMIO_GEN_SHIFT 20
260 #define MMIO_GEN_LOW_SHIFT 10
261 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
262 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
264 static u64
generation_mmio_spte_mask(unsigned int gen
)
268 WARN_ON(gen
& ~MMIO_GEN_MASK
);
270 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
271 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
275 static unsigned int get_mmio_spte_generation(u64 spte
)
279 spte
&= ~shadow_mmio_mask
;
281 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
282 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
286 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
288 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
291 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
294 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
295 u64 mask
= generation_mmio_spte_mask(gen
);
297 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
298 mask
|= shadow_mmio_value
| access
| gfn
<< PAGE_SHIFT
;
300 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
301 mmu_spte_set(sptep
, mask
);
304 static bool is_mmio_spte(u64 spte
)
306 return (spte
& shadow_mmio_mask
) == shadow_mmio_value
;
309 static gfn_t
get_mmio_spte_gfn(u64 spte
)
311 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
312 return (spte
& ~mask
) >> PAGE_SHIFT
;
315 static unsigned get_mmio_spte_access(u64 spte
)
317 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
318 return (spte
& ~mask
) & ~PAGE_MASK
;
321 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
322 kvm_pfn_t pfn
, unsigned access
)
324 if (unlikely(is_noslot_pfn(pfn
))) {
325 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
332 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
334 unsigned int kvm_gen
, spte_gen
;
336 kvm_gen
= kvm_current_mmio_generation(vcpu
);
337 spte_gen
= get_mmio_spte_generation(spte
);
339 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
340 return likely(kvm_gen
== spte_gen
);
344 * Sets the shadow PTE masks used by the MMU.
347 * - Setting either @accessed_mask or @dirty_mask requires setting both
348 * - At least one of @accessed_mask or @acc_track_mask must be set
350 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
351 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
354 BUG_ON(!dirty_mask
!= !accessed_mask
);
355 BUG_ON(!accessed_mask
&& !acc_track_mask
);
356 BUG_ON(acc_track_mask
& shadow_acc_track_value
);
358 shadow_user_mask
= user_mask
;
359 shadow_accessed_mask
= accessed_mask
;
360 shadow_dirty_mask
= dirty_mask
;
361 shadow_nx_mask
= nx_mask
;
362 shadow_x_mask
= x_mask
;
363 shadow_present_mask
= p_mask
;
364 shadow_acc_track_mask
= acc_track_mask
;
366 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
368 void kvm_mmu_clear_all_pte_masks(void)
370 shadow_user_mask
= 0;
371 shadow_accessed_mask
= 0;
372 shadow_dirty_mask
= 0;
375 shadow_mmio_mask
= 0;
376 shadow_present_mask
= 0;
377 shadow_acc_track_mask
= 0;
380 static int is_cpuid_PSE36(void)
385 static int is_nx(struct kvm_vcpu
*vcpu
)
387 return vcpu
->arch
.efer
& EFER_NX
;
390 static int is_shadow_present_pte(u64 pte
)
392 return (pte
!= 0) && !is_mmio_spte(pte
);
395 static int is_large_pte(u64 pte
)
397 return pte
& PT_PAGE_SIZE_MASK
;
400 static int is_last_spte(u64 pte
, int level
)
402 if (level
== PT_PAGE_TABLE_LEVEL
)
404 if (is_large_pte(pte
))
409 static bool is_executable_pte(u64 spte
)
411 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
414 static kvm_pfn_t
spte_to_pfn(u64 pte
)
416 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
419 static gfn_t
pse36_gfn_delta(u32 gpte
)
421 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
423 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
427 static void __set_spte(u64
*sptep
, u64 spte
)
429 WRITE_ONCE(*sptep
, spte
);
432 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
434 WRITE_ONCE(*sptep
, spte
);
437 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
439 return xchg(sptep
, spte
);
442 static u64
__get_spte_lockless(u64
*sptep
)
444 return ACCESS_ONCE(*sptep
);
455 static void count_spte_clear(u64
*sptep
, u64 spte
)
457 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
459 if (is_shadow_present_pte(spte
))
462 /* Ensure the spte is completely set before we increase the count */
464 sp
->clear_spte_count
++;
467 static void __set_spte(u64
*sptep
, u64 spte
)
469 union split_spte
*ssptep
, sspte
;
471 ssptep
= (union split_spte
*)sptep
;
472 sspte
= (union split_spte
)spte
;
474 ssptep
->spte_high
= sspte
.spte_high
;
477 * If we map the spte from nonpresent to present, We should store
478 * the high bits firstly, then set present bit, so cpu can not
479 * fetch this spte while we are setting the spte.
483 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
486 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
488 union split_spte
*ssptep
, sspte
;
490 ssptep
= (union split_spte
*)sptep
;
491 sspte
= (union split_spte
)spte
;
493 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
496 * If we map the spte from present to nonpresent, we should clear
497 * present bit firstly to avoid vcpu fetch the old high bits.
501 ssptep
->spte_high
= sspte
.spte_high
;
502 count_spte_clear(sptep
, spte
);
505 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
507 union split_spte
*ssptep
, sspte
, orig
;
509 ssptep
= (union split_spte
*)sptep
;
510 sspte
= (union split_spte
)spte
;
512 /* xchg acts as a barrier before the setting of the high bits */
513 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
514 orig
.spte_high
= ssptep
->spte_high
;
515 ssptep
->spte_high
= sspte
.spte_high
;
516 count_spte_clear(sptep
, spte
);
522 * The idea using the light way get the spte on x86_32 guest is from
523 * gup_get_pte(arch/x86/mm/gup.c).
525 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
526 * coalesces them and we are running out of the MMU lock. Therefore
527 * we need to protect against in-progress updates of the spte.
529 * Reading the spte while an update is in progress may get the old value
530 * for the high part of the spte. The race is fine for a present->non-present
531 * change (because the high part of the spte is ignored for non-present spte),
532 * but for a present->present change we must reread the spte.
534 * All such changes are done in two steps (present->non-present and
535 * non-present->present), hence it is enough to count the number of
536 * present->non-present updates: if it changed while reading the spte,
537 * we might have hit the race. This is done using clear_spte_count.
539 static u64
__get_spte_lockless(u64
*sptep
)
541 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
542 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
546 count
= sp
->clear_spte_count
;
549 spte
.spte_low
= orig
->spte_low
;
552 spte
.spte_high
= orig
->spte_high
;
555 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
556 count
!= sp
->clear_spte_count
))
563 static bool spte_can_locklessly_be_made_writable(u64 spte
)
565 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
566 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
569 static bool spte_has_volatile_bits(u64 spte
)
571 if (!is_shadow_present_pte(spte
))
575 * Always atomically update spte if it can be updated
576 * out of mmu-lock, it can ensure dirty bit is not lost,
577 * also, it can help us to get a stable is_writable_pte()
578 * to ensure tlb flush is not missed.
580 if (spte_can_locklessly_be_made_writable(spte
) ||
581 is_access_track_spte(spte
))
584 if (spte_ad_enabled(spte
)) {
585 if ((spte
& shadow_accessed_mask
) == 0 ||
586 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
593 static bool is_accessed_spte(u64 spte
)
595 u64 accessed_mask
= spte_shadow_accessed_mask(spte
);
597 return accessed_mask
? spte
& accessed_mask
598 : !is_access_track_spte(spte
);
601 static bool is_dirty_spte(u64 spte
)
603 u64 dirty_mask
= spte_shadow_dirty_mask(spte
);
605 return dirty_mask
? spte
& dirty_mask
: spte
& PT_WRITABLE_MASK
;
608 /* Rules for using mmu_spte_set:
609 * Set the sptep from nonpresent to present.
610 * Note: the sptep being assigned *must* be either not present
611 * or in a state where the hardware will not attempt to update
614 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
616 WARN_ON(is_shadow_present_pte(*sptep
));
617 __set_spte(sptep
, new_spte
);
621 * Update the SPTE (excluding the PFN), but do not track changes in its
622 * accessed/dirty status.
624 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
626 u64 old_spte
= *sptep
;
628 WARN_ON(!is_shadow_present_pte(new_spte
));
630 if (!is_shadow_present_pte(old_spte
)) {
631 mmu_spte_set(sptep
, new_spte
);
635 if (!spte_has_volatile_bits(old_spte
))
636 __update_clear_spte_fast(sptep
, new_spte
);
638 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
640 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
645 /* Rules for using mmu_spte_update:
646 * Update the state bits, it means the mapped pfn is not changed.
648 * Whenever we overwrite a writable spte with a read-only one we
649 * should flush remote TLBs. Otherwise rmap_write_protect
650 * will find a read-only spte, even though the writable spte
651 * might be cached on a CPU's TLB, the return value indicates this
654 * Returns true if the TLB needs to be flushed
656 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
659 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
661 if (!is_shadow_present_pte(old_spte
))
665 * For the spte updated out of mmu-lock is safe, since
666 * we always atomically update it, see the comments in
667 * spte_has_volatile_bits().
669 if (spte_can_locklessly_be_made_writable(old_spte
) &&
670 !is_writable_pte(new_spte
))
674 * Flush TLB when accessed/dirty states are changed in the page tables,
675 * to guarantee consistency between TLB and page tables.
678 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
680 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
683 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
685 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
692 * Rules for using mmu_spte_clear_track_bits:
693 * It sets the sptep from present to nonpresent, and track the
694 * state bits, it is used to clear the last level sptep.
695 * Returns non-zero if the PTE was previously valid.
697 static int mmu_spte_clear_track_bits(u64
*sptep
)
700 u64 old_spte
= *sptep
;
702 if (!spte_has_volatile_bits(old_spte
))
703 __update_clear_spte_fast(sptep
, 0ull);
705 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
707 if (!is_shadow_present_pte(old_spte
))
710 pfn
= spte_to_pfn(old_spte
);
713 * KVM does not hold the refcount of the page used by
714 * kvm mmu, before reclaiming the page, we should
715 * unmap it from mmu first.
717 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
719 if (is_accessed_spte(old_spte
))
720 kvm_set_pfn_accessed(pfn
);
722 if (is_dirty_spte(old_spte
))
723 kvm_set_pfn_dirty(pfn
);
729 * Rules for using mmu_spte_clear_no_track:
730 * Directly clear spte without caring the state bits of sptep,
731 * it is used to set the upper level spte.
733 static void mmu_spte_clear_no_track(u64
*sptep
)
735 __update_clear_spte_fast(sptep
, 0ull);
738 static u64
mmu_spte_get_lockless(u64
*sptep
)
740 return __get_spte_lockless(sptep
);
743 static u64
mark_spte_for_access_track(u64 spte
)
745 if (spte_ad_enabled(spte
))
746 return spte
& ~shadow_accessed_mask
;
748 if (is_access_track_spte(spte
))
752 * Making an Access Tracking PTE will result in removal of write access
753 * from the PTE. So, verify that we will be able to restore the write
754 * access in the fast page fault path later on.
756 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
757 !spte_can_locklessly_be_made_writable(spte
),
758 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
760 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
761 shadow_acc_track_saved_bits_shift
),
762 "kvm: Access Tracking saved bit locations are not zero\n");
764 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
765 shadow_acc_track_saved_bits_shift
;
766 spte
&= ~shadow_acc_track_mask
;
771 /* Restore an acc-track PTE back to a regular PTE */
772 static u64
restore_acc_track_spte(u64 spte
)
775 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
776 & shadow_acc_track_saved_bits_mask
;
778 WARN_ON_ONCE(spte_ad_enabled(spte
));
779 WARN_ON_ONCE(!is_access_track_spte(spte
));
781 new_spte
&= ~shadow_acc_track_mask
;
782 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
783 shadow_acc_track_saved_bits_shift
);
784 new_spte
|= saved_bits
;
789 /* Returns the Accessed status of the PTE and resets it at the same time. */
790 static bool mmu_spte_age(u64
*sptep
)
792 u64 spte
= mmu_spte_get_lockless(sptep
);
794 if (!is_accessed_spte(spte
))
797 if (spte_ad_enabled(spte
)) {
798 clear_bit((ffs(shadow_accessed_mask
) - 1),
799 (unsigned long *)sptep
);
802 * Capture the dirty status of the page, so that it doesn't get
803 * lost when the SPTE is marked for access tracking.
805 if (is_writable_pte(spte
))
806 kvm_set_pfn_dirty(spte_to_pfn(spte
));
808 spte
= mark_spte_for_access_track(spte
);
809 mmu_spte_update_no_track(sptep
, spte
);
815 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
818 * Prevent page table teardown by making any free-er wait during
819 * kvm_flush_remote_tlbs() IPI to all active vcpus.
824 * Make sure a following spte read is not reordered ahead of the write
827 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
830 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
833 * Make sure the write to vcpu->mode is not reordered in front of
834 * reads to sptes. If it does, kvm_commit_zap_page() can see us
835 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
837 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
841 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
842 struct kmem_cache
*base_cache
, int min
)
846 if (cache
->nobjs
>= min
)
848 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
849 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
852 cache
->objects
[cache
->nobjs
++] = obj
;
857 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
862 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
863 struct kmem_cache
*cache
)
866 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
869 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
874 if (cache
->nobjs
>= min
)
876 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
877 page
= (void *)__get_free_page(GFP_KERNEL
);
880 cache
->objects
[cache
->nobjs
++] = page
;
885 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
888 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
891 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
895 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
896 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
899 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
902 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
903 mmu_page_header_cache
, 4);
908 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
910 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
911 pte_list_desc_cache
);
912 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
913 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
914 mmu_page_header_cache
);
917 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
922 p
= mc
->objects
[--mc
->nobjs
];
926 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
928 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
931 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
933 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
936 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
938 if (!sp
->role
.direct
)
939 return sp
->gfns
[index
];
941 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
944 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
947 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
949 sp
->gfns
[index
] = gfn
;
953 * Return the pointer to the large page information for a given gfn,
954 * handling slots that are not large page aligned.
956 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
957 struct kvm_memory_slot
*slot
,
962 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
963 return &slot
->arch
.lpage_info
[level
- 2][idx
];
966 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
967 gfn_t gfn
, int count
)
969 struct kvm_lpage_info
*linfo
;
972 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
973 linfo
= lpage_info_slot(gfn
, slot
, i
);
974 linfo
->disallow_lpage
+= count
;
975 WARN_ON(linfo
->disallow_lpage
< 0);
979 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
981 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
984 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
986 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
989 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
991 struct kvm_memslots
*slots
;
992 struct kvm_memory_slot
*slot
;
995 kvm
->arch
.indirect_shadow_pages
++;
997 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
998 slot
= __gfn_to_memslot(slots
, gfn
);
1000 /* the non-leaf shadow pages are keeping readonly. */
1001 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1002 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
1003 KVM_PAGE_TRACK_WRITE
);
1005 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
1008 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1010 struct kvm_memslots
*slots
;
1011 struct kvm_memory_slot
*slot
;
1014 kvm
->arch
.indirect_shadow_pages
--;
1016 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1017 slot
= __gfn_to_memslot(slots
, gfn
);
1018 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1019 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
1020 KVM_PAGE_TRACK_WRITE
);
1022 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
1025 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
1026 struct kvm_memory_slot
*slot
)
1028 struct kvm_lpage_info
*linfo
;
1031 linfo
= lpage_info_slot(gfn
, slot
, level
);
1032 return !!linfo
->disallow_lpage
;
1038 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1041 struct kvm_memory_slot
*slot
;
1043 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1044 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
1047 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
1049 unsigned long page_size
;
1052 page_size
= kvm_host_page_size(kvm
, gfn
);
1054 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1055 if (page_size
>= KVM_HPAGE_SIZE(i
))
1064 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
1067 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1069 if (no_dirty_log
&& slot
->dirty_bitmap
)
1075 static struct kvm_memory_slot
*
1076 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1079 struct kvm_memory_slot
*slot
;
1081 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1082 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
1088 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
1089 bool *force_pt_level
)
1091 int host_level
, level
, max_level
;
1092 struct kvm_memory_slot
*slot
;
1094 if (unlikely(*force_pt_level
))
1095 return PT_PAGE_TABLE_LEVEL
;
1097 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
1098 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
1099 if (unlikely(*force_pt_level
))
1100 return PT_PAGE_TABLE_LEVEL
;
1102 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
1104 if (host_level
== PT_PAGE_TABLE_LEVEL
)
1107 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
1109 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
1110 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
1117 * About rmap_head encoding:
1119 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1120 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1121 * pte_list_desc containing more mappings.
1125 * Returns the number of pointers in the rmap chain, not counting the new one.
1127 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1128 struct kvm_rmap_head
*rmap_head
)
1130 struct pte_list_desc
*desc
;
1133 if (!rmap_head
->val
) {
1134 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1135 rmap_head
->val
= (unsigned long)spte
;
1136 } else if (!(rmap_head
->val
& 1)) {
1137 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1138 desc
= mmu_alloc_pte_list_desc(vcpu
);
1139 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1140 desc
->sptes
[1] = spte
;
1141 rmap_head
->val
= (unsigned long)desc
| 1;
1144 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1145 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1146 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1148 count
+= PTE_LIST_EXT
;
1150 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1151 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1154 for (i
= 0; desc
->sptes
[i
]; ++i
)
1156 desc
->sptes
[i
] = spte
;
1162 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1163 struct pte_list_desc
*desc
, int i
,
1164 struct pte_list_desc
*prev_desc
)
1168 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1170 desc
->sptes
[i
] = desc
->sptes
[j
];
1171 desc
->sptes
[j
] = NULL
;
1174 if (!prev_desc
&& !desc
->more
)
1175 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1178 prev_desc
->more
= desc
->more
;
1180 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1181 mmu_free_pte_list_desc(desc
);
1184 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1186 struct pte_list_desc
*desc
;
1187 struct pte_list_desc
*prev_desc
;
1190 if (!rmap_head
->val
) {
1191 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1193 } else if (!(rmap_head
->val
& 1)) {
1194 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1195 if ((u64
*)rmap_head
->val
!= spte
) {
1196 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1201 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1202 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1205 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1206 if (desc
->sptes
[i
] == spte
) {
1207 pte_list_desc_remove_entry(rmap_head
,
1208 desc
, i
, prev_desc
);
1215 pr_err("pte_list_remove: %p many->many\n", spte
);
1220 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1221 struct kvm_memory_slot
*slot
)
1225 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1226 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1229 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1230 struct kvm_mmu_page
*sp
)
1232 struct kvm_memslots
*slots
;
1233 struct kvm_memory_slot
*slot
;
1235 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1236 slot
= __gfn_to_memslot(slots
, gfn
);
1237 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1240 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1242 struct kvm_mmu_memory_cache
*cache
;
1244 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1245 return mmu_memory_cache_free_objects(cache
);
1248 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1250 struct kvm_mmu_page
*sp
;
1251 struct kvm_rmap_head
*rmap_head
;
1253 sp
= page_header(__pa(spte
));
1254 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1255 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1256 return pte_list_add(vcpu
, spte
, rmap_head
);
1259 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1261 struct kvm_mmu_page
*sp
;
1263 struct kvm_rmap_head
*rmap_head
;
1265 sp
= page_header(__pa(spte
));
1266 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1267 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1268 pte_list_remove(spte
, rmap_head
);
1272 * Used by the following functions to iterate through the sptes linked by a
1273 * rmap. All fields are private and not assumed to be used outside.
1275 struct rmap_iterator
{
1276 /* private fields */
1277 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1278 int pos
; /* index of the sptep */
1282 * Iteration must be started by this function. This should also be used after
1283 * removing/dropping sptes from the rmap link because in such cases the
1284 * information in the itererator may not be valid.
1286 * Returns sptep if found, NULL otherwise.
1288 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1289 struct rmap_iterator
*iter
)
1293 if (!rmap_head
->val
)
1296 if (!(rmap_head
->val
& 1)) {
1298 sptep
= (u64
*)rmap_head
->val
;
1302 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1304 sptep
= iter
->desc
->sptes
[iter
->pos
];
1306 BUG_ON(!is_shadow_present_pte(*sptep
));
1311 * Must be used with a valid iterator: e.g. after rmap_get_first().
1313 * Returns sptep if found, NULL otherwise.
1315 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1320 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1322 sptep
= iter
->desc
->sptes
[iter
->pos
];
1327 iter
->desc
= iter
->desc
->more
;
1331 /* desc->sptes[0] cannot be NULL */
1332 sptep
= iter
->desc
->sptes
[iter
->pos
];
1339 BUG_ON(!is_shadow_present_pte(*sptep
));
1343 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1344 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1345 _spte_; _spte_ = rmap_get_next(_iter_))
1347 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1349 if (mmu_spte_clear_track_bits(sptep
))
1350 rmap_remove(kvm
, sptep
);
1354 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1356 if (is_large_pte(*sptep
)) {
1357 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1358 PT_PAGE_TABLE_LEVEL
);
1359 drop_spte(kvm
, sptep
);
1367 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1369 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1370 kvm_flush_remote_tlbs(vcpu
->kvm
);
1374 * Write-protect on the specified @sptep, @pt_protect indicates whether
1375 * spte write-protection is caused by protecting shadow page table.
1377 * Note: write protection is difference between dirty logging and spte
1379 * - for dirty logging, the spte can be set to writable at anytime if
1380 * its dirty bitmap is properly set.
1381 * - for spte protection, the spte can be writable only after unsync-ing
1384 * Return true if tlb need be flushed.
1386 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1390 if (!is_writable_pte(spte
) &&
1391 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1394 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1397 spte
&= ~SPTE_MMU_WRITEABLE
;
1398 spte
= spte
& ~PT_WRITABLE_MASK
;
1400 return mmu_spte_update(sptep
, spte
);
1403 static bool __rmap_write_protect(struct kvm
*kvm
,
1404 struct kvm_rmap_head
*rmap_head
,
1408 struct rmap_iterator iter
;
1411 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1412 flush
|= spte_write_protect(sptep
, pt_protect
);
1417 static bool spte_clear_dirty(u64
*sptep
)
1421 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1423 spte
&= ~shadow_dirty_mask
;
1425 return mmu_spte_update(sptep
, spte
);
1428 static bool wrprot_ad_disabled_spte(u64
*sptep
)
1430 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1431 (unsigned long *)sptep
);
1433 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1435 return was_writable
;
1439 * Gets the GFN ready for another round of dirty logging by clearing the
1440 * - D bit on ad-enabled SPTEs, and
1441 * - W bit on ad-disabled SPTEs.
1442 * Returns true iff any D or W bits were cleared.
1444 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1447 struct rmap_iterator iter
;
1450 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1451 if (spte_ad_enabled(*sptep
))
1452 flush
|= spte_clear_dirty(sptep
);
1454 flush
|= wrprot_ad_disabled_spte(sptep
);
1459 static bool spte_set_dirty(u64
*sptep
)
1463 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1465 spte
|= shadow_dirty_mask
;
1467 return mmu_spte_update(sptep
, spte
);
1470 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1473 struct rmap_iterator iter
;
1476 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1477 if (spte_ad_enabled(*sptep
))
1478 flush
|= spte_set_dirty(sptep
);
1484 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1485 * @kvm: kvm instance
1486 * @slot: slot to protect
1487 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1488 * @mask: indicates which pages we should protect
1490 * Used when we do not need to care about huge page mappings: e.g. during dirty
1491 * logging we do not have any such mappings.
1493 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1494 struct kvm_memory_slot
*slot
,
1495 gfn_t gfn_offset
, unsigned long mask
)
1497 struct kvm_rmap_head
*rmap_head
;
1500 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1501 PT_PAGE_TABLE_LEVEL
, slot
);
1502 __rmap_write_protect(kvm
, rmap_head
, false);
1504 /* clear the first set bit */
1510 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1511 * protect the page if the D-bit isn't supported.
1512 * @kvm: kvm instance
1513 * @slot: slot to clear D-bit
1514 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1515 * @mask: indicates which pages we should clear D-bit
1517 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1519 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1520 struct kvm_memory_slot
*slot
,
1521 gfn_t gfn_offset
, unsigned long mask
)
1523 struct kvm_rmap_head
*rmap_head
;
1526 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1527 PT_PAGE_TABLE_LEVEL
, slot
);
1528 __rmap_clear_dirty(kvm
, rmap_head
);
1530 /* clear the first set bit */
1534 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1537 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1540 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1541 * enable dirty logging for them.
1543 * Used when we do not need to care about huge page mappings: e.g. during dirty
1544 * logging we do not have any such mappings.
1546 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1547 struct kvm_memory_slot
*slot
,
1548 gfn_t gfn_offset
, unsigned long mask
)
1550 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1551 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1554 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1558 * kvm_arch_write_log_dirty - emulate dirty page logging
1559 * @vcpu: Guest mode vcpu
1561 * Emulate arch specific page modification logging for the
1564 int kvm_arch_write_log_dirty(struct kvm_vcpu
*vcpu
)
1566 if (kvm_x86_ops
->write_log_dirty
)
1567 return kvm_x86_ops
->write_log_dirty(vcpu
);
1572 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1573 struct kvm_memory_slot
*slot
, u64 gfn
)
1575 struct kvm_rmap_head
*rmap_head
;
1577 bool write_protected
= false;
1579 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1580 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1581 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1584 return write_protected
;
1587 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1589 struct kvm_memory_slot
*slot
;
1591 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1592 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1595 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1598 struct rmap_iterator iter
;
1601 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1602 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1604 drop_spte(kvm
, sptep
);
1611 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1612 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1615 return kvm_zap_rmapp(kvm
, rmap_head
);
1618 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1619 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1623 struct rmap_iterator iter
;
1626 pte_t
*ptep
= (pte_t
*)data
;
1629 WARN_ON(pte_huge(*ptep
));
1630 new_pfn
= pte_pfn(*ptep
);
1633 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1634 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1635 sptep
, *sptep
, gfn
, level
);
1639 if (pte_write(*ptep
)) {
1640 drop_spte(kvm
, sptep
);
1643 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1644 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1646 new_spte
&= ~PT_WRITABLE_MASK
;
1647 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1649 new_spte
= mark_spte_for_access_track(new_spte
);
1651 mmu_spte_clear_track_bits(sptep
);
1652 mmu_spte_set(sptep
, new_spte
);
1657 kvm_flush_remote_tlbs(kvm
);
1662 struct slot_rmap_walk_iterator
{
1664 struct kvm_memory_slot
*slot
;
1670 /* output fields. */
1672 struct kvm_rmap_head
*rmap
;
1675 /* private field. */
1676 struct kvm_rmap_head
*end_rmap
;
1680 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1682 iterator
->level
= level
;
1683 iterator
->gfn
= iterator
->start_gfn
;
1684 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1685 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1690 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1691 struct kvm_memory_slot
*slot
, int start_level
,
1692 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1694 iterator
->slot
= slot
;
1695 iterator
->start_level
= start_level
;
1696 iterator
->end_level
= end_level
;
1697 iterator
->start_gfn
= start_gfn
;
1698 iterator
->end_gfn
= end_gfn
;
1700 rmap_walk_init_level(iterator
, iterator
->start_level
);
1703 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1705 return !!iterator
->rmap
;
1708 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1710 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1711 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1715 if (++iterator
->level
> iterator
->end_level
) {
1716 iterator
->rmap
= NULL
;
1720 rmap_walk_init_level(iterator
, iterator
->level
);
1723 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1724 _start_gfn, _end_gfn, _iter_) \
1725 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1726 _end_level_, _start_gfn, _end_gfn); \
1727 slot_rmap_walk_okay(_iter_); \
1728 slot_rmap_walk_next(_iter_))
1730 static int kvm_handle_hva_range(struct kvm
*kvm
,
1731 unsigned long start
,
1734 int (*handler
)(struct kvm
*kvm
,
1735 struct kvm_rmap_head
*rmap_head
,
1736 struct kvm_memory_slot
*slot
,
1739 unsigned long data
))
1741 struct kvm_memslots
*slots
;
1742 struct kvm_memory_slot
*memslot
;
1743 struct slot_rmap_walk_iterator iterator
;
1747 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1748 slots
= __kvm_memslots(kvm
, i
);
1749 kvm_for_each_memslot(memslot
, slots
) {
1750 unsigned long hva_start
, hva_end
;
1751 gfn_t gfn_start
, gfn_end
;
1753 hva_start
= max(start
, memslot
->userspace_addr
);
1754 hva_end
= min(end
, memslot
->userspace_addr
+
1755 (memslot
->npages
<< PAGE_SHIFT
));
1756 if (hva_start
>= hva_end
)
1759 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1760 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1762 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1763 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1765 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1766 PT_MAX_HUGEPAGE_LEVEL
,
1767 gfn_start
, gfn_end
- 1,
1769 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1770 iterator
.gfn
, iterator
.level
, data
);
1777 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1779 int (*handler
)(struct kvm
*kvm
,
1780 struct kvm_rmap_head
*rmap_head
,
1781 struct kvm_memory_slot
*slot
,
1782 gfn_t gfn
, int level
,
1783 unsigned long data
))
1785 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1788 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1790 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1793 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1795 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1798 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1800 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1803 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1804 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1808 struct rmap_iterator
uninitialized_var(iter
);
1811 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1812 young
|= mmu_spte_age(sptep
);
1814 trace_kvm_age_page(gfn
, level
, slot
, young
);
1818 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1819 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1820 int level
, unsigned long data
)
1823 struct rmap_iterator iter
;
1825 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1826 if (is_accessed_spte(*sptep
))
1831 #define RMAP_RECYCLE_THRESHOLD 1000
1833 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1835 struct kvm_rmap_head
*rmap_head
;
1836 struct kvm_mmu_page
*sp
;
1838 sp
= page_header(__pa(spte
));
1840 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1842 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1843 kvm_flush_remote_tlbs(vcpu
->kvm
);
1846 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1848 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1851 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1853 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1857 static int is_empty_shadow_page(u64
*spt
)
1862 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1863 if (is_shadow_present_pte(*pos
)) {
1864 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1873 * This value is the sum of all of the kvm instances's
1874 * kvm->arch.n_used_mmu_pages values. We need a global,
1875 * aggregate version in order to make the slab shrinker
1878 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1880 kvm
->arch
.n_used_mmu_pages
+= nr
;
1881 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1884 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1886 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1887 hlist_del(&sp
->hash_link
);
1888 list_del(&sp
->link
);
1889 free_page((unsigned long)sp
->spt
);
1890 if (!sp
->role
.direct
)
1891 free_page((unsigned long)sp
->gfns
);
1892 kmem_cache_free(mmu_page_header_cache
, sp
);
1895 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1897 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1900 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1901 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1906 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1909 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1912 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1915 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1918 mmu_page_remove_parent_pte(sp
, parent_pte
);
1919 mmu_spte_clear_no_track(parent_pte
);
1922 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1924 struct kvm_mmu_page
*sp
;
1926 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1927 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1929 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1930 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1933 * The active_mmu_pages list is the FIFO list, do not move the
1934 * page until it is zapped. kvm_zap_obsolete_pages depends on
1935 * this feature. See the comments in kvm_zap_obsolete_pages().
1937 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1938 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1942 static void mark_unsync(u64
*spte
);
1943 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1946 struct rmap_iterator iter
;
1948 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1953 static void mark_unsync(u64
*spte
)
1955 struct kvm_mmu_page
*sp
;
1958 sp
= page_header(__pa(spte
));
1959 index
= spte
- sp
->spt
;
1960 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1962 if (sp
->unsync_children
++)
1964 kvm_mmu_mark_parents_unsync(sp
);
1967 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1968 struct kvm_mmu_page
*sp
)
1973 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1977 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1978 struct kvm_mmu_page
*sp
, u64
*spte
,
1984 #define KVM_PAGE_ARRAY_NR 16
1986 struct kvm_mmu_pages
{
1987 struct mmu_page_and_offset
{
1988 struct kvm_mmu_page
*sp
;
1990 } page
[KVM_PAGE_ARRAY_NR
];
1994 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
2000 for (i
=0; i
< pvec
->nr
; i
++)
2001 if (pvec
->page
[i
].sp
== sp
)
2004 pvec
->page
[pvec
->nr
].sp
= sp
;
2005 pvec
->page
[pvec
->nr
].idx
= idx
;
2007 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
2010 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
2012 --sp
->unsync_children
;
2013 WARN_ON((int)sp
->unsync_children
< 0);
2014 __clear_bit(idx
, sp
->unsync_child_bitmap
);
2017 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2018 struct kvm_mmu_pages
*pvec
)
2020 int i
, ret
, nr_unsync_leaf
= 0;
2022 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
2023 struct kvm_mmu_page
*child
;
2024 u64 ent
= sp
->spt
[i
];
2026 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
2027 clear_unsync_child_bit(sp
, i
);
2031 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
2033 if (child
->unsync_children
) {
2034 if (mmu_pages_add(pvec
, child
, i
))
2037 ret
= __mmu_unsync_walk(child
, pvec
);
2039 clear_unsync_child_bit(sp
, i
);
2041 } else if (ret
> 0) {
2042 nr_unsync_leaf
+= ret
;
2045 } else if (child
->unsync
) {
2047 if (mmu_pages_add(pvec
, child
, i
))
2050 clear_unsync_child_bit(sp
, i
);
2053 return nr_unsync_leaf
;
2056 #define INVALID_INDEX (-1)
2058 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2059 struct kvm_mmu_pages
*pvec
)
2062 if (!sp
->unsync_children
)
2065 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2066 return __mmu_unsync_walk(sp
, pvec
);
2069 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2071 WARN_ON(!sp
->unsync
);
2072 trace_kvm_mmu_sync_page(sp
);
2074 --kvm
->stat
.mmu_unsync
;
2077 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2078 struct list_head
*invalid_list
);
2079 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2080 struct list_head
*invalid_list
);
2083 * NOTE: we should pay more attention on the zapped-obsolete page
2084 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2085 * since it has been deleted from active_mmu_pages but still can be found
2088 * for_each_valid_sp() has skipped that kind of pages.
2090 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2091 hlist_for_each_entry(_sp, \
2092 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2093 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2096 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2097 for_each_valid_sp(_kvm, _sp, _gfn) \
2098 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2100 /* @sp->gfn should be write-protected at the call site */
2101 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2102 struct list_head
*invalid_list
)
2104 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
2105 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2109 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
2110 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2117 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2118 struct list_head
*invalid_list
,
2119 bool remote_flush
, bool local_flush
)
2121 if (!list_empty(invalid_list
)) {
2122 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
2127 kvm_flush_remote_tlbs(vcpu
->kvm
);
2128 else if (local_flush
)
2129 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2132 #ifdef CONFIG_KVM_MMU_AUDIT
2133 #include "mmu_audit.c"
2135 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2136 static void mmu_audit_disable(void) { }
2139 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2141 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2144 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2145 struct list_head
*invalid_list
)
2147 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2148 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2151 /* @gfn should be write-protected at the call site */
2152 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2153 struct list_head
*invalid_list
)
2155 struct kvm_mmu_page
*s
;
2158 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2162 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2163 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2169 struct mmu_page_path
{
2170 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
2171 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
2174 #define for_each_sp(pvec, sp, parents, i) \
2175 for (i = mmu_pages_first(&pvec, &parents); \
2176 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2177 i = mmu_pages_next(&pvec, &parents, i))
2179 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2180 struct mmu_page_path
*parents
,
2185 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2186 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2187 unsigned idx
= pvec
->page
[n
].idx
;
2188 int level
= sp
->role
.level
;
2190 parents
->idx
[level
-1] = idx
;
2191 if (level
== PT_PAGE_TABLE_LEVEL
)
2194 parents
->parent
[level
-2] = sp
;
2200 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2201 struct mmu_page_path
*parents
)
2203 struct kvm_mmu_page
*sp
;
2209 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2211 sp
= pvec
->page
[0].sp
;
2212 level
= sp
->role
.level
;
2213 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2215 parents
->parent
[level
-2] = sp
;
2217 /* Also set up a sentinel. Further entries in pvec are all
2218 * children of sp, so this element is never overwritten.
2220 parents
->parent
[level
-1] = NULL
;
2221 return mmu_pages_next(pvec
, parents
, 0);
2224 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2226 struct kvm_mmu_page
*sp
;
2227 unsigned int level
= 0;
2230 unsigned int idx
= parents
->idx
[level
];
2231 sp
= parents
->parent
[level
];
2235 WARN_ON(idx
== INVALID_INDEX
);
2236 clear_unsync_child_bit(sp
, idx
);
2238 } while (!sp
->unsync_children
);
2241 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2242 struct kvm_mmu_page
*parent
)
2245 struct kvm_mmu_page
*sp
;
2246 struct mmu_page_path parents
;
2247 struct kvm_mmu_pages pages
;
2248 LIST_HEAD(invalid_list
);
2251 while (mmu_unsync_walk(parent
, &pages
)) {
2252 bool protected = false;
2254 for_each_sp(pages
, sp
, parents
, i
)
2255 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2258 kvm_flush_remote_tlbs(vcpu
->kvm
);
2262 for_each_sp(pages
, sp
, parents
, i
) {
2263 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2264 mmu_pages_clear_parents(&parents
);
2266 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2267 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2268 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2273 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2276 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2278 atomic_set(&sp
->write_flooding_count
, 0);
2281 static void clear_sp_write_flooding_count(u64
*spte
)
2283 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2285 __clear_sp_write_flooding_count(sp
);
2288 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2295 union kvm_mmu_page_role role
;
2297 struct kvm_mmu_page
*sp
;
2298 bool need_sync
= false;
2301 LIST_HEAD(invalid_list
);
2303 role
= vcpu
->arch
.mmu
.base_role
;
2305 role
.direct
= direct
;
2308 role
.access
= access
;
2309 if (!vcpu
->arch
.mmu
.direct_map
2310 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2311 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2312 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2313 role
.quadrant
= quadrant
;
2315 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2316 if (sp
->gfn
!= gfn
) {
2321 if (!need_sync
&& sp
->unsync
)
2324 if (sp
->role
.word
!= role
.word
)
2328 /* The page is good, but __kvm_sync_page might still end
2329 * up zapping it. If so, break in order to rebuild it.
2331 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2334 WARN_ON(!list_empty(&invalid_list
));
2335 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2338 if (sp
->unsync_children
)
2339 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2341 __clear_sp_write_flooding_count(sp
);
2342 trace_kvm_mmu_get_page(sp
, false);
2346 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2348 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2352 hlist_add_head(&sp
->hash_link
,
2353 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2356 * we should do write protection before syncing pages
2357 * otherwise the content of the synced shadow page may
2358 * be inconsistent with guest page table.
2360 account_shadowed(vcpu
->kvm
, sp
);
2361 if (level
== PT_PAGE_TABLE_LEVEL
&&
2362 rmap_write_protect(vcpu
, gfn
))
2363 kvm_flush_remote_tlbs(vcpu
->kvm
);
2365 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2366 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2368 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2369 clear_page(sp
->spt
);
2370 trace_kvm_mmu_get_page(sp
, true);
2372 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2374 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2375 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2379 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2380 struct kvm_vcpu
*vcpu
, u64 addr
)
2382 iterator
->addr
= addr
;
2383 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2384 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2386 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2387 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_4LEVEL
&&
2388 !vcpu
->arch
.mmu
.direct_map
)
2391 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2392 iterator
->shadow_addr
2393 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2394 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2396 if (!iterator
->shadow_addr
)
2397 iterator
->level
= 0;
2401 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2403 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2406 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2407 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2411 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2414 if (is_last_spte(spte
, iterator
->level
)) {
2415 iterator
->level
= 0;
2419 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2423 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2425 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2428 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2429 struct kvm_mmu_page
*sp
)
2433 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2435 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2436 shadow_user_mask
| shadow_x_mask
;
2438 if (sp_ad_disabled(sp
))
2439 spte
|= shadow_acc_track_value
;
2441 spte
|= shadow_accessed_mask
;
2443 mmu_spte_set(sptep
, spte
);
2445 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2447 if (sp
->unsync_children
|| sp
->unsync
)
2451 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2452 unsigned direct_access
)
2454 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2455 struct kvm_mmu_page
*child
;
2458 * For the direct sp, if the guest pte's dirty bit
2459 * changed form clean to dirty, it will corrupt the
2460 * sp's access: allow writable in the read-only sp,
2461 * so we should update the spte at this point to get
2462 * a new sp with the correct access.
2464 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2465 if (child
->role
.access
== direct_access
)
2468 drop_parent_pte(child
, sptep
);
2469 kvm_flush_remote_tlbs(vcpu
->kvm
);
2473 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2477 struct kvm_mmu_page
*child
;
2480 if (is_shadow_present_pte(pte
)) {
2481 if (is_last_spte(pte
, sp
->role
.level
)) {
2482 drop_spte(kvm
, spte
);
2483 if (is_large_pte(pte
))
2486 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2487 drop_parent_pte(child
, spte
);
2492 if (is_mmio_spte(pte
))
2493 mmu_spte_clear_no_track(spte
);
2498 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2499 struct kvm_mmu_page
*sp
)
2503 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2504 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2507 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2510 struct rmap_iterator iter
;
2512 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2513 drop_parent_pte(sp
, sptep
);
2516 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2517 struct kvm_mmu_page
*parent
,
2518 struct list_head
*invalid_list
)
2521 struct mmu_page_path parents
;
2522 struct kvm_mmu_pages pages
;
2524 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2527 while (mmu_unsync_walk(parent
, &pages
)) {
2528 struct kvm_mmu_page
*sp
;
2530 for_each_sp(pages
, sp
, parents
, i
) {
2531 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2532 mmu_pages_clear_parents(&parents
);
2540 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2541 struct list_head
*invalid_list
)
2545 trace_kvm_mmu_prepare_zap_page(sp
);
2546 ++kvm
->stat
.mmu_shadow_zapped
;
2547 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2548 kvm_mmu_page_unlink_children(kvm
, sp
);
2549 kvm_mmu_unlink_parents(kvm
, sp
);
2551 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2552 unaccount_shadowed(kvm
, sp
);
2555 kvm_unlink_unsync_page(kvm
, sp
);
2556 if (!sp
->root_count
) {
2559 list_move(&sp
->link
, invalid_list
);
2560 kvm_mod_used_mmu_pages(kvm
, -1);
2562 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2565 * The obsolete pages can not be used on any vcpus.
2566 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2568 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2569 kvm_reload_remote_mmus(kvm
);
2572 sp
->role
.invalid
= 1;
2576 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2577 struct list_head
*invalid_list
)
2579 struct kvm_mmu_page
*sp
, *nsp
;
2581 if (list_empty(invalid_list
))
2585 * We need to make sure everyone sees our modifications to
2586 * the page tables and see changes to vcpu->mode here. The barrier
2587 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2588 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2590 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2591 * guest mode and/or lockless shadow page table walks.
2593 kvm_flush_remote_tlbs(kvm
);
2595 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2596 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2597 kvm_mmu_free_page(sp
);
2601 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2602 struct list_head
*invalid_list
)
2604 struct kvm_mmu_page
*sp
;
2606 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2609 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2610 struct kvm_mmu_page
, link
);
2611 return kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2615 * Changing the number of mmu pages allocated to the vm
2616 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2618 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2620 LIST_HEAD(invalid_list
);
2622 spin_lock(&kvm
->mmu_lock
);
2624 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2625 /* Need to free some mmu pages to achieve the goal. */
2626 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2627 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2630 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2631 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2634 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2636 spin_unlock(&kvm
->mmu_lock
);
2639 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2641 struct kvm_mmu_page
*sp
;
2642 LIST_HEAD(invalid_list
);
2645 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2647 spin_lock(&kvm
->mmu_lock
);
2648 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2649 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2652 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2654 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2655 spin_unlock(&kvm
->mmu_lock
);
2659 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2661 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2663 trace_kvm_mmu_unsync_page(sp
);
2664 ++vcpu
->kvm
->stat
.mmu_unsync
;
2667 kvm_mmu_mark_parents_unsync(sp
);
2670 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2673 struct kvm_mmu_page
*sp
;
2675 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2678 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2685 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2686 kvm_unsync_page(vcpu
, sp
);
2692 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2695 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2700 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2701 unsigned pte_access
, int level
,
2702 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2703 bool can_unsync
, bool host_writable
)
2707 struct kvm_mmu_page
*sp
;
2709 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2712 sp
= page_header(__pa(sptep
));
2713 if (sp_ad_disabled(sp
))
2714 spte
|= shadow_acc_track_value
;
2717 * For the EPT case, shadow_present_mask is 0 if hardware
2718 * supports exec-only page table entries. In that case,
2719 * ACC_USER_MASK and shadow_user_mask are used to represent
2720 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2722 spte
|= shadow_present_mask
;
2724 spte
|= spte_shadow_accessed_mask(spte
);
2726 if (pte_access
& ACC_EXEC_MASK
)
2727 spte
|= shadow_x_mask
;
2729 spte
|= shadow_nx_mask
;
2731 if (pte_access
& ACC_USER_MASK
)
2732 spte
|= shadow_user_mask
;
2734 if (level
> PT_PAGE_TABLE_LEVEL
)
2735 spte
|= PT_PAGE_SIZE_MASK
;
2737 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2738 kvm_is_mmio_pfn(pfn
));
2741 spte
|= SPTE_HOST_WRITEABLE
;
2743 pte_access
&= ~ACC_WRITE_MASK
;
2745 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2747 if (pte_access
& ACC_WRITE_MASK
) {
2750 * Other vcpu creates new sp in the window between
2751 * mapping_level() and acquiring mmu-lock. We can
2752 * allow guest to retry the access, the mapping can
2753 * be fixed if guest refault.
2755 if (level
> PT_PAGE_TABLE_LEVEL
&&
2756 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2759 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2762 * Optimization: for pte sync, if spte was writable the hash
2763 * lookup is unnecessary (and expensive). Write protection
2764 * is responsibility of mmu_get_page / kvm_sync_page.
2765 * Same reasoning can be applied to dirty page accounting.
2767 if (!can_unsync
&& is_writable_pte(*sptep
))
2770 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2771 pgprintk("%s: found shadow page for %llx, marking ro\n",
2774 pte_access
&= ~ACC_WRITE_MASK
;
2775 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2779 if (pte_access
& ACC_WRITE_MASK
) {
2780 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2781 spte
|= spte_shadow_dirty_mask(spte
);
2785 spte
= mark_spte_for_access_track(spte
);
2788 if (mmu_spte_update(sptep
, spte
))
2789 kvm_flush_remote_tlbs(vcpu
->kvm
);
2794 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2795 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2796 bool speculative
, bool host_writable
)
2798 int was_rmapped
= 0;
2800 bool emulate
= false;
2802 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2803 *sptep
, write_fault
, gfn
);
2805 if (is_shadow_present_pte(*sptep
)) {
2807 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2808 * the parent of the now unreachable PTE.
2810 if (level
> PT_PAGE_TABLE_LEVEL
&&
2811 !is_large_pte(*sptep
)) {
2812 struct kvm_mmu_page
*child
;
2815 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2816 drop_parent_pte(child
, sptep
);
2817 kvm_flush_remote_tlbs(vcpu
->kvm
);
2818 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2819 pgprintk("hfn old %llx new %llx\n",
2820 spte_to_pfn(*sptep
), pfn
);
2821 drop_spte(vcpu
->kvm
, sptep
);
2822 kvm_flush_remote_tlbs(vcpu
->kvm
);
2827 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2828 true, host_writable
)) {
2831 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2834 if (unlikely(is_mmio_spte(*sptep
)))
2837 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2838 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2839 is_large_pte(*sptep
)? "2MB" : "4kB",
2840 *sptep
& PT_WRITABLE_MASK
? "RW" : "R", gfn
,
2842 if (!was_rmapped
&& is_large_pte(*sptep
))
2843 ++vcpu
->kvm
->stat
.lpages
;
2845 if (is_shadow_present_pte(*sptep
)) {
2847 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2848 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2849 rmap_recycle(vcpu
, sptep
, gfn
);
2853 kvm_release_pfn_clean(pfn
);
2858 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2861 struct kvm_memory_slot
*slot
;
2863 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2865 return KVM_PFN_ERR_FAULT
;
2867 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2870 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2871 struct kvm_mmu_page
*sp
,
2872 u64
*start
, u64
*end
)
2874 struct page
*pages
[PTE_PREFETCH_NUM
];
2875 struct kvm_memory_slot
*slot
;
2876 unsigned access
= sp
->role
.access
;
2880 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2881 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2885 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2889 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2890 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2891 page_to_pfn(pages
[i
]), true, true);
2896 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2897 struct kvm_mmu_page
*sp
, u64
*sptep
)
2899 u64
*spte
, *start
= NULL
;
2902 WARN_ON(!sp
->role
.direct
);
2904 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2907 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2908 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2911 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2919 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2921 struct kvm_mmu_page
*sp
;
2923 sp
= page_header(__pa(sptep
));
2926 * Without accessed bits, there's no way to distinguish between
2927 * actually accessed translations and prefetched, so disable pte
2928 * prefetch if accessed bits aren't available.
2930 if (sp_ad_disabled(sp
))
2933 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2936 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2939 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2940 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2942 struct kvm_shadow_walk_iterator iterator
;
2943 struct kvm_mmu_page
*sp
;
2947 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2950 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2951 if (iterator
.level
== level
) {
2952 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2953 write
, level
, gfn
, pfn
, prefault
,
2955 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2956 ++vcpu
->stat
.pf_fixed
;
2960 drop_large_spte(vcpu
, iterator
.sptep
);
2961 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2962 u64 base_addr
= iterator
.addr
;
2964 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2965 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2966 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2967 iterator
.level
- 1, 1, ACC_ALL
);
2969 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2975 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2979 info
.si_signo
= SIGBUS
;
2981 info
.si_code
= BUS_MCEERR_AR
;
2982 info
.si_addr
= (void __user
*)address
;
2983 info
.si_addr_lsb
= PAGE_SHIFT
;
2985 send_sig_info(SIGBUS
, &info
, tsk
);
2988 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2991 * Do not cache the mmio info caused by writing the readonly gfn
2992 * into the spte otherwise read access on readonly gfn also can
2993 * caused mmio page fault and treat it as mmio access.
2994 * Return 1 to tell kvm to emulate it.
2996 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2999 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3000 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3007 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
3008 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
3011 kvm_pfn_t pfn
= *pfnp
;
3013 int level
= *levelp
;
3016 * Check if it's a transparent hugepage. If this would be an
3017 * hugetlbfs page, level wouldn't be set to
3018 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3021 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
3022 level
== PT_PAGE_TABLE_LEVEL
&&
3023 PageTransCompoundMap(pfn_to_page(pfn
)) &&
3024 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
3027 * mmu_notifier_retry was successful and we hold the
3028 * mmu_lock here, so the pmd can't become splitting
3029 * from under us, and in turn
3030 * __split_huge_page_refcount() can't run from under
3031 * us and we can safely transfer the refcount from
3032 * PG_tail to PG_head as we switch the pfn to tail to
3035 *levelp
= level
= PT_DIRECTORY_LEVEL
;
3036 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
3037 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
3041 kvm_release_pfn_clean(pfn
);
3049 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3050 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
3052 /* The pfn is invalid, report the error! */
3053 if (unlikely(is_error_pfn(pfn
))) {
3054 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3058 if (unlikely(is_noslot_pfn(pfn
)))
3059 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
3064 static bool page_fault_can_be_fast(u32 error_code
)
3067 * Do not fix the mmio spte with invalid generation number which
3068 * need to be updated by slow page fault path.
3070 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3073 /* See if the page fault is due to an NX violation */
3074 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3075 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3079 * #PF can be fast if:
3080 * 1. The shadow page table entry is not present, which could mean that
3081 * the fault is potentially caused by access tracking (if enabled).
3082 * 2. The shadow page table entry is present and the fault
3083 * is caused by write-protect, that means we just need change the W
3084 * bit of the spte which can be done out of mmu-lock.
3086 * However, if access tracking is disabled we know that a non-present
3087 * page must be a genuine page fault where we have to create a new SPTE.
3088 * So, if access tracking is disabled, we return true only for write
3089 * accesses to a present page.
3092 return shadow_acc_track_mask
!= 0 ||
3093 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3094 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3098 * Returns true if the SPTE was fixed successfully. Otherwise,
3099 * someone else modified the SPTE from its original value.
3102 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3103 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3107 WARN_ON(!sp
->role
.direct
);
3110 * Theoretically we could also set dirty bit (and flush TLB) here in
3111 * order to eliminate unnecessary PML logging. See comments in
3112 * set_spte. But fast_page_fault is very unlikely to happen with PML
3113 * enabled, so we do not do this. This might result in the same GPA
3114 * to be logged in PML buffer again when the write really happens, and
3115 * eventually to be called by mark_page_dirty twice. But it's also no
3116 * harm. This also avoids the TLB flush needed after setting dirty bit
3117 * so non-PML cases won't be impacted.
3119 * Compare with set_spte where instead shadow_dirty_mask is set.
3121 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3124 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3126 * The gfn of direct spte is stable since it is
3127 * calculated by sp->gfn.
3129 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3130 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3136 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3138 if (fault_err_code
& PFERR_FETCH_MASK
)
3139 return is_executable_pte(spte
);
3141 if (fault_err_code
& PFERR_WRITE_MASK
)
3142 return is_writable_pte(spte
);
3144 /* Fault was on Read access */
3145 return spte
& PT_PRESENT_MASK
;
3150 * - true: let the vcpu to access on the same address again.
3151 * - false: let the real page fault path to fix it.
3153 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
3156 struct kvm_shadow_walk_iterator iterator
;
3157 struct kvm_mmu_page
*sp
;
3158 bool fault_handled
= false;
3160 uint retry_count
= 0;
3162 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3165 if (!page_fault_can_be_fast(error_code
))
3168 walk_shadow_page_lockless_begin(vcpu
);
3173 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
3174 if (!is_shadow_present_pte(spte
) ||
3175 iterator
.level
< level
)
3178 sp
= page_header(__pa(iterator
.sptep
));
3179 if (!is_last_spte(spte
, sp
->role
.level
))
3183 * Check whether the memory access that caused the fault would
3184 * still cause it if it were to be performed right now. If not,
3185 * then this is a spurious fault caused by TLB lazily flushed,
3186 * or some other CPU has already fixed the PTE after the
3187 * current CPU took the fault.
3189 * Need not check the access of upper level table entries since
3190 * they are always ACC_ALL.
3192 if (is_access_allowed(error_code
, spte
)) {
3193 fault_handled
= true;
3199 if (is_access_track_spte(spte
))
3200 new_spte
= restore_acc_track_spte(new_spte
);
3203 * Currently, to simplify the code, write-protection can
3204 * be removed in the fast path only if the SPTE was
3205 * write-protected for dirty-logging or access tracking.
3207 if ((error_code
& PFERR_WRITE_MASK
) &&
3208 spte_can_locklessly_be_made_writable(spte
))
3210 new_spte
|= PT_WRITABLE_MASK
;
3213 * Do not fix write-permission on the large spte. Since
3214 * we only dirty the first page into the dirty-bitmap in
3215 * fast_pf_fix_direct_spte(), other pages are missed
3216 * if its slot has dirty logging enabled.
3218 * Instead, we let the slow page fault path create a
3219 * normal spte to fix the access.
3221 * See the comments in kvm_arch_commit_memory_region().
3223 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3227 /* Verify that the fault can be handled in the fast path */
3228 if (new_spte
== spte
||
3229 !is_access_allowed(error_code
, new_spte
))
3233 * Currently, fast page fault only works for direct mapping
3234 * since the gfn is not stable for indirect shadow page. See
3235 * Documentation/virtual/kvm/locking.txt to get more detail.
3237 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3238 iterator
.sptep
, spte
,
3243 if (++retry_count
> 4) {
3244 printk_once(KERN_WARNING
3245 "kvm: Fast #PF retrying more than 4 times.\n");
3251 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3252 spte
, fault_handled
);
3253 walk_shadow_page_lockless_end(vcpu
);
3255 return fault_handled
;
3258 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3259 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3260 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3262 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3263 gfn_t gfn
, bool prefault
)
3267 bool force_pt_level
= false;
3269 unsigned long mmu_seq
;
3270 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3272 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3273 if (likely(!force_pt_level
)) {
3275 * This path builds a PAE pagetable - so we can map
3276 * 2mb pages at maximum. Therefore check if the level
3277 * is larger than that.
3279 if (level
> PT_DIRECTORY_LEVEL
)
3280 level
= PT_DIRECTORY_LEVEL
;
3282 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3285 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3288 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3291 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3294 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3297 spin_lock(&vcpu
->kvm
->mmu_lock
);
3298 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3300 if (make_mmu_pages_available(vcpu
) < 0)
3302 if (likely(!force_pt_level
))
3303 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3304 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3305 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3310 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3311 kvm_release_pfn_clean(pfn
);
3316 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3319 struct kvm_mmu_page
*sp
;
3320 LIST_HEAD(invalid_list
);
3322 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3325 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3326 (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
||
3327 vcpu
->arch
.mmu
.direct_map
)) {
3328 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3330 spin_lock(&vcpu
->kvm
->mmu_lock
);
3331 sp
= page_header(root
);
3333 if (!sp
->root_count
&& sp
->role
.invalid
) {
3334 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3335 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3337 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3338 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3342 spin_lock(&vcpu
->kvm
->mmu_lock
);
3343 for (i
= 0; i
< 4; ++i
) {
3344 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3347 root
&= PT64_BASE_ADDR_MASK
;
3348 sp
= page_header(root
);
3350 if (!sp
->root_count
&& sp
->role
.invalid
)
3351 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3354 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3356 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3357 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3358 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3361 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3365 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3366 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3373 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3375 struct kvm_mmu_page
*sp
;
3378 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3379 spin_lock(&vcpu
->kvm
->mmu_lock
);
3380 if(make_mmu_pages_available(vcpu
) < 0) {
3381 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3384 sp
= kvm_mmu_get_page(vcpu
, 0, 0,
3385 vcpu
->arch
.mmu
.shadow_root_level
, 1, ACC_ALL
);
3387 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3388 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3389 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3390 for (i
= 0; i
< 4; ++i
) {
3391 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3393 MMU_WARN_ON(VALID_PAGE(root
));
3394 spin_lock(&vcpu
->kvm
->mmu_lock
);
3395 if (make_mmu_pages_available(vcpu
) < 0) {
3396 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3399 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3400 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3401 root
= __pa(sp
->spt
);
3403 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3404 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3406 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3413 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3415 struct kvm_mmu_page
*sp
;
3420 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3422 if (mmu_check_root(vcpu
, root_gfn
))
3426 * Do we shadow a long mode page table? If so we need to
3427 * write-protect the guests page table root.
3429 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3430 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3432 MMU_WARN_ON(VALID_PAGE(root
));
3434 spin_lock(&vcpu
->kvm
->mmu_lock
);
3435 if (make_mmu_pages_available(vcpu
) < 0) {
3436 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3439 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0,
3440 vcpu
->arch
.mmu
.shadow_root_level
, 0, ACC_ALL
);
3441 root
= __pa(sp
->spt
);
3443 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3444 vcpu
->arch
.mmu
.root_hpa
= root
;
3449 * We shadow a 32 bit page table. This may be a legacy 2-level
3450 * or a PAE 3-level page table. In either case we need to be aware that
3451 * the shadow page table may be a PAE or a long mode page table.
3453 pm_mask
= PT_PRESENT_MASK
;
3454 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
)
3455 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3457 for (i
= 0; i
< 4; ++i
) {
3458 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3460 MMU_WARN_ON(VALID_PAGE(root
));
3461 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3462 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3463 if (!(pdptr
& PT_PRESENT_MASK
)) {
3464 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3467 root_gfn
= pdptr
>> PAGE_SHIFT
;
3468 if (mmu_check_root(vcpu
, root_gfn
))
3471 spin_lock(&vcpu
->kvm
->mmu_lock
);
3472 if (make_mmu_pages_available(vcpu
) < 0) {
3473 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3476 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3478 root
= __pa(sp
->spt
);
3480 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3482 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3484 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3487 * If we shadow a 32 bit page table with a long mode page
3488 * table we enter this path.
3490 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
) {
3491 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3493 * The additional page necessary for this is only
3494 * allocated on demand.
3499 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3500 if (lm_root
== NULL
)
3503 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3505 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3508 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3514 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3516 if (vcpu
->arch
.mmu
.direct_map
)
3517 return mmu_alloc_direct_roots(vcpu
);
3519 return mmu_alloc_shadow_roots(vcpu
);
3522 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3525 struct kvm_mmu_page
*sp
;
3527 if (vcpu
->arch
.mmu
.direct_map
)
3530 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3533 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3534 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3535 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3536 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3537 sp
= page_header(root
);
3538 mmu_sync_children(vcpu
, sp
);
3539 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3542 for (i
= 0; i
< 4; ++i
) {
3543 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3545 if (root
&& VALID_PAGE(root
)) {
3546 root
&= PT64_BASE_ADDR_MASK
;
3547 sp
= page_header(root
);
3548 mmu_sync_children(vcpu
, sp
);
3551 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3554 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3556 spin_lock(&vcpu
->kvm
->mmu_lock
);
3557 mmu_sync_roots(vcpu
);
3558 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3560 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3562 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3563 u32 access
, struct x86_exception
*exception
)
3566 exception
->error_code
= 0;
3570 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3572 struct x86_exception
*exception
)
3575 exception
->error_code
= 0;
3576 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3580 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3582 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3584 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3585 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3588 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3590 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3593 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3595 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3598 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3601 * A nested guest cannot use the MMIO cache if it is using nested
3602 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3604 if (mmu_is_nested(vcpu
))
3608 return vcpu_match_mmio_gpa(vcpu
, addr
);
3610 return vcpu_match_mmio_gva(vcpu
, addr
);
3613 /* return true if reserved bit is detected on spte. */
3615 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3617 struct kvm_shadow_walk_iterator iterator
;
3618 u64 sptes
[PT64_ROOT_MAX_LEVEL
], spte
= 0ull;
3620 bool reserved
= false;
3622 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3625 walk_shadow_page_lockless_begin(vcpu
);
3627 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3628 leaf
= root
= iterator
.level
;
3629 shadow_walk_okay(&iterator
);
3630 __shadow_walk_next(&iterator
, spte
)) {
3631 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3633 sptes
[leaf
- 1] = spte
;
3636 if (!is_shadow_present_pte(spte
))
3639 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3643 walk_shadow_page_lockless_end(vcpu
);
3646 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3648 while (root
> leaf
) {
3649 pr_err("------ spte 0x%llx level %d.\n",
3650 sptes
[root
- 1], root
);
3660 * Return values of handle_mmio_page_fault:
3661 * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
3663 * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
3664 * fault path update the mmio spte.
3665 * RET_MMIO_PF_RETRY: let CPU fault again on the address.
3666 * RET_MMIO_PF_BUG: a bug was detected (and a WARN was printed).
3669 RET_MMIO_PF_EMULATE
= 1,
3670 RET_MMIO_PF_INVALID
= 2,
3671 RET_MMIO_PF_RETRY
= 0,
3672 RET_MMIO_PF_BUG
= -1
3675 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3680 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3681 return RET_MMIO_PF_EMULATE
;
3683 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3684 if (WARN_ON(reserved
))
3685 return RET_MMIO_PF_BUG
;
3687 if (is_mmio_spte(spte
)) {
3688 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3689 unsigned access
= get_mmio_spte_access(spte
);
3691 if (!check_mmio_spte(vcpu
, spte
))
3692 return RET_MMIO_PF_INVALID
;
3697 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3698 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3699 return RET_MMIO_PF_EMULATE
;
3703 * If the page table is zapped by other cpus, let CPU fault again on
3706 return RET_MMIO_PF_RETRY
;
3708 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3710 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3711 u32 error_code
, gfn_t gfn
)
3713 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3716 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3717 !(error_code
& PFERR_WRITE_MASK
))
3721 * guest is writing the page which is write tracked which can
3722 * not be fixed by page fault handler.
3724 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3730 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3732 struct kvm_shadow_walk_iterator iterator
;
3735 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3738 walk_shadow_page_lockless_begin(vcpu
);
3739 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3740 clear_sp_write_flooding_count(iterator
.sptep
);
3741 if (!is_shadow_present_pte(spte
))
3744 walk_shadow_page_lockless_end(vcpu
);
3747 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3748 u32 error_code
, bool prefault
)
3750 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3753 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3755 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3758 r
= mmu_topup_memory_caches(vcpu
);
3762 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3765 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3766 error_code
, gfn
, prefault
);
3769 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3771 struct kvm_arch_async_pf arch
;
3773 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3775 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3776 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3778 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3781 bool kvm_can_do_async_pf(struct kvm_vcpu
*vcpu
)
3783 if (unlikely(!lapic_in_kernel(vcpu
) ||
3784 kvm_event_needs_reinjection(vcpu
)))
3787 if (!vcpu
->arch
.apf
.delivery_as_pf_vmexit
&& is_guest_mode(vcpu
))
3790 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3793 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3794 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3796 struct kvm_memory_slot
*slot
;
3799 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3801 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3803 return false; /* *pfn has correct page already */
3805 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3806 trace_kvm_try_async_get_page(gva
, gfn
);
3807 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3808 trace_kvm_async_pf_doublefault(gva
, gfn
);
3809 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3811 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3815 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3819 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3820 u64 fault_address
, char *insn
, int insn_len
,
3821 bool need_unprotect
)
3825 switch (vcpu
->arch
.apf
.host_apf_reason
) {
3827 trace_kvm_page_fault(fault_address
, error_code
);
3829 if (need_unprotect
&& kvm_event_needs_reinjection(vcpu
))
3830 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3831 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3834 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
3835 vcpu
->arch
.apf
.host_apf_reason
= 0;
3836 local_irq_disable();
3837 kvm_async_pf_task_wait(fault_address
);
3840 case KVM_PV_REASON_PAGE_READY
:
3841 vcpu
->arch
.apf
.host_apf_reason
= 0;
3842 local_irq_disable();
3843 kvm_async_pf_task_wake(fault_address
);
3849 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3852 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3854 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3856 gfn
&= ~(page_num
- 1);
3858 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3861 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3867 bool force_pt_level
;
3868 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3869 unsigned long mmu_seq
;
3870 int write
= error_code
& PFERR_WRITE_MASK
;
3873 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3875 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3878 r
= mmu_topup_memory_caches(vcpu
);
3882 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3883 PT_DIRECTORY_LEVEL
);
3884 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3885 if (likely(!force_pt_level
)) {
3886 if (level
> PT_DIRECTORY_LEVEL
&&
3887 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3888 level
= PT_DIRECTORY_LEVEL
;
3889 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3892 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3895 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3898 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3901 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3904 spin_lock(&vcpu
->kvm
->mmu_lock
);
3905 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3907 if (make_mmu_pages_available(vcpu
) < 0)
3909 if (likely(!force_pt_level
))
3910 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3911 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3912 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3917 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3918 kvm_release_pfn_clean(pfn
);
3922 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3923 struct kvm_mmu
*context
)
3925 context
->page_fault
= nonpaging_page_fault
;
3926 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3927 context
->sync_page
= nonpaging_sync_page
;
3928 context
->invlpg
= nonpaging_invlpg
;
3929 context
->update_pte
= nonpaging_update_pte
;
3930 context
->root_level
= 0;
3931 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3932 context
->root_hpa
= INVALID_PAGE
;
3933 context
->direct_map
= true;
3934 context
->nx
= false;
3937 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3939 mmu_free_roots(vcpu
);
3942 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3944 return kvm_read_cr3(vcpu
);
3947 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3948 struct x86_exception
*fault
)
3950 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3953 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3954 unsigned access
, int *nr_present
)
3956 if (unlikely(is_mmio_spte(*sptep
))) {
3957 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3958 mmu_spte_clear_no_track(sptep
);
3963 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3970 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3971 unsigned level
, unsigned gpte
)
3974 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3975 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3976 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3978 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3981 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3982 * If it is clear, there are no large pages at this level, so clear
3983 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3985 gpte
&= level
- mmu
->last_nonleaf_level
;
3987 return gpte
& PT_PAGE_SIZE_MASK
;
3990 #define PTTYPE_EPT 18 /* arbitrary */
3991 #define PTTYPE PTTYPE_EPT
3992 #include "paging_tmpl.h"
3996 #include "paging_tmpl.h"
4000 #include "paging_tmpl.h"
4004 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4005 struct rsvd_bits_validate
*rsvd_check
,
4006 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
4009 u64 exb_bit_rsvd
= 0;
4010 u64 gbpages_bit_rsvd
= 0;
4011 u64 nonleaf_bit8_rsvd
= 0;
4013 rsvd_check
->bad_mt_xwr
= 0;
4016 exb_bit_rsvd
= rsvd_bits(63, 63);
4018 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4021 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4022 * leaf entries) on AMD CPUs only.
4025 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4028 case PT32_ROOT_LEVEL
:
4029 /* no rsvd bits for 2 level 4K page table entries */
4030 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4031 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4032 rsvd_check
->rsvd_bits_mask
[1][0] =
4033 rsvd_check
->rsvd_bits_mask
[0][0];
4036 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4040 if (is_cpuid_PSE36())
4041 /* 36bits PSE 4MB page */
4042 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4044 /* 32 bits PSE 4MB page */
4045 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4047 case PT32E_ROOT_LEVEL
:
4048 rsvd_check
->rsvd_bits_mask
[0][2] =
4049 rsvd_bits(maxphyaddr
, 63) |
4050 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4051 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4052 rsvd_bits(maxphyaddr
, 62); /* PDE */
4053 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4054 rsvd_bits(maxphyaddr
, 62); /* PTE */
4055 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4056 rsvd_bits(maxphyaddr
, 62) |
4057 rsvd_bits(13, 20); /* large page */
4058 rsvd_check
->rsvd_bits_mask
[1][0] =
4059 rsvd_check
->rsvd_bits_mask
[0][0];
4061 case PT64_ROOT_5LEVEL
:
4062 rsvd_check
->rsvd_bits_mask
[0][4] = exb_bit_rsvd
|
4063 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4064 rsvd_bits(maxphyaddr
, 51);
4065 rsvd_check
->rsvd_bits_mask
[1][4] =
4066 rsvd_check
->rsvd_bits_mask
[0][4];
4067 case PT64_ROOT_4LEVEL
:
4068 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
4069 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4070 rsvd_bits(maxphyaddr
, 51);
4071 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
4072 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
4073 rsvd_bits(maxphyaddr
, 51);
4074 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4075 rsvd_bits(maxphyaddr
, 51);
4076 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4077 rsvd_bits(maxphyaddr
, 51);
4078 rsvd_check
->rsvd_bits_mask
[1][3] =
4079 rsvd_check
->rsvd_bits_mask
[0][3];
4080 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
4081 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
4083 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4084 rsvd_bits(maxphyaddr
, 51) |
4085 rsvd_bits(13, 20); /* large page */
4086 rsvd_check
->rsvd_bits_mask
[1][0] =
4087 rsvd_check
->rsvd_bits_mask
[0][0];
4092 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4093 struct kvm_mmu
*context
)
4095 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4096 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4098 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4099 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
4103 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4104 int maxphyaddr
, bool execonly
)
4108 rsvd_check
->rsvd_bits_mask
[0][4] =
4109 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4110 rsvd_check
->rsvd_bits_mask
[0][3] =
4111 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4112 rsvd_check
->rsvd_bits_mask
[0][2] =
4113 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4114 rsvd_check
->rsvd_bits_mask
[0][1] =
4115 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4116 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4119 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4120 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4121 rsvd_check
->rsvd_bits_mask
[1][2] =
4122 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4123 rsvd_check
->rsvd_bits_mask
[1][1] =
4124 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4125 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4127 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4128 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4129 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4130 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4131 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4133 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4134 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4136 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4139 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4140 struct kvm_mmu
*context
, bool execonly
)
4142 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4143 cpuid_maxphyaddr(vcpu
), execonly
);
4147 * the page table on host is the shadow page table for the page
4148 * table in guest or amd nested guest, its mmu features completely
4149 * follow the features in guest.
4152 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4154 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
4157 * Passing "true" to the last argument is okay; it adds a check
4158 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4160 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4161 boot_cpu_data
.x86_phys_bits
,
4162 context
->shadow_root_level
, uses_nx
,
4163 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4164 is_pse(vcpu
), true);
4166 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4168 static inline bool boot_cpu_is_amd(void)
4170 WARN_ON_ONCE(!tdp_enabled
);
4171 return shadow_x_mask
== 0;
4175 * the direct page table on host, use as much mmu features as
4176 * possible, however, kvm currently does not do execution-protection.
4179 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4180 struct kvm_mmu
*context
)
4182 if (boot_cpu_is_amd())
4183 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4184 boot_cpu_data
.x86_phys_bits
,
4185 context
->shadow_root_level
, false,
4186 boot_cpu_has(X86_FEATURE_GBPAGES
),
4189 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4190 boot_cpu_data
.x86_phys_bits
,
4196 * as the comments in reset_shadow_zero_bits_mask() except it
4197 * is the shadow page table for intel nested guest.
4200 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4201 struct kvm_mmu
*context
, bool execonly
)
4203 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4204 boot_cpu_data
.x86_phys_bits
, execonly
);
4207 #define BYTE_MASK(access) \
4208 ((1 & (access) ? 2 : 0) | \
4209 (2 & (access) ? 4 : 0) | \
4210 (3 & (access) ? 8 : 0) | \
4211 (4 & (access) ? 16 : 0) | \
4212 (5 & (access) ? 32 : 0) | \
4213 (6 & (access) ? 64 : 0) | \
4214 (7 & (access) ? 128 : 0))
4217 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4218 struct kvm_mmu
*mmu
, bool ept
)
4222 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4223 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4224 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4226 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4227 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4228 bool cr0_wp
= is_write_protection(vcpu
);
4230 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4231 unsigned pfec
= byte
<< 1;
4234 * Each "*f" variable has a 1 bit for each UWX value
4235 * that causes a fault with the given PFEC.
4238 /* Faults from writes to non-writable pages */
4239 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? ~w
: 0;
4240 /* Faults from user mode accesses to supervisor pages */
4241 u8 uf
= (pfec
& PFERR_USER_MASK
) ? ~u
: 0;
4242 /* Faults from fetches of non-executable pages*/
4243 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? ~x
: 0;
4244 /* Faults from kernel mode fetches of user pages */
4246 /* Faults from kernel mode accesses of user pages */
4250 /* Faults from kernel mode accesses to user pages */
4251 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4253 /* Not really needed: !nx will cause pte.nx to fault */
4257 /* Allow supervisor writes if !cr0.wp */
4259 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4261 /* Disallow supervisor fetches of user code if cr4.smep */
4263 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4266 * SMAP:kernel-mode data accesses from user-mode
4267 * mappings should fault. A fault is considered
4268 * as a SMAP violation if all of the following
4269 * conditions are ture:
4270 * - X86_CR4_SMAP is set in CR4
4271 * - A user page is accessed
4272 * - The access is not a fetch
4273 * - Page fault in kernel mode
4274 * - if CPL = 3 or X86_EFLAGS_AC is clear
4276 * Here, we cover the first three conditions.
4277 * The fourth is computed dynamically in permission_fault();
4278 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4279 * *not* subject to SMAP restrictions.
4282 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4285 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4290 * PKU is an additional mechanism by which the paging controls access to
4291 * user-mode addresses based on the value in the PKRU register. Protection
4292 * key violations are reported through a bit in the page fault error code.
4293 * Unlike other bits of the error code, the PK bit is not known at the
4294 * call site of e.g. gva_to_gpa; it must be computed directly in
4295 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4296 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4298 * In particular the following conditions come from the error code, the
4299 * page tables and the machine state:
4300 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4301 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4302 * - PK is always zero if U=0 in the page tables
4303 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4305 * The PKRU bitmask caches the result of these four conditions. The error
4306 * code (minus the P bit) and the page table's U bit form an index into the
4307 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4308 * with the two bits of the PKRU register corresponding to the protection key.
4309 * For the first three conditions above the bits will be 00, thus masking
4310 * away both AD and WD. For all reads or if the last condition holds, WD
4311 * only will be masked away.
4313 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4324 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4325 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4330 wp
= is_write_protection(vcpu
);
4332 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4333 unsigned pfec
, pkey_bits
;
4334 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4337 ff
= pfec
& PFERR_FETCH_MASK
;
4338 uf
= pfec
& PFERR_USER_MASK
;
4339 wf
= pfec
& PFERR_WRITE_MASK
;
4341 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4342 pte_user
= pfec
& PFERR_RSVD_MASK
;
4345 * Only need to check the access which is not an
4346 * instruction fetch and is to a user page.
4348 check_pkey
= (!ff
&& pte_user
);
4350 * write access is controlled by PKRU if it is a
4351 * user access or CR0.WP = 1.
4353 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4355 /* PKRU.AD stops both read and write access. */
4356 pkey_bits
= !!check_pkey
;
4357 /* PKRU.WD stops write access. */
4358 pkey_bits
|= (!!check_write
) << 1;
4360 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4364 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4366 unsigned root_level
= mmu
->root_level
;
4368 mmu
->last_nonleaf_level
= root_level
;
4369 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4370 mmu
->last_nonleaf_level
++;
4373 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4374 struct kvm_mmu
*context
,
4377 context
->nx
= is_nx(vcpu
);
4378 context
->root_level
= level
;
4380 reset_rsvds_bits_mask(vcpu
, context
);
4381 update_permission_bitmask(vcpu
, context
, false);
4382 update_pkru_bitmask(vcpu
, context
, false);
4383 update_last_nonleaf_level(vcpu
, context
);
4385 MMU_WARN_ON(!is_pae(vcpu
));
4386 context
->page_fault
= paging64_page_fault
;
4387 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4388 context
->sync_page
= paging64_sync_page
;
4389 context
->invlpg
= paging64_invlpg
;
4390 context
->update_pte
= paging64_update_pte
;
4391 context
->shadow_root_level
= level
;
4392 context
->root_hpa
= INVALID_PAGE
;
4393 context
->direct_map
= false;
4396 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4397 struct kvm_mmu
*context
)
4399 int root_level
= is_la57_mode(vcpu
) ?
4400 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4402 paging64_init_context_common(vcpu
, context
, root_level
);
4405 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4406 struct kvm_mmu
*context
)
4408 context
->nx
= false;
4409 context
->root_level
= PT32_ROOT_LEVEL
;
4411 reset_rsvds_bits_mask(vcpu
, context
);
4412 update_permission_bitmask(vcpu
, context
, false);
4413 update_pkru_bitmask(vcpu
, context
, false);
4414 update_last_nonleaf_level(vcpu
, context
);
4416 context
->page_fault
= paging32_page_fault
;
4417 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4418 context
->sync_page
= paging32_sync_page
;
4419 context
->invlpg
= paging32_invlpg
;
4420 context
->update_pte
= paging32_update_pte
;
4421 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4422 context
->root_hpa
= INVALID_PAGE
;
4423 context
->direct_map
= false;
4426 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4427 struct kvm_mmu
*context
)
4429 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4432 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4434 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4436 context
->base_role
.word
= 0;
4437 context
->base_role
.smm
= is_smm(vcpu
);
4438 context
->base_role
.ad_disabled
= (shadow_accessed_mask
== 0);
4439 context
->page_fault
= tdp_page_fault
;
4440 context
->sync_page
= nonpaging_sync_page
;
4441 context
->invlpg
= nonpaging_invlpg
;
4442 context
->update_pte
= nonpaging_update_pte
;
4443 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level(vcpu
);
4444 context
->root_hpa
= INVALID_PAGE
;
4445 context
->direct_map
= true;
4446 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4447 context
->get_cr3
= get_cr3
;
4448 context
->get_pdptr
= kvm_pdptr_read
;
4449 context
->inject_page_fault
= kvm_inject_page_fault
;
4451 if (!is_paging(vcpu
)) {
4452 context
->nx
= false;
4453 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4454 context
->root_level
= 0;
4455 } else if (is_long_mode(vcpu
)) {
4456 context
->nx
= is_nx(vcpu
);
4457 context
->root_level
= is_la57_mode(vcpu
) ?
4458 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4459 reset_rsvds_bits_mask(vcpu
, context
);
4460 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4461 } else if (is_pae(vcpu
)) {
4462 context
->nx
= is_nx(vcpu
);
4463 context
->root_level
= PT32E_ROOT_LEVEL
;
4464 reset_rsvds_bits_mask(vcpu
, context
);
4465 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4467 context
->nx
= false;
4468 context
->root_level
= PT32_ROOT_LEVEL
;
4469 reset_rsvds_bits_mask(vcpu
, context
);
4470 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4473 update_permission_bitmask(vcpu
, context
, false);
4474 update_pkru_bitmask(vcpu
, context
, false);
4475 update_last_nonleaf_level(vcpu
, context
);
4476 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4479 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4481 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4482 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4483 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4485 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4487 if (!is_paging(vcpu
))
4488 nonpaging_init_context(vcpu
, context
);
4489 else if (is_long_mode(vcpu
))
4490 paging64_init_context(vcpu
, context
);
4491 else if (is_pae(vcpu
))
4492 paging32E_init_context(vcpu
, context
);
4494 paging32_init_context(vcpu
, context
);
4496 context
->base_role
.nxe
= is_nx(vcpu
);
4497 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4498 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4499 context
->base_role
.smep_andnot_wp
4500 = smep
&& !is_write_protection(vcpu
);
4501 context
->base_role
.smap_andnot_wp
4502 = smap
&& !is_write_protection(vcpu
);
4503 context
->base_role
.smm
= is_smm(vcpu
);
4504 reset_shadow_zero_bits_mask(vcpu
, context
);
4506 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4508 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4509 bool accessed_dirty
)
4511 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4513 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4515 context
->shadow_root_level
= PT64_ROOT_4LEVEL
;
4518 context
->ept_ad
= accessed_dirty
;
4519 context
->page_fault
= ept_page_fault
;
4520 context
->gva_to_gpa
= ept_gva_to_gpa
;
4521 context
->sync_page
= ept_sync_page
;
4522 context
->invlpg
= ept_invlpg
;
4523 context
->update_pte
= ept_update_pte
;
4524 context
->root_level
= PT64_ROOT_4LEVEL
;
4525 context
->root_hpa
= INVALID_PAGE
;
4526 context
->direct_map
= false;
4527 context
->base_role
.ad_disabled
= !accessed_dirty
;
4529 update_permission_bitmask(vcpu
, context
, true);
4530 update_pkru_bitmask(vcpu
, context
, true);
4531 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4532 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4534 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4536 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4538 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4540 kvm_init_shadow_mmu(vcpu
);
4541 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4542 context
->get_cr3
= get_cr3
;
4543 context
->get_pdptr
= kvm_pdptr_read
;
4544 context
->inject_page_fault
= kvm_inject_page_fault
;
4547 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4549 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4551 g_context
->get_cr3
= get_cr3
;
4552 g_context
->get_pdptr
= kvm_pdptr_read
;
4553 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4556 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4557 * L1's nested page tables (e.g. EPT12). The nested translation
4558 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4559 * L2's page tables as the first level of translation and L1's
4560 * nested page tables as the second level of translation. Basically
4561 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4563 if (!is_paging(vcpu
)) {
4564 g_context
->nx
= false;
4565 g_context
->root_level
= 0;
4566 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4567 } else if (is_long_mode(vcpu
)) {
4568 g_context
->nx
= is_nx(vcpu
);
4569 g_context
->root_level
= is_la57_mode(vcpu
) ?
4570 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4571 reset_rsvds_bits_mask(vcpu
, g_context
);
4572 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4573 } else if (is_pae(vcpu
)) {
4574 g_context
->nx
= is_nx(vcpu
);
4575 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4576 reset_rsvds_bits_mask(vcpu
, g_context
);
4577 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4579 g_context
->nx
= false;
4580 g_context
->root_level
= PT32_ROOT_LEVEL
;
4581 reset_rsvds_bits_mask(vcpu
, g_context
);
4582 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4585 update_permission_bitmask(vcpu
, g_context
, false);
4586 update_pkru_bitmask(vcpu
, g_context
, false);
4587 update_last_nonleaf_level(vcpu
, g_context
);
4590 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4592 if (mmu_is_nested(vcpu
))
4593 init_kvm_nested_mmu(vcpu
);
4594 else if (tdp_enabled
)
4595 init_kvm_tdp_mmu(vcpu
);
4597 init_kvm_softmmu(vcpu
);
4600 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4602 kvm_mmu_unload(vcpu
);
4605 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4607 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4611 r
= mmu_topup_memory_caches(vcpu
);
4614 r
= mmu_alloc_roots(vcpu
);
4615 kvm_mmu_sync_roots(vcpu
);
4618 /* set_cr3() should ensure TLB has been flushed */
4619 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4623 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4625 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4627 mmu_free_roots(vcpu
);
4628 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4630 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4632 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4633 struct kvm_mmu_page
*sp
, u64
*spte
,
4636 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4637 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4641 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4642 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4645 static bool need_remote_flush(u64 old
, u64
new)
4647 if (!is_shadow_present_pte(old
))
4649 if (!is_shadow_present_pte(new))
4651 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4653 old
^= shadow_nx_mask
;
4654 new ^= shadow_nx_mask
;
4655 return (old
& ~new & PT64_PERM_MASK
) != 0;
4658 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4659 const u8
*new, int *bytes
)
4665 * Assume that the pte write on a page table of the same type
4666 * as the current vcpu paging mode since we update the sptes only
4667 * when they have the same mode.
4669 if (is_pae(vcpu
) && *bytes
== 4) {
4670 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4673 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4676 new = (const u8
*)&gentry
;
4681 gentry
= *(const u32
*)new;
4684 gentry
= *(const u64
*)new;
4695 * If we're seeing too many writes to a page, it may no longer be a page table,
4696 * or we may be forking, in which case it is better to unmap the page.
4698 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4701 * Skip write-flooding detected for the sp whose level is 1, because
4702 * it can become unsync, then the guest page is not write-protected.
4704 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4707 atomic_inc(&sp
->write_flooding_count
);
4708 return atomic_read(&sp
->write_flooding_count
) >= 3;
4712 * Misaligned accesses are too much trouble to fix up; also, they usually
4713 * indicate a page is not used as a page table.
4715 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4718 unsigned offset
, pte_size
, misaligned
;
4720 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4721 gpa
, bytes
, sp
->role
.word
);
4723 offset
= offset_in_page(gpa
);
4724 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4727 * Sometimes, the OS only writes the last one bytes to update status
4728 * bits, for example, in linux, andb instruction is used in clear_bit().
4730 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4733 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4734 misaligned
|= bytes
< 4;
4739 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4741 unsigned page_offset
, quadrant
;
4745 page_offset
= offset_in_page(gpa
);
4746 level
= sp
->role
.level
;
4748 if (!sp
->role
.cr4_pae
) {
4749 page_offset
<<= 1; /* 32->64 */
4751 * A 32-bit pde maps 4MB while the shadow pdes map
4752 * only 2MB. So we need to double the offset again
4753 * and zap two pdes instead of one.
4755 if (level
== PT32_ROOT_LEVEL
) {
4756 page_offset
&= ~7; /* kill rounding error */
4760 quadrant
= page_offset
>> PAGE_SHIFT
;
4761 page_offset
&= ~PAGE_MASK
;
4762 if (quadrant
!= sp
->role
.quadrant
)
4766 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4770 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4771 const u8
*new, int bytes
,
4772 struct kvm_page_track_notifier_node
*node
)
4774 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4775 struct kvm_mmu_page
*sp
;
4776 LIST_HEAD(invalid_list
);
4777 u64 entry
, gentry
, *spte
;
4779 bool remote_flush
, local_flush
;
4780 union kvm_mmu_page_role mask
= { };
4785 mask
.smep_andnot_wp
= 1;
4786 mask
.smap_andnot_wp
= 1;
4788 mask
.ad_disabled
= 1;
4791 * If we don't have indirect shadow pages, it means no page is
4792 * write-protected, so we can exit simply.
4794 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4797 remote_flush
= local_flush
= false;
4799 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4801 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4804 * No need to care whether allocation memory is successful
4805 * or not since pte prefetch is skiped if it does not have
4806 * enough objects in the cache.
4808 mmu_topup_memory_caches(vcpu
);
4810 spin_lock(&vcpu
->kvm
->mmu_lock
);
4811 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4812 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4814 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4815 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4816 detect_write_flooding(sp
)) {
4817 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4818 ++vcpu
->kvm
->stat
.mmu_flooded
;
4822 spte
= get_written_sptes(sp
, gpa
, &npte
);
4829 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4831 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4832 & mask
.word
) && rmap_can_add(vcpu
))
4833 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4834 if (need_remote_flush(entry
, *spte
))
4835 remote_flush
= true;
4839 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4840 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4841 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4844 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4849 if (vcpu
->arch
.mmu
.direct_map
)
4852 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4854 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4858 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4860 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4862 LIST_HEAD(invalid_list
);
4864 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4867 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4868 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4871 ++vcpu
->kvm
->stat
.mmu_recycled
;
4873 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4875 if (!kvm_mmu_available_pages(vcpu
->kvm
))
4880 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u64 error_code
,
4881 void *insn
, int insn_len
)
4883 int r
, emulation_type
= EMULTYPE_RETRY
;
4884 enum emulation_result er
;
4885 bool direct
= vcpu
->arch
.mmu
.direct_map
;
4887 /* With shadow page tables, fault_address contains a GVA or nGPA. */
4888 if (vcpu
->arch
.mmu
.direct_map
) {
4889 vcpu
->arch
.gpa_available
= true;
4890 vcpu
->arch
.gpa_val
= cr2
;
4893 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4894 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4895 if (r
== RET_MMIO_PF_EMULATE
) {
4899 if (r
== RET_MMIO_PF_RETRY
)
4903 /* Must be RET_MMIO_PF_INVALID. */
4906 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, lower_32_bits(error_code
),
4914 * Before emulating the instruction, check if the error code
4915 * was due to a RO violation while translating the guest page.
4916 * This can occur when using nested virtualization with nested
4917 * paging in both guests. If true, we simply unprotect the page
4918 * and resume the guest.
4920 if (vcpu
->arch
.mmu
.direct_map
&&
4921 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
4922 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2
));
4926 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4929 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4934 case EMULATE_USER_EXIT
:
4935 ++vcpu
->stat
.mmio_exits
;
4943 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4945 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4947 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4948 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4949 ++vcpu
->stat
.invlpg
;
4951 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4953 void kvm_enable_tdp(void)
4957 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4959 void kvm_disable_tdp(void)
4961 tdp_enabled
= false;
4963 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4965 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4967 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4968 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4969 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4972 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4978 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4979 * Therefore we need to allocate shadow page tables in the first
4980 * 4GB of memory, which happens to fit the DMA32 zone.
4982 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4986 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4987 for (i
= 0; i
< 4; ++i
)
4988 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4993 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4995 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4996 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4997 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4998 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5000 return alloc_mmu_pages(vcpu
);
5003 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
5005 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
5010 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5011 struct kvm_memory_slot
*slot
,
5012 struct kvm_page_track_notifier_node
*node
)
5014 kvm_mmu_invalidate_zap_all_pages(kvm
);
5017 void kvm_mmu_init_vm(struct kvm
*kvm
)
5019 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5021 node
->track_write
= kvm_mmu_pte_write
;
5022 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5023 kvm_page_track_register_notifier(kvm
, node
);
5026 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5028 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5030 kvm_page_track_unregister_notifier(kvm
, node
);
5033 /* The return value indicates if tlb flush on all vcpus is needed. */
5034 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
5036 /* The caller should hold mmu-lock before calling this function. */
5038 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5039 slot_level_handler fn
, int start_level
, int end_level
,
5040 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5042 struct slot_rmap_walk_iterator iterator
;
5045 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5046 end_gfn
, &iterator
) {
5048 flush
|= fn(kvm
, iterator
.rmap
);
5050 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5051 if (flush
&& lock_flush_tlb
) {
5052 kvm_flush_remote_tlbs(kvm
);
5055 cond_resched_lock(&kvm
->mmu_lock
);
5059 if (flush
&& lock_flush_tlb
) {
5060 kvm_flush_remote_tlbs(kvm
);
5068 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5069 slot_level_handler fn
, int start_level
, int end_level
,
5070 bool lock_flush_tlb
)
5072 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5073 end_level
, memslot
->base_gfn
,
5074 memslot
->base_gfn
+ memslot
->npages
- 1,
5079 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5080 slot_level_handler fn
, bool lock_flush_tlb
)
5082 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5083 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5087 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5088 slot_level_handler fn
, bool lock_flush_tlb
)
5090 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
5091 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5095 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5096 slot_level_handler fn
, bool lock_flush_tlb
)
5098 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5099 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
5102 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5104 struct kvm_memslots
*slots
;
5105 struct kvm_memory_slot
*memslot
;
5108 spin_lock(&kvm
->mmu_lock
);
5109 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5110 slots
= __kvm_memslots(kvm
, i
);
5111 kvm_for_each_memslot(memslot
, slots
) {
5114 start
= max(gfn_start
, memslot
->base_gfn
);
5115 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5119 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5120 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
5121 start
, end
- 1, true);
5125 spin_unlock(&kvm
->mmu_lock
);
5128 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5129 struct kvm_rmap_head
*rmap_head
)
5131 return __rmap_write_protect(kvm
, rmap_head
, false);
5134 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5135 struct kvm_memory_slot
*memslot
)
5139 spin_lock(&kvm
->mmu_lock
);
5140 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
5142 spin_unlock(&kvm
->mmu_lock
);
5145 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5146 * which do tlb flush out of mmu-lock should be serialized by
5147 * kvm->slots_lock otherwise tlb flush would be missed.
5149 lockdep_assert_held(&kvm
->slots_lock
);
5152 * We can flush all the TLBs out of the mmu lock without TLB
5153 * corruption since we just change the spte from writable to
5154 * readonly so that we only need to care the case of changing
5155 * spte from present to present (changing the spte from present
5156 * to nonpresent will flush all the TLBs immediately), in other
5157 * words, the only case we care is mmu_spte_update() where we
5158 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5159 * instead of PT_WRITABLE_MASK, that means it does not depend
5160 * on PT_WRITABLE_MASK anymore.
5163 kvm_flush_remote_tlbs(kvm
);
5166 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5167 struct kvm_rmap_head
*rmap_head
)
5170 struct rmap_iterator iter
;
5171 int need_tlb_flush
= 0;
5173 struct kvm_mmu_page
*sp
;
5176 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5177 sp
= page_header(__pa(sptep
));
5178 pfn
= spte_to_pfn(*sptep
);
5181 * We cannot do huge page mapping for indirect shadow pages,
5182 * which are found on the last rmap (level = 1) when not using
5183 * tdp; such shadow pages are synced with the page table in
5184 * the guest, and the guest page table is using 4K page size
5185 * mapping if the indirect sp has level = 1.
5187 if (sp
->role
.direct
&&
5188 !kvm_is_reserved_pfn(pfn
) &&
5189 PageTransCompoundMap(pfn_to_page(pfn
))) {
5190 drop_spte(kvm
, sptep
);
5196 return need_tlb_flush
;
5199 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5200 const struct kvm_memory_slot
*memslot
)
5202 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5203 spin_lock(&kvm
->mmu_lock
);
5204 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5205 kvm_mmu_zap_collapsible_spte
, true);
5206 spin_unlock(&kvm
->mmu_lock
);
5209 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5210 struct kvm_memory_slot
*memslot
)
5214 spin_lock(&kvm
->mmu_lock
);
5215 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5216 spin_unlock(&kvm
->mmu_lock
);
5218 lockdep_assert_held(&kvm
->slots_lock
);
5221 * It's also safe to flush TLBs out of mmu lock here as currently this
5222 * function is only used for dirty logging, in which case flushing TLB
5223 * out of mmu lock also guarantees no dirty pages will be lost in
5227 kvm_flush_remote_tlbs(kvm
);
5229 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5231 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5232 struct kvm_memory_slot
*memslot
)
5236 spin_lock(&kvm
->mmu_lock
);
5237 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5239 spin_unlock(&kvm
->mmu_lock
);
5241 /* see kvm_mmu_slot_remove_write_access */
5242 lockdep_assert_held(&kvm
->slots_lock
);
5245 kvm_flush_remote_tlbs(kvm
);
5247 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5249 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5250 struct kvm_memory_slot
*memslot
)
5254 spin_lock(&kvm
->mmu_lock
);
5255 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5256 spin_unlock(&kvm
->mmu_lock
);
5258 lockdep_assert_held(&kvm
->slots_lock
);
5260 /* see kvm_mmu_slot_leaf_clear_dirty */
5262 kvm_flush_remote_tlbs(kvm
);
5264 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5266 #define BATCH_ZAP_PAGES 10
5267 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5269 struct kvm_mmu_page
*sp
, *node
;
5273 list_for_each_entry_safe_reverse(sp
, node
,
5274 &kvm
->arch
.active_mmu_pages
, link
) {
5278 * No obsolete page exists before new created page since
5279 * active_mmu_pages is the FIFO list.
5281 if (!is_obsolete_sp(kvm
, sp
))
5285 * Since we are reversely walking the list and the invalid
5286 * list will be moved to the head, skip the invalid page
5287 * can help us to avoid the infinity list walking.
5289 if (sp
->role
.invalid
)
5293 * Need not flush tlb since we only zap the sp with invalid
5294 * generation number.
5296 if (batch
>= BATCH_ZAP_PAGES
&&
5297 cond_resched_lock(&kvm
->mmu_lock
)) {
5302 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
5303 &kvm
->arch
.zapped_obsolete_pages
);
5311 * Should flush tlb before free page tables since lockless-walking
5312 * may use the pages.
5314 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5318 * Fast invalidate all shadow pages and use lock-break technique
5319 * to zap obsolete pages.
5321 * It's required when memslot is being deleted or VM is being
5322 * destroyed, in these cases, we should ensure that KVM MMU does
5323 * not use any resource of the being-deleted slot or all slots
5324 * after calling the function.
5326 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
5328 spin_lock(&kvm
->mmu_lock
);
5329 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
5330 kvm
->arch
.mmu_valid_gen
++;
5333 * Notify all vcpus to reload its shadow page table
5334 * and flush TLB. Then all vcpus will switch to new
5335 * shadow page table with the new mmu_valid_gen.
5337 * Note: we should do this under the protection of
5338 * mmu-lock, otherwise, vcpu would purge shadow page
5339 * but miss tlb flush.
5341 kvm_reload_remote_mmus(kvm
);
5343 kvm_zap_obsolete_pages(kvm
);
5344 spin_unlock(&kvm
->mmu_lock
);
5347 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5349 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5352 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
5355 * The very rare case: if the generation-number is round,
5356 * zap all shadow pages.
5358 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
5359 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5360 kvm_mmu_invalidate_zap_all_pages(kvm
);
5364 static unsigned long
5365 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5368 int nr_to_scan
= sc
->nr_to_scan
;
5369 unsigned long freed
= 0;
5371 spin_lock(&kvm_lock
);
5373 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5375 LIST_HEAD(invalid_list
);
5378 * Never scan more than sc->nr_to_scan VM instances.
5379 * Will not hit this condition practically since we do not try
5380 * to shrink more than one VM and it is very unlikely to see
5381 * !n_used_mmu_pages so many times.
5386 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5387 * here. We may skip a VM instance errorneosly, but we do not
5388 * want to shrink a VM that only started to populate its MMU
5391 if (!kvm
->arch
.n_used_mmu_pages
&&
5392 !kvm_has_zapped_obsolete_pages(kvm
))
5395 idx
= srcu_read_lock(&kvm
->srcu
);
5396 spin_lock(&kvm
->mmu_lock
);
5398 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5399 kvm_mmu_commit_zap_page(kvm
,
5400 &kvm
->arch
.zapped_obsolete_pages
);
5404 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5406 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5409 spin_unlock(&kvm
->mmu_lock
);
5410 srcu_read_unlock(&kvm
->srcu
, idx
);
5413 * unfair on small ones
5414 * per-vm shrinkers cry out
5415 * sadness comes quickly
5417 list_move_tail(&kvm
->vm_list
, &vm_list
);
5421 spin_unlock(&kvm_lock
);
5425 static unsigned long
5426 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5428 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5431 static struct shrinker mmu_shrinker
= {
5432 .count_objects
= mmu_shrink_count
,
5433 .scan_objects
= mmu_shrink_scan
,
5434 .seeks
= DEFAULT_SEEKS
* 10,
5437 static void mmu_destroy_caches(void)
5439 if (pte_list_desc_cache
)
5440 kmem_cache_destroy(pte_list_desc_cache
);
5441 if (mmu_page_header_cache
)
5442 kmem_cache_destroy(mmu_page_header_cache
);
5445 int kvm_mmu_module_init(void)
5447 kvm_mmu_clear_all_pte_masks();
5449 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5450 sizeof(struct pte_list_desc
),
5452 if (!pte_list_desc_cache
)
5455 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5456 sizeof(struct kvm_mmu_page
),
5458 if (!mmu_page_header_cache
)
5461 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5464 register_shrinker(&mmu_shrinker
);
5469 mmu_destroy_caches();
5474 * Caculate mmu pages needed for kvm.
5476 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5478 unsigned int nr_mmu_pages
;
5479 unsigned int nr_pages
= 0;
5480 struct kvm_memslots
*slots
;
5481 struct kvm_memory_slot
*memslot
;
5484 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5485 slots
= __kvm_memslots(kvm
, i
);
5487 kvm_for_each_memslot(memslot
, slots
)
5488 nr_pages
+= memslot
->npages
;
5491 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5492 nr_mmu_pages
= max(nr_mmu_pages
,
5493 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5495 return nr_mmu_pages
;
5498 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5500 kvm_mmu_unload(vcpu
);
5501 free_mmu_pages(vcpu
);
5502 mmu_free_memory_caches(vcpu
);
5505 void kvm_mmu_module_exit(void)
5507 mmu_destroy_caches();
5508 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5509 unregister_shrinker(&mmu_shrinker
);
5510 mmu_audit_disable();