2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
51 * When setting this variable to true it enables Two-Dimensional-Paging
52 * where the hardware walks 2 page tables:
53 * 1. the guest-virtual to guest-physical
54 * 2. while doing 1. it walks guest-physical to host-physical
55 * If the hardware supports that we don't need to do shadow paging.
57 bool tdp_enabled
= false;
61 AUDIT_POST_PAGE_FAULT
,
72 module_param(dbg
, bool, 0644);
74 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
75 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
76 #define MMU_WARN_ON(x) WARN_ON(x)
78 #define pgprintk(x...) do { } while (0)
79 #define rmap_printk(x...) do { } while (0)
80 #define MMU_WARN_ON(x) do { } while (0)
83 #define PTE_PREFETCH_NUM 8
85 #define PT_FIRST_AVAIL_BITS_SHIFT 10
86 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
88 #define PT64_LEVEL_BITS 9
90 #define PT64_LEVEL_SHIFT(level) \
91 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
93 #define PT64_INDEX(address, level)\
94 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
97 #define PT32_LEVEL_BITS 10
99 #define PT32_LEVEL_SHIFT(level) \
100 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
102 #define PT32_LVL_OFFSET_MASK(level) \
103 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
104 * PT32_LEVEL_BITS))) - 1))
106 #define PT32_INDEX(address, level)\
107 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
110 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
111 #define PT64_DIR_BASE_ADDR_MASK \
112 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
113 #define PT64_LVL_ADDR_MASK(level) \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
115 * PT64_LEVEL_BITS))) - 1))
116 #define PT64_LVL_OFFSET_MASK(level) \
117 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
118 * PT64_LEVEL_BITS))) - 1))
120 #define PT32_BASE_ADDR_MASK PAGE_MASK
121 #define PT32_DIR_BASE_ADDR_MASK \
122 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
123 #define PT32_LVL_ADDR_MASK(level) \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
127 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
128 | shadow_x_mask | shadow_nx_mask)
130 #define ACC_EXEC_MASK 1
131 #define ACC_WRITE_MASK PT_WRITABLE_MASK
132 #define ACC_USER_MASK PT_USER_MASK
133 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
135 /* The mask for the R/X bits in EPT PTEs */
136 #define PT64_EPT_READABLE_MASK 0x1ull
137 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
139 #include <trace/events/kvm.h>
141 #define CREATE_TRACE_POINTS
142 #include "mmutrace.h"
144 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
145 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
147 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
149 /* make pte_list_desc fit well in cache line */
150 #define PTE_LIST_EXT 3
152 struct pte_list_desc
{
153 u64
*sptes
[PTE_LIST_EXT
];
154 struct pte_list_desc
*more
;
157 struct kvm_shadow_walk_iterator
{
165 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)); \
168 shadow_walk_next(&(_walker)))
170 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
171 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
172 shadow_walk_okay(&(_walker)) && \
173 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
174 __shadow_walk_next(&(_walker), spte))
176 static struct kmem_cache
*pte_list_desc_cache
;
177 static struct kmem_cache
*mmu_page_header_cache
;
178 static struct percpu_counter kvm_total_used_mmu_pages
;
180 static u64 __read_mostly shadow_nx_mask
;
181 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
182 static u64 __read_mostly shadow_user_mask
;
183 static u64 __read_mostly shadow_accessed_mask
;
184 static u64 __read_mostly shadow_dirty_mask
;
185 static u64 __read_mostly shadow_mmio_mask
;
186 static u64 __read_mostly shadow_mmio_value
;
187 static u64 __read_mostly shadow_present_mask
;
190 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
191 * Non-present SPTEs with shadow_acc_track_value set are in place for access
194 static u64 __read_mostly shadow_acc_track_mask
;
195 static const u64 shadow_acc_track_value
= SPTE_SPECIAL_MASK
;
198 * The mask/shift to use for saving the original R/X bits when marking the PTE
199 * as not-present for access tracking purposes. We do not save the W bit as the
200 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
201 * restored only when a write is attempted to the page.
203 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
204 PT64_EPT_EXECUTABLE_MASK
;
205 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
207 static void mmu_spte_set(u64
*sptep
, u64 spte
);
208 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
210 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
, u64 mmio_value
)
212 BUG_ON((mmio_mask
& mmio_value
) != mmio_value
);
213 shadow_mmio_value
= mmio_value
| SPTE_SPECIAL_MASK
;
214 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
216 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
218 static inline bool sp_ad_disabled(struct kvm_mmu_page
*sp
)
220 return sp
->role
.ad_disabled
;
223 static inline bool spte_ad_enabled(u64 spte
)
225 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
226 return !(spte
& shadow_acc_track_value
);
229 static inline u64
spte_shadow_accessed_mask(u64 spte
)
231 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
232 return spte_ad_enabled(spte
) ? shadow_accessed_mask
: 0;
235 static inline u64
spte_shadow_dirty_mask(u64 spte
)
237 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
238 return spte_ad_enabled(spte
) ? shadow_dirty_mask
: 0;
241 static inline bool is_access_track_spte(u64 spte
)
243 return !spte_ad_enabled(spte
) && (spte
& shadow_acc_track_mask
) == 0;
247 * the low bit of the generation number is always presumed to be zero.
248 * This disables mmio caching during memslot updates. The concept is
249 * similar to a seqcount but instead of retrying the access we just punt
250 * and ignore the cache.
252 * spte bits 3-11 are used as bits 1-9 of the generation number,
253 * the bits 52-61 are used as bits 10-19 of the generation number.
255 #define MMIO_SPTE_GEN_LOW_SHIFT 2
256 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
258 #define MMIO_GEN_SHIFT 20
259 #define MMIO_GEN_LOW_SHIFT 10
260 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
261 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
263 static u64
generation_mmio_spte_mask(unsigned int gen
)
267 WARN_ON(gen
& ~MMIO_GEN_MASK
);
269 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
270 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
274 static unsigned int get_mmio_spte_generation(u64 spte
)
278 spte
&= ~shadow_mmio_mask
;
280 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
281 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
285 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
287 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
290 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
293 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
294 u64 mask
= generation_mmio_spte_mask(gen
);
296 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
297 mask
|= shadow_mmio_value
| access
| gfn
<< PAGE_SHIFT
;
299 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
300 mmu_spte_set(sptep
, mask
);
303 static bool is_mmio_spte(u64 spte
)
305 return (spte
& shadow_mmio_mask
) == shadow_mmio_value
;
308 static gfn_t
get_mmio_spte_gfn(u64 spte
)
310 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
311 return (spte
& ~mask
) >> PAGE_SHIFT
;
314 static unsigned get_mmio_spte_access(u64 spte
)
316 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
317 return (spte
& ~mask
) & ~PAGE_MASK
;
320 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
321 kvm_pfn_t pfn
, unsigned access
)
323 if (unlikely(is_noslot_pfn(pfn
))) {
324 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
331 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
333 unsigned int kvm_gen
, spte_gen
;
335 kvm_gen
= kvm_current_mmio_generation(vcpu
);
336 spte_gen
= get_mmio_spte_generation(spte
);
338 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
339 return likely(kvm_gen
== spte_gen
);
343 * Sets the shadow PTE masks used by the MMU.
346 * - Setting either @accessed_mask or @dirty_mask requires setting both
347 * - At least one of @accessed_mask or @acc_track_mask must be set
349 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
350 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
353 BUG_ON(!dirty_mask
!= !accessed_mask
);
354 BUG_ON(!accessed_mask
&& !acc_track_mask
);
355 BUG_ON(acc_track_mask
& shadow_acc_track_value
);
357 shadow_user_mask
= user_mask
;
358 shadow_accessed_mask
= accessed_mask
;
359 shadow_dirty_mask
= dirty_mask
;
360 shadow_nx_mask
= nx_mask
;
361 shadow_x_mask
= x_mask
;
362 shadow_present_mask
= p_mask
;
363 shadow_acc_track_mask
= acc_track_mask
;
365 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
367 void kvm_mmu_clear_all_pte_masks(void)
369 shadow_user_mask
= 0;
370 shadow_accessed_mask
= 0;
371 shadow_dirty_mask
= 0;
374 shadow_mmio_mask
= 0;
375 shadow_present_mask
= 0;
376 shadow_acc_track_mask
= 0;
379 static int is_cpuid_PSE36(void)
384 static int is_nx(struct kvm_vcpu
*vcpu
)
386 return vcpu
->arch
.efer
& EFER_NX
;
389 static int is_shadow_present_pte(u64 pte
)
391 return (pte
!= 0) && !is_mmio_spte(pte
);
394 static int is_large_pte(u64 pte
)
396 return pte
& PT_PAGE_SIZE_MASK
;
399 static int is_last_spte(u64 pte
, int level
)
401 if (level
== PT_PAGE_TABLE_LEVEL
)
403 if (is_large_pte(pte
))
408 static bool is_executable_pte(u64 spte
)
410 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
413 static kvm_pfn_t
spte_to_pfn(u64 pte
)
415 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
418 static gfn_t
pse36_gfn_delta(u32 gpte
)
420 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
422 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
426 static void __set_spte(u64
*sptep
, u64 spte
)
428 WRITE_ONCE(*sptep
, spte
);
431 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
433 WRITE_ONCE(*sptep
, spte
);
436 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
438 return xchg(sptep
, spte
);
441 static u64
__get_spte_lockless(u64
*sptep
)
443 return ACCESS_ONCE(*sptep
);
454 static void count_spte_clear(u64
*sptep
, u64 spte
)
456 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
458 if (is_shadow_present_pte(spte
))
461 /* Ensure the spte is completely set before we increase the count */
463 sp
->clear_spte_count
++;
466 static void __set_spte(u64
*sptep
, u64 spte
)
468 union split_spte
*ssptep
, sspte
;
470 ssptep
= (union split_spte
*)sptep
;
471 sspte
= (union split_spte
)spte
;
473 ssptep
->spte_high
= sspte
.spte_high
;
476 * If we map the spte from nonpresent to present, We should store
477 * the high bits firstly, then set present bit, so cpu can not
478 * fetch this spte while we are setting the spte.
482 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
485 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
487 union split_spte
*ssptep
, sspte
;
489 ssptep
= (union split_spte
*)sptep
;
490 sspte
= (union split_spte
)spte
;
492 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
495 * If we map the spte from present to nonpresent, we should clear
496 * present bit firstly to avoid vcpu fetch the old high bits.
500 ssptep
->spte_high
= sspte
.spte_high
;
501 count_spte_clear(sptep
, spte
);
504 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
506 union split_spte
*ssptep
, sspte
, orig
;
508 ssptep
= (union split_spte
*)sptep
;
509 sspte
= (union split_spte
)spte
;
511 /* xchg acts as a barrier before the setting of the high bits */
512 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
513 orig
.spte_high
= ssptep
->spte_high
;
514 ssptep
->spte_high
= sspte
.spte_high
;
515 count_spte_clear(sptep
, spte
);
521 * The idea using the light way get the spte on x86_32 guest is from
522 * gup_get_pte(arch/x86/mm/gup.c).
524 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
525 * coalesces them and we are running out of the MMU lock. Therefore
526 * we need to protect against in-progress updates of the spte.
528 * Reading the spte while an update is in progress may get the old value
529 * for the high part of the spte. The race is fine for a present->non-present
530 * change (because the high part of the spte is ignored for non-present spte),
531 * but for a present->present change we must reread the spte.
533 * All such changes are done in two steps (present->non-present and
534 * non-present->present), hence it is enough to count the number of
535 * present->non-present updates: if it changed while reading the spte,
536 * we might have hit the race. This is done using clear_spte_count.
538 static u64
__get_spte_lockless(u64
*sptep
)
540 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
541 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
545 count
= sp
->clear_spte_count
;
548 spte
.spte_low
= orig
->spte_low
;
551 spte
.spte_high
= orig
->spte_high
;
554 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
555 count
!= sp
->clear_spte_count
))
562 static bool spte_can_locklessly_be_made_writable(u64 spte
)
564 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
565 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
568 static bool spte_has_volatile_bits(u64 spte
)
570 if (!is_shadow_present_pte(spte
))
574 * Always atomically update spte if it can be updated
575 * out of mmu-lock, it can ensure dirty bit is not lost,
576 * also, it can help us to get a stable is_writable_pte()
577 * to ensure tlb flush is not missed.
579 if (spte_can_locklessly_be_made_writable(spte
) ||
580 is_access_track_spte(spte
))
583 if (spte_ad_enabled(spte
)) {
584 if ((spte
& shadow_accessed_mask
) == 0 ||
585 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
592 static bool is_accessed_spte(u64 spte
)
594 u64 accessed_mask
= spte_shadow_accessed_mask(spte
);
596 return accessed_mask
? spte
& accessed_mask
597 : !is_access_track_spte(spte
);
600 static bool is_dirty_spte(u64 spte
)
602 u64 dirty_mask
= spte_shadow_dirty_mask(spte
);
604 return dirty_mask
? spte
& dirty_mask
: spte
& PT_WRITABLE_MASK
;
607 /* Rules for using mmu_spte_set:
608 * Set the sptep from nonpresent to present.
609 * Note: the sptep being assigned *must* be either not present
610 * or in a state where the hardware will not attempt to update
613 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
615 WARN_ON(is_shadow_present_pte(*sptep
));
616 __set_spte(sptep
, new_spte
);
620 * Update the SPTE (excluding the PFN), but do not track changes in its
621 * accessed/dirty status.
623 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
625 u64 old_spte
= *sptep
;
627 WARN_ON(!is_shadow_present_pte(new_spte
));
629 if (!is_shadow_present_pte(old_spte
)) {
630 mmu_spte_set(sptep
, new_spte
);
634 if (!spte_has_volatile_bits(old_spte
))
635 __update_clear_spte_fast(sptep
, new_spte
);
637 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
639 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
644 /* Rules for using mmu_spte_update:
645 * Update the state bits, it means the mapped pfn is not changed.
647 * Whenever we overwrite a writable spte with a read-only one we
648 * should flush remote TLBs. Otherwise rmap_write_protect
649 * will find a read-only spte, even though the writable spte
650 * might be cached on a CPU's TLB, the return value indicates this
653 * Returns true if the TLB needs to be flushed
655 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
658 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
660 if (!is_shadow_present_pte(old_spte
))
664 * For the spte updated out of mmu-lock is safe, since
665 * we always atomically update it, see the comments in
666 * spte_has_volatile_bits().
668 if (spte_can_locklessly_be_made_writable(old_spte
) &&
669 !is_writable_pte(new_spte
))
673 * Flush TLB when accessed/dirty states are changed in the page tables,
674 * to guarantee consistency between TLB and page tables.
677 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
679 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
682 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
684 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
691 * Rules for using mmu_spte_clear_track_bits:
692 * It sets the sptep from present to nonpresent, and track the
693 * state bits, it is used to clear the last level sptep.
694 * Returns non-zero if the PTE was previously valid.
696 static int mmu_spte_clear_track_bits(u64
*sptep
)
699 u64 old_spte
= *sptep
;
701 if (!spte_has_volatile_bits(old_spte
))
702 __update_clear_spte_fast(sptep
, 0ull);
704 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
706 if (!is_shadow_present_pte(old_spte
))
709 pfn
= spte_to_pfn(old_spte
);
712 * KVM does not hold the refcount of the page used by
713 * kvm mmu, before reclaiming the page, we should
714 * unmap it from mmu first.
716 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
718 if (is_accessed_spte(old_spte
))
719 kvm_set_pfn_accessed(pfn
);
721 if (is_dirty_spte(old_spte
))
722 kvm_set_pfn_dirty(pfn
);
728 * Rules for using mmu_spte_clear_no_track:
729 * Directly clear spte without caring the state bits of sptep,
730 * it is used to set the upper level spte.
732 static void mmu_spte_clear_no_track(u64
*sptep
)
734 __update_clear_spte_fast(sptep
, 0ull);
737 static u64
mmu_spte_get_lockless(u64
*sptep
)
739 return __get_spte_lockless(sptep
);
742 static u64
mark_spte_for_access_track(u64 spte
)
744 if (spte_ad_enabled(spte
))
745 return spte
& ~shadow_accessed_mask
;
747 if (is_access_track_spte(spte
))
751 * Making an Access Tracking PTE will result in removal of write access
752 * from the PTE. So, verify that we will be able to restore the write
753 * access in the fast page fault path later on.
755 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
756 !spte_can_locklessly_be_made_writable(spte
),
757 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
759 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
760 shadow_acc_track_saved_bits_shift
),
761 "kvm: Access Tracking saved bit locations are not zero\n");
763 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
764 shadow_acc_track_saved_bits_shift
;
765 spte
&= ~shadow_acc_track_mask
;
770 /* Restore an acc-track PTE back to a regular PTE */
771 static u64
restore_acc_track_spte(u64 spte
)
774 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
775 & shadow_acc_track_saved_bits_mask
;
777 WARN_ON_ONCE(spte_ad_enabled(spte
));
778 WARN_ON_ONCE(!is_access_track_spte(spte
));
780 new_spte
&= ~shadow_acc_track_mask
;
781 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
782 shadow_acc_track_saved_bits_shift
);
783 new_spte
|= saved_bits
;
788 /* Returns the Accessed status of the PTE and resets it at the same time. */
789 static bool mmu_spte_age(u64
*sptep
)
791 u64 spte
= mmu_spte_get_lockless(sptep
);
793 if (!is_accessed_spte(spte
))
796 if (spte_ad_enabled(spte
)) {
797 clear_bit((ffs(shadow_accessed_mask
) - 1),
798 (unsigned long *)sptep
);
801 * Capture the dirty status of the page, so that it doesn't get
802 * lost when the SPTE is marked for access tracking.
804 if (is_writable_pte(spte
))
805 kvm_set_pfn_dirty(spte_to_pfn(spte
));
807 spte
= mark_spte_for_access_track(spte
);
808 mmu_spte_update_no_track(sptep
, spte
);
814 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
817 * Prevent page table teardown by making any free-er wait during
818 * kvm_flush_remote_tlbs() IPI to all active vcpus.
823 * Make sure a following spte read is not reordered ahead of the write
826 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
829 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
832 * Make sure the write to vcpu->mode is not reordered in front of
833 * reads to sptes. If it does, kvm_commit_zap_page() can see us
834 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
836 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
840 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
841 struct kmem_cache
*base_cache
, int min
)
845 if (cache
->nobjs
>= min
)
847 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
848 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
851 cache
->objects
[cache
->nobjs
++] = obj
;
856 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
861 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
862 struct kmem_cache
*cache
)
865 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
868 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
873 if (cache
->nobjs
>= min
)
875 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
876 page
= (void *)__get_free_page(GFP_KERNEL
);
879 cache
->objects
[cache
->nobjs
++] = page
;
884 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
887 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
890 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
894 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
895 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
898 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
901 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
902 mmu_page_header_cache
, 4);
907 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
909 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
910 pte_list_desc_cache
);
911 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
912 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
913 mmu_page_header_cache
);
916 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
921 p
= mc
->objects
[--mc
->nobjs
];
925 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
927 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
930 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
932 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
935 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
937 if (!sp
->role
.direct
)
938 return sp
->gfns
[index
];
940 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
943 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
946 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
948 sp
->gfns
[index
] = gfn
;
952 * Return the pointer to the large page information for a given gfn,
953 * handling slots that are not large page aligned.
955 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
956 struct kvm_memory_slot
*slot
,
961 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
962 return &slot
->arch
.lpage_info
[level
- 2][idx
];
965 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
966 gfn_t gfn
, int count
)
968 struct kvm_lpage_info
*linfo
;
971 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
972 linfo
= lpage_info_slot(gfn
, slot
, i
);
973 linfo
->disallow_lpage
+= count
;
974 WARN_ON(linfo
->disallow_lpage
< 0);
978 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
980 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
983 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
985 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
988 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
990 struct kvm_memslots
*slots
;
991 struct kvm_memory_slot
*slot
;
994 kvm
->arch
.indirect_shadow_pages
++;
996 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
997 slot
= __gfn_to_memslot(slots
, gfn
);
999 /* the non-leaf shadow pages are keeping readonly. */
1000 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1001 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
1002 KVM_PAGE_TRACK_WRITE
);
1004 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
1007 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1009 struct kvm_memslots
*slots
;
1010 struct kvm_memory_slot
*slot
;
1013 kvm
->arch
.indirect_shadow_pages
--;
1015 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1016 slot
= __gfn_to_memslot(slots
, gfn
);
1017 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1018 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
1019 KVM_PAGE_TRACK_WRITE
);
1021 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
1024 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
1025 struct kvm_memory_slot
*slot
)
1027 struct kvm_lpage_info
*linfo
;
1030 linfo
= lpage_info_slot(gfn
, slot
, level
);
1031 return !!linfo
->disallow_lpage
;
1037 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1040 struct kvm_memory_slot
*slot
;
1042 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1043 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
1046 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
1048 unsigned long page_size
;
1051 page_size
= kvm_host_page_size(kvm
, gfn
);
1053 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1054 if (page_size
>= KVM_HPAGE_SIZE(i
))
1063 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
1066 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1068 if (no_dirty_log
&& slot
->dirty_bitmap
)
1074 static struct kvm_memory_slot
*
1075 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1078 struct kvm_memory_slot
*slot
;
1080 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1081 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
1087 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
1088 bool *force_pt_level
)
1090 int host_level
, level
, max_level
;
1091 struct kvm_memory_slot
*slot
;
1093 if (unlikely(*force_pt_level
))
1094 return PT_PAGE_TABLE_LEVEL
;
1096 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
1097 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
1098 if (unlikely(*force_pt_level
))
1099 return PT_PAGE_TABLE_LEVEL
;
1101 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
1103 if (host_level
== PT_PAGE_TABLE_LEVEL
)
1106 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
1108 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
1109 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
1116 * About rmap_head encoding:
1118 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1119 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1120 * pte_list_desc containing more mappings.
1124 * Returns the number of pointers in the rmap chain, not counting the new one.
1126 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1127 struct kvm_rmap_head
*rmap_head
)
1129 struct pte_list_desc
*desc
;
1132 if (!rmap_head
->val
) {
1133 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1134 rmap_head
->val
= (unsigned long)spte
;
1135 } else if (!(rmap_head
->val
& 1)) {
1136 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1137 desc
= mmu_alloc_pte_list_desc(vcpu
);
1138 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1139 desc
->sptes
[1] = spte
;
1140 rmap_head
->val
= (unsigned long)desc
| 1;
1143 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1144 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1145 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1147 count
+= PTE_LIST_EXT
;
1149 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1150 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1153 for (i
= 0; desc
->sptes
[i
]; ++i
)
1155 desc
->sptes
[i
] = spte
;
1161 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1162 struct pte_list_desc
*desc
, int i
,
1163 struct pte_list_desc
*prev_desc
)
1167 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1169 desc
->sptes
[i
] = desc
->sptes
[j
];
1170 desc
->sptes
[j
] = NULL
;
1173 if (!prev_desc
&& !desc
->more
)
1174 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1177 prev_desc
->more
= desc
->more
;
1179 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1180 mmu_free_pte_list_desc(desc
);
1183 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1185 struct pte_list_desc
*desc
;
1186 struct pte_list_desc
*prev_desc
;
1189 if (!rmap_head
->val
) {
1190 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1192 } else if (!(rmap_head
->val
& 1)) {
1193 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1194 if ((u64
*)rmap_head
->val
!= spte
) {
1195 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1200 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1201 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1204 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1205 if (desc
->sptes
[i
] == spte
) {
1206 pte_list_desc_remove_entry(rmap_head
,
1207 desc
, i
, prev_desc
);
1214 pr_err("pte_list_remove: %p many->many\n", spte
);
1219 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1220 struct kvm_memory_slot
*slot
)
1224 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1225 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1228 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1229 struct kvm_mmu_page
*sp
)
1231 struct kvm_memslots
*slots
;
1232 struct kvm_memory_slot
*slot
;
1234 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1235 slot
= __gfn_to_memslot(slots
, gfn
);
1236 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1239 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1241 struct kvm_mmu_memory_cache
*cache
;
1243 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1244 return mmu_memory_cache_free_objects(cache
);
1247 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1249 struct kvm_mmu_page
*sp
;
1250 struct kvm_rmap_head
*rmap_head
;
1252 sp
= page_header(__pa(spte
));
1253 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1254 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1255 return pte_list_add(vcpu
, spte
, rmap_head
);
1258 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1260 struct kvm_mmu_page
*sp
;
1262 struct kvm_rmap_head
*rmap_head
;
1264 sp
= page_header(__pa(spte
));
1265 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1266 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1267 pte_list_remove(spte
, rmap_head
);
1271 * Used by the following functions to iterate through the sptes linked by a
1272 * rmap. All fields are private and not assumed to be used outside.
1274 struct rmap_iterator
{
1275 /* private fields */
1276 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1277 int pos
; /* index of the sptep */
1281 * Iteration must be started by this function. This should also be used after
1282 * removing/dropping sptes from the rmap link because in such cases the
1283 * information in the itererator may not be valid.
1285 * Returns sptep if found, NULL otherwise.
1287 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1288 struct rmap_iterator
*iter
)
1292 if (!rmap_head
->val
)
1295 if (!(rmap_head
->val
& 1)) {
1297 sptep
= (u64
*)rmap_head
->val
;
1301 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1303 sptep
= iter
->desc
->sptes
[iter
->pos
];
1305 BUG_ON(!is_shadow_present_pte(*sptep
));
1310 * Must be used with a valid iterator: e.g. after rmap_get_first().
1312 * Returns sptep if found, NULL otherwise.
1314 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1319 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1321 sptep
= iter
->desc
->sptes
[iter
->pos
];
1326 iter
->desc
= iter
->desc
->more
;
1330 /* desc->sptes[0] cannot be NULL */
1331 sptep
= iter
->desc
->sptes
[iter
->pos
];
1338 BUG_ON(!is_shadow_present_pte(*sptep
));
1342 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1343 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1344 _spte_; _spte_ = rmap_get_next(_iter_))
1346 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1348 if (mmu_spte_clear_track_bits(sptep
))
1349 rmap_remove(kvm
, sptep
);
1353 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1355 if (is_large_pte(*sptep
)) {
1356 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1357 PT_PAGE_TABLE_LEVEL
);
1358 drop_spte(kvm
, sptep
);
1366 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1368 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1369 kvm_flush_remote_tlbs(vcpu
->kvm
);
1373 * Write-protect on the specified @sptep, @pt_protect indicates whether
1374 * spte write-protection is caused by protecting shadow page table.
1376 * Note: write protection is difference between dirty logging and spte
1378 * - for dirty logging, the spte can be set to writable at anytime if
1379 * its dirty bitmap is properly set.
1380 * - for spte protection, the spte can be writable only after unsync-ing
1383 * Return true if tlb need be flushed.
1385 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1389 if (!is_writable_pte(spte
) &&
1390 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1393 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1396 spte
&= ~SPTE_MMU_WRITEABLE
;
1397 spte
= spte
& ~PT_WRITABLE_MASK
;
1399 return mmu_spte_update(sptep
, spte
);
1402 static bool __rmap_write_protect(struct kvm
*kvm
,
1403 struct kvm_rmap_head
*rmap_head
,
1407 struct rmap_iterator iter
;
1410 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1411 flush
|= spte_write_protect(sptep
, pt_protect
);
1416 static bool spte_clear_dirty(u64
*sptep
)
1420 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1422 spte
&= ~shadow_dirty_mask
;
1424 return mmu_spte_update(sptep
, spte
);
1427 static bool wrprot_ad_disabled_spte(u64
*sptep
)
1429 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1430 (unsigned long *)sptep
);
1432 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1434 return was_writable
;
1438 * Gets the GFN ready for another round of dirty logging by clearing the
1439 * - D bit on ad-enabled SPTEs, and
1440 * - W bit on ad-disabled SPTEs.
1441 * Returns true iff any D or W bits were cleared.
1443 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1446 struct rmap_iterator iter
;
1449 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1450 if (spte_ad_enabled(*sptep
))
1451 flush
|= spte_clear_dirty(sptep
);
1453 flush
|= wrprot_ad_disabled_spte(sptep
);
1458 static bool spte_set_dirty(u64
*sptep
)
1462 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1464 spte
|= shadow_dirty_mask
;
1466 return mmu_spte_update(sptep
, spte
);
1469 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1472 struct rmap_iterator iter
;
1475 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1476 if (spte_ad_enabled(*sptep
))
1477 flush
|= spte_set_dirty(sptep
);
1483 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1484 * @kvm: kvm instance
1485 * @slot: slot to protect
1486 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1487 * @mask: indicates which pages we should protect
1489 * Used when we do not need to care about huge page mappings: e.g. during dirty
1490 * logging we do not have any such mappings.
1492 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1493 struct kvm_memory_slot
*slot
,
1494 gfn_t gfn_offset
, unsigned long mask
)
1496 struct kvm_rmap_head
*rmap_head
;
1499 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1500 PT_PAGE_TABLE_LEVEL
, slot
);
1501 __rmap_write_protect(kvm
, rmap_head
, false);
1503 /* clear the first set bit */
1509 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1510 * protect the page if the D-bit isn't supported.
1511 * @kvm: kvm instance
1512 * @slot: slot to clear D-bit
1513 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1514 * @mask: indicates which pages we should clear D-bit
1516 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1518 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1519 struct kvm_memory_slot
*slot
,
1520 gfn_t gfn_offset
, unsigned long mask
)
1522 struct kvm_rmap_head
*rmap_head
;
1525 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1526 PT_PAGE_TABLE_LEVEL
, slot
);
1527 __rmap_clear_dirty(kvm
, rmap_head
);
1529 /* clear the first set bit */
1533 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1536 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1539 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1540 * enable dirty logging for them.
1542 * Used when we do not need to care about huge page mappings: e.g. during dirty
1543 * logging we do not have any such mappings.
1545 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1546 struct kvm_memory_slot
*slot
,
1547 gfn_t gfn_offset
, unsigned long mask
)
1549 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1550 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1553 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1557 * kvm_arch_write_log_dirty - emulate dirty page logging
1558 * @vcpu: Guest mode vcpu
1560 * Emulate arch specific page modification logging for the
1563 int kvm_arch_write_log_dirty(struct kvm_vcpu
*vcpu
)
1565 if (kvm_x86_ops
->write_log_dirty
)
1566 return kvm_x86_ops
->write_log_dirty(vcpu
);
1571 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1572 struct kvm_memory_slot
*slot
, u64 gfn
)
1574 struct kvm_rmap_head
*rmap_head
;
1576 bool write_protected
= false;
1578 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1579 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1580 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1583 return write_protected
;
1586 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1588 struct kvm_memory_slot
*slot
;
1590 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1591 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1594 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1597 struct rmap_iterator iter
;
1600 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1601 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1603 drop_spte(kvm
, sptep
);
1610 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1611 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1614 return kvm_zap_rmapp(kvm
, rmap_head
);
1617 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1618 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1622 struct rmap_iterator iter
;
1625 pte_t
*ptep
= (pte_t
*)data
;
1628 WARN_ON(pte_huge(*ptep
));
1629 new_pfn
= pte_pfn(*ptep
);
1632 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1633 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1634 sptep
, *sptep
, gfn
, level
);
1638 if (pte_write(*ptep
)) {
1639 drop_spte(kvm
, sptep
);
1642 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1643 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1645 new_spte
&= ~PT_WRITABLE_MASK
;
1646 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1648 new_spte
= mark_spte_for_access_track(new_spte
);
1650 mmu_spte_clear_track_bits(sptep
);
1651 mmu_spte_set(sptep
, new_spte
);
1656 kvm_flush_remote_tlbs(kvm
);
1661 struct slot_rmap_walk_iterator
{
1663 struct kvm_memory_slot
*slot
;
1669 /* output fields. */
1671 struct kvm_rmap_head
*rmap
;
1674 /* private field. */
1675 struct kvm_rmap_head
*end_rmap
;
1679 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1681 iterator
->level
= level
;
1682 iterator
->gfn
= iterator
->start_gfn
;
1683 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1684 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1689 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1690 struct kvm_memory_slot
*slot
, int start_level
,
1691 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1693 iterator
->slot
= slot
;
1694 iterator
->start_level
= start_level
;
1695 iterator
->end_level
= end_level
;
1696 iterator
->start_gfn
= start_gfn
;
1697 iterator
->end_gfn
= end_gfn
;
1699 rmap_walk_init_level(iterator
, iterator
->start_level
);
1702 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1704 return !!iterator
->rmap
;
1707 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1709 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1710 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1714 if (++iterator
->level
> iterator
->end_level
) {
1715 iterator
->rmap
= NULL
;
1719 rmap_walk_init_level(iterator
, iterator
->level
);
1722 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1723 _start_gfn, _end_gfn, _iter_) \
1724 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1725 _end_level_, _start_gfn, _end_gfn); \
1726 slot_rmap_walk_okay(_iter_); \
1727 slot_rmap_walk_next(_iter_))
1729 static int kvm_handle_hva_range(struct kvm
*kvm
,
1730 unsigned long start
,
1733 int (*handler
)(struct kvm
*kvm
,
1734 struct kvm_rmap_head
*rmap_head
,
1735 struct kvm_memory_slot
*slot
,
1738 unsigned long data
))
1740 struct kvm_memslots
*slots
;
1741 struct kvm_memory_slot
*memslot
;
1742 struct slot_rmap_walk_iterator iterator
;
1746 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1747 slots
= __kvm_memslots(kvm
, i
);
1748 kvm_for_each_memslot(memslot
, slots
) {
1749 unsigned long hva_start
, hva_end
;
1750 gfn_t gfn_start
, gfn_end
;
1752 hva_start
= max(start
, memslot
->userspace_addr
);
1753 hva_end
= min(end
, memslot
->userspace_addr
+
1754 (memslot
->npages
<< PAGE_SHIFT
));
1755 if (hva_start
>= hva_end
)
1758 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1759 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1761 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1762 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1764 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1765 PT_MAX_HUGEPAGE_LEVEL
,
1766 gfn_start
, gfn_end
- 1,
1768 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1769 iterator
.gfn
, iterator
.level
, data
);
1776 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1778 int (*handler
)(struct kvm
*kvm
,
1779 struct kvm_rmap_head
*rmap_head
,
1780 struct kvm_memory_slot
*slot
,
1781 gfn_t gfn
, int level
,
1782 unsigned long data
))
1784 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1787 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1789 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1792 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1794 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1797 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1799 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1802 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1803 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1807 struct rmap_iterator
uninitialized_var(iter
);
1810 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1811 young
|= mmu_spte_age(sptep
);
1813 trace_kvm_age_page(gfn
, level
, slot
, young
);
1817 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1818 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1819 int level
, unsigned long data
)
1822 struct rmap_iterator iter
;
1824 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1825 if (is_accessed_spte(*sptep
))
1830 #define RMAP_RECYCLE_THRESHOLD 1000
1832 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1834 struct kvm_rmap_head
*rmap_head
;
1835 struct kvm_mmu_page
*sp
;
1837 sp
= page_header(__pa(spte
));
1839 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1841 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1842 kvm_flush_remote_tlbs(vcpu
->kvm
);
1845 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1847 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1850 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1852 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1856 static int is_empty_shadow_page(u64
*spt
)
1861 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1862 if (is_shadow_present_pte(*pos
)) {
1863 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1872 * This value is the sum of all of the kvm instances's
1873 * kvm->arch.n_used_mmu_pages values. We need a global,
1874 * aggregate version in order to make the slab shrinker
1877 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1879 kvm
->arch
.n_used_mmu_pages
+= nr
;
1880 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1883 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1885 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1886 hlist_del(&sp
->hash_link
);
1887 list_del(&sp
->link
);
1888 free_page((unsigned long)sp
->spt
);
1889 if (!sp
->role
.direct
)
1890 free_page((unsigned long)sp
->gfns
);
1891 kmem_cache_free(mmu_page_header_cache
, sp
);
1894 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1896 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1899 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1900 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1905 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1908 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1911 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1914 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1917 mmu_page_remove_parent_pte(sp
, parent_pte
);
1918 mmu_spte_clear_no_track(parent_pte
);
1921 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1923 struct kvm_mmu_page
*sp
;
1925 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1926 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1928 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1929 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1932 * The active_mmu_pages list is the FIFO list, do not move the
1933 * page until it is zapped. kvm_zap_obsolete_pages depends on
1934 * this feature. See the comments in kvm_zap_obsolete_pages().
1936 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1937 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1941 static void mark_unsync(u64
*spte
);
1942 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1945 struct rmap_iterator iter
;
1947 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1952 static void mark_unsync(u64
*spte
)
1954 struct kvm_mmu_page
*sp
;
1957 sp
= page_header(__pa(spte
));
1958 index
= spte
- sp
->spt
;
1959 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1961 if (sp
->unsync_children
++)
1963 kvm_mmu_mark_parents_unsync(sp
);
1966 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1967 struct kvm_mmu_page
*sp
)
1972 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1976 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1977 struct kvm_mmu_page
*sp
, u64
*spte
,
1983 #define KVM_PAGE_ARRAY_NR 16
1985 struct kvm_mmu_pages
{
1986 struct mmu_page_and_offset
{
1987 struct kvm_mmu_page
*sp
;
1989 } page
[KVM_PAGE_ARRAY_NR
];
1993 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1999 for (i
=0; i
< pvec
->nr
; i
++)
2000 if (pvec
->page
[i
].sp
== sp
)
2003 pvec
->page
[pvec
->nr
].sp
= sp
;
2004 pvec
->page
[pvec
->nr
].idx
= idx
;
2006 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
2009 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
2011 --sp
->unsync_children
;
2012 WARN_ON((int)sp
->unsync_children
< 0);
2013 __clear_bit(idx
, sp
->unsync_child_bitmap
);
2016 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2017 struct kvm_mmu_pages
*pvec
)
2019 int i
, ret
, nr_unsync_leaf
= 0;
2021 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
2022 struct kvm_mmu_page
*child
;
2023 u64 ent
= sp
->spt
[i
];
2025 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
2026 clear_unsync_child_bit(sp
, i
);
2030 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
2032 if (child
->unsync_children
) {
2033 if (mmu_pages_add(pvec
, child
, i
))
2036 ret
= __mmu_unsync_walk(child
, pvec
);
2038 clear_unsync_child_bit(sp
, i
);
2040 } else if (ret
> 0) {
2041 nr_unsync_leaf
+= ret
;
2044 } else if (child
->unsync
) {
2046 if (mmu_pages_add(pvec
, child
, i
))
2049 clear_unsync_child_bit(sp
, i
);
2052 return nr_unsync_leaf
;
2055 #define INVALID_INDEX (-1)
2057 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2058 struct kvm_mmu_pages
*pvec
)
2061 if (!sp
->unsync_children
)
2064 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2065 return __mmu_unsync_walk(sp
, pvec
);
2068 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2070 WARN_ON(!sp
->unsync
);
2071 trace_kvm_mmu_sync_page(sp
);
2073 --kvm
->stat
.mmu_unsync
;
2076 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2077 struct list_head
*invalid_list
);
2078 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2079 struct list_head
*invalid_list
);
2082 * NOTE: we should pay more attention on the zapped-obsolete page
2083 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2084 * since it has been deleted from active_mmu_pages but still can be found
2087 * for_each_valid_sp() has skipped that kind of pages.
2089 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2090 hlist_for_each_entry(_sp, \
2091 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2092 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2095 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2096 for_each_valid_sp(_kvm, _sp, _gfn) \
2097 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2099 /* @sp->gfn should be write-protected at the call site */
2100 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2101 struct list_head
*invalid_list
)
2103 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
2104 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2108 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
2109 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2116 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2117 struct list_head
*invalid_list
,
2118 bool remote_flush
, bool local_flush
)
2120 if (!list_empty(invalid_list
)) {
2121 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
2126 kvm_flush_remote_tlbs(vcpu
->kvm
);
2127 else if (local_flush
)
2128 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2131 #ifdef CONFIG_KVM_MMU_AUDIT
2132 #include "mmu_audit.c"
2134 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2135 static void mmu_audit_disable(void) { }
2138 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2140 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2143 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2144 struct list_head
*invalid_list
)
2146 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2147 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2150 /* @gfn should be write-protected at the call site */
2151 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2152 struct list_head
*invalid_list
)
2154 struct kvm_mmu_page
*s
;
2157 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2161 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2162 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2168 struct mmu_page_path
{
2169 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
];
2170 unsigned int idx
[PT64_ROOT_LEVEL
];
2173 #define for_each_sp(pvec, sp, parents, i) \
2174 for (i = mmu_pages_first(&pvec, &parents); \
2175 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2176 i = mmu_pages_next(&pvec, &parents, i))
2178 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2179 struct mmu_page_path
*parents
,
2184 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2185 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2186 unsigned idx
= pvec
->page
[n
].idx
;
2187 int level
= sp
->role
.level
;
2189 parents
->idx
[level
-1] = idx
;
2190 if (level
== PT_PAGE_TABLE_LEVEL
)
2193 parents
->parent
[level
-2] = sp
;
2199 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2200 struct mmu_page_path
*parents
)
2202 struct kvm_mmu_page
*sp
;
2208 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2210 sp
= pvec
->page
[0].sp
;
2211 level
= sp
->role
.level
;
2212 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2214 parents
->parent
[level
-2] = sp
;
2216 /* Also set up a sentinel. Further entries in pvec are all
2217 * children of sp, so this element is never overwritten.
2219 parents
->parent
[level
-1] = NULL
;
2220 return mmu_pages_next(pvec
, parents
, 0);
2223 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2225 struct kvm_mmu_page
*sp
;
2226 unsigned int level
= 0;
2229 unsigned int idx
= parents
->idx
[level
];
2230 sp
= parents
->parent
[level
];
2234 WARN_ON(idx
== INVALID_INDEX
);
2235 clear_unsync_child_bit(sp
, idx
);
2237 } while (!sp
->unsync_children
);
2240 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2241 struct kvm_mmu_page
*parent
)
2244 struct kvm_mmu_page
*sp
;
2245 struct mmu_page_path parents
;
2246 struct kvm_mmu_pages pages
;
2247 LIST_HEAD(invalid_list
);
2250 while (mmu_unsync_walk(parent
, &pages
)) {
2251 bool protected = false;
2253 for_each_sp(pages
, sp
, parents
, i
)
2254 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2257 kvm_flush_remote_tlbs(vcpu
->kvm
);
2261 for_each_sp(pages
, sp
, parents
, i
) {
2262 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2263 mmu_pages_clear_parents(&parents
);
2265 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2266 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2267 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2272 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2275 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2277 atomic_set(&sp
->write_flooding_count
, 0);
2280 static void clear_sp_write_flooding_count(u64
*spte
)
2282 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2284 __clear_sp_write_flooding_count(sp
);
2287 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2294 union kvm_mmu_page_role role
;
2296 struct kvm_mmu_page
*sp
;
2297 bool need_sync
= false;
2300 LIST_HEAD(invalid_list
);
2302 role
= vcpu
->arch
.mmu
.base_role
;
2304 role
.direct
= direct
;
2307 role
.access
= access
;
2308 if (!vcpu
->arch
.mmu
.direct_map
2309 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2310 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2311 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2312 role
.quadrant
= quadrant
;
2314 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2315 if (sp
->gfn
!= gfn
) {
2320 if (!need_sync
&& sp
->unsync
)
2323 if (sp
->role
.word
!= role
.word
)
2327 /* The page is good, but __kvm_sync_page might still end
2328 * up zapping it. If so, break in order to rebuild it.
2330 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2333 WARN_ON(!list_empty(&invalid_list
));
2334 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2337 if (sp
->unsync_children
)
2338 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2340 __clear_sp_write_flooding_count(sp
);
2341 trace_kvm_mmu_get_page(sp
, false);
2345 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2347 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2351 hlist_add_head(&sp
->hash_link
,
2352 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2355 * we should do write protection before syncing pages
2356 * otherwise the content of the synced shadow page may
2357 * be inconsistent with guest page table.
2359 account_shadowed(vcpu
->kvm
, sp
);
2360 if (level
== PT_PAGE_TABLE_LEVEL
&&
2361 rmap_write_protect(vcpu
, gfn
))
2362 kvm_flush_remote_tlbs(vcpu
->kvm
);
2364 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2365 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2367 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2368 clear_page(sp
->spt
);
2369 trace_kvm_mmu_get_page(sp
, true);
2371 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2373 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2374 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2378 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2379 struct kvm_vcpu
*vcpu
, u64 addr
)
2381 iterator
->addr
= addr
;
2382 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2383 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2385 if (iterator
->level
== PT64_ROOT_LEVEL
&&
2386 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
2387 !vcpu
->arch
.mmu
.direct_map
)
2390 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2391 iterator
->shadow_addr
2392 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2393 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2395 if (!iterator
->shadow_addr
)
2396 iterator
->level
= 0;
2400 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2402 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2405 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2406 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2410 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2413 if (is_last_spte(spte
, iterator
->level
)) {
2414 iterator
->level
= 0;
2418 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2422 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2424 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2427 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2428 struct kvm_mmu_page
*sp
)
2432 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2434 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2435 shadow_user_mask
| shadow_x_mask
;
2437 if (sp_ad_disabled(sp
))
2438 spte
|= shadow_acc_track_value
;
2440 spte
|= shadow_accessed_mask
;
2442 mmu_spte_set(sptep
, spte
);
2444 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2446 if (sp
->unsync_children
|| sp
->unsync
)
2450 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2451 unsigned direct_access
)
2453 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2454 struct kvm_mmu_page
*child
;
2457 * For the direct sp, if the guest pte's dirty bit
2458 * changed form clean to dirty, it will corrupt the
2459 * sp's access: allow writable in the read-only sp,
2460 * so we should update the spte at this point to get
2461 * a new sp with the correct access.
2463 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2464 if (child
->role
.access
== direct_access
)
2467 drop_parent_pte(child
, sptep
);
2468 kvm_flush_remote_tlbs(vcpu
->kvm
);
2472 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2476 struct kvm_mmu_page
*child
;
2479 if (is_shadow_present_pte(pte
)) {
2480 if (is_last_spte(pte
, sp
->role
.level
)) {
2481 drop_spte(kvm
, spte
);
2482 if (is_large_pte(pte
))
2485 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2486 drop_parent_pte(child
, spte
);
2491 if (is_mmio_spte(pte
))
2492 mmu_spte_clear_no_track(spte
);
2497 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2498 struct kvm_mmu_page
*sp
)
2502 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2503 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2506 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2509 struct rmap_iterator iter
;
2511 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2512 drop_parent_pte(sp
, sptep
);
2515 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2516 struct kvm_mmu_page
*parent
,
2517 struct list_head
*invalid_list
)
2520 struct mmu_page_path parents
;
2521 struct kvm_mmu_pages pages
;
2523 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2526 while (mmu_unsync_walk(parent
, &pages
)) {
2527 struct kvm_mmu_page
*sp
;
2529 for_each_sp(pages
, sp
, parents
, i
) {
2530 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2531 mmu_pages_clear_parents(&parents
);
2539 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2540 struct list_head
*invalid_list
)
2544 trace_kvm_mmu_prepare_zap_page(sp
);
2545 ++kvm
->stat
.mmu_shadow_zapped
;
2546 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2547 kvm_mmu_page_unlink_children(kvm
, sp
);
2548 kvm_mmu_unlink_parents(kvm
, sp
);
2550 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2551 unaccount_shadowed(kvm
, sp
);
2554 kvm_unlink_unsync_page(kvm
, sp
);
2555 if (!sp
->root_count
) {
2558 list_move(&sp
->link
, invalid_list
);
2559 kvm_mod_used_mmu_pages(kvm
, -1);
2561 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2564 * The obsolete pages can not be used on any vcpus.
2565 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2567 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2568 kvm_reload_remote_mmus(kvm
);
2571 sp
->role
.invalid
= 1;
2575 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2576 struct list_head
*invalid_list
)
2578 struct kvm_mmu_page
*sp
, *nsp
;
2580 if (list_empty(invalid_list
))
2584 * We need to make sure everyone sees our modifications to
2585 * the page tables and see changes to vcpu->mode here. The barrier
2586 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2587 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2589 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2590 * guest mode and/or lockless shadow page table walks.
2592 kvm_flush_remote_tlbs(kvm
);
2594 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2595 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2596 kvm_mmu_free_page(sp
);
2600 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2601 struct list_head
*invalid_list
)
2603 struct kvm_mmu_page
*sp
;
2605 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2608 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2609 struct kvm_mmu_page
, link
);
2610 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2616 * Changing the number of mmu pages allocated to the vm
2617 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2619 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2621 LIST_HEAD(invalid_list
);
2623 spin_lock(&kvm
->mmu_lock
);
2625 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2626 /* Need to free some mmu pages to achieve the goal. */
2627 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2628 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2631 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2632 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2635 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2637 spin_unlock(&kvm
->mmu_lock
);
2640 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2642 struct kvm_mmu_page
*sp
;
2643 LIST_HEAD(invalid_list
);
2646 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2648 spin_lock(&kvm
->mmu_lock
);
2649 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2650 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2653 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2655 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2656 spin_unlock(&kvm
->mmu_lock
);
2660 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2662 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2664 trace_kvm_mmu_unsync_page(sp
);
2665 ++vcpu
->kvm
->stat
.mmu_unsync
;
2668 kvm_mmu_mark_parents_unsync(sp
);
2671 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2674 struct kvm_mmu_page
*sp
;
2676 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2679 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2686 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2687 kvm_unsync_page(vcpu
, sp
);
2693 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2696 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2701 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2702 unsigned pte_access
, int level
,
2703 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2704 bool can_unsync
, bool host_writable
)
2708 struct kvm_mmu_page
*sp
;
2710 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2713 sp
= page_header(__pa(sptep
));
2714 if (sp_ad_disabled(sp
))
2715 spte
|= shadow_acc_track_value
;
2718 * For the EPT case, shadow_present_mask is 0 if hardware
2719 * supports exec-only page table entries. In that case,
2720 * ACC_USER_MASK and shadow_user_mask are used to represent
2721 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2723 spte
|= shadow_present_mask
;
2725 spte
|= spte_shadow_accessed_mask(spte
);
2727 if (pte_access
& ACC_EXEC_MASK
)
2728 spte
|= shadow_x_mask
;
2730 spte
|= shadow_nx_mask
;
2732 if (pte_access
& ACC_USER_MASK
)
2733 spte
|= shadow_user_mask
;
2735 if (level
> PT_PAGE_TABLE_LEVEL
)
2736 spte
|= PT_PAGE_SIZE_MASK
;
2738 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2739 kvm_is_mmio_pfn(pfn
));
2742 spte
|= SPTE_HOST_WRITEABLE
;
2744 pte_access
&= ~ACC_WRITE_MASK
;
2746 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2748 if (pte_access
& ACC_WRITE_MASK
) {
2751 * Other vcpu creates new sp in the window between
2752 * mapping_level() and acquiring mmu-lock. We can
2753 * allow guest to retry the access, the mapping can
2754 * be fixed if guest refault.
2756 if (level
> PT_PAGE_TABLE_LEVEL
&&
2757 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2760 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2763 * Optimization: for pte sync, if spte was writable the hash
2764 * lookup is unnecessary (and expensive). Write protection
2765 * is responsibility of mmu_get_page / kvm_sync_page.
2766 * Same reasoning can be applied to dirty page accounting.
2768 if (!can_unsync
&& is_writable_pte(*sptep
))
2771 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2772 pgprintk("%s: found shadow page for %llx, marking ro\n",
2775 pte_access
&= ~ACC_WRITE_MASK
;
2776 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2780 if (pte_access
& ACC_WRITE_MASK
) {
2781 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2782 spte
|= spte_shadow_dirty_mask(spte
);
2786 spte
= mark_spte_for_access_track(spte
);
2789 if (mmu_spte_update(sptep
, spte
))
2790 kvm_flush_remote_tlbs(vcpu
->kvm
);
2795 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2796 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2797 bool speculative
, bool host_writable
)
2799 int was_rmapped
= 0;
2801 bool emulate
= false;
2803 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2804 *sptep
, write_fault
, gfn
);
2806 if (is_shadow_present_pte(*sptep
)) {
2808 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2809 * the parent of the now unreachable PTE.
2811 if (level
> PT_PAGE_TABLE_LEVEL
&&
2812 !is_large_pte(*sptep
)) {
2813 struct kvm_mmu_page
*child
;
2816 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2817 drop_parent_pte(child
, sptep
);
2818 kvm_flush_remote_tlbs(vcpu
->kvm
);
2819 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2820 pgprintk("hfn old %llx new %llx\n",
2821 spte_to_pfn(*sptep
), pfn
);
2822 drop_spte(vcpu
->kvm
, sptep
);
2823 kvm_flush_remote_tlbs(vcpu
->kvm
);
2828 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2829 true, host_writable
)) {
2832 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2835 if (unlikely(is_mmio_spte(*sptep
)))
2838 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2839 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2840 is_large_pte(*sptep
)? "2MB" : "4kB",
2841 *sptep
& PT_WRITABLE_MASK
? "RW" : "R", gfn
,
2843 if (!was_rmapped
&& is_large_pte(*sptep
))
2844 ++vcpu
->kvm
->stat
.lpages
;
2846 if (is_shadow_present_pte(*sptep
)) {
2848 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2849 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2850 rmap_recycle(vcpu
, sptep
, gfn
);
2854 kvm_release_pfn_clean(pfn
);
2859 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2862 struct kvm_memory_slot
*slot
;
2864 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2866 return KVM_PFN_ERR_FAULT
;
2868 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2871 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2872 struct kvm_mmu_page
*sp
,
2873 u64
*start
, u64
*end
)
2875 struct page
*pages
[PTE_PREFETCH_NUM
];
2876 struct kvm_memory_slot
*slot
;
2877 unsigned access
= sp
->role
.access
;
2881 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2882 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2886 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2890 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2891 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2892 page_to_pfn(pages
[i
]), true, true);
2897 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2898 struct kvm_mmu_page
*sp
, u64
*sptep
)
2900 u64
*spte
, *start
= NULL
;
2903 WARN_ON(!sp
->role
.direct
);
2905 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2908 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2909 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2912 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2920 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2922 struct kvm_mmu_page
*sp
;
2924 sp
= page_header(__pa(sptep
));
2927 * Without accessed bits, there's no way to distinguish between
2928 * actually accessed translations and prefetched, so disable pte
2929 * prefetch if accessed bits aren't available.
2931 if (sp_ad_disabled(sp
))
2934 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2937 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2940 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2941 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2943 struct kvm_shadow_walk_iterator iterator
;
2944 struct kvm_mmu_page
*sp
;
2948 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2951 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2952 if (iterator
.level
== level
) {
2953 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2954 write
, level
, gfn
, pfn
, prefault
,
2956 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2957 ++vcpu
->stat
.pf_fixed
;
2961 drop_large_spte(vcpu
, iterator
.sptep
);
2962 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2963 u64 base_addr
= iterator
.addr
;
2965 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2966 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2967 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2968 iterator
.level
- 1, 1, ACC_ALL
);
2970 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2976 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2980 info
.si_signo
= SIGBUS
;
2982 info
.si_code
= BUS_MCEERR_AR
;
2983 info
.si_addr
= (void __user
*)address
;
2984 info
.si_addr_lsb
= PAGE_SHIFT
;
2986 send_sig_info(SIGBUS
, &info
, tsk
);
2989 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2992 * Do not cache the mmio info caused by writing the readonly gfn
2993 * into the spte otherwise read access on readonly gfn also can
2994 * caused mmio page fault and treat it as mmio access.
2995 * Return 1 to tell kvm to emulate it.
2997 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3000 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3001 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3008 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
3009 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
3012 kvm_pfn_t pfn
= *pfnp
;
3014 int level
= *levelp
;
3017 * Check if it's a transparent hugepage. If this would be an
3018 * hugetlbfs page, level wouldn't be set to
3019 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3022 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
3023 level
== PT_PAGE_TABLE_LEVEL
&&
3024 PageTransCompoundMap(pfn_to_page(pfn
)) &&
3025 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
3028 * mmu_notifier_retry was successful and we hold the
3029 * mmu_lock here, so the pmd can't become splitting
3030 * from under us, and in turn
3031 * __split_huge_page_refcount() can't run from under
3032 * us and we can safely transfer the refcount from
3033 * PG_tail to PG_head as we switch the pfn to tail to
3036 *levelp
= level
= PT_DIRECTORY_LEVEL
;
3037 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
3038 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
3042 kvm_release_pfn_clean(pfn
);
3050 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3051 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
3053 /* The pfn is invalid, report the error! */
3054 if (unlikely(is_error_pfn(pfn
))) {
3055 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3059 if (unlikely(is_noslot_pfn(pfn
)))
3060 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
3065 static bool page_fault_can_be_fast(u32 error_code
)
3068 * Do not fix the mmio spte with invalid generation number which
3069 * need to be updated by slow page fault path.
3071 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3074 /* See if the page fault is due to an NX violation */
3075 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3076 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3080 * #PF can be fast if:
3081 * 1. The shadow page table entry is not present, which could mean that
3082 * the fault is potentially caused by access tracking (if enabled).
3083 * 2. The shadow page table entry is present and the fault
3084 * is caused by write-protect, that means we just need change the W
3085 * bit of the spte which can be done out of mmu-lock.
3087 * However, if access tracking is disabled we know that a non-present
3088 * page must be a genuine page fault where we have to create a new SPTE.
3089 * So, if access tracking is disabled, we return true only for write
3090 * accesses to a present page.
3093 return shadow_acc_track_mask
!= 0 ||
3094 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3095 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3099 * Returns true if the SPTE was fixed successfully. Otherwise,
3100 * someone else modified the SPTE from its original value.
3103 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3104 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3108 WARN_ON(!sp
->role
.direct
);
3111 * Theoretically we could also set dirty bit (and flush TLB) here in
3112 * order to eliminate unnecessary PML logging. See comments in
3113 * set_spte. But fast_page_fault is very unlikely to happen with PML
3114 * enabled, so we do not do this. This might result in the same GPA
3115 * to be logged in PML buffer again when the write really happens, and
3116 * eventually to be called by mark_page_dirty twice. But it's also no
3117 * harm. This also avoids the TLB flush needed after setting dirty bit
3118 * so non-PML cases won't be impacted.
3120 * Compare with set_spte where instead shadow_dirty_mask is set.
3122 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3125 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3127 * The gfn of direct spte is stable since it is
3128 * calculated by sp->gfn.
3130 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3131 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3137 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3139 if (fault_err_code
& PFERR_FETCH_MASK
)
3140 return is_executable_pte(spte
);
3142 if (fault_err_code
& PFERR_WRITE_MASK
)
3143 return is_writable_pte(spte
);
3145 /* Fault was on Read access */
3146 return spte
& PT_PRESENT_MASK
;
3151 * - true: let the vcpu to access on the same address again.
3152 * - false: let the real page fault path to fix it.
3154 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
3157 struct kvm_shadow_walk_iterator iterator
;
3158 struct kvm_mmu_page
*sp
;
3159 bool fault_handled
= false;
3161 uint retry_count
= 0;
3163 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3166 if (!page_fault_can_be_fast(error_code
))
3169 walk_shadow_page_lockless_begin(vcpu
);
3174 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
3175 if (!is_shadow_present_pte(spte
) ||
3176 iterator
.level
< level
)
3179 sp
= page_header(__pa(iterator
.sptep
));
3180 if (!is_last_spte(spte
, sp
->role
.level
))
3184 * Check whether the memory access that caused the fault would
3185 * still cause it if it were to be performed right now. If not,
3186 * then this is a spurious fault caused by TLB lazily flushed,
3187 * or some other CPU has already fixed the PTE after the
3188 * current CPU took the fault.
3190 * Need not check the access of upper level table entries since
3191 * they are always ACC_ALL.
3193 if (is_access_allowed(error_code
, spte
)) {
3194 fault_handled
= true;
3200 if (is_access_track_spte(spte
))
3201 new_spte
= restore_acc_track_spte(new_spte
);
3204 * Currently, to simplify the code, write-protection can
3205 * be removed in the fast path only if the SPTE was
3206 * write-protected for dirty-logging or access tracking.
3208 if ((error_code
& PFERR_WRITE_MASK
) &&
3209 spte_can_locklessly_be_made_writable(spte
))
3211 new_spte
|= PT_WRITABLE_MASK
;
3214 * Do not fix write-permission on the large spte. Since
3215 * we only dirty the first page into the dirty-bitmap in
3216 * fast_pf_fix_direct_spte(), other pages are missed
3217 * if its slot has dirty logging enabled.
3219 * Instead, we let the slow page fault path create a
3220 * normal spte to fix the access.
3222 * See the comments in kvm_arch_commit_memory_region().
3224 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3228 /* Verify that the fault can be handled in the fast path */
3229 if (new_spte
== spte
||
3230 !is_access_allowed(error_code
, new_spte
))
3234 * Currently, fast page fault only works for direct mapping
3235 * since the gfn is not stable for indirect shadow page. See
3236 * Documentation/virtual/kvm/locking.txt to get more detail.
3238 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3239 iterator
.sptep
, spte
,
3244 if (++retry_count
> 4) {
3245 printk_once(KERN_WARNING
3246 "kvm: Fast #PF retrying more than 4 times.\n");
3252 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3253 spte
, fault_handled
);
3254 walk_shadow_page_lockless_end(vcpu
);
3256 return fault_handled
;
3259 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3260 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3261 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3263 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3264 gfn_t gfn
, bool prefault
)
3268 bool force_pt_level
= false;
3270 unsigned long mmu_seq
;
3271 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3273 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3274 if (likely(!force_pt_level
)) {
3276 * This path builds a PAE pagetable - so we can map
3277 * 2mb pages at maximum. Therefore check if the level
3278 * is larger than that.
3280 if (level
> PT_DIRECTORY_LEVEL
)
3281 level
= PT_DIRECTORY_LEVEL
;
3283 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3286 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3289 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3292 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3295 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3298 spin_lock(&vcpu
->kvm
->mmu_lock
);
3299 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3301 make_mmu_pages_available(vcpu
);
3302 if (likely(!force_pt_level
))
3303 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3304 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3305 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3310 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3311 kvm_release_pfn_clean(pfn
);
3316 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3319 struct kvm_mmu_page
*sp
;
3320 LIST_HEAD(invalid_list
);
3322 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3325 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
3326 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
3327 vcpu
->arch
.mmu
.direct_map
)) {
3328 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3330 spin_lock(&vcpu
->kvm
->mmu_lock
);
3331 sp
= page_header(root
);
3333 if (!sp
->root_count
&& sp
->role
.invalid
) {
3334 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3335 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3337 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3338 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3342 spin_lock(&vcpu
->kvm
->mmu_lock
);
3343 for (i
= 0; i
< 4; ++i
) {
3344 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3347 root
&= PT64_BASE_ADDR_MASK
;
3348 sp
= page_header(root
);
3350 if (!sp
->root_count
&& sp
->role
.invalid
)
3351 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3354 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3356 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3357 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3358 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3361 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3365 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3366 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3373 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3375 struct kvm_mmu_page
*sp
;
3378 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3379 spin_lock(&vcpu
->kvm
->mmu_lock
);
3380 make_mmu_pages_available(vcpu
);
3381 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
, 1, ACC_ALL
);
3383 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3384 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3385 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3386 for (i
= 0; i
< 4; ++i
) {
3387 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3389 MMU_WARN_ON(VALID_PAGE(root
));
3390 spin_lock(&vcpu
->kvm
->mmu_lock
);
3391 make_mmu_pages_available(vcpu
);
3392 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3393 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3394 root
= __pa(sp
->spt
);
3396 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3397 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3399 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3406 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3408 struct kvm_mmu_page
*sp
;
3413 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3415 if (mmu_check_root(vcpu
, root_gfn
))
3419 * Do we shadow a long mode page table? If so we need to
3420 * write-protect the guests page table root.
3422 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3423 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3425 MMU_WARN_ON(VALID_PAGE(root
));
3427 spin_lock(&vcpu
->kvm
->mmu_lock
);
3428 make_mmu_pages_available(vcpu
);
3429 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3431 root
= __pa(sp
->spt
);
3433 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3434 vcpu
->arch
.mmu
.root_hpa
= root
;
3439 * We shadow a 32 bit page table. This may be a legacy 2-level
3440 * or a PAE 3-level page table. In either case we need to be aware that
3441 * the shadow page table may be a PAE or a long mode page table.
3443 pm_mask
= PT_PRESENT_MASK
;
3444 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3445 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3447 for (i
= 0; i
< 4; ++i
) {
3448 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3450 MMU_WARN_ON(VALID_PAGE(root
));
3451 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3452 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3453 if (!(pdptr
& PT_PRESENT_MASK
)) {
3454 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3457 root_gfn
= pdptr
>> PAGE_SHIFT
;
3458 if (mmu_check_root(vcpu
, root_gfn
))
3461 spin_lock(&vcpu
->kvm
->mmu_lock
);
3462 make_mmu_pages_available(vcpu
);
3463 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3465 root
= __pa(sp
->spt
);
3467 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3469 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3471 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3474 * If we shadow a 32 bit page table with a long mode page
3475 * table we enter this path.
3477 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3478 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3480 * The additional page necessary for this is only
3481 * allocated on demand.
3486 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3487 if (lm_root
== NULL
)
3490 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3492 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3495 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3501 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3503 if (vcpu
->arch
.mmu
.direct_map
)
3504 return mmu_alloc_direct_roots(vcpu
);
3506 return mmu_alloc_shadow_roots(vcpu
);
3509 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3512 struct kvm_mmu_page
*sp
;
3514 if (vcpu
->arch
.mmu
.direct_map
)
3517 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3520 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3521 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3522 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3523 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3524 sp
= page_header(root
);
3525 mmu_sync_children(vcpu
, sp
);
3526 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3529 for (i
= 0; i
< 4; ++i
) {
3530 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3532 if (root
&& VALID_PAGE(root
)) {
3533 root
&= PT64_BASE_ADDR_MASK
;
3534 sp
= page_header(root
);
3535 mmu_sync_children(vcpu
, sp
);
3538 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3541 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3543 spin_lock(&vcpu
->kvm
->mmu_lock
);
3544 mmu_sync_roots(vcpu
);
3545 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3547 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3549 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3550 u32 access
, struct x86_exception
*exception
)
3553 exception
->error_code
= 0;
3557 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3559 struct x86_exception
*exception
)
3562 exception
->error_code
= 0;
3563 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3567 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3569 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3571 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3572 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3575 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3577 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3580 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3582 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3585 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3588 return vcpu_match_mmio_gpa(vcpu
, addr
);
3590 return vcpu_match_mmio_gva(vcpu
, addr
);
3593 /* return true if reserved bit is detected on spte. */
3595 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3597 struct kvm_shadow_walk_iterator iterator
;
3598 u64 sptes
[PT64_ROOT_LEVEL
], spte
= 0ull;
3600 bool reserved
= false;
3602 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3605 walk_shadow_page_lockless_begin(vcpu
);
3607 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3608 leaf
= root
= iterator
.level
;
3609 shadow_walk_okay(&iterator
);
3610 __shadow_walk_next(&iterator
, spte
)) {
3611 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3613 sptes
[leaf
- 1] = spte
;
3616 if (!is_shadow_present_pte(spte
))
3619 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3623 walk_shadow_page_lockless_end(vcpu
);
3626 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3628 while (root
> leaf
) {
3629 pr_err("------ spte 0x%llx level %d.\n",
3630 sptes
[root
- 1], root
);
3639 int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3644 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3645 return RET_MMIO_PF_EMULATE
;
3647 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3648 if (WARN_ON(reserved
))
3649 return RET_MMIO_PF_BUG
;
3651 if (is_mmio_spte(spte
)) {
3652 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3653 unsigned access
= get_mmio_spte_access(spte
);
3655 if (!check_mmio_spte(vcpu
, spte
))
3656 return RET_MMIO_PF_INVALID
;
3661 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3662 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3663 return RET_MMIO_PF_EMULATE
;
3667 * If the page table is zapped by other cpus, let CPU fault again on
3670 return RET_MMIO_PF_RETRY
;
3672 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3674 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3675 u32 error_code
, gfn_t gfn
)
3677 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3680 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3681 !(error_code
& PFERR_WRITE_MASK
))
3685 * guest is writing the page which is write tracked which can
3686 * not be fixed by page fault handler.
3688 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3694 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3696 struct kvm_shadow_walk_iterator iterator
;
3699 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3702 walk_shadow_page_lockless_begin(vcpu
);
3703 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3704 clear_sp_write_flooding_count(iterator
.sptep
);
3705 if (!is_shadow_present_pte(spte
))
3708 walk_shadow_page_lockless_end(vcpu
);
3711 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3712 u32 error_code
, bool prefault
)
3714 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3717 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3719 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3722 r
= mmu_topup_memory_caches(vcpu
);
3726 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3729 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3730 error_code
, gfn
, prefault
);
3733 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3735 struct kvm_arch_async_pf arch
;
3737 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3739 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3740 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3742 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3745 bool kvm_can_do_async_pf(struct kvm_vcpu
*vcpu
)
3747 if (unlikely(!lapic_in_kernel(vcpu
) ||
3748 kvm_event_needs_reinjection(vcpu
)))
3751 if (is_guest_mode(vcpu
))
3754 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3757 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3758 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3760 struct kvm_memory_slot
*slot
;
3763 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3765 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3767 return false; /* *pfn has correct page already */
3769 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3770 trace_kvm_try_async_get_page(gva
, gfn
);
3771 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3772 trace_kvm_async_pf_doublefault(gva
, gfn
);
3773 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3775 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3779 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3784 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3786 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3788 gfn
&= ~(page_num
- 1);
3790 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3793 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3799 bool force_pt_level
;
3800 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3801 unsigned long mmu_seq
;
3802 int write
= error_code
& PFERR_WRITE_MASK
;
3805 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3807 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3810 r
= mmu_topup_memory_caches(vcpu
);
3814 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3815 PT_DIRECTORY_LEVEL
);
3816 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3817 if (likely(!force_pt_level
)) {
3818 if (level
> PT_DIRECTORY_LEVEL
&&
3819 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3820 level
= PT_DIRECTORY_LEVEL
;
3821 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3824 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3827 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3830 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3833 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3836 spin_lock(&vcpu
->kvm
->mmu_lock
);
3837 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3839 make_mmu_pages_available(vcpu
);
3840 if (likely(!force_pt_level
))
3841 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3842 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3843 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3848 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3849 kvm_release_pfn_clean(pfn
);
3853 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3854 struct kvm_mmu
*context
)
3856 context
->page_fault
= nonpaging_page_fault
;
3857 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3858 context
->sync_page
= nonpaging_sync_page
;
3859 context
->invlpg
= nonpaging_invlpg
;
3860 context
->update_pte
= nonpaging_update_pte
;
3861 context
->root_level
= 0;
3862 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3863 context
->root_hpa
= INVALID_PAGE
;
3864 context
->direct_map
= true;
3865 context
->nx
= false;
3868 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3870 mmu_free_roots(vcpu
);
3873 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3875 return kvm_read_cr3(vcpu
);
3878 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3879 struct x86_exception
*fault
)
3881 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3884 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3885 unsigned access
, int *nr_present
)
3887 if (unlikely(is_mmio_spte(*sptep
))) {
3888 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3889 mmu_spte_clear_no_track(sptep
);
3894 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3901 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3902 unsigned level
, unsigned gpte
)
3905 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3906 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3907 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3909 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3912 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3913 * If it is clear, there are no large pages at this level, so clear
3914 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3916 gpte
&= level
- mmu
->last_nonleaf_level
;
3918 return gpte
& PT_PAGE_SIZE_MASK
;
3921 #define PTTYPE_EPT 18 /* arbitrary */
3922 #define PTTYPE PTTYPE_EPT
3923 #include "paging_tmpl.h"
3927 #include "paging_tmpl.h"
3931 #include "paging_tmpl.h"
3935 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3936 struct rsvd_bits_validate
*rsvd_check
,
3937 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
3940 u64 exb_bit_rsvd
= 0;
3941 u64 gbpages_bit_rsvd
= 0;
3942 u64 nonleaf_bit8_rsvd
= 0;
3944 rsvd_check
->bad_mt_xwr
= 0;
3947 exb_bit_rsvd
= rsvd_bits(63, 63);
3949 gbpages_bit_rsvd
= rsvd_bits(7, 7);
3952 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3953 * leaf entries) on AMD CPUs only.
3956 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
3959 case PT32_ROOT_LEVEL
:
3960 /* no rsvd bits for 2 level 4K page table entries */
3961 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
3962 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
3963 rsvd_check
->rsvd_bits_mask
[1][0] =
3964 rsvd_check
->rsvd_bits_mask
[0][0];
3967 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
3971 if (is_cpuid_PSE36())
3972 /* 36bits PSE 4MB page */
3973 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3975 /* 32 bits PSE 4MB page */
3976 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3978 case PT32E_ROOT_LEVEL
:
3979 rsvd_check
->rsvd_bits_mask
[0][2] =
3980 rsvd_bits(maxphyaddr
, 63) |
3981 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3982 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3983 rsvd_bits(maxphyaddr
, 62); /* PDE */
3984 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3985 rsvd_bits(maxphyaddr
, 62); /* PTE */
3986 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3987 rsvd_bits(maxphyaddr
, 62) |
3988 rsvd_bits(13, 20); /* large page */
3989 rsvd_check
->rsvd_bits_mask
[1][0] =
3990 rsvd_check
->rsvd_bits_mask
[0][0];
3992 case PT64_ROOT_LEVEL
:
3993 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3994 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3995 rsvd_bits(maxphyaddr
, 51);
3996 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3997 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
3998 rsvd_bits(maxphyaddr
, 51);
3999 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4000 rsvd_bits(maxphyaddr
, 51);
4001 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4002 rsvd_bits(maxphyaddr
, 51);
4003 rsvd_check
->rsvd_bits_mask
[1][3] =
4004 rsvd_check
->rsvd_bits_mask
[0][3];
4005 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
4006 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
4008 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4009 rsvd_bits(maxphyaddr
, 51) |
4010 rsvd_bits(13, 20); /* large page */
4011 rsvd_check
->rsvd_bits_mask
[1][0] =
4012 rsvd_check
->rsvd_bits_mask
[0][0];
4017 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4018 struct kvm_mmu
*context
)
4020 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4021 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4022 context
->nx
, guest_cpuid_has_gbpages(vcpu
),
4023 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
4027 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4028 int maxphyaddr
, bool execonly
)
4032 rsvd_check
->rsvd_bits_mask
[0][3] =
4033 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4034 rsvd_check
->rsvd_bits_mask
[0][2] =
4035 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4036 rsvd_check
->rsvd_bits_mask
[0][1] =
4037 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4038 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4041 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4042 rsvd_check
->rsvd_bits_mask
[1][2] =
4043 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4044 rsvd_check
->rsvd_bits_mask
[1][1] =
4045 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4046 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4048 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4049 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4050 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4051 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4052 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4054 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4055 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4057 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4060 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4061 struct kvm_mmu
*context
, bool execonly
)
4063 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4064 cpuid_maxphyaddr(vcpu
), execonly
);
4068 * the page table on host is the shadow page table for the page
4069 * table in guest or amd nested guest, its mmu features completely
4070 * follow the features in guest.
4073 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4075 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
4078 * Passing "true" to the last argument is okay; it adds a check
4079 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4081 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4082 boot_cpu_data
.x86_phys_bits
,
4083 context
->shadow_root_level
, uses_nx
,
4084 guest_cpuid_has_gbpages(vcpu
), is_pse(vcpu
),
4087 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4089 static inline bool boot_cpu_is_amd(void)
4091 WARN_ON_ONCE(!tdp_enabled
);
4092 return shadow_x_mask
== 0;
4096 * the direct page table on host, use as much mmu features as
4097 * possible, however, kvm currently does not do execution-protection.
4100 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4101 struct kvm_mmu
*context
)
4103 if (boot_cpu_is_amd())
4104 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
4105 boot_cpu_data
.x86_phys_bits
,
4106 context
->shadow_root_level
, false,
4107 boot_cpu_has(X86_FEATURE_GBPAGES
),
4110 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4111 boot_cpu_data
.x86_phys_bits
,
4117 * as the comments in reset_shadow_zero_bits_mask() except it
4118 * is the shadow page table for intel nested guest.
4121 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4122 struct kvm_mmu
*context
, bool execonly
)
4124 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4125 boot_cpu_data
.x86_phys_bits
, execonly
);
4128 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4129 struct kvm_mmu
*mmu
, bool ept
)
4131 unsigned bit
, byte
, pfec
;
4133 bool fault
, x
, w
, u
, wf
, uf
, ff
, smapf
, cr4_smap
, cr4_smep
, smap
= 0;
4135 cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4136 cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4137 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4140 wf
= pfec
& PFERR_WRITE_MASK
;
4141 uf
= pfec
& PFERR_USER_MASK
;
4142 ff
= pfec
& PFERR_FETCH_MASK
;
4144 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
4145 * subject to SMAP restrictions, and cleared otherwise. The
4146 * bit is only meaningful if the SMAP bit is set in CR4.
4148 smapf
= !(pfec
& PFERR_RSVD_MASK
);
4149 for (bit
= 0; bit
< 8; ++bit
) {
4150 x
= bit
& ACC_EXEC_MASK
;
4151 w
= bit
& ACC_WRITE_MASK
;
4152 u
= bit
& ACC_USER_MASK
;
4155 /* Not really needed: !nx will cause pte.nx to fault */
4157 /* Allow supervisor writes if !cr0.wp */
4158 w
|= !is_write_protection(vcpu
) && !uf
;
4159 /* Disallow supervisor fetches of user code if cr4.smep */
4160 x
&= !(cr4_smep
&& u
&& !uf
);
4163 * SMAP:kernel-mode data accesses from user-mode
4164 * mappings should fault. A fault is considered
4165 * as a SMAP violation if all of the following
4166 * conditions are ture:
4167 * - X86_CR4_SMAP is set in CR4
4168 * - A user page is accessed
4169 * - Page fault in kernel mode
4170 * - if CPL = 3 or X86_EFLAGS_AC is clear
4172 * Here, we cover the first three conditions.
4173 * The fourth is computed dynamically in
4174 * permission_fault() and is in smapf.
4176 * Also, SMAP does not affect instruction
4177 * fetches, add the !ff check here to make it
4180 smap
= cr4_smap
&& u
&& !uf
&& !ff
;
4183 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
) ||
4185 map
|= fault
<< bit
;
4187 mmu
->permissions
[byte
] = map
;
4192 * PKU is an additional mechanism by which the paging controls access to
4193 * user-mode addresses based on the value in the PKRU register. Protection
4194 * key violations are reported through a bit in the page fault error code.
4195 * Unlike other bits of the error code, the PK bit is not known at the
4196 * call site of e.g. gva_to_gpa; it must be computed directly in
4197 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4198 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4200 * In particular the following conditions come from the error code, the
4201 * page tables and the machine state:
4202 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4203 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4204 * - PK is always zero if U=0 in the page tables
4205 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4207 * The PKRU bitmask caches the result of these four conditions. The error
4208 * code (minus the P bit) and the page table's U bit form an index into the
4209 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4210 * with the two bits of the PKRU register corresponding to the protection key.
4211 * For the first three conditions above the bits will be 00, thus masking
4212 * away both AD and WD. For all reads or if the last condition holds, WD
4213 * only will be masked away.
4215 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4226 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4227 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4232 wp
= is_write_protection(vcpu
);
4234 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4235 unsigned pfec
, pkey_bits
;
4236 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4239 ff
= pfec
& PFERR_FETCH_MASK
;
4240 uf
= pfec
& PFERR_USER_MASK
;
4241 wf
= pfec
& PFERR_WRITE_MASK
;
4243 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4244 pte_user
= pfec
& PFERR_RSVD_MASK
;
4247 * Only need to check the access which is not an
4248 * instruction fetch and is to a user page.
4250 check_pkey
= (!ff
&& pte_user
);
4252 * write access is controlled by PKRU if it is a
4253 * user access or CR0.WP = 1.
4255 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4257 /* PKRU.AD stops both read and write access. */
4258 pkey_bits
= !!check_pkey
;
4259 /* PKRU.WD stops write access. */
4260 pkey_bits
|= (!!check_write
) << 1;
4262 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4266 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4268 unsigned root_level
= mmu
->root_level
;
4270 mmu
->last_nonleaf_level
= root_level
;
4271 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4272 mmu
->last_nonleaf_level
++;
4275 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4276 struct kvm_mmu
*context
,
4279 context
->nx
= is_nx(vcpu
);
4280 context
->root_level
= level
;
4282 reset_rsvds_bits_mask(vcpu
, context
);
4283 update_permission_bitmask(vcpu
, context
, false);
4284 update_pkru_bitmask(vcpu
, context
, false);
4285 update_last_nonleaf_level(vcpu
, context
);
4287 MMU_WARN_ON(!is_pae(vcpu
));
4288 context
->page_fault
= paging64_page_fault
;
4289 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4290 context
->sync_page
= paging64_sync_page
;
4291 context
->invlpg
= paging64_invlpg
;
4292 context
->update_pte
= paging64_update_pte
;
4293 context
->shadow_root_level
= level
;
4294 context
->root_hpa
= INVALID_PAGE
;
4295 context
->direct_map
= false;
4298 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4299 struct kvm_mmu
*context
)
4301 paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
4304 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4305 struct kvm_mmu
*context
)
4307 context
->nx
= false;
4308 context
->root_level
= PT32_ROOT_LEVEL
;
4310 reset_rsvds_bits_mask(vcpu
, context
);
4311 update_permission_bitmask(vcpu
, context
, false);
4312 update_pkru_bitmask(vcpu
, context
, false);
4313 update_last_nonleaf_level(vcpu
, context
);
4315 context
->page_fault
= paging32_page_fault
;
4316 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4317 context
->sync_page
= paging32_sync_page
;
4318 context
->invlpg
= paging32_invlpg
;
4319 context
->update_pte
= paging32_update_pte
;
4320 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4321 context
->root_hpa
= INVALID_PAGE
;
4322 context
->direct_map
= false;
4325 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4326 struct kvm_mmu
*context
)
4328 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4331 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4333 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4335 context
->base_role
.word
= 0;
4336 context
->base_role
.smm
= is_smm(vcpu
);
4337 context
->base_role
.ad_disabled
= (shadow_accessed_mask
== 0);
4338 context
->page_fault
= tdp_page_fault
;
4339 context
->sync_page
= nonpaging_sync_page
;
4340 context
->invlpg
= nonpaging_invlpg
;
4341 context
->update_pte
= nonpaging_update_pte
;
4342 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4343 context
->root_hpa
= INVALID_PAGE
;
4344 context
->direct_map
= true;
4345 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4346 context
->get_cr3
= get_cr3
;
4347 context
->get_pdptr
= kvm_pdptr_read
;
4348 context
->inject_page_fault
= kvm_inject_page_fault
;
4350 if (!is_paging(vcpu
)) {
4351 context
->nx
= false;
4352 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4353 context
->root_level
= 0;
4354 } else if (is_long_mode(vcpu
)) {
4355 context
->nx
= is_nx(vcpu
);
4356 context
->root_level
= PT64_ROOT_LEVEL
;
4357 reset_rsvds_bits_mask(vcpu
, context
);
4358 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4359 } else if (is_pae(vcpu
)) {
4360 context
->nx
= is_nx(vcpu
);
4361 context
->root_level
= PT32E_ROOT_LEVEL
;
4362 reset_rsvds_bits_mask(vcpu
, context
);
4363 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4365 context
->nx
= false;
4366 context
->root_level
= PT32_ROOT_LEVEL
;
4367 reset_rsvds_bits_mask(vcpu
, context
);
4368 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4371 update_permission_bitmask(vcpu
, context
, false);
4372 update_pkru_bitmask(vcpu
, context
, false);
4373 update_last_nonleaf_level(vcpu
, context
);
4374 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4377 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4379 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4380 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4381 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4383 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4385 if (!is_paging(vcpu
))
4386 nonpaging_init_context(vcpu
, context
);
4387 else if (is_long_mode(vcpu
))
4388 paging64_init_context(vcpu
, context
);
4389 else if (is_pae(vcpu
))
4390 paging32E_init_context(vcpu
, context
);
4392 paging32_init_context(vcpu
, context
);
4394 context
->base_role
.nxe
= is_nx(vcpu
);
4395 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4396 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4397 context
->base_role
.smep_andnot_wp
4398 = smep
&& !is_write_protection(vcpu
);
4399 context
->base_role
.smap_andnot_wp
4400 = smap
&& !is_write_protection(vcpu
);
4401 context
->base_role
.smm
= is_smm(vcpu
);
4402 reset_shadow_zero_bits_mask(vcpu
, context
);
4404 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4406 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4407 bool accessed_dirty
)
4409 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4411 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4413 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4416 context
->ept_ad
= accessed_dirty
;
4417 context
->page_fault
= ept_page_fault
;
4418 context
->gva_to_gpa
= ept_gva_to_gpa
;
4419 context
->sync_page
= ept_sync_page
;
4420 context
->invlpg
= ept_invlpg
;
4421 context
->update_pte
= ept_update_pte
;
4422 context
->root_level
= context
->shadow_root_level
;
4423 context
->root_hpa
= INVALID_PAGE
;
4424 context
->direct_map
= false;
4425 context
->base_role
.ad_disabled
= !accessed_dirty
;
4427 update_permission_bitmask(vcpu
, context
, true);
4428 update_pkru_bitmask(vcpu
, context
, true);
4429 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4430 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4432 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4434 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4436 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4438 kvm_init_shadow_mmu(vcpu
);
4439 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4440 context
->get_cr3
= get_cr3
;
4441 context
->get_pdptr
= kvm_pdptr_read
;
4442 context
->inject_page_fault
= kvm_inject_page_fault
;
4445 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4447 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4449 g_context
->get_cr3
= get_cr3
;
4450 g_context
->get_pdptr
= kvm_pdptr_read
;
4451 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4454 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4455 * L1's nested page tables (e.g. EPT12). The nested translation
4456 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4457 * L2's page tables as the first level of translation and L1's
4458 * nested page tables as the second level of translation. Basically
4459 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4461 if (!is_paging(vcpu
)) {
4462 g_context
->nx
= false;
4463 g_context
->root_level
= 0;
4464 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4465 } else if (is_long_mode(vcpu
)) {
4466 g_context
->nx
= is_nx(vcpu
);
4467 g_context
->root_level
= PT64_ROOT_LEVEL
;
4468 reset_rsvds_bits_mask(vcpu
, g_context
);
4469 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4470 } else if (is_pae(vcpu
)) {
4471 g_context
->nx
= is_nx(vcpu
);
4472 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4473 reset_rsvds_bits_mask(vcpu
, g_context
);
4474 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4476 g_context
->nx
= false;
4477 g_context
->root_level
= PT32_ROOT_LEVEL
;
4478 reset_rsvds_bits_mask(vcpu
, g_context
);
4479 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4482 update_permission_bitmask(vcpu
, g_context
, false);
4483 update_pkru_bitmask(vcpu
, g_context
, false);
4484 update_last_nonleaf_level(vcpu
, g_context
);
4487 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4489 if (mmu_is_nested(vcpu
))
4490 init_kvm_nested_mmu(vcpu
);
4491 else if (tdp_enabled
)
4492 init_kvm_tdp_mmu(vcpu
);
4494 init_kvm_softmmu(vcpu
);
4497 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4499 kvm_mmu_unload(vcpu
);
4502 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4504 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4508 r
= mmu_topup_memory_caches(vcpu
);
4511 r
= mmu_alloc_roots(vcpu
);
4512 kvm_mmu_sync_roots(vcpu
);
4515 /* set_cr3() should ensure TLB has been flushed */
4516 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4520 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4522 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4524 mmu_free_roots(vcpu
);
4525 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4527 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4529 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4530 struct kvm_mmu_page
*sp
, u64
*spte
,
4533 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4534 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4538 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4539 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4542 static bool need_remote_flush(u64 old
, u64
new)
4544 if (!is_shadow_present_pte(old
))
4546 if (!is_shadow_present_pte(new))
4548 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4550 old
^= shadow_nx_mask
;
4551 new ^= shadow_nx_mask
;
4552 return (old
& ~new & PT64_PERM_MASK
) != 0;
4555 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4556 const u8
*new, int *bytes
)
4562 * Assume that the pte write on a page table of the same type
4563 * as the current vcpu paging mode since we update the sptes only
4564 * when they have the same mode.
4566 if (is_pae(vcpu
) && *bytes
== 4) {
4567 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4570 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4573 new = (const u8
*)&gentry
;
4578 gentry
= *(const u32
*)new;
4581 gentry
= *(const u64
*)new;
4592 * If we're seeing too many writes to a page, it may no longer be a page table,
4593 * or we may be forking, in which case it is better to unmap the page.
4595 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4598 * Skip write-flooding detected for the sp whose level is 1, because
4599 * it can become unsync, then the guest page is not write-protected.
4601 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4604 atomic_inc(&sp
->write_flooding_count
);
4605 return atomic_read(&sp
->write_flooding_count
) >= 3;
4609 * Misaligned accesses are too much trouble to fix up; also, they usually
4610 * indicate a page is not used as a page table.
4612 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4615 unsigned offset
, pte_size
, misaligned
;
4617 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4618 gpa
, bytes
, sp
->role
.word
);
4620 offset
= offset_in_page(gpa
);
4621 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4624 * Sometimes, the OS only writes the last one bytes to update status
4625 * bits, for example, in linux, andb instruction is used in clear_bit().
4627 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4630 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4631 misaligned
|= bytes
< 4;
4636 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4638 unsigned page_offset
, quadrant
;
4642 page_offset
= offset_in_page(gpa
);
4643 level
= sp
->role
.level
;
4645 if (!sp
->role
.cr4_pae
) {
4646 page_offset
<<= 1; /* 32->64 */
4648 * A 32-bit pde maps 4MB while the shadow pdes map
4649 * only 2MB. So we need to double the offset again
4650 * and zap two pdes instead of one.
4652 if (level
== PT32_ROOT_LEVEL
) {
4653 page_offset
&= ~7; /* kill rounding error */
4657 quadrant
= page_offset
>> PAGE_SHIFT
;
4658 page_offset
&= ~PAGE_MASK
;
4659 if (quadrant
!= sp
->role
.quadrant
)
4663 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4667 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4668 const u8
*new, int bytes
,
4669 struct kvm_page_track_notifier_node
*node
)
4671 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4672 struct kvm_mmu_page
*sp
;
4673 LIST_HEAD(invalid_list
);
4674 u64 entry
, gentry
, *spte
;
4676 bool remote_flush
, local_flush
;
4677 union kvm_mmu_page_role mask
= { };
4682 mask
.smep_andnot_wp
= 1;
4683 mask
.smap_andnot_wp
= 1;
4685 mask
.ad_disabled
= 1;
4688 * If we don't have indirect shadow pages, it means no page is
4689 * write-protected, so we can exit simply.
4691 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4694 remote_flush
= local_flush
= false;
4696 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4698 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4701 * No need to care whether allocation memory is successful
4702 * or not since pte prefetch is skiped if it does not have
4703 * enough objects in the cache.
4705 mmu_topup_memory_caches(vcpu
);
4707 spin_lock(&vcpu
->kvm
->mmu_lock
);
4708 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4709 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4711 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4712 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4713 detect_write_flooding(sp
)) {
4714 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4715 ++vcpu
->kvm
->stat
.mmu_flooded
;
4719 spte
= get_written_sptes(sp
, gpa
, &npte
);
4726 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4728 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4729 & mask
.word
) && rmap_can_add(vcpu
))
4730 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4731 if (need_remote_flush(entry
, *spte
))
4732 remote_flush
= true;
4736 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4737 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4738 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4741 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4746 if (vcpu
->arch
.mmu
.direct_map
)
4749 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4751 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4755 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4757 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4759 LIST_HEAD(invalid_list
);
4761 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4764 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4765 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4768 ++vcpu
->kvm
->stat
.mmu_recycled
;
4770 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4773 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u64 error_code
,
4774 void *insn
, int insn_len
)
4776 int r
, emulation_type
= EMULTYPE_RETRY
;
4777 enum emulation_result er
;
4778 bool direct
= vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
);
4780 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4781 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4782 if (r
== RET_MMIO_PF_EMULATE
) {
4786 if (r
== RET_MMIO_PF_RETRY
)
4792 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, lower_32_bits(error_code
),
4800 * Before emulating the instruction, check if the error code
4801 * was due to a RO violation while translating the guest page.
4802 * This can occur when using nested virtualization with nested
4803 * paging in both guests. If true, we simply unprotect the page
4804 * and resume the guest.
4806 * Note: AMD only (since it supports the PFERR_GUEST_PAGE_MASK used
4807 * in PFERR_NEXT_GUEST_PAGE)
4809 if (error_code
== PFERR_NESTED_GUEST_PAGE
) {
4810 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2
));
4814 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4817 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4822 case EMULATE_USER_EXIT
:
4823 ++vcpu
->stat
.mmio_exits
;
4831 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4833 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4835 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4836 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4837 ++vcpu
->stat
.invlpg
;
4839 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4841 void kvm_enable_tdp(void)
4845 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4847 void kvm_disable_tdp(void)
4849 tdp_enabled
= false;
4851 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4853 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4855 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4856 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4857 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4860 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4866 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4867 * Therefore we need to allocate shadow page tables in the first
4868 * 4GB of memory, which happens to fit the DMA32 zone.
4870 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4874 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4875 for (i
= 0; i
< 4; ++i
)
4876 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4881 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4883 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4884 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4885 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4886 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4888 return alloc_mmu_pages(vcpu
);
4891 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4893 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4898 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
4899 struct kvm_memory_slot
*slot
,
4900 struct kvm_page_track_notifier_node
*node
)
4902 kvm_mmu_invalidate_zap_all_pages(kvm
);
4905 void kvm_mmu_init_vm(struct kvm
*kvm
)
4907 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4909 node
->track_write
= kvm_mmu_pte_write
;
4910 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
4911 kvm_page_track_register_notifier(kvm
, node
);
4914 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
4916 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4918 kvm_page_track_unregister_notifier(kvm
, node
);
4921 /* The return value indicates if tlb flush on all vcpus is needed. */
4922 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
4924 /* The caller should hold mmu-lock before calling this function. */
4926 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4927 slot_level_handler fn
, int start_level
, int end_level
,
4928 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
4930 struct slot_rmap_walk_iterator iterator
;
4933 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
4934 end_gfn
, &iterator
) {
4936 flush
|= fn(kvm
, iterator
.rmap
);
4938 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
4939 if (flush
&& lock_flush_tlb
) {
4940 kvm_flush_remote_tlbs(kvm
);
4943 cond_resched_lock(&kvm
->mmu_lock
);
4947 if (flush
&& lock_flush_tlb
) {
4948 kvm_flush_remote_tlbs(kvm
);
4956 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4957 slot_level_handler fn
, int start_level
, int end_level
,
4958 bool lock_flush_tlb
)
4960 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
4961 end_level
, memslot
->base_gfn
,
4962 memslot
->base_gfn
+ memslot
->npages
- 1,
4967 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4968 slot_level_handler fn
, bool lock_flush_tlb
)
4970 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4971 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4975 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4976 slot_level_handler fn
, bool lock_flush_tlb
)
4978 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
4979 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4983 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4984 slot_level_handler fn
, bool lock_flush_tlb
)
4986 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4987 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
4990 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
4992 struct kvm_memslots
*slots
;
4993 struct kvm_memory_slot
*memslot
;
4996 spin_lock(&kvm
->mmu_lock
);
4997 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
4998 slots
= __kvm_memslots(kvm
, i
);
4999 kvm_for_each_memslot(memslot
, slots
) {
5002 start
= max(gfn_start
, memslot
->base_gfn
);
5003 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5007 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5008 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
5009 start
, end
- 1, true);
5013 spin_unlock(&kvm
->mmu_lock
);
5016 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5017 struct kvm_rmap_head
*rmap_head
)
5019 return __rmap_write_protect(kvm
, rmap_head
, false);
5022 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5023 struct kvm_memory_slot
*memslot
)
5027 spin_lock(&kvm
->mmu_lock
);
5028 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
5030 spin_unlock(&kvm
->mmu_lock
);
5033 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5034 * which do tlb flush out of mmu-lock should be serialized by
5035 * kvm->slots_lock otherwise tlb flush would be missed.
5037 lockdep_assert_held(&kvm
->slots_lock
);
5040 * We can flush all the TLBs out of the mmu lock without TLB
5041 * corruption since we just change the spte from writable to
5042 * readonly so that we only need to care the case of changing
5043 * spte from present to present (changing the spte from present
5044 * to nonpresent will flush all the TLBs immediately), in other
5045 * words, the only case we care is mmu_spte_update() where we
5046 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5047 * instead of PT_WRITABLE_MASK, that means it does not depend
5048 * on PT_WRITABLE_MASK anymore.
5051 kvm_flush_remote_tlbs(kvm
);
5054 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5055 struct kvm_rmap_head
*rmap_head
)
5058 struct rmap_iterator iter
;
5059 int need_tlb_flush
= 0;
5061 struct kvm_mmu_page
*sp
;
5064 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5065 sp
= page_header(__pa(sptep
));
5066 pfn
= spte_to_pfn(*sptep
);
5069 * We cannot do huge page mapping for indirect shadow pages,
5070 * which are found on the last rmap (level = 1) when not using
5071 * tdp; such shadow pages are synced with the page table in
5072 * the guest, and the guest page table is using 4K page size
5073 * mapping if the indirect sp has level = 1.
5075 if (sp
->role
.direct
&&
5076 !kvm_is_reserved_pfn(pfn
) &&
5077 PageTransCompoundMap(pfn_to_page(pfn
))) {
5078 drop_spte(kvm
, sptep
);
5084 return need_tlb_flush
;
5087 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5088 const struct kvm_memory_slot
*memslot
)
5090 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5091 spin_lock(&kvm
->mmu_lock
);
5092 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5093 kvm_mmu_zap_collapsible_spte
, true);
5094 spin_unlock(&kvm
->mmu_lock
);
5097 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5098 struct kvm_memory_slot
*memslot
)
5102 spin_lock(&kvm
->mmu_lock
);
5103 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5104 spin_unlock(&kvm
->mmu_lock
);
5106 lockdep_assert_held(&kvm
->slots_lock
);
5109 * It's also safe to flush TLBs out of mmu lock here as currently this
5110 * function is only used for dirty logging, in which case flushing TLB
5111 * out of mmu lock also guarantees no dirty pages will be lost in
5115 kvm_flush_remote_tlbs(kvm
);
5117 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5119 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5120 struct kvm_memory_slot
*memslot
)
5124 spin_lock(&kvm
->mmu_lock
);
5125 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5127 spin_unlock(&kvm
->mmu_lock
);
5129 /* see kvm_mmu_slot_remove_write_access */
5130 lockdep_assert_held(&kvm
->slots_lock
);
5133 kvm_flush_remote_tlbs(kvm
);
5135 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5137 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5138 struct kvm_memory_slot
*memslot
)
5142 spin_lock(&kvm
->mmu_lock
);
5143 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5144 spin_unlock(&kvm
->mmu_lock
);
5146 lockdep_assert_held(&kvm
->slots_lock
);
5148 /* see kvm_mmu_slot_leaf_clear_dirty */
5150 kvm_flush_remote_tlbs(kvm
);
5152 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5154 #define BATCH_ZAP_PAGES 10
5155 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5157 struct kvm_mmu_page
*sp
, *node
;
5161 list_for_each_entry_safe_reverse(sp
, node
,
5162 &kvm
->arch
.active_mmu_pages
, link
) {
5166 * No obsolete page exists before new created page since
5167 * active_mmu_pages is the FIFO list.
5169 if (!is_obsolete_sp(kvm
, sp
))
5173 * Since we are reversely walking the list and the invalid
5174 * list will be moved to the head, skip the invalid page
5175 * can help us to avoid the infinity list walking.
5177 if (sp
->role
.invalid
)
5181 * Need not flush tlb since we only zap the sp with invalid
5182 * generation number.
5184 if (batch
>= BATCH_ZAP_PAGES
&&
5185 cond_resched_lock(&kvm
->mmu_lock
)) {
5190 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
5191 &kvm
->arch
.zapped_obsolete_pages
);
5199 * Should flush tlb before free page tables since lockless-walking
5200 * may use the pages.
5202 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5206 * Fast invalidate all shadow pages and use lock-break technique
5207 * to zap obsolete pages.
5209 * It's required when memslot is being deleted or VM is being
5210 * destroyed, in these cases, we should ensure that KVM MMU does
5211 * not use any resource of the being-deleted slot or all slots
5212 * after calling the function.
5214 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
5216 spin_lock(&kvm
->mmu_lock
);
5217 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
5218 kvm
->arch
.mmu_valid_gen
++;
5221 * Notify all vcpus to reload its shadow page table
5222 * and flush TLB. Then all vcpus will switch to new
5223 * shadow page table with the new mmu_valid_gen.
5225 * Note: we should do this under the protection of
5226 * mmu-lock, otherwise, vcpu would purge shadow page
5227 * but miss tlb flush.
5229 kvm_reload_remote_mmus(kvm
);
5231 kvm_zap_obsolete_pages(kvm
);
5232 spin_unlock(&kvm
->mmu_lock
);
5235 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5237 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5240 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
5243 * The very rare case: if the generation-number is round,
5244 * zap all shadow pages.
5246 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
5247 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5248 kvm_mmu_invalidate_zap_all_pages(kvm
);
5252 static unsigned long
5253 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5256 int nr_to_scan
= sc
->nr_to_scan
;
5257 unsigned long freed
= 0;
5259 spin_lock(&kvm_lock
);
5261 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5263 LIST_HEAD(invalid_list
);
5266 * Never scan more than sc->nr_to_scan VM instances.
5267 * Will not hit this condition practically since we do not try
5268 * to shrink more than one VM and it is very unlikely to see
5269 * !n_used_mmu_pages so many times.
5274 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5275 * here. We may skip a VM instance errorneosly, but we do not
5276 * want to shrink a VM that only started to populate its MMU
5279 if (!kvm
->arch
.n_used_mmu_pages
&&
5280 !kvm_has_zapped_obsolete_pages(kvm
))
5283 idx
= srcu_read_lock(&kvm
->srcu
);
5284 spin_lock(&kvm
->mmu_lock
);
5286 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5287 kvm_mmu_commit_zap_page(kvm
,
5288 &kvm
->arch
.zapped_obsolete_pages
);
5292 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5294 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5297 spin_unlock(&kvm
->mmu_lock
);
5298 srcu_read_unlock(&kvm
->srcu
, idx
);
5301 * unfair on small ones
5302 * per-vm shrinkers cry out
5303 * sadness comes quickly
5305 list_move_tail(&kvm
->vm_list
, &vm_list
);
5309 spin_unlock(&kvm_lock
);
5313 static unsigned long
5314 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5316 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5319 static struct shrinker mmu_shrinker
= {
5320 .count_objects
= mmu_shrink_count
,
5321 .scan_objects
= mmu_shrink_scan
,
5322 .seeks
= DEFAULT_SEEKS
* 10,
5325 static void mmu_destroy_caches(void)
5327 if (pte_list_desc_cache
)
5328 kmem_cache_destroy(pte_list_desc_cache
);
5329 if (mmu_page_header_cache
)
5330 kmem_cache_destroy(mmu_page_header_cache
);
5333 int kvm_mmu_module_init(void)
5335 kvm_mmu_clear_all_pte_masks();
5337 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5338 sizeof(struct pte_list_desc
),
5340 if (!pte_list_desc_cache
)
5343 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5344 sizeof(struct kvm_mmu_page
),
5346 if (!mmu_page_header_cache
)
5349 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5352 register_shrinker(&mmu_shrinker
);
5357 mmu_destroy_caches();
5362 * Caculate mmu pages needed for kvm.
5364 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5366 unsigned int nr_mmu_pages
;
5367 unsigned int nr_pages
= 0;
5368 struct kvm_memslots
*slots
;
5369 struct kvm_memory_slot
*memslot
;
5372 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5373 slots
= __kvm_memslots(kvm
, i
);
5375 kvm_for_each_memslot(memslot
, slots
)
5376 nr_pages
+= memslot
->npages
;
5379 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5380 nr_mmu_pages
= max(nr_mmu_pages
,
5381 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5383 return nr_mmu_pages
;
5386 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5388 kvm_mmu_unload(vcpu
);
5389 free_mmu_pages(vcpu
);
5390 mmu_free_memory_caches(vcpu
);
5393 void kvm_mmu_module_exit(void)
5395 mmu_destroy_caches();
5396 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5397 unregister_shrinker(&mmu_shrinker
);
5398 mmu_audit_disable();