2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
45 #include <asm/cmpxchg.h>
48 #include <asm/kvm_page_track.h>
52 * When setting this variable to true it enables Two-Dimensional-Paging
53 * where the hardware walks 2 page tables:
54 * 1. the guest-virtual to guest-physical
55 * 2. while doing 1. it walks guest-physical to host-physical
56 * If the hardware supports that we don't need to do shadow paging.
58 bool tdp_enabled
= false;
62 AUDIT_POST_PAGE_FAULT
,
73 module_param(dbg
, bool, 0644);
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
77 #define MMU_WARN_ON(x) WARN_ON(x)
79 #define pgprintk(x...) do { } while (0)
80 #define rmap_printk(x...) do { } while (0)
81 #define MMU_WARN_ON(x) do { } while (0)
84 #define PTE_PREFETCH_NUM 8
86 #define PT_FIRST_AVAIL_BITS_SHIFT 10
87 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
89 #define PT64_LEVEL_BITS 9
91 #define PT64_LEVEL_SHIFT(level) \
92 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
94 #define PT64_INDEX(address, level)\
95 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
98 #define PT32_LEVEL_BITS 10
100 #define PT32_LEVEL_SHIFT(level) \
101 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
103 #define PT32_LVL_OFFSET_MASK(level) \
104 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
105 * PT32_LEVEL_BITS))) - 1))
107 #define PT32_INDEX(address, level)\
108 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
111 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
112 #define PT64_DIR_BASE_ADDR_MASK \
113 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
114 #define PT64_LVL_ADDR_MASK(level) \
115 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT64_LEVEL_BITS))) - 1))
117 #define PT64_LVL_OFFSET_MASK(level) \
118 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
119 * PT64_LEVEL_BITS))) - 1))
121 #define PT32_BASE_ADDR_MASK PAGE_MASK
122 #define PT32_DIR_BASE_ADDR_MASK \
123 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
124 #define PT32_LVL_ADDR_MASK(level) \
125 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT32_LEVEL_BITS))) - 1))
128 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
129 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
131 #define ACC_EXEC_MASK 1
132 #define ACC_WRITE_MASK PT_WRITABLE_MASK
133 #define ACC_USER_MASK PT_USER_MASK
134 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
136 /* The mask for the R/X bits in EPT PTEs */
137 #define PT64_EPT_READABLE_MASK 0x1ull
138 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
140 #include <trace/events/kvm.h>
142 #define CREATE_TRACE_POINTS
143 #include "mmutrace.h"
145 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
146 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
148 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
150 /* make pte_list_desc fit well in cache line */
151 #define PTE_LIST_EXT 3
154 * Return values of handle_mmio_page_fault and mmu.page_fault:
155 * RET_PF_RETRY: let CPU fault again on the address.
156 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
158 * For handle_mmio_page_fault only:
159 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
167 struct pte_list_desc
{
168 u64
*sptes
[PTE_LIST_EXT
];
169 struct pte_list_desc
*more
;
172 struct kvm_shadow_walk_iterator
{
180 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
181 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
182 shadow_walk_okay(&(_walker)); \
183 shadow_walk_next(&(_walker)))
185 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
186 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
187 shadow_walk_okay(&(_walker)) && \
188 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
189 __shadow_walk_next(&(_walker), spte))
191 static struct kmem_cache
*pte_list_desc_cache
;
192 static struct kmem_cache
*mmu_page_header_cache
;
193 static struct percpu_counter kvm_total_used_mmu_pages
;
195 static u64 __read_mostly shadow_nx_mask
;
196 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
197 static u64 __read_mostly shadow_user_mask
;
198 static u64 __read_mostly shadow_accessed_mask
;
199 static u64 __read_mostly shadow_dirty_mask
;
200 static u64 __read_mostly shadow_mmio_mask
;
201 static u64 __read_mostly shadow_mmio_value
;
202 static u64 __read_mostly shadow_present_mask
;
203 static u64 __read_mostly shadow_me_mask
;
206 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
207 * Non-present SPTEs with shadow_acc_track_value set are in place for access
210 static u64 __read_mostly shadow_acc_track_mask
;
211 static const u64 shadow_acc_track_value
= SPTE_SPECIAL_MASK
;
214 * The mask/shift to use for saving the original R/X bits when marking the PTE
215 * as not-present for access tracking purposes. We do not save the W bit as the
216 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
217 * restored only when a write is attempted to the page.
219 static const u64 shadow_acc_track_saved_bits_mask
= PT64_EPT_READABLE_MASK
|
220 PT64_EPT_EXECUTABLE_MASK
;
221 static const u64 shadow_acc_track_saved_bits_shift
= PT64_SECOND_AVAIL_BITS_SHIFT
;
223 static void mmu_spte_set(u64
*sptep
, u64 spte
);
224 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
226 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
, u64 mmio_value
)
228 BUG_ON((mmio_mask
& mmio_value
) != mmio_value
);
229 shadow_mmio_value
= mmio_value
| SPTE_SPECIAL_MASK
;
230 shadow_mmio_mask
= mmio_mask
| SPTE_SPECIAL_MASK
;
232 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
234 static inline bool sp_ad_disabled(struct kvm_mmu_page
*sp
)
236 return sp
->role
.ad_disabled
;
239 static inline bool spte_ad_enabled(u64 spte
)
241 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
242 return !(spte
& shadow_acc_track_value
);
245 static inline u64
spte_shadow_accessed_mask(u64 spte
)
247 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
248 return spte_ad_enabled(spte
) ? shadow_accessed_mask
: 0;
251 static inline u64
spte_shadow_dirty_mask(u64 spte
)
253 MMU_WARN_ON((spte
& shadow_mmio_mask
) == shadow_mmio_value
);
254 return spte_ad_enabled(spte
) ? shadow_dirty_mask
: 0;
257 static inline bool is_access_track_spte(u64 spte
)
259 return !spte_ad_enabled(spte
) && (spte
& shadow_acc_track_mask
) == 0;
263 * the low bit of the generation number is always presumed to be zero.
264 * This disables mmio caching during memslot updates. The concept is
265 * similar to a seqcount but instead of retrying the access we just punt
266 * and ignore the cache.
268 * spte bits 3-11 are used as bits 1-9 of the generation number,
269 * the bits 52-61 are used as bits 10-19 of the generation number.
271 #define MMIO_SPTE_GEN_LOW_SHIFT 2
272 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
274 #define MMIO_GEN_SHIFT 20
275 #define MMIO_GEN_LOW_SHIFT 10
276 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
277 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
279 static u64
generation_mmio_spte_mask(unsigned int gen
)
283 WARN_ON(gen
& ~MMIO_GEN_MASK
);
285 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
286 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
290 static unsigned int get_mmio_spte_generation(u64 spte
)
294 spte
&= ~shadow_mmio_mask
;
296 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
297 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
301 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
303 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
306 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
309 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
310 u64 mask
= generation_mmio_spte_mask(gen
);
312 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
313 mask
|= shadow_mmio_value
| access
| gfn
<< PAGE_SHIFT
;
315 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
316 mmu_spte_set(sptep
, mask
);
319 static bool is_mmio_spte(u64 spte
)
321 return (spte
& shadow_mmio_mask
) == shadow_mmio_value
;
324 static gfn_t
get_mmio_spte_gfn(u64 spte
)
326 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
327 return (spte
& ~mask
) >> PAGE_SHIFT
;
330 static unsigned get_mmio_spte_access(u64 spte
)
332 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
333 return (spte
& ~mask
) & ~PAGE_MASK
;
336 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
337 kvm_pfn_t pfn
, unsigned access
)
339 if (unlikely(is_noslot_pfn(pfn
))) {
340 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
347 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
349 unsigned int kvm_gen
, spte_gen
;
351 kvm_gen
= kvm_current_mmio_generation(vcpu
);
352 spte_gen
= get_mmio_spte_generation(spte
);
354 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
355 return likely(kvm_gen
== spte_gen
);
359 * Sets the shadow PTE masks used by the MMU.
362 * - Setting either @accessed_mask or @dirty_mask requires setting both
363 * - At least one of @accessed_mask or @acc_track_mask must be set
365 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
366 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
, u64 p_mask
,
367 u64 acc_track_mask
, u64 me_mask
)
369 BUG_ON(!dirty_mask
!= !accessed_mask
);
370 BUG_ON(!accessed_mask
&& !acc_track_mask
);
371 BUG_ON(acc_track_mask
& shadow_acc_track_value
);
373 shadow_user_mask
= user_mask
;
374 shadow_accessed_mask
= accessed_mask
;
375 shadow_dirty_mask
= dirty_mask
;
376 shadow_nx_mask
= nx_mask
;
377 shadow_x_mask
= x_mask
;
378 shadow_present_mask
= p_mask
;
379 shadow_acc_track_mask
= acc_track_mask
;
380 shadow_me_mask
= me_mask
;
382 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
384 void kvm_mmu_clear_all_pte_masks(void)
386 shadow_user_mask
= 0;
387 shadow_accessed_mask
= 0;
388 shadow_dirty_mask
= 0;
391 shadow_mmio_mask
= 0;
392 shadow_present_mask
= 0;
393 shadow_acc_track_mask
= 0;
396 static int is_cpuid_PSE36(void)
401 static int is_nx(struct kvm_vcpu
*vcpu
)
403 return vcpu
->arch
.efer
& EFER_NX
;
406 static int is_shadow_present_pte(u64 pte
)
408 return (pte
!= 0) && !is_mmio_spte(pte
);
411 static int is_large_pte(u64 pte
)
413 return pte
& PT_PAGE_SIZE_MASK
;
416 static int is_last_spte(u64 pte
, int level
)
418 if (level
== PT_PAGE_TABLE_LEVEL
)
420 if (is_large_pte(pte
))
425 static bool is_executable_pte(u64 spte
)
427 return (spte
& (shadow_x_mask
| shadow_nx_mask
)) == shadow_x_mask
;
430 static kvm_pfn_t
spte_to_pfn(u64 pte
)
432 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
435 static gfn_t
pse36_gfn_delta(u32 gpte
)
437 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
439 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
443 static void __set_spte(u64
*sptep
, u64 spte
)
445 WRITE_ONCE(*sptep
, spte
);
448 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
450 WRITE_ONCE(*sptep
, spte
);
453 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
455 return xchg(sptep
, spte
);
458 static u64
__get_spte_lockless(u64
*sptep
)
460 return READ_ONCE(*sptep
);
471 static void count_spte_clear(u64
*sptep
, u64 spte
)
473 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
475 if (is_shadow_present_pte(spte
))
478 /* Ensure the spte is completely set before we increase the count */
480 sp
->clear_spte_count
++;
483 static void __set_spte(u64
*sptep
, u64 spte
)
485 union split_spte
*ssptep
, sspte
;
487 ssptep
= (union split_spte
*)sptep
;
488 sspte
= (union split_spte
)spte
;
490 ssptep
->spte_high
= sspte
.spte_high
;
493 * If we map the spte from nonpresent to present, We should store
494 * the high bits firstly, then set present bit, so cpu can not
495 * fetch this spte while we are setting the spte.
499 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
502 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
504 union split_spte
*ssptep
, sspte
;
506 ssptep
= (union split_spte
*)sptep
;
507 sspte
= (union split_spte
)spte
;
509 WRITE_ONCE(ssptep
->spte_low
, sspte
.spte_low
);
512 * If we map the spte from present to nonpresent, we should clear
513 * present bit firstly to avoid vcpu fetch the old high bits.
517 ssptep
->spte_high
= sspte
.spte_high
;
518 count_spte_clear(sptep
, spte
);
521 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
523 union split_spte
*ssptep
, sspte
, orig
;
525 ssptep
= (union split_spte
*)sptep
;
526 sspte
= (union split_spte
)spte
;
528 /* xchg acts as a barrier before the setting of the high bits */
529 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
530 orig
.spte_high
= ssptep
->spte_high
;
531 ssptep
->spte_high
= sspte
.spte_high
;
532 count_spte_clear(sptep
, spte
);
538 * The idea using the light way get the spte on x86_32 guest is from
539 * gup_get_pte(arch/x86/mm/gup.c).
541 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
542 * coalesces them and we are running out of the MMU lock. Therefore
543 * we need to protect against in-progress updates of the spte.
545 * Reading the spte while an update is in progress may get the old value
546 * for the high part of the spte. The race is fine for a present->non-present
547 * change (because the high part of the spte is ignored for non-present spte),
548 * but for a present->present change we must reread the spte.
550 * All such changes are done in two steps (present->non-present and
551 * non-present->present), hence it is enough to count the number of
552 * present->non-present updates: if it changed while reading the spte,
553 * we might have hit the race. This is done using clear_spte_count.
555 static u64
__get_spte_lockless(u64
*sptep
)
557 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
558 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
562 count
= sp
->clear_spte_count
;
565 spte
.spte_low
= orig
->spte_low
;
568 spte
.spte_high
= orig
->spte_high
;
571 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
572 count
!= sp
->clear_spte_count
))
579 static bool spte_can_locklessly_be_made_writable(u64 spte
)
581 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
582 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
585 static bool spte_has_volatile_bits(u64 spte
)
587 if (!is_shadow_present_pte(spte
))
591 * Always atomically update spte if it can be updated
592 * out of mmu-lock, it can ensure dirty bit is not lost,
593 * also, it can help us to get a stable is_writable_pte()
594 * to ensure tlb flush is not missed.
596 if (spte_can_locklessly_be_made_writable(spte
) ||
597 is_access_track_spte(spte
))
600 if (spte_ad_enabled(spte
)) {
601 if ((spte
& shadow_accessed_mask
) == 0 ||
602 (is_writable_pte(spte
) && (spte
& shadow_dirty_mask
) == 0))
609 static bool is_accessed_spte(u64 spte
)
611 u64 accessed_mask
= spte_shadow_accessed_mask(spte
);
613 return accessed_mask
? spte
& accessed_mask
614 : !is_access_track_spte(spte
);
617 static bool is_dirty_spte(u64 spte
)
619 u64 dirty_mask
= spte_shadow_dirty_mask(spte
);
621 return dirty_mask
? spte
& dirty_mask
: spte
& PT_WRITABLE_MASK
;
624 /* Rules for using mmu_spte_set:
625 * Set the sptep from nonpresent to present.
626 * Note: the sptep being assigned *must* be either not present
627 * or in a state where the hardware will not attempt to update
630 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
632 WARN_ON(is_shadow_present_pte(*sptep
));
633 __set_spte(sptep
, new_spte
);
637 * Update the SPTE (excluding the PFN), but do not track changes in its
638 * accessed/dirty status.
640 static u64
mmu_spte_update_no_track(u64
*sptep
, u64 new_spte
)
642 u64 old_spte
= *sptep
;
644 WARN_ON(!is_shadow_present_pte(new_spte
));
646 if (!is_shadow_present_pte(old_spte
)) {
647 mmu_spte_set(sptep
, new_spte
);
651 if (!spte_has_volatile_bits(old_spte
))
652 __update_clear_spte_fast(sptep
, new_spte
);
654 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
656 WARN_ON(spte_to_pfn(old_spte
) != spte_to_pfn(new_spte
));
661 /* Rules for using mmu_spte_update:
662 * Update the state bits, it means the mapped pfn is not changed.
664 * Whenever we overwrite a writable spte with a read-only one we
665 * should flush remote TLBs. Otherwise rmap_write_protect
666 * will find a read-only spte, even though the writable spte
667 * might be cached on a CPU's TLB, the return value indicates this
670 * Returns true if the TLB needs to be flushed
672 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
675 u64 old_spte
= mmu_spte_update_no_track(sptep
, new_spte
);
677 if (!is_shadow_present_pte(old_spte
))
681 * For the spte updated out of mmu-lock is safe, since
682 * we always atomically update it, see the comments in
683 * spte_has_volatile_bits().
685 if (spte_can_locklessly_be_made_writable(old_spte
) &&
686 !is_writable_pte(new_spte
))
690 * Flush TLB when accessed/dirty states are changed in the page tables,
691 * to guarantee consistency between TLB and page tables.
694 if (is_accessed_spte(old_spte
) && !is_accessed_spte(new_spte
)) {
696 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
699 if (is_dirty_spte(old_spte
) && !is_dirty_spte(new_spte
)) {
701 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
708 * Rules for using mmu_spte_clear_track_bits:
709 * It sets the sptep from present to nonpresent, and track the
710 * state bits, it is used to clear the last level sptep.
711 * Returns non-zero if the PTE was previously valid.
713 static int mmu_spte_clear_track_bits(u64
*sptep
)
716 u64 old_spte
= *sptep
;
718 if (!spte_has_volatile_bits(old_spte
))
719 __update_clear_spte_fast(sptep
, 0ull);
721 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
723 if (!is_shadow_present_pte(old_spte
))
726 pfn
= spte_to_pfn(old_spte
);
729 * KVM does not hold the refcount of the page used by
730 * kvm mmu, before reclaiming the page, we should
731 * unmap it from mmu first.
733 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
735 if (is_accessed_spte(old_spte
))
736 kvm_set_pfn_accessed(pfn
);
738 if (is_dirty_spte(old_spte
))
739 kvm_set_pfn_dirty(pfn
);
745 * Rules for using mmu_spte_clear_no_track:
746 * Directly clear spte without caring the state bits of sptep,
747 * it is used to set the upper level spte.
749 static void mmu_spte_clear_no_track(u64
*sptep
)
751 __update_clear_spte_fast(sptep
, 0ull);
754 static u64
mmu_spte_get_lockless(u64
*sptep
)
756 return __get_spte_lockless(sptep
);
759 static u64
mark_spte_for_access_track(u64 spte
)
761 if (spte_ad_enabled(spte
))
762 return spte
& ~shadow_accessed_mask
;
764 if (is_access_track_spte(spte
))
768 * Making an Access Tracking PTE will result in removal of write access
769 * from the PTE. So, verify that we will be able to restore the write
770 * access in the fast page fault path later on.
772 WARN_ONCE((spte
& PT_WRITABLE_MASK
) &&
773 !spte_can_locklessly_be_made_writable(spte
),
774 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
776 WARN_ONCE(spte
& (shadow_acc_track_saved_bits_mask
<<
777 shadow_acc_track_saved_bits_shift
),
778 "kvm: Access Tracking saved bit locations are not zero\n");
780 spte
|= (spte
& shadow_acc_track_saved_bits_mask
) <<
781 shadow_acc_track_saved_bits_shift
;
782 spte
&= ~shadow_acc_track_mask
;
787 /* Restore an acc-track PTE back to a regular PTE */
788 static u64
restore_acc_track_spte(u64 spte
)
791 u64 saved_bits
= (spte
>> shadow_acc_track_saved_bits_shift
)
792 & shadow_acc_track_saved_bits_mask
;
794 WARN_ON_ONCE(spte_ad_enabled(spte
));
795 WARN_ON_ONCE(!is_access_track_spte(spte
));
797 new_spte
&= ~shadow_acc_track_mask
;
798 new_spte
&= ~(shadow_acc_track_saved_bits_mask
<<
799 shadow_acc_track_saved_bits_shift
);
800 new_spte
|= saved_bits
;
805 /* Returns the Accessed status of the PTE and resets it at the same time. */
806 static bool mmu_spte_age(u64
*sptep
)
808 u64 spte
= mmu_spte_get_lockless(sptep
);
810 if (!is_accessed_spte(spte
))
813 if (spte_ad_enabled(spte
)) {
814 clear_bit((ffs(shadow_accessed_mask
) - 1),
815 (unsigned long *)sptep
);
818 * Capture the dirty status of the page, so that it doesn't get
819 * lost when the SPTE is marked for access tracking.
821 if (is_writable_pte(spte
))
822 kvm_set_pfn_dirty(spte_to_pfn(spte
));
824 spte
= mark_spte_for_access_track(spte
);
825 mmu_spte_update_no_track(sptep
, spte
);
831 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
834 * Prevent page table teardown by making any free-er wait during
835 * kvm_flush_remote_tlbs() IPI to all active vcpus.
840 * Make sure a following spte read is not reordered ahead of the write
843 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
846 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
849 * Make sure the write to vcpu->mode is not reordered in front of
850 * reads to sptes. If it does, kvm_commit_zap_page() can see us
851 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
853 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
857 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
858 struct kmem_cache
*base_cache
, int min
)
862 if (cache
->nobjs
>= min
)
864 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
865 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
868 cache
->objects
[cache
->nobjs
++] = obj
;
873 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
878 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
879 struct kmem_cache
*cache
)
882 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
885 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
890 if (cache
->nobjs
>= min
)
892 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
893 page
= (void *)__get_free_page(GFP_KERNEL
);
896 cache
->objects
[cache
->nobjs
++] = page
;
901 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
904 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
907 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
911 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
912 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
915 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
918 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
919 mmu_page_header_cache
, 4);
924 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
926 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
927 pte_list_desc_cache
);
928 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
929 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
930 mmu_page_header_cache
);
933 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
938 p
= mc
->objects
[--mc
->nobjs
];
942 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
944 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
947 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
949 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
952 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
954 if (!sp
->role
.direct
)
955 return sp
->gfns
[index
];
957 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
960 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
963 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
965 sp
->gfns
[index
] = gfn
;
969 * Return the pointer to the large page information for a given gfn,
970 * handling slots that are not large page aligned.
972 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
973 struct kvm_memory_slot
*slot
,
978 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
979 return &slot
->arch
.lpage_info
[level
- 2][idx
];
982 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
983 gfn_t gfn
, int count
)
985 struct kvm_lpage_info
*linfo
;
988 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
989 linfo
= lpage_info_slot(gfn
, slot
, i
);
990 linfo
->disallow_lpage
+= count
;
991 WARN_ON(linfo
->disallow_lpage
< 0);
995 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
997 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
1000 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
1002 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
1005 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1007 struct kvm_memslots
*slots
;
1008 struct kvm_memory_slot
*slot
;
1011 kvm
->arch
.indirect_shadow_pages
++;
1013 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1014 slot
= __gfn_to_memslot(slots
, gfn
);
1016 /* the non-leaf shadow pages are keeping readonly. */
1017 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1018 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
1019 KVM_PAGE_TRACK_WRITE
);
1021 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
1024 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1026 struct kvm_memslots
*slots
;
1027 struct kvm_memory_slot
*slot
;
1030 kvm
->arch
.indirect_shadow_pages
--;
1032 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1033 slot
= __gfn_to_memslot(slots
, gfn
);
1034 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
1035 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
1036 KVM_PAGE_TRACK_WRITE
);
1038 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
1041 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
1042 struct kvm_memory_slot
*slot
)
1044 struct kvm_lpage_info
*linfo
;
1047 linfo
= lpage_info_slot(gfn
, slot
, level
);
1048 return !!linfo
->disallow_lpage
;
1054 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1057 struct kvm_memory_slot
*slot
;
1059 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1060 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
1063 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
1065 unsigned long page_size
;
1068 page_size
= kvm_host_page_size(kvm
, gfn
);
1070 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1071 if (page_size
>= KVM_HPAGE_SIZE(i
))
1080 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
1083 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
1085 if (no_dirty_log
&& slot
->dirty_bitmap
)
1091 static struct kvm_memory_slot
*
1092 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1095 struct kvm_memory_slot
*slot
;
1097 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1098 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
1104 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
1105 bool *force_pt_level
)
1107 int host_level
, level
, max_level
;
1108 struct kvm_memory_slot
*slot
;
1110 if (unlikely(*force_pt_level
))
1111 return PT_PAGE_TABLE_LEVEL
;
1113 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
1114 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
1115 if (unlikely(*force_pt_level
))
1116 return PT_PAGE_TABLE_LEVEL
;
1118 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
1120 if (host_level
== PT_PAGE_TABLE_LEVEL
)
1123 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
1125 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
1126 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
1133 * About rmap_head encoding:
1135 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1136 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1137 * pte_list_desc containing more mappings.
1141 * Returns the number of pointers in the rmap chain, not counting the new one.
1143 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
1144 struct kvm_rmap_head
*rmap_head
)
1146 struct pte_list_desc
*desc
;
1149 if (!rmap_head
->val
) {
1150 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
1151 rmap_head
->val
= (unsigned long)spte
;
1152 } else if (!(rmap_head
->val
& 1)) {
1153 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
1154 desc
= mmu_alloc_pte_list_desc(vcpu
);
1155 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
1156 desc
->sptes
[1] = spte
;
1157 rmap_head
->val
= (unsigned long)desc
| 1;
1160 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
1161 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1162 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
1164 count
+= PTE_LIST_EXT
;
1166 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
1167 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
1170 for (i
= 0; desc
->sptes
[i
]; ++i
)
1172 desc
->sptes
[i
] = spte
;
1178 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
1179 struct pte_list_desc
*desc
, int i
,
1180 struct pte_list_desc
*prev_desc
)
1184 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
1186 desc
->sptes
[i
] = desc
->sptes
[j
];
1187 desc
->sptes
[j
] = NULL
;
1190 if (!prev_desc
&& !desc
->more
)
1191 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
1194 prev_desc
->more
= desc
->more
;
1196 rmap_head
->val
= (unsigned long)desc
->more
| 1;
1197 mmu_free_pte_list_desc(desc
);
1200 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
1202 struct pte_list_desc
*desc
;
1203 struct pte_list_desc
*prev_desc
;
1206 if (!rmap_head
->val
) {
1207 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1209 } else if (!(rmap_head
->val
& 1)) {
1210 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1211 if ((u64
*)rmap_head
->val
!= spte
) {
1212 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1217 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1218 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1221 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1222 if (desc
->sptes
[i
] == spte
) {
1223 pte_list_desc_remove_entry(rmap_head
,
1224 desc
, i
, prev_desc
);
1231 pr_err("pte_list_remove: %p many->many\n", spte
);
1236 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1237 struct kvm_memory_slot
*slot
)
1241 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1242 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1245 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1246 struct kvm_mmu_page
*sp
)
1248 struct kvm_memslots
*slots
;
1249 struct kvm_memory_slot
*slot
;
1251 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1252 slot
= __gfn_to_memslot(slots
, gfn
);
1253 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1256 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1258 struct kvm_mmu_memory_cache
*cache
;
1260 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1261 return mmu_memory_cache_free_objects(cache
);
1264 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1266 struct kvm_mmu_page
*sp
;
1267 struct kvm_rmap_head
*rmap_head
;
1269 sp
= page_header(__pa(spte
));
1270 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1271 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1272 return pte_list_add(vcpu
, spte
, rmap_head
);
1275 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1277 struct kvm_mmu_page
*sp
;
1279 struct kvm_rmap_head
*rmap_head
;
1281 sp
= page_header(__pa(spte
));
1282 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1283 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1284 pte_list_remove(spte
, rmap_head
);
1288 * Used by the following functions to iterate through the sptes linked by a
1289 * rmap. All fields are private and not assumed to be used outside.
1291 struct rmap_iterator
{
1292 /* private fields */
1293 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1294 int pos
; /* index of the sptep */
1298 * Iteration must be started by this function. This should also be used after
1299 * removing/dropping sptes from the rmap link because in such cases the
1300 * information in the itererator may not be valid.
1302 * Returns sptep if found, NULL otherwise.
1304 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1305 struct rmap_iterator
*iter
)
1309 if (!rmap_head
->val
)
1312 if (!(rmap_head
->val
& 1)) {
1314 sptep
= (u64
*)rmap_head
->val
;
1318 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1320 sptep
= iter
->desc
->sptes
[iter
->pos
];
1322 BUG_ON(!is_shadow_present_pte(*sptep
));
1327 * Must be used with a valid iterator: e.g. after rmap_get_first().
1329 * Returns sptep if found, NULL otherwise.
1331 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1336 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1338 sptep
= iter
->desc
->sptes
[iter
->pos
];
1343 iter
->desc
= iter
->desc
->more
;
1347 /* desc->sptes[0] cannot be NULL */
1348 sptep
= iter
->desc
->sptes
[iter
->pos
];
1355 BUG_ON(!is_shadow_present_pte(*sptep
));
1359 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1360 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1361 _spte_; _spte_ = rmap_get_next(_iter_))
1363 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1365 if (mmu_spte_clear_track_bits(sptep
))
1366 rmap_remove(kvm
, sptep
);
1370 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1372 if (is_large_pte(*sptep
)) {
1373 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1374 PT_PAGE_TABLE_LEVEL
);
1375 drop_spte(kvm
, sptep
);
1383 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1385 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1386 kvm_flush_remote_tlbs(vcpu
->kvm
);
1390 * Write-protect on the specified @sptep, @pt_protect indicates whether
1391 * spte write-protection is caused by protecting shadow page table.
1393 * Note: write protection is difference between dirty logging and spte
1395 * - for dirty logging, the spte can be set to writable at anytime if
1396 * its dirty bitmap is properly set.
1397 * - for spte protection, the spte can be writable only after unsync-ing
1400 * Return true if tlb need be flushed.
1402 static bool spte_write_protect(u64
*sptep
, bool pt_protect
)
1406 if (!is_writable_pte(spte
) &&
1407 !(pt_protect
&& spte_can_locklessly_be_made_writable(spte
)))
1410 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1413 spte
&= ~SPTE_MMU_WRITEABLE
;
1414 spte
= spte
& ~PT_WRITABLE_MASK
;
1416 return mmu_spte_update(sptep
, spte
);
1419 static bool __rmap_write_protect(struct kvm
*kvm
,
1420 struct kvm_rmap_head
*rmap_head
,
1424 struct rmap_iterator iter
;
1427 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1428 flush
|= spte_write_protect(sptep
, pt_protect
);
1433 static bool spte_clear_dirty(u64
*sptep
)
1437 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1439 spte
&= ~shadow_dirty_mask
;
1441 return mmu_spte_update(sptep
, spte
);
1444 static bool wrprot_ad_disabled_spte(u64
*sptep
)
1446 bool was_writable
= test_and_clear_bit(PT_WRITABLE_SHIFT
,
1447 (unsigned long *)sptep
);
1449 kvm_set_pfn_dirty(spte_to_pfn(*sptep
));
1451 return was_writable
;
1455 * Gets the GFN ready for another round of dirty logging by clearing the
1456 * - D bit on ad-enabled SPTEs, and
1457 * - W bit on ad-disabled SPTEs.
1458 * Returns true iff any D or W bits were cleared.
1460 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1463 struct rmap_iterator iter
;
1466 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1467 if (spte_ad_enabled(*sptep
))
1468 flush
|= spte_clear_dirty(sptep
);
1470 flush
|= wrprot_ad_disabled_spte(sptep
);
1475 static bool spte_set_dirty(u64
*sptep
)
1479 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1481 spte
|= shadow_dirty_mask
;
1483 return mmu_spte_update(sptep
, spte
);
1486 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1489 struct rmap_iterator iter
;
1492 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1493 if (spte_ad_enabled(*sptep
))
1494 flush
|= spte_set_dirty(sptep
);
1500 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1501 * @kvm: kvm instance
1502 * @slot: slot to protect
1503 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1504 * @mask: indicates which pages we should protect
1506 * Used when we do not need to care about huge page mappings: e.g. during dirty
1507 * logging we do not have any such mappings.
1509 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1510 struct kvm_memory_slot
*slot
,
1511 gfn_t gfn_offset
, unsigned long mask
)
1513 struct kvm_rmap_head
*rmap_head
;
1516 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1517 PT_PAGE_TABLE_LEVEL
, slot
);
1518 __rmap_write_protect(kvm
, rmap_head
, false);
1520 /* clear the first set bit */
1526 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1527 * protect the page if the D-bit isn't supported.
1528 * @kvm: kvm instance
1529 * @slot: slot to clear D-bit
1530 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1531 * @mask: indicates which pages we should clear D-bit
1533 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1535 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1536 struct kvm_memory_slot
*slot
,
1537 gfn_t gfn_offset
, unsigned long mask
)
1539 struct kvm_rmap_head
*rmap_head
;
1542 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1543 PT_PAGE_TABLE_LEVEL
, slot
);
1544 __rmap_clear_dirty(kvm
, rmap_head
);
1546 /* clear the first set bit */
1550 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1553 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1556 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1557 * enable dirty logging for them.
1559 * Used when we do not need to care about huge page mappings: e.g. during dirty
1560 * logging we do not have any such mappings.
1562 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1563 struct kvm_memory_slot
*slot
,
1564 gfn_t gfn_offset
, unsigned long mask
)
1566 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1567 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1570 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1574 * kvm_arch_write_log_dirty - emulate dirty page logging
1575 * @vcpu: Guest mode vcpu
1577 * Emulate arch specific page modification logging for the
1580 int kvm_arch_write_log_dirty(struct kvm_vcpu
*vcpu
)
1582 if (kvm_x86_ops
->write_log_dirty
)
1583 return kvm_x86_ops
->write_log_dirty(vcpu
);
1588 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1589 struct kvm_memory_slot
*slot
, u64 gfn
)
1591 struct kvm_rmap_head
*rmap_head
;
1593 bool write_protected
= false;
1595 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1596 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1597 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1600 return write_protected
;
1603 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1605 struct kvm_memory_slot
*slot
;
1607 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1608 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1611 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1614 struct rmap_iterator iter
;
1617 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1618 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1620 drop_spte(kvm
, sptep
);
1627 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1628 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1631 return kvm_zap_rmapp(kvm
, rmap_head
);
1634 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1635 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1639 struct rmap_iterator iter
;
1642 pte_t
*ptep
= (pte_t
*)data
;
1645 WARN_ON(pte_huge(*ptep
));
1646 new_pfn
= pte_pfn(*ptep
);
1649 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1650 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1651 sptep
, *sptep
, gfn
, level
);
1655 if (pte_write(*ptep
)) {
1656 drop_spte(kvm
, sptep
);
1659 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1660 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1662 new_spte
&= ~PT_WRITABLE_MASK
;
1663 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1665 new_spte
= mark_spte_for_access_track(new_spte
);
1667 mmu_spte_clear_track_bits(sptep
);
1668 mmu_spte_set(sptep
, new_spte
);
1673 kvm_flush_remote_tlbs(kvm
);
1678 struct slot_rmap_walk_iterator
{
1680 struct kvm_memory_slot
*slot
;
1686 /* output fields. */
1688 struct kvm_rmap_head
*rmap
;
1691 /* private field. */
1692 struct kvm_rmap_head
*end_rmap
;
1696 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1698 iterator
->level
= level
;
1699 iterator
->gfn
= iterator
->start_gfn
;
1700 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1701 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1706 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1707 struct kvm_memory_slot
*slot
, int start_level
,
1708 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1710 iterator
->slot
= slot
;
1711 iterator
->start_level
= start_level
;
1712 iterator
->end_level
= end_level
;
1713 iterator
->start_gfn
= start_gfn
;
1714 iterator
->end_gfn
= end_gfn
;
1716 rmap_walk_init_level(iterator
, iterator
->start_level
);
1719 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1721 return !!iterator
->rmap
;
1724 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1726 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1727 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1731 if (++iterator
->level
> iterator
->end_level
) {
1732 iterator
->rmap
= NULL
;
1736 rmap_walk_init_level(iterator
, iterator
->level
);
1739 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1740 _start_gfn, _end_gfn, _iter_) \
1741 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1742 _end_level_, _start_gfn, _end_gfn); \
1743 slot_rmap_walk_okay(_iter_); \
1744 slot_rmap_walk_next(_iter_))
1746 static int kvm_handle_hva_range(struct kvm
*kvm
,
1747 unsigned long start
,
1750 int (*handler
)(struct kvm
*kvm
,
1751 struct kvm_rmap_head
*rmap_head
,
1752 struct kvm_memory_slot
*slot
,
1755 unsigned long data
))
1757 struct kvm_memslots
*slots
;
1758 struct kvm_memory_slot
*memslot
;
1759 struct slot_rmap_walk_iterator iterator
;
1763 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1764 slots
= __kvm_memslots(kvm
, i
);
1765 kvm_for_each_memslot(memslot
, slots
) {
1766 unsigned long hva_start
, hva_end
;
1767 gfn_t gfn_start
, gfn_end
;
1769 hva_start
= max(start
, memslot
->userspace_addr
);
1770 hva_end
= min(end
, memslot
->userspace_addr
+
1771 (memslot
->npages
<< PAGE_SHIFT
));
1772 if (hva_start
>= hva_end
)
1775 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1776 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1778 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1779 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1781 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1782 PT_MAX_HUGEPAGE_LEVEL
,
1783 gfn_start
, gfn_end
- 1,
1785 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1786 iterator
.gfn
, iterator
.level
, data
);
1793 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1795 int (*handler
)(struct kvm
*kvm
,
1796 struct kvm_rmap_head
*rmap_head
,
1797 struct kvm_memory_slot
*slot
,
1798 gfn_t gfn
, int level
,
1799 unsigned long data
))
1801 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1804 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1806 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1809 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1811 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1814 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1816 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1819 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1820 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1824 struct rmap_iterator
uninitialized_var(iter
);
1827 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1828 young
|= mmu_spte_age(sptep
);
1830 trace_kvm_age_page(gfn
, level
, slot
, young
);
1834 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1835 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1836 int level
, unsigned long data
)
1839 struct rmap_iterator iter
;
1841 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1842 if (is_accessed_spte(*sptep
))
1847 #define RMAP_RECYCLE_THRESHOLD 1000
1849 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1851 struct kvm_rmap_head
*rmap_head
;
1852 struct kvm_mmu_page
*sp
;
1854 sp
= page_header(__pa(spte
));
1856 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1858 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1859 kvm_flush_remote_tlbs(vcpu
->kvm
);
1862 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1864 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1867 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1869 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1873 static int is_empty_shadow_page(u64
*spt
)
1878 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1879 if (is_shadow_present_pte(*pos
)) {
1880 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1889 * This value is the sum of all of the kvm instances's
1890 * kvm->arch.n_used_mmu_pages values. We need a global,
1891 * aggregate version in order to make the slab shrinker
1894 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1896 kvm
->arch
.n_used_mmu_pages
+= nr
;
1897 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1900 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1902 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1903 hlist_del(&sp
->hash_link
);
1904 list_del(&sp
->link
);
1905 free_page((unsigned long)sp
->spt
);
1906 if (!sp
->role
.direct
)
1907 free_page((unsigned long)sp
->gfns
);
1908 kmem_cache_free(mmu_page_header_cache
, sp
);
1911 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1913 return hash_64(gfn
, KVM_MMU_HASH_SHIFT
);
1916 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1917 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1922 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1925 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1928 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1931 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1934 mmu_page_remove_parent_pte(sp
, parent_pte
);
1935 mmu_spte_clear_no_track(parent_pte
);
1938 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1940 struct kvm_mmu_page
*sp
;
1942 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1943 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1945 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1946 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1949 * The active_mmu_pages list is the FIFO list, do not move the
1950 * page until it is zapped. kvm_zap_obsolete_pages depends on
1951 * this feature. See the comments in kvm_zap_obsolete_pages().
1953 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1954 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1958 static void mark_unsync(u64
*spte
);
1959 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1962 struct rmap_iterator iter
;
1964 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1969 static void mark_unsync(u64
*spte
)
1971 struct kvm_mmu_page
*sp
;
1974 sp
= page_header(__pa(spte
));
1975 index
= spte
- sp
->spt
;
1976 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1978 if (sp
->unsync_children
++)
1980 kvm_mmu_mark_parents_unsync(sp
);
1983 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1984 struct kvm_mmu_page
*sp
)
1989 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1993 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1994 struct kvm_mmu_page
*sp
, u64
*spte
,
2000 #define KVM_PAGE_ARRAY_NR 16
2002 struct kvm_mmu_pages
{
2003 struct mmu_page_and_offset
{
2004 struct kvm_mmu_page
*sp
;
2006 } page
[KVM_PAGE_ARRAY_NR
];
2010 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
2016 for (i
=0; i
< pvec
->nr
; i
++)
2017 if (pvec
->page
[i
].sp
== sp
)
2020 pvec
->page
[pvec
->nr
].sp
= sp
;
2021 pvec
->page
[pvec
->nr
].idx
= idx
;
2023 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
2026 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
2028 --sp
->unsync_children
;
2029 WARN_ON((int)sp
->unsync_children
< 0);
2030 __clear_bit(idx
, sp
->unsync_child_bitmap
);
2033 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2034 struct kvm_mmu_pages
*pvec
)
2036 int i
, ret
, nr_unsync_leaf
= 0;
2038 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
2039 struct kvm_mmu_page
*child
;
2040 u64 ent
= sp
->spt
[i
];
2042 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
2043 clear_unsync_child_bit(sp
, i
);
2047 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
2049 if (child
->unsync_children
) {
2050 if (mmu_pages_add(pvec
, child
, i
))
2053 ret
= __mmu_unsync_walk(child
, pvec
);
2055 clear_unsync_child_bit(sp
, i
);
2057 } else if (ret
> 0) {
2058 nr_unsync_leaf
+= ret
;
2061 } else if (child
->unsync
) {
2063 if (mmu_pages_add(pvec
, child
, i
))
2066 clear_unsync_child_bit(sp
, i
);
2069 return nr_unsync_leaf
;
2072 #define INVALID_INDEX (-1)
2074 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
2075 struct kvm_mmu_pages
*pvec
)
2078 if (!sp
->unsync_children
)
2081 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
2082 return __mmu_unsync_walk(sp
, pvec
);
2085 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2087 WARN_ON(!sp
->unsync
);
2088 trace_kvm_mmu_sync_page(sp
);
2090 --kvm
->stat
.mmu_unsync
;
2093 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2094 struct list_head
*invalid_list
);
2095 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2096 struct list_head
*invalid_list
);
2099 * NOTE: we should pay more attention on the zapped-obsolete page
2100 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2101 * since it has been deleted from active_mmu_pages but still can be found
2104 * for_each_valid_sp() has skipped that kind of pages.
2106 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2107 hlist_for_each_entry(_sp, \
2108 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2109 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2112 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2113 for_each_valid_sp(_kvm, _sp, _gfn) \
2114 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2116 /* @sp->gfn should be write-protected at the call site */
2117 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2118 struct list_head
*invalid_list
)
2120 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
2121 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2125 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
2126 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
2133 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
2134 struct list_head
*invalid_list
,
2135 bool remote_flush
, bool local_flush
)
2137 if (!list_empty(invalid_list
)) {
2138 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
2143 kvm_flush_remote_tlbs(vcpu
->kvm
);
2144 else if (local_flush
)
2145 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2148 #ifdef CONFIG_KVM_MMU_AUDIT
2149 #include "mmu_audit.c"
2151 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
2152 static void mmu_audit_disable(void) { }
2155 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2157 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2160 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2161 struct list_head
*invalid_list
)
2163 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
2164 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
2167 /* @gfn should be write-protected at the call site */
2168 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2169 struct list_head
*invalid_list
)
2171 struct kvm_mmu_page
*s
;
2174 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
2178 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2179 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
2185 struct mmu_page_path
{
2186 struct kvm_mmu_page
*parent
[PT64_ROOT_MAX_LEVEL
];
2187 unsigned int idx
[PT64_ROOT_MAX_LEVEL
];
2190 #define for_each_sp(pvec, sp, parents, i) \
2191 for (i = mmu_pages_first(&pvec, &parents); \
2192 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2193 i = mmu_pages_next(&pvec, &parents, i))
2195 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
2196 struct mmu_page_path
*parents
,
2201 for (n
= i
+1; n
< pvec
->nr
; n
++) {
2202 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
2203 unsigned idx
= pvec
->page
[n
].idx
;
2204 int level
= sp
->role
.level
;
2206 parents
->idx
[level
-1] = idx
;
2207 if (level
== PT_PAGE_TABLE_LEVEL
)
2210 parents
->parent
[level
-2] = sp
;
2216 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2217 struct mmu_page_path
*parents
)
2219 struct kvm_mmu_page
*sp
;
2225 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2227 sp
= pvec
->page
[0].sp
;
2228 level
= sp
->role
.level
;
2229 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2231 parents
->parent
[level
-2] = sp
;
2233 /* Also set up a sentinel. Further entries in pvec are all
2234 * children of sp, so this element is never overwritten.
2236 parents
->parent
[level
-1] = NULL
;
2237 return mmu_pages_next(pvec
, parents
, 0);
2240 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2242 struct kvm_mmu_page
*sp
;
2243 unsigned int level
= 0;
2246 unsigned int idx
= parents
->idx
[level
];
2247 sp
= parents
->parent
[level
];
2251 WARN_ON(idx
== INVALID_INDEX
);
2252 clear_unsync_child_bit(sp
, idx
);
2254 } while (!sp
->unsync_children
);
2257 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2258 struct kvm_mmu_page
*parent
)
2261 struct kvm_mmu_page
*sp
;
2262 struct mmu_page_path parents
;
2263 struct kvm_mmu_pages pages
;
2264 LIST_HEAD(invalid_list
);
2267 while (mmu_unsync_walk(parent
, &pages
)) {
2268 bool protected = false;
2270 for_each_sp(pages
, sp
, parents
, i
)
2271 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2274 kvm_flush_remote_tlbs(vcpu
->kvm
);
2278 for_each_sp(pages
, sp
, parents
, i
) {
2279 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2280 mmu_pages_clear_parents(&parents
);
2282 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2283 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2284 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2289 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2292 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2294 atomic_set(&sp
->write_flooding_count
, 0);
2297 static void clear_sp_write_flooding_count(u64
*spte
)
2299 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2301 __clear_sp_write_flooding_count(sp
);
2304 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2311 union kvm_mmu_page_role role
;
2313 struct kvm_mmu_page
*sp
;
2314 bool need_sync
= false;
2317 LIST_HEAD(invalid_list
);
2319 role
= vcpu
->arch
.mmu
.base_role
;
2321 role
.direct
= direct
;
2324 role
.access
= access
;
2325 if (!vcpu
->arch
.mmu
.direct_map
2326 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2327 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2328 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2329 role
.quadrant
= quadrant
;
2331 for_each_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2332 if (sp
->gfn
!= gfn
) {
2337 if (!need_sync
&& sp
->unsync
)
2340 if (sp
->role
.word
!= role
.word
)
2344 /* The page is good, but __kvm_sync_page might still end
2345 * up zapping it. If so, break in order to rebuild it.
2347 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2350 WARN_ON(!list_empty(&invalid_list
));
2351 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2354 if (sp
->unsync_children
)
2355 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2357 __clear_sp_write_flooding_count(sp
);
2358 trace_kvm_mmu_get_page(sp
, false);
2362 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2364 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2368 hlist_add_head(&sp
->hash_link
,
2369 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2372 * we should do write protection before syncing pages
2373 * otherwise the content of the synced shadow page may
2374 * be inconsistent with guest page table.
2376 account_shadowed(vcpu
->kvm
, sp
);
2377 if (level
== PT_PAGE_TABLE_LEVEL
&&
2378 rmap_write_protect(vcpu
, gfn
))
2379 kvm_flush_remote_tlbs(vcpu
->kvm
);
2381 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2382 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2384 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2385 clear_page(sp
->spt
);
2386 trace_kvm_mmu_get_page(sp
, true);
2388 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2390 if (collisions
> vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
)
2391 vcpu
->kvm
->stat
.max_mmu_page_hash_collisions
= collisions
;
2395 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2396 struct kvm_vcpu
*vcpu
, u64 addr
)
2398 iterator
->addr
= addr
;
2399 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2400 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2402 if (iterator
->level
== PT64_ROOT_4LEVEL
&&
2403 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_4LEVEL
&&
2404 !vcpu
->arch
.mmu
.direct_map
)
2407 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2408 iterator
->shadow_addr
2409 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2410 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2412 if (!iterator
->shadow_addr
)
2413 iterator
->level
= 0;
2417 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2419 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2422 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2423 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2427 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2430 if (is_last_spte(spte
, iterator
->level
)) {
2431 iterator
->level
= 0;
2435 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2439 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2441 __shadow_walk_next(iterator
, *iterator
->sptep
);
2444 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2445 struct kvm_mmu_page
*sp
)
2449 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2451 spte
= __pa(sp
->spt
) | shadow_present_mask
| PT_WRITABLE_MASK
|
2452 shadow_user_mask
| shadow_x_mask
| shadow_me_mask
;
2454 if (sp_ad_disabled(sp
))
2455 spte
|= shadow_acc_track_value
;
2457 spte
|= shadow_accessed_mask
;
2459 mmu_spte_set(sptep
, spte
);
2461 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2463 if (sp
->unsync_children
|| sp
->unsync
)
2467 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2468 unsigned direct_access
)
2470 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2471 struct kvm_mmu_page
*child
;
2474 * For the direct sp, if the guest pte's dirty bit
2475 * changed form clean to dirty, it will corrupt the
2476 * sp's access: allow writable in the read-only sp,
2477 * so we should update the spte at this point to get
2478 * a new sp with the correct access.
2480 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2481 if (child
->role
.access
== direct_access
)
2484 drop_parent_pte(child
, sptep
);
2485 kvm_flush_remote_tlbs(vcpu
->kvm
);
2489 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2493 struct kvm_mmu_page
*child
;
2496 if (is_shadow_present_pte(pte
)) {
2497 if (is_last_spte(pte
, sp
->role
.level
)) {
2498 drop_spte(kvm
, spte
);
2499 if (is_large_pte(pte
))
2502 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2503 drop_parent_pte(child
, spte
);
2508 if (is_mmio_spte(pte
))
2509 mmu_spte_clear_no_track(spte
);
2514 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2515 struct kvm_mmu_page
*sp
)
2519 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2520 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2523 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2526 struct rmap_iterator iter
;
2528 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2529 drop_parent_pte(sp
, sptep
);
2532 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2533 struct kvm_mmu_page
*parent
,
2534 struct list_head
*invalid_list
)
2537 struct mmu_page_path parents
;
2538 struct kvm_mmu_pages pages
;
2540 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2543 while (mmu_unsync_walk(parent
, &pages
)) {
2544 struct kvm_mmu_page
*sp
;
2546 for_each_sp(pages
, sp
, parents
, i
) {
2547 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2548 mmu_pages_clear_parents(&parents
);
2556 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2557 struct list_head
*invalid_list
)
2561 trace_kvm_mmu_prepare_zap_page(sp
);
2562 ++kvm
->stat
.mmu_shadow_zapped
;
2563 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2564 kvm_mmu_page_unlink_children(kvm
, sp
);
2565 kvm_mmu_unlink_parents(kvm
, sp
);
2567 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2568 unaccount_shadowed(kvm
, sp
);
2571 kvm_unlink_unsync_page(kvm
, sp
);
2572 if (!sp
->root_count
) {
2575 list_move(&sp
->link
, invalid_list
);
2576 kvm_mod_used_mmu_pages(kvm
, -1);
2578 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2581 * The obsolete pages can not be used on any vcpus.
2582 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2584 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2585 kvm_reload_remote_mmus(kvm
);
2588 sp
->role
.invalid
= 1;
2592 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2593 struct list_head
*invalid_list
)
2595 struct kvm_mmu_page
*sp
, *nsp
;
2597 if (list_empty(invalid_list
))
2601 * We need to make sure everyone sees our modifications to
2602 * the page tables and see changes to vcpu->mode here. The barrier
2603 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2604 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2606 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2607 * guest mode and/or lockless shadow page table walks.
2609 kvm_flush_remote_tlbs(kvm
);
2611 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2612 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2613 kvm_mmu_free_page(sp
);
2617 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2618 struct list_head
*invalid_list
)
2620 struct kvm_mmu_page
*sp
;
2622 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2625 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2626 struct kvm_mmu_page
, link
);
2627 return kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2631 * Changing the number of mmu pages allocated to the vm
2632 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2634 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2636 LIST_HEAD(invalid_list
);
2638 spin_lock(&kvm
->mmu_lock
);
2640 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2641 /* Need to free some mmu pages to achieve the goal. */
2642 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2643 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2646 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2647 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2650 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2652 spin_unlock(&kvm
->mmu_lock
);
2655 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2657 struct kvm_mmu_page
*sp
;
2658 LIST_HEAD(invalid_list
);
2661 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2663 spin_lock(&kvm
->mmu_lock
);
2664 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2665 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2668 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2670 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2671 spin_unlock(&kvm
->mmu_lock
);
2675 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2677 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2679 trace_kvm_mmu_unsync_page(sp
);
2680 ++vcpu
->kvm
->stat
.mmu_unsync
;
2683 kvm_mmu_mark_parents_unsync(sp
);
2686 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2689 struct kvm_mmu_page
*sp
;
2691 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2694 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2701 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2702 kvm_unsync_page(vcpu
, sp
);
2708 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2711 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2716 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2717 unsigned pte_access
, int level
,
2718 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2719 bool can_unsync
, bool host_writable
)
2723 struct kvm_mmu_page
*sp
;
2725 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2728 sp
= page_header(__pa(sptep
));
2729 if (sp_ad_disabled(sp
))
2730 spte
|= shadow_acc_track_value
;
2733 * For the EPT case, shadow_present_mask is 0 if hardware
2734 * supports exec-only page table entries. In that case,
2735 * ACC_USER_MASK and shadow_user_mask are used to represent
2736 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2738 spte
|= shadow_present_mask
;
2740 spte
|= spte_shadow_accessed_mask(spte
);
2742 if (pte_access
& ACC_EXEC_MASK
)
2743 spte
|= shadow_x_mask
;
2745 spte
|= shadow_nx_mask
;
2747 if (pte_access
& ACC_USER_MASK
)
2748 spte
|= shadow_user_mask
;
2750 if (level
> PT_PAGE_TABLE_LEVEL
)
2751 spte
|= PT_PAGE_SIZE_MASK
;
2753 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2754 kvm_is_mmio_pfn(pfn
));
2757 spte
|= SPTE_HOST_WRITEABLE
;
2759 pte_access
&= ~ACC_WRITE_MASK
;
2761 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2762 spte
|= shadow_me_mask
;
2764 if (pte_access
& ACC_WRITE_MASK
) {
2767 * Other vcpu creates new sp in the window between
2768 * mapping_level() and acquiring mmu-lock. We can
2769 * allow guest to retry the access, the mapping can
2770 * be fixed if guest refault.
2772 if (level
> PT_PAGE_TABLE_LEVEL
&&
2773 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2776 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2779 * Optimization: for pte sync, if spte was writable the hash
2780 * lookup is unnecessary (and expensive). Write protection
2781 * is responsibility of mmu_get_page / kvm_sync_page.
2782 * Same reasoning can be applied to dirty page accounting.
2784 if (!can_unsync
&& is_writable_pte(*sptep
))
2787 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2788 pgprintk("%s: found shadow page for %llx, marking ro\n",
2791 pte_access
&= ~ACC_WRITE_MASK
;
2792 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2796 if (pte_access
& ACC_WRITE_MASK
) {
2797 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2798 spte
|= spte_shadow_dirty_mask(spte
);
2802 spte
= mark_spte_for_access_track(spte
);
2805 if (mmu_spte_update(sptep
, spte
))
2806 kvm_flush_remote_tlbs(vcpu
->kvm
);
2811 static int mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2812 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2813 bool speculative
, bool host_writable
)
2815 int was_rmapped
= 0;
2817 int ret
= RET_PF_RETRY
;
2819 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2820 *sptep
, write_fault
, gfn
);
2822 if (is_shadow_present_pte(*sptep
)) {
2824 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2825 * the parent of the now unreachable PTE.
2827 if (level
> PT_PAGE_TABLE_LEVEL
&&
2828 !is_large_pte(*sptep
)) {
2829 struct kvm_mmu_page
*child
;
2832 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2833 drop_parent_pte(child
, sptep
);
2834 kvm_flush_remote_tlbs(vcpu
->kvm
);
2835 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2836 pgprintk("hfn old %llx new %llx\n",
2837 spte_to_pfn(*sptep
), pfn
);
2838 drop_spte(vcpu
->kvm
, sptep
);
2839 kvm_flush_remote_tlbs(vcpu
->kvm
);
2844 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2845 true, host_writable
)) {
2847 ret
= RET_PF_EMULATE
;
2848 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2851 if (unlikely(is_mmio_spte(*sptep
)))
2852 ret
= RET_PF_EMULATE
;
2854 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2855 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2856 is_large_pte(*sptep
)? "2MB" : "4kB",
2857 *sptep
& PT_WRITABLE_MASK
? "RW" : "R", gfn
,
2859 if (!was_rmapped
&& is_large_pte(*sptep
))
2860 ++vcpu
->kvm
->stat
.lpages
;
2862 if (is_shadow_present_pte(*sptep
)) {
2864 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2865 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2866 rmap_recycle(vcpu
, sptep
, gfn
);
2870 kvm_release_pfn_clean(pfn
);
2875 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2878 struct kvm_memory_slot
*slot
;
2880 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2882 return KVM_PFN_ERR_FAULT
;
2884 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2887 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2888 struct kvm_mmu_page
*sp
,
2889 u64
*start
, u64
*end
)
2891 struct page
*pages
[PTE_PREFETCH_NUM
];
2892 struct kvm_memory_slot
*slot
;
2893 unsigned access
= sp
->role
.access
;
2897 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2898 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2902 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2906 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2907 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2908 page_to_pfn(pages
[i
]), true, true);
2913 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2914 struct kvm_mmu_page
*sp
, u64
*sptep
)
2916 u64
*spte
, *start
= NULL
;
2919 WARN_ON(!sp
->role
.direct
);
2921 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2924 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2925 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2928 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2936 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2938 struct kvm_mmu_page
*sp
;
2940 sp
= page_header(__pa(sptep
));
2943 * Without accessed bits, there's no way to distinguish between
2944 * actually accessed translations and prefetched, so disable pte
2945 * prefetch if accessed bits aren't available.
2947 if (sp_ad_disabled(sp
))
2950 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2953 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2956 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2957 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2959 struct kvm_shadow_walk_iterator iterator
;
2960 struct kvm_mmu_page
*sp
;
2964 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2967 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2968 if (iterator
.level
== level
) {
2969 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2970 write
, level
, gfn
, pfn
, prefault
,
2972 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2973 ++vcpu
->stat
.pf_fixed
;
2977 drop_large_spte(vcpu
, iterator
.sptep
);
2978 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2979 u64 base_addr
= iterator
.addr
;
2981 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2982 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2983 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2984 iterator
.level
- 1, 1, ACC_ALL
);
2986 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2992 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2996 info
.si_signo
= SIGBUS
;
2998 info
.si_code
= BUS_MCEERR_AR
;
2999 info
.si_addr
= (void __user
*)address
;
3000 info
.si_addr_lsb
= PAGE_SHIFT
;
3002 send_sig_info(SIGBUS
, &info
, tsk
);
3005 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
3008 * Do not cache the mmio info caused by writing the readonly gfn
3009 * into the spte otherwise read access on readonly gfn also can
3010 * caused mmio page fault and treat it as mmio access.
3012 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
3013 return RET_PF_EMULATE
;
3015 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
3016 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
3017 return RET_PF_RETRY
;
3023 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
3024 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
3027 kvm_pfn_t pfn
= *pfnp
;
3029 int level
= *levelp
;
3032 * Check if it's a transparent hugepage. If this would be an
3033 * hugetlbfs page, level wouldn't be set to
3034 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3037 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
3038 level
== PT_PAGE_TABLE_LEVEL
&&
3039 PageTransCompoundMap(pfn_to_page(pfn
)) &&
3040 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
3043 * mmu_notifier_retry was successful and we hold the
3044 * mmu_lock here, so the pmd can't become splitting
3045 * from under us, and in turn
3046 * __split_huge_page_refcount() can't run from under
3047 * us and we can safely transfer the refcount from
3048 * PG_tail to PG_head as we switch the pfn to tail to
3051 *levelp
= level
= PT_DIRECTORY_LEVEL
;
3052 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
3053 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
3057 kvm_release_pfn_clean(pfn
);
3065 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
3066 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
3068 /* The pfn is invalid, report the error! */
3069 if (unlikely(is_error_pfn(pfn
))) {
3070 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
3074 if (unlikely(is_noslot_pfn(pfn
)))
3075 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
3080 static bool page_fault_can_be_fast(u32 error_code
)
3083 * Do not fix the mmio spte with invalid generation number which
3084 * need to be updated by slow page fault path.
3086 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3089 /* See if the page fault is due to an NX violation */
3090 if (unlikely(((error_code
& (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))
3091 == (PFERR_FETCH_MASK
| PFERR_PRESENT_MASK
))))
3095 * #PF can be fast if:
3096 * 1. The shadow page table entry is not present, which could mean that
3097 * the fault is potentially caused by access tracking (if enabled).
3098 * 2. The shadow page table entry is present and the fault
3099 * is caused by write-protect, that means we just need change the W
3100 * bit of the spte which can be done out of mmu-lock.
3102 * However, if access tracking is disabled we know that a non-present
3103 * page must be a genuine page fault where we have to create a new SPTE.
3104 * So, if access tracking is disabled, we return true only for write
3105 * accesses to a present page.
3108 return shadow_acc_track_mask
!= 0 ||
3109 ((error_code
& (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
))
3110 == (PFERR_WRITE_MASK
| PFERR_PRESENT_MASK
));
3114 * Returns true if the SPTE was fixed successfully. Otherwise,
3115 * someone else modified the SPTE from its original value.
3118 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
3119 u64
*sptep
, u64 old_spte
, u64 new_spte
)
3123 WARN_ON(!sp
->role
.direct
);
3126 * Theoretically we could also set dirty bit (and flush TLB) here in
3127 * order to eliminate unnecessary PML logging. See comments in
3128 * set_spte. But fast_page_fault is very unlikely to happen with PML
3129 * enabled, so we do not do this. This might result in the same GPA
3130 * to be logged in PML buffer again when the write really happens, and
3131 * eventually to be called by mark_page_dirty twice. But it's also no
3132 * harm. This also avoids the TLB flush needed after setting dirty bit
3133 * so non-PML cases won't be impacted.
3135 * Compare with set_spte where instead shadow_dirty_mask is set.
3137 if (cmpxchg64(sptep
, old_spte
, new_spte
) != old_spte
)
3140 if (is_writable_pte(new_spte
) && !is_writable_pte(old_spte
)) {
3142 * The gfn of direct spte is stable since it is
3143 * calculated by sp->gfn.
3145 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
3146 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
3152 static bool is_access_allowed(u32 fault_err_code
, u64 spte
)
3154 if (fault_err_code
& PFERR_FETCH_MASK
)
3155 return is_executable_pte(spte
);
3157 if (fault_err_code
& PFERR_WRITE_MASK
)
3158 return is_writable_pte(spte
);
3160 /* Fault was on Read access */
3161 return spte
& PT_PRESENT_MASK
;
3166 * - true: let the vcpu to access on the same address again.
3167 * - false: let the real page fault path to fix it.
3169 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
3172 struct kvm_shadow_walk_iterator iterator
;
3173 struct kvm_mmu_page
*sp
;
3174 bool fault_handled
= false;
3176 uint retry_count
= 0;
3178 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3181 if (!page_fault_can_be_fast(error_code
))
3184 walk_shadow_page_lockless_begin(vcpu
);
3189 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
3190 if (!is_shadow_present_pte(spte
) ||
3191 iterator
.level
< level
)
3194 sp
= page_header(__pa(iterator
.sptep
));
3195 if (!is_last_spte(spte
, sp
->role
.level
))
3199 * Check whether the memory access that caused the fault would
3200 * still cause it if it were to be performed right now. If not,
3201 * then this is a spurious fault caused by TLB lazily flushed,
3202 * or some other CPU has already fixed the PTE after the
3203 * current CPU took the fault.
3205 * Need not check the access of upper level table entries since
3206 * they are always ACC_ALL.
3208 if (is_access_allowed(error_code
, spte
)) {
3209 fault_handled
= true;
3215 if (is_access_track_spte(spte
))
3216 new_spte
= restore_acc_track_spte(new_spte
);
3219 * Currently, to simplify the code, write-protection can
3220 * be removed in the fast path only if the SPTE was
3221 * write-protected for dirty-logging or access tracking.
3223 if ((error_code
& PFERR_WRITE_MASK
) &&
3224 spte_can_locklessly_be_made_writable(spte
))
3226 new_spte
|= PT_WRITABLE_MASK
;
3229 * Do not fix write-permission on the large spte. Since
3230 * we only dirty the first page into the dirty-bitmap in
3231 * fast_pf_fix_direct_spte(), other pages are missed
3232 * if its slot has dirty logging enabled.
3234 * Instead, we let the slow page fault path create a
3235 * normal spte to fix the access.
3237 * See the comments in kvm_arch_commit_memory_region().
3239 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
3243 /* Verify that the fault can be handled in the fast path */
3244 if (new_spte
== spte
||
3245 !is_access_allowed(error_code
, new_spte
))
3249 * Currently, fast page fault only works for direct mapping
3250 * since the gfn is not stable for indirect shadow page. See
3251 * Documentation/virtual/kvm/locking.txt to get more detail.
3253 fault_handled
= fast_pf_fix_direct_spte(vcpu
, sp
,
3254 iterator
.sptep
, spte
,
3259 if (++retry_count
> 4) {
3260 printk_once(KERN_WARNING
3261 "kvm: Fast #PF retrying more than 4 times.\n");
3267 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
3268 spte
, fault_handled
);
3269 walk_shadow_page_lockless_end(vcpu
);
3271 return fault_handled
;
3274 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3275 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
3276 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
3278 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
3279 gfn_t gfn
, bool prefault
)
3283 bool force_pt_level
= false;
3285 unsigned long mmu_seq
;
3286 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3288 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3289 if (likely(!force_pt_level
)) {
3291 * This path builds a PAE pagetable - so we can map
3292 * 2mb pages at maximum. Therefore check if the level
3293 * is larger than that.
3295 if (level
> PT_DIRECTORY_LEVEL
)
3296 level
= PT_DIRECTORY_LEVEL
;
3298 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3301 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3302 return RET_PF_RETRY
;
3304 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3307 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3308 return RET_PF_RETRY
;
3310 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3313 spin_lock(&vcpu
->kvm
->mmu_lock
);
3314 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3316 if (make_mmu_pages_available(vcpu
) < 0)
3318 if (likely(!force_pt_level
))
3319 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3320 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3321 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3326 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3327 kvm_release_pfn_clean(pfn
);
3328 return RET_PF_RETRY
;
3332 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3335 struct kvm_mmu_page
*sp
;
3336 LIST_HEAD(invalid_list
);
3338 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3341 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
&&
3342 (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
||
3343 vcpu
->arch
.mmu
.direct_map
)) {
3344 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3346 spin_lock(&vcpu
->kvm
->mmu_lock
);
3347 sp
= page_header(root
);
3349 if (!sp
->root_count
&& sp
->role
.invalid
) {
3350 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3351 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3353 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3354 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3358 spin_lock(&vcpu
->kvm
->mmu_lock
);
3359 for (i
= 0; i
< 4; ++i
) {
3360 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3363 root
&= PT64_BASE_ADDR_MASK
;
3364 sp
= page_header(root
);
3366 if (!sp
->root_count
&& sp
->role
.invalid
)
3367 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3370 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3372 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3373 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3374 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3377 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3381 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3382 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3389 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3391 struct kvm_mmu_page
*sp
;
3394 if (vcpu
->arch
.mmu
.shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3395 spin_lock(&vcpu
->kvm
->mmu_lock
);
3396 if(make_mmu_pages_available(vcpu
) < 0) {
3397 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3400 sp
= kvm_mmu_get_page(vcpu
, 0, 0,
3401 vcpu
->arch
.mmu
.shadow_root_level
, 1, ACC_ALL
);
3403 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3404 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3405 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3406 for (i
= 0; i
< 4; ++i
) {
3407 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3409 MMU_WARN_ON(VALID_PAGE(root
));
3410 spin_lock(&vcpu
->kvm
->mmu_lock
);
3411 if (make_mmu_pages_available(vcpu
) < 0) {
3412 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3415 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3416 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3417 root
= __pa(sp
->spt
);
3419 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3420 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3422 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3429 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3431 struct kvm_mmu_page
*sp
;
3436 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3438 if (mmu_check_root(vcpu
, root_gfn
))
3442 * Do we shadow a long mode page table? If so we need to
3443 * write-protect the guests page table root.
3445 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3446 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3448 MMU_WARN_ON(VALID_PAGE(root
));
3450 spin_lock(&vcpu
->kvm
->mmu_lock
);
3451 if (make_mmu_pages_available(vcpu
) < 0) {
3452 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3455 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0,
3456 vcpu
->arch
.mmu
.shadow_root_level
, 0, ACC_ALL
);
3457 root
= __pa(sp
->spt
);
3459 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3460 vcpu
->arch
.mmu
.root_hpa
= root
;
3465 * We shadow a 32 bit page table. This may be a legacy 2-level
3466 * or a PAE 3-level page table. In either case we need to be aware that
3467 * the shadow page table may be a PAE or a long mode page table.
3469 pm_mask
= PT_PRESENT_MASK
;
3470 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
)
3471 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3473 for (i
= 0; i
< 4; ++i
) {
3474 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3476 MMU_WARN_ON(VALID_PAGE(root
));
3477 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3478 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3479 if (!(pdptr
& PT_PRESENT_MASK
)) {
3480 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3483 root_gfn
= pdptr
>> PAGE_SHIFT
;
3484 if (mmu_check_root(vcpu
, root_gfn
))
3487 spin_lock(&vcpu
->kvm
->mmu_lock
);
3488 if (make_mmu_pages_available(vcpu
) < 0) {
3489 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3492 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3494 root
= __pa(sp
->spt
);
3496 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3498 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3500 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3503 * If we shadow a 32 bit page table with a long mode page
3504 * table we enter this path.
3506 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_4LEVEL
) {
3507 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3509 * The additional page necessary for this is only
3510 * allocated on demand.
3515 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3516 if (lm_root
== NULL
)
3519 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3521 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3524 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3530 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3532 if (vcpu
->arch
.mmu
.direct_map
)
3533 return mmu_alloc_direct_roots(vcpu
);
3535 return mmu_alloc_shadow_roots(vcpu
);
3538 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3541 struct kvm_mmu_page
*sp
;
3543 if (vcpu
->arch
.mmu
.direct_map
)
3546 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3549 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3550 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3551 if (vcpu
->arch
.mmu
.root_level
>= PT64_ROOT_4LEVEL
) {
3552 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3553 sp
= page_header(root
);
3554 mmu_sync_children(vcpu
, sp
);
3555 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3558 for (i
= 0; i
< 4; ++i
) {
3559 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3561 if (root
&& VALID_PAGE(root
)) {
3562 root
&= PT64_BASE_ADDR_MASK
;
3563 sp
= page_header(root
);
3564 mmu_sync_children(vcpu
, sp
);
3567 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3570 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3572 spin_lock(&vcpu
->kvm
->mmu_lock
);
3573 mmu_sync_roots(vcpu
);
3574 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3576 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3578 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3579 u32 access
, struct x86_exception
*exception
)
3582 exception
->error_code
= 0;
3586 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3588 struct x86_exception
*exception
)
3591 exception
->error_code
= 0;
3592 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3596 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3598 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3600 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3601 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3604 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3606 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3609 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3611 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3614 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3617 * A nested guest cannot use the MMIO cache if it is using nested
3618 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3620 if (mmu_is_nested(vcpu
))
3624 return vcpu_match_mmio_gpa(vcpu
, addr
);
3626 return vcpu_match_mmio_gva(vcpu
, addr
);
3629 /* return true if reserved bit is detected on spte. */
3631 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3633 struct kvm_shadow_walk_iterator iterator
;
3634 u64 sptes
[PT64_ROOT_MAX_LEVEL
], spte
= 0ull;
3636 bool reserved
= false;
3638 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3641 walk_shadow_page_lockless_begin(vcpu
);
3643 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3644 leaf
= root
= iterator
.level
;
3645 shadow_walk_okay(&iterator
);
3646 __shadow_walk_next(&iterator
, spte
)) {
3647 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3649 sptes
[leaf
- 1] = spte
;
3652 if (!is_shadow_present_pte(spte
))
3655 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3659 walk_shadow_page_lockless_end(vcpu
);
3662 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3664 while (root
> leaf
) {
3665 pr_err("------ spte 0x%llx level %d.\n",
3666 sptes
[root
- 1], root
);
3675 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3680 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3681 return RET_PF_EMULATE
;
3683 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3684 if (WARN_ON(reserved
))
3687 if (is_mmio_spte(spte
)) {
3688 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3689 unsigned access
= get_mmio_spte_access(spte
);
3691 if (!check_mmio_spte(vcpu
, spte
))
3692 return RET_PF_INVALID
;
3697 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3698 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3699 return RET_PF_EMULATE
;
3703 * If the page table is zapped by other cpus, let CPU fault again on
3706 return RET_PF_RETRY
;
3708 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3710 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3711 u32 error_code
, gfn_t gfn
)
3713 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3716 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3717 !(error_code
& PFERR_WRITE_MASK
))
3721 * guest is writing the page which is write tracked which can
3722 * not be fixed by page fault handler.
3724 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3730 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3732 struct kvm_shadow_walk_iterator iterator
;
3735 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3738 walk_shadow_page_lockless_begin(vcpu
);
3739 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3740 clear_sp_write_flooding_count(iterator
.sptep
);
3741 if (!is_shadow_present_pte(spte
))
3744 walk_shadow_page_lockless_end(vcpu
);
3747 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3748 u32 error_code
, bool prefault
)
3750 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3753 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3755 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3756 return RET_PF_EMULATE
;
3758 r
= mmu_topup_memory_caches(vcpu
);
3762 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3765 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3766 error_code
, gfn
, prefault
);
3769 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3771 struct kvm_arch_async_pf arch
;
3773 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3775 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3776 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3778 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3781 bool kvm_can_do_async_pf(struct kvm_vcpu
*vcpu
)
3783 if (unlikely(!lapic_in_kernel(vcpu
) ||
3784 kvm_event_needs_reinjection(vcpu
) ||
3785 vcpu
->arch
.exception
.pending
))
3788 if (!vcpu
->arch
.apf
.delivery_as_pf_vmexit
&& is_guest_mode(vcpu
))
3791 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3794 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3795 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3797 struct kvm_memory_slot
*slot
;
3800 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3802 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3804 return false; /* *pfn has correct page already */
3806 if (!prefault
&& kvm_can_do_async_pf(vcpu
)) {
3807 trace_kvm_try_async_get_page(gva
, gfn
);
3808 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3809 trace_kvm_async_pf_doublefault(gva
, gfn
);
3810 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3812 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3816 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3820 int kvm_handle_page_fault(struct kvm_vcpu
*vcpu
, u64 error_code
,
3821 u64 fault_address
, char *insn
, int insn_len
)
3825 switch (vcpu
->arch
.apf
.host_apf_reason
) {
3827 trace_kvm_page_fault(fault_address
, error_code
);
3829 if (kvm_event_needs_reinjection(vcpu
))
3830 kvm_mmu_unprotect_page_virt(vcpu
, fault_address
);
3831 r
= kvm_mmu_page_fault(vcpu
, fault_address
, error_code
, insn
,
3834 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
3835 vcpu
->arch
.apf
.host_apf_reason
= 0;
3836 local_irq_disable();
3837 kvm_async_pf_task_wait(fault_address
, 0);
3840 case KVM_PV_REASON_PAGE_READY
:
3841 vcpu
->arch
.apf
.host_apf_reason
= 0;
3842 local_irq_disable();
3843 kvm_async_pf_task_wake(fault_address
);
3849 EXPORT_SYMBOL_GPL(kvm_handle_page_fault
);
3852 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3854 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3856 gfn
&= ~(page_num
- 1);
3858 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3861 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3867 bool force_pt_level
;
3868 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3869 unsigned long mmu_seq
;
3870 int write
= error_code
& PFERR_WRITE_MASK
;
3873 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3875 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3876 return RET_PF_EMULATE
;
3878 r
= mmu_topup_memory_caches(vcpu
);
3882 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3883 PT_DIRECTORY_LEVEL
);
3884 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3885 if (likely(!force_pt_level
)) {
3886 if (level
> PT_DIRECTORY_LEVEL
&&
3887 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3888 level
= PT_DIRECTORY_LEVEL
;
3889 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3892 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3893 return RET_PF_RETRY
;
3895 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3898 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3899 return RET_PF_RETRY
;
3901 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3904 spin_lock(&vcpu
->kvm
->mmu_lock
);
3905 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3907 if (make_mmu_pages_available(vcpu
) < 0)
3909 if (likely(!force_pt_level
))
3910 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3911 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3912 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3917 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3918 kvm_release_pfn_clean(pfn
);
3919 return RET_PF_RETRY
;
3922 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3923 struct kvm_mmu
*context
)
3925 context
->page_fault
= nonpaging_page_fault
;
3926 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3927 context
->sync_page
= nonpaging_sync_page
;
3928 context
->invlpg
= nonpaging_invlpg
;
3929 context
->update_pte
= nonpaging_update_pte
;
3930 context
->root_level
= 0;
3931 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3932 context
->root_hpa
= INVALID_PAGE
;
3933 context
->direct_map
= true;
3934 context
->nx
= false;
3937 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3939 mmu_free_roots(vcpu
);
3942 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3944 return kvm_read_cr3(vcpu
);
3947 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3948 struct x86_exception
*fault
)
3950 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3953 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3954 unsigned access
, int *nr_present
)
3956 if (unlikely(is_mmio_spte(*sptep
))) {
3957 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3958 mmu_spte_clear_no_track(sptep
);
3963 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3970 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3971 unsigned level
, unsigned gpte
)
3974 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3975 * If it is clear, there are no large pages at this level, so clear
3976 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3978 gpte
&= level
- mmu
->last_nonleaf_level
;
3981 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3982 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3983 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3985 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3987 return gpte
& PT_PAGE_SIZE_MASK
;
3990 #define PTTYPE_EPT 18 /* arbitrary */
3991 #define PTTYPE PTTYPE_EPT
3992 #include "paging_tmpl.h"
3996 #include "paging_tmpl.h"
4000 #include "paging_tmpl.h"
4004 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4005 struct rsvd_bits_validate
*rsvd_check
,
4006 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
4009 u64 exb_bit_rsvd
= 0;
4010 u64 gbpages_bit_rsvd
= 0;
4011 u64 nonleaf_bit8_rsvd
= 0;
4013 rsvd_check
->bad_mt_xwr
= 0;
4016 exb_bit_rsvd
= rsvd_bits(63, 63);
4018 gbpages_bit_rsvd
= rsvd_bits(7, 7);
4021 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4022 * leaf entries) on AMD CPUs only.
4025 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
4028 case PT32_ROOT_LEVEL
:
4029 /* no rsvd bits for 2 level 4K page table entries */
4030 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
4031 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
4032 rsvd_check
->rsvd_bits_mask
[1][0] =
4033 rsvd_check
->rsvd_bits_mask
[0][0];
4036 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
4040 if (is_cpuid_PSE36())
4041 /* 36bits PSE 4MB page */
4042 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
4044 /* 32 bits PSE 4MB page */
4045 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
4047 case PT32E_ROOT_LEVEL
:
4048 rsvd_check
->rsvd_bits_mask
[0][2] =
4049 rsvd_bits(maxphyaddr
, 63) |
4050 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4051 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4052 rsvd_bits(maxphyaddr
, 62); /* PDE */
4053 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4054 rsvd_bits(maxphyaddr
, 62); /* PTE */
4055 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4056 rsvd_bits(maxphyaddr
, 62) |
4057 rsvd_bits(13, 20); /* large page */
4058 rsvd_check
->rsvd_bits_mask
[1][0] =
4059 rsvd_check
->rsvd_bits_mask
[0][0];
4061 case PT64_ROOT_5LEVEL
:
4062 rsvd_check
->rsvd_bits_mask
[0][4] = exb_bit_rsvd
|
4063 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4064 rsvd_bits(maxphyaddr
, 51);
4065 rsvd_check
->rsvd_bits_mask
[1][4] =
4066 rsvd_check
->rsvd_bits_mask
[0][4];
4067 case PT64_ROOT_4LEVEL
:
4068 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
4069 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
4070 rsvd_bits(maxphyaddr
, 51);
4071 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
4072 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
4073 rsvd_bits(maxphyaddr
, 51);
4074 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
4075 rsvd_bits(maxphyaddr
, 51);
4076 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
4077 rsvd_bits(maxphyaddr
, 51);
4078 rsvd_check
->rsvd_bits_mask
[1][3] =
4079 rsvd_check
->rsvd_bits_mask
[0][3];
4080 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
4081 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
4083 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
4084 rsvd_bits(maxphyaddr
, 51) |
4085 rsvd_bits(13, 20); /* large page */
4086 rsvd_check
->rsvd_bits_mask
[1][0] =
4087 rsvd_check
->rsvd_bits_mask
[0][0];
4092 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
4093 struct kvm_mmu
*context
)
4095 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
4096 cpuid_maxphyaddr(vcpu
), context
->root_level
,
4098 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4099 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
4103 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
4104 int maxphyaddr
, bool execonly
)
4108 rsvd_check
->rsvd_bits_mask
[0][4] =
4109 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4110 rsvd_check
->rsvd_bits_mask
[0][3] =
4111 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
4112 rsvd_check
->rsvd_bits_mask
[0][2] =
4113 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4114 rsvd_check
->rsvd_bits_mask
[0][1] =
4115 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
4116 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
4119 rsvd_check
->rsvd_bits_mask
[1][4] = rsvd_check
->rsvd_bits_mask
[0][4];
4120 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
4121 rsvd_check
->rsvd_bits_mask
[1][2] =
4122 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
4123 rsvd_check
->rsvd_bits_mask
[1][1] =
4124 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
4125 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
4127 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
4128 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
4129 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
4130 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4131 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4133 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4134 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
4136 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
4139 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
4140 struct kvm_mmu
*context
, bool execonly
)
4142 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
4143 cpuid_maxphyaddr(vcpu
), execonly
);
4147 * the page table on host is the shadow page table for the page
4148 * table in guest or amd nested guest, its mmu features completely
4149 * follow the features in guest.
4152 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
4154 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
4155 struct rsvd_bits_validate
*shadow_zero_check
;
4159 * Passing "true" to the last argument is okay; it adds a check
4160 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4162 shadow_zero_check
= &context
->shadow_zero_check
;
4163 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4164 boot_cpu_data
.x86_phys_bits
,
4165 context
->shadow_root_level
, uses_nx
,
4166 guest_cpuid_has(vcpu
, X86_FEATURE_GBPAGES
),
4167 is_pse(vcpu
), true);
4169 if (!shadow_me_mask
)
4172 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4173 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4174 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4178 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
4180 static inline bool boot_cpu_is_amd(void)
4182 WARN_ON_ONCE(!tdp_enabled
);
4183 return shadow_x_mask
== 0;
4187 * the direct page table on host, use as much mmu features as
4188 * possible, however, kvm currently does not do execution-protection.
4191 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4192 struct kvm_mmu
*context
)
4194 struct rsvd_bits_validate
*shadow_zero_check
;
4197 shadow_zero_check
= &context
->shadow_zero_check
;
4199 if (boot_cpu_is_amd())
4200 __reset_rsvds_bits_mask(vcpu
, shadow_zero_check
,
4201 boot_cpu_data
.x86_phys_bits
,
4202 context
->shadow_root_level
, false,
4203 boot_cpu_has(X86_FEATURE_GBPAGES
),
4206 __reset_rsvds_bits_mask_ept(shadow_zero_check
,
4207 boot_cpu_data
.x86_phys_bits
,
4210 if (!shadow_me_mask
)
4213 for (i
= context
->shadow_root_level
; --i
>= 0;) {
4214 shadow_zero_check
->rsvd_bits_mask
[0][i
] &= ~shadow_me_mask
;
4215 shadow_zero_check
->rsvd_bits_mask
[1][i
] &= ~shadow_me_mask
;
4220 * as the comments in reset_shadow_zero_bits_mask() except it
4221 * is the shadow page table for intel nested guest.
4224 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
4225 struct kvm_mmu
*context
, bool execonly
)
4227 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
4228 boot_cpu_data
.x86_phys_bits
, execonly
);
4231 #define BYTE_MASK(access) \
4232 ((1 & (access) ? 2 : 0) | \
4233 (2 & (access) ? 4 : 0) | \
4234 (3 & (access) ? 8 : 0) | \
4235 (4 & (access) ? 16 : 0) | \
4236 (5 & (access) ? 32 : 0) | \
4237 (6 & (access) ? 64 : 0) | \
4238 (7 & (access) ? 128 : 0))
4241 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
4242 struct kvm_mmu
*mmu
, bool ept
)
4246 const u8 x
= BYTE_MASK(ACC_EXEC_MASK
);
4247 const u8 w
= BYTE_MASK(ACC_WRITE_MASK
);
4248 const u8 u
= BYTE_MASK(ACC_USER_MASK
);
4250 bool cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
) != 0;
4251 bool cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
) != 0;
4252 bool cr0_wp
= is_write_protection(vcpu
);
4254 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
4255 unsigned pfec
= byte
<< 1;
4258 * Each "*f" variable has a 1 bit for each UWX value
4259 * that causes a fault with the given PFEC.
4262 /* Faults from writes to non-writable pages */
4263 u8 wf
= (pfec
& PFERR_WRITE_MASK
) ? ~w
: 0;
4264 /* Faults from user mode accesses to supervisor pages */
4265 u8 uf
= (pfec
& PFERR_USER_MASK
) ? ~u
: 0;
4266 /* Faults from fetches of non-executable pages*/
4267 u8 ff
= (pfec
& PFERR_FETCH_MASK
) ? ~x
: 0;
4268 /* Faults from kernel mode fetches of user pages */
4270 /* Faults from kernel mode accesses of user pages */
4274 /* Faults from kernel mode accesses to user pages */
4275 u8 kf
= (pfec
& PFERR_USER_MASK
) ? 0 : u
;
4277 /* Not really needed: !nx will cause pte.nx to fault */
4281 /* Allow supervisor writes if !cr0.wp */
4283 wf
= (pfec
& PFERR_USER_MASK
) ? wf
: 0;
4285 /* Disallow supervisor fetches of user code if cr4.smep */
4287 smepf
= (pfec
& PFERR_FETCH_MASK
) ? kf
: 0;
4290 * SMAP:kernel-mode data accesses from user-mode
4291 * mappings should fault. A fault is considered
4292 * as a SMAP violation if all of the following
4293 * conditions are ture:
4294 * - X86_CR4_SMAP is set in CR4
4295 * - A user page is accessed
4296 * - The access is not a fetch
4297 * - Page fault in kernel mode
4298 * - if CPL = 3 or X86_EFLAGS_AC is clear
4300 * Here, we cover the first three conditions.
4301 * The fourth is computed dynamically in permission_fault();
4302 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4303 * *not* subject to SMAP restrictions.
4306 smapf
= (pfec
& (PFERR_RSVD_MASK
|PFERR_FETCH_MASK
)) ? 0 : kf
;
4309 mmu
->permissions
[byte
] = ff
| uf
| wf
| smepf
| smapf
;
4314 * PKU is an additional mechanism by which the paging controls access to
4315 * user-mode addresses based on the value in the PKRU register. Protection
4316 * key violations are reported through a bit in the page fault error code.
4317 * Unlike other bits of the error code, the PK bit is not known at the
4318 * call site of e.g. gva_to_gpa; it must be computed directly in
4319 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4320 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4322 * In particular the following conditions come from the error code, the
4323 * page tables and the machine state:
4324 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4325 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4326 * - PK is always zero if U=0 in the page tables
4327 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4329 * The PKRU bitmask caches the result of these four conditions. The error
4330 * code (minus the P bit) and the page table's U bit form an index into the
4331 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4332 * with the two bits of the PKRU register corresponding to the protection key.
4333 * For the first three conditions above the bits will be 00, thus masking
4334 * away both AD and WD. For all reads or if the last condition holds, WD
4335 * only will be masked away.
4337 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
4348 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4349 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
4354 wp
= is_write_protection(vcpu
);
4356 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
4357 unsigned pfec
, pkey_bits
;
4358 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
4361 ff
= pfec
& PFERR_FETCH_MASK
;
4362 uf
= pfec
& PFERR_USER_MASK
;
4363 wf
= pfec
& PFERR_WRITE_MASK
;
4365 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4366 pte_user
= pfec
& PFERR_RSVD_MASK
;
4369 * Only need to check the access which is not an
4370 * instruction fetch and is to a user page.
4372 check_pkey
= (!ff
&& pte_user
);
4374 * write access is controlled by PKRU if it is a
4375 * user access or CR0.WP = 1.
4377 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
4379 /* PKRU.AD stops both read and write access. */
4380 pkey_bits
= !!check_pkey
;
4381 /* PKRU.WD stops write access. */
4382 pkey_bits
|= (!!check_write
) << 1;
4384 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
4388 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4390 unsigned root_level
= mmu
->root_level
;
4392 mmu
->last_nonleaf_level
= root_level
;
4393 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4394 mmu
->last_nonleaf_level
++;
4397 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4398 struct kvm_mmu
*context
,
4401 context
->nx
= is_nx(vcpu
);
4402 context
->root_level
= level
;
4404 reset_rsvds_bits_mask(vcpu
, context
);
4405 update_permission_bitmask(vcpu
, context
, false);
4406 update_pkru_bitmask(vcpu
, context
, false);
4407 update_last_nonleaf_level(vcpu
, context
);
4409 MMU_WARN_ON(!is_pae(vcpu
));
4410 context
->page_fault
= paging64_page_fault
;
4411 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4412 context
->sync_page
= paging64_sync_page
;
4413 context
->invlpg
= paging64_invlpg
;
4414 context
->update_pte
= paging64_update_pte
;
4415 context
->shadow_root_level
= level
;
4416 context
->root_hpa
= INVALID_PAGE
;
4417 context
->direct_map
= false;
4420 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4421 struct kvm_mmu
*context
)
4423 int root_level
= is_la57_mode(vcpu
) ?
4424 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4426 paging64_init_context_common(vcpu
, context
, root_level
);
4429 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4430 struct kvm_mmu
*context
)
4432 context
->nx
= false;
4433 context
->root_level
= PT32_ROOT_LEVEL
;
4435 reset_rsvds_bits_mask(vcpu
, context
);
4436 update_permission_bitmask(vcpu
, context
, false);
4437 update_pkru_bitmask(vcpu
, context
, false);
4438 update_last_nonleaf_level(vcpu
, context
);
4440 context
->page_fault
= paging32_page_fault
;
4441 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4442 context
->sync_page
= paging32_sync_page
;
4443 context
->invlpg
= paging32_invlpg
;
4444 context
->update_pte
= paging32_update_pte
;
4445 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4446 context
->root_hpa
= INVALID_PAGE
;
4447 context
->direct_map
= false;
4450 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4451 struct kvm_mmu
*context
)
4453 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4456 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4458 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4460 context
->base_role
.word
= 0;
4461 context
->base_role
.smm
= is_smm(vcpu
);
4462 context
->base_role
.ad_disabled
= (shadow_accessed_mask
== 0);
4463 context
->page_fault
= tdp_page_fault
;
4464 context
->sync_page
= nonpaging_sync_page
;
4465 context
->invlpg
= nonpaging_invlpg
;
4466 context
->update_pte
= nonpaging_update_pte
;
4467 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level(vcpu
);
4468 context
->root_hpa
= INVALID_PAGE
;
4469 context
->direct_map
= true;
4470 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4471 context
->get_cr3
= get_cr3
;
4472 context
->get_pdptr
= kvm_pdptr_read
;
4473 context
->inject_page_fault
= kvm_inject_page_fault
;
4475 if (!is_paging(vcpu
)) {
4476 context
->nx
= false;
4477 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4478 context
->root_level
= 0;
4479 } else if (is_long_mode(vcpu
)) {
4480 context
->nx
= is_nx(vcpu
);
4481 context
->root_level
= is_la57_mode(vcpu
) ?
4482 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4483 reset_rsvds_bits_mask(vcpu
, context
);
4484 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4485 } else if (is_pae(vcpu
)) {
4486 context
->nx
= is_nx(vcpu
);
4487 context
->root_level
= PT32E_ROOT_LEVEL
;
4488 reset_rsvds_bits_mask(vcpu
, context
);
4489 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4491 context
->nx
= false;
4492 context
->root_level
= PT32_ROOT_LEVEL
;
4493 reset_rsvds_bits_mask(vcpu
, context
);
4494 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4497 update_permission_bitmask(vcpu
, context
, false);
4498 update_pkru_bitmask(vcpu
, context
, false);
4499 update_last_nonleaf_level(vcpu
, context
);
4500 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4503 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4505 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4506 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4507 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4509 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4511 if (!is_paging(vcpu
))
4512 nonpaging_init_context(vcpu
, context
);
4513 else if (is_long_mode(vcpu
))
4514 paging64_init_context(vcpu
, context
);
4515 else if (is_pae(vcpu
))
4516 paging32E_init_context(vcpu
, context
);
4518 paging32_init_context(vcpu
, context
);
4520 context
->base_role
.nxe
= is_nx(vcpu
);
4521 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4522 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4523 context
->base_role
.smep_andnot_wp
4524 = smep
&& !is_write_protection(vcpu
);
4525 context
->base_role
.smap_andnot_wp
4526 = smap
&& !is_write_protection(vcpu
);
4527 context
->base_role
.smm
= is_smm(vcpu
);
4528 reset_shadow_zero_bits_mask(vcpu
, context
);
4530 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4532 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
,
4533 bool accessed_dirty
)
4535 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4537 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4539 context
->shadow_root_level
= PT64_ROOT_4LEVEL
;
4542 context
->ept_ad
= accessed_dirty
;
4543 context
->page_fault
= ept_page_fault
;
4544 context
->gva_to_gpa
= ept_gva_to_gpa
;
4545 context
->sync_page
= ept_sync_page
;
4546 context
->invlpg
= ept_invlpg
;
4547 context
->update_pte
= ept_update_pte
;
4548 context
->root_level
= PT64_ROOT_4LEVEL
;
4549 context
->root_hpa
= INVALID_PAGE
;
4550 context
->direct_map
= false;
4551 context
->base_role
.ad_disabled
= !accessed_dirty
;
4553 update_permission_bitmask(vcpu
, context
, true);
4554 update_pkru_bitmask(vcpu
, context
, true);
4555 update_last_nonleaf_level(vcpu
, context
);
4556 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4557 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4559 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4561 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4563 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4565 kvm_init_shadow_mmu(vcpu
);
4566 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4567 context
->get_cr3
= get_cr3
;
4568 context
->get_pdptr
= kvm_pdptr_read
;
4569 context
->inject_page_fault
= kvm_inject_page_fault
;
4572 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4574 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4576 g_context
->get_cr3
= get_cr3
;
4577 g_context
->get_pdptr
= kvm_pdptr_read
;
4578 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4581 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4582 * L1's nested page tables (e.g. EPT12). The nested translation
4583 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4584 * L2's page tables as the first level of translation and L1's
4585 * nested page tables as the second level of translation. Basically
4586 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4588 if (!is_paging(vcpu
)) {
4589 g_context
->nx
= false;
4590 g_context
->root_level
= 0;
4591 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4592 } else if (is_long_mode(vcpu
)) {
4593 g_context
->nx
= is_nx(vcpu
);
4594 g_context
->root_level
= is_la57_mode(vcpu
) ?
4595 PT64_ROOT_5LEVEL
: PT64_ROOT_4LEVEL
;
4596 reset_rsvds_bits_mask(vcpu
, g_context
);
4597 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4598 } else if (is_pae(vcpu
)) {
4599 g_context
->nx
= is_nx(vcpu
);
4600 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4601 reset_rsvds_bits_mask(vcpu
, g_context
);
4602 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4604 g_context
->nx
= false;
4605 g_context
->root_level
= PT32_ROOT_LEVEL
;
4606 reset_rsvds_bits_mask(vcpu
, g_context
);
4607 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4610 update_permission_bitmask(vcpu
, g_context
, false);
4611 update_pkru_bitmask(vcpu
, g_context
, false);
4612 update_last_nonleaf_level(vcpu
, g_context
);
4615 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4617 if (mmu_is_nested(vcpu
))
4618 init_kvm_nested_mmu(vcpu
);
4619 else if (tdp_enabled
)
4620 init_kvm_tdp_mmu(vcpu
);
4622 init_kvm_softmmu(vcpu
);
4625 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4627 kvm_mmu_unload(vcpu
);
4630 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4632 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4636 r
= mmu_topup_memory_caches(vcpu
);
4639 r
= mmu_alloc_roots(vcpu
);
4640 kvm_mmu_sync_roots(vcpu
);
4643 /* set_cr3() should ensure TLB has been flushed */
4644 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4648 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4650 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4652 mmu_free_roots(vcpu
);
4653 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4655 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4657 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4658 struct kvm_mmu_page
*sp
, u64
*spte
,
4661 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4662 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4666 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4667 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4670 static bool need_remote_flush(u64 old
, u64
new)
4672 if (!is_shadow_present_pte(old
))
4674 if (!is_shadow_present_pte(new))
4676 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4678 old
^= shadow_nx_mask
;
4679 new ^= shadow_nx_mask
;
4680 return (old
& ~new & PT64_PERM_MASK
) != 0;
4683 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4684 const u8
*new, int *bytes
)
4690 * Assume that the pte write on a page table of the same type
4691 * as the current vcpu paging mode since we update the sptes only
4692 * when they have the same mode.
4694 if (is_pae(vcpu
) && *bytes
== 4) {
4695 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4698 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4701 new = (const u8
*)&gentry
;
4706 gentry
= *(const u32
*)new;
4709 gentry
= *(const u64
*)new;
4720 * If we're seeing too many writes to a page, it may no longer be a page table,
4721 * or we may be forking, in which case it is better to unmap the page.
4723 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4726 * Skip write-flooding detected for the sp whose level is 1, because
4727 * it can become unsync, then the guest page is not write-protected.
4729 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4732 atomic_inc(&sp
->write_flooding_count
);
4733 return atomic_read(&sp
->write_flooding_count
) >= 3;
4737 * Misaligned accesses are too much trouble to fix up; also, they usually
4738 * indicate a page is not used as a page table.
4740 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4743 unsigned offset
, pte_size
, misaligned
;
4745 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4746 gpa
, bytes
, sp
->role
.word
);
4748 offset
= offset_in_page(gpa
);
4749 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4752 * Sometimes, the OS only writes the last one bytes to update status
4753 * bits, for example, in linux, andb instruction is used in clear_bit().
4755 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4758 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4759 misaligned
|= bytes
< 4;
4764 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4766 unsigned page_offset
, quadrant
;
4770 page_offset
= offset_in_page(gpa
);
4771 level
= sp
->role
.level
;
4773 if (!sp
->role
.cr4_pae
) {
4774 page_offset
<<= 1; /* 32->64 */
4776 * A 32-bit pde maps 4MB while the shadow pdes map
4777 * only 2MB. So we need to double the offset again
4778 * and zap two pdes instead of one.
4780 if (level
== PT32_ROOT_LEVEL
) {
4781 page_offset
&= ~7; /* kill rounding error */
4785 quadrant
= page_offset
>> PAGE_SHIFT
;
4786 page_offset
&= ~PAGE_MASK
;
4787 if (quadrant
!= sp
->role
.quadrant
)
4791 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4795 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4796 const u8
*new, int bytes
,
4797 struct kvm_page_track_notifier_node
*node
)
4799 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4800 struct kvm_mmu_page
*sp
;
4801 LIST_HEAD(invalid_list
);
4802 u64 entry
, gentry
, *spte
;
4804 bool remote_flush
, local_flush
;
4805 union kvm_mmu_page_role mask
= { };
4810 mask
.smep_andnot_wp
= 1;
4811 mask
.smap_andnot_wp
= 1;
4813 mask
.ad_disabled
= 1;
4816 * If we don't have indirect shadow pages, it means no page is
4817 * write-protected, so we can exit simply.
4819 if (!READ_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4822 remote_flush
= local_flush
= false;
4824 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4826 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4829 * No need to care whether allocation memory is successful
4830 * or not since pte prefetch is skiped if it does not have
4831 * enough objects in the cache.
4833 mmu_topup_memory_caches(vcpu
);
4835 spin_lock(&vcpu
->kvm
->mmu_lock
);
4836 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4837 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4839 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4840 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4841 detect_write_flooding(sp
)) {
4842 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4843 ++vcpu
->kvm
->stat
.mmu_flooded
;
4847 spte
= get_written_sptes(sp
, gpa
, &npte
);
4854 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4856 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4857 & mask
.word
) && rmap_can_add(vcpu
))
4858 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4859 if (need_remote_flush(entry
, *spte
))
4860 remote_flush
= true;
4864 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4865 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4866 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4869 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4874 if (vcpu
->arch
.mmu
.direct_map
)
4877 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4879 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4883 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4885 static int make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4887 LIST_HEAD(invalid_list
);
4889 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4892 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4893 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4896 ++vcpu
->kvm
->stat
.mmu_recycled
;
4898 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4900 if (!kvm_mmu_available_pages(vcpu
->kvm
))
4905 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u64 error_code
,
4906 void *insn
, int insn_len
)
4908 int r
, emulation_type
= EMULTYPE_RETRY
;
4909 enum emulation_result er
;
4910 bool direct
= vcpu
->arch
.mmu
.direct_map
;
4912 /* With shadow page tables, fault_address contains a GVA or nGPA. */
4913 if (vcpu
->arch
.mmu
.direct_map
) {
4914 vcpu
->arch
.gpa_available
= true;
4915 vcpu
->arch
.gpa_val
= cr2
;
4919 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4920 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4921 if (r
== RET_PF_EMULATE
) {
4927 if (r
== RET_PF_INVALID
) {
4928 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, lower_32_bits(error_code
),
4930 WARN_ON(r
== RET_PF_INVALID
);
4933 if (r
== RET_PF_RETRY
)
4939 * Before emulating the instruction, check if the error code
4940 * was due to a RO violation while translating the guest page.
4941 * This can occur when using nested virtualization with nested
4942 * paging in both guests. If true, we simply unprotect the page
4943 * and resume the guest.
4945 if (vcpu
->arch
.mmu
.direct_map
&&
4946 (error_code
& PFERR_NESTED_GUEST_PAGE
) == PFERR_NESTED_GUEST_PAGE
) {
4947 kvm_mmu_unprotect_page(vcpu
->kvm
, gpa_to_gfn(cr2
));
4951 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4954 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4959 case EMULATE_USER_EXIT
:
4960 ++vcpu
->stat
.mmio_exits
;
4968 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4970 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4972 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4973 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4974 ++vcpu
->stat
.invlpg
;
4976 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4978 void kvm_enable_tdp(void)
4982 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4984 void kvm_disable_tdp(void)
4986 tdp_enabled
= false;
4988 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4990 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4992 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4993 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4996 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
5002 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5003 * Therefore we need to allocate shadow page tables in the first
5004 * 4GB of memory, which happens to fit the DMA32 zone.
5006 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
5010 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
5011 for (i
= 0; i
< 4; ++i
)
5012 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
5017 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
5019 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
5020 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
5021 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
5022 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
5024 return alloc_mmu_pages(vcpu
);
5027 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
5029 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
5034 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm
*kvm
,
5035 struct kvm_memory_slot
*slot
,
5036 struct kvm_page_track_notifier_node
*node
)
5038 kvm_mmu_invalidate_zap_all_pages(kvm
);
5041 void kvm_mmu_init_vm(struct kvm
*kvm
)
5043 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5045 node
->track_write
= kvm_mmu_pte_write
;
5046 node
->track_flush_slot
= kvm_mmu_invalidate_zap_pages_in_memslot
;
5047 kvm_page_track_register_notifier(kvm
, node
);
5050 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
5052 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
5054 kvm_page_track_unregister_notifier(kvm
, node
);
5057 /* The return value indicates if tlb flush on all vcpus is needed. */
5058 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
5060 /* The caller should hold mmu-lock before calling this function. */
5062 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5063 slot_level_handler fn
, int start_level
, int end_level
,
5064 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
5066 struct slot_rmap_walk_iterator iterator
;
5069 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
5070 end_gfn
, &iterator
) {
5072 flush
|= fn(kvm
, iterator
.rmap
);
5074 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
5075 if (flush
&& lock_flush_tlb
) {
5076 kvm_flush_remote_tlbs(kvm
);
5079 cond_resched_lock(&kvm
->mmu_lock
);
5083 if (flush
&& lock_flush_tlb
) {
5084 kvm_flush_remote_tlbs(kvm
);
5092 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5093 slot_level_handler fn
, int start_level
, int end_level
,
5094 bool lock_flush_tlb
)
5096 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
5097 end_level
, memslot
->base_gfn
,
5098 memslot
->base_gfn
+ memslot
->npages
- 1,
5103 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5104 slot_level_handler fn
, bool lock_flush_tlb
)
5106 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5107 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5111 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5112 slot_level_handler fn
, bool lock_flush_tlb
)
5114 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
5115 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
5119 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
5120 slot_level_handler fn
, bool lock_flush_tlb
)
5122 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
5123 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
5126 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
5128 struct kvm_memslots
*slots
;
5129 struct kvm_memory_slot
*memslot
;
5132 spin_lock(&kvm
->mmu_lock
);
5133 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5134 slots
= __kvm_memslots(kvm
, i
);
5135 kvm_for_each_memslot(memslot
, slots
) {
5138 start
= max(gfn_start
, memslot
->base_gfn
);
5139 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
5143 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
5144 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
5145 start
, end
- 1, true);
5149 spin_unlock(&kvm
->mmu_lock
);
5152 static bool slot_rmap_write_protect(struct kvm
*kvm
,
5153 struct kvm_rmap_head
*rmap_head
)
5155 return __rmap_write_protect(kvm
, rmap_head
, false);
5158 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
5159 struct kvm_memory_slot
*memslot
)
5163 spin_lock(&kvm
->mmu_lock
);
5164 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
5166 spin_unlock(&kvm
->mmu_lock
);
5169 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5170 * which do tlb flush out of mmu-lock should be serialized by
5171 * kvm->slots_lock otherwise tlb flush would be missed.
5173 lockdep_assert_held(&kvm
->slots_lock
);
5176 * We can flush all the TLBs out of the mmu lock without TLB
5177 * corruption since we just change the spte from writable to
5178 * readonly so that we only need to care the case of changing
5179 * spte from present to present (changing the spte from present
5180 * to nonpresent will flush all the TLBs immediately), in other
5181 * words, the only case we care is mmu_spte_update() where we
5182 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5183 * instead of PT_WRITABLE_MASK, that means it does not depend
5184 * on PT_WRITABLE_MASK anymore.
5187 kvm_flush_remote_tlbs(kvm
);
5190 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
5191 struct kvm_rmap_head
*rmap_head
)
5194 struct rmap_iterator iter
;
5195 int need_tlb_flush
= 0;
5197 struct kvm_mmu_page
*sp
;
5200 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
5201 sp
= page_header(__pa(sptep
));
5202 pfn
= spte_to_pfn(*sptep
);
5205 * We cannot do huge page mapping for indirect shadow pages,
5206 * which are found on the last rmap (level = 1) when not using
5207 * tdp; such shadow pages are synced with the page table in
5208 * the guest, and the guest page table is using 4K page size
5209 * mapping if the indirect sp has level = 1.
5211 if (sp
->role
.direct
&&
5212 !kvm_is_reserved_pfn(pfn
) &&
5213 PageTransCompoundMap(pfn_to_page(pfn
))) {
5214 drop_spte(kvm
, sptep
);
5220 return need_tlb_flush
;
5223 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
5224 const struct kvm_memory_slot
*memslot
)
5226 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5227 spin_lock(&kvm
->mmu_lock
);
5228 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
5229 kvm_mmu_zap_collapsible_spte
, true);
5230 spin_unlock(&kvm
->mmu_lock
);
5233 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
5234 struct kvm_memory_slot
*memslot
)
5238 spin_lock(&kvm
->mmu_lock
);
5239 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
5240 spin_unlock(&kvm
->mmu_lock
);
5242 lockdep_assert_held(&kvm
->slots_lock
);
5245 * It's also safe to flush TLBs out of mmu lock here as currently this
5246 * function is only used for dirty logging, in which case flushing TLB
5247 * out of mmu lock also guarantees no dirty pages will be lost in
5251 kvm_flush_remote_tlbs(kvm
);
5253 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
5255 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
5256 struct kvm_memory_slot
*memslot
)
5260 spin_lock(&kvm
->mmu_lock
);
5261 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
5263 spin_unlock(&kvm
->mmu_lock
);
5265 /* see kvm_mmu_slot_remove_write_access */
5266 lockdep_assert_held(&kvm
->slots_lock
);
5269 kvm_flush_remote_tlbs(kvm
);
5271 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
5273 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
5274 struct kvm_memory_slot
*memslot
)
5278 spin_lock(&kvm
->mmu_lock
);
5279 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
5280 spin_unlock(&kvm
->mmu_lock
);
5282 lockdep_assert_held(&kvm
->slots_lock
);
5284 /* see kvm_mmu_slot_leaf_clear_dirty */
5286 kvm_flush_remote_tlbs(kvm
);
5288 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
5290 #define BATCH_ZAP_PAGES 10
5291 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
5293 struct kvm_mmu_page
*sp
, *node
;
5297 list_for_each_entry_safe_reverse(sp
, node
,
5298 &kvm
->arch
.active_mmu_pages
, link
) {
5302 * No obsolete page exists before new created page since
5303 * active_mmu_pages is the FIFO list.
5305 if (!is_obsolete_sp(kvm
, sp
))
5309 * Since we are reversely walking the list and the invalid
5310 * list will be moved to the head, skip the invalid page
5311 * can help us to avoid the infinity list walking.
5313 if (sp
->role
.invalid
)
5317 * Need not flush tlb since we only zap the sp with invalid
5318 * generation number.
5320 if (batch
>= BATCH_ZAP_PAGES
&&
5321 cond_resched_lock(&kvm
->mmu_lock
)) {
5326 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
5327 &kvm
->arch
.zapped_obsolete_pages
);
5335 * Should flush tlb before free page tables since lockless-walking
5336 * may use the pages.
5338 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
5342 * Fast invalidate all shadow pages and use lock-break technique
5343 * to zap obsolete pages.
5345 * It's required when memslot is being deleted or VM is being
5346 * destroyed, in these cases, we should ensure that KVM MMU does
5347 * not use any resource of the being-deleted slot or all slots
5348 * after calling the function.
5350 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
5352 spin_lock(&kvm
->mmu_lock
);
5353 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
5354 kvm
->arch
.mmu_valid_gen
++;
5357 * Notify all vcpus to reload its shadow page table
5358 * and flush TLB. Then all vcpus will switch to new
5359 * shadow page table with the new mmu_valid_gen.
5361 * Note: we should do this under the protection of
5362 * mmu-lock, otherwise, vcpu would purge shadow page
5363 * but miss tlb flush.
5365 kvm_reload_remote_mmus(kvm
);
5367 kvm_zap_obsolete_pages(kvm
);
5368 spin_unlock(&kvm
->mmu_lock
);
5371 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
5373 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
5376 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
5379 * The very rare case: if the generation-number is round,
5380 * zap all shadow pages.
5382 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
5383 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5384 kvm_mmu_invalidate_zap_all_pages(kvm
);
5388 static unsigned long
5389 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
5392 int nr_to_scan
= sc
->nr_to_scan
;
5393 unsigned long freed
= 0;
5395 spin_lock(&kvm_lock
);
5397 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
5399 LIST_HEAD(invalid_list
);
5402 * Never scan more than sc->nr_to_scan VM instances.
5403 * Will not hit this condition practically since we do not try
5404 * to shrink more than one VM and it is very unlikely to see
5405 * !n_used_mmu_pages so many times.
5410 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5411 * here. We may skip a VM instance errorneosly, but we do not
5412 * want to shrink a VM that only started to populate its MMU
5415 if (!kvm
->arch
.n_used_mmu_pages
&&
5416 !kvm_has_zapped_obsolete_pages(kvm
))
5419 idx
= srcu_read_lock(&kvm
->srcu
);
5420 spin_lock(&kvm
->mmu_lock
);
5422 if (kvm_has_zapped_obsolete_pages(kvm
)) {
5423 kvm_mmu_commit_zap_page(kvm
,
5424 &kvm
->arch
.zapped_obsolete_pages
);
5428 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
5430 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5433 spin_unlock(&kvm
->mmu_lock
);
5434 srcu_read_unlock(&kvm
->srcu
, idx
);
5437 * unfair on small ones
5438 * per-vm shrinkers cry out
5439 * sadness comes quickly
5441 list_move_tail(&kvm
->vm_list
, &vm_list
);
5445 spin_unlock(&kvm_lock
);
5449 static unsigned long
5450 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5452 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5455 static struct shrinker mmu_shrinker
= {
5456 .count_objects
= mmu_shrink_count
,
5457 .scan_objects
= mmu_shrink_scan
,
5458 .seeks
= DEFAULT_SEEKS
* 10,
5461 static void mmu_destroy_caches(void)
5463 kmem_cache_destroy(pte_list_desc_cache
);
5464 kmem_cache_destroy(mmu_page_header_cache
);
5467 int kvm_mmu_module_init(void)
5471 kvm_mmu_clear_all_pte_masks();
5473 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5474 sizeof(struct pte_list_desc
),
5475 0, SLAB_ACCOUNT
, NULL
);
5476 if (!pte_list_desc_cache
)
5479 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5480 sizeof(struct kvm_mmu_page
),
5481 0, SLAB_ACCOUNT
, NULL
);
5482 if (!mmu_page_header_cache
)
5485 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5488 ret
= register_shrinker(&mmu_shrinker
);
5495 mmu_destroy_caches();
5500 * Caculate mmu pages needed for kvm.
5502 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5504 unsigned int nr_mmu_pages
;
5505 unsigned int nr_pages
= 0;
5506 struct kvm_memslots
*slots
;
5507 struct kvm_memory_slot
*memslot
;
5510 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5511 slots
= __kvm_memslots(kvm
, i
);
5513 kvm_for_each_memslot(memslot
, slots
)
5514 nr_pages
+= memslot
->npages
;
5517 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5518 nr_mmu_pages
= max(nr_mmu_pages
,
5519 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5521 return nr_mmu_pages
;
5524 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5526 kvm_mmu_unload(vcpu
);
5527 free_mmu_pages(vcpu
);
5528 mmu_free_memory_caches(vcpu
);
5531 void kvm_mmu_module_exit(void)
5533 mmu_destroy_caches();
5534 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5535 unregister_shrinker(&mmu_shrinker
);
5536 mmu_audit_disable();