2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
62 char *audit_point_name
[] = {
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
87 module_param(dbg
, bool, 0644);
90 static int oos_shadow
= 1;
91 module_param(oos_shadow
, bool, 0644);
94 #define ASSERT(x) do { } while (0)
98 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
99 __FILE__, __LINE__, #x); \
103 #define PTE_PREFETCH_NUM 8
105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
108 #define PT64_LEVEL_BITS 9
110 #define PT64_LEVEL_SHIFT(level) \
111 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
113 #define PT64_INDEX(address, level)\
114 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
117 #define PT32_LEVEL_BITS 10
119 #define PT32_LEVEL_SHIFT(level) \
120 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT64_LEVEL_BITS))) - 1))
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145 * PT32_LEVEL_BITS))) - 1))
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
150 #define PTE_LIST_EXT 4
152 #define ACC_EXEC_MASK 1
153 #define ACC_WRITE_MASK PT_WRITABLE_MASK
154 #define ACC_USER_MASK PT_USER_MASK
155 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
157 #include <trace/events/kvm.h>
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
166 struct pte_list_desc
{
167 u64
*sptes
[PTE_LIST_EXT
];
168 struct pte_list_desc
*more
;
171 struct kvm_shadow_walk_iterator
{
179 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
180 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
181 shadow_walk_okay(&(_walker)); \
182 shadow_walk_next(&(_walker)))
184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
185 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
186 shadow_walk_okay(&(_walker)) && \
187 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
188 __shadow_walk_next(&(_walker), spte))
190 static struct kmem_cache
*pte_list_desc_cache
;
191 static struct kmem_cache
*mmu_page_header_cache
;
192 static struct percpu_counter kvm_total_used_mmu_pages
;
194 static u64 __read_mostly shadow_nx_mask
;
195 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask
;
197 static u64 __read_mostly shadow_accessed_mask
;
198 static u64 __read_mostly shadow_dirty_mask
;
199 static u64 __read_mostly shadow_mmio_mask
;
201 static void mmu_spte_set(u64
*sptep
, u64 spte
);
203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
205 shadow_mmio_mask
= mmio_mask
;
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
209 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
211 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
213 trace_mark_mmio_spte(sptep
, gfn
, access
);
214 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
217 static bool is_mmio_spte(u64 spte
)
219 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
222 static gfn_t
get_mmio_spte_gfn(u64 spte
)
224 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
227 static unsigned get_mmio_spte_access(u64 spte
)
229 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
232 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
234 if (unlikely(is_noslot_pfn(pfn
))) {
235 mark_mmio_spte(sptep
, gfn
, access
);
242 static inline u64
rsvd_bits(int s
, int e
)
244 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
247 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
248 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
250 shadow_user_mask
= user_mask
;
251 shadow_accessed_mask
= accessed_mask
;
252 shadow_dirty_mask
= dirty_mask
;
253 shadow_nx_mask
= nx_mask
;
254 shadow_x_mask
= x_mask
;
256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
258 static int is_cpuid_PSE36(void)
263 static int is_nx(struct kvm_vcpu
*vcpu
)
265 return vcpu
->arch
.efer
& EFER_NX
;
268 static int is_shadow_present_pte(u64 pte
)
270 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
273 static int is_large_pte(u64 pte
)
275 return pte
& PT_PAGE_SIZE_MASK
;
278 static int is_dirty_gpte(unsigned long pte
)
280 return pte
& PT_DIRTY_MASK
;
283 static int is_rmap_spte(u64 pte
)
285 return is_shadow_present_pte(pte
);
288 static int is_last_spte(u64 pte
, int level
)
290 if (level
== PT_PAGE_TABLE_LEVEL
)
292 if (is_large_pte(pte
))
297 static pfn_t
spte_to_pfn(u64 pte
)
299 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
302 static gfn_t
pse36_gfn_delta(u32 gpte
)
304 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
306 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
310 static void __set_spte(u64
*sptep
, u64 spte
)
315 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
320 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
322 return xchg(sptep
, spte
);
325 static u64
__get_spte_lockless(u64
*sptep
)
327 return ACCESS_ONCE(*sptep
);
330 static bool __check_direct_spte_mmio_pf(u64 spte
)
332 /* It is valid if the spte is zapped. */
344 static void count_spte_clear(u64
*sptep
, u64 spte
)
346 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
348 if (is_shadow_present_pte(spte
))
351 /* Ensure the spte is completely set before we increase the count */
353 sp
->clear_spte_count
++;
356 static void __set_spte(u64
*sptep
, u64 spte
)
358 union split_spte
*ssptep
, sspte
;
360 ssptep
= (union split_spte
*)sptep
;
361 sspte
= (union split_spte
)spte
;
363 ssptep
->spte_high
= sspte
.spte_high
;
366 * If we map the spte from nonpresent to present, We should store
367 * the high bits firstly, then set present bit, so cpu can not
368 * fetch this spte while we are setting the spte.
372 ssptep
->spte_low
= sspte
.spte_low
;
375 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
377 union split_spte
*ssptep
, sspte
;
379 ssptep
= (union split_spte
*)sptep
;
380 sspte
= (union split_spte
)spte
;
382 ssptep
->spte_low
= sspte
.spte_low
;
385 * If we map the spte from present to nonpresent, we should clear
386 * present bit firstly to avoid vcpu fetch the old high bits.
390 ssptep
->spte_high
= sspte
.spte_high
;
391 count_spte_clear(sptep
, spte
);
394 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
396 union split_spte
*ssptep
, sspte
, orig
;
398 ssptep
= (union split_spte
*)sptep
;
399 sspte
= (union split_spte
)spte
;
401 /* xchg acts as a barrier before the setting of the high bits */
402 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
403 orig
.spte_high
= ssptep
->spte_high
;
404 ssptep
->spte_high
= sspte
.spte_high
;
405 count_spte_clear(sptep
, spte
);
411 * The idea using the light way get the spte on x86_32 guest is from
412 * gup_get_pte(arch/x86/mm/gup.c).
413 * The difference is we can not catch the spte tlb flush if we leave
414 * guest mode, so we emulate it by increase clear_spte_count when spte
417 static u64
__get_spte_lockless(u64
*sptep
)
419 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
420 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
424 count
= sp
->clear_spte_count
;
427 spte
.spte_low
= orig
->spte_low
;
430 spte
.spte_high
= orig
->spte_high
;
433 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
434 count
!= sp
->clear_spte_count
))
440 static bool __check_direct_spte_mmio_pf(u64 spte
)
442 union split_spte sspte
= (union split_spte
)spte
;
443 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
445 /* It is valid if the spte is zapped. */
449 /* It is valid if the spte is being zapped. */
450 if (sspte
.spte_low
== 0ull &&
451 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
458 static bool spte_has_volatile_bits(u64 spte
)
460 if (!shadow_accessed_mask
)
463 if (!is_shadow_present_pte(spte
))
466 if ((spte
& shadow_accessed_mask
) &&
467 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
473 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
475 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
478 /* Rules for using mmu_spte_set:
479 * Set the sptep from nonpresent to present.
480 * Note: the sptep being assigned *must* be either not present
481 * or in a state where the hardware will not attempt to update
484 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
486 WARN_ON(is_shadow_present_pte(*sptep
));
487 __set_spte(sptep
, new_spte
);
490 /* Rules for using mmu_spte_update:
491 * Update the state bits, it means the mapped pfn is not changged.
493 static void mmu_spte_update(u64
*sptep
, u64 new_spte
)
495 u64 mask
, old_spte
= *sptep
;
497 WARN_ON(!is_rmap_spte(new_spte
));
499 if (!is_shadow_present_pte(old_spte
))
500 return mmu_spte_set(sptep
, new_spte
);
502 new_spte
|= old_spte
& shadow_dirty_mask
;
504 mask
= shadow_accessed_mask
;
505 if (is_writable_pte(old_spte
))
506 mask
|= shadow_dirty_mask
;
508 if (!spte_has_volatile_bits(old_spte
) || (new_spte
& mask
) == mask
)
509 __update_clear_spte_fast(sptep
, new_spte
);
511 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
513 if (!shadow_accessed_mask
)
516 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
517 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
518 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
519 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
523 * Rules for using mmu_spte_clear_track_bits:
524 * It sets the sptep from present to nonpresent, and track the
525 * state bits, it is used to clear the last level sptep.
527 static int mmu_spte_clear_track_bits(u64
*sptep
)
530 u64 old_spte
= *sptep
;
532 if (!spte_has_volatile_bits(old_spte
))
533 __update_clear_spte_fast(sptep
, 0ull);
535 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
537 if (!is_rmap_spte(old_spte
))
540 pfn
= spte_to_pfn(old_spte
);
541 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
542 kvm_set_pfn_accessed(pfn
);
543 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
544 kvm_set_pfn_dirty(pfn
);
549 * Rules for using mmu_spte_clear_no_track:
550 * Directly clear spte without caring the state bits of sptep,
551 * it is used to set the upper level spte.
553 static void mmu_spte_clear_no_track(u64
*sptep
)
555 __update_clear_spte_fast(sptep
, 0ull);
558 static u64
mmu_spte_get_lockless(u64
*sptep
)
560 return __get_spte_lockless(sptep
);
563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
566 atomic_inc(&vcpu
->kvm
->arch
.reader_counter
);
568 /* Increase the counter before walking shadow page table */
569 smp_mb__after_atomic_inc();
572 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
574 /* Decrease the counter after walking shadow page table finished */
575 smp_mb__before_atomic_dec();
576 atomic_dec(&vcpu
->kvm
->arch
.reader_counter
);
580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
581 struct kmem_cache
*base_cache
, int min
)
585 if (cache
->nobjs
>= min
)
587 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
588 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
591 cache
->objects
[cache
->nobjs
++] = obj
;
596 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
601 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
602 struct kmem_cache
*cache
)
605 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
608 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
613 if (cache
->nobjs
>= min
)
615 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
616 page
= (void *)__get_free_page(GFP_KERNEL
);
619 cache
->objects
[cache
->nobjs
++] = page
;
624 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
627 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
630 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
634 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
635 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
638 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
641 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
642 mmu_page_header_cache
, 4);
647 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
649 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
650 pte_list_desc_cache
);
651 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
652 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
653 mmu_page_header_cache
);
656 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
,
662 p
= mc
->objects
[--mc
->nobjs
];
666 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
668 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
,
669 sizeof(struct pte_list_desc
));
672 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
674 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
677 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
679 if (!sp
->role
.direct
)
680 return sp
->gfns
[index
];
682 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
685 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
688 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
690 sp
->gfns
[index
] = gfn
;
694 * Return the pointer to the large page information for a given gfn,
695 * handling slots that are not large page aligned.
697 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
698 struct kvm_memory_slot
*slot
,
703 idx
= (gfn
>> KVM_HPAGE_GFN_SHIFT(level
)) -
704 (slot
->base_gfn
>> KVM_HPAGE_GFN_SHIFT(level
));
705 return &slot
->lpage_info
[level
- 2][idx
];
708 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
710 struct kvm_memory_slot
*slot
;
711 struct kvm_lpage_info
*linfo
;
714 slot
= gfn_to_memslot(kvm
, gfn
);
715 for (i
= PT_DIRECTORY_LEVEL
;
716 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
717 linfo
= lpage_info_slot(gfn
, slot
, i
);
718 linfo
->write_count
+= 1;
720 kvm
->arch
.indirect_shadow_pages
++;
723 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
725 struct kvm_memory_slot
*slot
;
726 struct kvm_lpage_info
*linfo
;
729 slot
= gfn_to_memslot(kvm
, gfn
);
730 for (i
= PT_DIRECTORY_LEVEL
;
731 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
732 linfo
= lpage_info_slot(gfn
, slot
, i
);
733 linfo
->write_count
-= 1;
734 WARN_ON(linfo
->write_count
< 0);
736 kvm
->arch
.indirect_shadow_pages
--;
739 static int has_wrprotected_page(struct kvm
*kvm
,
743 struct kvm_memory_slot
*slot
;
744 struct kvm_lpage_info
*linfo
;
746 slot
= gfn_to_memslot(kvm
, gfn
);
748 linfo
= lpage_info_slot(gfn
, slot
, level
);
749 return linfo
->write_count
;
755 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
757 unsigned long page_size
;
760 page_size
= kvm_host_page_size(kvm
, gfn
);
762 for (i
= PT_PAGE_TABLE_LEVEL
;
763 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
764 if (page_size
>= KVM_HPAGE_SIZE(i
))
773 static struct kvm_memory_slot
*
774 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
777 struct kvm_memory_slot
*slot
;
779 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
780 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
781 (no_dirty_log
&& slot
->dirty_bitmap
))
787 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
789 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
792 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
794 int host_level
, level
, max_level
;
796 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
798 if (host_level
== PT_PAGE_TABLE_LEVEL
)
801 max_level
= kvm_x86_ops
->get_lpage_level() < host_level
?
802 kvm_x86_ops
->get_lpage_level() : host_level
;
804 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
805 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
812 * Pte mapping structures:
814 * If pte_list bit zero is zero, then pte_list point to the spte.
816 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
817 * pte_list_desc containing more mappings.
819 * Returns the number of pte entries before the spte was added or zero if
820 * the spte was not added.
823 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
824 unsigned long *pte_list
)
826 struct pte_list_desc
*desc
;
830 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
831 *pte_list
= (unsigned long)spte
;
832 } else if (!(*pte_list
& 1)) {
833 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
834 desc
= mmu_alloc_pte_list_desc(vcpu
);
835 desc
->sptes
[0] = (u64
*)*pte_list
;
836 desc
->sptes
[1] = spte
;
837 *pte_list
= (unsigned long)desc
| 1;
840 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
841 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
842 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
844 count
+= PTE_LIST_EXT
;
846 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
847 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
850 for (i
= 0; desc
->sptes
[i
]; ++i
)
852 desc
->sptes
[i
] = spte
;
857 static u64
*pte_list_next(unsigned long *pte_list
, u64
*spte
)
859 struct pte_list_desc
*desc
;
865 else if (!(*pte_list
& 1)) {
867 return (u64
*)*pte_list
;
870 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
873 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
874 if (prev_spte
== spte
)
875 return desc
->sptes
[i
];
876 prev_spte
= desc
->sptes
[i
];
884 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
885 int i
, struct pte_list_desc
*prev_desc
)
889 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
891 desc
->sptes
[i
] = desc
->sptes
[j
];
892 desc
->sptes
[j
] = NULL
;
895 if (!prev_desc
&& !desc
->more
)
896 *pte_list
= (unsigned long)desc
->sptes
[0];
899 prev_desc
->more
= desc
->more
;
901 *pte_list
= (unsigned long)desc
->more
| 1;
902 mmu_free_pte_list_desc(desc
);
905 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
907 struct pte_list_desc
*desc
;
908 struct pte_list_desc
*prev_desc
;
912 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
914 } else if (!(*pte_list
& 1)) {
915 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
916 if ((u64
*)*pte_list
!= spte
) {
917 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
922 rmap_printk("pte_list_remove: %p many->many\n", spte
);
923 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
926 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
927 if (desc
->sptes
[i
] == spte
) {
928 pte_list_desc_remove_entry(pte_list
,
936 pr_err("pte_list_remove: %p many->many\n", spte
);
941 typedef void (*pte_list_walk_fn
) (u64
*spte
);
942 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
944 struct pte_list_desc
*desc
;
950 if (!(*pte_list
& 1))
951 return fn((u64
*)*pte_list
);
953 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
955 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
962 * Take gfn and return the reverse mapping to it.
964 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
966 struct kvm_memory_slot
*slot
;
967 struct kvm_lpage_info
*linfo
;
969 slot
= gfn_to_memslot(kvm
, gfn
);
970 if (likely(level
== PT_PAGE_TABLE_LEVEL
))
971 return &slot
->rmap
[gfn
- slot
->base_gfn
];
973 linfo
= lpage_info_slot(gfn
, slot
, level
);
975 return &linfo
->rmap_pde
;
978 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
980 struct kvm_mmu_memory_cache
*cache
;
982 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
983 return mmu_memory_cache_free_objects(cache
);
986 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
988 struct kvm_mmu_page
*sp
;
989 unsigned long *rmapp
;
991 sp
= page_header(__pa(spte
));
992 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
993 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
994 return pte_list_add(vcpu
, spte
, rmapp
);
997 static u64
*rmap_next(struct kvm
*kvm
, unsigned long *rmapp
, u64
*spte
)
999 return pte_list_next(rmapp
, spte
);
1002 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1004 struct kvm_mmu_page
*sp
;
1006 unsigned long *rmapp
;
1008 sp
= page_header(__pa(spte
));
1009 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1010 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
1011 pte_list_remove(spte
, rmapp
);
1014 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1016 if (mmu_spte_clear_track_bits(sptep
))
1017 rmap_remove(kvm
, sptep
);
1020 static int rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1022 unsigned long *rmapp
;
1024 int i
, write_protected
= 0;
1026 rmapp
= gfn_to_rmap(kvm
, gfn
, PT_PAGE_TABLE_LEVEL
);
1028 spte
= rmap_next(kvm
, rmapp
, NULL
);
1031 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1032 rmap_printk("rmap_write_protect: spte %p %llx\n", spte
, *spte
);
1033 if (is_writable_pte(*spte
)) {
1034 mmu_spte_update(spte
, *spte
& ~PT_WRITABLE_MASK
);
1035 write_protected
= 1;
1037 spte
= rmap_next(kvm
, rmapp
, spte
);
1040 /* check for huge page mappings */
1041 for (i
= PT_DIRECTORY_LEVEL
;
1042 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1043 rmapp
= gfn_to_rmap(kvm
, gfn
, i
);
1044 spte
= rmap_next(kvm
, rmapp
, NULL
);
1047 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1048 BUG_ON((*spte
& (PT_PAGE_SIZE_MASK
|PT_PRESENT_MASK
)) != (PT_PAGE_SIZE_MASK
|PT_PRESENT_MASK
));
1049 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte
, *spte
, gfn
);
1050 if (is_writable_pte(*spte
)) {
1051 drop_spte(kvm
, spte
);
1054 write_protected
= 1;
1056 spte
= rmap_next(kvm
, rmapp
, spte
);
1060 return write_protected
;
1063 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1067 int need_tlb_flush
= 0;
1069 while ((spte
= rmap_next(kvm
, rmapp
, NULL
))) {
1070 BUG_ON(!(*spte
& PT_PRESENT_MASK
));
1071 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte
, *spte
);
1072 drop_spte(kvm
, spte
);
1075 return need_tlb_flush
;
1078 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1082 u64
*spte
, new_spte
;
1083 pte_t
*ptep
= (pte_t
*)data
;
1086 WARN_ON(pte_huge(*ptep
));
1087 new_pfn
= pte_pfn(*ptep
);
1088 spte
= rmap_next(kvm
, rmapp
, NULL
);
1090 BUG_ON(!is_shadow_present_pte(*spte
));
1091 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte
, *spte
);
1093 if (pte_write(*ptep
)) {
1094 drop_spte(kvm
, spte
);
1095 spte
= rmap_next(kvm
, rmapp
, NULL
);
1097 new_spte
= *spte
&~ (PT64_BASE_ADDR_MASK
);
1098 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1100 new_spte
&= ~PT_WRITABLE_MASK
;
1101 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1102 new_spte
&= ~shadow_accessed_mask
;
1103 mmu_spte_clear_track_bits(spte
);
1104 mmu_spte_set(spte
, new_spte
);
1105 spte
= rmap_next(kvm
, rmapp
, spte
);
1109 kvm_flush_remote_tlbs(kvm
);
1114 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1116 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1117 unsigned long data
))
1122 struct kvm_memslots
*slots
;
1124 slots
= kvm_memslots(kvm
);
1126 for (i
= 0; i
< slots
->nmemslots
; i
++) {
1127 struct kvm_memory_slot
*memslot
= &slots
->memslots
[i
];
1128 unsigned long start
= memslot
->userspace_addr
;
1131 end
= start
+ (memslot
->npages
<< PAGE_SHIFT
);
1132 if (hva
>= start
&& hva
< end
) {
1133 gfn_t gfn_offset
= (hva
- start
) >> PAGE_SHIFT
;
1134 gfn_t gfn
= memslot
->base_gfn
+ gfn_offset
;
1136 ret
= handler(kvm
, &memslot
->rmap
[gfn_offset
], data
);
1138 for (j
= 0; j
< KVM_NR_PAGE_SIZES
- 1; ++j
) {
1139 struct kvm_lpage_info
*linfo
;
1141 linfo
= lpage_info_slot(gfn
, memslot
,
1142 PT_DIRECTORY_LEVEL
+ j
);
1143 ret
|= handler(kvm
, &linfo
->rmap_pde
, data
);
1145 trace_kvm_age_page(hva
, memslot
, ret
);
1153 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1155 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1158 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1160 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1163 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1170 * Emulate the accessed bit for EPT, by checking if this page has
1171 * an EPT mapping, and clearing it if it does. On the next access,
1172 * a new EPT mapping will be established.
1173 * This has some overhead, but not as much as the cost of swapping
1174 * out actively used pages or breaking up actively used hugepages.
1176 if (!shadow_accessed_mask
)
1177 return kvm_unmap_rmapp(kvm
, rmapp
, data
);
1179 spte
= rmap_next(kvm
, rmapp
, NULL
);
1183 BUG_ON(!(_spte
& PT_PRESENT_MASK
));
1184 _young
= _spte
& PT_ACCESSED_MASK
;
1187 clear_bit(PT_ACCESSED_SHIFT
, (unsigned long *)spte
);
1189 spte
= rmap_next(kvm
, rmapp
, spte
);
1194 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1201 * If there's no access bit in the secondary pte set by the
1202 * hardware it's up to gup-fast/gup to set the access bit in
1203 * the primary pte or in the page structure.
1205 if (!shadow_accessed_mask
)
1208 spte
= rmap_next(kvm
, rmapp
, NULL
);
1211 BUG_ON(!(_spte
& PT_PRESENT_MASK
));
1212 young
= _spte
& PT_ACCESSED_MASK
;
1217 spte
= rmap_next(kvm
, rmapp
, spte
);
1223 #define RMAP_RECYCLE_THRESHOLD 1000
1225 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1227 unsigned long *rmapp
;
1228 struct kvm_mmu_page
*sp
;
1230 sp
= page_header(__pa(spte
));
1232 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1234 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, 0);
1235 kvm_flush_remote_tlbs(vcpu
->kvm
);
1238 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1240 return kvm_handle_hva(kvm
, hva
, 0, kvm_age_rmapp
);
1243 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1245 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1249 static int is_empty_shadow_page(u64
*spt
)
1254 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1255 if (is_shadow_present_pte(*pos
)) {
1256 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1265 * This value is the sum of all of the kvm instances's
1266 * kvm->arch.n_used_mmu_pages values. We need a global,
1267 * aggregate version in order to make the slab shrinker
1270 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1272 kvm
->arch
.n_used_mmu_pages
+= nr
;
1273 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1277 * Remove the sp from shadow page cache, after call it,
1278 * we can not find this sp from the cache, and the shadow
1279 * page table is still valid.
1280 * It should be under the protection of mmu lock.
1282 static void kvm_mmu_isolate_page(struct kvm_mmu_page
*sp
)
1284 ASSERT(is_empty_shadow_page(sp
->spt
));
1285 hlist_del(&sp
->hash_link
);
1286 if (!sp
->role
.direct
)
1287 free_page((unsigned long)sp
->gfns
);
1291 * Free the shadow page table and the sp, we can do it
1292 * out of the protection of mmu lock.
1294 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1296 list_del(&sp
->link
);
1297 free_page((unsigned long)sp
->spt
);
1298 kmem_cache_free(mmu_page_header_cache
, sp
);
1301 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1303 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1306 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1307 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1312 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1315 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1318 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1321 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1324 mmu_page_remove_parent_pte(sp
, parent_pte
);
1325 mmu_spte_clear_no_track(parent_pte
);
1328 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1329 u64
*parent_pte
, int direct
)
1331 struct kvm_mmu_page
*sp
;
1332 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
,
1334 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
, PAGE_SIZE
);
1336 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
,
1338 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1339 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1340 bitmap_zero(sp
->slot_bitmap
, KVM_MEMORY_SLOTS
+ KVM_PRIVATE_MEM_SLOTS
);
1341 sp
->parent_ptes
= 0;
1342 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1343 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1347 static void mark_unsync(u64
*spte
);
1348 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1350 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1353 static void mark_unsync(u64
*spte
)
1355 struct kvm_mmu_page
*sp
;
1358 sp
= page_header(__pa(spte
));
1359 index
= spte
- sp
->spt
;
1360 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1362 if (sp
->unsync_children
++)
1364 kvm_mmu_mark_parents_unsync(sp
);
1367 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1368 struct kvm_mmu_page
*sp
)
1373 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1377 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1378 struct kvm_mmu_page
*sp
, u64
*spte
,
1384 #define KVM_PAGE_ARRAY_NR 16
1386 struct kvm_mmu_pages
{
1387 struct mmu_page_and_offset
{
1388 struct kvm_mmu_page
*sp
;
1390 } page
[KVM_PAGE_ARRAY_NR
];
1394 #define for_each_unsync_children(bitmap, idx) \
1395 for (idx = find_first_bit(bitmap, 512); \
1397 idx = find_next_bit(bitmap, 512, idx+1))
1399 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1405 for (i
=0; i
< pvec
->nr
; i
++)
1406 if (pvec
->page
[i
].sp
== sp
)
1409 pvec
->page
[pvec
->nr
].sp
= sp
;
1410 pvec
->page
[pvec
->nr
].idx
= idx
;
1412 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1415 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1416 struct kvm_mmu_pages
*pvec
)
1418 int i
, ret
, nr_unsync_leaf
= 0;
1420 for_each_unsync_children(sp
->unsync_child_bitmap
, i
) {
1421 struct kvm_mmu_page
*child
;
1422 u64 ent
= sp
->spt
[i
];
1424 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1425 goto clear_child_bitmap
;
1427 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1429 if (child
->unsync_children
) {
1430 if (mmu_pages_add(pvec
, child
, i
))
1433 ret
= __mmu_unsync_walk(child
, pvec
);
1435 goto clear_child_bitmap
;
1437 nr_unsync_leaf
+= ret
;
1440 } else if (child
->unsync
) {
1442 if (mmu_pages_add(pvec
, child
, i
))
1445 goto clear_child_bitmap
;
1450 __clear_bit(i
, sp
->unsync_child_bitmap
);
1451 sp
->unsync_children
--;
1452 WARN_ON((int)sp
->unsync_children
< 0);
1456 return nr_unsync_leaf
;
1459 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1460 struct kvm_mmu_pages
*pvec
)
1462 if (!sp
->unsync_children
)
1465 mmu_pages_add(pvec
, sp
, 0);
1466 return __mmu_unsync_walk(sp
, pvec
);
1469 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1471 WARN_ON(!sp
->unsync
);
1472 trace_kvm_mmu_sync_page(sp
);
1474 --kvm
->stat
.mmu_unsync
;
1477 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1478 struct list_head
*invalid_list
);
1479 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1480 struct list_head
*invalid_list
);
1482 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1483 hlist_for_each_entry(sp, pos, \
1484 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1485 if ((sp)->gfn != (gfn)) {} else
1487 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1488 hlist_for_each_entry(sp, pos, \
1489 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1490 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1491 (sp)->role.invalid) {} else
1493 /* @sp->gfn should be write-protected at the call site */
1494 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1495 struct list_head
*invalid_list
, bool clear_unsync
)
1497 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1498 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1503 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1505 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1506 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1510 kvm_mmu_flush_tlb(vcpu
);
1514 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1515 struct kvm_mmu_page
*sp
)
1517 LIST_HEAD(invalid_list
);
1520 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1522 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1527 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1528 struct list_head
*invalid_list
)
1530 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1533 /* @gfn should be write-protected at the call site */
1534 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1536 struct kvm_mmu_page
*s
;
1537 struct hlist_node
*node
;
1538 LIST_HEAD(invalid_list
);
1541 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
1545 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1546 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1547 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1548 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1549 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1555 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1557 kvm_mmu_flush_tlb(vcpu
);
1560 struct mmu_page_path
{
1561 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1562 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1565 #define for_each_sp(pvec, sp, parents, i) \
1566 for (i = mmu_pages_next(&pvec, &parents, -1), \
1567 sp = pvec.page[i].sp; \
1568 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1569 i = mmu_pages_next(&pvec, &parents, i))
1571 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1572 struct mmu_page_path
*parents
,
1577 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1578 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1580 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1581 parents
->idx
[0] = pvec
->page
[n
].idx
;
1585 parents
->parent
[sp
->role
.level
-2] = sp
;
1586 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1592 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1594 struct kvm_mmu_page
*sp
;
1595 unsigned int level
= 0;
1598 unsigned int idx
= parents
->idx
[level
];
1600 sp
= parents
->parent
[level
];
1604 --sp
->unsync_children
;
1605 WARN_ON((int)sp
->unsync_children
< 0);
1606 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1608 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1611 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1612 struct mmu_page_path
*parents
,
1613 struct kvm_mmu_pages
*pvec
)
1615 parents
->parent
[parent
->role
.level
-1] = NULL
;
1619 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1620 struct kvm_mmu_page
*parent
)
1623 struct kvm_mmu_page
*sp
;
1624 struct mmu_page_path parents
;
1625 struct kvm_mmu_pages pages
;
1626 LIST_HEAD(invalid_list
);
1628 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1629 while (mmu_unsync_walk(parent
, &pages
)) {
1632 for_each_sp(pages
, sp
, parents
, i
)
1633 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1636 kvm_flush_remote_tlbs(vcpu
->kvm
);
1638 for_each_sp(pages
, sp
, parents
, i
) {
1639 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1640 mmu_pages_clear_parents(&parents
);
1642 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1643 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1644 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1648 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1652 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1656 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1658 sp
->write_flooding_count
= 0;
1661 static void clear_sp_write_flooding_count(u64
*spte
)
1663 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
1665 __clear_sp_write_flooding_count(sp
);
1668 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1676 union kvm_mmu_page_role role
;
1678 struct kvm_mmu_page
*sp
;
1679 struct hlist_node
*node
;
1680 bool need_sync
= false;
1682 role
= vcpu
->arch
.mmu
.base_role
;
1684 role
.direct
= direct
;
1687 role
.access
= access
;
1688 if (!vcpu
->arch
.mmu
.direct_map
1689 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1690 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1691 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1692 role
.quadrant
= quadrant
;
1694 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
, node
) {
1695 if (!need_sync
&& sp
->unsync
)
1698 if (sp
->role
.word
!= role
.word
)
1701 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1704 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1705 if (sp
->unsync_children
) {
1706 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1707 kvm_mmu_mark_parents_unsync(sp
);
1708 } else if (sp
->unsync
)
1709 kvm_mmu_mark_parents_unsync(sp
);
1711 __clear_sp_write_flooding_count(sp
);
1712 trace_kvm_mmu_get_page(sp
, false);
1715 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1716 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1721 hlist_add_head(&sp
->hash_link
,
1722 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1724 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1725 kvm_flush_remote_tlbs(vcpu
->kvm
);
1726 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1727 kvm_sync_pages(vcpu
, gfn
);
1729 account_shadowed(vcpu
->kvm
, gfn
);
1731 init_shadow_page_table(sp
);
1732 trace_kvm_mmu_get_page(sp
, true);
1736 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1737 struct kvm_vcpu
*vcpu
, u64 addr
)
1739 iterator
->addr
= addr
;
1740 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1741 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1743 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1744 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1745 !vcpu
->arch
.mmu
.direct_map
)
1748 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1749 iterator
->shadow_addr
1750 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1751 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1753 if (!iterator
->shadow_addr
)
1754 iterator
->level
= 0;
1758 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1760 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1763 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1764 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1768 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1771 if (is_last_spte(spte
, iterator
->level
)) {
1772 iterator
->level
= 0;
1776 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1780 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1782 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1785 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1789 spte
= __pa(sp
->spt
)
1790 | PT_PRESENT_MASK
| PT_ACCESSED_MASK
1791 | PT_WRITABLE_MASK
| PT_USER_MASK
;
1792 mmu_spte_set(sptep
, spte
);
1795 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1797 if (is_large_pte(*sptep
)) {
1798 drop_spte(vcpu
->kvm
, sptep
);
1799 kvm_flush_remote_tlbs(vcpu
->kvm
);
1803 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1804 unsigned direct_access
)
1806 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1807 struct kvm_mmu_page
*child
;
1810 * For the direct sp, if the guest pte's dirty bit
1811 * changed form clean to dirty, it will corrupt the
1812 * sp's access: allow writable in the read-only sp,
1813 * so we should update the spte at this point to get
1814 * a new sp with the correct access.
1816 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
1817 if (child
->role
.access
== direct_access
)
1820 drop_parent_pte(child
, sptep
);
1821 kvm_flush_remote_tlbs(vcpu
->kvm
);
1825 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1829 struct kvm_mmu_page
*child
;
1832 if (is_shadow_present_pte(pte
)) {
1833 if (is_last_spte(pte
, sp
->role
.level
)) {
1834 drop_spte(kvm
, spte
);
1835 if (is_large_pte(pte
))
1838 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
1839 drop_parent_pte(child
, spte
);
1844 if (is_mmio_spte(pte
))
1845 mmu_spte_clear_no_track(spte
);
1850 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
1851 struct kvm_mmu_page
*sp
)
1855 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1856 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
1859 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1861 mmu_page_remove_parent_pte(sp
, parent_pte
);
1864 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1868 while ((parent_pte
= pte_list_next(&sp
->parent_ptes
, NULL
)))
1869 drop_parent_pte(sp
, parent_pte
);
1872 static int mmu_zap_unsync_children(struct kvm
*kvm
,
1873 struct kvm_mmu_page
*parent
,
1874 struct list_head
*invalid_list
)
1877 struct mmu_page_path parents
;
1878 struct kvm_mmu_pages pages
;
1880 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
1883 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1884 while (mmu_unsync_walk(parent
, &pages
)) {
1885 struct kvm_mmu_page
*sp
;
1887 for_each_sp(pages
, sp
, parents
, i
) {
1888 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
1889 mmu_pages_clear_parents(&parents
);
1892 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1898 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1899 struct list_head
*invalid_list
)
1903 trace_kvm_mmu_prepare_zap_page(sp
);
1904 ++kvm
->stat
.mmu_shadow_zapped
;
1905 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
1906 kvm_mmu_page_unlink_children(kvm
, sp
);
1907 kvm_mmu_unlink_parents(kvm
, sp
);
1908 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
1909 unaccount_shadowed(kvm
, sp
->gfn
);
1911 kvm_unlink_unsync_page(kvm
, sp
);
1912 if (!sp
->root_count
) {
1915 list_move(&sp
->link
, invalid_list
);
1916 kvm_mod_used_mmu_pages(kvm
, -1);
1918 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
1919 kvm_reload_remote_mmus(kvm
);
1922 sp
->role
.invalid
= 1;
1926 static void kvm_mmu_isolate_pages(struct list_head
*invalid_list
)
1928 struct kvm_mmu_page
*sp
;
1930 list_for_each_entry(sp
, invalid_list
, link
)
1931 kvm_mmu_isolate_page(sp
);
1934 static void free_pages_rcu(struct rcu_head
*head
)
1936 struct kvm_mmu_page
*next
, *sp
;
1938 sp
= container_of(head
, struct kvm_mmu_page
, rcu
);
1940 if (!list_empty(&sp
->link
))
1941 next
= list_first_entry(&sp
->link
,
1942 struct kvm_mmu_page
, link
);
1945 kvm_mmu_free_page(sp
);
1950 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1951 struct list_head
*invalid_list
)
1953 struct kvm_mmu_page
*sp
;
1955 if (list_empty(invalid_list
))
1958 kvm_flush_remote_tlbs(kvm
);
1960 if (atomic_read(&kvm
->arch
.reader_counter
)) {
1961 kvm_mmu_isolate_pages(invalid_list
);
1962 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
1963 list_del_init(invalid_list
);
1965 trace_kvm_mmu_delay_free_pages(sp
);
1966 call_rcu(&sp
->rcu
, free_pages_rcu
);
1971 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
1972 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
1973 kvm_mmu_isolate_page(sp
);
1974 kvm_mmu_free_page(sp
);
1975 } while (!list_empty(invalid_list
));
1980 * Changing the number of mmu pages allocated to the vm
1981 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1983 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
1985 LIST_HEAD(invalid_list
);
1987 * If we set the number of mmu pages to be smaller be than the
1988 * number of actived pages , we must to free some mmu pages before we
1992 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
1993 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
&&
1994 !list_empty(&kvm
->arch
.active_mmu_pages
)) {
1995 struct kvm_mmu_page
*page
;
1997 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
1998 struct kvm_mmu_page
, link
);
1999 kvm_mmu_prepare_zap_page(kvm
, page
, &invalid_list
);
2001 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2002 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2005 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2008 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2010 struct kvm_mmu_page
*sp
;
2011 struct hlist_node
*node
;
2012 LIST_HEAD(invalid_list
);
2015 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2017 spin_lock(&kvm
->mmu_lock
);
2018 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2019 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2022 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2024 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2025 spin_unlock(&kvm
->mmu_lock
);
2029 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2031 static void mmu_unshadow(struct kvm
*kvm
, gfn_t gfn
)
2033 struct kvm_mmu_page
*sp
;
2034 struct hlist_node
*node
;
2035 LIST_HEAD(invalid_list
);
2037 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2038 pgprintk("%s: zap %llx %x\n",
2039 __func__
, gfn
, sp
->role
.word
);
2040 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2042 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2045 static void page_header_update_slot(struct kvm
*kvm
, void *pte
, gfn_t gfn
)
2047 int slot
= memslot_id(kvm
, gfn
);
2048 struct kvm_mmu_page
*sp
= page_header(__pa(pte
));
2050 __set_bit(slot
, sp
->slot_bitmap
);
2054 * The function is based on mtrr_type_lookup() in
2055 * arch/x86/kernel/cpu/mtrr/generic.c
2057 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2062 u8 prev_match
, curr_match
;
2063 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2065 if (!mtrr_state
->enabled
)
2068 /* Make end inclusive end, instead of exclusive */
2071 /* Look in fixed ranges. Just return the type as per start */
2072 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2075 if (start
< 0x80000) {
2077 idx
+= (start
>> 16);
2078 return mtrr_state
->fixed_ranges
[idx
];
2079 } else if (start
< 0xC0000) {
2081 idx
+= ((start
- 0x80000) >> 14);
2082 return mtrr_state
->fixed_ranges
[idx
];
2083 } else if (start
< 0x1000000) {
2085 idx
+= ((start
- 0xC0000) >> 12);
2086 return mtrr_state
->fixed_ranges
[idx
];
2091 * Look in variable ranges
2092 * Look of multiple ranges matching this address and pick type
2093 * as per MTRR precedence
2095 if (!(mtrr_state
->enabled
& 2))
2096 return mtrr_state
->def_type
;
2099 for (i
= 0; i
< num_var_ranges
; ++i
) {
2100 unsigned short start_state
, end_state
;
2102 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2105 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2106 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2107 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2108 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2110 start_state
= ((start
& mask
) == (base
& mask
));
2111 end_state
= ((end
& mask
) == (base
& mask
));
2112 if (start_state
!= end_state
)
2115 if ((start
& mask
) != (base
& mask
))
2118 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2119 if (prev_match
== 0xFF) {
2120 prev_match
= curr_match
;
2124 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2125 curr_match
== MTRR_TYPE_UNCACHABLE
)
2126 return MTRR_TYPE_UNCACHABLE
;
2128 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2129 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2130 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2131 curr_match
== MTRR_TYPE_WRBACK
)) {
2132 prev_match
= MTRR_TYPE_WRTHROUGH
;
2133 curr_match
= MTRR_TYPE_WRTHROUGH
;
2136 if (prev_match
!= curr_match
)
2137 return MTRR_TYPE_UNCACHABLE
;
2140 if (prev_match
!= 0xFF)
2143 return mtrr_state
->def_type
;
2146 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2150 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2151 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2152 if (mtrr
== 0xfe || mtrr
== 0xff)
2153 mtrr
= MTRR_TYPE_WRBACK
;
2156 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2158 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2160 trace_kvm_mmu_unsync_page(sp
);
2161 ++vcpu
->kvm
->stat
.mmu_unsync
;
2164 kvm_mmu_mark_parents_unsync(sp
);
2167 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2169 struct kvm_mmu_page
*s
;
2170 struct hlist_node
*node
;
2172 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2175 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2176 __kvm_unsync_page(vcpu
, s
);
2180 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2183 struct kvm_mmu_page
*s
;
2184 struct hlist_node
*node
;
2185 bool need_unsync
= false;
2187 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2191 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2194 if (!need_unsync
&& !s
->unsync
) {
2201 kvm_unsync_pages(vcpu
, gfn
);
2205 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2206 unsigned pte_access
, int user_fault
,
2207 int write_fault
, int level
,
2208 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2209 bool can_unsync
, bool host_writable
)
2211 u64 spte
, entry
= *sptep
;
2214 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2217 spte
= PT_PRESENT_MASK
;
2219 spte
|= shadow_accessed_mask
;
2221 if (pte_access
& ACC_EXEC_MASK
)
2222 spte
|= shadow_x_mask
;
2224 spte
|= shadow_nx_mask
;
2225 if (pte_access
& ACC_USER_MASK
)
2226 spte
|= shadow_user_mask
;
2227 if (level
> PT_PAGE_TABLE_LEVEL
)
2228 spte
|= PT_PAGE_SIZE_MASK
;
2230 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2231 kvm_is_mmio_pfn(pfn
));
2234 spte
|= SPTE_HOST_WRITEABLE
;
2236 pte_access
&= ~ACC_WRITE_MASK
;
2238 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2240 if ((pte_access
& ACC_WRITE_MASK
)
2241 || (!vcpu
->arch
.mmu
.direct_map
&& write_fault
2242 && !is_write_protection(vcpu
) && !user_fault
)) {
2244 if (level
> PT_PAGE_TABLE_LEVEL
&&
2245 has_wrprotected_page(vcpu
->kvm
, gfn
, level
)) {
2247 drop_spte(vcpu
->kvm
, sptep
);
2251 spte
|= PT_WRITABLE_MASK
;
2253 if (!vcpu
->arch
.mmu
.direct_map
2254 && !(pte_access
& ACC_WRITE_MASK
)) {
2255 spte
&= ~PT_USER_MASK
;
2257 * If we converted a user page to a kernel page,
2258 * so that the kernel can write to it when cr0.wp=0,
2259 * then we should prevent the kernel from executing it
2260 * if SMEP is enabled.
2262 if (kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
))
2263 spte
|= PT64_NX_MASK
;
2267 * Optimization: for pte sync, if spte was writable the hash
2268 * lookup is unnecessary (and expensive). Write protection
2269 * is responsibility of mmu_get_page / kvm_sync_page.
2270 * Same reasoning can be applied to dirty page accounting.
2272 if (!can_unsync
&& is_writable_pte(*sptep
))
2275 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2276 pgprintk("%s: found shadow page for %llx, marking ro\n",
2279 pte_access
&= ~ACC_WRITE_MASK
;
2280 if (is_writable_pte(spte
))
2281 spte
&= ~PT_WRITABLE_MASK
;
2285 if (pte_access
& ACC_WRITE_MASK
)
2286 mark_page_dirty(vcpu
->kvm
, gfn
);
2289 mmu_spte_update(sptep
, spte
);
2291 * If we overwrite a writable spte with a read-only one we
2292 * should flush remote TLBs. Otherwise rmap_write_protect
2293 * will find a read-only spte, even though the writable spte
2294 * might be cached on a CPU's TLB.
2296 if (is_writable_pte(entry
) && !is_writable_pte(*sptep
))
2297 kvm_flush_remote_tlbs(vcpu
->kvm
);
2302 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2303 unsigned pt_access
, unsigned pte_access
,
2304 int user_fault
, int write_fault
,
2305 int *emulate
, int level
, gfn_t gfn
,
2306 pfn_t pfn
, bool speculative
,
2309 int was_rmapped
= 0;
2312 pgprintk("%s: spte %llx access %x write_fault %d"
2313 " user_fault %d gfn %llx\n",
2314 __func__
, *sptep
, pt_access
,
2315 write_fault
, user_fault
, gfn
);
2317 if (is_rmap_spte(*sptep
)) {
2319 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2320 * the parent of the now unreachable PTE.
2322 if (level
> PT_PAGE_TABLE_LEVEL
&&
2323 !is_large_pte(*sptep
)) {
2324 struct kvm_mmu_page
*child
;
2327 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2328 drop_parent_pte(child
, sptep
);
2329 kvm_flush_remote_tlbs(vcpu
->kvm
);
2330 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2331 pgprintk("hfn old %llx new %llx\n",
2332 spte_to_pfn(*sptep
), pfn
);
2333 drop_spte(vcpu
->kvm
, sptep
);
2334 kvm_flush_remote_tlbs(vcpu
->kvm
);
2339 if (set_spte(vcpu
, sptep
, pte_access
, user_fault
, write_fault
,
2340 level
, gfn
, pfn
, speculative
, true,
2344 kvm_mmu_flush_tlb(vcpu
);
2347 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2350 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2351 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2352 is_large_pte(*sptep
)? "2MB" : "4kB",
2353 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2355 if (!was_rmapped
&& is_large_pte(*sptep
))
2356 ++vcpu
->kvm
->stat
.lpages
;
2358 if (is_shadow_present_pte(*sptep
)) {
2359 page_header_update_slot(vcpu
->kvm
, sptep
, gfn
);
2361 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2362 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2363 rmap_recycle(vcpu
, sptep
, gfn
);
2366 kvm_release_pfn_clean(pfn
);
2369 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2373 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2376 struct kvm_memory_slot
*slot
;
2379 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2381 get_page(fault_page
);
2382 return page_to_pfn(fault_page
);
2385 hva
= gfn_to_hva_memslot(slot
, gfn
);
2387 return hva_to_pfn_atomic(vcpu
->kvm
, hva
);
2390 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2391 struct kvm_mmu_page
*sp
,
2392 u64
*start
, u64
*end
)
2394 struct page
*pages
[PTE_PREFETCH_NUM
];
2395 unsigned access
= sp
->role
.access
;
2399 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2400 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2403 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2407 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2408 mmu_set_spte(vcpu
, start
, ACC_ALL
,
2410 sp
->role
.level
, gfn
,
2411 page_to_pfn(pages
[i
]), true, true);
2416 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2417 struct kvm_mmu_page
*sp
, u64
*sptep
)
2419 u64
*spte
, *start
= NULL
;
2422 WARN_ON(!sp
->role
.direct
);
2424 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2427 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2428 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2431 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2439 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2441 struct kvm_mmu_page
*sp
;
2444 * Since it's no accessed bit on EPT, it's no way to
2445 * distinguish between actually accessed translations
2446 * and prefetched, so disable pte prefetch if EPT is
2449 if (!shadow_accessed_mask
)
2452 sp
= page_header(__pa(sptep
));
2453 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2456 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2459 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2460 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2463 struct kvm_shadow_walk_iterator iterator
;
2464 struct kvm_mmu_page
*sp
;
2468 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2469 if (iterator
.level
== level
) {
2470 unsigned pte_access
= ACC_ALL
;
2472 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
, pte_access
,
2474 level
, gfn
, pfn
, prefault
, map_writable
);
2475 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2476 ++vcpu
->stat
.pf_fixed
;
2480 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2481 u64 base_addr
= iterator
.addr
;
2483 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2484 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2485 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2487 1, ACC_ALL
, iterator
.sptep
);
2489 pgprintk("nonpaging_map: ENOMEM\n");
2490 kvm_release_pfn_clean(pfn
);
2494 mmu_spte_set(iterator
.sptep
,
2496 | PT_PRESENT_MASK
| PT_WRITABLE_MASK
2497 | shadow_user_mask
| shadow_x_mask
2498 | shadow_accessed_mask
);
2504 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2508 info
.si_signo
= SIGBUS
;
2510 info
.si_code
= BUS_MCEERR_AR
;
2511 info
.si_addr
= (void __user
*)address
;
2512 info
.si_addr_lsb
= PAGE_SHIFT
;
2514 send_sig_info(SIGBUS
, &info
, tsk
);
2517 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2519 kvm_release_pfn_clean(pfn
);
2520 if (is_hwpoison_pfn(pfn
)) {
2521 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2528 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2529 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2533 int level
= *levelp
;
2536 * Check if it's a transparent hugepage. If this would be an
2537 * hugetlbfs page, level wouldn't be set to
2538 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2541 if (!is_error_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2542 level
== PT_PAGE_TABLE_LEVEL
&&
2543 PageTransCompound(pfn_to_page(pfn
)) &&
2544 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2547 * mmu_notifier_retry was successful and we hold the
2548 * mmu_lock here, so the pmd can't become splitting
2549 * from under us, and in turn
2550 * __split_huge_page_refcount() can't run from under
2551 * us and we can safely transfer the refcount from
2552 * PG_tail to PG_head as we switch the pfn to tail to
2555 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2556 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2557 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2561 kvm_release_pfn_clean(pfn
);
2563 if (!get_page_unless_zero(pfn_to_page(pfn
)))
2570 static bool mmu_invalid_pfn(pfn_t pfn
)
2572 return unlikely(is_invalid_pfn(pfn
));
2575 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2576 pfn_t pfn
, unsigned access
, int *ret_val
)
2580 /* The pfn is invalid, report the error! */
2581 if (unlikely(is_invalid_pfn(pfn
))) {
2582 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2586 if (unlikely(is_noslot_pfn(pfn
)))
2587 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2594 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2595 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2597 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, int write
, gfn_t gfn
,
2604 unsigned long mmu_seq
;
2607 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2608 if (likely(!force_pt_level
)) {
2609 level
= mapping_level(vcpu
, gfn
);
2611 * This path builds a PAE pagetable - so we can map
2612 * 2mb pages at maximum. Therefore check if the level
2613 * is larger than that.
2615 if (level
> PT_DIRECTORY_LEVEL
)
2616 level
= PT_DIRECTORY_LEVEL
;
2618 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2620 level
= PT_PAGE_TABLE_LEVEL
;
2622 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2625 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2628 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2631 spin_lock(&vcpu
->kvm
->mmu_lock
);
2632 if (mmu_notifier_retry(vcpu
, mmu_seq
))
2634 kvm_mmu_free_some_pages(vcpu
);
2635 if (likely(!force_pt_level
))
2636 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2637 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2639 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2645 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2646 kvm_release_pfn_clean(pfn
);
2651 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2654 struct kvm_mmu_page
*sp
;
2655 LIST_HEAD(invalid_list
);
2657 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2659 spin_lock(&vcpu
->kvm
->mmu_lock
);
2660 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2661 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2662 vcpu
->arch
.mmu
.direct_map
)) {
2663 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2665 sp
= page_header(root
);
2667 if (!sp
->root_count
&& sp
->role
.invalid
) {
2668 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2669 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2671 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2672 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2675 for (i
= 0; i
< 4; ++i
) {
2676 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2679 root
&= PT64_BASE_ADDR_MASK
;
2680 sp
= page_header(root
);
2682 if (!sp
->root_count
&& sp
->role
.invalid
)
2683 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2686 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2688 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2689 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2690 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2693 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2697 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2698 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2705 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2707 struct kvm_mmu_page
*sp
;
2710 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2711 spin_lock(&vcpu
->kvm
->mmu_lock
);
2712 kvm_mmu_free_some_pages(vcpu
);
2713 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2716 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2717 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2718 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2719 for (i
= 0; i
< 4; ++i
) {
2720 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2722 ASSERT(!VALID_PAGE(root
));
2723 spin_lock(&vcpu
->kvm
->mmu_lock
);
2724 kvm_mmu_free_some_pages(vcpu
);
2725 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2727 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2729 root
= __pa(sp
->spt
);
2731 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2732 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2734 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2741 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2743 struct kvm_mmu_page
*sp
;
2748 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2750 if (mmu_check_root(vcpu
, root_gfn
))
2754 * Do we shadow a long mode page table? If so we need to
2755 * write-protect the guests page table root.
2757 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2758 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2760 ASSERT(!VALID_PAGE(root
));
2762 spin_lock(&vcpu
->kvm
->mmu_lock
);
2763 kvm_mmu_free_some_pages(vcpu
);
2764 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
2766 root
= __pa(sp
->spt
);
2768 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2769 vcpu
->arch
.mmu
.root_hpa
= root
;
2774 * We shadow a 32 bit page table. This may be a legacy 2-level
2775 * or a PAE 3-level page table. In either case we need to be aware that
2776 * the shadow page table may be a PAE or a long mode page table.
2778 pm_mask
= PT_PRESENT_MASK
;
2779 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
2780 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
2782 for (i
= 0; i
< 4; ++i
) {
2783 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2785 ASSERT(!VALID_PAGE(root
));
2786 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
2787 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
2788 if (!is_present_gpte(pdptr
)) {
2789 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
2792 root_gfn
= pdptr
>> PAGE_SHIFT
;
2793 if (mmu_check_root(vcpu
, root_gfn
))
2796 spin_lock(&vcpu
->kvm
->mmu_lock
);
2797 kvm_mmu_free_some_pages(vcpu
);
2798 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
2801 root
= __pa(sp
->spt
);
2803 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2805 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
2807 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2810 * If we shadow a 32 bit page table with a long mode page
2811 * table we enter this path.
2813 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2814 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
2816 * The additional page necessary for this is only
2817 * allocated on demand.
2822 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
2823 if (lm_root
== NULL
)
2826 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
2828 vcpu
->arch
.mmu
.lm_root
= lm_root
;
2831 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
2837 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
2839 if (vcpu
->arch
.mmu
.direct_map
)
2840 return mmu_alloc_direct_roots(vcpu
);
2842 return mmu_alloc_shadow_roots(vcpu
);
2845 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
2848 struct kvm_mmu_page
*sp
;
2850 if (vcpu
->arch
.mmu
.direct_map
)
2853 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2856 vcpu_clear_mmio_info(vcpu
, ~0ul);
2857 trace_kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
2858 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2859 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2860 sp
= page_header(root
);
2861 mmu_sync_children(vcpu
, sp
);
2862 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
2865 for (i
= 0; i
< 4; ++i
) {
2866 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2868 if (root
&& VALID_PAGE(root
)) {
2869 root
&= PT64_BASE_ADDR_MASK
;
2870 sp
= page_header(root
);
2871 mmu_sync_children(vcpu
, sp
);
2874 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
2877 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
2879 spin_lock(&vcpu
->kvm
->mmu_lock
);
2880 mmu_sync_roots(vcpu
);
2881 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2884 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
2885 u32 access
, struct x86_exception
*exception
)
2888 exception
->error_code
= 0;
2892 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
2894 struct x86_exception
*exception
)
2897 exception
->error_code
= 0;
2898 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
2901 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
2904 return vcpu_match_mmio_gpa(vcpu
, addr
);
2906 return vcpu_match_mmio_gva(vcpu
, addr
);
2911 * On direct hosts, the last spte is only allows two states
2912 * for mmio page fault:
2913 * - It is the mmio spte
2914 * - It is zapped or it is being zapped.
2916 * This function completely checks the spte when the last spte
2917 * is not the mmio spte.
2919 static bool check_direct_spte_mmio_pf(u64 spte
)
2921 return __check_direct_spte_mmio_pf(spte
);
2924 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
2926 struct kvm_shadow_walk_iterator iterator
;
2929 walk_shadow_page_lockless_begin(vcpu
);
2930 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
2931 if (!is_shadow_present_pte(spte
))
2933 walk_shadow_page_lockless_end(vcpu
);
2939 * If it is a real mmio page fault, return 1 and emulat the instruction
2940 * directly, return 0 to let CPU fault again on the address, -1 is
2941 * returned if bug is detected.
2943 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
2947 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
2950 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
2952 if (is_mmio_spte(spte
)) {
2953 gfn_t gfn
= get_mmio_spte_gfn(spte
);
2954 unsigned access
= get_mmio_spte_access(spte
);
2959 trace_handle_mmio_page_fault(addr
, gfn
, access
);
2960 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
2965 * It's ok if the gva is remapped by other cpus on shadow guest,
2966 * it's a BUG if the gfn is not a mmio page.
2968 if (direct
&& !check_direct_spte_mmio_pf(spte
))
2972 * If the page table is zapped by other cpus, let CPU fault again on
2977 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
2979 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
2980 u32 error_code
, bool direct
)
2984 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
2989 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
2990 u32 error_code
, bool prefault
)
2995 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
2997 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2998 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
3000 r
= mmu_topup_memory_caches(vcpu
);
3005 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3007 gfn
= gva
>> PAGE_SHIFT
;
3009 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3010 error_code
& PFERR_WRITE_MASK
, gfn
, prefault
);
3013 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3015 struct kvm_arch_async_pf arch
;
3017 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3019 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3020 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3022 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3025 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3027 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3028 kvm_event_needs_reinjection(vcpu
)))
3031 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3034 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3035 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3039 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3042 return false; /* *pfn has correct page already */
3044 put_page(pfn_to_page(*pfn
));
3046 if (!prefault
&& can_do_async_pf(vcpu
)) {
3047 trace_kvm_try_async_get_page(gva
, gfn
);
3048 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3049 trace_kvm_async_pf_doublefault(gva
, gfn
);
3050 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3052 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3056 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3061 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3068 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3069 unsigned long mmu_seq
;
3070 int write
= error_code
& PFERR_WRITE_MASK
;
3074 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3076 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3077 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3079 r
= mmu_topup_memory_caches(vcpu
);
3083 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3084 if (likely(!force_pt_level
)) {
3085 level
= mapping_level(vcpu
, gfn
);
3086 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3088 level
= PT_PAGE_TABLE_LEVEL
;
3090 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3093 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3096 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3099 spin_lock(&vcpu
->kvm
->mmu_lock
);
3100 if (mmu_notifier_retry(vcpu
, mmu_seq
))
3102 kvm_mmu_free_some_pages(vcpu
);
3103 if (likely(!force_pt_level
))
3104 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3105 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3106 level
, gfn
, pfn
, prefault
);
3107 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3112 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3113 kvm_release_pfn_clean(pfn
);
3117 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3119 mmu_free_roots(vcpu
);
3122 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3123 struct kvm_mmu
*context
)
3125 context
->new_cr3
= nonpaging_new_cr3
;
3126 context
->page_fault
= nonpaging_page_fault
;
3127 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3128 context
->free
= nonpaging_free
;
3129 context
->sync_page
= nonpaging_sync_page
;
3130 context
->invlpg
= nonpaging_invlpg
;
3131 context
->update_pte
= nonpaging_update_pte
;
3132 context
->root_level
= 0;
3133 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3134 context
->root_hpa
= INVALID_PAGE
;
3135 context
->direct_map
= true;
3136 context
->nx
= false;
3140 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3142 ++vcpu
->stat
.tlb_flush
;
3143 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3146 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3148 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3149 mmu_free_roots(vcpu
);
3152 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3154 return kvm_read_cr3(vcpu
);
3157 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3158 struct x86_exception
*fault
)
3160 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3163 static void paging_free(struct kvm_vcpu
*vcpu
)
3165 nonpaging_free(vcpu
);
3168 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3172 bit7
= (gpte
>> 7) & 1;
3173 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
3176 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3179 if (unlikely(is_mmio_spte(*sptep
))) {
3180 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3181 mmu_spte_clear_no_track(sptep
);
3186 mark_mmio_spte(sptep
, gfn
, access
);
3194 #include "paging_tmpl.h"
3198 #include "paging_tmpl.h"
3201 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3202 struct kvm_mmu
*context
,
3205 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3206 u64 exb_bit_rsvd
= 0;
3209 exb_bit_rsvd
= rsvd_bits(63, 63);
3211 case PT32_ROOT_LEVEL
:
3212 /* no rsvd bits for 2 level 4K page table entries */
3213 context
->rsvd_bits_mask
[0][1] = 0;
3214 context
->rsvd_bits_mask
[0][0] = 0;
3215 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3217 if (!is_pse(vcpu
)) {
3218 context
->rsvd_bits_mask
[1][1] = 0;
3222 if (is_cpuid_PSE36())
3223 /* 36bits PSE 4MB page */
3224 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3226 /* 32 bits PSE 4MB page */
3227 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3229 case PT32E_ROOT_LEVEL
:
3230 context
->rsvd_bits_mask
[0][2] =
3231 rsvd_bits(maxphyaddr
, 63) |
3232 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3233 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3234 rsvd_bits(maxphyaddr
, 62); /* PDE */
3235 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3236 rsvd_bits(maxphyaddr
, 62); /* PTE */
3237 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3238 rsvd_bits(maxphyaddr
, 62) |
3239 rsvd_bits(13, 20); /* large page */
3240 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3242 case PT64_ROOT_LEVEL
:
3243 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3244 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3245 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3246 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3247 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3248 rsvd_bits(maxphyaddr
, 51);
3249 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3250 rsvd_bits(maxphyaddr
, 51);
3251 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3252 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3253 rsvd_bits(maxphyaddr
, 51) |
3255 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3256 rsvd_bits(maxphyaddr
, 51) |
3257 rsvd_bits(13, 20); /* large page */
3258 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3263 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3264 struct kvm_mmu
*context
,
3267 context
->nx
= is_nx(vcpu
);
3269 reset_rsvds_bits_mask(vcpu
, context
, level
);
3271 ASSERT(is_pae(vcpu
));
3272 context
->new_cr3
= paging_new_cr3
;
3273 context
->page_fault
= paging64_page_fault
;
3274 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3275 context
->sync_page
= paging64_sync_page
;
3276 context
->invlpg
= paging64_invlpg
;
3277 context
->update_pte
= paging64_update_pte
;
3278 context
->free
= paging_free
;
3279 context
->root_level
= level
;
3280 context
->shadow_root_level
= level
;
3281 context
->root_hpa
= INVALID_PAGE
;
3282 context
->direct_map
= false;
3286 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3287 struct kvm_mmu
*context
)
3289 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3292 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3293 struct kvm_mmu
*context
)
3295 context
->nx
= false;
3297 reset_rsvds_bits_mask(vcpu
, context
, PT32_ROOT_LEVEL
);
3299 context
->new_cr3
= paging_new_cr3
;
3300 context
->page_fault
= paging32_page_fault
;
3301 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3302 context
->free
= paging_free
;
3303 context
->sync_page
= paging32_sync_page
;
3304 context
->invlpg
= paging32_invlpg
;
3305 context
->update_pte
= paging32_update_pte
;
3306 context
->root_level
= PT32_ROOT_LEVEL
;
3307 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3308 context
->root_hpa
= INVALID_PAGE
;
3309 context
->direct_map
= false;
3313 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3314 struct kvm_mmu
*context
)
3316 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3319 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3321 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3323 context
->base_role
.word
= 0;
3324 context
->new_cr3
= nonpaging_new_cr3
;
3325 context
->page_fault
= tdp_page_fault
;
3326 context
->free
= nonpaging_free
;
3327 context
->sync_page
= nonpaging_sync_page
;
3328 context
->invlpg
= nonpaging_invlpg
;
3329 context
->update_pte
= nonpaging_update_pte
;
3330 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3331 context
->root_hpa
= INVALID_PAGE
;
3332 context
->direct_map
= true;
3333 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3334 context
->get_cr3
= get_cr3
;
3335 context
->get_pdptr
= kvm_pdptr_read
;
3336 context
->inject_page_fault
= kvm_inject_page_fault
;
3337 context
->nx
= is_nx(vcpu
);
3339 if (!is_paging(vcpu
)) {
3340 context
->nx
= false;
3341 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3342 context
->root_level
= 0;
3343 } else if (is_long_mode(vcpu
)) {
3344 context
->nx
= is_nx(vcpu
);
3345 reset_rsvds_bits_mask(vcpu
, context
, PT64_ROOT_LEVEL
);
3346 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3347 context
->root_level
= PT64_ROOT_LEVEL
;
3348 } else if (is_pae(vcpu
)) {
3349 context
->nx
= is_nx(vcpu
);
3350 reset_rsvds_bits_mask(vcpu
, context
, PT32E_ROOT_LEVEL
);
3351 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3352 context
->root_level
= PT32E_ROOT_LEVEL
;
3354 context
->nx
= false;
3355 reset_rsvds_bits_mask(vcpu
, context
, PT32_ROOT_LEVEL
);
3356 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3357 context
->root_level
= PT32_ROOT_LEVEL
;
3363 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3366 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3368 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3370 if (!is_paging(vcpu
))
3371 r
= nonpaging_init_context(vcpu
, context
);
3372 else if (is_long_mode(vcpu
))
3373 r
= paging64_init_context(vcpu
, context
);
3374 else if (is_pae(vcpu
))
3375 r
= paging32E_init_context(vcpu
, context
);
3377 r
= paging32_init_context(vcpu
, context
);
3379 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3380 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3381 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3382 = smep
&& !is_write_protection(vcpu
);
3386 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3388 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3390 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3392 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3393 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3394 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3395 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3400 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3402 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3404 g_context
->get_cr3
= get_cr3
;
3405 g_context
->get_pdptr
= kvm_pdptr_read
;
3406 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3409 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3410 * translation of l2_gpa to l1_gpa addresses is done using the
3411 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3412 * functions between mmu and nested_mmu are swapped.
3414 if (!is_paging(vcpu
)) {
3415 g_context
->nx
= false;
3416 g_context
->root_level
= 0;
3417 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3418 } else if (is_long_mode(vcpu
)) {
3419 g_context
->nx
= is_nx(vcpu
);
3420 reset_rsvds_bits_mask(vcpu
, g_context
, PT64_ROOT_LEVEL
);
3421 g_context
->root_level
= PT64_ROOT_LEVEL
;
3422 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3423 } else if (is_pae(vcpu
)) {
3424 g_context
->nx
= is_nx(vcpu
);
3425 reset_rsvds_bits_mask(vcpu
, g_context
, PT32E_ROOT_LEVEL
);
3426 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3427 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3429 g_context
->nx
= false;
3430 reset_rsvds_bits_mask(vcpu
, g_context
, PT32_ROOT_LEVEL
);
3431 g_context
->root_level
= PT32_ROOT_LEVEL
;
3432 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3438 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3440 if (mmu_is_nested(vcpu
))
3441 return init_kvm_nested_mmu(vcpu
);
3442 else if (tdp_enabled
)
3443 return init_kvm_tdp_mmu(vcpu
);
3445 return init_kvm_softmmu(vcpu
);
3448 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3451 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3452 /* mmu.free() should set root_hpa = INVALID_PAGE */
3453 vcpu
->arch
.mmu
.free(vcpu
);
3456 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3458 destroy_kvm_mmu(vcpu
);
3459 return init_kvm_mmu(vcpu
);
3461 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3463 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3467 r
= mmu_topup_memory_caches(vcpu
);
3470 r
= mmu_alloc_roots(vcpu
);
3471 spin_lock(&vcpu
->kvm
->mmu_lock
);
3472 mmu_sync_roots(vcpu
);
3473 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3476 /* set_cr3() should ensure TLB has been flushed */
3477 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3481 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3483 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3485 mmu_free_roots(vcpu
);
3487 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3489 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3490 struct kvm_mmu_page
*sp
, u64
*spte
,
3493 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3494 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3498 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3499 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3502 static bool need_remote_flush(u64 old
, u64
new)
3504 if (!is_shadow_present_pte(old
))
3506 if (!is_shadow_present_pte(new))
3508 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3510 old
^= PT64_NX_MASK
;
3511 new ^= PT64_NX_MASK
;
3512 return (old
& ~new & PT64_PERM_MASK
) != 0;
3515 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3516 bool remote_flush
, bool local_flush
)
3522 kvm_flush_remote_tlbs(vcpu
->kvm
);
3523 else if (local_flush
)
3524 kvm_mmu_flush_tlb(vcpu
);
3527 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
3528 const u8
*new, int *bytes
)
3534 * Assume that the pte write on a page table of the same type
3535 * as the current vcpu paging mode since we update the sptes only
3536 * when they have the same mode.
3538 if (is_pae(vcpu
) && *bytes
== 4) {
3539 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3542 r
= kvm_read_guest(vcpu
->kvm
, *gpa
, &gentry
, min(*bytes
, 8));
3545 new = (const u8
*)&gentry
;
3550 gentry
= *(const u32
*)new;
3553 gentry
= *(const u64
*)new;
3564 * If we're seeing too many writes to a page, it may no longer be a page table,
3565 * or we may be forking, in which case it is better to unmap the page.
3567 static bool detect_write_flooding(struct kvm_mmu_page
*sp
, u64
*spte
)
3570 * Skip write-flooding detected for the sp whose level is 1, because
3571 * it can become unsync, then the guest page is not write-protected.
3573 if (sp
->role
.level
== 1)
3576 return ++sp
->write_flooding_count
>= 3;
3580 * Misaligned accesses are too much trouble to fix up; also, they usually
3581 * indicate a page is not used as a page table.
3583 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
3586 unsigned offset
, pte_size
, misaligned
;
3588 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3589 gpa
, bytes
, sp
->role
.word
);
3591 offset
= offset_in_page(gpa
);
3592 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3595 * Sometimes, the OS only writes the last one bytes to update status
3596 * bits, for example, in linux, andb instruction is used in clear_bit().
3598 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
3601 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3602 misaligned
|= bytes
< 4;
3607 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
3609 unsigned page_offset
, quadrant
;
3613 page_offset
= offset_in_page(gpa
);
3614 level
= sp
->role
.level
;
3616 if (!sp
->role
.cr4_pae
) {
3617 page_offset
<<= 1; /* 32->64 */
3619 * A 32-bit pde maps 4MB while the shadow pdes map
3620 * only 2MB. So we need to double the offset again
3621 * and zap two pdes instead of one.
3623 if (level
== PT32_ROOT_LEVEL
) {
3624 page_offset
&= ~7; /* kill rounding error */
3628 quadrant
= page_offset
>> PAGE_SHIFT
;
3629 page_offset
&= ~PAGE_MASK
;
3630 if (quadrant
!= sp
->role
.quadrant
)
3634 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3638 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3639 const u8
*new, int bytes
)
3641 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3642 union kvm_mmu_page_role mask
= { .word
= 0 };
3643 struct kvm_mmu_page
*sp
;
3644 struct hlist_node
*node
;
3645 LIST_HEAD(invalid_list
);
3646 u64 entry
, gentry
, *spte
;
3648 bool remote_flush
, local_flush
, zap_page
;
3651 * If we don't have indirect shadow pages, it means no page is
3652 * write-protected, so we can exit simply.
3654 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3657 zap_page
= remote_flush
= local_flush
= false;
3659 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3661 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
3664 * No need to care whether allocation memory is successful
3665 * or not since pte prefetch is skiped if it does not have
3666 * enough objects in the cache.
3668 mmu_topup_memory_caches(vcpu
);
3670 spin_lock(&vcpu
->kvm
->mmu_lock
);
3671 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3672 trace_kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3674 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3675 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
, node
) {
3676 spte
= get_written_sptes(sp
, gpa
, &npte
);
3678 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
3679 detect_write_flooding(sp
, spte
)) {
3680 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3682 ++vcpu
->kvm
->stat
.mmu_flooded
;
3686 spte
= get_written_sptes(sp
, gpa
, &npte
);
3693 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
3695 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
3696 & mask
.word
) && rmap_can_add(vcpu
))
3697 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
3698 if (!remote_flush
&& need_remote_flush(entry
, *spte
))
3699 remote_flush
= true;
3703 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
3704 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3705 trace_kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
3706 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3709 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
3714 if (vcpu
->arch
.mmu
.direct_map
)
3717 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
3719 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
3723 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
3725 void __kvm_mmu_free_some_pages(struct kvm_vcpu
*vcpu
)
3727 LIST_HEAD(invalid_list
);
3729 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
&&
3730 !list_empty(&vcpu
->kvm
->arch
.active_mmu_pages
)) {
3731 struct kvm_mmu_page
*sp
;
3733 sp
= container_of(vcpu
->kvm
->arch
.active_mmu_pages
.prev
,
3734 struct kvm_mmu_page
, link
);
3735 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3736 ++vcpu
->kvm
->stat
.mmu_recycled
;
3738 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3741 static bool is_mmio_page_fault(struct kvm_vcpu
*vcpu
, gva_t addr
)
3743 if (vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
))
3744 return vcpu_match_mmio_gpa(vcpu
, addr
);
3746 return vcpu_match_mmio_gva(vcpu
, addr
);
3749 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
3750 void *insn
, int insn_len
)
3752 int r
, emulation_type
= EMULTYPE_RETRY
;
3753 enum emulation_result er
;
3755 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
3764 if (is_mmio_page_fault(vcpu
, cr2
))
3767 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
3772 case EMULATE_DO_MMIO
:
3773 ++vcpu
->stat
.mmio_exits
;
3783 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
3785 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
3787 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
3788 kvm_mmu_flush_tlb(vcpu
);
3789 ++vcpu
->stat
.invlpg
;
3791 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
3793 void kvm_enable_tdp(void)
3797 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
3799 void kvm_disable_tdp(void)
3801 tdp_enabled
= false;
3803 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
3805 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
3807 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
3808 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
3809 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
3812 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
3820 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3821 * Therefore we need to allocate shadow page tables in the first
3822 * 4GB of memory, which happens to fit the DMA32 zone.
3824 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
3828 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
3829 for (i
= 0; i
< 4; ++i
)
3830 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3835 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
3838 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3840 return alloc_mmu_pages(vcpu
);
3843 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
3846 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3848 return init_kvm_mmu(vcpu
);
3851 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
3853 struct kvm_mmu_page
*sp
;
3855 list_for_each_entry(sp
, &kvm
->arch
.active_mmu_pages
, link
) {
3859 if (!test_bit(slot
, sp
->slot_bitmap
))
3863 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
) {
3864 if (!is_shadow_present_pte(pt
[i
]) ||
3865 !is_last_spte(pt
[i
], sp
->role
.level
))
3868 if (is_large_pte(pt
[i
])) {
3869 drop_spte(kvm
, &pt
[i
]);
3875 if (is_writable_pte(pt
[i
]))
3876 mmu_spte_update(&pt
[i
],
3877 pt
[i
] & ~PT_WRITABLE_MASK
);
3880 kvm_flush_remote_tlbs(kvm
);
3883 void kvm_mmu_zap_all(struct kvm
*kvm
)
3885 struct kvm_mmu_page
*sp
, *node
;
3886 LIST_HEAD(invalid_list
);
3888 spin_lock(&kvm
->mmu_lock
);
3890 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
)
3891 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
3894 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3895 spin_unlock(&kvm
->mmu_lock
);
3898 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm
*kvm
,
3899 struct list_head
*invalid_list
)
3901 struct kvm_mmu_page
*page
;
3903 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
3904 struct kvm_mmu_page
, link
);
3905 return kvm_mmu_prepare_zap_page(kvm
, page
, invalid_list
);
3908 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
3911 struct kvm
*kvm_freed
= NULL
;
3912 int nr_to_scan
= sc
->nr_to_scan
;
3914 if (nr_to_scan
== 0)
3917 raw_spin_lock(&kvm_lock
);
3919 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
3920 int idx
, freed_pages
;
3921 LIST_HEAD(invalid_list
);
3923 idx
= srcu_read_lock(&kvm
->srcu
);
3924 spin_lock(&kvm
->mmu_lock
);
3925 if (!kvm_freed
&& nr_to_scan
> 0 &&
3926 kvm
->arch
.n_used_mmu_pages
> 0) {
3927 freed_pages
= kvm_mmu_remove_some_alloc_mmu_pages(kvm
,
3933 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
3934 spin_unlock(&kvm
->mmu_lock
);
3935 srcu_read_unlock(&kvm
->srcu
, idx
);
3938 list_move_tail(&kvm_freed
->vm_list
, &vm_list
);
3940 raw_spin_unlock(&kvm_lock
);
3943 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
3946 static struct shrinker mmu_shrinker
= {
3947 .shrink
= mmu_shrink
,
3948 .seeks
= DEFAULT_SEEKS
* 10,
3951 static void mmu_destroy_caches(void)
3953 if (pte_list_desc_cache
)
3954 kmem_cache_destroy(pte_list_desc_cache
);
3955 if (mmu_page_header_cache
)
3956 kmem_cache_destroy(mmu_page_header_cache
);
3959 int kvm_mmu_module_init(void)
3961 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
3962 sizeof(struct pte_list_desc
),
3964 if (!pte_list_desc_cache
)
3967 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
3968 sizeof(struct kvm_mmu_page
),
3970 if (!mmu_page_header_cache
)
3973 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
3976 register_shrinker(&mmu_shrinker
);
3981 mmu_destroy_caches();
3986 * Caculate mmu pages needed for kvm.
3988 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
3991 unsigned int nr_mmu_pages
;
3992 unsigned int nr_pages
= 0;
3993 struct kvm_memslots
*slots
;
3995 slots
= kvm_memslots(kvm
);
3997 for (i
= 0; i
< slots
->nmemslots
; i
++)
3998 nr_pages
+= slots
->memslots
[i
].npages
;
4000 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
4001 nr_mmu_pages
= max(nr_mmu_pages
,
4002 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
4004 return nr_mmu_pages
;
4007 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer
*buffer
,
4010 if (len
> buffer
->len
)
4015 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer
*buffer
,
4020 ret
= pv_mmu_peek_buffer(buffer
, len
);
4025 buffer
->processed
+= len
;
4029 static int kvm_pv_mmu_write(struct kvm_vcpu
*vcpu
,
4030 gpa_t addr
, gpa_t value
)
4035 if (!is_long_mode(vcpu
) && !is_pae(vcpu
))
4038 r
= mmu_topup_memory_caches(vcpu
);
4042 if (!emulator_write_phys(vcpu
, addr
, &value
, bytes
))
4048 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
4050 (void)kvm_set_cr3(vcpu
, kvm_read_cr3(vcpu
));
4054 static int kvm_pv_mmu_release_pt(struct kvm_vcpu
*vcpu
, gpa_t addr
)
4056 spin_lock(&vcpu
->kvm
->mmu_lock
);
4057 mmu_unshadow(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
4058 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4062 static int kvm_pv_mmu_op_one(struct kvm_vcpu
*vcpu
,
4063 struct kvm_pv_mmu_op_buffer
*buffer
)
4065 struct kvm_mmu_op_header
*header
;
4067 header
= pv_mmu_peek_buffer(buffer
, sizeof *header
);
4070 switch (header
->op
) {
4071 case KVM_MMU_OP_WRITE_PTE
: {
4072 struct kvm_mmu_op_write_pte
*wpte
;
4074 wpte
= pv_mmu_read_buffer(buffer
, sizeof *wpte
);
4077 return kvm_pv_mmu_write(vcpu
, wpte
->pte_phys
,
4080 case KVM_MMU_OP_FLUSH_TLB
: {
4081 struct kvm_mmu_op_flush_tlb
*ftlb
;
4083 ftlb
= pv_mmu_read_buffer(buffer
, sizeof *ftlb
);
4086 return kvm_pv_mmu_flush_tlb(vcpu
);
4088 case KVM_MMU_OP_RELEASE_PT
: {
4089 struct kvm_mmu_op_release_pt
*rpt
;
4091 rpt
= pv_mmu_read_buffer(buffer
, sizeof *rpt
);
4094 return kvm_pv_mmu_release_pt(vcpu
, rpt
->pt_phys
);
4100 int kvm_pv_mmu_op(struct kvm_vcpu
*vcpu
, unsigned long bytes
,
4101 gpa_t addr
, unsigned long *ret
)
4104 struct kvm_pv_mmu_op_buffer
*buffer
= &vcpu
->arch
.mmu_op_buffer
;
4106 buffer
->ptr
= buffer
->buf
;
4107 buffer
->len
= min_t(unsigned long, bytes
, sizeof buffer
->buf
);
4108 buffer
->processed
= 0;
4110 r
= kvm_read_guest(vcpu
->kvm
, addr
, buffer
->buf
, buffer
->len
);
4114 while (buffer
->len
) {
4115 r
= kvm_pv_mmu_op_one(vcpu
, buffer
);
4124 *ret
= buffer
->processed
;
4128 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4130 struct kvm_shadow_walk_iterator iterator
;
4134 walk_shadow_page_lockless_begin(vcpu
);
4135 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4136 sptes
[iterator
.level
-1] = spte
;
4138 if (!is_shadow_present_pte(spte
))
4141 walk_shadow_page_lockless_end(vcpu
);
4145 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4147 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4151 destroy_kvm_mmu(vcpu
);
4152 free_mmu_pages(vcpu
);
4153 mmu_free_memory_caches(vcpu
);
4156 #ifdef CONFIG_KVM_MMU_AUDIT
4157 #include "mmu_audit.c"
4159 static void mmu_audit_disable(void) { }
4162 void kvm_mmu_module_exit(void)
4164 mmu_destroy_caches();
4165 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4166 unregister_shrinker(&mmu_shrinker
);
4167 mmu_audit_disable();