2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled
= false;
55 AUDIT_POST_PAGE_FAULT
,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg
, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc
{
157 u64
*sptes
[PTE_LIST_EXT
];
158 struct pte_list_desc
*more
;
161 struct kvm_shadow_walk_iterator
{
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache
*pte_list_desc_cache
;
181 static struct kmem_cache
*mmu_page_header_cache
;
182 static struct percpu_counter kvm_total_used_mmu_pages
;
184 static u64 __read_mostly shadow_nx_mask
;
185 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask
;
187 static u64 __read_mostly shadow_accessed_mask
;
188 static u64 __read_mostly shadow_dirty_mask
;
189 static u64 __read_mostly shadow_mmio_mask
;
191 static void mmu_spte_set(u64
*sptep
, u64 spte
);
192 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
196 shadow_mmio_mask
= mmio_mask
;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
200 static void mark_mmio_spte(u64
*sptep
, u64 gfn
, unsigned access
)
202 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
204 trace_mark_mmio_spte(sptep
, gfn
, access
);
205 mmu_spte_set(sptep
, shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
);
208 static bool is_mmio_spte(u64 spte
)
210 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
213 static gfn_t
get_mmio_spte_gfn(u64 spte
)
215 return (spte
& ~shadow_mmio_mask
) >> PAGE_SHIFT
;
218 static unsigned get_mmio_spte_access(u64 spte
)
220 return (spte
& ~shadow_mmio_mask
) & ~PAGE_MASK
;
223 static bool set_mmio_spte(u64
*sptep
, gfn_t gfn
, pfn_t pfn
, unsigned access
)
225 if (unlikely(is_noslot_pfn(pfn
))) {
226 mark_mmio_spte(sptep
, gfn
, access
);
233 static inline u64
rsvd_bits(int s
, int e
)
235 return ((1ULL << (e
- s
+ 1)) - 1) << s
;
238 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
239 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
241 shadow_user_mask
= user_mask
;
242 shadow_accessed_mask
= accessed_mask
;
243 shadow_dirty_mask
= dirty_mask
;
244 shadow_nx_mask
= nx_mask
;
245 shadow_x_mask
= x_mask
;
247 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
249 static int is_cpuid_PSE36(void)
254 static int is_nx(struct kvm_vcpu
*vcpu
)
256 return vcpu
->arch
.efer
& EFER_NX
;
259 static int is_shadow_present_pte(u64 pte
)
261 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
264 static int is_large_pte(u64 pte
)
266 return pte
& PT_PAGE_SIZE_MASK
;
269 static int is_dirty_gpte(unsigned long pte
)
271 return pte
& PT_DIRTY_MASK
;
274 static int is_rmap_spte(u64 pte
)
276 return is_shadow_present_pte(pte
);
279 static int is_last_spte(u64 pte
, int level
)
281 if (level
== PT_PAGE_TABLE_LEVEL
)
283 if (is_large_pte(pte
))
288 static pfn_t
spte_to_pfn(u64 pte
)
290 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
293 static gfn_t
pse36_gfn_delta(u32 gpte
)
295 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
297 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
301 static void __set_spte(u64
*sptep
, u64 spte
)
306 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
311 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
313 return xchg(sptep
, spte
);
316 static u64
__get_spte_lockless(u64
*sptep
)
318 return ACCESS_ONCE(*sptep
);
321 static bool __check_direct_spte_mmio_pf(u64 spte
)
323 /* It is valid if the spte is zapped. */
335 static void count_spte_clear(u64
*sptep
, u64 spte
)
337 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
339 if (is_shadow_present_pte(spte
))
342 /* Ensure the spte is completely set before we increase the count */
344 sp
->clear_spte_count
++;
347 static void __set_spte(u64
*sptep
, u64 spte
)
349 union split_spte
*ssptep
, sspte
;
351 ssptep
= (union split_spte
*)sptep
;
352 sspte
= (union split_spte
)spte
;
354 ssptep
->spte_high
= sspte
.spte_high
;
357 * If we map the spte from nonpresent to present, We should store
358 * the high bits firstly, then set present bit, so cpu can not
359 * fetch this spte while we are setting the spte.
363 ssptep
->spte_low
= sspte
.spte_low
;
366 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
368 union split_spte
*ssptep
, sspte
;
370 ssptep
= (union split_spte
*)sptep
;
371 sspte
= (union split_spte
)spte
;
373 ssptep
->spte_low
= sspte
.spte_low
;
376 * If we map the spte from present to nonpresent, we should clear
377 * present bit firstly to avoid vcpu fetch the old high bits.
381 ssptep
->spte_high
= sspte
.spte_high
;
382 count_spte_clear(sptep
, spte
);
385 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
387 union split_spte
*ssptep
, sspte
, orig
;
389 ssptep
= (union split_spte
*)sptep
;
390 sspte
= (union split_spte
)spte
;
392 /* xchg acts as a barrier before the setting of the high bits */
393 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
394 orig
.spte_high
= ssptep
->spte_high
;
395 ssptep
->spte_high
= sspte
.spte_high
;
396 count_spte_clear(sptep
, spte
);
402 * The idea using the light way get the spte on x86_32 guest is from
403 * gup_get_pte(arch/x86/mm/gup.c).
404 * The difference is we can not catch the spte tlb flush if we leave
405 * guest mode, so we emulate it by increase clear_spte_count when spte
408 static u64
__get_spte_lockless(u64
*sptep
)
410 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
411 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
415 count
= sp
->clear_spte_count
;
418 spte
.spte_low
= orig
->spte_low
;
421 spte
.spte_high
= orig
->spte_high
;
424 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
425 count
!= sp
->clear_spte_count
))
431 static bool __check_direct_spte_mmio_pf(u64 spte
)
433 union split_spte sspte
= (union split_spte
)spte
;
434 u32 high_mmio_mask
= shadow_mmio_mask
>> 32;
436 /* It is valid if the spte is zapped. */
440 /* It is valid if the spte is being zapped. */
441 if (sspte
.spte_low
== 0ull &&
442 (sspte
.spte_high
& high_mmio_mask
) == high_mmio_mask
)
449 static bool spte_is_locklessly_modifiable(u64 spte
)
451 return !(~spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
));
454 static bool spte_has_volatile_bits(u64 spte
)
457 * Always atomicly update spte if it can be updated
458 * out of mmu-lock, it can ensure dirty bit is not lost,
459 * also, it can help us to get a stable is_writable_pte()
460 * to ensure tlb flush is not missed.
462 if (spte_is_locklessly_modifiable(spte
))
465 if (!shadow_accessed_mask
)
468 if (!is_shadow_present_pte(spte
))
471 if ((spte
& shadow_accessed_mask
) &&
472 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
478 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
480 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
483 /* Rules for using mmu_spte_set:
484 * Set the sptep from nonpresent to present.
485 * Note: the sptep being assigned *must* be either not present
486 * or in a state where the hardware will not attempt to update
489 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
491 WARN_ON(is_shadow_present_pte(*sptep
));
492 __set_spte(sptep
, new_spte
);
495 /* Rules for using mmu_spte_update:
496 * Update the state bits, it means the mapped pfn is not changged.
498 * Whenever we overwrite a writable spte with a read-only one we
499 * should flush remote TLBs. Otherwise rmap_write_protect
500 * will find a read-only spte, even though the writable spte
501 * might be cached on a CPU's TLB, the return value indicates this
504 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
506 u64 old_spte
= *sptep
;
509 WARN_ON(!is_rmap_spte(new_spte
));
511 if (!is_shadow_present_pte(old_spte
)) {
512 mmu_spte_set(sptep
, new_spte
);
516 if (!spte_has_volatile_bits(old_spte
))
517 __update_clear_spte_fast(sptep
, new_spte
);
519 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
522 * For the spte updated out of mmu-lock is safe, since
523 * we always atomicly update it, see the comments in
524 * spte_has_volatile_bits().
526 if (is_writable_pte(old_spte
) && !is_writable_pte(new_spte
))
529 if (!shadow_accessed_mask
)
532 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
533 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
534 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
535 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
541 * Rules for using mmu_spte_clear_track_bits:
542 * It sets the sptep from present to nonpresent, and track the
543 * state bits, it is used to clear the last level sptep.
545 static int mmu_spte_clear_track_bits(u64
*sptep
)
548 u64 old_spte
= *sptep
;
550 if (!spte_has_volatile_bits(old_spte
))
551 __update_clear_spte_fast(sptep
, 0ull);
553 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
555 if (!is_rmap_spte(old_spte
))
558 pfn
= spte_to_pfn(old_spte
);
561 * KVM does not hold the refcount of the page used by
562 * kvm mmu, before reclaiming the page, we should
563 * unmap it from mmu first.
565 WARN_ON(!kvm_is_mmio_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
567 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
568 kvm_set_pfn_accessed(pfn
);
569 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
570 kvm_set_pfn_dirty(pfn
);
575 * Rules for using mmu_spte_clear_no_track:
576 * Directly clear spte without caring the state bits of sptep,
577 * it is used to set the upper level spte.
579 static void mmu_spte_clear_no_track(u64
*sptep
)
581 __update_clear_spte_fast(sptep
, 0ull);
584 static u64
mmu_spte_get_lockless(u64
*sptep
)
586 return __get_spte_lockless(sptep
);
589 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
592 * Prevent page table teardown by making any free-er wait during
593 * kvm_flush_remote_tlbs() IPI to all active vcpus.
596 vcpu
->mode
= READING_SHADOW_PAGE_TABLES
;
598 * Make sure a following spte read is not reordered ahead of the write
604 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
607 * Make sure the write to vcpu->mode is not reordered in front of
608 * reads to sptes. If it does, kvm_commit_zap_page() can see us
609 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
612 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
616 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
617 struct kmem_cache
*base_cache
, int min
)
621 if (cache
->nobjs
>= min
)
623 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
624 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
627 cache
->objects
[cache
->nobjs
++] = obj
;
632 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
637 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
638 struct kmem_cache
*cache
)
641 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
644 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
649 if (cache
->nobjs
>= min
)
651 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
652 page
= (void *)__get_free_page(GFP_KERNEL
);
655 cache
->objects
[cache
->nobjs
++] = page
;
660 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
663 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
666 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
670 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
671 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
674 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
677 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
678 mmu_page_header_cache
, 4);
683 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
685 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
686 pte_list_desc_cache
);
687 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
688 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
689 mmu_page_header_cache
);
692 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
697 p
= mc
->objects
[--mc
->nobjs
];
701 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
703 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
706 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
708 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
711 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
713 if (!sp
->role
.direct
)
714 return sp
->gfns
[index
];
716 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
719 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
722 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
724 sp
->gfns
[index
] = gfn
;
728 * Return the pointer to the large page information for a given gfn,
729 * handling slots that are not large page aligned.
731 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
732 struct kvm_memory_slot
*slot
,
737 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
738 return &slot
->arch
.lpage_info
[level
- 2][idx
];
741 static void account_shadowed(struct kvm
*kvm
, gfn_t gfn
)
743 struct kvm_memory_slot
*slot
;
744 struct kvm_lpage_info
*linfo
;
747 slot
= gfn_to_memslot(kvm
, gfn
);
748 for (i
= PT_DIRECTORY_LEVEL
;
749 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
750 linfo
= lpage_info_slot(gfn
, slot
, i
);
751 linfo
->write_count
+= 1;
753 kvm
->arch
.indirect_shadow_pages
++;
756 static void unaccount_shadowed(struct kvm
*kvm
, gfn_t gfn
)
758 struct kvm_memory_slot
*slot
;
759 struct kvm_lpage_info
*linfo
;
762 slot
= gfn_to_memslot(kvm
, gfn
);
763 for (i
= PT_DIRECTORY_LEVEL
;
764 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
765 linfo
= lpage_info_slot(gfn
, slot
, i
);
766 linfo
->write_count
-= 1;
767 WARN_ON(linfo
->write_count
< 0);
769 kvm
->arch
.indirect_shadow_pages
--;
772 static int has_wrprotected_page(struct kvm
*kvm
,
776 struct kvm_memory_slot
*slot
;
777 struct kvm_lpage_info
*linfo
;
779 slot
= gfn_to_memslot(kvm
, gfn
);
781 linfo
= lpage_info_slot(gfn
, slot
, level
);
782 return linfo
->write_count
;
788 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
790 unsigned long page_size
;
793 page_size
= kvm_host_page_size(kvm
, gfn
);
795 for (i
= PT_PAGE_TABLE_LEVEL
;
796 i
< (PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
); ++i
) {
797 if (page_size
>= KVM_HPAGE_SIZE(i
))
806 static struct kvm_memory_slot
*
807 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
810 struct kvm_memory_slot
*slot
;
812 slot
= gfn_to_memslot(vcpu
->kvm
, gfn
);
813 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
||
814 (no_dirty_log
&& slot
->dirty_bitmap
))
820 static bool mapping_level_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
822 return !gfn_to_memslot_dirty_bitmap(vcpu
, large_gfn
, true);
825 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
)
827 int host_level
, level
, max_level
;
829 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
831 if (host_level
== PT_PAGE_TABLE_LEVEL
)
834 max_level
= kvm_x86_ops
->get_lpage_level() < host_level
?
835 kvm_x86_ops
->get_lpage_level() : host_level
;
837 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
838 if (has_wrprotected_page(vcpu
->kvm
, large_gfn
, level
))
845 * Pte mapping structures:
847 * If pte_list bit zero is zero, then pte_list point to the spte.
849 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
850 * pte_list_desc containing more mappings.
852 * Returns the number of pte entries before the spte was added or zero if
853 * the spte was not added.
856 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
857 unsigned long *pte_list
)
859 struct pte_list_desc
*desc
;
863 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
864 *pte_list
= (unsigned long)spte
;
865 } else if (!(*pte_list
& 1)) {
866 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
867 desc
= mmu_alloc_pte_list_desc(vcpu
);
868 desc
->sptes
[0] = (u64
*)*pte_list
;
869 desc
->sptes
[1] = spte
;
870 *pte_list
= (unsigned long)desc
| 1;
873 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
874 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
875 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
877 count
+= PTE_LIST_EXT
;
879 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
880 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
883 for (i
= 0; desc
->sptes
[i
]; ++i
)
885 desc
->sptes
[i
] = spte
;
891 pte_list_desc_remove_entry(unsigned long *pte_list
, struct pte_list_desc
*desc
,
892 int i
, struct pte_list_desc
*prev_desc
)
896 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
898 desc
->sptes
[i
] = desc
->sptes
[j
];
899 desc
->sptes
[j
] = NULL
;
902 if (!prev_desc
&& !desc
->more
)
903 *pte_list
= (unsigned long)desc
->sptes
[0];
906 prev_desc
->more
= desc
->more
;
908 *pte_list
= (unsigned long)desc
->more
| 1;
909 mmu_free_pte_list_desc(desc
);
912 static void pte_list_remove(u64
*spte
, unsigned long *pte_list
)
914 struct pte_list_desc
*desc
;
915 struct pte_list_desc
*prev_desc
;
919 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
921 } else if (!(*pte_list
& 1)) {
922 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
923 if ((u64
*)*pte_list
!= spte
) {
924 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
929 rmap_printk("pte_list_remove: %p many->many\n", spte
);
930 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
933 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
934 if (desc
->sptes
[i
] == spte
) {
935 pte_list_desc_remove_entry(pte_list
,
943 pr_err("pte_list_remove: %p many->many\n", spte
);
948 typedef void (*pte_list_walk_fn
) (u64
*spte
);
949 static void pte_list_walk(unsigned long *pte_list
, pte_list_walk_fn fn
)
951 struct pte_list_desc
*desc
;
957 if (!(*pte_list
& 1))
958 return fn((u64
*)*pte_list
);
960 desc
= (struct pte_list_desc
*)(*pte_list
& ~1ul);
962 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
)
968 static unsigned long *__gfn_to_rmap(gfn_t gfn
, int level
,
969 struct kvm_memory_slot
*slot
)
973 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
974 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
978 * Take gfn and return the reverse mapping to it.
980 static unsigned long *gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
, int level
)
982 struct kvm_memory_slot
*slot
;
984 slot
= gfn_to_memslot(kvm
, gfn
);
985 return __gfn_to_rmap(gfn
, level
, slot
);
988 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
990 struct kvm_mmu_memory_cache
*cache
;
992 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
993 return mmu_memory_cache_free_objects(cache
);
996 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
998 struct kvm_mmu_page
*sp
;
999 unsigned long *rmapp
;
1001 sp
= page_header(__pa(spte
));
1002 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1003 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1004 return pte_list_add(vcpu
, spte
, rmapp
);
1007 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1009 struct kvm_mmu_page
*sp
;
1011 unsigned long *rmapp
;
1013 sp
= page_header(__pa(spte
));
1014 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1015 rmapp
= gfn_to_rmap(kvm
, gfn
, sp
->role
.level
);
1016 pte_list_remove(spte
, rmapp
);
1020 * Used by the following functions to iterate through the sptes linked by a
1021 * rmap. All fields are private and not assumed to be used outside.
1023 struct rmap_iterator
{
1024 /* private fields */
1025 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1026 int pos
; /* index of the sptep */
1030 * Iteration must be started by this function. This should also be used after
1031 * removing/dropping sptes from the rmap link because in such cases the
1032 * information in the itererator may not be valid.
1034 * Returns sptep if found, NULL otherwise.
1036 static u64
*rmap_get_first(unsigned long rmap
, struct rmap_iterator
*iter
)
1046 iter
->desc
= (struct pte_list_desc
*)(rmap
& ~1ul);
1048 return iter
->desc
->sptes
[iter
->pos
];
1052 * Must be used with a valid iterator: e.g. after rmap_get_first().
1054 * Returns sptep if found, NULL otherwise.
1056 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1059 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1063 sptep
= iter
->desc
->sptes
[iter
->pos
];
1068 iter
->desc
= iter
->desc
->more
;
1072 /* desc->sptes[0] cannot be NULL */
1073 return iter
->desc
->sptes
[iter
->pos
];
1080 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1082 if (mmu_spte_clear_track_bits(sptep
))
1083 rmap_remove(kvm
, sptep
);
1087 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1089 if (is_large_pte(*sptep
)) {
1090 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1091 PT_PAGE_TABLE_LEVEL
);
1092 drop_spte(kvm
, sptep
);
1100 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1102 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1103 kvm_flush_remote_tlbs(vcpu
->kvm
);
1107 * Write-protect on the specified @sptep, @pt_protect indicates whether
1108 * spte writ-protection is caused by protecting shadow page table.
1109 * @flush indicates whether tlb need be flushed.
1111 * Note: write protection is difference between drity logging and spte
1113 * - for dirty logging, the spte can be set to writable at anytime if
1114 * its dirty bitmap is properly set.
1115 * - for spte protection, the spte can be writable only after unsync-ing
1118 * Return true if the spte is dropped.
1121 spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool *flush
, bool pt_protect
)
1125 if (!is_writable_pte(spte
) &&
1126 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1129 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1131 if (__drop_large_spte(kvm
, sptep
)) {
1137 spte
&= ~SPTE_MMU_WRITEABLE
;
1138 spte
= spte
& ~PT_WRITABLE_MASK
;
1140 *flush
|= mmu_spte_update(sptep
, spte
);
1144 static bool __rmap_write_protect(struct kvm
*kvm
, unsigned long *rmapp
,
1148 struct rmap_iterator iter
;
1151 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1152 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1153 if (spte_write_protect(kvm
, sptep
, &flush
, pt_protect
)) {
1154 sptep
= rmap_get_first(*rmapp
, &iter
);
1158 sptep
= rmap_get_next(&iter
);
1165 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1166 * @kvm: kvm instance
1167 * @slot: slot to protect
1168 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1169 * @mask: indicates which pages we should protect
1171 * Used when we do not need to care about huge page mappings: e.g. during dirty
1172 * logging we do not have any such mappings.
1174 void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1175 struct kvm_memory_slot
*slot
,
1176 gfn_t gfn_offset
, unsigned long mask
)
1178 unsigned long *rmapp
;
1181 rmapp
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1182 PT_PAGE_TABLE_LEVEL
, slot
);
1183 __rmap_write_protect(kvm
, rmapp
, false);
1185 /* clear the first set bit */
1190 static bool rmap_write_protect(struct kvm
*kvm
, u64 gfn
)
1192 struct kvm_memory_slot
*slot
;
1193 unsigned long *rmapp
;
1195 bool write_protected
= false;
1197 slot
= gfn_to_memslot(kvm
, gfn
);
1199 for (i
= PT_PAGE_TABLE_LEVEL
;
1200 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
1201 rmapp
= __gfn_to_rmap(gfn
, i
, slot
);
1202 write_protected
|= __rmap_write_protect(kvm
, rmapp
, true);
1205 return write_protected
;
1208 static int kvm_unmap_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1209 struct kvm_memory_slot
*slot
, unsigned long data
)
1212 struct rmap_iterator iter
;
1213 int need_tlb_flush
= 0;
1215 while ((sptep
= rmap_get_first(*rmapp
, &iter
))) {
1216 BUG_ON(!(*sptep
& PT_PRESENT_MASK
));
1217 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep
, *sptep
);
1219 drop_spte(kvm
, sptep
);
1223 return need_tlb_flush
;
1226 static int kvm_set_pte_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1227 struct kvm_memory_slot
*slot
, unsigned long data
)
1230 struct rmap_iterator iter
;
1233 pte_t
*ptep
= (pte_t
*)data
;
1236 WARN_ON(pte_huge(*ptep
));
1237 new_pfn
= pte_pfn(*ptep
);
1239 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;) {
1240 BUG_ON(!is_shadow_present_pte(*sptep
));
1241 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep
, *sptep
);
1245 if (pte_write(*ptep
)) {
1246 drop_spte(kvm
, sptep
);
1247 sptep
= rmap_get_first(*rmapp
, &iter
);
1249 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1250 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1252 new_spte
&= ~PT_WRITABLE_MASK
;
1253 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1254 new_spte
&= ~shadow_accessed_mask
;
1256 mmu_spte_clear_track_bits(sptep
);
1257 mmu_spte_set(sptep
, new_spte
);
1258 sptep
= rmap_get_next(&iter
);
1263 kvm_flush_remote_tlbs(kvm
);
1268 static int kvm_handle_hva_range(struct kvm
*kvm
,
1269 unsigned long start
,
1272 int (*handler
)(struct kvm
*kvm
,
1273 unsigned long *rmapp
,
1274 struct kvm_memory_slot
*slot
,
1275 unsigned long data
))
1279 struct kvm_memslots
*slots
;
1280 struct kvm_memory_slot
*memslot
;
1282 slots
= kvm_memslots(kvm
);
1284 kvm_for_each_memslot(memslot
, slots
) {
1285 unsigned long hva_start
, hva_end
;
1286 gfn_t gfn_start
, gfn_end
;
1288 hva_start
= max(start
, memslot
->userspace_addr
);
1289 hva_end
= min(end
, memslot
->userspace_addr
+
1290 (memslot
->npages
<< PAGE_SHIFT
));
1291 if (hva_start
>= hva_end
)
1294 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1295 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1297 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1298 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1300 for (j
= PT_PAGE_TABLE_LEVEL
;
1301 j
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++j
) {
1302 unsigned long idx
, idx_end
;
1303 unsigned long *rmapp
;
1306 * {idx(page_j) | page_j intersects with
1307 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1309 idx
= gfn_to_index(gfn_start
, memslot
->base_gfn
, j
);
1310 idx_end
= gfn_to_index(gfn_end
- 1, memslot
->base_gfn
, j
);
1312 rmapp
= __gfn_to_rmap(gfn_start
, j
, memslot
);
1314 for (; idx
<= idx_end
; ++idx
)
1315 ret
|= handler(kvm
, rmapp
++, memslot
, data
);
1322 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1324 int (*handler
)(struct kvm
*kvm
, unsigned long *rmapp
,
1325 struct kvm_memory_slot
*slot
,
1326 unsigned long data
))
1328 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1331 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1333 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1336 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1338 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1341 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1343 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1346 static int kvm_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1347 struct kvm_memory_slot
*slot
, unsigned long data
)
1350 struct rmap_iterator
uninitialized_var(iter
);
1354 * In case of absence of EPT Access and Dirty Bits supports,
1355 * emulate the accessed bit for EPT, by checking if this page has
1356 * an EPT mapping, and clearing it if it does. On the next access,
1357 * a new EPT mapping will be established.
1358 * This has some overhead, but not as much as the cost of swapping
1359 * out actively used pages or breaking up actively used hugepages.
1361 if (!shadow_accessed_mask
) {
1362 young
= kvm_unmap_rmapp(kvm
, rmapp
, slot
, data
);
1366 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1367 sptep
= rmap_get_next(&iter
)) {
1368 BUG_ON(!is_shadow_present_pte(*sptep
));
1370 if (*sptep
& shadow_accessed_mask
) {
1372 clear_bit((ffs(shadow_accessed_mask
) - 1),
1373 (unsigned long *)sptep
);
1377 /* @data has hva passed to kvm_age_hva(). */
1378 trace_kvm_age_page(data
, slot
, young
);
1382 static int kvm_test_age_rmapp(struct kvm
*kvm
, unsigned long *rmapp
,
1383 struct kvm_memory_slot
*slot
, unsigned long data
)
1386 struct rmap_iterator iter
;
1390 * If there's no access bit in the secondary pte set by the
1391 * hardware it's up to gup-fast/gup to set the access bit in
1392 * the primary pte or in the page structure.
1394 if (!shadow_accessed_mask
)
1397 for (sptep
= rmap_get_first(*rmapp
, &iter
); sptep
;
1398 sptep
= rmap_get_next(&iter
)) {
1399 BUG_ON(!is_shadow_present_pte(*sptep
));
1401 if (*sptep
& shadow_accessed_mask
) {
1410 #define RMAP_RECYCLE_THRESHOLD 1000
1412 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1414 unsigned long *rmapp
;
1415 struct kvm_mmu_page
*sp
;
1417 sp
= page_header(__pa(spte
));
1419 rmapp
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
->role
.level
);
1421 kvm_unmap_rmapp(vcpu
->kvm
, rmapp
, NULL
, 0);
1422 kvm_flush_remote_tlbs(vcpu
->kvm
);
1425 int kvm_age_hva(struct kvm
*kvm
, unsigned long hva
)
1427 return kvm_handle_hva(kvm
, hva
, hva
, kvm_age_rmapp
);
1430 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1432 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1436 static int is_empty_shadow_page(u64
*spt
)
1441 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1442 if (is_shadow_present_pte(*pos
)) {
1443 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1452 * This value is the sum of all of the kvm instances's
1453 * kvm->arch.n_used_mmu_pages values. We need a global,
1454 * aggregate version in order to make the slab shrinker
1457 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1459 kvm
->arch
.n_used_mmu_pages
+= nr
;
1460 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1464 * Remove the sp from shadow page cache, after call it,
1465 * we can not find this sp from the cache, and the shadow
1466 * page table is still valid.
1467 * It should be under the protection of mmu lock.
1469 static void kvm_mmu_isolate_page(struct kvm_mmu_page
*sp
)
1471 ASSERT(is_empty_shadow_page(sp
->spt
));
1472 hlist_del(&sp
->hash_link
);
1473 if (!sp
->role
.direct
)
1474 free_page((unsigned long)sp
->gfns
);
1478 * Free the shadow page table and the sp, we can do it
1479 * out of the protection of mmu lock.
1481 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1483 list_del(&sp
->link
);
1484 free_page((unsigned long)sp
->spt
);
1485 kmem_cache_free(mmu_page_header_cache
, sp
);
1488 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1490 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1493 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1494 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1499 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1502 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1505 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1508 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1511 mmu_page_remove_parent_pte(sp
, parent_pte
);
1512 mmu_spte_clear_no_track(parent_pte
);
1515 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
,
1516 u64
*parent_pte
, int direct
)
1518 struct kvm_mmu_page
*sp
;
1519 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1520 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1522 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1523 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1524 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1525 bitmap_zero(sp
->slot_bitmap
, KVM_MEM_SLOTS_NUM
);
1526 sp
->parent_ptes
= 0;
1527 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1528 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1532 static void mark_unsync(u64
*spte
);
1533 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1535 pte_list_walk(&sp
->parent_ptes
, mark_unsync
);
1538 static void mark_unsync(u64
*spte
)
1540 struct kvm_mmu_page
*sp
;
1543 sp
= page_header(__pa(spte
));
1544 index
= spte
- sp
->spt
;
1545 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1547 if (sp
->unsync_children
++)
1549 kvm_mmu_mark_parents_unsync(sp
);
1552 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1553 struct kvm_mmu_page
*sp
)
1558 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1562 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1563 struct kvm_mmu_page
*sp
, u64
*spte
,
1569 #define KVM_PAGE_ARRAY_NR 16
1571 struct kvm_mmu_pages
{
1572 struct mmu_page_and_offset
{
1573 struct kvm_mmu_page
*sp
;
1575 } page
[KVM_PAGE_ARRAY_NR
];
1579 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1585 for (i
=0; i
< pvec
->nr
; i
++)
1586 if (pvec
->page
[i
].sp
== sp
)
1589 pvec
->page
[pvec
->nr
].sp
= sp
;
1590 pvec
->page
[pvec
->nr
].idx
= idx
;
1592 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1595 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1596 struct kvm_mmu_pages
*pvec
)
1598 int i
, ret
, nr_unsync_leaf
= 0;
1600 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1601 struct kvm_mmu_page
*child
;
1602 u64 ent
= sp
->spt
[i
];
1604 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
))
1605 goto clear_child_bitmap
;
1607 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1609 if (child
->unsync_children
) {
1610 if (mmu_pages_add(pvec
, child
, i
))
1613 ret
= __mmu_unsync_walk(child
, pvec
);
1615 goto clear_child_bitmap
;
1617 nr_unsync_leaf
+= ret
;
1620 } else if (child
->unsync
) {
1622 if (mmu_pages_add(pvec
, child
, i
))
1625 goto clear_child_bitmap
;
1630 __clear_bit(i
, sp
->unsync_child_bitmap
);
1631 sp
->unsync_children
--;
1632 WARN_ON((int)sp
->unsync_children
< 0);
1636 return nr_unsync_leaf
;
1639 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1640 struct kvm_mmu_pages
*pvec
)
1642 if (!sp
->unsync_children
)
1645 mmu_pages_add(pvec
, sp
, 0);
1646 return __mmu_unsync_walk(sp
, pvec
);
1649 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1651 WARN_ON(!sp
->unsync
);
1652 trace_kvm_mmu_sync_page(sp
);
1654 --kvm
->stat
.mmu_unsync
;
1657 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1658 struct list_head
*invalid_list
);
1659 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1660 struct list_head
*invalid_list
);
1662 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1663 hlist_for_each_entry(sp, pos, \
1664 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1665 if ((sp)->gfn != (gfn)) {} else
1667 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1668 hlist_for_each_entry(sp, pos, \
1669 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1670 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1671 (sp)->role.invalid) {} else
1673 /* @sp->gfn should be write-protected at the call site */
1674 static int __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1675 struct list_head
*invalid_list
, bool clear_unsync
)
1677 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1678 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1683 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1685 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
)) {
1686 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1690 kvm_mmu_flush_tlb(vcpu
);
1694 static int kvm_sync_page_transient(struct kvm_vcpu
*vcpu
,
1695 struct kvm_mmu_page
*sp
)
1697 LIST_HEAD(invalid_list
);
1700 ret
= __kvm_sync_page(vcpu
, sp
, &invalid_list
, false);
1702 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1707 #ifdef CONFIG_KVM_MMU_AUDIT
1708 #include "mmu_audit.c"
1710 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1711 static void mmu_audit_disable(void) { }
1714 static int kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1715 struct list_head
*invalid_list
)
1717 return __kvm_sync_page(vcpu
, sp
, invalid_list
, true);
1720 /* @gfn should be write-protected at the call site */
1721 static void kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
1723 struct kvm_mmu_page
*s
;
1724 struct hlist_node
*node
;
1725 LIST_HEAD(invalid_list
);
1728 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
1732 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1733 kvm_unlink_unsync_page(vcpu
->kvm
, s
);
1734 if ((s
->role
.cr4_pae
!= !!is_pae(vcpu
)) ||
1735 (vcpu
->arch
.mmu
.sync_page(vcpu
, s
))) {
1736 kvm_mmu_prepare_zap_page(vcpu
->kvm
, s
, &invalid_list
);
1742 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1744 kvm_mmu_flush_tlb(vcpu
);
1747 struct mmu_page_path
{
1748 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
-1];
1749 unsigned int idx
[PT64_ROOT_LEVEL
-1];
1752 #define for_each_sp(pvec, sp, parents, i) \
1753 for (i = mmu_pages_next(&pvec, &parents, -1), \
1754 sp = pvec.page[i].sp; \
1755 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1756 i = mmu_pages_next(&pvec, &parents, i))
1758 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1759 struct mmu_page_path
*parents
,
1764 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1765 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1767 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
) {
1768 parents
->idx
[0] = pvec
->page
[n
].idx
;
1772 parents
->parent
[sp
->role
.level
-2] = sp
;
1773 parents
->idx
[sp
->role
.level
-1] = pvec
->page
[n
].idx
;
1779 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
1781 struct kvm_mmu_page
*sp
;
1782 unsigned int level
= 0;
1785 unsigned int idx
= parents
->idx
[level
];
1787 sp
= parents
->parent
[level
];
1791 --sp
->unsync_children
;
1792 WARN_ON((int)sp
->unsync_children
< 0);
1793 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1795 } while (level
< PT64_ROOT_LEVEL
-1 && !sp
->unsync_children
);
1798 static void kvm_mmu_pages_init(struct kvm_mmu_page
*parent
,
1799 struct mmu_page_path
*parents
,
1800 struct kvm_mmu_pages
*pvec
)
1802 parents
->parent
[parent
->role
.level
-1] = NULL
;
1806 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
1807 struct kvm_mmu_page
*parent
)
1810 struct kvm_mmu_page
*sp
;
1811 struct mmu_page_path parents
;
1812 struct kvm_mmu_pages pages
;
1813 LIST_HEAD(invalid_list
);
1815 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1816 while (mmu_unsync_walk(parent
, &pages
)) {
1817 bool protected = false;
1819 for_each_sp(pages
, sp
, parents
, i
)
1820 protected |= rmap_write_protect(vcpu
->kvm
, sp
->gfn
);
1823 kvm_flush_remote_tlbs(vcpu
->kvm
);
1825 for_each_sp(pages
, sp
, parents
, i
) {
1826 kvm_sync_page(vcpu
, sp
, &invalid_list
);
1827 mmu_pages_clear_parents(&parents
);
1829 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
1830 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
1831 kvm_mmu_pages_init(parent
, &parents
, &pages
);
1835 static void init_shadow_page_table(struct kvm_mmu_page
*sp
)
1839 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
1843 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
1845 sp
->write_flooding_count
= 0;
1848 static void clear_sp_write_flooding_count(u64
*spte
)
1850 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
1852 __clear_sp_write_flooding_count(sp
);
1855 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
1863 union kvm_mmu_page_role role
;
1865 struct kvm_mmu_page
*sp
;
1866 struct hlist_node
*node
;
1867 bool need_sync
= false;
1869 role
= vcpu
->arch
.mmu
.base_role
;
1871 role
.direct
= direct
;
1874 role
.access
= access
;
1875 if (!vcpu
->arch
.mmu
.direct_map
1876 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
1877 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
1878 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
1879 role
.quadrant
= quadrant
;
1881 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
, node
) {
1882 if (!need_sync
&& sp
->unsync
)
1885 if (sp
->role
.word
!= role
.word
)
1888 if (sp
->unsync
&& kvm_sync_page_transient(vcpu
, sp
))
1891 mmu_page_add_parent_pte(vcpu
, sp
, parent_pte
);
1892 if (sp
->unsync_children
) {
1893 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
1894 kvm_mmu_mark_parents_unsync(sp
);
1895 } else if (sp
->unsync
)
1896 kvm_mmu_mark_parents_unsync(sp
);
1898 __clear_sp_write_flooding_count(sp
);
1899 trace_kvm_mmu_get_page(sp
, false);
1902 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
1903 sp
= kvm_mmu_alloc_page(vcpu
, parent_pte
, direct
);
1908 hlist_add_head(&sp
->hash_link
,
1909 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
1911 if (rmap_write_protect(vcpu
->kvm
, gfn
))
1912 kvm_flush_remote_tlbs(vcpu
->kvm
);
1913 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
1914 kvm_sync_pages(vcpu
, gfn
);
1916 account_shadowed(vcpu
->kvm
, gfn
);
1918 init_shadow_page_table(sp
);
1919 trace_kvm_mmu_get_page(sp
, true);
1923 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
1924 struct kvm_vcpu
*vcpu
, u64 addr
)
1926 iterator
->addr
= addr
;
1927 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
1928 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
1930 if (iterator
->level
== PT64_ROOT_LEVEL
&&
1931 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
1932 !vcpu
->arch
.mmu
.direct_map
)
1935 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
1936 iterator
->shadow_addr
1937 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
1938 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
1940 if (!iterator
->shadow_addr
)
1941 iterator
->level
= 0;
1945 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
1947 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
1950 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
1951 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
1955 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
1958 if (is_last_spte(spte
, iterator
->level
)) {
1959 iterator
->level
= 0;
1963 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
1967 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
1969 return __shadow_walk_next(iterator
, *iterator
->sptep
);
1972 static void link_shadow_page(u64
*sptep
, struct kvm_mmu_page
*sp
)
1976 spte
= __pa(sp
->spt
)
1977 | PT_PRESENT_MASK
| PT_ACCESSED_MASK
1978 | PT_WRITABLE_MASK
| PT_USER_MASK
;
1979 mmu_spte_set(sptep
, spte
);
1982 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
1983 unsigned direct_access
)
1985 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
1986 struct kvm_mmu_page
*child
;
1989 * For the direct sp, if the guest pte's dirty bit
1990 * changed form clean to dirty, it will corrupt the
1991 * sp's access: allow writable in the read-only sp,
1992 * so we should update the spte at this point to get
1993 * a new sp with the correct access.
1995 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
1996 if (child
->role
.access
== direct_access
)
1999 drop_parent_pte(child
, sptep
);
2000 kvm_flush_remote_tlbs(vcpu
->kvm
);
2004 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2008 struct kvm_mmu_page
*child
;
2011 if (is_shadow_present_pte(pte
)) {
2012 if (is_last_spte(pte
, sp
->role
.level
)) {
2013 drop_spte(kvm
, spte
);
2014 if (is_large_pte(pte
))
2017 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2018 drop_parent_pte(child
, spte
);
2023 if (is_mmio_spte(pte
))
2024 mmu_spte_clear_no_track(spte
);
2029 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2030 struct kvm_mmu_page
*sp
)
2034 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2035 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2038 static void kvm_mmu_put_page(struct kvm_mmu_page
*sp
, u64
*parent_pte
)
2040 mmu_page_remove_parent_pte(sp
, parent_pte
);
2043 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2046 struct rmap_iterator iter
;
2048 while ((sptep
= rmap_get_first(sp
->parent_ptes
, &iter
)))
2049 drop_parent_pte(sp
, sptep
);
2052 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2053 struct kvm_mmu_page
*parent
,
2054 struct list_head
*invalid_list
)
2057 struct mmu_page_path parents
;
2058 struct kvm_mmu_pages pages
;
2060 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2063 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2064 while (mmu_unsync_walk(parent
, &pages
)) {
2065 struct kvm_mmu_page
*sp
;
2067 for_each_sp(pages
, sp
, parents
, i
) {
2068 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2069 mmu_pages_clear_parents(&parents
);
2072 kvm_mmu_pages_init(parent
, &parents
, &pages
);
2078 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2079 struct list_head
*invalid_list
)
2083 trace_kvm_mmu_prepare_zap_page(sp
);
2084 ++kvm
->stat
.mmu_shadow_zapped
;
2085 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2086 kvm_mmu_page_unlink_children(kvm
, sp
);
2087 kvm_mmu_unlink_parents(kvm
, sp
);
2088 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2089 unaccount_shadowed(kvm
, sp
->gfn
);
2091 kvm_unlink_unsync_page(kvm
, sp
);
2092 if (!sp
->root_count
) {
2095 list_move(&sp
->link
, invalid_list
);
2096 kvm_mod_used_mmu_pages(kvm
, -1);
2098 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2099 kvm_reload_remote_mmus(kvm
);
2102 sp
->role
.invalid
= 1;
2106 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2107 struct list_head
*invalid_list
)
2109 struct kvm_mmu_page
*sp
;
2111 if (list_empty(invalid_list
))
2115 * wmb: make sure everyone sees our modifications to the page tables
2116 * rmb: make sure we see changes to vcpu->mode
2121 * Wait for all vcpus to exit guest mode and/or lockless shadow
2124 kvm_flush_remote_tlbs(kvm
);
2127 sp
= list_first_entry(invalid_list
, struct kvm_mmu_page
, link
);
2128 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2129 kvm_mmu_isolate_page(sp
);
2130 kvm_mmu_free_page(sp
);
2131 } while (!list_empty(invalid_list
));
2135 * Changing the number of mmu pages allocated to the vm
2136 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2138 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2140 LIST_HEAD(invalid_list
);
2142 * If we set the number of mmu pages to be smaller be than the
2143 * number of actived pages , we must to free some mmu pages before we
2147 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2148 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
&&
2149 !list_empty(&kvm
->arch
.active_mmu_pages
)) {
2150 struct kvm_mmu_page
*page
;
2152 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
2153 struct kvm_mmu_page
, link
);
2154 kvm_mmu_prepare_zap_page(kvm
, page
, &invalid_list
);
2156 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2157 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2160 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2163 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2165 struct kvm_mmu_page
*sp
;
2166 struct hlist_node
*node
;
2167 LIST_HEAD(invalid_list
);
2170 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2172 spin_lock(&kvm
->mmu_lock
);
2173 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
, node
) {
2174 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2177 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2179 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2180 spin_unlock(&kvm
->mmu_lock
);
2184 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2186 static void page_header_update_slot(struct kvm
*kvm
, void *pte
, gfn_t gfn
)
2188 int slot
= memslot_id(kvm
, gfn
);
2189 struct kvm_mmu_page
*sp
= page_header(__pa(pte
));
2191 __set_bit(slot
, sp
->slot_bitmap
);
2195 * The function is based on mtrr_type_lookup() in
2196 * arch/x86/kernel/cpu/mtrr/generic.c
2198 static int get_mtrr_type(struct mtrr_state_type
*mtrr_state
,
2203 u8 prev_match
, curr_match
;
2204 int num_var_ranges
= KVM_NR_VAR_MTRR
;
2206 if (!mtrr_state
->enabled
)
2209 /* Make end inclusive end, instead of exclusive */
2212 /* Look in fixed ranges. Just return the type as per start */
2213 if (mtrr_state
->have_fixed
&& (start
< 0x100000)) {
2216 if (start
< 0x80000) {
2218 idx
+= (start
>> 16);
2219 return mtrr_state
->fixed_ranges
[idx
];
2220 } else if (start
< 0xC0000) {
2222 idx
+= ((start
- 0x80000) >> 14);
2223 return mtrr_state
->fixed_ranges
[idx
];
2224 } else if (start
< 0x1000000) {
2226 idx
+= ((start
- 0xC0000) >> 12);
2227 return mtrr_state
->fixed_ranges
[idx
];
2232 * Look in variable ranges
2233 * Look of multiple ranges matching this address and pick type
2234 * as per MTRR precedence
2236 if (!(mtrr_state
->enabled
& 2))
2237 return mtrr_state
->def_type
;
2240 for (i
= 0; i
< num_var_ranges
; ++i
) {
2241 unsigned short start_state
, end_state
;
2243 if (!(mtrr_state
->var_ranges
[i
].mask_lo
& (1 << 11)))
2246 base
= (((u64
)mtrr_state
->var_ranges
[i
].base_hi
) << 32) +
2247 (mtrr_state
->var_ranges
[i
].base_lo
& PAGE_MASK
);
2248 mask
= (((u64
)mtrr_state
->var_ranges
[i
].mask_hi
) << 32) +
2249 (mtrr_state
->var_ranges
[i
].mask_lo
& PAGE_MASK
);
2251 start_state
= ((start
& mask
) == (base
& mask
));
2252 end_state
= ((end
& mask
) == (base
& mask
));
2253 if (start_state
!= end_state
)
2256 if ((start
& mask
) != (base
& mask
))
2259 curr_match
= mtrr_state
->var_ranges
[i
].base_lo
& 0xff;
2260 if (prev_match
== 0xFF) {
2261 prev_match
= curr_match
;
2265 if (prev_match
== MTRR_TYPE_UNCACHABLE
||
2266 curr_match
== MTRR_TYPE_UNCACHABLE
)
2267 return MTRR_TYPE_UNCACHABLE
;
2269 if ((prev_match
== MTRR_TYPE_WRBACK
&&
2270 curr_match
== MTRR_TYPE_WRTHROUGH
) ||
2271 (prev_match
== MTRR_TYPE_WRTHROUGH
&&
2272 curr_match
== MTRR_TYPE_WRBACK
)) {
2273 prev_match
= MTRR_TYPE_WRTHROUGH
;
2274 curr_match
= MTRR_TYPE_WRTHROUGH
;
2277 if (prev_match
!= curr_match
)
2278 return MTRR_TYPE_UNCACHABLE
;
2281 if (prev_match
!= 0xFF)
2284 return mtrr_state
->def_type
;
2287 u8
kvm_get_guest_memory_type(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2291 mtrr
= get_mtrr_type(&vcpu
->arch
.mtrr_state
, gfn
<< PAGE_SHIFT
,
2292 (gfn
<< PAGE_SHIFT
) + PAGE_SIZE
);
2293 if (mtrr
== 0xfe || mtrr
== 0xff)
2294 mtrr
= MTRR_TYPE_WRBACK
;
2297 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type
);
2299 static void __kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2301 trace_kvm_mmu_unsync_page(sp
);
2302 ++vcpu
->kvm
->stat
.mmu_unsync
;
2305 kvm_mmu_mark_parents_unsync(sp
);
2308 static void kvm_unsync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
)
2310 struct kvm_mmu_page
*s
;
2311 struct hlist_node
*node
;
2313 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2316 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2317 __kvm_unsync_page(vcpu
, s
);
2321 static int mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2324 struct kvm_mmu_page
*s
;
2325 struct hlist_node
*node
;
2326 bool need_unsync
= false;
2328 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
, node
) {
2332 if (s
->role
.level
!= PT_PAGE_TABLE_LEVEL
)
2335 if (!need_unsync
&& !s
->unsync
) {
2340 kvm_unsync_pages(vcpu
, gfn
);
2344 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2345 unsigned pte_access
, int level
,
2346 gfn_t gfn
, pfn_t pfn
, bool speculative
,
2347 bool can_unsync
, bool host_writable
)
2352 if (set_mmio_spte(sptep
, gfn
, pfn
, pte_access
))
2355 spte
= PT_PRESENT_MASK
;
2357 spte
|= shadow_accessed_mask
;
2359 if (pte_access
& ACC_EXEC_MASK
)
2360 spte
|= shadow_x_mask
;
2362 spte
|= shadow_nx_mask
;
2364 if (pte_access
& ACC_USER_MASK
)
2365 spte
|= shadow_user_mask
;
2367 if (level
> PT_PAGE_TABLE_LEVEL
)
2368 spte
|= PT_PAGE_SIZE_MASK
;
2370 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2371 kvm_is_mmio_pfn(pfn
));
2374 spte
|= SPTE_HOST_WRITEABLE
;
2376 pte_access
&= ~ACC_WRITE_MASK
;
2378 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2380 if (pte_access
& ACC_WRITE_MASK
) {
2383 * Other vcpu creates new sp in the window between
2384 * mapping_level() and acquiring mmu-lock. We can
2385 * allow guest to retry the access, the mapping can
2386 * be fixed if guest refault.
2388 if (level
> PT_PAGE_TABLE_LEVEL
&&
2389 has_wrprotected_page(vcpu
->kvm
, gfn
, level
))
2392 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2395 * Optimization: for pte sync, if spte was writable the hash
2396 * lookup is unnecessary (and expensive). Write protection
2397 * is responsibility of mmu_get_page / kvm_sync_page.
2398 * Same reasoning can be applied to dirty page accounting.
2400 if (!can_unsync
&& is_writable_pte(*sptep
))
2403 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2404 pgprintk("%s: found shadow page for %llx, marking ro\n",
2407 pte_access
&= ~ACC_WRITE_MASK
;
2408 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2412 if (pte_access
& ACC_WRITE_MASK
)
2413 mark_page_dirty(vcpu
->kvm
, gfn
);
2416 if (mmu_spte_update(sptep
, spte
))
2417 kvm_flush_remote_tlbs(vcpu
->kvm
);
2422 static void mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2423 unsigned pt_access
, unsigned pte_access
,
2424 int write_fault
, int *emulate
, int level
, gfn_t gfn
,
2425 pfn_t pfn
, bool speculative
, bool host_writable
)
2427 int was_rmapped
= 0;
2430 pgprintk("%s: spte %llx access %x write_fault %d gfn %llx\n",
2431 __func__
, *sptep
, pt_access
,
2434 if (is_rmap_spte(*sptep
)) {
2436 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2437 * the parent of the now unreachable PTE.
2439 if (level
> PT_PAGE_TABLE_LEVEL
&&
2440 !is_large_pte(*sptep
)) {
2441 struct kvm_mmu_page
*child
;
2444 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2445 drop_parent_pte(child
, sptep
);
2446 kvm_flush_remote_tlbs(vcpu
->kvm
);
2447 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2448 pgprintk("hfn old %llx new %llx\n",
2449 spte_to_pfn(*sptep
), pfn
);
2450 drop_spte(vcpu
->kvm
, sptep
);
2451 kvm_flush_remote_tlbs(vcpu
->kvm
);
2456 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2457 true, host_writable
)) {
2460 kvm_mmu_flush_tlb(vcpu
);
2463 if (unlikely(is_mmio_spte(*sptep
) && emulate
))
2466 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2467 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2468 is_large_pte(*sptep
)? "2MB" : "4kB",
2469 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2471 if (!was_rmapped
&& is_large_pte(*sptep
))
2472 ++vcpu
->kvm
->stat
.lpages
;
2474 if (is_shadow_present_pte(*sptep
)) {
2475 page_header_update_slot(vcpu
->kvm
, sptep
, gfn
);
2477 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2478 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2479 rmap_recycle(vcpu
, sptep
, gfn
);
2483 kvm_release_pfn_clean(pfn
);
2486 static void nonpaging_new_cr3(struct kvm_vcpu
*vcpu
)
2488 mmu_free_roots(vcpu
);
2491 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
2495 bit7
= (gpte
>> 7) & 1;
2496 return (gpte
& mmu
->rsvd_bits_mask
[bit7
][level
-1]) != 0;
2499 static pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2502 struct kvm_memory_slot
*slot
;
2504 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2506 return KVM_PFN_ERR_FAULT
;
2508 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2511 static bool prefetch_invalid_gpte(struct kvm_vcpu
*vcpu
,
2512 struct kvm_mmu_page
*sp
, u64
*spte
,
2515 if (is_rsvd_bits_set(&vcpu
->arch
.mmu
, gpte
, PT_PAGE_TABLE_LEVEL
))
2518 if (!is_present_gpte(gpte
))
2521 if (!(gpte
& PT_ACCESSED_MASK
))
2527 drop_spte(vcpu
->kvm
, spte
);
2531 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2532 struct kvm_mmu_page
*sp
,
2533 u64
*start
, u64
*end
)
2535 struct page
*pages
[PTE_PREFETCH_NUM
];
2536 unsigned access
= sp
->role
.access
;
2540 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2541 if (!gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
))
2544 ret
= gfn_to_page_many_atomic(vcpu
->kvm
, gfn
, pages
, end
- start
);
2548 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2549 mmu_set_spte(vcpu
, start
, ACC_ALL
, access
, 0, NULL
,
2550 sp
->role
.level
, gfn
, page_to_pfn(pages
[i
]),
2556 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2557 struct kvm_mmu_page
*sp
, u64
*sptep
)
2559 u64
*spte
, *start
= NULL
;
2562 WARN_ON(!sp
->role
.direct
);
2564 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2567 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2568 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2571 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2579 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2581 struct kvm_mmu_page
*sp
;
2584 * Since it's no accessed bit on EPT, it's no way to
2585 * distinguish between actually accessed translations
2586 * and prefetched, so disable pte prefetch if EPT is
2589 if (!shadow_accessed_mask
)
2592 sp
= page_header(__pa(sptep
));
2593 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2596 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2599 static int __direct_map(struct kvm_vcpu
*vcpu
, gpa_t v
, int write
,
2600 int map_writable
, int level
, gfn_t gfn
, pfn_t pfn
,
2603 struct kvm_shadow_walk_iterator iterator
;
2604 struct kvm_mmu_page
*sp
;
2608 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2609 if (iterator
.level
== level
) {
2610 unsigned pte_access
= ACC_ALL
;
2612 mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
, pte_access
,
2613 write
, &emulate
, level
, gfn
, pfn
,
2614 prefault
, map_writable
);
2615 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2616 ++vcpu
->stat
.pf_fixed
;
2620 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2621 u64 base_addr
= iterator
.addr
;
2623 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2624 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2625 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2627 1, ACC_ALL
, iterator
.sptep
);
2629 mmu_spte_set(iterator
.sptep
,
2631 | PT_PRESENT_MASK
| PT_WRITABLE_MASK
2632 | shadow_user_mask
| shadow_x_mask
2633 | shadow_accessed_mask
);
2639 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2643 info
.si_signo
= SIGBUS
;
2645 info
.si_code
= BUS_MCEERR_AR
;
2646 info
.si_addr
= (void __user
*)address
;
2647 info
.si_addr_lsb
= PAGE_SHIFT
;
2649 send_sig_info(SIGBUS
, &info
, tsk
);
2652 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, pfn_t pfn
)
2655 * Do not cache the mmio info caused by writing the readonly gfn
2656 * into the spte otherwise read access on readonly gfn also can
2657 * caused mmio page fault and treat it as mmio access.
2658 * Return 1 to tell kvm to emulate it.
2660 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2663 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2664 kvm_send_hwpoison_signal(gfn_to_hva(vcpu
->kvm
, gfn
), current
);
2671 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2672 gfn_t
*gfnp
, pfn_t
*pfnp
, int *levelp
)
2676 int level
= *levelp
;
2679 * Check if it's a transparent hugepage. If this would be an
2680 * hugetlbfs page, level wouldn't be set to
2681 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2684 if (!is_error_noslot_pfn(pfn
) && !kvm_is_mmio_pfn(pfn
) &&
2685 level
== PT_PAGE_TABLE_LEVEL
&&
2686 PageTransCompound(pfn_to_page(pfn
)) &&
2687 !has_wrprotected_page(vcpu
->kvm
, gfn
, PT_DIRECTORY_LEVEL
)) {
2690 * mmu_notifier_retry was successful and we hold the
2691 * mmu_lock here, so the pmd can't become splitting
2692 * from under us, and in turn
2693 * __split_huge_page_refcount() can't run from under
2694 * us and we can safely transfer the refcount from
2695 * PG_tail to PG_head as we switch the pfn to tail to
2698 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2699 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2700 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2704 kvm_release_pfn_clean(pfn
);
2712 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2713 pfn_t pfn
, unsigned access
, int *ret_val
)
2717 /* The pfn is invalid, report the error! */
2718 if (unlikely(is_error_pfn(pfn
))) {
2719 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2723 if (unlikely(is_noslot_pfn(pfn
)))
2724 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2731 static bool page_fault_can_be_fast(struct kvm_vcpu
*vcpu
, u32 error_code
)
2734 * #PF can be fast only if the shadow page table is present and it
2735 * is caused by write-protect, that means we just need change the
2736 * W bit of the spte which can be done out of mmu-lock.
2738 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2739 !(error_code
& PFERR_WRITE_MASK
))
2746 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 spte
)
2748 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
2751 WARN_ON(!sp
->role
.direct
);
2754 * The gfn of direct spte is stable since it is calculated
2757 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2759 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2760 mark_page_dirty(vcpu
->kvm
, gfn
);
2767 * - true: let the vcpu to access on the same address again.
2768 * - false: let the real page fault path to fix it.
2770 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2773 struct kvm_shadow_walk_iterator iterator
;
2777 if (!page_fault_can_be_fast(vcpu
, error_code
))
2780 walk_shadow_page_lockless_begin(vcpu
);
2781 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2782 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2786 * If the mapping has been changed, let the vcpu fault on the
2787 * same address again.
2789 if (!is_rmap_spte(spte
)) {
2794 if (!is_last_spte(spte
, level
))
2798 * Check if it is a spurious fault caused by TLB lazily flushed.
2800 * Need not check the access of upper level table entries since
2801 * they are always ACC_ALL.
2803 if (is_writable_pte(spte
)) {
2809 * Currently, to simplify the code, only the spte write-protected
2810 * by dirty-log can be fast fixed.
2812 if (!spte_is_locklessly_modifiable(spte
))
2816 * Currently, fast page fault only works for direct mapping since
2817 * the gfn is not stable for indirect shadow page.
2818 * See Documentation/virtual/kvm/locking.txt to get more detail.
2820 ret
= fast_pf_fix_direct_spte(vcpu
, iterator
.sptep
, spte
);
2822 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
2824 walk_shadow_page_lockless_end(vcpu
);
2829 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2830 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
);
2832 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
2833 gfn_t gfn
, bool prefault
)
2839 unsigned long mmu_seq
;
2840 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
2842 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
2843 if (likely(!force_pt_level
)) {
2844 level
= mapping_level(vcpu
, gfn
);
2846 * This path builds a PAE pagetable - so we can map
2847 * 2mb pages at maximum. Therefore check if the level
2848 * is larger than that.
2850 if (level
> PT_DIRECTORY_LEVEL
)
2851 level
= PT_DIRECTORY_LEVEL
;
2853 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
2855 level
= PT_PAGE_TABLE_LEVEL
;
2857 if (fast_page_fault(vcpu
, v
, level
, error_code
))
2860 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
2863 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
2866 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
2869 spin_lock(&vcpu
->kvm
->mmu_lock
);
2870 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
2872 kvm_mmu_free_some_pages(vcpu
);
2873 if (likely(!force_pt_level
))
2874 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
2875 r
= __direct_map(vcpu
, v
, write
, map_writable
, level
, gfn
, pfn
,
2877 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2883 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2884 kvm_release_pfn_clean(pfn
);
2889 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
2892 struct kvm_mmu_page
*sp
;
2893 LIST_HEAD(invalid_list
);
2895 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2897 spin_lock(&vcpu
->kvm
->mmu_lock
);
2898 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
2899 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
2900 vcpu
->arch
.mmu
.direct_map
)) {
2901 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2903 sp
= page_header(root
);
2905 if (!sp
->root_count
&& sp
->role
.invalid
) {
2906 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
2907 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2909 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2910 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2913 for (i
= 0; i
< 4; ++i
) {
2914 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2917 root
&= PT64_BASE_ADDR_MASK
;
2918 sp
= page_header(root
);
2920 if (!sp
->root_count
&& sp
->role
.invalid
)
2921 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
2924 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
2926 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
2927 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2928 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
2931 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
2935 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
2936 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2943 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
2945 struct kvm_mmu_page
*sp
;
2948 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
2949 spin_lock(&vcpu
->kvm
->mmu_lock
);
2950 kvm_mmu_free_some_pages(vcpu
);
2951 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
,
2954 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2955 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
2956 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
2957 for (i
= 0; i
< 4; ++i
) {
2958 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
2960 ASSERT(!VALID_PAGE(root
));
2961 spin_lock(&vcpu
->kvm
->mmu_lock
);
2962 kvm_mmu_free_some_pages(vcpu
);
2963 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
2965 PT32_ROOT_LEVEL
, 1, ACC_ALL
,
2967 root
= __pa(sp
->spt
);
2969 spin_unlock(&vcpu
->kvm
->mmu_lock
);
2970 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
2972 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
2979 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
2981 struct kvm_mmu_page
*sp
;
2986 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
2988 if (mmu_check_root(vcpu
, root_gfn
))
2992 * Do we shadow a long mode page table? If so we need to
2993 * write-protect the guests page table root.
2995 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
2996 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
2998 ASSERT(!VALID_PAGE(root
));
3000 spin_lock(&vcpu
->kvm
->mmu_lock
);
3001 kvm_mmu_free_some_pages(vcpu
);
3002 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3004 root
= __pa(sp
->spt
);
3006 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3007 vcpu
->arch
.mmu
.root_hpa
= root
;
3012 * We shadow a 32 bit page table. This may be a legacy 2-level
3013 * or a PAE 3-level page table. In either case we need to be aware that
3014 * the shadow page table may be a PAE or a long mode page table.
3016 pm_mask
= PT_PRESENT_MASK
;
3017 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3018 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3020 for (i
= 0; i
< 4; ++i
) {
3021 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3023 ASSERT(!VALID_PAGE(root
));
3024 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3025 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3026 if (!is_present_gpte(pdptr
)) {
3027 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3030 root_gfn
= pdptr
>> PAGE_SHIFT
;
3031 if (mmu_check_root(vcpu
, root_gfn
))
3034 spin_lock(&vcpu
->kvm
->mmu_lock
);
3035 kvm_mmu_free_some_pages(vcpu
);
3036 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30,
3039 root
= __pa(sp
->spt
);
3041 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3043 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3045 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3048 * If we shadow a 32 bit page table with a long mode page
3049 * table we enter this path.
3051 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3052 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3054 * The additional page necessary for this is only
3055 * allocated on demand.
3060 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3061 if (lm_root
== NULL
)
3064 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3066 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3069 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3075 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3077 if (vcpu
->arch
.mmu
.direct_map
)
3078 return mmu_alloc_direct_roots(vcpu
);
3080 return mmu_alloc_shadow_roots(vcpu
);
3083 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3086 struct kvm_mmu_page
*sp
;
3088 if (vcpu
->arch
.mmu
.direct_map
)
3091 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3094 vcpu_clear_mmio_info(vcpu
, ~0ul);
3095 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3096 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3097 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3098 sp
= page_header(root
);
3099 mmu_sync_children(vcpu
, sp
);
3100 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3103 for (i
= 0; i
< 4; ++i
) {
3104 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3106 if (root
&& VALID_PAGE(root
)) {
3107 root
&= PT64_BASE_ADDR_MASK
;
3108 sp
= page_header(root
);
3109 mmu_sync_children(vcpu
, sp
);
3112 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3115 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3117 spin_lock(&vcpu
->kvm
->mmu_lock
);
3118 mmu_sync_roots(vcpu
);
3119 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3122 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3123 u32 access
, struct x86_exception
*exception
)
3126 exception
->error_code
= 0;
3130 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3132 struct x86_exception
*exception
)
3135 exception
->error_code
= 0;
3136 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
);
3139 static bool quickly_check_mmio_pf(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3142 return vcpu_match_mmio_gpa(vcpu
, addr
);
3144 return vcpu_match_mmio_gva(vcpu
, addr
);
3149 * On direct hosts, the last spte is only allows two states
3150 * for mmio page fault:
3151 * - It is the mmio spte
3152 * - It is zapped or it is being zapped.
3154 * This function completely checks the spte when the last spte
3155 * is not the mmio spte.
3157 static bool check_direct_spte_mmio_pf(u64 spte
)
3159 return __check_direct_spte_mmio_pf(spte
);
3162 static u64
walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
)
3164 struct kvm_shadow_walk_iterator iterator
;
3167 walk_shadow_page_lockless_begin(vcpu
);
3168 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
)
3169 if (!is_shadow_present_pte(spte
))
3171 walk_shadow_page_lockless_end(vcpu
);
3177 * If it is a real mmio page fault, return 1 and emulat the instruction
3178 * directly, return 0 to let CPU fault again on the address, -1 is
3179 * returned if bug is detected.
3181 int handle_mmio_page_fault_common(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3185 if (quickly_check_mmio_pf(vcpu
, addr
, direct
))
3188 spte
= walk_shadow_page_get_mmio_spte(vcpu
, addr
);
3190 if (is_mmio_spte(spte
)) {
3191 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3192 unsigned access
= get_mmio_spte_access(spte
);
3197 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3198 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3203 * It's ok if the gva is remapped by other cpus on shadow guest,
3204 * it's a BUG if the gfn is not a mmio page.
3206 if (direct
&& !check_direct_spte_mmio_pf(spte
))
3210 * If the page table is zapped by other cpus, let CPU fault again on
3215 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common
);
3217 static int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
,
3218 u32 error_code
, bool direct
)
3222 ret
= handle_mmio_page_fault_common(vcpu
, addr
, direct
);
3227 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3228 u32 error_code
, bool prefault
)
3233 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3235 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3236 return handle_mmio_page_fault(vcpu
, gva
, error_code
, true);
3238 r
= mmu_topup_memory_caches(vcpu
);
3243 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3245 gfn
= gva
>> PAGE_SHIFT
;
3247 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3248 error_code
, gfn
, prefault
);
3251 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3253 struct kvm_arch_async_pf arch
;
3255 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3257 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3258 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3260 return kvm_setup_async_pf(vcpu
, gva
, gfn
, &arch
);
3263 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3265 if (unlikely(!irqchip_in_kernel(vcpu
->kvm
) ||
3266 kvm_event_needs_reinjection(vcpu
)))
3269 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3272 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3273 gva_t gva
, pfn_t
*pfn
, bool write
, bool *writable
)
3277 *pfn
= gfn_to_pfn_async(vcpu
->kvm
, gfn
, &async
, write
, writable
);
3280 return false; /* *pfn has correct page already */
3282 if (!prefault
&& can_do_async_pf(vcpu
)) {
3283 trace_kvm_try_async_get_page(gva
, gfn
);
3284 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3285 trace_kvm_async_pf_doublefault(gva
, gfn
);
3286 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3288 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3292 *pfn
= gfn_to_pfn_prot(vcpu
->kvm
, gfn
, write
, writable
);
3297 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3304 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3305 unsigned long mmu_seq
;
3306 int write
= error_code
& PFERR_WRITE_MASK
;
3310 ASSERT(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3312 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3313 return handle_mmio_page_fault(vcpu
, gpa
, error_code
, true);
3315 r
= mmu_topup_memory_caches(vcpu
);
3319 force_pt_level
= mapping_level_dirty_bitmap(vcpu
, gfn
);
3320 if (likely(!force_pt_level
)) {
3321 level
= mapping_level(vcpu
, gfn
);
3322 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3324 level
= PT_PAGE_TABLE_LEVEL
;
3326 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3329 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3332 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3335 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3338 spin_lock(&vcpu
->kvm
->mmu_lock
);
3339 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3341 kvm_mmu_free_some_pages(vcpu
);
3342 if (likely(!force_pt_level
))
3343 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3344 r
= __direct_map(vcpu
, gpa
, write
, map_writable
,
3345 level
, gfn
, pfn
, prefault
);
3346 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3351 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3352 kvm_release_pfn_clean(pfn
);
3356 static void nonpaging_free(struct kvm_vcpu
*vcpu
)
3358 mmu_free_roots(vcpu
);
3361 static int nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3362 struct kvm_mmu
*context
)
3364 context
->new_cr3
= nonpaging_new_cr3
;
3365 context
->page_fault
= nonpaging_page_fault
;
3366 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3367 context
->free
= nonpaging_free
;
3368 context
->sync_page
= nonpaging_sync_page
;
3369 context
->invlpg
= nonpaging_invlpg
;
3370 context
->update_pte
= nonpaging_update_pte
;
3371 context
->root_level
= 0;
3372 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3373 context
->root_hpa
= INVALID_PAGE
;
3374 context
->direct_map
= true;
3375 context
->nx
= false;
3379 void kvm_mmu_flush_tlb(struct kvm_vcpu
*vcpu
)
3381 ++vcpu
->stat
.tlb_flush
;
3382 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3385 static void paging_new_cr3(struct kvm_vcpu
*vcpu
)
3387 pgprintk("%s: cr3 %lx\n", __func__
, kvm_read_cr3(vcpu
));
3388 mmu_free_roots(vcpu
);
3391 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3393 return kvm_read_cr3(vcpu
);
3396 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3397 struct x86_exception
*fault
)
3399 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3402 static void paging_free(struct kvm_vcpu
*vcpu
)
3404 nonpaging_free(vcpu
);
3407 static inline void protect_clean_gpte(unsigned *access
, unsigned gpte
)
3411 BUILD_BUG_ON(PT_WRITABLE_MASK
!= ACC_WRITE_MASK
);
3413 mask
= (unsigned)~ACC_WRITE_MASK
;
3414 /* Allow write access to dirty gptes */
3415 mask
|= (gpte
>> (PT_DIRTY_SHIFT
- PT_WRITABLE_SHIFT
)) & PT_WRITABLE_MASK
;
3419 static bool sync_mmio_spte(u64
*sptep
, gfn_t gfn
, unsigned access
,
3422 if (unlikely(is_mmio_spte(*sptep
))) {
3423 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3424 mmu_spte_clear_no_track(sptep
);
3429 mark_mmio_spte(sptep
, gfn
, access
);
3436 static inline unsigned gpte_access(struct kvm_vcpu
*vcpu
, u64 gpte
)
3440 access
= (gpte
& (PT_WRITABLE_MASK
| PT_USER_MASK
)) | ACC_EXEC_MASK
;
3441 access
&= ~(gpte
>> PT64_NX_SHIFT
);
3446 static inline bool is_last_gpte(struct kvm_mmu
*mmu
, unsigned level
, unsigned gpte
)
3451 index
|= (gpte
& PT_PAGE_SIZE_MASK
) >> (PT_PAGE_SIZE_SHIFT
- 2);
3452 return mmu
->last_pte_bitmap
& (1 << index
);
3456 #include "paging_tmpl.h"
3460 #include "paging_tmpl.h"
3463 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3464 struct kvm_mmu
*context
)
3466 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
3467 u64 exb_bit_rsvd
= 0;
3470 exb_bit_rsvd
= rsvd_bits(63, 63);
3471 switch (context
->root_level
) {
3472 case PT32_ROOT_LEVEL
:
3473 /* no rsvd bits for 2 level 4K page table entries */
3474 context
->rsvd_bits_mask
[0][1] = 0;
3475 context
->rsvd_bits_mask
[0][0] = 0;
3476 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3478 if (!is_pse(vcpu
)) {
3479 context
->rsvd_bits_mask
[1][1] = 0;
3483 if (is_cpuid_PSE36())
3484 /* 36bits PSE 4MB page */
3485 context
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3487 /* 32 bits PSE 4MB page */
3488 context
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3490 case PT32E_ROOT_LEVEL
:
3491 context
->rsvd_bits_mask
[0][2] =
3492 rsvd_bits(maxphyaddr
, 63) |
3493 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3494 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3495 rsvd_bits(maxphyaddr
, 62); /* PDE */
3496 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3497 rsvd_bits(maxphyaddr
, 62); /* PTE */
3498 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3499 rsvd_bits(maxphyaddr
, 62) |
3500 rsvd_bits(13, 20); /* large page */
3501 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3503 case PT64_ROOT_LEVEL
:
3504 context
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3505 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3506 context
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3507 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(7, 8);
3508 context
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3509 rsvd_bits(maxphyaddr
, 51);
3510 context
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3511 rsvd_bits(maxphyaddr
, 51);
3512 context
->rsvd_bits_mask
[1][3] = context
->rsvd_bits_mask
[0][3];
3513 context
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3514 rsvd_bits(maxphyaddr
, 51) |
3516 context
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3517 rsvd_bits(maxphyaddr
, 51) |
3518 rsvd_bits(13, 20); /* large page */
3519 context
->rsvd_bits_mask
[1][0] = context
->rsvd_bits_mask
[0][0];
3524 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3526 unsigned bit
, byte
, pfec
;
3528 bool fault
, x
, w
, u
, wf
, uf
, ff
, smep
;
3530 smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3531 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
3534 wf
= pfec
& PFERR_WRITE_MASK
;
3535 uf
= pfec
& PFERR_USER_MASK
;
3536 ff
= pfec
& PFERR_FETCH_MASK
;
3537 for (bit
= 0; bit
< 8; ++bit
) {
3538 x
= bit
& ACC_EXEC_MASK
;
3539 w
= bit
& ACC_WRITE_MASK
;
3540 u
= bit
& ACC_USER_MASK
;
3542 /* Not really needed: !nx will cause pte.nx to fault */
3544 /* Allow supervisor writes if !cr0.wp */
3545 w
|= !is_write_protection(vcpu
) && !uf
;
3546 /* Disallow supervisor fetches of user code if cr4.smep */
3547 x
&= !(smep
&& u
&& !uf
);
3549 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
);
3550 map
|= fault
<< bit
;
3552 mmu
->permissions
[byte
] = map
;
3556 static void update_last_pte_bitmap(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
3559 unsigned level
, root_level
= mmu
->root_level
;
3560 const unsigned ps_set_index
= 1 << 2; /* bit 2 of index: ps */
3562 if (root_level
== PT32E_ROOT_LEVEL
)
3564 /* PT_PAGE_TABLE_LEVEL always terminates */
3565 map
= 1 | (1 << ps_set_index
);
3566 for (level
= PT_DIRECTORY_LEVEL
; level
<= root_level
; ++level
) {
3567 if (level
<= PT_PDPE_LEVEL
3568 && (mmu
->root_level
>= PT32E_ROOT_LEVEL
|| is_pse(vcpu
)))
3569 map
|= 1 << (ps_set_index
| (level
- 1));
3571 mmu
->last_pte_bitmap
= map
;
3574 static int paging64_init_context_common(struct kvm_vcpu
*vcpu
,
3575 struct kvm_mmu
*context
,
3578 context
->nx
= is_nx(vcpu
);
3579 context
->root_level
= level
;
3581 reset_rsvds_bits_mask(vcpu
, context
);
3582 update_permission_bitmask(vcpu
, context
);
3583 update_last_pte_bitmap(vcpu
, context
);
3585 ASSERT(is_pae(vcpu
));
3586 context
->new_cr3
= paging_new_cr3
;
3587 context
->page_fault
= paging64_page_fault
;
3588 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3589 context
->sync_page
= paging64_sync_page
;
3590 context
->invlpg
= paging64_invlpg
;
3591 context
->update_pte
= paging64_update_pte
;
3592 context
->free
= paging_free
;
3593 context
->shadow_root_level
= level
;
3594 context
->root_hpa
= INVALID_PAGE
;
3595 context
->direct_map
= false;
3599 static int paging64_init_context(struct kvm_vcpu
*vcpu
,
3600 struct kvm_mmu
*context
)
3602 return paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
3605 static int paging32_init_context(struct kvm_vcpu
*vcpu
,
3606 struct kvm_mmu
*context
)
3608 context
->nx
= false;
3609 context
->root_level
= PT32_ROOT_LEVEL
;
3611 reset_rsvds_bits_mask(vcpu
, context
);
3612 update_permission_bitmask(vcpu
, context
);
3613 update_last_pte_bitmap(vcpu
, context
);
3615 context
->new_cr3
= paging_new_cr3
;
3616 context
->page_fault
= paging32_page_fault
;
3617 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3618 context
->free
= paging_free
;
3619 context
->sync_page
= paging32_sync_page
;
3620 context
->invlpg
= paging32_invlpg
;
3621 context
->update_pte
= paging32_update_pte
;
3622 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3623 context
->root_hpa
= INVALID_PAGE
;
3624 context
->direct_map
= false;
3628 static int paging32E_init_context(struct kvm_vcpu
*vcpu
,
3629 struct kvm_mmu
*context
)
3631 return paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
3634 static int init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
3636 struct kvm_mmu
*context
= vcpu
->arch
.walk_mmu
;
3638 context
->base_role
.word
= 0;
3639 context
->new_cr3
= nonpaging_new_cr3
;
3640 context
->page_fault
= tdp_page_fault
;
3641 context
->free
= nonpaging_free
;
3642 context
->sync_page
= nonpaging_sync_page
;
3643 context
->invlpg
= nonpaging_invlpg
;
3644 context
->update_pte
= nonpaging_update_pte
;
3645 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
3646 context
->root_hpa
= INVALID_PAGE
;
3647 context
->direct_map
= true;
3648 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
3649 context
->get_cr3
= get_cr3
;
3650 context
->get_pdptr
= kvm_pdptr_read
;
3651 context
->inject_page_fault
= kvm_inject_page_fault
;
3653 if (!is_paging(vcpu
)) {
3654 context
->nx
= false;
3655 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3656 context
->root_level
= 0;
3657 } else if (is_long_mode(vcpu
)) {
3658 context
->nx
= is_nx(vcpu
);
3659 context
->root_level
= PT64_ROOT_LEVEL
;
3660 reset_rsvds_bits_mask(vcpu
, context
);
3661 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3662 } else if (is_pae(vcpu
)) {
3663 context
->nx
= is_nx(vcpu
);
3664 context
->root_level
= PT32E_ROOT_LEVEL
;
3665 reset_rsvds_bits_mask(vcpu
, context
);
3666 context
->gva_to_gpa
= paging64_gva_to_gpa
;
3668 context
->nx
= false;
3669 context
->root_level
= PT32_ROOT_LEVEL
;
3670 reset_rsvds_bits_mask(vcpu
, context
);
3671 context
->gva_to_gpa
= paging32_gva_to_gpa
;
3674 update_permission_bitmask(vcpu
, context
);
3675 update_last_pte_bitmap(vcpu
, context
);
3680 int kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3683 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3685 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3687 if (!is_paging(vcpu
))
3688 r
= nonpaging_init_context(vcpu
, context
);
3689 else if (is_long_mode(vcpu
))
3690 r
= paging64_init_context(vcpu
, context
);
3691 else if (is_pae(vcpu
))
3692 r
= paging32E_init_context(vcpu
, context
);
3694 r
= paging32_init_context(vcpu
, context
);
3696 vcpu
->arch
.mmu
.base_role
.cr4_pae
= !!is_pae(vcpu
);
3697 vcpu
->arch
.mmu
.base_role
.cr0_wp
= is_write_protection(vcpu
);
3698 vcpu
->arch
.mmu
.base_role
.smep_andnot_wp
3699 = smep
&& !is_write_protection(vcpu
);
3703 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
3705 static int init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
3707 int r
= kvm_init_shadow_mmu(vcpu
, vcpu
->arch
.walk_mmu
);
3709 vcpu
->arch
.walk_mmu
->set_cr3
= kvm_x86_ops
->set_cr3
;
3710 vcpu
->arch
.walk_mmu
->get_cr3
= get_cr3
;
3711 vcpu
->arch
.walk_mmu
->get_pdptr
= kvm_pdptr_read
;
3712 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
3717 static int init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
3719 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
3721 g_context
->get_cr3
= get_cr3
;
3722 g_context
->get_pdptr
= kvm_pdptr_read
;
3723 g_context
->inject_page_fault
= kvm_inject_page_fault
;
3726 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3727 * translation of l2_gpa to l1_gpa addresses is done using the
3728 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3729 * functions between mmu and nested_mmu are swapped.
3731 if (!is_paging(vcpu
)) {
3732 g_context
->nx
= false;
3733 g_context
->root_level
= 0;
3734 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
3735 } else if (is_long_mode(vcpu
)) {
3736 g_context
->nx
= is_nx(vcpu
);
3737 g_context
->root_level
= PT64_ROOT_LEVEL
;
3738 reset_rsvds_bits_mask(vcpu
, g_context
);
3739 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3740 } else if (is_pae(vcpu
)) {
3741 g_context
->nx
= is_nx(vcpu
);
3742 g_context
->root_level
= PT32E_ROOT_LEVEL
;
3743 reset_rsvds_bits_mask(vcpu
, g_context
);
3744 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
3746 g_context
->nx
= false;
3747 g_context
->root_level
= PT32_ROOT_LEVEL
;
3748 reset_rsvds_bits_mask(vcpu
, g_context
);
3749 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
3752 update_permission_bitmask(vcpu
, g_context
);
3753 update_last_pte_bitmap(vcpu
, g_context
);
3758 static int init_kvm_mmu(struct kvm_vcpu
*vcpu
)
3760 if (mmu_is_nested(vcpu
))
3761 return init_kvm_nested_mmu(vcpu
);
3762 else if (tdp_enabled
)
3763 return init_kvm_tdp_mmu(vcpu
);
3765 return init_kvm_softmmu(vcpu
);
3768 static void destroy_kvm_mmu(struct kvm_vcpu
*vcpu
)
3771 if (VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3772 /* mmu.free() should set root_hpa = INVALID_PAGE */
3773 vcpu
->arch
.mmu
.free(vcpu
);
3776 int kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
3778 destroy_kvm_mmu(vcpu
);
3779 return init_kvm_mmu(vcpu
);
3781 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
3783 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
3787 r
= mmu_topup_memory_caches(vcpu
);
3790 r
= mmu_alloc_roots(vcpu
);
3791 spin_lock(&vcpu
->kvm
->mmu_lock
);
3792 mmu_sync_roots(vcpu
);
3793 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3796 /* set_cr3() should ensure TLB has been flushed */
3797 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
3801 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
3803 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
3805 mmu_free_roots(vcpu
);
3807 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
3809 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
3810 struct kvm_mmu_page
*sp
, u64
*spte
,
3813 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
3814 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
3818 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
3819 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
3822 static bool need_remote_flush(u64 old
, u64
new)
3824 if (!is_shadow_present_pte(old
))
3826 if (!is_shadow_present_pte(new))
3828 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
3830 old
^= PT64_NX_MASK
;
3831 new ^= PT64_NX_MASK
;
3832 return (old
& ~new & PT64_PERM_MASK
) != 0;
3835 static void mmu_pte_write_flush_tlb(struct kvm_vcpu
*vcpu
, bool zap_page
,
3836 bool remote_flush
, bool local_flush
)
3842 kvm_flush_remote_tlbs(vcpu
->kvm
);
3843 else if (local_flush
)
3844 kvm_mmu_flush_tlb(vcpu
);
3847 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
3848 const u8
*new, int *bytes
)
3854 * Assume that the pte write on a page table of the same type
3855 * as the current vcpu paging mode since we update the sptes only
3856 * when they have the same mode.
3858 if (is_pae(vcpu
) && *bytes
== 4) {
3859 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3862 r
= kvm_read_guest(vcpu
->kvm
, *gpa
, &gentry
, min(*bytes
, 8));
3865 new = (const u8
*)&gentry
;
3870 gentry
= *(const u32
*)new;
3873 gentry
= *(const u64
*)new;
3884 * If we're seeing too many writes to a page, it may no longer be a page table,
3885 * or we may be forking, in which case it is better to unmap the page.
3887 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
3890 * Skip write-flooding detected for the sp whose level is 1, because
3891 * it can become unsync, then the guest page is not write-protected.
3893 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
3896 return ++sp
->write_flooding_count
>= 3;
3900 * Misaligned accesses are too much trouble to fix up; also, they usually
3901 * indicate a page is not used as a page table.
3903 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
3906 unsigned offset
, pte_size
, misaligned
;
3908 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3909 gpa
, bytes
, sp
->role
.word
);
3911 offset
= offset_in_page(gpa
);
3912 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
3915 * Sometimes, the OS only writes the last one bytes to update status
3916 * bits, for example, in linux, andb instruction is used in clear_bit().
3918 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
3921 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
3922 misaligned
|= bytes
< 4;
3927 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
3929 unsigned page_offset
, quadrant
;
3933 page_offset
= offset_in_page(gpa
);
3934 level
= sp
->role
.level
;
3936 if (!sp
->role
.cr4_pae
) {
3937 page_offset
<<= 1; /* 32->64 */
3939 * A 32-bit pde maps 4MB while the shadow pdes map
3940 * only 2MB. So we need to double the offset again
3941 * and zap two pdes instead of one.
3943 if (level
== PT32_ROOT_LEVEL
) {
3944 page_offset
&= ~7; /* kill rounding error */
3948 quadrant
= page_offset
>> PAGE_SHIFT
;
3949 page_offset
&= ~PAGE_MASK
;
3950 if (quadrant
!= sp
->role
.quadrant
)
3954 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
3958 void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
3959 const u8
*new, int bytes
)
3961 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3962 union kvm_mmu_page_role mask
= { .word
= 0 };
3963 struct kvm_mmu_page
*sp
;
3964 struct hlist_node
*node
;
3965 LIST_HEAD(invalid_list
);
3966 u64 entry
, gentry
, *spte
;
3968 bool remote_flush
, local_flush
, zap_page
;
3971 * If we don't have indirect shadow pages, it means no page is
3972 * write-protected, so we can exit simply.
3974 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
3977 zap_page
= remote_flush
= local_flush
= false;
3979 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
3981 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
3984 * No need to care whether allocation memory is successful
3985 * or not since pte prefetch is skiped if it does not have
3986 * enough objects in the cache.
3988 mmu_topup_memory_caches(vcpu
);
3990 spin_lock(&vcpu
->kvm
->mmu_lock
);
3991 ++vcpu
->kvm
->stat
.mmu_pte_write
;
3992 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
3994 mask
.cr0_wp
= mask
.cr4_pae
= mask
.nxe
= 1;
3995 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
, node
) {
3996 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
3997 detect_write_flooding(sp
)) {
3998 zap_page
|= !!kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
4000 ++vcpu
->kvm
->stat
.mmu_flooded
;
4004 spte
= get_written_sptes(sp
, gpa
, &npte
);
4011 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4013 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4014 & mask
.word
) && rmap_can_add(vcpu
))
4015 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4016 if (!remote_flush
&& need_remote_flush(entry
, *spte
))
4017 remote_flush
= true;
4021 mmu_pte_write_flush_tlb(vcpu
, zap_page
, remote_flush
, local_flush
);
4022 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4023 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4024 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4027 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4032 if (vcpu
->arch
.mmu
.direct_map
)
4035 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4037 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4041 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4043 void __kvm_mmu_free_some_pages(struct kvm_vcpu
*vcpu
)
4045 LIST_HEAD(invalid_list
);
4047 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
&&
4048 !list_empty(&vcpu
->kvm
->arch
.active_mmu_pages
)) {
4049 struct kvm_mmu_page
*sp
;
4051 sp
= container_of(vcpu
->kvm
->arch
.active_mmu_pages
.prev
,
4052 struct kvm_mmu_page
, link
);
4053 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4054 ++vcpu
->kvm
->stat
.mmu_recycled
;
4056 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4059 static bool is_mmio_page_fault(struct kvm_vcpu
*vcpu
, gva_t addr
)
4061 if (vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
))
4062 return vcpu_match_mmio_gpa(vcpu
, addr
);
4064 return vcpu_match_mmio_gva(vcpu
, addr
);
4067 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
4068 void *insn
, int insn_len
)
4070 int r
, emulation_type
= EMULTYPE_RETRY
;
4071 enum emulation_result er
;
4073 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
4082 if (is_mmio_page_fault(vcpu
, cr2
))
4085 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4090 case EMULATE_DO_MMIO
:
4091 ++vcpu
->stat
.mmio_exits
;
4101 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4103 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4105 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4106 kvm_mmu_flush_tlb(vcpu
);
4107 ++vcpu
->stat
.invlpg
;
4109 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4111 void kvm_enable_tdp(void)
4115 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4117 void kvm_disable_tdp(void)
4119 tdp_enabled
= false;
4121 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4123 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4125 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4126 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4127 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4130 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4138 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4139 * Therefore we need to allocate shadow page tables in the first
4140 * 4GB of memory, which happens to fit the DMA32 zone.
4142 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4146 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4147 for (i
= 0; i
< 4; ++i
)
4148 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4153 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4157 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4158 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4159 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4160 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4162 return alloc_mmu_pages(vcpu
);
4165 int kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4168 ASSERT(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4170 return init_kvm_mmu(vcpu
);
4173 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
, int slot
)
4175 struct kvm_memory_slot
*memslot
;
4179 memslot
= id_to_memslot(kvm
->memslots
, slot
);
4180 last_gfn
= memslot
->base_gfn
+ memslot
->npages
- 1;
4182 for (i
= PT_PAGE_TABLE_LEVEL
;
4183 i
< PT_PAGE_TABLE_LEVEL
+ KVM_NR_PAGE_SIZES
; ++i
) {
4184 unsigned long *rmapp
;
4185 unsigned long last_index
, index
;
4187 rmapp
= memslot
->arch
.rmap
[i
- PT_PAGE_TABLE_LEVEL
];
4188 last_index
= gfn_to_index(last_gfn
, memslot
->base_gfn
, i
);
4190 for (index
= 0; index
<= last_index
; ++index
, ++rmapp
) {
4192 __rmap_write_protect(kvm
, rmapp
, false);
4196 kvm_flush_remote_tlbs(kvm
);
4199 void kvm_mmu_zap_all(struct kvm
*kvm
)
4201 struct kvm_mmu_page
*sp
, *node
;
4202 LIST_HEAD(invalid_list
);
4204 spin_lock(&kvm
->mmu_lock
);
4206 list_for_each_entry_safe(sp
, node
, &kvm
->arch
.active_mmu_pages
, link
)
4207 if (kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
))
4210 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4211 spin_unlock(&kvm
->mmu_lock
);
4214 static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm
*kvm
,
4215 struct list_head
*invalid_list
)
4217 struct kvm_mmu_page
*page
;
4219 if (list_empty(&kvm
->arch
.active_mmu_pages
))
4222 page
= container_of(kvm
->arch
.active_mmu_pages
.prev
,
4223 struct kvm_mmu_page
, link
);
4224 kvm_mmu_prepare_zap_page(kvm
, page
, invalid_list
);
4227 static int mmu_shrink(struct shrinker
*shrink
, struct shrink_control
*sc
)
4230 int nr_to_scan
= sc
->nr_to_scan
;
4232 if (nr_to_scan
== 0)
4235 raw_spin_lock(&kvm_lock
);
4237 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4239 LIST_HEAD(invalid_list
);
4242 * Never scan more than sc->nr_to_scan VM instances.
4243 * Will not hit this condition practically since we do not try
4244 * to shrink more than one VM and it is very unlikely to see
4245 * !n_used_mmu_pages so many times.
4250 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4251 * here. We may skip a VM instance errorneosly, but we do not
4252 * want to shrink a VM that only started to populate its MMU
4255 if (!kvm
->arch
.n_used_mmu_pages
)
4258 idx
= srcu_read_lock(&kvm
->srcu
);
4259 spin_lock(&kvm
->mmu_lock
);
4261 kvm_mmu_remove_some_alloc_mmu_pages(kvm
, &invalid_list
);
4262 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
4264 spin_unlock(&kvm
->mmu_lock
);
4265 srcu_read_unlock(&kvm
->srcu
, idx
);
4267 list_move_tail(&kvm
->vm_list
, &vm_list
);
4271 raw_spin_unlock(&kvm_lock
);
4274 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
4277 static struct shrinker mmu_shrinker
= {
4278 .shrink
= mmu_shrink
,
4279 .seeks
= DEFAULT_SEEKS
* 10,
4282 static void mmu_destroy_caches(void)
4284 if (pte_list_desc_cache
)
4285 kmem_cache_destroy(pte_list_desc_cache
);
4286 if (mmu_page_header_cache
)
4287 kmem_cache_destroy(mmu_page_header_cache
);
4290 int kvm_mmu_module_init(void)
4292 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
4293 sizeof(struct pte_list_desc
),
4295 if (!pte_list_desc_cache
)
4298 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
4299 sizeof(struct kvm_mmu_page
),
4301 if (!mmu_page_header_cache
)
4304 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0))
4307 register_shrinker(&mmu_shrinker
);
4312 mmu_destroy_caches();
4317 * Caculate mmu pages needed for kvm.
4319 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
4321 unsigned int nr_mmu_pages
;
4322 unsigned int nr_pages
= 0;
4323 struct kvm_memslots
*slots
;
4324 struct kvm_memory_slot
*memslot
;
4326 slots
= kvm_memslots(kvm
);
4328 kvm_for_each_memslot(memslot
, slots
)
4329 nr_pages
+= memslot
->npages
;
4331 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
4332 nr_mmu_pages
= max(nr_mmu_pages
,
4333 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
4335 return nr_mmu_pages
;
4338 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu
*vcpu
, u64 addr
, u64 sptes
[4])
4340 struct kvm_shadow_walk_iterator iterator
;
4344 walk_shadow_page_lockless_begin(vcpu
);
4345 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
4346 sptes
[iterator
.level
-1] = spte
;
4348 if (!is_shadow_present_pte(spte
))
4351 walk_shadow_page_lockless_end(vcpu
);
4355 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy
);
4357 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
4361 destroy_kvm_mmu(vcpu
);
4362 free_mmu_pages(vcpu
);
4363 mmu_free_memory_caches(vcpu
);
4366 void kvm_mmu_module_exit(void)
4368 mmu_destroy_caches();
4369 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
4370 unregister_shrinker(&mmu_shrinker
);
4371 mmu_audit_disable();