1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
40 #include <asm/virtext.h>
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
48 MODULE_AUTHOR("Qumranet");
49 MODULE_LICENSE("GPL");
52 static const struct x86_cpu_id svm_cpu_id
[] = {
53 X86_MATCH_FEATURE(X86_FEATURE_SVM
, NULL
),
56 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
59 #define SEG_TYPE_LDT 2
60 #define SEG_TYPE_BUSY_TSS16 3
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_TSC_RATE (1 << 4)
65 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
67 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
70 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
72 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
73 #define TSC_RATIO_MIN 0x0000000000000001ULL
74 #define TSC_RATIO_MAX 0x000000ffffffffffULL
76 static bool erratum_383_found __read_mostly
;
78 u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
81 * Set osvw_len to higher value when updated Revision Guides
82 * are published and we know what the new status bits are
84 static uint64_t osvw_len
= 4, osvw_status
;
86 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
87 #define TSC_RATIO_DEFAULT 0x0100000000ULL
89 static const struct svm_direct_access_msrs
{
90 u32 index
; /* Index of the MSR */
91 bool always
; /* True if intercept is initially cleared */
92 } direct_access_msrs
[MAX_DIRECT_ACCESS_MSRS
] = {
93 { .index
= MSR_STAR
, .always
= true },
94 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
95 { .index
= MSR_IA32_SYSENTER_EIP
, .always
= false },
96 { .index
= MSR_IA32_SYSENTER_ESP
, .always
= false },
98 { .index
= MSR_GS_BASE
, .always
= true },
99 { .index
= MSR_FS_BASE
, .always
= true },
100 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
101 { .index
= MSR_LSTAR
, .always
= true },
102 { .index
= MSR_CSTAR
, .always
= true },
103 { .index
= MSR_SYSCALL_MASK
, .always
= true },
105 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
106 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
107 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
108 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
109 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
110 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
111 { .index
= MSR_EFER
, .always
= false },
112 { .index
= MSR_IA32_CR_PAT
, .always
= false },
113 { .index
= MSR_AMD64_SEV_ES_GHCB
, .always
= true },
114 { .index
= MSR_INVALID
, .always
= false },
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * pause_filter_count: On processors that support Pause filtering(indicated
120 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
121 * count value. On VMRUN this value is loaded into an internal counter.
122 * Each time a pause instruction is executed, this counter is decremented
123 * until it reaches zero at which time a #VMEXIT is generated if pause
124 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
125 * Intercept Filtering for more details.
126 * This also indicate if ple logic enabled.
128 * pause_filter_thresh: In addition, some processor families support advanced
129 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
130 * the amount of time a guest is allowed to execute in a pause loop.
131 * In this mode, a 16-bit pause filter threshold field is added in the
132 * VMCB. The threshold value is a cycle count that is used to reset the
133 * pause counter. As with simple pause filtering, VMRUN loads the pause
134 * count value from VMCB into an internal counter. Then, on each pause
135 * instruction the hardware checks the elapsed number of cycles since
136 * the most recent pause instruction against the pause filter threshold.
137 * If the elapsed cycle count is greater than the pause filter threshold,
138 * then the internal pause count is reloaded from the VMCB and execution
139 * continues. If the elapsed cycle count is less than the pause filter
140 * threshold, then the internal pause count is decremented. If the count
141 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
142 * triggered. If advanced pause filtering is supported and pause filter
143 * threshold field is set to zero, the filter will operate in the simpler,
147 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
148 module_param(pause_filter_thresh
, ushort
, 0444);
150 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
151 module_param(pause_filter_count
, ushort
, 0444);
153 /* Default doubles per-vcpu window every exit. */
154 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
155 module_param(pause_filter_count_grow
, ushort
, 0444);
157 /* Default resets per-vcpu window every exit to pause_filter_count. */
158 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
159 module_param(pause_filter_count_shrink
, ushort
, 0444);
161 /* Default is to compute the maximum so we can never overflow. */
162 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
163 module_param(pause_filter_count_max
, ushort
, 0444);
166 * Use nested page tables by default. Note, NPT may get forced off by
167 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
169 bool npt_enabled
= true;
170 module_param_named(npt
, npt_enabled
, bool, 0444);
172 /* allow nested virtualization in KVM/SVM */
173 static int nested
= true;
174 module_param(nested
, int, S_IRUGO
);
176 /* enable/disable Next RIP Save */
177 static int nrips
= true;
178 module_param(nrips
, int, 0444);
180 /* enable/disable Virtual VMLOAD VMSAVE */
181 static int vls
= true;
182 module_param(vls
, int, 0444);
184 /* enable/disable Virtual GIF */
185 static int vgif
= true;
186 module_param(vgif
, int, 0444);
188 bool __read_mostly dump_invalid_vmcb
;
189 module_param(dump_invalid_vmcb
, bool, 0644);
191 static bool svm_gp_erratum_intercept
= true;
193 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
195 static unsigned long iopm_base
;
197 struct kvm_ldttss_desc
{
200 unsigned base1
:8, type
:5, dpl
:2, p
:1;
201 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
204 } __attribute__((packed
));
206 DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
209 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
210 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
212 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
213 * defer the restoration of TSC_AUX until the CPU returns to userspace.
215 #define TSC_AUX_URET_SLOT 0
217 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
220 #define MSRS_RANGE_SIZE 2048
221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
223 u32
svm_msrpm_offset(u32 msr
)
228 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
229 if (msr
< msrpm_ranges
[i
] ||
230 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
233 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
234 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
236 /* Now we have the u8 offset - but need the u32 offset */
240 /* MSR not in any range */
244 #define MAX_INST_SIZE 15
246 static int get_max_npt_level(void)
249 return PT64_ROOT_4LEVEL
;
251 return PT32E_ROOT_LEVEL
;
255 int svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
257 struct vcpu_svm
*svm
= to_svm(vcpu
);
258 u64 old_efer
= vcpu
->arch
.efer
;
259 vcpu
->arch
.efer
= efer
;
262 /* Shadow paging assumes NX to be available. */
265 if (!(efer
& EFER_LMA
))
269 if ((old_efer
& EFER_SVME
) != (efer
& EFER_SVME
)) {
270 if (!(efer
& EFER_SVME
)) {
271 svm_leave_nested(svm
);
272 svm_set_gif(svm
, true);
273 /* #GP intercept is still needed for vmware backdoor */
274 if (!enable_vmware_backdoor
)
275 clr_exception_intercept(svm
, GP_VECTOR
);
278 * Free the nested guest state, unless we are in SMM.
279 * In this case we will return to the nested guest
280 * as soon as we leave SMM.
283 svm_free_nested(svm
);
286 int ret
= svm_allocate_nested(svm
);
289 vcpu
->arch
.efer
= old_efer
;
293 if (svm_gp_erratum_intercept
)
294 set_exception_intercept(svm
, GP_VECTOR
);
298 svm
->vmcb
->save
.efer
= efer
| EFER_SVME
;
299 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
303 static int is_external_interrupt(u32 info
)
305 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
306 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
309 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
311 struct vcpu_svm
*svm
= to_svm(vcpu
);
314 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
315 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
319 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
321 struct vcpu_svm
*svm
= to_svm(vcpu
);
324 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
326 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
330 static int skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
332 struct vcpu_svm
*svm
= to_svm(vcpu
);
335 * SEV-ES does not expose the next RIP. The RIP update is controlled by
336 * the type of exit and the #VC handler in the guest.
338 if (sev_es_guest(vcpu
->kvm
))
341 if (nrips
&& svm
->vmcb
->control
.next_rip
!= 0) {
342 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
343 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
346 if (!svm
->next_rip
) {
347 if (!kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
))
350 kvm_rip_write(vcpu
, svm
->next_rip
);
354 svm_set_interrupt_shadow(vcpu
, 0);
359 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
361 struct vcpu_svm
*svm
= to_svm(vcpu
);
362 unsigned nr
= vcpu
->arch
.exception
.nr
;
363 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
364 u32 error_code
= vcpu
->arch
.exception
.error_code
;
366 kvm_deliver_exception_payload(vcpu
);
368 if (nr
== BP_VECTOR
&& !nrips
) {
369 unsigned long rip
, old_rip
= kvm_rip_read(vcpu
);
372 * For guest debugging where we have to reinject #BP if some
373 * INT3 is guest-owned:
374 * Emulate nRIP by moving RIP forward. Will fail if injection
375 * raises a fault that is not intercepted. Still better than
376 * failing in all cases.
378 (void)skip_emulated_instruction(vcpu
);
379 rip
= kvm_rip_read(vcpu
);
380 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
381 svm
->int3_injected
= rip
- old_rip
;
384 svm
->vmcb
->control
.event_inj
= nr
386 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
387 | SVM_EVTINJ_TYPE_EXEPT
;
388 svm
->vmcb
->control
.event_inj_err
= error_code
;
391 static void svm_init_erratum_383(void)
397 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
400 /* Use _safe variants to not break nested virtualization */
401 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
407 low
= lower_32_bits(val
);
408 high
= upper_32_bits(val
);
410 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
412 erratum_383_found
= true;
415 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
418 * Guests should see errata 400 and 415 as fixed (assuming that
419 * HLT and IO instructions are intercepted).
421 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
422 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
425 * By increasing VCPU's osvw.length to 3 we are telling the guest that
426 * all osvw.status bits inside that length, including bit 0 (which is
427 * reserved for erratum 298), are valid. However, if host processor's
428 * osvw_len is 0 then osvw_status[0] carries no information. We need to
429 * be conservative here and therefore we tell the guest that erratum 298
430 * is present (because we really don't know).
432 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
433 vcpu
->arch
.osvw
.status
|= 1;
436 static int has_svm(void)
440 if (!cpu_has_svm(&msg
)) {
441 printk(KERN_INFO
"has_svm: %s\n", msg
);
446 pr_info("KVM is unsupported when running as an SEV guest\n");
453 static void svm_hardware_disable(void)
455 /* Make sure we clean up behind us */
456 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
457 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
461 amd_pmu_disable_virt();
464 static int svm_hardware_enable(void)
467 struct svm_cpu_data
*sd
;
469 struct desc_struct
*gdt
;
470 int me
= raw_smp_processor_id();
472 rdmsrl(MSR_EFER
, efer
);
473 if (efer
& EFER_SVME
)
477 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
480 sd
= per_cpu(svm_data
, me
);
482 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
486 sd
->asid_generation
= 1;
487 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
488 sd
->next_asid
= sd
->max_asid
+ 1;
489 sd
->min_asid
= max_sev_asid
+ 1;
491 gdt
= get_current_gdt_rw();
492 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
494 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
496 wrmsrl(MSR_VM_HSAVE_PA
, __sme_page_pa(sd
->save_area
));
498 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
499 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
500 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
507 * Note that it is possible to have a system with mixed processor
508 * revisions and therefore different OSVW bits. If bits are not the same
509 * on different processors then choose the worst case (i.e. if erratum
510 * is present on one processor and not on another then assume that the
511 * erratum is present everywhere).
513 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
514 uint64_t len
, status
= 0;
517 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
519 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
523 osvw_status
= osvw_len
= 0;
527 osvw_status
|= status
;
528 osvw_status
&= (1ULL << osvw_len
) - 1;
531 osvw_status
= osvw_len
= 0;
533 svm_init_erratum_383();
535 amd_pmu_enable_virt();
540 static void svm_cpu_uninit(int cpu
)
542 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
547 per_cpu(svm_data
, cpu
) = NULL
;
548 kfree(sd
->sev_vmcbs
);
549 __free_page(sd
->save_area
);
553 static int svm_cpu_init(int cpu
)
555 struct svm_cpu_data
*sd
;
558 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
562 sd
->save_area
= alloc_page(GFP_KERNEL
);
566 clear_page(page_address(sd
->save_area
));
568 ret
= sev_cpu_init(sd
);
572 per_cpu(svm_data
, cpu
) = sd
;
577 __free_page(sd
->save_area
);
584 static int direct_access_msr_slot(u32 msr
)
588 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
589 if (direct_access_msrs
[i
].index
== msr
)
595 static void set_shadow_msr_intercept(struct kvm_vcpu
*vcpu
, u32 msr
, int read
,
598 struct vcpu_svm
*svm
= to_svm(vcpu
);
599 int slot
= direct_access_msr_slot(msr
);
604 /* Set the shadow bitmaps to the desired intercept states */
606 set_bit(slot
, svm
->shadow_msr_intercept
.read
);
608 clear_bit(slot
, svm
->shadow_msr_intercept
.read
);
611 set_bit(slot
, svm
->shadow_msr_intercept
.write
);
613 clear_bit(slot
, svm
->shadow_msr_intercept
.write
);
616 static bool valid_msr_intercept(u32 index
)
618 return direct_access_msr_slot(index
) != -ENOENT
;
621 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
628 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
631 offset
= svm_msrpm_offset(msr
);
632 bit_write
= 2 * (msr
& 0x0f) + 1;
635 BUG_ON(offset
== MSR_INVALID
);
637 return !!test_bit(bit_write
, &tmp
);
640 static void set_msr_interception_bitmap(struct kvm_vcpu
*vcpu
, u32
*msrpm
,
641 u32 msr
, int read
, int write
)
643 u8 bit_read
, bit_write
;
648 * If this warning triggers extend the direct_access_msrs list at the
649 * beginning of the file
651 WARN_ON(!valid_msr_intercept(msr
));
653 /* Enforce non allowed MSRs to trap */
654 if (read
&& !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_READ
))
657 if (write
&& !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_WRITE
))
660 offset
= svm_msrpm_offset(msr
);
661 bit_read
= 2 * (msr
& 0x0f);
662 bit_write
= 2 * (msr
& 0x0f) + 1;
665 BUG_ON(offset
== MSR_INVALID
);
667 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
668 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
673 void set_msr_interception(struct kvm_vcpu
*vcpu
, u32
*msrpm
, u32 msr
,
676 set_shadow_msr_intercept(vcpu
, msr
, read
, write
);
677 set_msr_interception_bitmap(vcpu
, msrpm
, msr
, read
, write
);
680 u32
*svm_vcpu_alloc_msrpm(void)
682 unsigned int order
= get_order(MSRPM_SIZE
);
683 struct page
*pages
= alloc_pages(GFP_KERNEL_ACCOUNT
, order
);
689 msrpm
= page_address(pages
);
690 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << order
));
695 void svm_vcpu_init_msrpm(struct kvm_vcpu
*vcpu
, u32
*msrpm
)
699 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
700 if (!direct_access_msrs
[i
].always
)
702 set_msr_interception(vcpu
, msrpm
, direct_access_msrs
[i
].index
, 1, 1);
707 void svm_vcpu_free_msrpm(u32
*msrpm
)
709 __free_pages(virt_to_page(msrpm
), get_order(MSRPM_SIZE
));
712 static void svm_msr_filter_changed(struct kvm_vcpu
*vcpu
)
714 struct vcpu_svm
*svm
= to_svm(vcpu
);
718 * Set intercept permissions for all direct access MSRs again. They
719 * will automatically get filtered through the MSR filter, so we are
720 * back in sync after this.
722 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
723 u32 msr
= direct_access_msrs
[i
].index
;
724 u32 read
= test_bit(i
, svm
->shadow_msr_intercept
.read
);
725 u32 write
= test_bit(i
, svm
->shadow_msr_intercept
.write
);
727 set_msr_interception_bitmap(vcpu
, svm
->msrpm
, msr
, read
, write
);
731 static void add_msr_offset(u32 offset
)
735 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
737 /* Offset already in list? */
738 if (msrpm_offsets
[i
] == offset
)
741 /* Slot used by another offset? */
742 if (msrpm_offsets
[i
] != MSR_INVALID
)
745 /* Add offset to list */
746 msrpm_offsets
[i
] = offset
;
752 * If this BUG triggers the msrpm_offsets table has an overflow. Just
753 * increase MSRPM_OFFSETS in this case.
758 static void init_msrpm_offsets(void)
762 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
764 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
767 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
768 BUG_ON(offset
== MSR_INVALID
);
770 add_msr_offset(offset
);
774 static void svm_enable_lbrv(struct kvm_vcpu
*vcpu
)
776 struct vcpu_svm
*svm
= to_svm(vcpu
);
778 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
779 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
780 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
781 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
782 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
785 static void svm_disable_lbrv(struct kvm_vcpu
*vcpu
)
787 struct vcpu_svm
*svm
= to_svm(vcpu
);
789 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
790 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
791 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
792 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
793 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
796 void disable_nmi_singlestep(struct vcpu_svm
*svm
)
798 svm
->nmi_singlestep
= false;
800 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
801 /* Clear our flags if they were not set by the guest */
802 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
803 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
804 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
805 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
809 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
811 struct vcpu_svm
*svm
= to_svm(vcpu
);
812 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
813 int old
= control
->pause_filter_count
;
815 control
->pause_filter_count
= __grow_ple_window(old
,
817 pause_filter_count_grow
,
818 pause_filter_count_max
);
820 if (control
->pause_filter_count
!= old
) {
821 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
822 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
823 control
->pause_filter_count
, old
);
827 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
829 struct vcpu_svm
*svm
= to_svm(vcpu
);
830 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
831 int old
= control
->pause_filter_count
;
833 control
->pause_filter_count
=
834 __shrink_ple_window(old
,
836 pause_filter_count_shrink
,
838 if (control
->pause_filter_count
!= old
) {
839 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
840 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
841 control
->pause_filter_count
, old
);
846 * The default MMIO mask is a single bit (excluding the present bit),
847 * which could conflict with the memory encryption bit. Check for
848 * memory encryption support and override the default MMIO mask if
849 * memory encryption is enabled.
851 static __init
void svm_adjust_mmio_mask(void)
853 unsigned int enc_bit
, mask_bit
;
856 /* If there is no memory encryption support, use existing mask */
857 if (cpuid_eax(0x80000000) < 0x8000001f)
860 /* If memory encryption is not enabled, use existing mask */
861 rdmsrl(MSR_K8_SYSCFG
, msr
);
862 if (!(msr
& MSR_K8_SYSCFG_MEM_ENCRYPT
))
865 enc_bit
= cpuid_ebx(0x8000001f) & 0x3f;
866 mask_bit
= boot_cpu_data
.x86_phys_bits
;
868 /* Increment the mask bit if it is the same as the encryption bit */
869 if (enc_bit
== mask_bit
)
873 * If the mask bit location is below 52, then some bits above the
874 * physical addressing limit will always be reserved, so use the
875 * rsvd_bits() function to generate the mask. This mask, along with
876 * the present bit, will be used to generate a page fault with
879 * If the mask bit location is 52 (or above), then clear the mask.
881 mask
= (mask_bit
< 52) ? rsvd_bits(mask_bit
, 51) | PT_PRESENT_MASK
: 0;
883 kvm_mmu_set_mmio_spte_mask(mask
, mask
, PT_WRITABLE_MASK
| PT_USER_MASK
);
886 static void svm_hardware_teardown(void)
890 sev_hardware_teardown();
892 for_each_possible_cpu(cpu
)
895 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
),
896 get_order(IOPM_SIZE
));
900 static __init
void svm_set_cpu_caps(void)
906 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
908 kvm_cpu_cap_set(X86_FEATURE_SVM
);
911 kvm_cpu_cap_set(X86_FEATURE_NRIPS
);
914 kvm_cpu_cap_set(X86_FEATURE_NPT
);
916 /* Nested VM can receive #VMEXIT instead of triggering #GP */
917 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK
);
920 /* CPUID 0x80000008 */
921 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
) ||
922 boot_cpu_has(X86_FEATURE_AMD_SSBD
))
923 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD
);
925 /* CPUID 0x8000001F (SME/SEV features) */
929 static __init
int svm_hardware_setup(void)
932 struct page
*iopm_pages
;
935 unsigned int order
= get_order(IOPM_SIZE
);
937 iopm_pages
= alloc_pages(GFP_KERNEL
, order
);
942 iopm_va
= page_address(iopm_pages
);
943 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << order
));
944 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
946 init_msrpm_offsets();
948 supported_xcr0
&= ~(XFEATURE_MASK_BNDREGS
| XFEATURE_MASK_BNDCSR
);
950 if (boot_cpu_has(X86_FEATURE_NX
))
951 kvm_enable_efer_bits(EFER_NX
);
953 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
954 kvm_enable_efer_bits(EFER_FFXSR
);
956 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
957 kvm_has_tsc_control
= true;
958 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
959 kvm_tsc_scaling_ratio_frac_bits
= 32;
962 if (boot_cpu_has(X86_FEATURE_RDTSCP
))
963 kvm_define_user_return_msr(TSC_AUX_URET_SLOT
, MSR_TSC_AUX
);
965 /* Check for pause filtering support */
966 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
967 pause_filter_count
= 0;
968 pause_filter_thresh
= 0;
969 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
970 pause_filter_thresh
= 0;
974 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
975 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
979 * KVM's MMU doesn't support using 2-level paging for itself, and thus
980 * NPT isn't supported if the host is using 2-level paging since host
981 * CR4 is unchanged on VMRUN.
983 if (!IS_ENABLED(CONFIG_X86_64
) && !IS_ENABLED(CONFIG_X86_PAE
))
986 if (!boot_cpu_has(X86_FEATURE_NPT
))
989 kvm_configure_mmu(npt_enabled
, get_max_npt_level(), PG_LEVEL_1G
);
990 pr_info("kvm: Nested Paging %sabled\n", npt_enabled
? "en" : "dis");
992 /* Note, SEV setup consumes npt_enabled. */
993 sev_hardware_setup();
995 svm_adjust_mmio_mask();
997 for_each_possible_cpu(cpu
) {
998 r
= svm_cpu_init(cpu
);
1004 if (!boot_cpu_has(X86_FEATURE_NRIPS
))
1010 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1011 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1014 pr_info("AVIC enabled\n");
1016 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1022 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1023 !IS_ENABLED(CONFIG_X86_64
)) {
1026 pr_info("Virtual VMLOAD VMSAVE supported\n");
1030 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK
))
1031 svm_gp_erratum_intercept
= false;
1034 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1037 pr_info("Virtual GIF supported\n");
1043 * It seems that on AMD processors PTE's accessed bit is
1044 * being set by the CPU hardware before the NPF vmexit.
1045 * This is not expected behaviour and our tests fail because
1047 * A workaround here is to disable support for
1048 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1049 * In this case userspace can know if there is support using
1050 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1052 * If future AMD CPU models change the behaviour described above,
1053 * this variable can be changed accordingly
1055 allow_smaller_maxphyaddr
= !npt_enabled
;
1060 svm_hardware_teardown();
1064 static void init_seg(struct vmcb_seg
*seg
)
1067 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1068 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1069 seg
->limit
= 0xffff;
1073 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1076 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1077 seg
->limit
= 0xffff;
1081 static u64
svm_write_l1_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1083 struct vcpu_svm
*svm
= to_svm(vcpu
);
1084 u64 g_tsc_offset
= 0;
1086 if (is_guest_mode(vcpu
)) {
1087 /* Write L1's TSC offset. */
1088 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1089 svm
->vmcb01
.ptr
->control
.tsc_offset
;
1090 svm
->vmcb01
.ptr
->control
.tsc_offset
= offset
;
1093 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1094 svm
->vmcb
->control
.tsc_offset
- g_tsc_offset
,
1097 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1099 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1100 return svm
->vmcb
->control
.tsc_offset
;
1103 static void svm_check_invpcid(struct vcpu_svm
*svm
)
1106 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1107 * roots, or if INVPCID is disabled in the guest to inject #UD.
1109 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID
)) {
1111 !guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_INVPCID
))
1112 svm_set_intercept(svm
, INTERCEPT_INVPCID
);
1114 svm_clr_intercept(svm
, INTERCEPT_INVPCID
);
1118 static void init_vmcb(struct kvm_vcpu
*vcpu
)
1120 struct vcpu_svm
*svm
= to_svm(vcpu
);
1121 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1122 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1124 vcpu
->arch
.hflags
= 0;
1126 svm_set_intercept(svm
, INTERCEPT_CR0_READ
);
1127 svm_set_intercept(svm
, INTERCEPT_CR3_READ
);
1128 svm_set_intercept(svm
, INTERCEPT_CR4_READ
);
1129 svm_set_intercept(svm
, INTERCEPT_CR0_WRITE
);
1130 svm_set_intercept(svm
, INTERCEPT_CR3_WRITE
);
1131 svm_set_intercept(svm
, INTERCEPT_CR4_WRITE
);
1132 if (!kvm_vcpu_apicv_active(vcpu
))
1133 svm_set_intercept(svm
, INTERCEPT_CR8_WRITE
);
1135 set_dr_intercepts(svm
);
1137 set_exception_intercept(svm
, PF_VECTOR
);
1138 set_exception_intercept(svm
, UD_VECTOR
);
1139 set_exception_intercept(svm
, MC_VECTOR
);
1140 set_exception_intercept(svm
, AC_VECTOR
);
1141 set_exception_intercept(svm
, DB_VECTOR
);
1143 * Guest access to VMware backdoor ports could legitimately
1144 * trigger #GP because of TSS I/O permission bitmap.
1145 * We intercept those #GP and allow access to them anyway
1148 if (enable_vmware_backdoor
)
1149 set_exception_intercept(svm
, GP_VECTOR
);
1151 svm_set_intercept(svm
, INTERCEPT_INTR
);
1152 svm_set_intercept(svm
, INTERCEPT_NMI
);
1153 svm_set_intercept(svm
, INTERCEPT_SMI
);
1154 svm_set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1155 svm_set_intercept(svm
, INTERCEPT_RDPMC
);
1156 svm_set_intercept(svm
, INTERCEPT_CPUID
);
1157 svm_set_intercept(svm
, INTERCEPT_INVD
);
1158 svm_set_intercept(svm
, INTERCEPT_INVLPG
);
1159 svm_set_intercept(svm
, INTERCEPT_INVLPGA
);
1160 svm_set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1161 svm_set_intercept(svm
, INTERCEPT_MSR_PROT
);
1162 svm_set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1163 svm_set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1164 svm_set_intercept(svm
, INTERCEPT_VMRUN
);
1165 svm_set_intercept(svm
, INTERCEPT_VMMCALL
);
1166 svm_set_intercept(svm
, INTERCEPT_VMLOAD
);
1167 svm_set_intercept(svm
, INTERCEPT_VMSAVE
);
1168 svm_set_intercept(svm
, INTERCEPT_STGI
);
1169 svm_set_intercept(svm
, INTERCEPT_CLGI
);
1170 svm_set_intercept(svm
, INTERCEPT_SKINIT
);
1171 svm_set_intercept(svm
, INTERCEPT_WBINVD
);
1172 svm_set_intercept(svm
, INTERCEPT_XSETBV
);
1173 svm_set_intercept(svm
, INTERCEPT_RDPRU
);
1174 svm_set_intercept(svm
, INTERCEPT_RSM
);
1176 if (!kvm_mwait_in_guest(vcpu
->kvm
)) {
1177 svm_set_intercept(svm
, INTERCEPT_MONITOR
);
1178 svm_set_intercept(svm
, INTERCEPT_MWAIT
);
1181 if (!kvm_hlt_in_guest(vcpu
->kvm
))
1182 svm_set_intercept(svm
, INTERCEPT_HLT
);
1184 control
->iopm_base_pa
= __sme_set(iopm_base
);
1185 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1186 control
->int_ctl
= V_INTR_MASKING_MASK
;
1188 init_seg(&save
->es
);
1189 init_seg(&save
->ss
);
1190 init_seg(&save
->ds
);
1191 init_seg(&save
->fs
);
1192 init_seg(&save
->gs
);
1194 save
->cs
.selector
= 0xf000;
1195 save
->cs
.base
= 0xffff0000;
1196 /* Executable/Readable Code Segment */
1197 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1198 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1199 save
->cs
.limit
= 0xffff;
1201 save
->gdtr
.limit
= 0xffff;
1202 save
->idtr
.limit
= 0xffff;
1204 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1205 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1207 svm_set_cr4(vcpu
, 0);
1208 svm_set_efer(vcpu
, 0);
1209 save
->dr6
= 0xffff0ff0;
1210 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
1211 save
->rip
= 0x0000fff0;
1212 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1215 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1216 * It also updates the guest-visible cr0 value.
1218 svm_set_cr0(vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1219 kvm_mmu_reset_context(vcpu
);
1221 save
->cr4
= X86_CR4_PAE
;
1225 /* Setup VMCB for Nested Paging */
1226 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1227 svm_clr_intercept(svm
, INTERCEPT_INVLPG
);
1228 clr_exception_intercept(svm
, PF_VECTOR
);
1229 svm_clr_intercept(svm
, INTERCEPT_CR3_READ
);
1230 svm_clr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1231 save
->g_pat
= vcpu
->arch
.pat
;
1235 svm
->current_vmcb
->asid_generation
= 0;
1238 svm
->nested
.vmcb12_gpa
= 0;
1239 svm
->nested
.last_vmcb12_gpa
= 0;
1240 vcpu
->arch
.hflags
= 0;
1242 if (!kvm_pause_in_guest(vcpu
->kvm
)) {
1243 control
->pause_filter_count
= pause_filter_count
;
1244 if (pause_filter_thresh
)
1245 control
->pause_filter_thresh
= pause_filter_thresh
;
1246 svm_set_intercept(svm
, INTERCEPT_PAUSE
);
1248 svm_clr_intercept(svm
, INTERCEPT_PAUSE
);
1251 svm_check_invpcid(svm
);
1254 * If the host supports V_SPEC_CTRL then disable the interception
1255 * of MSR_IA32_SPEC_CTRL.
1257 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL
))
1258 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
1260 if (kvm_vcpu_apicv_active(vcpu
))
1261 avic_init_vmcb(svm
);
1264 svm_clr_intercept(svm
, INTERCEPT_STGI
);
1265 svm_clr_intercept(svm
, INTERCEPT_CLGI
);
1266 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1269 if (sev_guest(vcpu
->kvm
)) {
1270 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1271 clr_exception_intercept(svm
, UD_VECTOR
);
1273 if (sev_es_guest(vcpu
->kvm
)) {
1274 /* Perform SEV-ES specific VMCB updates */
1275 sev_es_init_vmcb(svm
);
1279 vmcb_mark_all_dirty(svm
->vmcb
);
1285 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1287 struct vcpu_svm
*svm
= to_svm(vcpu
);
1292 svm
->virt_spec_ctrl
= 0;
1295 vcpu
->arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1296 MSR_IA32_APICBASE_ENABLE
;
1297 if (kvm_vcpu_is_reset_bsp(vcpu
))
1298 vcpu
->arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1302 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, false);
1303 kvm_rdx_write(vcpu
, eax
);
1305 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1306 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1309 void svm_switch_vmcb(struct vcpu_svm
*svm
, struct kvm_vmcb_info
*target_vmcb
)
1311 svm
->current_vmcb
= target_vmcb
;
1312 svm
->vmcb
= target_vmcb
->ptr
;
1315 static int svm_create_vcpu(struct kvm_vcpu
*vcpu
)
1317 struct vcpu_svm
*svm
;
1318 struct page
*vmcb01_page
;
1319 struct page
*vmsa_page
= NULL
;
1322 BUILD_BUG_ON(offsetof(struct vcpu_svm
, vcpu
) != 0);
1326 vmcb01_page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_ZERO
);
1330 if (sev_es_guest(vcpu
->kvm
)) {
1332 * SEV-ES guests require a separate VMSA page used to contain
1333 * the encrypted register state of the guest.
1335 vmsa_page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_ZERO
);
1337 goto error_free_vmcb_page
;
1340 * SEV-ES guests maintain an encrypted version of their FPU
1341 * state which is restored and saved on VMRUN and VMEXIT.
1342 * Free the fpu structure to prevent KVM from attempting to
1343 * access the FPU state.
1345 kvm_free_guest_fpu(vcpu
);
1348 err
= avic_init_vcpu(svm
);
1350 goto error_free_vmsa_page
;
1352 /* We initialize this flag to true to make sure that the is_running
1353 * bit would be set the first time the vcpu is loaded.
1355 if (irqchip_in_kernel(vcpu
->kvm
) && kvm_apicv_activated(vcpu
->kvm
))
1356 svm
->avic_is_running
= true;
1358 svm
->msrpm
= svm_vcpu_alloc_msrpm();
1361 goto error_free_vmsa_page
;
1364 svm_vcpu_init_msrpm(vcpu
, svm
->msrpm
);
1366 svm
->vmcb01
.ptr
= page_address(vmcb01_page
);
1367 svm
->vmcb01
.pa
= __sme_set(page_to_pfn(vmcb01_page
) << PAGE_SHIFT
);
1370 svm
->vmsa
= page_address(vmsa_page
);
1372 svm
->guest_state_loaded
= false;
1374 svm_switch_vmcb(svm
, &svm
->vmcb01
);
1377 svm_init_osvw(vcpu
);
1378 vcpu
->arch
.microcode_version
= 0x01000065;
1380 if (sev_es_guest(vcpu
->kvm
))
1381 /* Perform SEV-ES specific VMCB creation updates */
1382 sev_es_create_vcpu(svm
);
1386 error_free_vmsa_page
:
1388 __free_page(vmsa_page
);
1389 error_free_vmcb_page
:
1390 __free_page(vmcb01_page
);
1395 static void svm_clear_current_vmcb(struct vmcb
*vmcb
)
1399 for_each_online_cpu(i
)
1400 cmpxchg(&per_cpu(svm_data
, i
)->current_vmcb
, vmcb
, NULL
);
1403 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1405 struct vcpu_svm
*svm
= to_svm(vcpu
);
1408 * The vmcb page can be recycled, causing a false negative in
1409 * svm_vcpu_load(). So, ensure that no logical CPU has this
1410 * vmcb page recorded as its current vmcb.
1412 svm_clear_current_vmcb(svm
->vmcb
);
1414 svm_free_nested(svm
);
1416 sev_free_vcpu(vcpu
);
1418 __free_page(pfn_to_page(__sme_clr(svm
->vmcb01
.pa
) >> PAGE_SHIFT
));
1419 __free_pages(virt_to_page(svm
->msrpm
), get_order(MSRPM_SIZE
));
1422 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
1424 struct vcpu_svm
*svm
= to_svm(vcpu
);
1425 struct svm_cpu_data
*sd
= per_cpu(svm_data
, vcpu
->cpu
);
1427 if (svm
->guest_state_loaded
)
1431 * Save additional host state that will be restored on VMEXIT (sev-es)
1432 * or subsequent vmload of host save area.
1434 if (sev_es_guest(vcpu
->kvm
)) {
1435 sev_es_prepare_guest_switch(svm
, vcpu
->cpu
);
1437 vmsave(__sme_page_pa(sd
->save_area
));
1440 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1441 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1442 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1443 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1444 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1448 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1449 kvm_set_user_return_msr(TSC_AUX_URET_SLOT
, svm
->tsc_aux
, -1ull);
1451 svm
->guest_state_loaded
= true;
1454 static void svm_prepare_host_switch(struct kvm_vcpu
*vcpu
)
1456 to_svm(vcpu
)->guest_state_loaded
= false;
1459 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1461 struct vcpu_svm
*svm
= to_svm(vcpu
);
1462 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
1464 if (sd
->current_vmcb
!= svm
->vmcb
) {
1465 sd
->current_vmcb
= svm
->vmcb
;
1466 indirect_branch_prediction_barrier();
1468 avic_vcpu_load(vcpu
, cpu
);
1471 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1473 avic_vcpu_put(vcpu
);
1474 svm_prepare_host_switch(vcpu
);
1476 ++vcpu
->stat
.host_state_reload
;
1479 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1481 struct vcpu_svm
*svm
= to_svm(vcpu
);
1482 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
1484 if (svm
->nmi_singlestep
) {
1485 /* Hide our flags if they were not set by the guest */
1486 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1487 rflags
&= ~X86_EFLAGS_TF
;
1488 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1489 rflags
&= ~X86_EFLAGS_RF
;
1494 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1496 if (to_svm(vcpu
)->nmi_singlestep
)
1497 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1500 * Any change of EFLAGS.VM is accompanied by a reload of SS
1501 * (caused by either a task switch or an inter-privilege IRET),
1502 * so we do not need to update the CPL here.
1504 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1507 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1510 case VCPU_EXREG_PDPTR
:
1511 BUG_ON(!npt_enabled
);
1512 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1519 static void svm_set_vintr(struct vcpu_svm
*svm
)
1521 struct vmcb_control_area
*control
;
1523 /* The following fields are ignored when AVIC is enabled */
1524 WARN_ON(kvm_vcpu_apicv_active(&svm
->vcpu
));
1525 svm_set_intercept(svm
, INTERCEPT_VINTR
);
1528 * This is just a dummy VINTR to actually cause a vmexit to happen.
1529 * Actual injection of virtual interrupts happens through EVENTINJ.
1531 control
= &svm
->vmcb
->control
;
1532 control
->int_vector
= 0x0;
1533 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
1534 control
->int_ctl
|= V_IRQ_MASK
|
1535 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
1536 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTR
);
1539 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1541 const u32 mask
= V_TPR_MASK
| V_GIF_ENABLE_MASK
| V_GIF_MASK
| V_INTR_MASKING_MASK
;
1542 svm_clr_intercept(svm
, INTERCEPT_VINTR
);
1544 /* Drop int_ctl fields related to VINTR injection. */
1545 svm
->vmcb
->control
.int_ctl
&= mask
;
1546 if (is_guest_mode(&svm
->vcpu
)) {
1547 svm
->vmcb01
.ptr
->control
.int_ctl
&= mask
;
1549 WARN_ON((svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
) !=
1550 (svm
->nested
.ctl
.int_ctl
& V_TPR_MASK
));
1551 svm
->vmcb
->control
.int_ctl
|= svm
->nested
.ctl
.int_ctl
& ~mask
;
1554 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTR
);
1557 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1559 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1560 struct vmcb_save_area
*save01
= &to_svm(vcpu
)->vmcb01
.ptr
->save
;
1563 case VCPU_SREG_CS
: return &save
->cs
;
1564 case VCPU_SREG_DS
: return &save
->ds
;
1565 case VCPU_SREG_ES
: return &save
->es
;
1566 case VCPU_SREG_FS
: return &save01
->fs
;
1567 case VCPU_SREG_GS
: return &save01
->gs
;
1568 case VCPU_SREG_SS
: return &save
->ss
;
1569 case VCPU_SREG_TR
: return &save01
->tr
;
1570 case VCPU_SREG_LDTR
: return &save01
->ldtr
;
1576 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1578 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1583 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1584 struct kvm_segment
*var
, int seg
)
1586 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1588 var
->base
= s
->base
;
1589 var
->limit
= s
->limit
;
1590 var
->selector
= s
->selector
;
1591 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1592 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1593 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1594 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1595 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1596 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1597 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1600 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1601 * However, the SVM spec states that the G bit is not observed by the
1602 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1603 * So let's synthesize a legal G bit for all segments, this helps
1604 * running KVM nested. It also helps cross-vendor migration, because
1605 * Intel's vmentry has a check on the 'G' bit.
1607 var
->g
= s
->limit
> 0xfffff;
1610 * AMD's VMCB does not have an explicit unusable field, so emulate it
1611 * for cross vendor migration purposes by "not present"
1613 var
->unusable
= !var
->present
;
1618 * Work around a bug where the busy flag in the tr selector
1628 * The accessed bit must always be set in the segment
1629 * descriptor cache, although it can be cleared in the
1630 * descriptor, the cached bit always remains at 1. Since
1631 * Intel has a check on this, set it here to support
1632 * cross-vendor migration.
1639 * On AMD CPUs sometimes the DB bit in the segment
1640 * descriptor is left as 1, although the whole segment has
1641 * been made unusable. Clear it here to pass an Intel VMX
1642 * entry check when cross vendor migrating.
1646 /* This is symmetric with svm_set_segment() */
1647 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1652 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1654 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1659 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1661 struct vcpu_svm
*svm
= to_svm(vcpu
);
1663 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1664 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1667 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1669 struct vcpu_svm
*svm
= to_svm(vcpu
);
1671 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1672 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1673 vmcb_mark_dirty(svm
->vmcb
, VMCB_DT
);
1676 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1678 struct vcpu_svm
*svm
= to_svm(vcpu
);
1680 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1681 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1684 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1686 struct vcpu_svm
*svm
= to_svm(vcpu
);
1688 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1689 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1690 vmcb_mark_dirty(svm
->vmcb
, VMCB_DT
);
1693 void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1695 struct vcpu_svm
*svm
= to_svm(vcpu
);
1698 #ifdef CONFIG_X86_64
1699 if (vcpu
->arch
.efer
& EFER_LME
&& !vcpu
->arch
.guest_state_protected
) {
1700 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1701 vcpu
->arch
.efer
|= EFER_LMA
;
1702 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1705 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1706 vcpu
->arch
.efer
&= ~EFER_LMA
;
1707 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1711 vcpu
->arch
.cr0
= cr0
;
1714 hcr0
|= X86_CR0_PG
| X86_CR0_WP
;
1717 * re-enable caching here because the QEMU bios
1718 * does not do it - this results in some delay at
1721 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
1722 hcr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1724 svm
->vmcb
->save
.cr0
= hcr0
;
1725 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
1728 * SEV-ES guests must always keep the CR intercepts cleared. CR
1729 * tracking is done using the CR write traps.
1731 if (sev_es_guest(vcpu
->kvm
))
1735 /* Selective CR0 write remains on. */
1736 svm_clr_intercept(svm
, INTERCEPT_CR0_READ
);
1737 svm_clr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1739 svm_set_intercept(svm
, INTERCEPT_CR0_READ
);
1740 svm_set_intercept(svm
, INTERCEPT_CR0_WRITE
);
1744 static bool svm_is_valid_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1749 void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1751 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
1752 unsigned long old_cr4
= vcpu
->arch
.cr4
;
1754 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1755 svm_flush_tlb(vcpu
);
1757 vcpu
->arch
.cr4
= cr4
;
1760 cr4
|= host_cr4_mce
;
1761 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1762 vmcb_mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1764 if ((cr4
^ old_cr4
) & (X86_CR4_OSXSAVE
| X86_CR4_PKE
))
1765 kvm_update_cpuid_runtime(vcpu
);
1768 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1769 struct kvm_segment
*var
, int seg
)
1771 struct vcpu_svm
*svm
= to_svm(vcpu
);
1772 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1774 s
->base
= var
->base
;
1775 s
->limit
= var
->limit
;
1776 s
->selector
= var
->selector
;
1777 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1778 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1779 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1780 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
1781 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1782 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1783 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1784 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1787 * This is always accurate, except if SYSRET returned to a segment
1788 * with SS.DPL != 3. Intel does not have this quirk, and always
1789 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1790 * would entail passing the CPL to userspace and back.
1792 if (seg
== VCPU_SREG_SS
)
1793 /* This is symmetric with svm_get_segment() */
1794 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
1796 vmcb_mark_dirty(svm
->vmcb
, VMCB_SEG
);
1799 static void svm_update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1801 struct vcpu_svm
*svm
= to_svm(vcpu
);
1803 clr_exception_intercept(svm
, BP_VECTOR
);
1805 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1806 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1807 set_exception_intercept(svm
, BP_VECTOR
);
1811 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1813 if (sd
->next_asid
> sd
->max_asid
) {
1814 ++sd
->asid_generation
;
1815 sd
->next_asid
= sd
->min_asid
;
1816 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1817 vmcb_mark_dirty(svm
->vmcb
, VMCB_ASID
);
1820 svm
->current_vmcb
->asid_generation
= sd
->asid_generation
;
1821 svm
->asid
= sd
->next_asid
++;
1824 static void svm_set_dr6(struct vcpu_svm
*svm
, unsigned long value
)
1826 struct vmcb
*vmcb
= svm
->vmcb
;
1828 if (svm
->vcpu
.arch
.guest_state_protected
)
1831 if (unlikely(value
!= vmcb
->save
.dr6
)) {
1832 vmcb
->save
.dr6
= value
;
1833 vmcb_mark_dirty(vmcb
, VMCB_DR
);
1837 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
1839 struct vcpu_svm
*svm
= to_svm(vcpu
);
1841 if (vcpu
->arch
.guest_state_protected
)
1844 get_debugreg(vcpu
->arch
.db
[0], 0);
1845 get_debugreg(vcpu
->arch
.db
[1], 1);
1846 get_debugreg(vcpu
->arch
.db
[2], 2);
1847 get_debugreg(vcpu
->arch
.db
[3], 3);
1849 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1850 * because db_interception might need it. We can do it before vmentry.
1852 vcpu
->arch
.dr6
= svm
->vmcb
->save
.dr6
;
1853 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
1854 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
1855 set_dr_intercepts(svm
);
1858 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1860 struct vcpu_svm
*svm
= to_svm(vcpu
);
1862 if (vcpu
->arch
.guest_state_protected
)
1865 svm
->vmcb
->save
.dr7
= value
;
1866 vmcb_mark_dirty(svm
->vmcb
, VMCB_DR
);
1869 static int pf_interception(struct kvm_vcpu
*vcpu
)
1871 struct vcpu_svm
*svm
= to_svm(vcpu
);
1873 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1874 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
1876 return kvm_handle_page_fault(vcpu
, error_code
, fault_address
,
1877 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
1878 svm
->vmcb
->control
.insn_bytes
: NULL
,
1879 svm
->vmcb
->control
.insn_len
);
1882 static int npf_interception(struct kvm_vcpu
*vcpu
)
1884 struct vcpu_svm
*svm
= to_svm(vcpu
);
1886 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
1887 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
1889 trace_kvm_page_fault(fault_address
, error_code
);
1890 return kvm_mmu_page_fault(vcpu
, fault_address
, error_code
,
1891 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
1892 svm
->vmcb
->control
.insn_bytes
: NULL
,
1893 svm
->vmcb
->control
.insn_len
);
1896 static int db_interception(struct kvm_vcpu
*vcpu
)
1898 struct kvm_run
*kvm_run
= vcpu
->run
;
1899 struct vcpu_svm
*svm
= to_svm(vcpu
);
1901 if (!(vcpu
->guest_debug
&
1902 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1903 !svm
->nmi_singlestep
) {
1904 u32 payload
= svm
->vmcb
->save
.dr6
^ DR6_ACTIVE_LOW
;
1905 kvm_queue_exception_p(vcpu
, DB_VECTOR
, payload
);
1909 if (svm
->nmi_singlestep
) {
1910 disable_nmi_singlestep(svm
);
1911 /* Make sure we check for pending NMIs upon entry */
1912 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1915 if (vcpu
->guest_debug
&
1916 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1917 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1918 kvm_run
->debug
.arch
.dr6
= svm
->vmcb
->save
.dr6
;
1919 kvm_run
->debug
.arch
.dr7
= svm
->vmcb
->save
.dr7
;
1920 kvm_run
->debug
.arch
.pc
=
1921 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1922 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1929 static int bp_interception(struct kvm_vcpu
*vcpu
)
1931 struct vcpu_svm
*svm
= to_svm(vcpu
);
1932 struct kvm_run
*kvm_run
= vcpu
->run
;
1934 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1935 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1936 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1940 static int ud_interception(struct kvm_vcpu
*vcpu
)
1942 return handle_ud(vcpu
);
1945 static int ac_interception(struct kvm_vcpu
*vcpu
)
1947 kvm_queue_exception_e(vcpu
, AC_VECTOR
, 0);
1951 static bool is_erratum_383(void)
1956 if (!erratum_383_found
)
1959 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1963 /* Bit 62 may or may not be set for this mce */
1964 value
&= ~(1ULL << 62);
1966 if (value
!= 0xb600000000010015ULL
)
1969 /* Clear MCi_STATUS registers */
1970 for (i
= 0; i
< 6; ++i
)
1971 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1973 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1977 value
&= ~(1ULL << 2);
1978 low
= lower_32_bits(value
);
1979 high
= upper_32_bits(value
);
1981 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1984 /* Flush tlb to evict multi-match entries */
1990 static void svm_handle_mce(struct kvm_vcpu
*vcpu
)
1992 if (is_erratum_383()) {
1994 * Erratum 383 triggered. Guest state is corrupt so kill the
1997 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1999 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2005 * On an #MC intercept the MCE handler is not called automatically in
2006 * the host. So do it by hand here.
2008 kvm_machine_check();
2011 static int mc_interception(struct kvm_vcpu
*vcpu
)
2016 static int shutdown_interception(struct kvm_vcpu
*vcpu
)
2018 struct kvm_run
*kvm_run
= vcpu
->run
;
2019 struct vcpu_svm
*svm
= to_svm(vcpu
);
2022 * The VM save area has already been encrypted so it
2023 * cannot be reinitialized - just terminate.
2025 if (sev_es_guest(vcpu
->kvm
))
2029 * VMCB is undefined after a SHUTDOWN intercept
2030 * so reinitialize it.
2032 clear_page(svm
->vmcb
);
2035 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2039 static int io_interception(struct kvm_vcpu
*vcpu
)
2041 struct vcpu_svm
*svm
= to_svm(vcpu
);
2042 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2043 int size
, in
, string
;
2046 ++vcpu
->stat
.io_exits
;
2047 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2048 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2049 port
= io_info
>> 16;
2050 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2053 if (sev_es_guest(vcpu
->kvm
))
2054 return sev_es_string_io(svm
, size
, port
, in
);
2056 return kvm_emulate_instruction(vcpu
, 0);
2059 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2061 return kvm_fast_pio(vcpu
, size
, port
, in
);
2064 static int nmi_interception(struct kvm_vcpu
*vcpu
)
2069 static int intr_interception(struct kvm_vcpu
*vcpu
)
2071 ++vcpu
->stat
.irq_exits
;
2075 static int vmload_vmsave_interception(struct kvm_vcpu
*vcpu
, bool vmload
)
2077 struct vcpu_svm
*svm
= to_svm(vcpu
);
2078 struct vmcb
*vmcb12
;
2079 struct kvm_host_map map
;
2082 if (nested_svm_check_permissions(vcpu
))
2085 ret
= kvm_vcpu_map(vcpu
, gpa_to_gfn(svm
->vmcb
->save
.rax
), &map
);
2088 kvm_inject_gp(vcpu
, 0);
2094 ret
= kvm_skip_emulated_instruction(vcpu
);
2097 nested_svm_vmloadsave(vmcb12
, svm
->vmcb
);
2098 svm
->sysenter_eip_hi
= 0;
2099 svm
->sysenter_esp_hi
= 0;
2101 nested_svm_vmloadsave(svm
->vmcb
, vmcb12
);
2103 kvm_vcpu_unmap(vcpu
, &map
, true);
2108 static int vmload_interception(struct kvm_vcpu
*vcpu
)
2110 return vmload_vmsave_interception(vcpu
, true);
2113 static int vmsave_interception(struct kvm_vcpu
*vcpu
)
2115 return vmload_vmsave_interception(vcpu
, false);
2118 static int vmrun_interception(struct kvm_vcpu
*vcpu
)
2120 if (nested_svm_check_permissions(vcpu
))
2123 return nested_svm_vmrun(vcpu
);
2133 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2134 static int svm_instr_opcode(struct kvm_vcpu
*vcpu
)
2136 struct x86_emulate_ctxt
*ctxt
= vcpu
->arch
.emulate_ctxt
;
2138 if (ctxt
->b
!= 0x1 || ctxt
->opcode_len
!= 2)
2139 return NONE_SVM_INSTR
;
2141 switch (ctxt
->modrm
) {
2142 case 0xd8: /* VMRUN */
2143 return SVM_INSTR_VMRUN
;
2144 case 0xda: /* VMLOAD */
2145 return SVM_INSTR_VMLOAD
;
2146 case 0xdb: /* VMSAVE */
2147 return SVM_INSTR_VMSAVE
;
2152 return NONE_SVM_INSTR
;
2155 static int emulate_svm_instr(struct kvm_vcpu
*vcpu
, int opcode
)
2157 const int guest_mode_exit_codes
[] = {
2158 [SVM_INSTR_VMRUN
] = SVM_EXIT_VMRUN
,
2159 [SVM_INSTR_VMLOAD
] = SVM_EXIT_VMLOAD
,
2160 [SVM_INSTR_VMSAVE
] = SVM_EXIT_VMSAVE
,
2162 int (*const svm_instr_handlers
[])(struct kvm_vcpu
*vcpu
) = {
2163 [SVM_INSTR_VMRUN
] = vmrun_interception
,
2164 [SVM_INSTR_VMLOAD
] = vmload_interception
,
2165 [SVM_INSTR_VMSAVE
] = vmsave_interception
,
2167 struct vcpu_svm
*svm
= to_svm(vcpu
);
2170 if (is_guest_mode(vcpu
)) {
2171 /* Returns '1' or -errno on failure, '0' on success. */
2172 ret
= nested_svm_simple_vmexit(svm
, guest_mode_exit_codes
[opcode
]);
2177 return svm_instr_handlers
[opcode
](vcpu
);
2181 * #GP handling code. Note that #GP can be triggered under the following two
2183 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2184 * some AMD CPUs when EAX of these instructions are in the reserved memory
2185 * regions (e.g. SMM memory on host).
2186 * 2) VMware backdoor
2188 static int gp_interception(struct kvm_vcpu
*vcpu
)
2190 struct vcpu_svm
*svm
= to_svm(vcpu
);
2191 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
2194 /* Both #GP cases have zero error_code */
2198 /* Decode the instruction for usage later */
2199 if (x86_decode_emulated_instruction(vcpu
, 0, NULL
, 0) != EMULATION_OK
)
2202 opcode
= svm_instr_opcode(vcpu
);
2204 if (opcode
== NONE_SVM_INSTR
) {
2205 if (!enable_vmware_backdoor
)
2209 * VMware backdoor emulation on #GP interception only handles
2210 * IN{S}, OUT{S}, and RDPMC.
2212 if (!is_guest_mode(vcpu
))
2213 return kvm_emulate_instruction(vcpu
,
2214 EMULTYPE_VMWARE_GP
| EMULTYPE_NO_DECODE
);
2216 return emulate_svm_instr(vcpu
, opcode
);
2219 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
2223 void svm_set_gif(struct vcpu_svm
*svm
, bool value
)
2227 * If VGIF is enabled, the STGI intercept is only added to
2228 * detect the opening of the SMI/NMI window; remove it now.
2229 * Likewise, clear the VINTR intercept, we will set it
2230 * again while processing KVM_REQ_EVENT if needed.
2232 if (vgif_enabled(svm
))
2233 svm_clr_intercept(svm
, INTERCEPT_STGI
);
2234 if (svm_is_intercept(svm
, INTERCEPT_VINTR
))
2235 svm_clear_vintr(svm
);
2238 if (svm
->vcpu
.arch
.smi_pending
||
2239 svm
->vcpu
.arch
.nmi_pending
||
2240 kvm_cpu_has_injectable_intr(&svm
->vcpu
))
2241 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2246 * After a CLGI no interrupts should come. But if vGIF is
2247 * in use, we still rely on the VINTR intercept (rather than
2248 * STGI) to detect an open interrupt window.
2250 if (!vgif_enabled(svm
))
2251 svm_clear_vintr(svm
);
2255 static int stgi_interception(struct kvm_vcpu
*vcpu
)
2259 if (nested_svm_check_permissions(vcpu
))
2262 ret
= kvm_skip_emulated_instruction(vcpu
);
2263 svm_set_gif(to_svm(vcpu
), true);
2267 static int clgi_interception(struct kvm_vcpu
*vcpu
)
2271 if (nested_svm_check_permissions(vcpu
))
2274 ret
= kvm_skip_emulated_instruction(vcpu
);
2275 svm_set_gif(to_svm(vcpu
), false);
2279 static int invlpga_interception(struct kvm_vcpu
*vcpu
)
2281 gva_t gva
= kvm_rax_read(vcpu
);
2282 u32 asid
= kvm_rcx_read(vcpu
);
2284 /* FIXME: Handle an address size prefix. */
2285 if (!is_long_mode(vcpu
))
2288 trace_kvm_invlpga(to_svm(vcpu
)->vmcb
->save
.rip
, asid
, gva
);
2290 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2291 kvm_mmu_invlpg(vcpu
, gva
);
2293 return kvm_skip_emulated_instruction(vcpu
);
2296 static int skinit_interception(struct kvm_vcpu
*vcpu
)
2298 trace_kvm_skinit(to_svm(vcpu
)->vmcb
->save
.rip
, kvm_rax_read(vcpu
));
2300 kvm_queue_exception(vcpu
, UD_VECTOR
);
2304 static int task_switch_interception(struct kvm_vcpu
*vcpu
)
2306 struct vcpu_svm
*svm
= to_svm(vcpu
);
2309 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2310 SVM_EXITINTINFO_TYPE_MASK
;
2311 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2313 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2315 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2316 bool has_error_code
= false;
2319 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2321 if (svm
->vmcb
->control
.exit_info_2
&
2322 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2323 reason
= TASK_SWITCH_IRET
;
2324 else if (svm
->vmcb
->control
.exit_info_2
&
2325 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2326 reason
= TASK_SWITCH_JMP
;
2328 reason
= TASK_SWITCH_GATE
;
2330 reason
= TASK_SWITCH_CALL
;
2332 if (reason
== TASK_SWITCH_GATE
) {
2334 case SVM_EXITINTINFO_TYPE_NMI
:
2335 vcpu
->arch
.nmi_injected
= false;
2337 case SVM_EXITINTINFO_TYPE_EXEPT
:
2338 if (svm
->vmcb
->control
.exit_info_2
&
2339 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2340 has_error_code
= true;
2342 (u32
)svm
->vmcb
->control
.exit_info_2
;
2344 kvm_clear_exception_queue(vcpu
);
2346 case SVM_EXITINTINFO_TYPE_INTR
:
2347 kvm_clear_interrupt_queue(vcpu
);
2354 if (reason
!= TASK_SWITCH_GATE
||
2355 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2356 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2357 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
))) {
2358 if (!skip_emulated_instruction(vcpu
))
2362 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2365 return kvm_task_switch(vcpu
, tss_selector
, int_vec
, reason
,
2366 has_error_code
, error_code
);
2369 static int iret_interception(struct kvm_vcpu
*vcpu
)
2371 struct vcpu_svm
*svm
= to_svm(vcpu
);
2373 ++vcpu
->stat
.nmi_window_exits
;
2374 vcpu
->arch
.hflags
|= HF_IRET_MASK
;
2375 if (!sev_es_guest(vcpu
->kvm
)) {
2376 svm_clr_intercept(svm
, INTERCEPT_IRET
);
2377 svm
->nmi_iret_rip
= kvm_rip_read(vcpu
);
2379 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2383 static int invlpg_interception(struct kvm_vcpu
*vcpu
)
2385 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2386 return kvm_emulate_instruction(vcpu
, 0);
2388 kvm_mmu_invlpg(vcpu
, to_svm(vcpu
)->vmcb
->control
.exit_info_1
);
2389 return kvm_skip_emulated_instruction(vcpu
);
2392 static int emulate_on_interception(struct kvm_vcpu
*vcpu
)
2394 return kvm_emulate_instruction(vcpu
, 0);
2397 static int rsm_interception(struct kvm_vcpu
*vcpu
)
2399 return kvm_emulate_instruction_from_buffer(vcpu
, rsm_ins_bytes
, 2);
2402 static bool check_selective_cr0_intercepted(struct kvm_vcpu
*vcpu
,
2405 struct vcpu_svm
*svm
= to_svm(vcpu
);
2406 unsigned long cr0
= vcpu
->arch
.cr0
;
2409 if (!is_guest_mode(vcpu
) ||
2410 (!(vmcb_is_intercept(&svm
->nested
.ctl
, INTERCEPT_SELECTIVE_CR0
))))
2413 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2414 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2417 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2418 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2424 #define CR_VALID (1ULL << 63)
2426 static int cr_interception(struct kvm_vcpu
*vcpu
)
2428 struct vcpu_svm
*svm
= to_svm(vcpu
);
2433 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2434 return emulate_on_interception(vcpu
);
2436 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2437 return emulate_on_interception(vcpu
);
2439 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2440 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
2441 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
2443 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2446 if (cr
>= 16) { /* mov to cr */
2448 val
= kvm_register_read(vcpu
, reg
);
2449 trace_kvm_cr_write(cr
, val
);
2452 if (!check_selective_cr0_intercepted(vcpu
, val
))
2453 err
= kvm_set_cr0(vcpu
, val
);
2459 err
= kvm_set_cr3(vcpu
, val
);
2462 err
= kvm_set_cr4(vcpu
, val
);
2465 err
= kvm_set_cr8(vcpu
, val
);
2468 WARN(1, "unhandled write to CR%d", cr
);
2469 kvm_queue_exception(vcpu
, UD_VECTOR
);
2472 } else { /* mov from cr */
2475 val
= kvm_read_cr0(vcpu
);
2478 val
= vcpu
->arch
.cr2
;
2481 val
= kvm_read_cr3(vcpu
);
2484 val
= kvm_read_cr4(vcpu
);
2487 val
= kvm_get_cr8(vcpu
);
2490 WARN(1, "unhandled read from CR%d", cr
);
2491 kvm_queue_exception(vcpu
, UD_VECTOR
);
2494 kvm_register_write(vcpu
, reg
, val
);
2495 trace_kvm_cr_read(cr
, val
);
2497 return kvm_complete_insn_gp(vcpu
, err
);
2500 static int cr_trap(struct kvm_vcpu
*vcpu
)
2502 struct vcpu_svm
*svm
= to_svm(vcpu
);
2503 unsigned long old_value
, new_value
;
2507 new_value
= (unsigned long)svm
->vmcb
->control
.exit_info_1
;
2509 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_CR0_WRITE_TRAP
;
2512 old_value
= kvm_read_cr0(vcpu
);
2513 svm_set_cr0(vcpu
, new_value
);
2515 kvm_post_set_cr0(vcpu
, old_value
, new_value
);
2518 old_value
= kvm_read_cr4(vcpu
);
2519 svm_set_cr4(vcpu
, new_value
);
2521 kvm_post_set_cr4(vcpu
, old_value
, new_value
);
2524 ret
= kvm_set_cr8(vcpu
, new_value
);
2527 WARN(1, "unhandled CR%d write trap", cr
);
2528 kvm_queue_exception(vcpu
, UD_VECTOR
);
2532 return kvm_complete_insn_gp(vcpu
, ret
);
2535 static int dr_interception(struct kvm_vcpu
*vcpu
)
2537 struct vcpu_svm
*svm
= to_svm(vcpu
);
2542 if (vcpu
->guest_debug
== 0) {
2544 * No more DR vmexits; force a reload of the debug registers
2545 * and reenter on this instruction. The next vmexit will
2546 * retrieve the full state of the debug registers.
2548 clr_dr_intercepts(svm
);
2549 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
2553 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2554 return emulate_on_interception(vcpu
);
2556 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2557 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2558 if (dr
>= 16) { /* mov to DRn */
2560 val
= kvm_register_read(vcpu
, reg
);
2561 err
= kvm_set_dr(vcpu
, dr
, val
);
2563 kvm_get_dr(vcpu
, dr
, &val
);
2564 kvm_register_write(vcpu
, reg
, val
);
2567 return kvm_complete_insn_gp(vcpu
, err
);
2570 static int cr8_write_interception(struct kvm_vcpu
*vcpu
)
2574 u8 cr8_prev
= kvm_get_cr8(vcpu
);
2575 /* instruction emulation calls kvm_set_cr8() */
2576 r
= cr_interception(vcpu
);
2577 if (lapic_in_kernel(vcpu
))
2579 if (cr8_prev
<= kvm_get_cr8(vcpu
))
2581 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
2585 static int efer_trap(struct kvm_vcpu
*vcpu
)
2587 struct msr_data msr_info
;
2591 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2592 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2593 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2594 * the guest doesn't have X86_FEATURE_SVM.
2596 msr_info
.host_initiated
= false;
2597 msr_info
.index
= MSR_EFER
;
2598 msr_info
.data
= to_svm(vcpu
)->vmcb
->control
.exit_info_1
& ~EFER_SVME
;
2599 ret
= kvm_set_msr_common(vcpu
, &msr_info
);
2601 return kvm_complete_insn_gp(vcpu
, ret
);
2604 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
2608 switch (msr
->index
) {
2609 case MSR_F10H_DECFG
:
2610 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
2611 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
2613 case MSR_IA32_PERF_CAPABILITIES
:
2616 return KVM_MSR_RET_INVALID
;
2622 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2624 struct vcpu_svm
*svm
= to_svm(vcpu
);
2626 switch (msr_info
->index
) {
2628 msr_info
->data
= svm
->vmcb01
.ptr
->save
.star
;
2630 #ifdef CONFIG_X86_64
2632 msr_info
->data
= svm
->vmcb01
.ptr
->save
.lstar
;
2635 msr_info
->data
= svm
->vmcb01
.ptr
->save
.cstar
;
2637 case MSR_KERNEL_GS_BASE
:
2638 msr_info
->data
= svm
->vmcb01
.ptr
->save
.kernel_gs_base
;
2640 case MSR_SYSCALL_MASK
:
2641 msr_info
->data
= svm
->vmcb01
.ptr
->save
.sfmask
;
2644 case MSR_IA32_SYSENTER_CS
:
2645 msr_info
->data
= svm
->vmcb01
.ptr
->save
.sysenter_cs
;
2647 case MSR_IA32_SYSENTER_EIP
:
2648 msr_info
->data
= (u32
)svm
->vmcb01
.ptr
->save
.sysenter_eip
;
2649 if (guest_cpuid_is_intel(vcpu
))
2650 msr_info
->data
|= (u64
)svm
->sysenter_eip_hi
<< 32;
2652 case MSR_IA32_SYSENTER_ESP
:
2653 msr_info
->data
= svm
->vmcb01
.ptr
->save
.sysenter_esp
;
2654 if (guest_cpuid_is_intel(vcpu
))
2655 msr_info
->data
|= (u64
)svm
->sysenter_esp_hi
<< 32;
2658 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
2660 if (!msr_info
->host_initiated
&&
2661 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2663 msr_info
->data
= svm
->tsc_aux
;
2666 * Nobody will change the following 5 values in the VMCB so we can
2667 * safely return them on rdmsr. They will always be 0 until LBRV is
2670 case MSR_IA32_DEBUGCTLMSR
:
2671 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
2673 case MSR_IA32_LASTBRANCHFROMIP
:
2674 msr_info
->data
= svm
->vmcb
->save
.br_from
;
2676 case MSR_IA32_LASTBRANCHTOIP
:
2677 msr_info
->data
= svm
->vmcb
->save
.br_to
;
2679 case MSR_IA32_LASTINTFROMIP
:
2680 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
2682 case MSR_IA32_LASTINTTOIP
:
2683 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
2685 case MSR_VM_HSAVE_PA
:
2686 msr_info
->data
= svm
->nested
.hsave_msr
;
2689 msr_info
->data
= svm
->nested
.vm_cr_msr
;
2691 case MSR_IA32_SPEC_CTRL
:
2692 if (!msr_info
->host_initiated
&&
2693 !guest_has_spec_ctrl_msr(vcpu
))
2696 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL
))
2697 msr_info
->data
= svm
->vmcb
->save
.spec_ctrl
;
2699 msr_info
->data
= svm
->spec_ctrl
;
2701 case MSR_AMD64_VIRT_SPEC_CTRL
:
2702 if (!msr_info
->host_initiated
&&
2703 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
2706 msr_info
->data
= svm
->virt_spec_ctrl
;
2708 case MSR_F15H_IC_CFG
: {
2712 family
= guest_cpuid_family(vcpu
);
2713 model
= guest_cpuid_model(vcpu
);
2715 if (family
< 0 || model
< 0)
2716 return kvm_get_msr_common(vcpu
, msr_info
);
2720 if (family
== 0x15 &&
2721 (model
>= 0x2 && model
< 0x20))
2722 msr_info
->data
= 0x1E;
2725 case MSR_F10H_DECFG
:
2726 msr_info
->data
= svm
->msr_decfg
;
2729 return kvm_get_msr_common(vcpu
, msr_info
);
2734 static int svm_complete_emulated_msr(struct kvm_vcpu
*vcpu
, int err
)
2736 struct vcpu_svm
*svm
= to_svm(vcpu
);
2737 if (!err
|| !sev_es_guest(vcpu
->kvm
) || WARN_ON_ONCE(!svm
->ghcb
))
2738 return kvm_complete_insn_gp(vcpu
, err
);
2740 ghcb_set_sw_exit_info_1(svm
->ghcb
, 1);
2741 ghcb_set_sw_exit_info_2(svm
->ghcb
,
2743 SVM_EVTINJ_TYPE_EXEPT
|
2748 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2750 struct vcpu_svm
*svm
= to_svm(vcpu
);
2751 int svm_dis
, chg_mask
;
2753 if (data
& ~SVM_VM_CR_VALID_MASK
)
2756 chg_mask
= SVM_VM_CR_VALID_MASK
;
2758 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2759 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2761 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2762 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2764 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2766 /* check for svm_disable while efer.svme is set */
2767 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2773 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
2775 struct vcpu_svm
*svm
= to_svm(vcpu
);
2778 u32 ecx
= msr
->index
;
2779 u64 data
= msr
->data
;
2781 case MSR_IA32_CR_PAT
:
2782 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2784 vcpu
->arch
.pat
= data
;
2785 svm
->vmcb01
.ptr
->save
.g_pat
= data
;
2786 if (is_guest_mode(vcpu
))
2787 nested_vmcb02_compute_g_pat(svm
);
2788 vmcb_mark_dirty(svm
->vmcb
, VMCB_NPT
);
2790 case MSR_IA32_SPEC_CTRL
:
2791 if (!msr
->host_initiated
&&
2792 !guest_has_spec_ctrl_msr(vcpu
))
2795 if (kvm_spec_ctrl_test_value(data
))
2798 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL
))
2799 svm
->vmcb
->save
.spec_ctrl
= data
;
2801 svm
->spec_ctrl
= data
;
2807 * When it's written (to non-zero) for the first time, pass
2811 * The handling of the MSR bitmap for L2 guests is done in
2812 * nested_svm_vmrun_msrpm.
2813 * We update the L1 MSR bit as well since it will end up
2814 * touching the MSR anyway now.
2816 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
2818 case MSR_IA32_PRED_CMD
:
2819 if (!msr
->host_initiated
&&
2820 !guest_has_pred_cmd_msr(vcpu
))
2823 if (data
& ~PRED_CMD_IBPB
)
2825 if (!boot_cpu_has(X86_FEATURE_IBPB
))
2830 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
2831 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
2833 case MSR_AMD64_VIRT_SPEC_CTRL
:
2834 if (!msr
->host_initiated
&&
2835 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
2838 if (data
& ~SPEC_CTRL_SSBD
)
2841 svm
->virt_spec_ctrl
= data
;
2844 svm
->vmcb01
.ptr
->save
.star
= data
;
2846 #ifdef CONFIG_X86_64
2848 svm
->vmcb01
.ptr
->save
.lstar
= data
;
2851 svm
->vmcb01
.ptr
->save
.cstar
= data
;
2853 case MSR_KERNEL_GS_BASE
:
2854 svm
->vmcb01
.ptr
->save
.kernel_gs_base
= data
;
2856 case MSR_SYSCALL_MASK
:
2857 svm
->vmcb01
.ptr
->save
.sfmask
= data
;
2860 case MSR_IA32_SYSENTER_CS
:
2861 svm
->vmcb01
.ptr
->save
.sysenter_cs
= data
;
2863 case MSR_IA32_SYSENTER_EIP
:
2864 svm
->vmcb01
.ptr
->save
.sysenter_eip
= (u32
)data
;
2866 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2867 * when we spoof an Intel vendor ID (for cross vendor migration).
2868 * In this case we use this intercept to track the high
2869 * 32 bit part of these msrs to support Intel's
2870 * implementation of SYSENTER/SYSEXIT.
2872 svm
->sysenter_eip_hi
= guest_cpuid_is_intel(vcpu
) ? (data
>> 32) : 0;
2874 case MSR_IA32_SYSENTER_ESP
:
2875 svm
->vmcb01
.ptr
->save
.sysenter_esp
= (u32
)data
;
2876 svm
->sysenter_esp_hi
= guest_cpuid_is_intel(vcpu
) ? (data
>> 32) : 0;
2879 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
2882 if (!msr
->host_initiated
&&
2883 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2887 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
2888 * incomplete and conflicting architectural behavior. Current
2889 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
2890 * reserved and always read as zeros. Emulate AMD CPU behavior
2891 * to avoid explosions if the vCPU is migrated from an AMD host
2897 * TSC_AUX is usually changed only during boot and never read
2898 * directly. Intercept TSC_AUX instead of exposing it to the
2899 * guest via direct_access_msrs, and switch it via user return.
2902 r
= kvm_set_user_return_msr(TSC_AUX_URET_SLOT
, data
, -1ull);
2907 svm
->tsc_aux
= data
;
2909 case MSR_IA32_DEBUGCTLMSR
:
2910 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2911 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2915 if (data
& DEBUGCTL_RESERVED_BITS
)
2918 svm
->vmcb
->save
.dbgctl
= data
;
2919 vmcb_mark_dirty(svm
->vmcb
, VMCB_LBR
);
2920 if (data
& (1ULL<<0))
2921 svm_enable_lbrv(vcpu
);
2923 svm_disable_lbrv(vcpu
);
2925 case MSR_VM_HSAVE_PA
:
2926 svm
->nested
.hsave_msr
= data
;
2929 return svm_set_vm_cr(vcpu
, data
);
2931 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2933 case MSR_F10H_DECFG
: {
2934 struct kvm_msr_entry msr_entry
;
2936 msr_entry
.index
= msr
->index
;
2937 if (svm_get_msr_feature(&msr_entry
))
2940 /* Check the supported bits */
2941 if (data
& ~msr_entry
.data
)
2944 /* Don't allow the guest to change a bit, #GP */
2945 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
2948 svm
->msr_decfg
= data
;
2951 case MSR_IA32_APICBASE
:
2952 if (kvm_vcpu_apicv_active(vcpu
))
2953 avic_update_vapic_bar(to_svm(vcpu
), data
);
2956 return kvm_set_msr_common(vcpu
, msr
);
2961 static int msr_interception(struct kvm_vcpu
*vcpu
)
2963 if (to_svm(vcpu
)->vmcb
->control
.exit_info_1
)
2964 return kvm_emulate_wrmsr(vcpu
);
2966 return kvm_emulate_rdmsr(vcpu
);
2969 static int interrupt_window_interception(struct kvm_vcpu
*vcpu
)
2971 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
2972 svm_clear_vintr(to_svm(vcpu
));
2975 * For AVIC, the only reason to end up here is ExtINTs.
2976 * In this case AVIC was temporarily disabled for
2977 * requesting the IRQ window and we have to re-enable it.
2979 svm_toggle_avic_for_irq_window(vcpu
, true);
2981 ++vcpu
->stat
.irq_window_exits
;
2985 static int pause_interception(struct kvm_vcpu
*vcpu
)
2990 * CPL is not made available for an SEV-ES guest, therefore
2991 * vcpu->arch.preempted_in_kernel can never be true. Just
2992 * set in_kernel to false as well.
2994 in_kernel
= !sev_es_guest(vcpu
->kvm
) && svm_get_cpl(vcpu
) == 0;
2996 if (!kvm_pause_in_guest(vcpu
->kvm
))
2997 grow_ple_window(vcpu
);
2999 kvm_vcpu_on_spin(vcpu
, in_kernel
);
3000 return kvm_skip_emulated_instruction(vcpu
);
3003 static int invpcid_interception(struct kvm_vcpu
*vcpu
)
3005 struct vcpu_svm
*svm
= to_svm(vcpu
);
3009 if (!guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
)) {
3010 kvm_queue_exception(vcpu
, UD_VECTOR
);
3015 * For an INVPCID intercept:
3016 * EXITINFO1 provides the linear address of the memory operand.
3017 * EXITINFO2 provides the contents of the register operand.
3019 type
= svm
->vmcb
->control
.exit_info_2
;
3020 gva
= svm
->vmcb
->control
.exit_info_1
;
3023 kvm_inject_gp(vcpu
, 0);
3027 return kvm_handle_invpcid(vcpu
, type
, gva
);
3030 static int (*const svm_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3031 [SVM_EXIT_READ_CR0
] = cr_interception
,
3032 [SVM_EXIT_READ_CR3
] = cr_interception
,
3033 [SVM_EXIT_READ_CR4
] = cr_interception
,
3034 [SVM_EXIT_READ_CR8
] = cr_interception
,
3035 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
3036 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3037 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3038 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3039 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3040 [SVM_EXIT_READ_DR0
] = dr_interception
,
3041 [SVM_EXIT_READ_DR1
] = dr_interception
,
3042 [SVM_EXIT_READ_DR2
] = dr_interception
,
3043 [SVM_EXIT_READ_DR3
] = dr_interception
,
3044 [SVM_EXIT_READ_DR4
] = dr_interception
,
3045 [SVM_EXIT_READ_DR5
] = dr_interception
,
3046 [SVM_EXIT_READ_DR6
] = dr_interception
,
3047 [SVM_EXIT_READ_DR7
] = dr_interception
,
3048 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3049 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3050 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3051 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3052 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3053 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3054 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3055 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3056 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3057 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3058 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3059 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3060 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3061 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
3062 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
3063 [SVM_EXIT_INTR
] = intr_interception
,
3064 [SVM_EXIT_NMI
] = nmi_interception
,
3065 [SVM_EXIT_SMI
] = kvm_emulate_as_nop
,
3066 [SVM_EXIT_INIT
] = kvm_emulate_as_nop
,
3067 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3068 [SVM_EXIT_RDPMC
] = kvm_emulate_rdpmc
,
3069 [SVM_EXIT_CPUID
] = kvm_emulate_cpuid
,
3070 [SVM_EXIT_IRET
] = iret_interception
,
3071 [SVM_EXIT_INVD
] = kvm_emulate_invd
,
3072 [SVM_EXIT_PAUSE
] = pause_interception
,
3073 [SVM_EXIT_HLT
] = kvm_emulate_halt
,
3074 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3075 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3076 [SVM_EXIT_IOIO
] = io_interception
,
3077 [SVM_EXIT_MSR
] = msr_interception
,
3078 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3079 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3080 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3081 [SVM_EXIT_VMMCALL
] = kvm_emulate_hypercall
,
3082 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3083 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3084 [SVM_EXIT_STGI
] = stgi_interception
,
3085 [SVM_EXIT_CLGI
] = clgi_interception
,
3086 [SVM_EXIT_SKINIT
] = skinit_interception
,
3087 [SVM_EXIT_WBINVD
] = kvm_emulate_wbinvd
,
3088 [SVM_EXIT_MONITOR
] = kvm_emulate_monitor
,
3089 [SVM_EXIT_MWAIT
] = kvm_emulate_mwait
,
3090 [SVM_EXIT_XSETBV
] = kvm_emulate_xsetbv
,
3091 [SVM_EXIT_RDPRU
] = kvm_handle_invalid_op
,
3092 [SVM_EXIT_EFER_WRITE_TRAP
] = efer_trap
,
3093 [SVM_EXIT_CR0_WRITE_TRAP
] = cr_trap
,
3094 [SVM_EXIT_CR4_WRITE_TRAP
] = cr_trap
,
3095 [SVM_EXIT_CR8_WRITE_TRAP
] = cr_trap
,
3096 [SVM_EXIT_INVPCID
] = invpcid_interception
,
3097 [SVM_EXIT_NPF
] = npf_interception
,
3098 [SVM_EXIT_RSM
] = rsm_interception
,
3099 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
3100 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
3101 [SVM_EXIT_VMGEXIT
] = sev_handle_vmgexit
,
3104 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3106 struct vcpu_svm
*svm
= to_svm(vcpu
);
3107 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3108 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3109 struct vmcb_save_area
*save01
= &svm
->vmcb01
.ptr
->save
;
3111 if (!dump_invalid_vmcb
) {
3112 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3116 pr_err("VMCB Control Area:\n");
3117 pr_err("%-20s%04x\n", "cr_read:", control
->intercepts
[INTERCEPT_CR
] & 0xffff);
3118 pr_err("%-20s%04x\n", "cr_write:", control
->intercepts
[INTERCEPT_CR
] >> 16);
3119 pr_err("%-20s%04x\n", "dr_read:", control
->intercepts
[INTERCEPT_DR
] & 0xffff);
3120 pr_err("%-20s%04x\n", "dr_write:", control
->intercepts
[INTERCEPT_DR
] >> 16);
3121 pr_err("%-20s%08x\n", "exceptions:", control
->intercepts
[INTERCEPT_EXCEPTION
]);
3122 pr_err("%-20s%08x %08x\n", "intercepts:",
3123 control
->intercepts
[INTERCEPT_WORD3
],
3124 control
->intercepts
[INTERCEPT_WORD4
]);
3125 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3126 pr_err("%-20s%d\n", "pause filter threshold:",
3127 control
->pause_filter_thresh
);
3128 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3129 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3130 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3131 pr_err("%-20s%d\n", "asid:", control
->asid
);
3132 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3133 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3134 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3135 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3136 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3137 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3138 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3139 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3140 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3141 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3142 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3143 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
3144 pr_err("%-20s%016llx\n", "ghcb:", control
->ghcb_gpa
);
3145 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3146 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3147 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
3148 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3149 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
3150 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
3151 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
3152 pr_err("%-20s%016llx\n", "vmsa_pa:", control
->vmsa_pa
);
3153 pr_err("VMCB State Save Area:\n");
3154 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3156 save
->es
.selector
, save
->es
.attrib
,
3157 save
->es
.limit
, save
->es
.base
);
3158 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3160 save
->cs
.selector
, save
->cs
.attrib
,
3161 save
->cs
.limit
, save
->cs
.base
);
3162 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3164 save
->ss
.selector
, save
->ss
.attrib
,
3165 save
->ss
.limit
, save
->ss
.base
);
3166 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3168 save
->ds
.selector
, save
->ds
.attrib
,
3169 save
->ds
.limit
, save
->ds
.base
);
3170 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3172 save01
->fs
.selector
, save01
->fs
.attrib
,
3173 save01
->fs
.limit
, save01
->fs
.base
);
3174 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3176 save01
->gs
.selector
, save01
->gs
.attrib
,
3177 save01
->gs
.limit
, save01
->gs
.base
);
3178 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3180 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3181 save
->gdtr
.limit
, save
->gdtr
.base
);
3182 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3184 save01
->ldtr
.selector
, save01
->ldtr
.attrib
,
3185 save01
->ldtr
.limit
, save01
->ldtr
.base
);
3186 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3188 save
->idtr
.selector
, save
->idtr
.attrib
,
3189 save
->idtr
.limit
, save
->idtr
.base
);
3190 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3192 save01
->tr
.selector
, save01
->tr
.attrib
,
3193 save01
->tr
.limit
, save01
->tr
.base
);
3194 pr_err("cpl: %d efer: %016llx\n",
3195 save
->cpl
, save
->efer
);
3196 pr_err("%-15s %016llx %-13s %016llx\n",
3197 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3198 pr_err("%-15s %016llx %-13s %016llx\n",
3199 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3200 pr_err("%-15s %016llx %-13s %016llx\n",
3201 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3202 pr_err("%-15s %016llx %-13s %016llx\n",
3203 "rip:", save
->rip
, "rflags:", save
->rflags
);
3204 pr_err("%-15s %016llx %-13s %016llx\n",
3205 "rsp:", save
->rsp
, "rax:", save
->rax
);
3206 pr_err("%-15s %016llx %-13s %016llx\n",
3207 "star:", save01
->star
, "lstar:", save01
->lstar
);
3208 pr_err("%-15s %016llx %-13s %016llx\n",
3209 "cstar:", save01
->cstar
, "sfmask:", save01
->sfmask
);
3210 pr_err("%-15s %016llx %-13s %016llx\n",
3211 "kernel_gs_base:", save01
->kernel_gs_base
,
3212 "sysenter_cs:", save01
->sysenter_cs
);
3213 pr_err("%-15s %016llx %-13s %016llx\n",
3214 "sysenter_esp:", save01
->sysenter_esp
,
3215 "sysenter_eip:", save01
->sysenter_eip
);
3216 pr_err("%-15s %016llx %-13s %016llx\n",
3217 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3218 pr_err("%-15s %016llx %-13s %016llx\n",
3219 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3220 pr_err("%-15s %016llx %-13s %016llx\n",
3221 "excp_from:", save
->last_excp_from
,
3222 "excp_to:", save
->last_excp_to
);
3225 static int svm_handle_invalid_exit(struct kvm_vcpu
*vcpu
, u64 exit_code
)
3227 if (exit_code
< ARRAY_SIZE(svm_exit_handlers
) &&
3228 svm_exit_handlers
[exit_code
])
3231 vcpu_unimpl(vcpu
, "svm: unexpected exit reason 0x%llx\n", exit_code
);
3233 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3234 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON
;
3235 vcpu
->run
->internal
.ndata
= 2;
3236 vcpu
->run
->internal
.data
[0] = exit_code
;
3237 vcpu
->run
->internal
.data
[1] = vcpu
->arch
.last_vmentry_cpu
;
3242 int svm_invoke_exit_handler(struct kvm_vcpu
*vcpu
, u64 exit_code
)
3244 if (svm_handle_invalid_exit(vcpu
, exit_code
))
3247 #ifdef CONFIG_RETPOLINE
3248 if (exit_code
== SVM_EXIT_MSR
)
3249 return msr_interception(vcpu
);
3250 else if (exit_code
== SVM_EXIT_VINTR
)
3251 return interrupt_window_interception(vcpu
);
3252 else if (exit_code
== SVM_EXIT_INTR
)
3253 return intr_interception(vcpu
);
3254 else if (exit_code
== SVM_EXIT_HLT
)
3255 return kvm_emulate_halt(vcpu
);
3256 else if (exit_code
== SVM_EXIT_NPF
)
3257 return npf_interception(vcpu
);
3259 return svm_exit_handlers
[exit_code
](vcpu
);
3262 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
,
3263 u32
*intr_info
, u32
*error_code
)
3265 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3267 *info1
= control
->exit_info_1
;
3268 *info2
= control
->exit_info_2
;
3269 *intr_info
= control
->exit_int_info
;
3270 if ((*intr_info
& SVM_EXITINTINFO_VALID
) &&
3271 (*intr_info
& SVM_EXITINTINFO_VALID_ERR
))
3272 *error_code
= control
->exit_int_info_err
;
3277 static int handle_exit(struct kvm_vcpu
*vcpu
, fastpath_t exit_fastpath
)
3279 struct vcpu_svm
*svm
= to_svm(vcpu
);
3280 struct kvm_run
*kvm_run
= vcpu
->run
;
3281 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3283 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3285 /* SEV-ES guests must use the CR write traps to track CR registers. */
3286 if (!sev_es_guest(vcpu
->kvm
)) {
3287 if (!svm_is_intercept(svm
, INTERCEPT_CR0_WRITE
))
3288 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3290 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3293 if (is_guest_mode(vcpu
)) {
3296 trace_kvm_nested_vmexit(exit_code
, vcpu
, KVM_ISA_SVM
);
3298 vmexit
= nested_svm_exit_special(svm
);
3300 if (vmexit
== NESTED_EXIT_CONTINUE
)
3301 vmexit
= nested_svm_exit_handled(svm
);
3303 if (vmexit
== NESTED_EXIT_DONE
)
3307 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3308 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3309 kvm_run
->fail_entry
.hardware_entry_failure_reason
3310 = svm
->vmcb
->control
.exit_code
;
3311 kvm_run
->fail_entry
.cpu
= vcpu
->arch
.last_vmentry_cpu
;
3316 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3317 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3318 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3319 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3320 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
3322 __func__
, svm
->vmcb
->control
.exit_int_info
,
3325 if (exit_fastpath
!= EXIT_FASTPATH_NONE
)
3328 return svm_invoke_exit_handler(vcpu
, exit_code
);
3331 static void reload_tss(struct kvm_vcpu
*vcpu
)
3333 struct svm_cpu_data
*sd
= per_cpu(svm_data
, vcpu
->cpu
);
3335 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3339 static void pre_svm_run(struct kvm_vcpu
*vcpu
)
3341 struct svm_cpu_data
*sd
= per_cpu(svm_data
, vcpu
->cpu
);
3342 struct vcpu_svm
*svm
= to_svm(vcpu
);
3345 * If the previous vmrun of the vmcb occurred on a different physical
3346 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3347 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3349 if (unlikely(svm
->current_vmcb
->cpu
!= vcpu
->cpu
)) {
3350 svm
->current_vmcb
->asid_generation
= 0;
3351 vmcb_mark_all_dirty(svm
->vmcb
);
3352 svm
->current_vmcb
->cpu
= vcpu
->cpu
;
3355 if (sev_guest(vcpu
->kvm
))
3356 return pre_sev_run(svm
, vcpu
->cpu
);
3358 /* FIXME: handle wraparound of asid_generation */
3359 if (svm
->current_vmcb
->asid_generation
!= sd
->asid_generation
)
3363 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3365 struct vcpu_svm
*svm
= to_svm(vcpu
);
3367 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3368 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3369 if (!sev_es_guest(vcpu
->kvm
))
3370 svm_set_intercept(svm
, INTERCEPT_IRET
);
3371 ++vcpu
->stat
.nmi_injections
;
3374 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3376 struct vcpu_svm
*svm
= to_svm(vcpu
);
3378 BUG_ON(!(gif_set(svm
)));
3380 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3381 ++vcpu
->stat
.irq_injections
;
3383 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3384 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3387 static void svm_update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3389 struct vcpu_svm
*svm
= to_svm(vcpu
);
3392 * SEV-ES guests must always keep the CR intercepts cleared. CR
3393 * tracking is done using the CR write traps.
3395 if (sev_es_guest(vcpu
->kvm
))
3398 if (nested_svm_virtualize_tpr(vcpu
))
3401 svm_clr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3407 svm_set_intercept(svm
, INTERCEPT_CR8_WRITE
);
3410 bool svm_nmi_blocked(struct kvm_vcpu
*vcpu
)
3412 struct vcpu_svm
*svm
= to_svm(vcpu
);
3413 struct vmcb
*vmcb
= svm
->vmcb
;
3419 if (is_guest_mode(vcpu
) && nested_exit_on_nmi(svm
))
3422 ret
= (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) ||
3423 (vcpu
->arch
.hflags
& HF_NMI_MASK
);
3428 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
3430 struct vcpu_svm
*svm
= to_svm(vcpu
);
3431 if (svm
->nested
.nested_run_pending
)
3434 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3435 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_nmi(svm
))
3438 return !svm_nmi_blocked(vcpu
);
3441 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3443 return !!(vcpu
->arch
.hflags
& HF_NMI_MASK
);
3446 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3448 struct vcpu_svm
*svm
= to_svm(vcpu
);
3451 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3452 if (!sev_es_guest(vcpu
->kvm
))
3453 svm_set_intercept(svm
, INTERCEPT_IRET
);
3455 vcpu
->arch
.hflags
&= ~HF_NMI_MASK
;
3456 if (!sev_es_guest(vcpu
->kvm
))
3457 svm_clr_intercept(svm
, INTERCEPT_IRET
);
3461 bool svm_interrupt_blocked(struct kvm_vcpu
*vcpu
)
3463 struct vcpu_svm
*svm
= to_svm(vcpu
);
3464 struct vmcb
*vmcb
= svm
->vmcb
;
3469 if (sev_es_guest(vcpu
->kvm
)) {
3471 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3472 * bit to determine the state of the IF flag.
3474 if (!(vmcb
->control
.int_state
& SVM_GUEST_INTERRUPT_MASK
))
3476 } else if (is_guest_mode(vcpu
)) {
3477 /* As long as interrupts are being delivered... */
3478 if ((svm
->nested
.ctl
.int_ctl
& V_INTR_MASKING_MASK
)
3479 ? !(svm
->vmcb01
.ptr
->save
.rflags
& X86_EFLAGS_IF
)
3480 : !(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
))
3483 /* ... vmexits aren't blocked by the interrupt shadow */
3484 if (nested_exit_on_intr(svm
))
3487 if (!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
))
3491 return (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
);
3494 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
3496 struct vcpu_svm
*svm
= to_svm(vcpu
);
3497 if (svm
->nested
.nested_run_pending
)
3501 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3502 * e.g. if the IRQ arrived asynchronously after checking nested events.
3504 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_intr(svm
))
3507 return !svm_interrupt_blocked(vcpu
);
3510 static void svm_enable_irq_window(struct kvm_vcpu
*vcpu
)
3512 struct vcpu_svm
*svm
= to_svm(vcpu
);
3515 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3516 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3517 * get that intercept, this function will be called again though and
3518 * we'll get the vintr intercept. However, if the vGIF feature is
3519 * enabled, the STGI interception will not occur. Enable the irq
3520 * window under the assumption that the hardware will set the GIF.
3522 if (vgif_enabled(svm
) || gif_set(svm
)) {
3524 * IRQ window is not needed when AVIC is enabled,
3525 * unless we have pending ExtINT since it cannot be injected
3526 * via AVIC. In such case, we need to temporarily disable AVIC,
3527 * and fallback to injecting IRQ via V_IRQ.
3529 svm_toggle_avic_for_irq_window(vcpu
, false);
3534 static void svm_enable_nmi_window(struct kvm_vcpu
*vcpu
)
3536 struct vcpu_svm
*svm
= to_svm(vcpu
);
3538 if ((vcpu
->arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
)) == HF_NMI_MASK
)
3539 return; /* IRET will cause a vm exit */
3541 if (!gif_set(svm
)) {
3542 if (vgif_enabled(svm
))
3543 svm_set_intercept(svm
, INTERCEPT_STGI
);
3544 return; /* STGI will cause a vm exit */
3548 * Something prevents NMI from been injected. Single step over possible
3549 * problem (IRET or exception injection or interrupt shadow)
3551 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
3552 svm
->nmi_singlestep
= true;
3553 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3556 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3561 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
3566 void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3568 struct vcpu_svm
*svm
= to_svm(vcpu
);
3571 * Flush only the current ASID even if the TLB flush was invoked via
3572 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3573 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3574 * unconditionally does a TLB flush on both nested VM-Enter and nested
3575 * VM-Exit (via kvm_mmu_reset_context()).
3577 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3578 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3580 svm
->current_vmcb
->asid_generation
--;
3583 static void svm_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t gva
)
3585 struct vcpu_svm
*svm
= to_svm(vcpu
);
3587 invlpga(gva
, svm
->vmcb
->control
.asid
);
3590 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3592 struct vcpu_svm
*svm
= to_svm(vcpu
);
3594 if (nested_svm_virtualize_tpr(vcpu
))
3597 if (!svm_is_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3598 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3599 kvm_set_cr8(vcpu
, cr8
);
3603 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3605 struct vcpu_svm
*svm
= to_svm(vcpu
);
3608 if (nested_svm_virtualize_tpr(vcpu
) ||
3609 kvm_vcpu_apicv_active(vcpu
))
3612 cr8
= kvm_get_cr8(vcpu
);
3613 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3614 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3617 static void svm_complete_interrupts(struct kvm_vcpu
*vcpu
)
3619 struct vcpu_svm
*svm
= to_svm(vcpu
);
3622 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3623 unsigned int3_injected
= svm
->int3_injected
;
3625 svm
->int3_injected
= 0;
3628 * If we've made progress since setting HF_IRET_MASK, we've
3629 * executed an IRET and can allow NMI injection.
3631 if ((vcpu
->arch
.hflags
& HF_IRET_MASK
) &&
3632 (sev_es_guest(vcpu
->kvm
) ||
3633 kvm_rip_read(vcpu
) != svm
->nmi_iret_rip
)) {
3634 vcpu
->arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3635 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3638 vcpu
->arch
.nmi_injected
= false;
3639 kvm_clear_exception_queue(vcpu
);
3640 kvm_clear_interrupt_queue(vcpu
);
3642 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3645 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3647 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3648 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3651 case SVM_EXITINTINFO_TYPE_NMI
:
3652 vcpu
->arch
.nmi_injected
= true;
3654 case SVM_EXITINTINFO_TYPE_EXEPT
:
3656 * Never re-inject a #VC exception.
3658 if (vector
== X86_TRAP_VC
)
3662 * In case of software exceptions, do not reinject the vector,
3663 * but re-execute the instruction instead. Rewind RIP first
3664 * if we emulated INT3 before.
3666 if (kvm_exception_is_soft(vector
)) {
3667 if (vector
== BP_VECTOR
&& int3_injected
&&
3668 kvm_is_linear_rip(vcpu
, svm
->int3_rip
))
3670 kvm_rip_read(vcpu
) - int3_injected
);
3673 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3674 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3675 kvm_requeue_exception_e(vcpu
, vector
, err
);
3678 kvm_requeue_exception(vcpu
, vector
);
3680 case SVM_EXITINTINFO_TYPE_INTR
:
3681 kvm_queue_interrupt(vcpu
, vector
, false);
3688 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3690 struct vcpu_svm
*svm
= to_svm(vcpu
);
3691 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3693 control
->exit_int_info
= control
->event_inj
;
3694 control
->exit_int_info_err
= control
->event_inj_err
;
3695 control
->event_inj
= 0;
3696 svm_complete_interrupts(vcpu
);
3699 static fastpath_t
svm_exit_handlers_fastpath(struct kvm_vcpu
*vcpu
)
3701 if (to_svm(vcpu
)->vmcb
->control
.exit_code
== SVM_EXIT_MSR
&&
3702 to_svm(vcpu
)->vmcb
->control
.exit_info_1
)
3703 return handle_fastpath_set_msr_irqoff(vcpu
);
3705 return EXIT_FASTPATH_NONE
;
3708 static noinstr
void svm_vcpu_enter_exit(struct kvm_vcpu
*vcpu
)
3710 struct vcpu_svm
*svm
= to_svm(vcpu
);
3711 unsigned long vmcb_pa
= svm
->current_vmcb
->pa
;
3714 * VMENTER enables interrupts (host state), but the kernel state is
3715 * interrupts disabled when this is invoked. Also tell RCU about
3716 * it. This is the same logic as for exit_to_user_mode().
3718 * This ensures that e.g. latency analysis on the host observes
3719 * guest mode as interrupt enabled.
3721 * guest_enter_irqoff() informs context tracking about the
3722 * transition to guest mode and if enabled adjusts RCU state
3725 instrumentation_begin();
3726 trace_hardirqs_on_prepare();
3727 lockdep_hardirqs_on_prepare(CALLER_ADDR0
);
3728 instrumentation_end();
3730 guest_enter_irqoff();
3731 lockdep_hardirqs_on(CALLER_ADDR0
);
3733 if (sev_es_guest(vcpu
->kvm
)) {
3734 __svm_sev_es_vcpu_run(vmcb_pa
);
3736 struct svm_cpu_data
*sd
= per_cpu(svm_data
, vcpu
->cpu
);
3739 * Use a single vmcb (vmcb01 because it's always valid) for
3740 * context switching guest state via VMLOAD/VMSAVE, that way
3741 * the state doesn't need to be copied between vmcb01 and
3742 * vmcb02 when switching vmcbs for nested virtualization.
3744 vmload(svm
->vmcb01
.pa
);
3745 __svm_vcpu_run(vmcb_pa
, (unsigned long *)&vcpu
->arch
.regs
);
3746 vmsave(svm
->vmcb01
.pa
);
3748 vmload(__sme_page_pa(sd
->save_area
));
3752 * VMEXIT disables interrupts (host state), but tracing and lockdep
3753 * have them in state 'on' as recorded before entering guest mode.
3754 * Same as enter_from_user_mode().
3756 * context_tracking_guest_exit() restores host context and reinstates
3757 * RCU if enabled and required.
3759 * This needs to be done before the below as native_read_msr()
3760 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3761 * into world and some more.
3763 lockdep_hardirqs_off(CALLER_ADDR0
);
3764 context_tracking_guest_exit();
3766 instrumentation_begin();
3767 trace_hardirqs_off_finish();
3768 instrumentation_end();
3771 static __no_kcsan fastpath_t
svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3773 struct vcpu_svm
*svm
= to_svm(vcpu
);
3775 trace_kvm_entry(vcpu
);
3777 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3778 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3779 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3782 * Disable singlestep if we're injecting an interrupt/exception.
3783 * We don't want our modified rflags to be pushed on the stack where
3784 * we might not be able to easily reset them if we disabled NMI
3787 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
3789 * Event injection happens before external interrupts cause a
3790 * vmexit and interrupts are disabled here, so smp_send_reschedule
3791 * is enough to force an immediate vmexit.
3793 disable_nmi_singlestep(svm
);
3794 smp_send_reschedule(vcpu
->cpu
);
3799 sync_lapic_to_cr8(vcpu
);
3801 if (unlikely(svm
->asid
!= svm
->vmcb
->control
.asid
)) {
3802 svm
->vmcb
->control
.asid
= svm
->asid
;
3803 vmcb_mark_dirty(svm
->vmcb
, VMCB_ASID
);
3805 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3808 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3811 if (unlikely(vcpu
->arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
))
3812 svm_set_dr6(svm
, vcpu
->arch
.dr6
);
3814 svm_set_dr6(svm
, DR6_ACTIVE_LOW
);
3817 kvm_load_guest_xsave_state(vcpu
);
3819 kvm_wait_lapic_expire(vcpu
);
3822 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3823 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3824 * is no need to worry about the conditional branch over the wrmsr
3825 * being speculatively taken.
3827 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL
))
3828 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
3830 svm_vcpu_enter_exit(vcpu
);
3833 * We do not use IBRS in the kernel. If this vCPU has used the
3834 * SPEC_CTRL MSR it may have left it on; save the value and
3835 * turn it off. This is much more efficient than blindly adding
3836 * it to the atomic save/restore list. Especially as the former
3837 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3839 * For non-nested case:
3840 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3844 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3847 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL
) &&
3848 unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
3849 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
3851 if (!sev_es_guest(vcpu
->kvm
))
3854 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL
))
3855 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
3857 if (!sev_es_guest(vcpu
->kvm
)) {
3858 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3859 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3860 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3861 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3864 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3865 kvm_before_interrupt(vcpu
);
3867 kvm_load_host_xsave_state(vcpu
);
3870 /* Any pending NMI will happen here */
3872 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3873 kvm_after_interrupt(vcpu
);
3875 sync_cr8_to_lapic(vcpu
);
3878 if (is_guest_mode(vcpu
)) {
3879 nested_sync_control_from_vmcb02(svm
);
3880 svm
->nested
.nested_run_pending
= 0;
3883 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3884 vmcb_mark_all_clean(svm
->vmcb
);
3886 /* if exit due to PF check for async PF */
3887 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3888 vcpu
->arch
.apf
.host_apf_flags
=
3889 kvm_read_and_reset_apf_flags();
3892 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3893 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3897 * We need to handle MC intercepts here before the vcpu has a chance to
3898 * change the physical cpu
3900 if (unlikely(svm
->vmcb
->control
.exit_code
==
3901 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3902 svm_handle_mce(vcpu
);
3904 svm_complete_interrupts(vcpu
);
3906 if (is_guest_mode(vcpu
))
3907 return EXIT_FASTPATH_NONE
;
3909 return svm_exit_handlers_fastpath(vcpu
);
3912 static void svm_load_mmu_pgd(struct kvm_vcpu
*vcpu
, hpa_t root_hpa
,
3915 struct vcpu_svm
*svm
= to_svm(vcpu
);
3919 svm
->vmcb
->control
.nested_cr3
= __sme_set(root_hpa
);
3920 vmcb_mark_dirty(svm
->vmcb
, VMCB_NPT
);
3922 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3923 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3925 cr3
= vcpu
->arch
.cr3
;
3926 } else if (vcpu
->arch
.mmu
->shadow_root_level
>= PT64_ROOT_4LEVEL
) {
3927 cr3
= __sme_set(root_hpa
) | kvm_get_active_pcid(vcpu
);
3929 /* PCID in the guest should be impossible with a 32-bit MMU. */
3930 WARN_ON_ONCE(kvm_get_active_pcid(vcpu
));
3934 svm
->vmcb
->save
.cr3
= cr3
;
3935 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
3938 static int is_disabled(void)
3942 rdmsrl(MSR_VM_CR
, vm_cr
);
3943 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3950 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3953 * Patch in the VMMCALL instruction:
3955 hypercall
[0] = 0x0f;
3956 hypercall
[1] = 0x01;
3957 hypercall
[2] = 0xd9;
3960 static int __init
svm_check_processor_compat(void)
3965 static bool svm_cpu_has_accelerated_tpr(void)
3971 * The kvm parameter can be NULL (module initialization, or invocation before
3972 * VM creation). Be sure to check the kvm parameter before using it.
3974 static bool svm_has_emulated_msr(struct kvm
*kvm
, u32 index
)
3977 case MSR_IA32_MCG_EXT_CTL
:
3978 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3980 case MSR_IA32_SMBASE
:
3981 /* SEV-ES guests do not support SMM, so report false */
3982 if (kvm
&& sev_es_guest(kvm
))
3992 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3997 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu
*vcpu
)
3999 struct vcpu_svm
*svm
= to_svm(vcpu
);
4000 struct kvm_cpuid_entry2
*best
;
4002 vcpu
->arch
.xsaves_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
4003 boot_cpu_has(X86_FEATURE_XSAVE
) &&
4004 boot_cpu_has(X86_FEATURE_XSAVES
);
4006 /* Update nrips enabled cache */
4007 svm
->nrips_enabled
= kvm_cpu_cap_has(X86_FEATURE_NRIPS
) &&
4008 guest_cpuid_has(vcpu
, X86_FEATURE_NRIPS
);
4010 /* Check again if INVPCID interception if required */
4011 svm_check_invpcid(svm
);
4013 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4014 if (sev_guest(vcpu
->kvm
)) {
4015 best
= kvm_find_cpuid_entry(vcpu
, 0x8000001F, 0);
4017 vcpu
->arch
.reserved_gpa_bits
&= ~(1UL << (best
->ebx
& 0x3f));
4020 if (kvm_vcpu_apicv_active(vcpu
)) {
4022 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4023 * is exposed to the guest, disable AVIC.
4025 if (guest_cpuid_has(vcpu
, X86_FEATURE_X2APIC
))
4026 kvm_request_apicv_update(vcpu
->kvm
, false,
4027 APICV_INHIBIT_REASON_X2APIC
);
4030 * Currently, AVIC does not work with nested virtualization.
4031 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4033 if (nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_SVM
))
4034 kvm_request_apicv_update(vcpu
->kvm
, false,
4035 APICV_INHIBIT_REASON_NESTED
);
4038 if (guest_cpuid_is_intel(vcpu
)) {
4040 * We must intercept SYSENTER_EIP and SYSENTER_ESP
4041 * accesses because the processor only stores 32 bits.
4042 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4044 svm_set_intercept(svm
, INTERCEPT_VMLOAD
);
4045 svm_set_intercept(svm
, INTERCEPT_VMSAVE
);
4046 svm
->vmcb
->control
.virt_ext
&= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
4048 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SYSENTER_EIP
, 0, 0);
4049 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SYSENTER_ESP
, 0, 0);
4052 * If hardware supports Virtual VMLOAD VMSAVE then enable it
4053 * in VMCB and clear intercepts to avoid #VMEXIT.
4056 svm_clr_intercept(svm
, INTERCEPT_VMLOAD
);
4057 svm_clr_intercept(svm
, INTERCEPT_VMSAVE
);
4058 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
4060 /* No need to intercept these MSRs */
4061 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SYSENTER_EIP
, 1, 1);
4062 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SYSENTER_ESP
, 1, 1);
4066 static bool svm_has_wbinvd_exit(void)
4071 #define PRE_EX(exit) { .exit_code = (exit), \
4072 .stage = X86_ICPT_PRE_EXCEPT, }
4073 #define POST_EX(exit) { .exit_code = (exit), \
4074 .stage = X86_ICPT_POST_EXCEPT, }
4075 #define POST_MEM(exit) { .exit_code = (exit), \
4076 .stage = X86_ICPT_POST_MEMACCESS, }
4078 static const struct __x86_intercept
{
4080 enum x86_intercept_stage stage
;
4081 } x86_intercept_map
[] = {
4082 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4083 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4084 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4085 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4086 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4087 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4088 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4089 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4090 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4091 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4092 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4093 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4094 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4095 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4096 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4097 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4098 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4099 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4100 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4101 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4102 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4103 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4104 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4105 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4106 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4107 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4108 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4109 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4110 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4111 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4112 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4113 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4114 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4115 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4116 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4117 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4118 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4119 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4120 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4121 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4122 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4123 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4124 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4125 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4126 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4127 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4128 [x86_intercept_xsetbv
] = PRE_EX(SVM_EXIT_XSETBV
),
4135 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4136 struct x86_instruction_info
*info
,
4137 enum x86_intercept_stage stage
,
4138 struct x86_exception
*exception
)
4140 struct vcpu_svm
*svm
= to_svm(vcpu
);
4141 int vmexit
, ret
= X86EMUL_CONTINUE
;
4142 struct __x86_intercept icpt_info
;
4143 struct vmcb
*vmcb
= svm
->vmcb
;
4145 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4148 icpt_info
= x86_intercept_map
[info
->intercept
];
4150 if (stage
!= icpt_info
.stage
)
4153 switch (icpt_info
.exit_code
) {
4154 case SVM_EXIT_READ_CR0
:
4155 if (info
->intercept
== x86_intercept_cr_read
)
4156 icpt_info
.exit_code
+= info
->modrm_reg
;
4158 case SVM_EXIT_WRITE_CR0
: {
4159 unsigned long cr0
, val
;
4161 if (info
->intercept
== x86_intercept_cr_write
)
4162 icpt_info
.exit_code
+= info
->modrm_reg
;
4164 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
4165 info
->intercept
== x86_intercept_clts
)
4168 if (!(vmcb_is_intercept(&svm
->nested
.ctl
,
4169 INTERCEPT_SELECTIVE_CR0
)))
4172 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4173 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4175 if (info
->intercept
== x86_intercept_lmsw
) {
4178 /* lmsw can't clear PE - catch this here */
4179 if (cr0
& X86_CR0_PE
)
4184 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4188 case SVM_EXIT_READ_DR0
:
4189 case SVM_EXIT_WRITE_DR0
:
4190 icpt_info
.exit_code
+= info
->modrm_reg
;
4193 if (info
->intercept
== x86_intercept_wrmsr
)
4194 vmcb
->control
.exit_info_1
= 1;
4196 vmcb
->control
.exit_info_1
= 0;
4198 case SVM_EXIT_PAUSE
:
4200 * We get this for NOP only, but pause
4201 * is rep not, check this here
4203 if (info
->rep_prefix
!= REPE_PREFIX
)
4206 case SVM_EXIT_IOIO
: {
4210 if (info
->intercept
== x86_intercept_in
||
4211 info
->intercept
== x86_intercept_ins
) {
4212 exit_info
= ((info
->src_val
& 0xffff) << 16) |
4214 bytes
= info
->dst_bytes
;
4216 exit_info
= (info
->dst_val
& 0xffff) << 16;
4217 bytes
= info
->src_bytes
;
4220 if (info
->intercept
== x86_intercept_outs
||
4221 info
->intercept
== x86_intercept_ins
)
4222 exit_info
|= SVM_IOIO_STR_MASK
;
4224 if (info
->rep_prefix
)
4225 exit_info
|= SVM_IOIO_REP_MASK
;
4227 bytes
= min(bytes
, 4u);
4229 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4231 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4233 vmcb
->control
.exit_info_1
= exit_info
;
4234 vmcb
->control
.exit_info_2
= info
->next_rip
;
4242 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4243 if (static_cpu_has(X86_FEATURE_NRIPS
))
4244 vmcb
->control
.next_rip
= info
->next_rip
;
4245 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4246 vmexit
= nested_svm_exit_handled(svm
);
4248 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4255 static void svm_handle_exit_irqoff(struct kvm_vcpu
*vcpu
)
4259 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
4261 if (!kvm_pause_in_guest(vcpu
->kvm
))
4262 shrink_ple_window(vcpu
);
4265 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
4267 /* [63:9] are reserved. */
4268 vcpu
->arch
.mcg_cap
&= 0x1ff;
4271 bool svm_smi_blocked(struct kvm_vcpu
*vcpu
)
4273 struct vcpu_svm
*svm
= to_svm(vcpu
);
4275 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4279 return is_smm(vcpu
);
4282 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
4284 struct vcpu_svm
*svm
= to_svm(vcpu
);
4285 if (svm
->nested
.nested_run_pending
)
4288 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4289 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_smi(svm
))
4292 return !svm_smi_blocked(vcpu
);
4295 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
4297 struct vcpu_svm
*svm
= to_svm(vcpu
);
4300 if (is_guest_mode(vcpu
)) {
4301 /* FED8h - SVM Guest */
4302 put_smstate(u64
, smstate
, 0x7ed8, 1);
4303 /* FEE0h - SVM Guest VMCB Physical Address */
4304 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb12_gpa
);
4306 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
4307 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
4308 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
4310 ret
= nested_svm_vmexit(svm
);
4317 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, const char *smstate
)
4319 struct vcpu_svm
*svm
= to_svm(vcpu
);
4320 struct kvm_host_map map
;
4323 if (guest_cpuid_has(vcpu
, X86_FEATURE_LM
)) {
4324 u64 saved_efer
= GET_SMSTATE(u64
, smstate
, 0x7ed0);
4325 u64 guest
= GET_SMSTATE(u64
, smstate
, 0x7ed8);
4326 u64 vmcb12_gpa
= GET_SMSTATE(u64
, smstate
, 0x7ee0);
4329 if (!guest_cpuid_has(vcpu
, X86_FEATURE_SVM
))
4332 if (!(saved_efer
& EFER_SVME
))
4335 if (kvm_vcpu_map(vcpu
,
4336 gpa_to_gfn(vmcb12_gpa
), &map
) == -EINVAL
)
4339 if (svm_allocate_nested(svm
))
4342 ret
= enter_svm_guest_mode(vcpu
, vmcb12_gpa
, map
.hva
);
4343 kvm_vcpu_unmap(vcpu
, &map
, true);
4350 static void svm_enable_smi_window(struct kvm_vcpu
*vcpu
)
4352 struct vcpu_svm
*svm
= to_svm(vcpu
);
4354 if (!gif_set(svm
)) {
4355 if (vgif_enabled(svm
))
4356 svm_set_intercept(svm
, INTERCEPT_STGI
);
4357 /* STGI will cause a vm exit */
4359 /* We must be in SMM; RSM will cause a vmexit anyway. */
4363 static bool svm_can_emulate_instruction(struct kvm_vcpu
*vcpu
, void *insn
, int insn_len
)
4365 bool smep
, smap
, is_user
;
4369 * When the guest is an SEV-ES guest, emulation is not possible.
4371 if (sev_es_guest(vcpu
->kvm
))
4375 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4378 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4379 * possible that CPU microcode implementing DecodeAssist will fail
4380 * to read bytes of instruction which caused #NPF. In this case,
4381 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4382 * return 0 instead of the correct guest instruction bytes.
4384 * This happens because CPU microcode reading instruction bytes
4385 * uses a special opcode which attempts to read data using CPL=0
4386 * privileges. The microcode reads CS:RIP and if it hits a SMAP
4387 * fault, it gives up and returns no instruction bytes.
4390 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4391 * returned 0 in GuestIntrBytes field of the VMCB.
4392 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4393 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4394 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4395 * a SMEP fault instead of #NPF).
4396 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4397 * As most guests enable SMAP if they have also enabled SMEP, use above
4398 * logic in order to attempt minimize false-positive of detecting errata
4399 * while still preserving all cases semantic correctness.
4402 * To determine what instruction the guest was executing, the hypervisor
4403 * will have to decode the instruction at the instruction pointer.
4405 * In non SEV guest, hypervisor will be able to read the guest
4406 * memory to decode the instruction pointer when insn_len is zero
4407 * so we return true to indicate that decoding is possible.
4409 * But in the SEV guest, the guest memory is encrypted with the
4410 * guest specific key and hypervisor will not be able to decode the
4411 * instruction pointer so we will not able to workaround it. Lets
4412 * print the error and request to kill the guest.
4414 if (likely(!insn
|| insn_len
))
4418 * If RIP is invalid, go ahead with emulation which will cause an
4419 * internal error exit.
4421 if (!kvm_vcpu_gfn_to_memslot(vcpu
, kvm_rip_read(vcpu
) >> PAGE_SHIFT
))
4424 cr4
= kvm_read_cr4(vcpu
);
4425 smep
= cr4
& X86_CR4_SMEP
;
4426 smap
= cr4
& X86_CR4_SMAP
;
4427 is_user
= svm_get_cpl(vcpu
) == 3;
4428 if (smap
&& (!smep
|| is_user
)) {
4429 if (!sev_guest(vcpu
->kvm
))
4432 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4433 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4439 static bool svm_apic_init_signal_blocked(struct kvm_vcpu
*vcpu
)
4441 struct vcpu_svm
*svm
= to_svm(vcpu
);
4444 * TODO: Last condition latch INIT signals on vCPU when
4445 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4446 * To properly emulate the INIT intercept,
4447 * svm_check_nested_events() should call nested_svm_vmexit()
4448 * if an INIT signal is pending.
4450 return !gif_set(svm
) ||
4451 (vmcb_is_intercept(&svm
->vmcb
->control
, INTERCEPT_INIT
));
4454 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu
*vcpu
, u8 vector
)
4456 if (!sev_es_guest(vcpu
->kvm
))
4457 return kvm_vcpu_deliver_sipi_vector(vcpu
, vector
);
4459 sev_vcpu_deliver_sipi_vector(vcpu
, vector
);
4462 static void svm_vm_destroy(struct kvm
*kvm
)
4464 avic_vm_destroy(kvm
);
4465 sev_vm_destroy(kvm
);
4468 static int svm_vm_init(struct kvm
*kvm
)
4470 if (!pause_filter_count
|| !pause_filter_thresh
)
4471 kvm
->arch
.pause_in_guest
= true;
4474 int ret
= avic_vm_init(kvm
);
4479 kvm_apicv_init(kvm
, avic
);
4483 static struct kvm_x86_ops svm_x86_ops __initdata
= {
4484 .hardware_unsetup
= svm_hardware_teardown
,
4485 .hardware_enable
= svm_hardware_enable
,
4486 .hardware_disable
= svm_hardware_disable
,
4487 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4488 .has_emulated_msr
= svm_has_emulated_msr
,
4490 .vcpu_create
= svm_create_vcpu
,
4491 .vcpu_free
= svm_free_vcpu
,
4492 .vcpu_reset
= svm_vcpu_reset
,
4494 .vm_size
= sizeof(struct kvm_svm
),
4495 .vm_init
= svm_vm_init
,
4496 .vm_destroy
= svm_vm_destroy
,
4498 .prepare_guest_switch
= svm_prepare_guest_switch
,
4499 .vcpu_load
= svm_vcpu_load
,
4500 .vcpu_put
= svm_vcpu_put
,
4501 .vcpu_blocking
= svm_vcpu_blocking
,
4502 .vcpu_unblocking
= svm_vcpu_unblocking
,
4504 .update_exception_bitmap
= svm_update_exception_bitmap
,
4505 .get_msr_feature
= svm_get_msr_feature
,
4506 .get_msr
= svm_get_msr
,
4507 .set_msr
= svm_set_msr
,
4508 .get_segment_base
= svm_get_segment_base
,
4509 .get_segment
= svm_get_segment
,
4510 .set_segment
= svm_set_segment
,
4511 .get_cpl
= svm_get_cpl
,
4512 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4513 .set_cr0
= svm_set_cr0
,
4514 .is_valid_cr4
= svm_is_valid_cr4
,
4515 .set_cr4
= svm_set_cr4
,
4516 .set_efer
= svm_set_efer
,
4517 .get_idt
= svm_get_idt
,
4518 .set_idt
= svm_set_idt
,
4519 .get_gdt
= svm_get_gdt
,
4520 .set_gdt
= svm_set_gdt
,
4521 .set_dr7
= svm_set_dr7
,
4522 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
4523 .cache_reg
= svm_cache_reg
,
4524 .get_rflags
= svm_get_rflags
,
4525 .set_rflags
= svm_set_rflags
,
4527 .tlb_flush_all
= svm_flush_tlb
,
4528 .tlb_flush_current
= svm_flush_tlb
,
4529 .tlb_flush_gva
= svm_flush_tlb_gva
,
4530 .tlb_flush_guest
= svm_flush_tlb
,
4532 .run
= svm_vcpu_run
,
4533 .handle_exit
= handle_exit
,
4534 .skip_emulated_instruction
= skip_emulated_instruction
,
4535 .update_emulated_instruction
= NULL
,
4536 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4537 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4538 .patch_hypercall
= svm_patch_hypercall
,
4539 .set_irq
= svm_set_irq
,
4540 .set_nmi
= svm_inject_nmi
,
4541 .queue_exception
= svm_queue_exception
,
4542 .cancel_injection
= svm_cancel_injection
,
4543 .interrupt_allowed
= svm_interrupt_allowed
,
4544 .nmi_allowed
= svm_nmi_allowed
,
4545 .get_nmi_mask
= svm_get_nmi_mask
,
4546 .set_nmi_mask
= svm_set_nmi_mask
,
4547 .enable_nmi_window
= svm_enable_nmi_window
,
4548 .enable_irq_window
= svm_enable_irq_window
,
4549 .update_cr8_intercept
= svm_update_cr8_intercept
,
4550 .set_virtual_apic_mode
= svm_set_virtual_apic_mode
,
4551 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
4552 .check_apicv_inhibit_reasons
= svm_check_apicv_inhibit_reasons
,
4553 .pre_update_apicv_exec_ctrl
= svm_pre_update_apicv_exec_ctrl
,
4554 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
4555 .hwapic_irr_update
= svm_hwapic_irr_update
,
4556 .hwapic_isr_update
= svm_hwapic_isr_update
,
4557 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
4558 .apicv_post_state_restore
= avic_post_state_restore
,
4560 .set_tss_addr
= svm_set_tss_addr
,
4561 .set_identity_map_addr
= svm_set_identity_map_addr
,
4562 .get_mt_mask
= svm_get_mt_mask
,
4564 .get_exit_info
= svm_get_exit_info
,
4566 .vcpu_after_set_cpuid
= svm_vcpu_after_set_cpuid
,
4568 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4570 .write_l1_tsc_offset
= svm_write_l1_tsc_offset
,
4572 .load_mmu_pgd
= svm_load_mmu_pgd
,
4574 .check_intercept
= svm_check_intercept
,
4575 .handle_exit_irqoff
= svm_handle_exit_irqoff
,
4577 .request_immediate_exit
= __kvm_request_immediate_exit
,
4579 .sched_in
= svm_sched_in
,
4581 .pmu_ops
= &amd_pmu_ops
,
4582 .nested_ops
= &svm_nested_ops
,
4584 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
4585 .dy_apicv_has_pending_interrupt
= svm_dy_apicv_has_pending_interrupt
,
4586 .update_pi_irte
= svm_update_pi_irte
,
4587 .setup_mce
= svm_setup_mce
,
4589 .smi_allowed
= svm_smi_allowed
,
4590 .pre_enter_smm
= svm_pre_enter_smm
,
4591 .pre_leave_smm
= svm_pre_leave_smm
,
4592 .enable_smi_window
= svm_enable_smi_window
,
4594 .mem_enc_op
= svm_mem_enc_op
,
4595 .mem_enc_reg_region
= svm_register_enc_region
,
4596 .mem_enc_unreg_region
= svm_unregister_enc_region
,
4598 .vm_copy_enc_context_from
= svm_vm_copy_asid_from
,
4600 .can_emulate_instruction
= svm_can_emulate_instruction
,
4602 .apic_init_signal_blocked
= svm_apic_init_signal_blocked
,
4604 .msr_filter_changed
= svm_msr_filter_changed
,
4605 .complete_emulated_msr
= svm_complete_emulated_msr
,
4607 .vcpu_deliver_sipi_vector
= svm_vcpu_deliver_sipi_vector
,
4610 static struct kvm_x86_init_ops svm_init_ops __initdata
= {
4611 .cpu_has_kvm_support
= has_svm
,
4612 .disabled_by_bios
= is_disabled
,
4613 .hardware_setup
= svm_hardware_setup
,
4614 .check_processor_compatibility
= svm_check_processor_compat
,
4616 .runtime_ops
= &svm_x86_ops
,
4619 static int __init
svm_init(void)
4621 __unused_size_checks();
4623 return kvm_init(&svm_init_ops
, sizeof(struct vcpu_svm
),
4624 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4627 static void __exit
svm_exit(void)
4632 module_init(svm_init
)
4633 module_exit(svm_exit
)