1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
40 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
51 static const struct x86_cpu_id svm_cpu_id
[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM
, NULL
),
55 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly
;
80 u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
86 static uint64_t osvw_len
= 4, osvw_status
;
88 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
91 static const struct svm_direct_access_msrs
{
92 u32 index
; /* Index of the MSR */
93 bool always
; /* True if intercept is initially cleared */
94 } direct_access_msrs
[MAX_DIRECT_ACCESS_MSRS
] = {
95 { .index
= MSR_STAR
, .always
= true },
96 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
98 { .index
= MSR_GS_BASE
, .always
= true },
99 { .index
= MSR_FS_BASE
, .always
= true },
100 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
101 { .index
= MSR_LSTAR
, .always
= true },
102 { .index
= MSR_CSTAR
, .always
= true },
103 { .index
= MSR_SYSCALL_MASK
, .always
= true },
105 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
106 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
107 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
108 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
109 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
110 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
111 { .index
= MSR_EFER
, .always
= false },
112 { .index
= MSR_IA32_CR_PAT
, .always
= false },
113 { .index
= MSR_AMD64_SEV_ES_GHCB
, .always
= true },
114 { .index
= MSR_INVALID
, .always
= false },
117 /* enable NPT for AMD64 and X86 with PAE */
118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
119 bool npt_enabled
= true;
125 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
126 * pause_filter_count: On processors that support Pause filtering(indicated
127 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
128 * count value. On VMRUN this value is loaded into an internal counter.
129 * Each time a pause instruction is executed, this counter is decremented
130 * until it reaches zero at which time a #VMEXIT is generated if pause
131 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
132 * Intercept Filtering for more details.
133 * This also indicate if ple logic enabled.
135 * pause_filter_thresh: In addition, some processor families support advanced
136 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
137 * the amount of time a guest is allowed to execute in a pause loop.
138 * In this mode, a 16-bit pause filter threshold field is added in the
139 * VMCB. The threshold value is a cycle count that is used to reset the
140 * pause counter. As with simple pause filtering, VMRUN loads the pause
141 * count value from VMCB into an internal counter. Then, on each pause
142 * instruction the hardware checks the elapsed number of cycles since
143 * the most recent pause instruction against the pause filter threshold.
144 * If the elapsed cycle count is greater than the pause filter threshold,
145 * then the internal pause count is reloaded from the VMCB and execution
146 * continues. If the elapsed cycle count is less than the pause filter
147 * threshold, then the internal pause count is decremented. If the count
148 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
149 * triggered. If advanced pause filtering is supported and pause filter
150 * threshold field is set to zero, the filter will operate in the simpler,
154 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
155 module_param(pause_filter_thresh
, ushort
, 0444);
157 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
158 module_param(pause_filter_count
, ushort
, 0444);
160 /* Default doubles per-vcpu window every exit. */
161 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
162 module_param(pause_filter_count_grow
, ushort
, 0444);
164 /* Default resets per-vcpu window every exit to pause_filter_count. */
165 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
166 module_param(pause_filter_count_shrink
, ushort
, 0444);
168 /* Default is to compute the maximum so we can never overflow. */
169 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
170 module_param(pause_filter_count_max
, ushort
, 0444);
172 /* allow nested paging (virtualized MMU) for all guests */
173 static int npt
= true;
174 module_param(npt
, int, S_IRUGO
);
176 /* allow nested virtualization in KVM/SVM */
177 static int nested
= true;
178 module_param(nested
, int, S_IRUGO
);
180 /* enable/disable Next RIP Save */
181 static int nrips
= true;
182 module_param(nrips
, int, 0444);
184 /* enable/disable Virtual VMLOAD VMSAVE */
185 static int vls
= true;
186 module_param(vls
, int, 0444);
188 /* enable/disable Virtual GIF */
189 static int vgif
= true;
190 module_param(vgif
, int, 0444);
192 /* enable/disable SEV support */
193 int sev
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
194 module_param(sev
, int, 0444);
196 /* enable/disable SEV-ES support */
197 int sev_es
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
198 module_param(sev_es
, int, 0444);
200 bool __read_mostly dump_invalid_vmcb
;
201 module_param(dump_invalid_vmcb
, bool, 0644);
203 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
205 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
207 static unsigned long iopm_base
;
209 struct kvm_ldttss_desc
{
212 unsigned base1
:8, type
:5, dpl
:2, p
:1;
213 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
216 } __attribute__((packed
));
218 DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
220 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
222 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
223 #define MSRS_RANGE_SIZE 2048
224 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
226 u32
svm_msrpm_offset(u32 msr
)
231 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
232 if (msr
< msrpm_ranges
[i
] ||
233 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
236 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
237 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
239 /* Now we have the u8 offset - but need the u32 offset */
243 /* MSR not in any range */
247 #define MAX_INST_SIZE 15
249 static inline void clgi(void)
251 asm volatile (__ex("clgi"));
254 static inline void stgi(void)
256 asm volatile (__ex("stgi"));
259 static inline void invlpga(unsigned long addr
, u32 asid
)
261 asm volatile (__ex("invlpga %1, %0") : : "c"(asid
), "a"(addr
));
264 static int get_max_npt_level(void)
267 return PT64_ROOT_4LEVEL
;
269 return PT32E_ROOT_LEVEL
;
273 int svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
275 struct vcpu_svm
*svm
= to_svm(vcpu
);
276 u64 old_efer
= vcpu
->arch
.efer
;
277 vcpu
->arch
.efer
= efer
;
280 /* Shadow paging assumes NX to be available. */
283 if (!(efer
& EFER_LMA
))
287 if ((old_efer
& EFER_SVME
) != (efer
& EFER_SVME
)) {
288 if (!(efer
& EFER_SVME
)) {
289 svm_leave_nested(svm
);
290 svm_set_gif(svm
, true);
293 * Free the nested guest state, unless we are in SMM.
294 * In this case we will return to the nested guest
295 * as soon as we leave SMM.
297 if (!is_smm(&svm
->vcpu
))
298 svm_free_nested(svm
);
301 int ret
= svm_allocate_nested(svm
);
304 vcpu
->arch
.efer
= old_efer
;
310 svm
->vmcb
->save
.efer
= efer
| EFER_SVME
;
311 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
315 static int is_external_interrupt(u32 info
)
317 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
318 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
321 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
323 struct vcpu_svm
*svm
= to_svm(vcpu
);
326 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
327 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
331 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
333 struct vcpu_svm
*svm
= to_svm(vcpu
);
336 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
338 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
342 static int skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
344 struct vcpu_svm
*svm
= to_svm(vcpu
);
347 * SEV-ES does not expose the next RIP. The RIP update is controlled by
348 * the type of exit and the #VC handler in the guest.
350 if (sev_es_guest(vcpu
->kvm
))
353 if (nrips
&& svm
->vmcb
->control
.next_rip
!= 0) {
354 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
355 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
358 if (!svm
->next_rip
) {
359 if (!kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
))
362 kvm_rip_write(vcpu
, svm
->next_rip
);
366 svm_set_interrupt_shadow(vcpu
, 0);
371 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
373 struct vcpu_svm
*svm
= to_svm(vcpu
);
374 unsigned nr
= vcpu
->arch
.exception
.nr
;
375 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
376 u32 error_code
= vcpu
->arch
.exception
.error_code
;
378 kvm_deliver_exception_payload(&svm
->vcpu
);
380 if (nr
== BP_VECTOR
&& !nrips
) {
381 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
384 * For guest debugging where we have to reinject #BP if some
385 * INT3 is guest-owned:
386 * Emulate nRIP by moving RIP forward. Will fail if injection
387 * raises a fault that is not intercepted. Still better than
388 * failing in all cases.
390 (void)skip_emulated_instruction(&svm
->vcpu
);
391 rip
= kvm_rip_read(&svm
->vcpu
);
392 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
393 svm
->int3_injected
= rip
- old_rip
;
396 svm
->vmcb
->control
.event_inj
= nr
398 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
399 | SVM_EVTINJ_TYPE_EXEPT
;
400 svm
->vmcb
->control
.event_inj_err
= error_code
;
403 static void svm_init_erratum_383(void)
409 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
412 /* Use _safe variants to not break nested virtualization */
413 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
419 low
= lower_32_bits(val
);
420 high
= upper_32_bits(val
);
422 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
424 erratum_383_found
= true;
427 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
430 * Guests should see errata 400 and 415 as fixed (assuming that
431 * HLT and IO instructions are intercepted).
433 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
434 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
437 * By increasing VCPU's osvw.length to 3 we are telling the guest that
438 * all osvw.status bits inside that length, including bit 0 (which is
439 * reserved for erratum 298), are valid. However, if host processor's
440 * osvw_len is 0 then osvw_status[0] carries no information. We need to
441 * be conservative here and therefore we tell the guest that erratum 298
442 * is present (because we really don't know).
444 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
445 vcpu
->arch
.osvw
.status
|= 1;
448 static int has_svm(void)
452 if (!cpu_has_svm(&msg
)) {
453 printk(KERN_INFO
"has_svm: %s\n", msg
);
458 pr_info("KVM is unsupported when running as an SEV guest\n");
465 static void svm_hardware_disable(void)
467 /* Make sure we clean up behind us */
468 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
469 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
473 amd_pmu_disable_virt();
476 static int svm_hardware_enable(void)
479 struct svm_cpu_data
*sd
;
481 struct desc_struct
*gdt
;
482 int me
= raw_smp_processor_id();
484 rdmsrl(MSR_EFER
, efer
);
485 if (efer
& EFER_SVME
)
489 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
492 sd
= per_cpu(svm_data
, me
);
494 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
498 sd
->asid_generation
= 1;
499 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
500 sd
->next_asid
= sd
->max_asid
+ 1;
501 sd
->min_asid
= max_sev_asid
+ 1;
503 gdt
= get_current_gdt_rw();
504 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
506 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
508 wrmsrl(MSR_VM_HSAVE_PA
, __sme_page_pa(sd
->save_area
));
510 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
511 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
512 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
519 * Note that it is possible to have a system with mixed processor
520 * revisions and therefore different OSVW bits. If bits are not the same
521 * on different processors then choose the worst case (i.e. if erratum
522 * is present on one processor and not on another then assume that the
523 * erratum is present everywhere).
525 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
526 uint64_t len
, status
= 0;
529 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
531 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
535 osvw_status
= osvw_len
= 0;
539 osvw_status
|= status
;
540 osvw_status
&= (1ULL << osvw_len
) - 1;
543 osvw_status
= osvw_len
= 0;
545 svm_init_erratum_383();
547 amd_pmu_enable_virt();
552 static void svm_cpu_uninit(int cpu
)
554 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
559 per_cpu(svm_data
, cpu
) = NULL
;
560 kfree(sd
->sev_vmcbs
);
561 __free_page(sd
->save_area
);
565 static int svm_cpu_init(int cpu
)
567 struct svm_cpu_data
*sd
;
569 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
573 sd
->save_area
= alloc_page(GFP_KERNEL
);
576 clear_page(page_address(sd
->save_area
));
578 if (svm_sev_enabled()) {
579 sd
->sev_vmcbs
= kmalloc_array(max_sev_asid
+ 1,
586 per_cpu(svm_data
, cpu
) = sd
;
591 __free_page(sd
->save_area
);
598 static int direct_access_msr_slot(u32 msr
)
602 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
603 if (direct_access_msrs
[i
].index
== msr
)
609 static void set_shadow_msr_intercept(struct kvm_vcpu
*vcpu
, u32 msr
, int read
,
612 struct vcpu_svm
*svm
= to_svm(vcpu
);
613 int slot
= direct_access_msr_slot(msr
);
618 /* Set the shadow bitmaps to the desired intercept states */
620 set_bit(slot
, svm
->shadow_msr_intercept
.read
);
622 clear_bit(slot
, svm
->shadow_msr_intercept
.read
);
625 set_bit(slot
, svm
->shadow_msr_intercept
.write
);
627 clear_bit(slot
, svm
->shadow_msr_intercept
.write
);
630 static bool valid_msr_intercept(u32 index
)
632 return direct_access_msr_slot(index
) != -ENOENT
;
635 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
642 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
645 offset
= svm_msrpm_offset(msr
);
646 bit_write
= 2 * (msr
& 0x0f) + 1;
649 BUG_ON(offset
== MSR_INVALID
);
651 return !!test_bit(bit_write
, &tmp
);
654 static void set_msr_interception_bitmap(struct kvm_vcpu
*vcpu
, u32
*msrpm
,
655 u32 msr
, int read
, int write
)
657 u8 bit_read
, bit_write
;
662 * If this warning triggers extend the direct_access_msrs list at the
663 * beginning of the file
665 WARN_ON(!valid_msr_intercept(msr
));
667 /* Enforce non allowed MSRs to trap */
668 if (read
&& !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_READ
))
671 if (write
&& !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_WRITE
))
674 offset
= svm_msrpm_offset(msr
);
675 bit_read
= 2 * (msr
& 0x0f);
676 bit_write
= 2 * (msr
& 0x0f) + 1;
679 BUG_ON(offset
== MSR_INVALID
);
681 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
682 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
687 void set_msr_interception(struct kvm_vcpu
*vcpu
, u32
*msrpm
, u32 msr
,
690 set_shadow_msr_intercept(vcpu
, msr
, read
, write
);
691 set_msr_interception_bitmap(vcpu
, msrpm
, msr
, read
, write
);
694 u32
*svm_vcpu_alloc_msrpm(void)
696 struct page
*pages
= alloc_pages(GFP_KERNEL_ACCOUNT
, MSRPM_ALLOC_ORDER
);
702 msrpm
= page_address(pages
);
703 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
708 void svm_vcpu_init_msrpm(struct kvm_vcpu
*vcpu
, u32
*msrpm
)
712 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
713 if (!direct_access_msrs
[i
].always
)
715 set_msr_interception(vcpu
, msrpm
, direct_access_msrs
[i
].index
, 1, 1);
720 void svm_vcpu_free_msrpm(u32
*msrpm
)
722 __free_pages(virt_to_page(msrpm
), MSRPM_ALLOC_ORDER
);
725 static void svm_msr_filter_changed(struct kvm_vcpu
*vcpu
)
727 struct vcpu_svm
*svm
= to_svm(vcpu
);
731 * Set intercept permissions for all direct access MSRs again. They
732 * will automatically get filtered through the MSR filter, so we are
733 * back in sync after this.
735 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
736 u32 msr
= direct_access_msrs
[i
].index
;
737 u32 read
= test_bit(i
, svm
->shadow_msr_intercept
.read
);
738 u32 write
= test_bit(i
, svm
->shadow_msr_intercept
.write
);
740 set_msr_interception_bitmap(vcpu
, svm
->msrpm
, msr
, read
, write
);
744 static void add_msr_offset(u32 offset
)
748 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
750 /* Offset already in list? */
751 if (msrpm_offsets
[i
] == offset
)
754 /* Slot used by another offset? */
755 if (msrpm_offsets
[i
] != MSR_INVALID
)
758 /* Add offset to list */
759 msrpm_offsets
[i
] = offset
;
765 * If this BUG triggers the msrpm_offsets table has an overflow. Just
766 * increase MSRPM_OFFSETS in this case.
771 static void init_msrpm_offsets(void)
775 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
777 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
780 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
781 BUG_ON(offset
== MSR_INVALID
);
783 add_msr_offset(offset
);
787 static void svm_enable_lbrv(struct kvm_vcpu
*vcpu
)
789 struct vcpu_svm
*svm
= to_svm(vcpu
);
791 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
792 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
793 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
794 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
795 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
798 static void svm_disable_lbrv(struct kvm_vcpu
*vcpu
)
800 struct vcpu_svm
*svm
= to_svm(vcpu
);
802 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
803 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
804 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
805 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
806 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
809 void disable_nmi_singlestep(struct vcpu_svm
*svm
)
811 svm
->nmi_singlestep
= false;
813 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
814 /* Clear our flags if they were not set by the guest */
815 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
816 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
817 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
818 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
822 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
824 struct vcpu_svm
*svm
= to_svm(vcpu
);
825 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
826 int old
= control
->pause_filter_count
;
828 control
->pause_filter_count
= __grow_ple_window(old
,
830 pause_filter_count_grow
,
831 pause_filter_count_max
);
833 if (control
->pause_filter_count
!= old
) {
834 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
835 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
836 control
->pause_filter_count
, old
);
840 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
842 struct vcpu_svm
*svm
= to_svm(vcpu
);
843 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
844 int old
= control
->pause_filter_count
;
846 control
->pause_filter_count
=
847 __shrink_ple_window(old
,
849 pause_filter_count_shrink
,
851 if (control
->pause_filter_count
!= old
) {
852 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
853 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
854 control
->pause_filter_count
, old
);
859 * The default MMIO mask is a single bit (excluding the present bit),
860 * which could conflict with the memory encryption bit. Check for
861 * memory encryption support and override the default MMIO mask if
862 * memory encryption is enabled.
864 static __init
void svm_adjust_mmio_mask(void)
866 unsigned int enc_bit
, mask_bit
;
869 /* If there is no memory encryption support, use existing mask */
870 if (cpuid_eax(0x80000000) < 0x8000001f)
873 /* If memory encryption is not enabled, use existing mask */
874 rdmsrl(MSR_K8_SYSCFG
, msr
);
875 if (!(msr
& MSR_K8_SYSCFG_MEM_ENCRYPT
))
878 enc_bit
= cpuid_ebx(0x8000001f) & 0x3f;
879 mask_bit
= boot_cpu_data
.x86_phys_bits
;
881 /* Increment the mask bit if it is the same as the encryption bit */
882 if (enc_bit
== mask_bit
)
886 * If the mask bit location is below 52, then some bits above the
887 * physical addressing limit will always be reserved, so use the
888 * rsvd_bits() function to generate the mask. This mask, along with
889 * the present bit, will be used to generate a page fault with
892 * If the mask bit location is 52 (or above), then clear the mask.
894 mask
= (mask_bit
< 52) ? rsvd_bits(mask_bit
, 51) | PT_PRESENT_MASK
: 0;
896 kvm_mmu_set_mmio_spte_mask(mask
, PT_WRITABLE_MASK
| PT_USER_MASK
);
899 static void svm_hardware_teardown(void)
903 if (svm_sev_enabled())
904 sev_hardware_teardown();
906 for_each_possible_cpu(cpu
)
909 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
913 static __init
void svm_set_cpu_caps(void)
919 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
921 kvm_cpu_cap_set(X86_FEATURE_SVM
);
924 kvm_cpu_cap_set(X86_FEATURE_NRIPS
);
927 kvm_cpu_cap_set(X86_FEATURE_NPT
);
930 /* CPUID 0x80000008 */
931 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD
) ||
932 boot_cpu_has(X86_FEATURE_AMD_SSBD
))
933 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD
);
935 /* Enable INVPCID feature */
936 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID
);
939 static __init
int svm_hardware_setup(void)
942 struct page
*iopm_pages
;
946 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
951 iopm_va
= page_address(iopm_pages
);
952 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
953 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
955 init_msrpm_offsets();
957 supported_xcr0
&= ~(XFEATURE_MASK_BNDREGS
| XFEATURE_MASK_BNDCSR
);
959 if (boot_cpu_has(X86_FEATURE_NX
))
960 kvm_enable_efer_bits(EFER_NX
);
962 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
963 kvm_enable_efer_bits(EFER_FFXSR
);
965 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
966 kvm_has_tsc_control
= true;
967 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
968 kvm_tsc_scaling_ratio_frac_bits
= 32;
971 /* Check for pause filtering support */
972 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
973 pause_filter_count
= 0;
974 pause_filter_thresh
= 0;
975 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
976 pause_filter_thresh
= 0;
980 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
981 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
984 if (IS_ENABLED(CONFIG_KVM_AMD_SEV
) && sev
) {
985 sev_hardware_setup();
991 svm_adjust_mmio_mask();
993 for_each_possible_cpu(cpu
) {
994 r
= svm_cpu_init(cpu
);
999 if (!boot_cpu_has(X86_FEATURE_NPT
))
1000 npt_enabled
= false;
1002 if (npt_enabled
&& !npt
)
1003 npt_enabled
= false;
1005 kvm_configure_mmu(npt_enabled
, get_max_npt_level(), PG_LEVEL_1G
);
1006 pr_info("kvm: Nested Paging %sabled\n", npt_enabled
? "en" : "dis");
1009 if (!boot_cpu_has(X86_FEATURE_NRIPS
))
1015 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1016 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1019 pr_info("AVIC enabled\n");
1021 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1027 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1028 !IS_ENABLED(CONFIG_X86_64
)) {
1031 pr_info("Virtual VMLOAD VMSAVE supported\n");
1036 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1039 pr_info("Virtual GIF supported\n");
1045 * It seems that on AMD processors PTE's accessed bit is
1046 * being set by the CPU hardware before the NPF vmexit.
1047 * This is not expected behaviour and our tests fail because
1049 * A workaround here is to disable support for
1050 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1051 * In this case userspace can know if there is support using
1052 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1054 * If future AMD CPU models change the behaviour described above,
1055 * this variable can be changed accordingly
1057 allow_smaller_maxphyaddr
= !npt_enabled
;
1062 svm_hardware_teardown();
1066 static void init_seg(struct vmcb_seg
*seg
)
1069 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1070 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1071 seg
->limit
= 0xffff;
1075 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1078 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1079 seg
->limit
= 0xffff;
1083 static u64
svm_write_l1_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1085 struct vcpu_svm
*svm
= to_svm(vcpu
);
1086 u64 g_tsc_offset
= 0;
1088 if (is_guest_mode(vcpu
)) {
1089 /* Write L1's TSC offset. */
1090 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1091 svm
->nested
.hsave
->control
.tsc_offset
;
1092 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1095 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1096 svm
->vmcb
->control
.tsc_offset
- g_tsc_offset
,
1099 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1101 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1102 return svm
->vmcb
->control
.tsc_offset
;
1105 static void svm_check_invpcid(struct vcpu_svm
*svm
)
1108 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1109 * roots, or if INVPCID is disabled in the guest to inject #UD.
1111 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID
)) {
1113 !guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_INVPCID
))
1114 svm_set_intercept(svm
, INTERCEPT_INVPCID
);
1116 svm_clr_intercept(svm
, INTERCEPT_INVPCID
);
1120 static void init_vmcb(struct vcpu_svm
*svm
)
1122 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1123 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1125 svm
->vcpu
.arch
.hflags
= 0;
1127 svm_set_intercept(svm
, INTERCEPT_CR0_READ
);
1128 svm_set_intercept(svm
, INTERCEPT_CR3_READ
);
1129 svm_set_intercept(svm
, INTERCEPT_CR4_READ
);
1130 svm_set_intercept(svm
, INTERCEPT_CR0_WRITE
);
1131 svm_set_intercept(svm
, INTERCEPT_CR3_WRITE
);
1132 svm_set_intercept(svm
, INTERCEPT_CR4_WRITE
);
1133 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1134 svm_set_intercept(svm
, INTERCEPT_CR8_WRITE
);
1136 set_dr_intercepts(svm
);
1138 set_exception_intercept(svm
, PF_VECTOR
);
1139 set_exception_intercept(svm
, UD_VECTOR
);
1140 set_exception_intercept(svm
, MC_VECTOR
);
1141 set_exception_intercept(svm
, AC_VECTOR
);
1142 set_exception_intercept(svm
, DB_VECTOR
);
1144 * Guest access to VMware backdoor ports could legitimately
1145 * trigger #GP because of TSS I/O permission bitmap.
1146 * We intercept those #GP and allow access to them anyway
1149 if (enable_vmware_backdoor
)
1150 set_exception_intercept(svm
, GP_VECTOR
);
1152 svm_set_intercept(svm
, INTERCEPT_INTR
);
1153 svm_set_intercept(svm
, INTERCEPT_NMI
);
1154 svm_set_intercept(svm
, INTERCEPT_SMI
);
1155 svm_set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1156 svm_set_intercept(svm
, INTERCEPT_RDPMC
);
1157 svm_set_intercept(svm
, INTERCEPT_CPUID
);
1158 svm_set_intercept(svm
, INTERCEPT_INVD
);
1159 svm_set_intercept(svm
, INTERCEPT_INVLPG
);
1160 svm_set_intercept(svm
, INTERCEPT_INVLPGA
);
1161 svm_set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1162 svm_set_intercept(svm
, INTERCEPT_MSR_PROT
);
1163 svm_set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1164 svm_set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1165 svm_set_intercept(svm
, INTERCEPT_VMRUN
);
1166 svm_set_intercept(svm
, INTERCEPT_VMMCALL
);
1167 svm_set_intercept(svm
, INTERCEPT_VMLOAD
);
1168 svm_set_intercept(svm
, INTERCEPT_VMSAVE
);
1169 svm_set_intercept(svm
, INTERCEPT_STGI
);
1170 svm_set_intercept(svm
, INTERCEPT_CLGI
);
1171 svm_set_intercept(svm
, INTERCEPT_SKINIT
);
1172 svm_set_intercept(svm
, INTERCEPT_WBINVD
);
1173 svm_set_intercept(svm
, INTERCEPT_XSETBV
);
1174 svm_set_intercept(svm
, INTERCEPT_RDPRU
);
1175 svm_set_intercept(svm
, INTERCEPT_RSM
);
1177 if (!kvm_mwait_in_guest(svm
->vcpu
.kvm
)) {
1178 svm_set_intercept(svm
, INTERCEPT_MONITOR
);
1179 svm_set_intercept(svm
, INTERCEPT_MWAIT
);
1182 if (!kvm_hlt_in_guest(svm
->vcpu
.kvm
))
1183 svm_set_intercept(svm
, INTERCEPT_HLT
);
1185 control
->iopm_base_pa
= __sme_set(iopm_base
);
1186 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1187 control
->int_ctl
= V_INTR_MASKING_MASK
;
1189 init_seg(&save
->es
);
1190 init_seg(&save
->ss
);
1191 init_seg(&save
->ds
);
1192 init_seg(&save
->fs
);
1193 init_seg(&save
->gs
);
1195 save
->cs
.selector
= 0xf000;
1196 save
->cs
.base
= 0xffff0000;
1197 /* Executable/Readable Code Segment */
1198 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1199 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1200 save
->cs
.limit
= 0xffff;
1202 save
->gdtr
.limit
= 0xffff;
1203 save
->idtr
.limit
= 0xffff;
1205 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1206 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1208 svm_set_cr4(&svm
->vcpu
, 0);
1209 svm_set_efer(&svm
->vcpu
, 0);
1210 save
->dr6
= 0xffff0ff0;
1211 kvm_set_rflags(&svm
->vcpu
, 2);
1212 save
->rip
= 0x0000fff0;
1213 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1216 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1217 * It also updates the guest-visible cr0 value.
1219 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1220 kvm_mmu_reset_context(&svm
->vcpu
);
1222 save
->cr4
= X86_CR4_PAE
;
1226 /* Setup VMCB for Nested Paging */
1227 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1228 svm_clr_intercept(svm
, INTERCEPT_INVLPG
);
1229 clr_exception_intercept(svm
, PF_VECTOR
);
1230 svm_clr_intercept(svm
, INTERCEPT_CR3_READ
);
1231 svm_clr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1232 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1236 svm
->asid_generation
= 0;
1239 svm
->nested
.vmcb12_gpa
= 0;
1240 svm
->vcpu
.arch
.hflags
= 0;
1242 if (!kvm_pause_in_guest(svm
->vcpu
.kvm
)) {
1243 control
->pause_filter_count
= pause_filter_count
;
1244 if (pause_filter_thresh
)
1245 control
->pause_filter_thresh
= pause_filter_thresh
;
1246 svm_set_intercept(svm
, INTERCEPT_PAUSE
);
1248 svm_clr_intercept(svm
, INTERCEPT_PAUSE
);
1251 svm_check_invpcid(svm
);
1253 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1254 avic_init_vmcb(svm
);
1257 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1258 * in VMCB and clear intercepts to avoid #VMEXIT.
1261 svm_clr_intercept(svm
, INTERCEPT_VMLOAD
);
1262 svm_clr_intercept(svm
, INTERCEPT_VMSAVE
);
1263 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1267 svm_clr_intercept(svm
, INTERCEPT_STGI
);
1268 svm_clr_intercept(svm
, INTERCEPT_CLGI
);
1269 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1272 if (sev_guest(svm
->vcpu
.kvm
)) {
1273 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1274 clr_exception_intercept(svm
, UD_VECTOR
);
1276 if (sev_es_guest(svm
->vcpu
.kvm
)) {
1277 /* Perform SEV-ES specific VMCB updates */
1278 sev_es_init_vmcb(svm
);
1282 vmcb_mark_all_dirty(svm
->vmcb
);
1288 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1290 struct vcpu_svm
*svm
= to_svm(vcpu
);
1295 svm
->virt_spec_ctrl
= 0;
1298 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1299 MSR_IA32_APICBASE_ENABLE
;
1300 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1301 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1305 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, false);
1306 kvm_rdx_write(vcpu
, eax
);
1308 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1309 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1312 static int svm_create_vcpu(struct kvm_vcpu
*vcpu
)
1314 struct vcpu_svm
*svm
;
1315 struct page
*vmcb_page
;
1316 struct page
*vmsa_page
= NULL
;
1319 BUILD_BUG_ON(offsetof(struct vcpu_svm
, vcpu
) != 0);
1323 vmcb_page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_ZERO
);
1327 if (sev_es_guest(svm
->vcpu
.kvm
)) {
1329 * SEV-ES guests require a separate VMSA page used to contain
1330 * the encrypted register state of the guest.
1332 vmsa_page
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_ZERO
);
1334 goto error_free_vmcb_page
;
1337 * SEV-ES guests maintain an encrypted version of their FPU
1338 * state which is restored and saved on VMRUN and VMEXIT.
1339 * Free the fpu structure to prevent KVM from attempting to
1340 * access the FPU state.
1342 kvm_free_guest_fpu(vcpu
);
1345 err
= avic_init_vcpu(svm
);
1347 goto error_free_vmsa_page
;
1349 /* We initialize this flag to true to make sure that the is_running
1350 * bit would be set the first time the vcpu is loaded.
1352 if (irqchip_in_kernel(vcpu
->kvm
) && kvm_apicv_activated(vcpu
->kvm
))
1353 svm
->avic_is_running
= true;
1355 svm
->msrpm
= svm_vcpu_alloc_msrpm();
1358 goto error_free_vmsa_page
;
1361 svm_vcpu_init_msrpm(vcpu
, svm
->msrpm
);
1363 svm
->vmcb
= page_address(vmcb_page
);
1364 svm
->vmcb_pa
= __sme_set(page_to_pfn(vmcb_page
) << PAGE_SHIFT
);
1367 svm
->vmsa
= page_address(vmsa_page
);
1369 svm
->asid_generation
= 0;
1372 svm_init_osvw(vcpu
);
1373 vcpu
->arch
.microcode_version
= 0x01000065;
1375 if (sev_es_guest(svm
->vcpu
.kvm
))
1376 /* Perform SEV-ES specific VMCB creation updates */
1377 sev_es_create_vcpu(svm
);
1381 error_free_vmsa_page
:
1383 __free_page(vmsa_page
);
1384 error_free_vmcb_page
:
1385 __free_page(vmcb_page
);
1390 static void svm_clear_current_vmcb(struct vmcb
*vmcb
)
1394 for_each_online_cpu(i
)
1395 cmpxchg(&per_cpu(svm_data
, i
)->current_vmcb
, vmcb
, NULL
);
1398 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1400 struct vcpu_svm
*svm
= to_svm(vcpu
);
1403 * The vmcb page can be recycled, causing a false negative in
1404 * svm_vcpu_load(). So, ensure that no logical CPU has this
1405 * vmcb page recorded as its current vmcb.
1407 svm_clear_current_vmcb(svm
->vmcb
);
1409 svm_free_nested(svm
);
1411 sev_free_vcpu(vcpu
);
1413 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
1414 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1417 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1419 struct vcpu_svm
*svm
= to_svm(vcpu
);
1420 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
1423 if (unlikely(cpu
!= vcpu
->cpu
)) {
1424 svm
->asid_generation
= 0;
1425 vmcb_mark_all_dirty(svm
->vmcb
);
1428 if (sev_es_guest(svm
->vcpu
.kvm
)) {
1429 sev_es_vcpu_load(svm
, cpu
);
1431 #ifdef CONFIG_X86_64
1432 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1434 savesegment(fs
, svm
->host
.fs
);
1435 savesegment(gs
, svm
->host
.gs
);
1436 svm
->host
.ldt
= kvm_read_ldt();
1438 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1439 rdmsrl(host_save_user_msrs
[i
].index
,
1440 svm
->host_user_msrs
[i
]);
1443 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1444 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1445 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1446 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1447 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1450 /* This assumes that the kernel never uses MSR_TSC_AUX */
1451 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1452 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
1454 if (sd
->current_vmcb
!= svm
->vmcb
) {
1455 sd
->current_vmcb
= svm
->vmcb
;
1456 indirect_branch_prediction_barrier();
1458 avic_vcpu_load(vcpu
, cpu
);
1461 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1463 struct vcpu_svm
*svm
= to_svm(vcpu
);
1466 avic_vcpu_put(vcpu
);
1468 ++vcpu
->stat
.host_state_reload
;
1469 if (sev_es_guest(svm
->vcpu
.kvm
)) {
1470 sev_es_vcpu_put(svm
);
1472 kvm_load_ldt(svm
->host
.ldt
);
1473 #ifdef CONFIG_X86_64
1474 loadsegment(fs
, svm
->host
.fs
);
1475 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
1476 load_gs_index(svm
->host
.gs
);
1478 #ifdef CONFIG_X86_32_LAZY_GS
1479 loadsegment(gs
, svm
->host
.gs
);
1483 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1484 wrmsrl(host_save_user_msrs
[i
].index
,
1485 svm
->host_user_msrs
[i
]);
1489 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1491 struct vcpu_svm
*svm
= to_svm(vcpu
);
1492 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
1494 if (svm
->nmi_singlestep
) {
1495 /* Hide our flags if they were not set by the guest */
1496 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1497 rflags
&= ~X86_EFLAGS_TF
;
1498 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1499 rflags
&= ~X86_EFLAGS_RF
;
1504 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1506 if (to_svm(vcpu
)->nmi_singlestep
)
1507 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1510 * Any change of EFLAGS.VM is accompanied by a reload of SS
1511 * (caused by either a task switch or an inter-privilege IRET),
1512 * so we do not need to update the CPL here.
1514 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1517 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1520 case VCPU_EXREG_PDPTR
:
1521 BUG_ON(!npt_enabled
);
1522 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1529 static void svm_set_vintr(struct vcpu_svm
*svm
)
1531 struct vmcb_control_area
*control
;
1533 /* The following fields are ignored when AVIC is enabled */
1534 WARN_ON(kvm_vcpu_apicv_active(&svm
->vcpu
));
1535 svm_set_intercept(svm
, INTERCEPT_VINTR
);
1538 * This is just a dummy VINTR to actually cause a vmexit to happen.
1539 * Actual injection of virtual interrupts happens through EVENTINJ.
1541 control
= &svm
->vmcb
->control
;
1542 control
->int_vector
= 0x0;
1543 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
1544 control
->int_ctl
|= V_IRQ_MASK
|
1545 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
1546 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTR
);
1549 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1551 const u32 mask
= V_TPR_MASK
| V_GIF_ENABLE_MASK
| V_GIF_MASK
| V_INTR_MASKING_MASK
;
1552 svm_clr_intercept(svm
, INTERCEPT_VINTR
);
1554 /* Drop int_ctl fields related to VINTR injection. */
1555 svm
->vmcb
->control
.int_ctl
&= mask
;
1556 if (is_guest_mode(&svm
->vcpu
)) {
1557 svm
->nested
.hsave
->control
.int_ctl
&= mask
;
1559 WARN_ON((svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
) !=
1560 (svm
->nested
.ctl
.int_ctl
& V_TPR_MASK
));
1561 svm
->vmcb
->control
.int_ctl
|= svm
->nested
.ctl
.int_ctl
& ~mask
;
1564 vmcb_mark_dirty(svm
->vmcb
, VMCB_INTR
);
1567 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1569 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1572 case VCPU_SREG_CS
: return &save
->cs
;
1573 case VCPU_SREG_DS
: return &save
->ds
;
1574 case VCPU_SREG_ES
: return &save
->es
;
1575 case VCPU_SREG_FS
: return &save
->fs
;
1576 case VCPU_SREG_GS
: return &save
->gs
;
1577 case VCPU_SREG_SS
: return &save
->ss
;
1578 case VCPU_SREG_TR
: return &save
->tr
;
1579 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1585 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1587 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1592 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1593 struct kvm_segment
*var
, int seg
)
1595 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1597 var
->base
= s
->base
;
1598 var
->limit
= s
->limit
;
1599 var
->selector
= s
->selector
;
1600 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1601 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1602 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1603 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1604 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1605 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1606 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1609 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1610 * However, the SVM spec states that the G bit is not observed by the
1611 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1612 * So let's synthesize a legal G bit for all segments, this helps
1613 * running KVM nested. It also helps cross-vendor migration, because
1614 * Intel's vmentry has a check on the 'G' bit.
1616 var
->g
= s
->limit
> 0xfffff;
1619 * AMD's VMCB does not have an explicit unusable field, so emulate it
1620 * for cross vendor migration purposes by "not present"
1622 var
->unusable
= !var
->present
;
1627 * Work around a bug where the busy flag in the tr selector
1637 * The accessed bit must always be set in the segment
1638 * descriptor cache, although it can be cleared in the
1639 * descriptor, the cached bit always remains at 1. Since
1640 * Intel has a check on this, set it here to support
1641 * cross-vendor migration.
1648 * On AMD CPUs sometimes the DB bit in the segment
1649 * descriptor is left as 1, although the whole segment has
1650 * been made unusable. Clear it here to pass an Intel VMX
1651 * entry check when cross vendor migrating.
1655 /* This is symmetric with svm_set_segment() */
1656 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1661 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1663 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1668 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1670 struct vcpu_svm
*svm
= to_svm(vcpu
);
1672 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1673 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1676 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1678 struct vcpu_svm
*svm
= to_svm(vcpu
);
1680 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1681 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1682 vmcb_mark_dirty(svm
->vmcb
, VMCB_DT
);
1685 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1687 struct vcpu_svm
*svm
= to_svm(vcpu
);
1689 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1690 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1693 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1695 struct vcpu_svm
*svm
= to_svm(vcpu
);
1697 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1698 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1699 vmcb_mark_dirty(svm
->vmcb
, VMCB_DT
);
1702 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1708 * SEV-ES guests must always keep the CR intercepts cleared. CR
1709 * tracking is done using the CR write traps.
1711 if (sev_es_guest(svm
->vcpu
.kvm
))
1714 gcr0
= svm
->vcpu
.arch
.cr0
;
1715 hcr0
= &svm
->vmcb
->save
.cr0
;
1716 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1717 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1719 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
1721 if (gcr0
== *hcr0
) {
1722 svm_clr_intercept(svm
, INTERCEPT_CR0_READ
);
1723 svm_clr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1725 svm_set_intercept(svm
, INTERCEPT_CR0_READ
);
1726 svm_set_intercept(svm
, INTERCEPT_CR0_WRITE
);
1730 void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1732 struct vcpu_svm
*svm
= to_svm(vcpu
);
1734 #ifdef CONFIG_X86_64
1735 if (vcpu
->arch
.efer
& EFER_LME
&& !vcpu
->arch
.guest_state_protected
) {
1736 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1737 vcpu
->arch
.efer
|= EFER_LMA
;
1738 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1741 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1742 vcpu
->arch
.efer
&= ~EFER_LMA
;
1743 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1747 vcpu
->arch
.cr0
= cr0
;
1750 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1753 * re-enable caching here because the QEMU bios
1754 * does not do it - this results in some delay at
1757 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
1758 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1759 svm
->vmcb
->save
.cr0
= cr0
;
1760 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
1761 update_cr0_intercept(svm
);
1764 static bool svm_is_valid_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1769 void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1771 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
1772 unsigned long old_cr4
= vcpu
->arch
.cr4
;
1774 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1775 svm_flush_tlb(vcpu
);
1777 vcpu
->arch
.cr4
= cr4
;
1780 cr4
|= host_cr4_mce
;
1781 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1782 vmcb_mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1784 if ((cr4
^ old_cr4
) & (X86_CR4_OSXSAVE
| X86_CR4_PKE
))
1785 kvm_update_cpuid_runtime(vcpu
);
1788 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1789 struct kvm_segment
*var
, int seg
)
1791 struct vcpu_svm
*svm
= to_svm(vcpu
);
1792 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1794 s
->base
= var
->base
;
1795 s
->limit
= var
->limit
;
1796 s
->selector
= var
->selector
;
1797 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1798 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1799 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1800 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
1801 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1802 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1803 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1804 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1807 * This is always accurate, except if SYSRET returned to a segment
1808 * with SS.DPL != 3. Intel does not have this quirk, and always
1809 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1810 * would entail passing the CPL to userspace and back.
1812 if (seg
== VCPU_SREG_SS
)
1813 /* This is symmetric with svm_get_segment() */
1814 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
1816 vmcb_mark_dirty(svm
->vmcb
, VMCB_SEG
);
1819 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1821 struct vcpu_svm
*svm
= to_svm(vcpu
);
1823 clr_exception_intercept(svm
, BP_VECTOR
);
1825 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1826 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1827 set_exception_intercept(svm
, BP_VECTOR
);
1831 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1833 if (sd
->next_asid
> sd
->max_asid
) {
1834 ++sd
->asid_generation
;
1835 sd
->next_asid
= sd
->min_asid
;
1836 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1837 vmcb_mark_dirty(svm
->vmcb
, VMCB_ASID
);
1840 svm
->asid_generation
= sd
->asid_generation
;
1841 svm
->asid
= sd
->next_asid
++;
1844 static void svm_set_dr6(struct vcpu_svm
*svm
, unsigned long value
)
1846 struct vmcb
*vmcb
= svm
->vmcb
;
1848 if (svm
->vcpu
.arch
.guest_state_protected
)
1851 if (unlikely(value
!= vmcb
->save
.dr6
)) {
1852 vmcb
->save
.dr6
= value
;
1853 vmcb_mark_dirty(vmcb
, VMCB_DR
);
1857 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
1859 struct vcpu_svm
*svm
= to_svm(vcpu
);
1861 if (vcpu
->arch
.guest_state_protected
)
1864 get_debugreg(vcpu
->arch
.db
[0], 0);
1865 get_debugreg(vcpu
->arch
.db
[1], 1);
1866 get_debugreg(vcpu
->arch
.db
[2], 2);
1867 get_debugreg(vcpu
->arch
.db
[3], 3);
1869 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1870 * because db_interception might need it. We can do it before vmentry.
1872 vcpu
->arch
.dr6
= svm
->vmcb
->save
.dr6
;
1873 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
1874 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
1875 set_dr_intercepts(svm
);
1878 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1880 struct vcpu_svm
*svm
= to_svm(vcpu
);
1882 if (vcpu
->arch
.guest_state_protected
)
1885 svm
->vmcb
->save
.dr7
= value
;
1886 vmcb_mark_dirty(svm
->vmcb
, VMCB_DR
);
1889 static int pf_interception(struct vcpu_svm
*svm
)
1891 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1892 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
1894 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
1895 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
1896 svm
->vmcb
->control
.insn_bytes
: NULL
,
1897 svm
->vmcb
->control
.insn_len
);
1900 static int npf_interception(struct vcpu_svm
*svm
)
1902 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
1903 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
1905 trace_kvm_page_fault(fault_address
, error_code
);
1906 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1907 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
1908 svm
->vmcb
->control
.insn_bytes
: NULL
,
1909 svm
->vmcb
->control
.insn_len
);
1912 static int db_interception(struct vcpu_svm
*svm
)
1914 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1915 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1917 if (!(svm
->vcpu
.guest_debug
&
1918 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1919 !svm
->nmi_singlestep
) {
1920 u32 payload
= (svm
->vmcb
->save
.dr6
^ DR6_RTM
) & ~DR6_FIXED_1
;
1921 kvm_queue_exception_p(&svm
->vcpu
, DB_VECTOR
, payload
);
1925 if (svm
->nmi_singlestep
) {
1926 disable_nmi_singlestep(svm
);
1927 /* Make sure we check for pending NMIs upon entry */
1928 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1931 if (svm
->vcpu
.guest_debug
&
1932 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1933 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1934 kvm_run
->debug
.arch
.dr6
= svm
->vmcb
->save
.dr6
;
1935 kvm_run
->debug
.arch
.dr7
= svm
->vmcb
->save
.dr7
;
1936 kvm_run
->debug
.arch
.pc
=
1937 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1938 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1945 static int bp_interception(struct vcpu_svm
*svm
)
1947 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1949 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1950 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1951 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1955 static int ud_interception(struct vcpu_svm
*svm
)
1957 return handle_ud(&svm
->vcpu
);
1960 static int ac_interception(struct vcpu_svm
*svm
)
1962 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
1966 static int gp_interception(struct vcpu_svm
*svm
)
1968 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1969 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
1971 WARN_ON_ONCE(!enable_vmware_backdoor
);
1974 * VMware backdoor emulation on #GP interception only handles IN{S},
1975 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1978 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
1981 return kvm_emulate_instruction(vcpu
, EMULTYPE_VMWARE_GP
);
1984 static bool is_erratum_383(void)
1989 if (!erratum_383_found
)
1992 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1996 /* Bit 62 may or may not be set for this mce */
1997 value
&= ~(1ULL << 62);
1999 if (value
!= 0xb600000000010015ULL
)
2002 /* Clear MCi_STATUS registers */
2003 for (i
= 0; i
< 6; ++i
)
2004 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2006 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2010 value
&= ~(1ULL << 2);
2011 low
= lower_32_bits(value
);
2012 high
= upper_32_bits(value
);
2014 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2017 /* Flush tlb to evict multi-match entries */
2023 static void svm_handle_mce(struct vcpu_svm
*svm
)
2025 if (is_erratum_383()) {
2027 * Erratum 383 triggered. Guest state is corrupt so kill the
2030 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2032 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2038 * On an #MC intercept the MCE handler is not called automatically in
2039 * the host. So do it by hand here.
2041 kvm_machine_check();
2044 static int mc_interception(struct vcpu_svm
*svm
)
2049 static int shutdown_interception(struct vcpu_svm
*svm
)
2051 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2054 * The VM save area has already been encrypted so it
2055 * cannot be reinitialized - just terminate.
2057 if (sev_es_guest(svm
->vcpu
.kvm
))
2061 * VMCB is undefined after a SHUTDOWN intercept
2062 * so reinitialize it.
2064 clear_page(svm
->vmcb
);
2067 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2071 static int io_interception(struct vcpu_svm
*svm
)
2073 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2074 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2075 int size
, in
, string
;
2078 ++svm
->vcpu
.stat
.io_exits
;
2079 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2080 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2081 port
= io_info
>> 16;
2082 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2085 if (sev_es_guest(vcpu
->kvm
))
2086 return sev_es_string_io(svm
, size
, port
, in
);
2088 return kvm_emulate_instruction(vcpu
, 0);
2091 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2093 return kvm_fast_pio(&svm
->vcpu
, size
, port
, in
);
2096 static int nmi_interception(struct vcpu_svm
*svm
)
2101 static int intr_interception(struct vcpu_svm
*svm
)
2103 ++svm
->vcpu
.stat
.irq_exits
;
2107 static int nop_on_interception(struct vcpu_svm
*svm
)
2112 static int halt_interception(struct vcpu_svm
*svm
)
2114 return kvm_emulate_halt(&svm
->vcpu
);
2117 static int vmmcall_interception(struct vcpu_svm
*svm
)
2119 return kvm_emulate_hypercall(&svm
->vcpu
);
2122 static int vmload_interception(struct vcpu_svm
*svm
)
2124 struct vmcb
*nested_vmcb
;
2125 struct kvm_host_map map
;
2128 if (nested_svm_check_permissions(svm
))
2131 ret
= kvm_vcpu_map(&svm
->vcpu
, gpa_to_gfn(svm
->vmcb
->save
.rax
), &map
);
2134 kvm_inject_gp(&svm
->vcpu
, 0);
2138 nested_vmcb
= map
.hva
;
2140 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2142 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2143 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
2148 static int vmsave_interception(struct vcpu_svm
*svm
)
2150 struct vmcb
*nested_vmcb
;
2151 struct kvm_host_map map
;
2154 if (nested_svm_check_permissions(svm
))
2157 ret
= kvm_vcpu_map(&svm
->vcpu
, gpa_to_gfn(svm
->vmcb
->save
.rax
), &map
);
2160 kvm_inject_gp(&svm
->vcpu
, 0);
2164 nested_vmcb
= map
.hva
;
2166 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2168 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2169 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
2174 static int vmrun_interception(struct vcpu_svm
*svm
)
2176 if (nested_svm_check_permissions(svm
))
2179 return nested_svm_vmrun(svm
);
2182 void svm_set_gif(struct vcpu_svm
*svm
, bool value
)
2186 * If VGIF is enabled, the STGI intercept is only added to
2187 * detect the opening of the SMI/NMI window; remove it now.
2188 * Likewise, clear the VINTR intercept, we will set it
2189 * again while processing KVM_REQ_EVENT if needed.
2191 if (vgif_enabled(svm
))
2192 svm_clr_intercept(svm
, INTERCEPT_STGI
);
2193 if (svm_is_intercept(svm
, INTERCEPT_VINTR
))
2194 svm_clear_vintr(svm
);
2197 if (svm
->vcpu
.arch
.smi_pending
||
2198 svm
->vcpu
.arch
.nmi_pending
||
2199 kvm_cpu_has_injectable_intr(&svm
->vcpu
))
2200 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2205 * After a CLGI no interrupts should come. But if vGIF is
2206 * in use, we still rely on the VINTR intercept (rather than
2207 * STGI) to detect an open interrupt window.
2209 if (!vgif_enabled(svm
))
2210 svm_clear_vintr(svm
);
2214 static int stgi_interception(struct vcpu_svm
*svm
)
2218 if (nested_svm_check_permissions(svm
))
2221 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2222 svm_set_gif(svm
, true);
2226 static int clgi_interception(struct vcpu_svm
*svm
)
2230 if (nested_svm_check_permissions(svm
))
2233 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2234 svm_set_gif(svm
, false);
2238 static int invlpga_interception(struct vcpu_svm
*svm
)
2240 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2242 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_rcx_read(&svm
->vcpu
),
2243 kvm_rax_read(&svm
->vcpu
));
2245 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2246 kvm_mmu_invlpg(vcpu
, kvm_rax_read(&svm
->vcpu
));
2248 return kvm_skip_emulated_instruction(&svm
->vcpu
);
2251 static int skinit_interception(struct vcpu_svm
*svm
)
2253 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_rax_read(&svm
->vcpu
));
2255 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2259 static int wbinvd_interception(struct vcpu_svm
*svm
)
2261 return kvm_emulate_wbinvd(&svm
->vcpu
);
2264 static int xsetbv_interception(struct vcpu_svm
*svm
)
2266 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2267 u32 index
= kvm_rcx_read(&svm
->vcpu
);
2269 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2270 return kvm_skip_emulated_instruction(&svm
->vcpu
);
2276 static int rdpru_interception(struct vcpu_svm
*svm
)
2278 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2282 static int task_switch_interception(struct vcpu_svm
*svm
)
2286 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2287 SVM_EXITINTINFO_TYPE_MASK
;
2288 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2290 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2292 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2293 bool has_error_code
= false;
2296 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2298 if (svm
->vmcb
->control
.exit_info_2
&
2299 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2300 reason
= TASK_SWITCH_IRET
;
2301 else if (svm
->vmcb
->control
.exit_info_2
&
2302 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2303 reason
= TASK_SWITCH_JMP
;
2305 reason
= TASK_SWITCH_GATE
;
2307 reason
= TASK_SWITCH_CALL
;
2309 if (reason
== TASK_SWITCH_GATE
) {
2311 case SVM_EXITINTINFO_TYPE_NMI
:
2312 svm
->vcpu
.arch
.nmi_injected
= false;
2314 case SVM_EXITINTINFO_TYPE_EXEPT
:
2315 if (svm
->vmcb
->control
.exit_info_2
&
2316 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2317 has_error_code
= true;
2319 (u32
)svm
->vmcb
->control
.exit_info_2
;
2321 kvm_clear_exception_queue(&svm
->vcpu
);
2323 case SVM_EXITINTINFO_TYPE_INTR
:
2324 kvm_clear_interrupt_queue(&svm
->vcpu
);
2331 if (reason
!= TASK_SWITCH_GATE
||
2332 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2333 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2334 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
))) {
2335 if (!skip_emulated_instruction(&svm
->vcpu
))
2339 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2342 return kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
2343 has_error_code
, error_code
);
2346 static int cpuid_interception(struct vcpu_svm
*svm
)
2348 return kvm_emulate_cpuid(&svm
->vcpu
);
2351 static int iret_interception(struct vcpu_svm
*svm
)
2353 ++svm
->vcpu
.stat
.nmi_window_exits
;
2354 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2355 if (!sev_es_guest(svm
->vcpu
.kvm
)) {
2356 svm_clr_intercept(svm
, INTERCEPT_IRET
);
2357 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2359 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2363 static int invd_interception(struct vcpu_svm
*svm
)
2365 /* Treat an INVD instruction as a NOP and just skip it. */
2366 return kvm_skip_emulated_instruction(&svm
->vcpu
);
2369 static int invlpg_interception(struct vcpu_svm
*svm
)
2371 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2372 return kvm_emulate_instruction(&svm
->vcpu
, 0);
2374 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2375 return kvm_skip_emulated_instruction(&svm
->vcpu
);
2378 static int emulate_on_interception(struct vcpu_svm
*svm
)
2380 return kvm_emulate_instruction(&svm
->vcpu
, 0);
2383 static int rsm_interception(struct vcpu_svm
*svm
)
2385 return kvm_emulate_instruction_from_buffer(&svm
->vcpu
, rsm_ins_bytes
, 2);
2388 static int rdpmc_interception(struct vcpu_svm
*svm
)
2393 return emulate_on_interception(svm
);
2395 err
= kvm_rdpmc(&svm
->vcpu
);
2396 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
2399 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
2402 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
2405 if (!is_guest_mode(&svm
->vcpu
) ||
2406 (!(vmcb_is_intercept(&svm
->nested
.ctl
, INTERCEPT_SELECTIVE_CR0
))))
2409 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2410 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2413 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2414 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2420 #define CR_VALID (1ULL << 63)
2422 static int cr_interception(struct vcpu_svm
*svm
)
2428 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2429 return emulate_on_interception(svm
);
2431 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2432 return emulate_on_interception(svm
);
2434 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2435 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
2436 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
2438 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2441 if (cr
>= 16) { /* mov to cr */
2443 val
= kvm_register_read(&svm
->vcpu
, reg
);
2444 trace_kvm_cr_write(cr
, val
);
2447 if (!check_selective_cr0_intercepted(svm
, val
))
2448 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2454 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2457 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2460 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2463 WARN(1, "unhandled write to CR%d", cr
);
2464 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2467 } else { /* mov from cr */
2470 val
= kvm_read_cr0(&svm
->vcpu
);
2473 val
= svm
->vcpu
.arch
.cr2
;
2476 val
= kvm_read_cr3(&svm
->vcpu
);
2479 val
= kvm_read_cr4(&svm
->vcpu
);
2482 val
= kvm_get_cr8(&svm
->vcpu
);
2485 WARN(1, "unhandled read from CR%d", cr
);
2486 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2489 kvm_register_write(&svm
->vcpu
, reg
, val
);
2490 trace_kvm_cr_read(cr
, val
);
2492 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
2495 static int cr_trap(struct vcpu_svm
*svm
)
2497 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2498 unsigned long old_value
, new_value
;
2502 new_value
= (unsigned long)svm
->vmcb
->control
.exit_info_1
;
2504 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_CR0_WRITE_TRAP
;
2507 old_value
= kvm_read_cr0(vcpu
);
2508 svm_set_cr0(vcpu
, new_value
);
2510 kvm_post_set_cr0(vcpu
, old_value
, new_value
);
2513 old_value
= kvm_read_cr4(vcpu
);
2514 svm_set_cr4(vcpu
, new_value
);
2516 kvm_post_set_cr4(vcpu
, old_value
, new_value
);
2519 ret
= kvm_set_cr8(&svm
->vcpu
, new_value
);
2522 WARN(1, "unhandled CR%d write trap", cr
);
2523 kvm_queue_exception(vcpu
, UD_VECTOR
);
2527 return kvm_complete_insn_gp(vcpu
, ret
);
2530 static int dr_interception(struct vcpu_svm
*svm
)
2535 if (svm
->vcpu
.guest_debug
== 0) {
2537 * No more DR vmexits; force a reload of the debug registers
2538 * and reenter on this instruction. The next vmexit will
2539 * retrieve the full state of the debug registers.
2541 clr_dr_intercepts(svm
);
2542 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
2546 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2547 return emulate_on_interception(svm
);
2549 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2550 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2552 if (dr
>= 16) { /* mov to DRn */
2553 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
2555 val
= kvm_register_read(&svm
->vcpu
, reg
);
2556 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
2558 if (!kvm_require_dr(&svm
->vcpu
, dr
))
2560 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
2561 kvm_register_write(&svm
->vcpu
, reg
, val
);
2564 return kvm_skip_emulated_instruction(&svm
->vcpu
);
2567 static int cr8_write_interception(struct vcpu_svm
*svm
)
2569 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2572 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2573 /* instruction emulation calls kvm_set_cr8() */
2574 r
= cr_interception(svm
);
2575 if (lapic_in_kernel(&svm
->vcpu
))
2577 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2579 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2583 static int efer_trap(struct vcpu_svm
*svm
)
2585 struct msr_data msr_info
;
2589 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2590 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2591 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2592 * the guest doesn't have X86_FEATURE_SVM.
2594 msr_info
.host_initiated
= false;
2595 msr_info
.index
= MSR_EFER
;
2596 msr_info
.data
= svm
->vmcb
->control
.exit_info_1
& ~EFER_SVME
;
2597 ret
= kvm_set_msr_common(&svm
->vcpu
, &msr_info
);
2599 return kvm_complete_insn_gp(&svm
->vcpu
, ret
);
2602 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
2606 switch (msr
->index
) {
2607 case MSR_F10H_DECFG
:
2608 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
2609 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
2611 case MSR_IA32_PERF_CAPABILITIES
:
2614 return KVM_MSR_RET_INVALID
;
2620 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2622 struct vcpu_svm
*svm
= to_svm(vcpu
);
2624 switch (msr_info
->index
) {
2626 msr_info
->data
= svm
->vmcb
->save
.star
;
2628 #ifdef CONFIG_X86_64
2630 msr_info
->data
= svm
->vmcb
->save
.lstar
;
2633 msr_info
->data
= svm
->vmcb
->save
.cstar
;
2635 case MSR_KERNEL_GS_BASE
:
2636 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
2638 case MSR_SYSCALL_MASK
:
2639 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
2642 case MSR_IA32_SYSENTER_CS
:
2643 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
2645 case MSR_IA32_SYSENTER_EIP
:
2646 msr_info
->data
= svm
->sysenter_eip
;
2648 case MSR_IA32_SYSENTER_ESP
:
2649 msr_info
->data
= svm
->sysenter_esp
;
2652 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
2654 if (!msr_info
->host_initiated
&&
2655 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2657 msr_info
->data
= svm
->tsc_aux
;
2660 * Nobody will change the following 5 values in the VMCB so we can
2661 * safely return them on rdmsr. They will always be 0 until LBRV is
2664 case MSR_IA32_DEBUGCTLMSR
:
2665 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
2667 case MSR_IA32_LASTBRANCHFROMIP
:
2668 msr_info
->data
= svm
->vmcb
->save
.br_from
;
2670 case MSR_IA32_LASTBRANCHTOIP
:
2671 msr_info
->data
= svm
->vmcb
->save
.br_to
;
2673 case MSR_IA32_LASTINTFROMIP
:
2674 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
2676 case MSR_IA32_LASTINTTOIP
:
2677 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
2679 case MSR_VM_HSAVE_PA
:
2680 msr_info
->data
= svm
->nested
.hsave_msr
;
2683 msr_info
->data
= svm
->nested
.vm_cr_msr
;
2685 case MSR_IA32_SPEC_CTRL
:
2686 if (!msr_info
->host_initiated
&&
2687 !guest_has_spec_ctrl_msr(vcpu
))
2690 msr_info
->data
= svm
->spec_ctrl
;
2692 case MSR_AMD64_VIRT_SPEC_CTRL
:
2693 if (!msr_info
->host_initiated
&&
2694 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
2697 msr_info
->data
= svm
->virt_spec_ctrl
;
2699 case MSR_F15H_IC_CFG
: {
2703 family
= guest_cpuid_family(vcpu
);
2704 model
= guest_cpuid_model(vcpu
);
2706 if (family
< 0 || model
< 0)
2707 return kvm_get_msr_common(vcpu
, msr_info
);
2711 if (family
== 0x15 &&
2712 (model
>= 0x2 && model
< 0x20))
2713 msr_info
->data
= 0x1E;
2716 case MSR_F10H_DECFG
:
2717 msr_info
->data
= svm
->msr_decfg
;
2720 return kvm_get_msr_common(vcpu
, msr_info
);
2725 static int svm_complete_emulated_msr(struct kvm_vcpu
*vcpu
, int err
)
2727 struct vcpu_svm
*svm
= to_svm(vcpu
);
2728 if (!sev_es_guest(svm
->vcpu
.kvm
) || !err
)
2729 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
2731 ghcb_set_sw_exit_info_1(svm
->ghcb
, 1);
2732 ghcb_set_sw_exit_info_2(svm
->ghcb
,
2734 SVM_EVTINJ_TYPE_EXEPT
|
2739 static int rdmsr_interception(struct vcpu_svm
*svm
)
2741 return kvm_emulate_rdmsr(&svm
->vcpu
);
2744 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2746 struct vcpu_svm
*svm
= to_svm(vcpu
);
2747 int svm_dis
, chg_mask
;
2749 if (data
& ~SVM_VM_CR_VALID_MASK
)
2752 chg_mask
= SVM_VM_CR_VALID_MASK
;
2754 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2755 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2757 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2758 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2760 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2762 /* check for svm_disable while efer.svme is set */
2763 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2769 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
2771 struct vcpu_svm
*svm
= to_svm(vcpu
);
2773 u32 ecx
= msr
->index
;
2774 u64 data
= msr
->data
;
2776 case MSR_IA32_CR_PAT
:
2777 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2779 vcpu
->arch
.pat
= data
;
2780 svm
->vmcb
->save
.g_pat
= data
;
2781 vmcb_mark_dirty(svm
->vmcb
, VMCB_NPT
);
2783 case MSR_IA32_SPEC_CTRL
:
2784 if (!msr
->host_initiated
&&
2785 !guest_has_spec_ctrl_msr(vcpu
))
2788 if (kvm_spec_ctrl_test_value(data
))
2791 svm
->spec_ctrl
= data
;
2797 * When it's written (to non-zero) for the first time, pass
2801 * The handling of the MSR bitmap for L2 guests is done in
2802 * nested_svm_vmrun_msrpm.
2803 * We update the L1 MSR bit as well since it will end up
2804 * touching the MSR anyway now.
2806 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
2808 case MSR_IA32_PRED_CMD
:
2809 if (!msr
->host_initiated
&&
2810 !guest_has_pred_cmd_msr(vcpu
))
2813 if (data
& ~PRED_CMD_IBPB
)
2815 if (!boot_cpu_has(X86_FEATURE_IBPB
))
2820 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
2821 set_msr_interception(vcpu
, svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
2823 case MSR_AMD64_VIRT_SPEC_CTRL
:
2824 if (!msr
->host_initiated
&&
2825 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
2828 if (data
& ~SPEC_CTRL_SSBD
)
2831 svm
->virt_spec_ctrl
= data
;
2834 svm
->vmcb
->save
.star
= data
;
2836 #ifdef CONFIG_X86_64
2838 svm
->vmcb
->save
.lstar
= data
;
2841 svm
->vmcb
->save
.cstar
= data
;
2843 case MSR_KERNEL_GS_BASE
:
2844 svm
->vmcb
->save
.kernel_gs_base
= data
;
2846 case MSR_SYSCALL_MASK
:
2847 svm
->vmcb
->save
.sfmask
= data
;
2850 case MSR_IA32_SYSENTER_CS
:
2851 svm
->vmcb
->save
.sysenter_cs
= data
;
2853 case MSR_IA32_SYSENTER_EIP
:
2854 svm
->sysenter_eip
= data
;
2855 svm
->vmcb
->save
.sysenter_eip
= data
;
2857 case MSR_IA32_SYSENTER_ESP
:
2858 svm
->sysenter_esp
= data
;
2859 svm
->vmcb
->save
.sysenter_esp
= data
;
2862 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
2865 if (!msr
->host_initiated
&&
2866 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
2870 * This is rare, so we update the MSR here instead of using
2871 * direct_access_msrs. Doing that would require a rdmsr in
2874 svm
->tsc_aux
= data
;
2875 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
2877 case MSR_IA32_DEBUGCTLMSR
:
2878 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2879 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2883 if (data
& DEBUGCTL_RESERVED_BITS
)
2886 svm
->vmcb
->save
.dbgctl
= data
;
2887 vmcb_mark_dirty(svm
->vmcb
, VMCB_LBR
);
2888 if (data
& (1ULL<<0))
2889 svm_enable_lbrv(vcpu
);
2891 svm_disable_lbrv(vcpu
);
2893 case MSR_VM_HSAVE_PA
:
2894 svm
->nested
.hsave_msr
= data
;
2897 return svm_set_vm_cr(vcpu
, data
);
2899 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2901 case MSR_F10H_DECFG
: {
2902 struct kvm_msr_entry msr_entry
;
2904 msr_entry
.index
= msr
->index
;
2905 if (svm_get_msr_feature(&msr_entry
))
2908 /* Check the supported bits */
2909 if (data
& ~msr_entry
.data
)
2912 /* Don't allow the guest to change a bit, #GP */
2913 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
2916 svm
->msr_decfg
= data
;
2919 case MSR_IA32_APICBASE
:
2920 if (kvm_vcpu_apicv_active(vcpu
))
2921 avic_update_vapic_bar(to_svm(vcpu
), data
);
2924 return kvm_set_msr_common(vcpu
, msr
);
2929 static int wrmsr_interception(struct vcpu_svm
*svm
)
2931 return kvm_emulate_wrmsr(&svm
->vcpu
);
2934 static int msr_interception(struct vcpu_svm
*svm
)
2936 if (svm
->vmcb
->control
.exit_info_1
)
2937 return wrmsr_interception(svm
);
2939 return rdmsr_interception(svm
);
2942 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2944 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2945 svm_clear_vintr(svm
);
2948 * For AVIC, the only reason to end up here is ExtINTs.
2949 * In this case AVIC was temporarily disabled for
2950 * requesting the IRQ window and we have to re-enable it.
2952 svm_toggle_avic_for_irq_window(&svm
->vcpu
, true);
2954 ++svm
->vcpu
.stat
.irq_window_exits
;
2958 static int pause_interception(struct vcpu_svm
*svm
)
2960 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2964 * CPL is not made available for an SEV-ES guest, therefore
2965 * vcpu->arch.preempted_in_kernel can never be true. Just
2966 * set in_kernel to false as well.
2968 in_kernel
= !sev_es_guest(svm
->vcpu
.kvm
) && svm_get_cpl(vcpu
) == 0;
2970 if (!kvm_pause_in_guest(vcpu
->kvm
))
2971 grow_ple_window(vcpu
);
2973 kvm_vcpu_on_spin(vcpu
, in_kernel
);
2977 static int nop_interception(struct vcpu_svm
*svm
)
2979 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
2982 static int monitor_interception(struct vcpu_svm
*svm
)
2984 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
2985 return nop_interception(svm
);
2988 static int mwait_interception(struct vcpu_svm
*svm
)
2990 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
2991 return nop_interception(svm
);
2994 static int invpcid_interception(struct vcpu_svm
*svm
)
2996 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3000 if (!guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
)) {
3001 kvm_queue_exception(vcpu
, UD_VECTOR
);
3006 * For an INVPCID intercept:
3007 * EXITINFO1 provides the linear address of the memory operand.
3008 * EXITINFO2 provides the contents of the register operand.
3010 type
= svm
->vmcb
->control
.exit_info_2
;
3011 gva
= svm
->vmcb
->control
.exit_info_1
;
3014 kvm_inject_gp(vcpu
, 0);
3018 return kvm_handle_invpcid(vcpu
, type
, gva
);
3021 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3022 [SVM_EXIT_READ_CR0
] = cr_interception
,
3023 [SVM_EXIT_READ_CR3
] = cr_interception
,
3024 [SVM_EXIT_READ_CR4
] = cr_interception
,
3025 [SVM_EXIT_READ_CR8
] = cr_interception
,
3026 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
3027 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3028 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3029 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3030 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3031 [SVM_EXIT_READ_DR0
] = dr_interception
,
3032 [SVM_EXIT_READ_DR1
] = dr_interception
,
3033 [SVM_EXIT_READ_DR2
] = dr_interception
,
3034 [SVM_EXIT_READ_DR3
] = dr_interception
,
3035 [SVM_EXIT_READ_DR4
] = dr_interception
,
3036 [SVM_EXIT_READ_DR5
] = dr_interception
,
3037 [SVM_EXIT_READ_DR6
] = dr_interception
,
3038 [SVM_EXIT_READ_DR7
] = dr_interception
,
3039 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3040 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3041 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3042 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3043 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3044 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3045 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3046 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3047 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3048 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3049 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3050 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3051 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3052 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
3053 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
3054 [SVM_EXIT_INTR
] = intr_interception
,
3055 [SVM_EXIT_NMI
] = nmi_interception
,
3056 [SVM_EXIT_SMI
] = nop_on_interception
,
3057 [SVM_EXIT_INIT
] = nop_on_interception
,
3058 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3059 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3060 [SVM_EXIT_CPUID
] = cpuid_interception
,
3061 [SVM_EXIT_IRET
] = iret_interception
,
3062 [SVM_EXIT_INVD
] = invd_interception
,
3063 [SVM_EXIT_PAUSE
] = pause_interception
,
3064 [SVM_EXIT_HLT
] = halt_interception
,
3065 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3066 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3067 [SVM_EXIT_IOIO
] = io_interception
,
3068 [SVM_EXIT_MSR
] = msr_interception
,
3069 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3070 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3071 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3072 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3073 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3074 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3075 [SVM_EXIT_STGI
] = stgi_interception
,
3076 [SVM_EXIT_CLGI
] = clgi_interception
,
3077 [SVM_EXIT_SKINIT
] = skinit_interception
,
3078 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
3079 [SVM_EXIT_MONITOR
] = monitor_interception
,
3080 [SVM_EXIT_MWAIT
] = mwait_interception
,
3081 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3082 [SVM_EXIT_RDPRU
] = rdpru_interception
,
3083 [SVM_EXIT_EFER_WRITE_TRAP
] = efer_trap
,
3084 [SVM_EXIT_CR0_WRITE_TRAP
] = cr_trap
,
3085 [SVM_EXIT_CR4_WRITE_TRAP
] = cr_trap
,
3086 [SVM_EXIT_CR8_WRITE_TRAP
] = cr_trap
,
3087 [SVM_EXIT_INVPCID
] = invpcid_interception
,
3088 [SVM_EXIT_NPF
] = npf_interception
,
3089 [SVM_EXIT_RSM
] = rsm_interception
,
3090 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
3091 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
3092 [SVM_EXIT_VMGEXIT
] = sev_handle_vmgexit
,
3095 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3097 struct vcpu_svm
*svm
= to_svm(vcpu
);
3098 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3099 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3101 if (!dump_invalid_vmcb
) {
3102 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3106 pr_err("VMCB Control Area:\n");
3107 pr_err("%-20s%04x\n", "cr_read:", control
->intercepts
[INTERCEPT_CR
] & 0xffff);
3108 pr_err("%-20s%04x\n", "cr_write:", control
->intercepts
[INTERCEPT_CR
] >> 16);
3109 pr_err("%-20s%04x\n", "dr_read:", control
->intercepts
[INTERCEPT_DR
] & 0xffff);
3110 pr_err("%-20s%04x\n", "dr_write:", control
->intercepts
[INTERCEPT_DR
] >> 16);
3111 pr_err("%-20s%08x\n", "exceptions:", control
->intercepts
[INTERCEPT_EXCEPTION
]);
3112 pr_err("%-20s%08x %08x\n", "intercepts:",
3113 control
->intercepts
[INTERCEPT_WORD3
],
3114 control
->intercepts
[INTERCEPT_WORD4
]);
3115 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3116 pr_err("%-20s%d\n", "pause filter threshold:",
3117 control
->pause_filter_thresh
);
3118 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3119 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3120 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3121 pr_err("%-20s%d\n", "asid:", control
->asid
);
3122 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3123 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3124 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3125 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3126 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3127 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3128 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3129 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3130 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3131 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3132 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3133 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
3134 pr_err("%-20s%016llx\n", "ghcb:", control
->ghcb_gpa
);
3135 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3136 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3137 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
3138 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3139 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
3140 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
3141 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
3142 pr_err("%-20s%016llx\n", "vmsa_pa:", control
->vmsa_pa
);
3143 pr_err("VMCB State Save Area:\n");
3144 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3146 save
->es
.selector
, save
->es
.attrib
,
3147 save
->es
.limit
, save
->es
.base
);
3148 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3150 save
->cs
.selector
, save
->cs
.attrib
,
3151 save
->cs
.limit
, save
->cs
.base
);
3152 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3154 save
->ss
.selector
, save
->ss
.attrib
,
3155 save
->ss
.limit
, save
->ss
.base
);
3156 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3158 save
->ds
.selector
, save
->ds
.attrib
,
3159 save
->ds
.limit
, save
->ds
.base
);
3160 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3162 save
->fs
.selector
, save
->fs
.attrib
,
3163 save
->fs
.limit
, save
->fs
.base
);
3164 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3166 save
->gs
.selector
, save
->gs
.attrib
,
3167 save
->gs
.limit
, save
->gs
.base
);
3168 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3170 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3171 save
->gdtr
.limit
, save
->gdtr
.base
);
3172 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3174 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3175 save
->ldtr
.limit
, save
->ldtr
.base
);
3176 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3178 save
->idtr
.selector
, save
->idtr
.attrib
,
3179 save
->idtr
.limit
, save
->idtr
.base
);
3180 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3182 save
->tr
.selector
, save
->tr
.attrib
,
3183 save
->tr
.limit
, save
->tr
.base
);
3184 pr_err("cpl: %d efer: %016llx\n",
3185 save
->cpl
, save
->efer
);
3186 pr_err("%-15s %016llx %-13s %016llx\n",
3187 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3188 pr_err("%-15s %016llx %-13s %016llx\n",
3189 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3190 pr_err("%-15s %016llx %-13s %016llx\n",
3191 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3192 pr_err("%-15s %016llx %-13s %016llx\n",
3193 "rip:", save
->rip
, "rflags:", save
->rflags
);
3194 pr_err("%-15s %016llx %-13s %016llx\n",
3195 "rsp:", save
->rsp
, "rax:", save
->rax
);
3196 pr_err("%-15s %016llx %-13s %016llx\n",
3197 "star:", save
->star
, "lstar:", save
->lstar
);
3198 pr_err("%-15s %016llx %-13s %016llx\n",
3199 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3200 pr_err("%-15s %016llx %-13s %016llx\n",
3201 "kernel_gs_base:", save
->kernel_gs_base
,
3202 "sysenter_cs:", save
->sysenter_cs
);
3203 pr_err("%-15s %016llx %-13s %016llx\n",
3204 "sysenter_esp:", save
->sysenter_esp
,
3205 "sysenter_eip:", save
->sysenter_eip
);
3206 pr_err("%-15s %016llx %-13s %016llx\n",
3207 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3208 pr_err("%-15s %016llx %-13s %016llx\n",
3209 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3210 pr_err("%-15s %016llx %-13s %016llx\n",
3211 "excp_from:", save
->last_excp_from
,
3212 "excp_to:", save
->last_excp_to
);
3215 static int svm_handle_invalid_exit(struct kvm_vcpu
*vcpu
, u64 exit_code
)
3217 if (exit_code
< ARRAY_SIZE(svm_exit_handlers
) &&
3218 svm_exit_handlers
[exit_code
])
3221 vcpu_unimpl(vcpu
, "svm: unexpected exit reason 0x%llx\n", exit_code
);
3223 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3224 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON
;
3225 vcpu
->run
->internal
.ndata
= 2;
3226 vcpu
->run
->internal
.data
[0] = exit_code
;
3227 vcpu
->run
->internal
.data
[1] = vcpu
->arch
.last_vmentry_cpu
;
3232 int svm_invoke_exit_handler(struct vcpu_svm
*svm
, u64 exit_code
)
3234 if (svm_handle_invalid_exit(&svm
->vcpu
, exit_code
))
3237 #ifdef CONFIG_RETPOLINE
3238 if (exit_code
== SVM_EXIT_MSR
)
3239 return msr_interception(svm
);
3240 else if (exit_code
== SVM_EXIT_VINTR
)
3241 return interrupt_window_interception(svm
);
3242 else if (exit_code
== SVM_EXIT_INTR
)
3243 return intr_interception(svm
);
3244 else if (exit_code
== SVM_EXIT_HLT
)
3245 return halt_interception(svm
);
3246 else if (exit_code
== SVM_EXIT_NPF
)
3247 return npf_interception(svm
);
3249 return svm_exit_handlers
[exit_code
](svm
);
3252 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
,
3253 u32
*intr_info
, u32
*error_code
)
3255 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3257 *info1
= control
->exit_info_1
;
3258 *info2
= control
->exit_info_2
;
3259 *intr_info
= control
->exit_int_info
;
3260 if ((*intr_info
& SVM_EXITINTINFO_VALID
) &&
3261 (*intr_info
& SVM_EXITINTINFO_VALID_ERR
))
3262 *error_code
= control
->exit_int_info_err
;
3267 static int handle_exit(struct kvm_vcpu
*vcpu
, fastpath_t exit_fastpath
)
3269 struct vcpu_svm
*svm
= to_svm(vcpu
);
3270 struct kvm_run
*kvm_run
= vcpu
->run
;
3271 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3273 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3275 /* SEV-ES guests must use the CR write traps to track CR registers. */
3276 if (!sev_es_guest(vcpu
->kvm
)) {
3277 if (!svm_is_intercept(svm
, INTERCEPT_CR0_WRITE
))
3278 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3280 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3283 if (is_guest_mode(vcpu
)) {
3286 trace_kvm_nested_vmexit(exit_code
, vcpu
, KVM_ISA_SVM
);
3288 vmexit
= nested_svm_exit_special(svm
);
3290 if (vmexit
== NESTED_EXIT_CONTINUE
)
3291 vmexit
= nested_svm_exit_handled(svm
);
3293 if (vmexit
== NESTED_EXIT_DONE
)
3297 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3298 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3299 kvm_run
->fail_entry
.hardware_entry_failure_reason
3300 = svm
->vmcb
->control
.exit_code
;
3301 kvm_run
->fail_entry
.cpu
= vcpu
->arch
.last_vmentry_cpu
;
3306 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3307 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3308 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3309 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3310 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
3312 __func__
, svm
->vmcb
->control
.exit_int_info
,
3315 if (exit_fastpath
!= EXIT_FASTPATH_NONE
)
3318 return svm_invoke_exit_handler(svm
, exit_code
);
3321 static void reload_tss(struct kvm_vcpu
*vcpu
)
3323 struct svm_cpu_data
*sd
= per_cpu(svm_data
, vcpu
->cpu
);
3325 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3329 static void pre_svm_run(struct vcpu_svm
*svm
)
3331 struct svm_cpu_data
*sd
= per_cpu(svm_data
, svm
->vcpu
.cpu
);
3333 if (sev_guest(svm
->vcpu
.kvm
))
3334 return pre_sev_run(svm
, svm
->vcpu
.cpu
);
3336 /* FIXME: handle wraparound of asid_generation */
3337 if (svm
->asid_generation
!= sd
->asid_generation
)
3341 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3343 struct vcpu_svm
*svm
= to_svm(vcpu
);
3345 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3346 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3347 if (!sev_es_guest(svm
->vcpu
.kvm
))
3348 svm_set_intercept(svm
, INTERCEPT_IRET
);
3349 ++vcpu
->stat
.nmi_injections
;
3352 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3354 struct vcpu_svm
*svm
= to_svm(vcpu
);
3356 BUG_ON(!(gif_set(svm
)));
3358 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3359 ++vcpu
->stat
.irq_injections
;
3361 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3362 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3365 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3367 struct vcpu_svm
*svm
= to_svm(vcpu
);
3370 * SEV-ES guests must always keep the CR intercepts cleared. CR
3371 * tracking is done using the CR write traps.
3373 if (sev_es_guest(vcpu
->kvm
))
3376 if (nested_svm_virtualize_tpr(vcpu
))
3379 svm_clr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3385 svm_set_intercept(svm
, INTERCEPT_CR8_WRITE
);
3388 bool svm_nmi_blocked(struct kvm_vcpu
*vcpu
)
3390 struct vcpu_svm
*svm
= to_svm(vcpu
);
3391 struct vmcb
*vmcb
= svm
->vmcb
;
3397 if (is_guest_mode(vcpu
) && nested_exit_on_nmi(svm
))
3400 ret
= (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) ||
3401 (svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3406 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
3408 struct vcpu_svm
*svm
= to_svm(vcpu
);
3409 if (svm
->nested
.nested_run_pending
)
3412 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3413 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_nmi(svm
))
3416 return !svm_nmi_blocked(vcpu
);
3419 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3421 struct vcpu_svm
*svm
= to_svm(vcpu
);
3423 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3426 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3428 struct vcpu_svm
*svm
= to_svm(vcpu
);
3431 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3432 if (!sev_es_guest(svm
->vcpu
.kvm
))
3433 svm_set_intercept(svm
, INTERCEPT_IRET
);
3435 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3436 if (!sev_es_guest(svm
->vcpu
.kvm
))
3437 svm_clr_intercept(svm
, INTERCEPT_IRET
);
3441 bool svm_interrupt_blocked(struct kvm_vcpu
*vcpu
)
3443 struct vcpu_svm
*svm
= to_svm(vcpu
);
3444 struct vmcb
*vmcb
= svm
->vmcb
;
3449 if (sev_es_guest(svm
->vcpu
.kvm
)) {
3451 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3452 * bit to determine the state of the IF flag.
3454 if (!(vmcb
->control
.int_state
& SVM_GUEST_INTERRUPT_MASK
))
3456 } else if (is_guest_mode(vcpu
)) {
3457 /* As long as interrupts are being delivered... */
3458 if ((svm
->nested
.ctl
.int_ctl
& V_INTR_MASKING_MASK
)
3459 ? !(svm
->nested
.hsave
->save
.rflags
& X86_EFLAGS_IF
)
3460 : !(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
))
3463 /* ... vmexits aren't blocked by the interrupt shadow */
3464 if (nested_exit_on_intr(svm
))
3467 if (!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
))
3471 return (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
);
3474 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
3476 struct vcpu_svm
*svm
= to_svm(vcpu
);
3477 if (svm
->nested
.nested_run_pending
)
3481 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3482 * e.g. if the IRQ arrived asynchronously after checking nested events.
3484 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_intr(svm
))
3487 return !svm_interrupt_blocked(vcpu
);
3490 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3492 struct vcpu_svm
*svm
= to_svm(vcpu
);
3495 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3496 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3497 * get that intercept, this function will be called again though and
3498 * we'll get the vintr intercept. However, if the vGIF feature is
3499 * enabled, the STGI interception will not occur. Enable the irq
3500 * window under the assumption that the hardware will set the GIF.
3502 if (vgif_enabled(svm
) || gif_set(svm
)) {
3504 * IRQ window is not needed when AVIC is enabled,
3505 * unless we have pending ExtINT since it cannot be injected
3506 * via AVIC. In such case, we need to temporarily disable AVIC,
3507 * and fallback to injecting IRQ via V_IRQ.
3509 svm_toggle_avic_for_irq_window(vcpu
, false);
3514 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3516 struct vcpu_svm
*svm
= to_svm(vcpu
);
3518 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3520 return; /* IRET will cause a vm exit */
3522 if (!gif_set(svm
)) {
3523 if (vgif_enabled(svm
))
3524 svm_set_intercept(svm
, INTERCEPT_STGI
);
3525 return; /* STGI will cause a vm exit */
3529 * Something prevents NMI from been injected. Single step over possible
3530 * problem (IRET or exception injection or interrupt shadow)
3532 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
3533 svm
->nmi_singlestep
= true;
3534 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3537 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3542 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
3547 void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3549 struct vcpu_svm
*svm
= to_svm(vcpu
);
3552 * Flush only the current ASID even if the TLB flush was invoked via
3553 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3554 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3555 * unconditionally does a TLB flush on both nested VM-Enter and nested
3556 * VM-Exit (via kvm_mmu_reset_context()).
3558 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3559 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3561 svm
->asid_generation
--;
3564 static void svm_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t gva
)
3566 struct vcpu_svm
*svm
= to_svm(vcpu
);
3568 invlpga(gva
, svm
->vmcb
->control
.asid
);
3571 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3575 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3577 struct vcpu_svm
*svm
= to_svm(vcpu
);
3579 if (nested_svm_virtualize_tpr(vcpu
))
3582 if (!svm_is_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3583 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3584 kvm_set_cr8(vcpu
, cr8
);
3588 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3590 struct vcpu_svm
*svm
= to_svm(vcpu
);
3593 if (nested_svm_virtualize_tpr(vcpu
) ||
3594 kvm_vcpu_apicv_active(vcpu
))
3597 cr8
= kvm_get_cr8(vcpu
);
3598 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3599 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3602 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3606 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3607 unsigned int3_injected
= svm
->int3_injected
;
3609 svm
->int3_injected
= 0;
3612 * If we've made progress since setting HF_IRET_MASK, we've
3613 * executed an IRET and can allow NMI injection.
3615 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) &&
3616 (sev_es_guest(svm
->vcpu
.kvm
) ||
3617 kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
)) {
3618 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3619 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3622 svm
->vcpu
.arch
.nmi_injected
= false;
3623 kvm_clear_exception_queue(&svm
->vcpu
);
3624 kvm_clear_interrupt_queue(&svm
->vcpu
);
3626 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3629 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3631 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3632 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3635 case SVM_EXITINTINFO_TYPE_NMI
:
3636 svm
->vcpu
.arch
.nmi_injected
= true;
3638 case SVM_EXITINTINFO_TYPE_EXEPT
:
3640 * Never re-inject a #VC exception.
3642 if (vector
== X86_TRAP_VC
)
3646 * In case of software exceptions, do not reinject the vector,
3647 * but re-execute the instruction instead. Rewind RIP first
3648 * if we emulated INT3 before.
3650 if (kvm_exception_is_soft(vector
)) {
3651 if (vector
== BP_VECTOR
&& int3_injected
&&
3652 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3653 kvm_rip_write(&svm
->vcpu
,
3654 kvm_rip_read(&svm
->vcpu
) -
3658 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3659 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3660 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3663 kvm_requeue_exception(&svm
->vcpu
, vector
);
3665 case SVM_EXITINTINFO_TYPE_INTR
:
3666 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3673 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3675 struct vcpu_svm
*svm
= to_svm(vcpu
);
3676 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3678 control
->exit_int_info
= control
->event_inj
;
3679 control
->exit_int_info_err
= control
->event_inj_err
;
3680 control
->event_inj
= 0;
3681 svm_complete_interrupts(svm
);
3684 static fastpath_t
svm_exit_handlers_fastpath(struct kvm_vcpu
*vcpu
)
3686 if (to_svm(vcpu
)->vmcb
->control
.exit_code
== SVM_EXIT_MSR
&&
3687 to_svm(vcpu
)->vmcb
->control
.exit_info_1
)
3688 return handle_fastpath_set_msr_irqoff(vcpu
);
3690 return EXIT_FASTPATH_NONE
;
3693 static noinstr
void svm_vcpu_enter_exit(struct kvm_vcpu
*vcpu
,
3694 struct vcpu_svm
*svm
)
3697 * VMENTER enables interrupts (host state), but the kernel state is
3698 * interrupts disabled when this is invoked. Also tell RCU about
3699 * it. This is the same logic as for exit_to_user_mode().
3701 * This ensures that e.g. latency analysis on the host observes
3702 * guest mode as interrupt enabled.
3704 * guest_enter_irqoff() informs context tracking about the
3705 * transition to guest mode and if enabled adjusts RCU state
3708 instrumentation_begin();
3709 trace_hardirqs_on_prepare();
3710 lockdep_hardirqs_on_prepare(CALLER_ADDR0
);
3711 instrumentation_end();
3713 guest_enter_irqoff();
3714 lockdep_hardirqs_on(CALLER_ADDR0
);
3716 if (sev_es_guest(svm
->vcpu
.kvm
)) {
3717 __svm_sev_es_vcpu_run(svm
->vmcb_pa
);
3719 __svm_vcpu_run(svm
->vmcb_pa
, (unsigned long *)&svm
->vcpu
.arch
.regs
);
3721 #ifdef CONFIG_X86_64
3722 native_wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3724 loadsegment(fs
, svm
->host
.fs
);
3725 #ifndef CONFIG_X86_32_LAZY_GS
3726 loadsegment(gs
, svm
->host
.gs
);
3732 * VMEXIT disables interrupts (host state), but tracing and lockdep
3733 * have them in state 'on' as recorded before entering guest mode.
3734 * Same as enter_from_user_mode().
3736 * guest_exit_irqoff() restores host context and reinstates RCU if
3737 * enabled and required.
3739 * This needs to be done before the below as native_read_msr()
3740 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3741 * into world and some more.
3743 lockdep_hardirqs_off(CALLER_ADDR0
);
3744 guest_exit_irqoff();
3746 instrumentation_begin();
3747 trace_hardirqs_off_finish();
3748 instrumentation_end();
3751 static __no_kcsan fastpath_t
svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3753 struct vcpu_svm
*svm
= to_svm(vcpu
);
3755 trace_kvm_entry(vcpu
);
3757 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3758 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3759 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3762 * Disable singlestep if we're injecting an interrupt/exception.
3763 * We don't want our modified rflags to be pushed on the stack where
3764 * we might not be able to easily reset them if we disabled NMI
3767 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
3769 * Event injection happens before external interrupts cause a
3770 * vmexit and interrupts are disabled here, so smp_send_reschedule
3771 * is enough to force an immediate vmexit.
3773 disable_nmi_singlestep(svm
);
3774 smp_send_reschedule(vcpu
->cpu
);
3779 sync_lapic_to_cr8(vcpu
);
3781 if (unlikely(svm
->asid
!= svm
->vmcb
->control
.asid
)) {
3782 svm
->vmcb
->control
.asid
= svm
->asid
;
3783 vmcb_mark_dirty(svm
->vmcb
, VMCB_ASID
);
3785 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3788 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3791 if (unlikely(svm
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
))
3792 svm_set_dr6(svm
, vcpu
->arch
.dr6
);
3794 svm_set_dr6(svm
, DR6_FIXED_1
| DR6_RTM
);
3797 kvm_load_guest_xsave_state(vcpu
);
3799 kvm_wait_lapic_expire(vcpu
);
3802 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3803 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3804 * is no need to worry about the conditional branch over the wrmsr
3805 * being speculatively taken.
3807 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
3809 svm_vcpu_enter_exit(vcpu
, svm
);
3812 * We do not use IBRS in the kernel. If this vCPU has used the
3813 * SPEC_CTRL MSR it may have left it on; save the value and
3814 * turn it off. This is much more efficient than blindly adding
3815 * it to the atomic save/restore list. Especially as the former
3816 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3818 * For non-nested case:
3819 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3823 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3826 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
3827 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
3829 if (!sev_es_guest(svm
->vcpu
.kvm
))
3832 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
3834 if (!sev_es_guest(svm
->vcpu
.kvm
)) {
3835 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3836 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3837 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3838 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3841 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3842 kvm_before_interrupt(&svm
->vcpu
);
3844 kvm_load_host_xsave_state(vcpu
);
3847 /* Any pending NMI will happen here */
3849 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3850 kvm_after_interrupt(&svm
->vcpu
);
3852 sync_cr8_to_lapic(vcpu
);
3855 if (is_guest_mode(&svm
->vcpu
)) {
3856 sync_nested_vmcb_control(svm
);
3857 svm
->nested
.nested_run_pending
= 0;
3860 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3861 vmcb_mark_all_clean(svm
->vmcb
);
3863 /* if exit due to PF check for async PF */
3864 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3865 svm
->vcpu
.arch
.apf
.host_apf_flags
=
3866 kvm_read_and_reset_apf_flags();
3869 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3870 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3874 * We need to handle MC intercepts here before the vcpu has a chance to
3875 * change the physical cpu
3877 if (unlikely(svm
->vmcb
->control
.exit_code
==
3878 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3879 svm_handle_mce(svm
);
3881 svm_complete_interrupts(svm
);
3883 if (is_guest_mode(vcpu
))
3884 return EXIT_FASTPATH_NONE
;
3886 return svm_exit_handlers_fastpath(vcpu
);
3889 static void svm_load_mmu_pgd(struct kvm_vcpu
*vcpu
, unsigned long root
,
3892 struct vcpu_svm
*svm
= to_svm(vcpu
);
3895 cr3
= __sme_set(root
);
3897 svm
->vmcb
->control
.nested_cr3
= cr3
;
3898 vmcb_mark_dirty(svm
->vmcb
, VMCB_NPT
);
3900 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3901 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3903 cr3
= vcpu
->arch
.cr3
;
3906 svm
->vmcb
->save
.cr3
= cr3
;
3907 vmcb_mark_dirty(svm
->vmcb
, VMCB_CR
);
3910 static int is_disabled(void)
3914 rdmsrl(MSR_VM_CR
, vm_cr
);
3915 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3922 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3925 * Patch in the VMMCALL instruction:
3927 hypercall
[0] = 0x0f;
3928 hypercall
[1] = 0x01;
3929 hypercall
[2] = 0xd9;
3932 static int __init
svm_check_processor_compat(void)
3937 static bool svm_cpu_has_accelerated_tpr(void)
3943 * The kvm parameter can be NULL (module initialization, or invocation before
3944 * VM creation). Be sure to check the kvm parameter before using it.
3946 static bool svm_has_emulated_msr(struct kvm
*kvm
, u32 index
)
3949 case MSR_IA32_MCG_EXT_CTL
:
3950 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3952 case MSR_IA32_SMBASE
:
3953 /* SEV-ES guests do not support SMM, so report false */
3954 if (kvm
&& sev_es_guest(kvm
))
3964 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3969 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu
*vcpu
)
3971 struct vcpu_svm
*svm
= to_svm(vcpu
);
3972 struct kvm_cpuid_entry2
*best
;
3974 vcpu
->arch
.xsaves_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
3975 boot_cpu_has(X86_FEATURE_XSAVE
) &&
3976 boot_cpu_has(X86_FEATURE_XSAVES
);
3978 /* Update nrips enabled cache */
3979 svm
->nrips_enabled
= kvm_cpu_cap_has(X86_FEATURE_NRIPS
) &&
3980 guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
3982 /* Check again if INVPCID interception if required */
3983 svm_check_invpcid(svm
);
3985 /* For sev guests, the memory encryption bit is not reserved in CR3. */
3986 if (sev_guest(vcpu
->kvm
)) {
3987 best
= kvm_find_cpuid_entry(vcpu
, 0x8000001F, 0);
3989 vcpu
->arch
.cr3_lm_rsvd_bits
&= ~(1UL << (best
->ebx
& 0x3f));
3992 if (!kvm_vcpu_apicv_active(vcpu
))
3996 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3997 * is exposed to the guest, disable AVIC.
3999 if (guest_cpuid_has(vcpu
, X86_FEATURE_X2APIC
))
4000 kvm_request_apicv_update(vcpu
->kvm
, false,
4001 APICV_INHIBIT_REASON_X2APIC
);
4004 * Currently, AVIC does not work with nested virtualization.
4005 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4007 if (nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_SVM
))
4008 kvm_request_apicv_update(vcpu
->kvm
, false,
4009 APICV_INHIBIT_REASON_NESTED
);
4012 static bool svm_has_wbinvd_exit(void)
4017 #define PRE_EX(exit) { .exit_code = (exit), \
4018 .stage = X86_ICPT_PRE_EXCEPT, }
4019 #define POST_EX(exit) { .exit_code = (exit), \
4020 .stage = X86_ICPT_POST_EXCEPT, }
4021 #define POST_MEM(exit) { .exit_code = (exit), \
4022 .stage = X86_ICPT_POST_MEMACCESS, }
4024 static const struct __x86_intercept
{
4026 enum x86_intercept_stage stage
;
4027 } x86_intercept_map
[] = {
4028 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4029 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4030 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4031 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4032 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4033 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4034 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4035 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4036 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4037 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4038 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4039 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4040 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4041 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4042 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4043 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4044 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4045 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4046 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4047 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4048 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4049 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4050 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4051 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4052 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4053 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4054 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4055 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4056 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4057 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4058 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4059 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4060 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4061 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4062 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4063 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4064 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4065 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4066 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4067 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4068 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4069 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4070 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4071 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4072 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4073 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4074 [x86_intercept_xsetbv
] = PRE_EX(SVM_EXIT_XSETBV
),
4081 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4082 struct x86_instruction_info
*info
,
4083 enum x86_intercept_stage stage
,
4084 struct x86_exception
*exception
)
4086 struct vcpu_svm
*svm
= to_svm(vcpu
);
4087 int vmexit
, ret
= X86EMUL_CONTINUE
;
4088 struct __x86_intercept icpt_info
;
4089 struct vmcb
*vmcb
= svm
->vmcb
;
4091 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4094 icpt_info
= x86_intercept_map
[info
->intercept
];
4096 if (stage
!= icpt_info
.stage
)
4099 switch (icpt_info
.exit_code
) {
4100 case SVM_EXIT_READ_CR0
:
4101 if (info
->intercept
== x86_intercept_cr_read
)
4102 icpt_info
.exit_code
+= info
->modrm_reg
;
4104 case SVM_EXIT_WRITE_CR0
: {
4105 unsigned long cr0
, val
;
4107 if (info
->intercept
== x86_intercept_cr_write
)
4108 icpt_info
.exit_code
+= info
->modrm_reg
;
4110 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
4111 info
->intercept
== x86_intercept_clts
)
4114 if (!(vmcb_is_intercept(&svm
->nested
.ctl
,
4115 INTERCEPT_SELECTIVE_CR0
)))
4118 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4119 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4121 if (info
->intercept
== x86_intercept_lmsw
) {
4124 /* lmsw can't clear PE - catch this here */
4125 if (cr0
& X86_CR0_PE
)
4130 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4134 case SVM_EXIT_READ_DR0
:
4135 case SVM_EXIT_WRITE_DR0
:
4136 icpt_info
.exit_code
+= info
->modrm_reg
;
4139 if (info
->intercept
== x86_intercept_wrmsr
)
4140 vmcb
->control
.exit_info_1
= 1;
4142 vmcb
->control
.exit_info_1
= 0;
4144 case SVM_EXIT_PAUSE
:
4146 * We get this for NOP only, but pause
4147 * is rep not, check this here
4149 if (info
->rep_prefix
!= REPE_PREFIX
)
4152 case SVM_EXIT_IOIO
: {
4156 if (info
->intercept
== x86_intercept_in
||
4157 info
->intercept
== x86_intercept_ins
) {
4158 exit_info
= ((info
->src_val
& 0xffff) << 16) |
4160 bytes
= info
->dst_bytes
;
4162 exit_info
= (info
->dst_val
& 0xffff) << 16;
4163 bytes
= info
->src_bytes
;
4166 if (info
->intercept
== x86_intercept_outs
||
4167 info
->intercept
== x86_intercept_ins
)
4168 exit_info
|= SVM_IOIO_STR_MASK
;
4170 if (info
->rep_prefix
)
4171 exit_info
|= SVM_IOIO_REP_MASK
;
4173 bytes
= min(bytes
, 4u);
4175 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4177 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4179 vmcb
->control
.exit_info_1
= exit_info
;
4180 vmcb
->control
.exit_info_2
= info
->next_rip
;
4188 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4189 if (static_cpu_has(X86_FEATURE_NRIPS
))
4190 vmcb
->control
.next_rip
= info
->next_rip
;
4191 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4192 vmexit
= nested_svm_exit_handled(svm
);
4194 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4201 static void svm_handle_exit_irqoff(struct kvm_vcpu
*vcpu
)
4205 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
4207 if (!kvm_pause_in_guest(vcpu
->kvm
))
4208 shrink_ple_window(vcpu
);
4211 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
4213 /* [63:9] are reserved. */
4214 vcpu
->arch
.mcg_cap
&= 0x1ff;
4217 bool svm_smi_blocked(struct kvm_vcpu
*vcpu
)
4219 struct vcpu_svm
*svm
= to_svm(vcpu
);
4221 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4225 return is_smm(vcpu
);
4228 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
4230 struct vcpu_svm
*svm
= to_svm(vcpu
);
4231 if (svm
->nested
.nested_run_pending
)
4234 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4235 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_smi(svm
))
4238 return !svm_smi_blocked(vcpu
);
4241 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
4243 struct vcpu_svm
*svm
= to_svm(vcpu
);
4246 if (is_guest_mode(vcpu
)) {
4247 /* FED8h - SVM Guest */
4248 put_smstate(u64
, smstate
, 0x7ed8, 1);
4249 /* FEE0h - SVM Guest VMCB Physical Address */
4250 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb12_gpa
);
4252 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
4253 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
4254 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
4256 ret
= nested_svm_vmexit(svm
);
4263 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, const char *smstate
)
4265 struct vcpu_svm
*svm
= to_svm(vcpu
);
4266 struct kvm_host_map map
;
4269 if (guest_cpuid_has(vcpu
, X86_FEATURE_LM
)) {
4270 u64 saved_efer
= GET_SMSTATE(u64
, smstate
, 0x7ed0);
4271 u64 guest
= GET_SMSTATE(u64
, smstate
, 0x7ed8);
4272 u64 vmcb12_gpa
= GET_SMSTATE(u64
, smstate
, 0x7ee0);
4275 if (!guest_cpuid_has(vcpu
, X86_FEATURE_SVM
))
4278 if (!(saved_efer
& EFER_SVME
))
4281 if (kvm_vcpu_map(&svm
->vcpu
,
4282 gpa_to_gfn(vmcb12_gpa
), &map
) == -EINVAL
)
4285 if (svm_allocate_nested(svm
))
4288 ret
= enter_svm_guest_mode(svm
, vmcb12_gpa
, map
.hva
);
4289 kvm_vcpu_unmap(&svm
->vcpu
, &map
, true);
4296 static void enable_smi_window(struct kvm_vcpu
*vcpu
)
4298 struct vcpu_svm
*svm
= to_svm(vcpu
);
4300 if (!gif_set(svm
)) {
4301 if (vgif_enabled(svm
))
4302 svm_set_intercept(svm
, INTERCEPT_STGI
);
4303 /* STGI will cause a vm exit */
4305 /* We must be in SMM; RSM will cause a vmexit anyway. */
4309 static bool svm_can_emulate_instruction(struct kvm_vcpu
*vcpu
, void *insn
, int insn_len
)
4311 bool smep
, smap
, is_user
;
4315 * When the guest is an SEV-ES guest, emulation is not possible.
4317 if (sev_es_guest(vcpu
->kvm
))
4321 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4324 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4325 * possible that CPU microcode implementing DecodeAssist will fail
4326 * to read bytes of instruction which caused #NPF. In this case,
4327 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4328 * return 0 instead of the correct guest instruction bytes.
4330 * This happens because CPU microcode reading instruction bytes
4331 * uses a special opcode which attempts to read data using CPL=0
4332 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4333 * fault, it gives up and returns no instruction bytes.
4336 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4337 * returned 0 in GuestIntrBytes field of the VMCB.
4338 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4339 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4340 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4341 * a SMEP fault instead of #NPF).
4342 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4343 * As most guests enable SMAP if they have also enabled SMEP, use above
4344 * logic in order to attempt minimize false-positive of detecting errata
4345 * while still preserving all cases semantic correctness.
4348 * To determine what instruction the guest was executing, the hypervisor
4349 * will have to decode the instruction at the instruction pointer.
4351 * In non SEV guest, hypervisor will be able to read the guest
4352 * memory to decode the instruction pointer when insn_len is zero
4353 * so we return true to indicate that decoding is possible.
4355 * But in the SEV guest, the guest memory is encrypted with the
4356 * guest specific key and hypervisor will not be able to decode the
4357 * instruction pointer so we will not able to workaround it. Lets
4358 * print the error and request to kill the guest.
4360 if (likely(!insn
|| insn_len
))
4364 * If RIP is invalid, go ahead with emulation which will cause an
4365 * internal error exit.
4367 if (!kvm_vcpu_gfn_to_memslot(vcpu
, kvm_rip_read(vcpu
) >> PAGE_SHIFT
))
4370 cr4
= kvm_read_cr4(vcpu
);
4371 smep
= cr4
& X86_CR4_SMEP
;
4372 smap
= cr4
& X86_CR4_SMAP
;
4373 is_user
= svm_get_cpl(vcpu
) == 3;
4374 if (smap
&& (!smep
|| is_user
)) {
4375 if (!sev_guest(vcpu
->kvm
))
4378 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4379 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4385 static bool svm_apic_init_signal_blocked(struct kvm_vcpu
*vcpu
)
4387 struct vcpu_svm
*svm
= to_svm(vcpu
);
4390 * TODO: Last condition latch INIT signals on vCPU when
4391 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4392 * To properly emulate the INIT intercept,
4393 * svm_check_nested_events() should call nested_svm_vmexit()
4394 * if an INIT signal is pending.
4396 return !gif_set(svm
) ||
4397 (vmcb_is_intercept(&svm
->vmcb
->control
, INTERCEPT_INIT
));
4400 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu
*vcpu
, u8 vector
)
4402 if (!sev_es_guest(vcpu
->kvm
))
4403 return kvm_vcpu_deliver_sipi_vector(vcpu
, vector
);
4405 sev_vcpu_deliver_sipi_vector(vcpu
, vector
);
4408 static void svm_vm_destroy(struct kvm
*kvm
)
4410 avic_vm_destroy(kvm
);
4411 sev_vm_destroy(kvm
);
4414 static int svm_vm_init(struct kvm
*kvm
)
4416 if (!pause_filter_count
|| !pause_filter_thresh
)
4417 kvm
->arch
.pause_in_guest
= true;
4420 int ret
= avic_vm_init(kvm
);
4425 kvm_apicv_init(kvm
, avic
);
4429 static struct kvm_x86_ops svm_x86_ops __initdata
= {
4430 .hardware_unsetup
= svm_hardware_teardown
,
4431 .hardware_enable
= svm_hardware_enable
,
4432 .hardware_disable
= svm_hardware_disable
,
4433 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4434 .has_emulated_msr
= svm_has_emulated_msr
,
4436 .vcpu_create
= svm_create_vcpu
,
4437 .vcpu_free
= svm_free_vcpu
,
4438 .vcpu_reset
= svm_vcpu_reset
,
4440 .vm_size
= sizeof(struct kvm_svm
),
4441 .vm_init
= svm_vm_init
,
4442 .vm_destroy
= svm_vm_destroy
,
4444 .prepare_guest_switch
= svm_prepare_guest_switch
,
4445 .vcpu_load
= svm_vcpu_load
,
4446 .vcpu_put
= svm_vcpu_put
,
4447 .vcpu_blocking
= svm_vcpu_blocking
,
4448 .vcpu_unblocking
= svm_vcpu_unblocking
,
4450 .update_exception_bitmap
= update_exception_bitmap
,
4451 .get_msr_feature
= svm_get_msr_feature
,
4452 .get_msr
= svm_get_msr
,
4453 .set_msr
= svm_set_msr
,
4454 .get_segment_base
= svm_get_segment_base
,
4455 .get_segment
= svm_get_segment
,
4456 .set_segment
= svm_set_segment
,
4457 .get_cpl
= svm_get_cpl
,
4458 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4459 .set_cr0
= svm_set_cr0
,
4460 .is_valid_cr4
= svm_is_valid_cr4
,
4461 .set_cr4
= svm_set_cr4
,
4462 .set_efer
= svm_set_efer
,
4463 .get_idt
= svm_get_idt
,
4464 .set_idt
= svm_set_idt
,
4465 .get_gdt
= svm_get_gdt
,
4466 .set_gdt
= svm_set_gdt
,
4467 .set_dr7
= svm_set_dr7
,
4468 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
4469 .cache_reg
= svm_cache_reg
,
4470 .get_rflags
= svm_get_rflags
,
4471 .set_rflags
= svm_set_rflags
,
4473 .tlb_flush_all
= svm_flush_tlb
,
4474 .tlb_flush_current
= svm_flush_tlb
,
4475 .tlb_flush_gva
= svm_flush_tlb_gva
,
4476 .tlb_flush_guest
= svm_flush_tlb
,
4478 .run
= svm_vcpu_run
,
4479 .handle_exit
= handle_exit
,
4480 .skip_emulated_instruction
= skip_emulated_instruction
,
4481 .update_emulated_instruction
= NULL
,
4482 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4483 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4484 .patch_hypercall
= svm_patch_hypercall
,
4485 .set_irq
= svm_set_irq
,
4486 .set_nmi
= svm_inject_nmi
,
4487 .queue_exception
= svm_queue_exception
,
4488 .cancel_injection
= svm_cancel_injection
,
4489 .interrupt_allowed
= svm_interrupt_allowed
,
4490 .nmi_allowed
= svm_nmi_allowed
,
4491 .get_nmi_mask
= svm_get_nmi_mask
,
4492 .set_nmi_mask
= svm_set_nmi_mask
,
4493 .enable_nmi_window
= enable_nmi_window
,
4494 .enable_irq_window
= enable_irq_window
,
4495 .update_cr8_intercept
= update_cr8_intercept
,
4496 .set_virtual_apic_mode
= svm_set_virtual_apic_mode
,
4497 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
4498 .check_apicv_inhibit_reasons
= svm_check_apicv_inhibit_reasons
,
4499 .pre_update_apicv_exec_ctrl
= svm_pre_update_apicv_exec_ctrl
,
4500 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
4501 .hwapic_irr_update
= svm_hwapic_irr_update
,
4502 .hwapic_isr_update
= svm_hwapic_isr_update
,
4503 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
4504 .apicv_post_state_restore
= avic_post_state_restore
,
4506 .set_tss_addr
= svm_set_tss_addr
,
4507 .set_identity_map_addr
= svm_set_identity_map_addr
,
4508 .get_mt_mask
= svm_get_mt_mask
,
4510 .get_exit_info
= svm_get_exit_info
,
4512 .vcpu_after_set_cpuid
= svm_vcpu_after_set_cpuid
,
4514 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4516 .write_l1_tsc_offset
= svm_write_l1_tsc_offset
,
4518 .load_mmu_pgd
= svm_load_mmu_pgd
,
4520 .check_intercept
= svm_check_intercept
,
4521 .handle_exit_irqoff
= svm_handle_exit_irqoff
,
4523 .request_immediate_exit
= __kvm_request_immediate_exit
,
4525 .sched_in
= svm_sched_in
,
4527 .pmu_ops
= &amd_pmu_ops
,
4528 .nested_ops
= &svm_nested_ops
,
4530 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
4531 .dy_apicv_has_pending_interrupt
= svm_dy_apicv_has_pending_interrupt
,
4532 .update_pi_irte
= svm_update_pi_irte
,
4533 .setup_mce
= svm_setup_mce
,
4535 .smi_allowed
= svm_smi_allowed
,
4536 .pre_enter_smm
= svm_pre_enter_smm
,
4537 .pre_leave_smm
= svm_pre_leave_smm
,
4538 .enable_smi_window
= enable_smi_window
,
4540 .mem_enc_op
= svm_mem_enc_op
,
4541 .mem_enc_reg_region
= svm_register_enc_region
,
4542 .mem_enc_unreg_region
= svm_unregister_enc_region
,
4544 .can_emulate_instruction
= svm_can_emulate_instruction
,
4546 .apic_init_signal_blocked
= svm_apic_init_signal_blocked
,
4548 .msr_filter_changed
= svm_msr_filter_changed
,
4549 .complete_emulated_msr
= svm_complete_emulated_msr
,
4551 .vcpu_deliver_sipi_vector
= svm_vcpu_deliver_sipi_vector
,
4554 static struct kvm_x86_init_ops svm_init_ops __initdata
= {
4555 .cpu_has_kvm_support
= has_svm
,
4556 .disabled_by_bios
= is_disabled
,
4557 .hardware_setup
= svm_hardware_setup
,
4558 .check_processor_compatibility
= svm_check_processor_compat
,
4560 .runtime_ops
= &svm_x86_ops
,
4563 static int __init
svm_init(void)
4565 __unused_size_checks();
4567 return kvm_init(&svm_init_ops
, sizeof(struct vcpu_svm
),
4568 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4571 static void __exit
svm_exit(void)
4576 module_init(svm_init
)
4577 module_exit(svm_exit
)