2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
62 static bool erratum_383_found __read_mostly
;
64 static const u32 host_save_user_msrs
[] = {
66 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
69 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
82 /* These are the merged vectors */
85 /* gpa pointers to the real vectors */
89 /* A VMEXIT is required but not yet emulated */
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
96 unsigned long vmexit_rip
;
97 unsigned long vmexit_rsp
;
98 unsigned long vmexit_rax
;
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions
;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
114 struct kvm_vcpu vcpu
;
116 unsigned long vmcb_pa
;
117 struct svm_cpu_data
*svm_data
;
118 uint64_t asid_generation
;
119 uint64_t sysenter_esp
;
120 uint64_t sysenter_eip
;
124 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
134 struct nested_state nested
;
138 unsigned int3_injected
;
139 unsigned long int3_rip
;
143 #define MSR_INVALID 0xffffffffU
145 static struct svm_direct_access_msrs
{
146 u32 index
; /* Index of the MSR */
147 bool always
; /* True if intercept is always on */
148 } direct_access_msrs
[] = {
149 { .index
= MSR_STAR
, .always
= true },
150 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
152 { .index
= MSR_GS_BASE
, .always
= true },
153 { .index
= MSR_FS_BASE
, .always
= true },
154 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
155 { .index
= MSR_LSTAR
, .always
= true },
156 { .index
= MSR_CSTAR
, .always
= true },
157 { .index
= MSR_SYSCALL_MASK
, .always
= true },
159 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
160 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
161 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
162 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
163 { .index
= MSR_INVALID
, .always
= false },
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled
= true;
170 static bool npt_enabled
;
174 module_param(npt
, int, S_IRUGO
);
176 static int nested
= 1;
177 module_param(nested
, int, S_IRUGO
);
179 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
180 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
182 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
183 static int nested_svm_intercept(struct vcpu_svm
*svm
);
184 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
185 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
186 bool has_error_code
, u32 error_code
);
189 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
190 pause filter count */
191 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
192 VMCB_ASID
, /* ASID */
193 VMCB_INTR
, /* int_ctl, int_vector */
194 VMCB_NPT
, /* npt_en, nCR3, gPAT */
195 VMCB_CR
, /* CR0, CR3, CR4, EFER */
196 VMCB_DR
, /* DR6, DR7 */
197 VMCB_DT
, /* GDT, IDT */
198 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
199 VMCB_CR2
, /* CR2 only */
200 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
204 /* TPR and CR2 are always written before VMRUN */
205 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
207 static inline void mark_all_dirty(struct vmcb
*vmcb
)
209 vmcb
->control
.clean
= 0;
212 static inline void mark_all_clean(struct vmcb
*vmcb
)
214 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
215 & ~VMCB_ALWAYS_DIRTY_MASK
;
218 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
220 vmcb
->control
.clean
&= ~(1 << bit
);
223 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
225 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
228 static void recalc_intercepts(struct vcpu_svm
*svm
)
230 struct vmcb_control_area
*c
, *h
;
231 struct nested_state
*g
;
233 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
235 if (!is_guest_mode(&svm
->vcpu
))
238 c
= &svm
->vmcb
->control
;
239 h
= &svm
->nested
.hsave
->control
;
242 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
243 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
244 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
245 c
->intercept
= h
->intercept
| g
->intercept
;
248 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
250 if (is_guest_mode(&svm
->vcpu
))
251 return svm
->nested
.hsave
;
256 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
258 struct vmcb
*vmcb
= get_host_vmcb(svm
);
260 vmcb
->control
.intercept_cr
|= (1U << bit
);
262 recalc_intercepts(svm
);
265 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
267 struct vmcb
*vmcb
= get_host_vmcb(svm
);
269 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
271 recalc_intercepts(svm
);
274 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
276 struct vmcb
*vmcb
= get_host_vmcb(svm
);
278 return vmcb
->control
.intercept_cr
& (1U << bit
);
281 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
283 struct vmcb
*vmcb
= get_host_vmcb(svm
);
285 vmcb
->control
.intercept_dr
|= (1U << bit
);
287 recalc_intercepts(svm
);
290 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
292 struct vmcb
*vmcb
= get_host_vmcb(svm
);
294 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
296 recalc_intercepts(svm
);
299 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
301 struct vmcb
*vmcb
= get_host_vmcb(svm
);
303 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
305 recalc_intercepts(svm
);
308 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
310 struct vmcb
*vmcb
= get_host_vmcb(svm
);
312 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
314 recalc_intercepts(svm
);
317 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
319 struct vmcb
*vmcb
= get_host_vmcb(svm
);
321 vmcb
->control
.intercept
|= (1ULL << bit
);
323 recalc_intercepts(svm
);
326 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
328 struct vmcb
*vmcb
= get_host_vmcb(svm
);
330 vmcb
->control
.intercept
&= ~(1ULL << bit
);
332 recalc_intercepts(svm
);
335 static inline void enable_gif(struct vcpu_svm
*svm
)
337 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
340 static inline void disable_gif(struct vcpu_svm
*svm
)
342 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
345 static inline bool gif_set(struct vcpu_svm
*svm
)
347 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
350 static unsigned long iopm_base
;
352 struct kvm_ldttss_desc
{
355 unsigned base1
:8, type
:5, dpl
:2, p
:1;
356 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
359 } __attribute__((packed
));
361 struct svm_cpu_data
{
367 struct kvm_ldttss_desc
*tss_desc
;
369 struct page
*save_area
;
372 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
373 static uint32_t svm_features
;
375 struct svm_init_data
{
380 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
382 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
383 #define MSRS_RANGE_SIZE 2048
384 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
386 static u32
svm_msrpm_offset(u32 msr
)
391 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
392 if (msr
< msrpm_ranges
[i
] ||
393 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
396 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
397 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
399 /* Now we have the u8 offset - but need the u32 offset */
403 /* MSR not in any range */
407 #define MAX_INST_SIZE 15
409 static inline void clgi(void)
411 asm volatile (__ex(SVM_CLGI
));
414 static inline void stgi(void)
416 asm volatile (__ex(SVM_STGI
));
419 static inline void invlpga(unsigned long addr
, u32 asid
)
421 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
424 static int get_npt_level(void)
427 return PT64_ROOT_LEVEL
;
429 return PT32E_ROOT_LEVEL
;
433 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
435 vcpu
->arch
.efer
= efer
;
436 if (!npt_enabled
&& !(efer
& EFER_LMA
))
439 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
440 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
443 static int is_external_interrupt(u32 info
)
445 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
446 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
449 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
451 struct vcpu_svm
*svm
= to_svm(vcpu
);
454 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
455 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
459 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
461 struct vcpu_svm
*svm
= to_svm(vcpu
);
464 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
466 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
470 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
472 struct vcpu_svm
*svm
= to_svm(vcpu
);
474 if (svm
->vmcb
->control
.next_rip
!= 0)
475 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
477 if (!svm
->next_rip
) {
478 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
480 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
483 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
484 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
485 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
487 kvm_rip_write(vcpu
, svm
->next_rip
);
488 svm_set_interrupt_shadow(vcpu
, 0);
491 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
492 bool has_error_code
, u32 error_code
,
495 struct vcpu_svm
*svm
= to_svm(vcpu
);
498 * If we are within a nested VM we'd better #VMEXIT and let the guest
499 * handle the exception
502 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
505 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
506 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
509 * For guest debugging where we have to reinject #BP if some
510 * INT3 is guest-owned:
511 * Emulate nRIP by moving RIP forward. Will fail if injection
512 * raises a fault that is not intercepted. Still better than
513 * failing in all cases.
515 skip_emulated_instruction(&svm
->vcpu
);
516 rip
= kvm_rip_read(&svm
->vcpu
);
517 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
518 svm
->int3_injected
= rip
- old_rip
;
521 svm
->vmcb
->control
.event_inj
= nr
523 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
524 | SVM_EVTINJ_TYPE_EXEPT
;
525 svm
->vmcb
->control
.event_inj_err
= error_code
;
528 static void svm_init_erratum_383(void)
534 if (!cpu_has_amd_erratum(amd_erratum_383
))
537 /* Use _safe variants to not break nested virtualization */
538 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
544 low
= lower_32_bits(val
);
545 high
= upper_32_bits(val
);
547 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
549 erratum_383_found
= true;
552 static int has_svm(void)
556 if (!cpu_has_svm(&msg
)) {
557 printk(KERN_INFO
"has_svm: %s\n", msg
);
564 static void svm_hardware_disable(void *garbage
)
569 static int svm_hardware_enable(void *garbage
)
572 struct svm_cpu_data
*sd
;
574 struct desc_ptr gdt_descr
;
575 struct desc_struct
*gdt
;
576 int me
= raw_smp_processor_id();
578 rdmsrl(MSR_EFER
, efer
);
579 if (efer
& EFER_SVME
)
583 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
587 sd
= per_cpu(svm_data
, me
);
590 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
595 sd
->asid_generation
= 1;
596 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
597 sd
->next_asid
= sd
->max_asid
+ 1;
599 native_store_gdt(&gdt_descr
);
600 gdt
= (struct desc_struct
*)gdt_descr
.address
;
601 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
603 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
605 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
607 svm_init_erratum_383();
612 static void svm_cpu_uninit(int cpu
)
614 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
619 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
620 __free_page(sd
->save_area
);
624 static int svm_cpu_init(int cpu
)
626 struct svm_cpu_data
*sd
;
629 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
633 sd
->save_area
= alloc_page(GFP_KERNEL
);
638 per_cpu(svm_data
, cpu
) = sd
;
648 static bool valid_msr_intercept(u32 index
)
652 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
653 if (direct_access_msrs
[i
].index
== index
)
659 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
662 u8 bit_read
, bit_write
;
667 * If this warning triggers extend the direct_access_msrs list at the
668 * beginning of the file
670 WARN_ON(!valid_msr_intercept(msr
));
672 offset
= svm_msrpm_offset(msr
);
673 bit_read
= 2 * (msr
& 0x0f);
674 bit_write
= 2 * (msr
& 0x0f) + 1;
677 BUG_ON(offset
== MSR_INVALID
);
679 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
680 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
685 static void svm_vcpu_init_msrpm(u32
*msrpm
)
689 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
691 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
692 if (!direct_access_msrs
[i
].always
)
695 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
699 static void add_msr_offset(u32 offset
)
703 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
705 /* Offset already in list? */
706 if (msrpm_offsets
[i
] == offset
)
709 /* Slot used by another offset? */
710 if (msrpm_offsets
[i
] != MSR_INVALID
)
713 /* Add offset to list */
714 msrpm_offsets
[i
] = offset
;
720 * If this BUG triggers the msrpm_offsets table has an overflow. Just
721 * increase MSRPM_OFFSETS in this case.
726 static void init_msrpm_offsets(void)
730 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
732 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
735 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
736 BUG_ON(offset
== MSR_INVALID
);
738 add_msr_offset(offset
);
742 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
744 u32
*msrpm
= svm
->msrpm
;
746 svm
->vmcb
->control
.lbr_ctl
= 1;
747 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
748 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
749 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
750 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
753 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
755 u32
*msrpm
= svm
->msrpm
;
757 svm
->vmcb
->control
.lbr_ctl
= 0;
758 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
759 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
760 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
761 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
764 static __init
int svm_hardware_setup(void)
767 struct page
*iopm_pages
;
771 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
776 iopm_va
= page_address(iopm_pages
);
777 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
778 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
780 init_msrpm_offsets();
782 if (boot_cpu_has(X86_FEATURE_NX
))
783 kvm_enable_efer_bits(EFER_NX
);
785 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
786 kvm_enable_efer_bits(EFER_FFXSR
);
789 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
790 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
793 for_each_possible_cpu(cpu
) {
794 r
= svm_cpu_init(cpu
);
799 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
801 if (!boot_cpu_has(X86_FEATURE_NPT
))
804 if (npt_enabled
&& !npt
) {
805 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
810 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
818 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
823 static __exit
void svm_hardware_unsetup(void)
827 for_each_possible_cpu(cpu
)
830 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
834 static void init_seg(struct vmcb_seg
*seg
)
837 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
838 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
843 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
846 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
851 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
853 struct vcpu_svm
*svm
= to_svm(vcpu
);
854 u64 g_tsc_offset
= 0;
856 if (is_guest_mode(vcpu
)) {
857 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
858 svm
->nested
.hsave
->control
.tsc_offset
;
859 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
862 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
864 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
867 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
869 struct vcpu_svm
*svm
= to_svm(vcpu
);
871 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
872 if (is_guest_mode(vcpu
))
873 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
874 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
877 static void init_vmcb(struct vcpu_svm
*svm
)
879 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
880 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
882 svm
->vcpu
.fpu_active
= 1;
883 svm
->vcpu
.arch
.hflags
= 0;
885 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
886 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
887 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
888 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
889 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
890 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
891 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
893 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
894 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
895 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
896 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
897 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
898 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
899 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
900 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
902 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
903 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
904 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
905 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
906 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
907 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
908 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
909 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
911 set_exception_intercept(svm
, PF_VECTOR
);
912 set_exception_intercept(svm
, UD_VECTOR
);
913 set_exception_intercept(svm
, MC_VECTOR
);
915 set_intercept(svm
, INTERCEPT_INTR
);
916 set_intercept(svm
, INTERCEPT_NMI
);
917 set_intercept(svm
, INTERCEPT_SMI
);
918 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
919 set_intercept(svm
, INTERCEPT_CPUID
);
920 set_intercept(svm
, INTERCEPT_INVD
);
921 set_intercept(svm
, INTERCEPT_HLT
);
922 set_intercept(svm
, INTERCEPT_INVLPG
);
923 set_intercept(svm
, INTERCEPT_INVLPGA
);
924 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
925 set_intercept(svm
, INTERCEPT_MSR_PROT
);
926 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
927 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
928 set_intercept(svm
, INTERCEPT_VMRUN
);
929 set_intercept(svm
, INTERCEPT_VMMCALL
);
930 set_intercept(svm
, INTERCEPT_VMLOAD
);
931 set_intercept(svm
, INTERCEPT_VMSAVE
);
932 set_intercept(svm
, INTERCEPT_STGI
);
933 set_intercept(svm
, INTERCEPT_CLGI
);
934 set_intercept(svm
, INTERCEPT_SKINIT
);
935 set_intercept(svm
, INTERCEPT_WBINVD
);
936 set_intercept(svm
, INTERCEPT_MONITOR
);
937 set_intercept(svm
, INTERCEPT_MWAIT
);
938 set_intercept(svm
, INTERCEPT_XSETBV
);
940 control
->iopm_base_pa
= iopm_base
;
941 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
942 control
->int_ctl
= V_INTR_MASKING_MASK
;
950 save
->cs
.selector
= 0xf000;
951 /* Executable/Readable Code Segment */
952 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
953 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
954 save
->cs
.limit
= 0xffff;
956 * cs.base should really be 0xffff0000, but vmx can't handle that, so
957 * be consistent with it.
959 * Replace when we have real mode working for vmx.
961 save
->cs
.base
= 0xf0000;
963 save
->gdtr
.limit
= 0xffff;
964 save
->idtr
.limit
= 0xffff;
966 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
967 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
969 svm_set_efer(&svm
->vcpu
, 0);
970 save
->dr6
= 0xffff0ff0;
973 save
->rip
= 0x0000fff0;
974 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
977 * This is the guest-visible cr0 value.
978 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
980 svm
->vcpu
.arch
.cr0
= 0;
981 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
983 save
->cr4
= X86_CR4_PAE
;
987 /* Setup VMCB for Nested Paging */
988 control
->nested_ctl
= 1;
989 clr_intercept(svm
, INTERCEPT_TASK_SWITCH
);
990 clr_intercept(svm
, INTERCEPT_INVLPG
);
991 clr_exception_intercept(svm
, PF_VECTOR
);
992 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
993 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
994 save
->g_pat
= 0x0007040600070406ULL
;
998 svm
->asid_generation
= 0;
1000 svm
->nested
.vmcb
= 0;
1001 svm
->vcpu
.arch
.hflags
= 0;
1003 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1004 control
->pause_filter_count
= 3000;
1005 set_intercept(svm
, INTERCEPT_PAUSE
);
1008 mark_all_dirty(svm
->vmcb
);
1013 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1015 struct vcpu_svm
*svm
= to_svm(vcpu
);
1019 if (!kvm_vcpu_is_bsp(vcpu
)) {
1020 kvm_rip_write(vcpu
, 0);
1021 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1022 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1024 vcpu
->arch
.regs_avail
= ~0;
1025 vcpu
->arch
.regs_dirty
= ~0;
1030 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1032 struct vcpu_svm
*svm
;
1034 struct page
*msrpm_pages
;
1035 struct page
*hsave_page
;
1036 struct page
*nested_msrpm_pages
;
1039 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1045 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1050 page
= alloc_page(GFP_KERNEL
);
1054 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1058 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1059 if (!nested_msrpm_pages
)
1062 hsave_page
= alloc_page(GFP_KERNEL
);
1066 svm
->nested
.hsave
= page_address(hsave_page
);
1068 svm
->msrpm
= page_address(msrpm_pages
);
1069 svm_vcpu_init_msrpm(svm
->msrpm
);
1071 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1072 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1074 svm
->vmcb
= page_address(page
);
1075 clear_page(svm
->vmcb
);
1076 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1077 svm
->asid_generation
= 0;
1079 kvm_write_tsc(&svm
->vcpu
, 0);
1081 err
= fx_init(&svm
->vcpu
);
1085 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1086 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1087 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1092 __free_page(hsave_page
);
1094 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1096 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1100 kvm_vcpu_uninit(&svm
->vcpu
);
1102 kmem_cache_free(kvm_vcpu_cache
, svm
);
1104 return ERR_PTR(err
);
1107 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1109 struct vcpu_svm
*svm
= to_svm(vcpu
);
1111 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1112 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1113 __free_page(virt_to_page(svm
->nested
.hsave
));
1114 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1115 kvm_vcpu_uninit(vcpu
);
1116 kmem_cache_free(kvm_vcpu_cache
, svm
);
1119 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1121 struct vcpu_svm
*svm
= to_svm(vcpu
);
1124 if (unlikely(cpu
!= vcpu
->cpu
)) {
1125 svm
->asid_generation
= 0;
1126 mark_all_dirty(svm
->vmcb
);
1129 #ifdef CONFIG_X86_64
1130 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1132 savesegment(fs
, svm
->host
.fs
);
1133 savesegment(gs
, svm
->host
.gs
);
1134 svm
->host
.ldt
= kvm_read_ldt();
1136 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1137 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1140 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1142 struct vcpu_svm
*svm
= to_svm(vcpu
);
1145 ++vcpu
->stat
.host_state_reload
;
1146 kvm_load_ldt(svm
->host
.ldt
);
1147 #ifdef CONFIG_X86_64
1148 loadsegment(fs
, svm
->host
.fs
);
1149 load_gs_index(svm
->host
.gs
);
1150 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1152 loadsegment(gs
, svm
->host
.gs
);
1154 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1155 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1158 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1160 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1163 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1165 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1168 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1171 case VCPU_EXREG_PDPTR
:
1172 BUG_ON(!npt_enabled
);
1173 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, vcpu
->arch
.cr3
);
1180 static void svm_set_vintr(struct vcpu_svm
*svm
)
1182 set_intercept(svm
, INTERCEPT_VINTR
);
1185 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1187 clr_intercept(svm
, INTERCEPT_VINTR
);
1190 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1192 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1195 case VCPU_SREG_CS
: return &save
->cs
;
1196 case VCPU_SREG_DS
: return &save
->ds
;
1197 case VCPU_SREG_ES
: return &save
->es
;
1198 case VCPU_SREG_FS
: return &save
->fs
;
1199 case VCPU_SREG_GS
: return &save
->gs
;
1200 case VCPU_SREG_SS
: return &save
->ss
;
1201 case VCPU_SREG_TR
: return &save
->tr
;
1202 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1208 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1210 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1215 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1216 struct kvm_segment
*var
, int seg
)
1218 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1220 var
->base
= s
->base
;
1221 var
->limit
= s
->limit
;
1222 var
->selector
= s
->selector
;
1223 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1224 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1225 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1226 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1227 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1228 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1229 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1230 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1233 * AMD's VMCB does not have an explicit unusable field, so emulate it
1234 * for cross vendor migration purposes by "not present"
1236 var
->unusable
= !var
->present
|| (var
->type
== 0);
1241 * SVM always stores 0 for the 'G' bit in the CS selector in
1242 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1243 * Intel's VMENTRY has a check on the 'G' bit.
1245 var
->g
= s
->limit
> 0xfffff;
1249 * Work around a bug where the busy flag in the tr selector
1259 * The accessed bit must always be set in the segment
1260 * descriptor cache, although it can be cleared in the
1261 * descriptor, the cached bit always remains at 1. Since
1262 * Intel has a check on this, set it here to support
1263 * cross-vendor migration.
1270 * On AMD CPUs sometimes the DB bit in the segment
1271 * descriptor is left as 1, although the whole segment has
1272 * been made unusable. Clear it here to pass an Intel VMX
1273 * entry check when cross vendor migrating.
1281 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1283 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1288 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1290 struct vcpu_svm
*svm
= to_svm(vcpu
);
1292 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1293 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1296 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1298 struct vcpu_svm
*svm
= to_svm(vcpu
);
1300 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1301 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1302 mark_dirty(svm
->vmcb
, VMCB_DT
);
1305 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1307 struct vcpu_svm
*svm
= to_svm(vcpu
);
1309 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1310 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1313 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1315 struct vcpu_svm
*svm
= to_svm(vcpu
);
1317 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1318 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1319 mark_dirty(svm
->vmcb
, VMCB_DT
);
1322 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1326 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1330 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1332 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1333 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1335 if (!svm
->vcpu
.fpu_active
)
1336 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1338 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1339 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1341 mark_dirty(svm
->vmcb
, VMCB_CR
);
1343 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1344 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1345 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1347 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1348 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1352 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1354 struct vcpu_svm
*svm
= to_svm(vcpu
);
1356 if (is_guest_mode(vcpu
)) {
1358 * We are here because we run in nested mode, the host kvm
1359 * intercepts cr0 writes but the l1 hypervisor does not.
1360 * But the L1 hypervisor may intercept selective cr0 writes.
1361 * This needs to be checked here.
1363 unsigned long old
, new;
1365 /* Remove bits that would trigger a real cr0 write intercept */
1366 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1367 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1370 /* cr0 write with ts and mp unchanged */
1371 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1372 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1373 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1374 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1375 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1381 #ifdef CONFIG_X86_64
1382 if (vcpu
->arch
.efer
& EFER_LME
) {
1383 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1384 vcpu
->arch
.efer
|= EFER_LMA
;
1385 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1388 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1389 vcpu
->arch
.efer
&= ~EFER_LMA
;
1390 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1394 vcpu
->arch
.cr0
= cr0
;
1397 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1399 if (!vcpu
->fpu_active
)
1402 * re-enable caching here because the QEMU bios
1403 * does not do it - this results in some delay at
1406 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1407 svm
->vmcb
->save
.cr0
= cr0
;
1408 mark_dirty(svm
->vmcb
, VMCB_CR
);
1409 update_cr0_intercept(svm
);
1412 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1414 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1415 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1417 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1418 svm_flush_tlb(vcpu
);
1420 vcpu
->arch
.cr4
= cr4
;
1423 cr4
|= host_cr4_mce
;
1424 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1425 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1428 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1429 struct kvm_segment
*var
, int seg
)
1431 struct vcpu_svm
*svm
= to_svm(vcpu
);
1432 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1434 s
->base
= var
->base
;
1435 s
->limit
= var
->limit
;
1436 s
->selector
= var
->selector
;
1440 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1441 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1442 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1443 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1444 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1445 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1446 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1447 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1449 if (seg
== VCPU_SREG_CS
)
1451 = (svm
->vmcb
->save
.cs
.attrib
1452 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1454 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1457 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1459 struct vcpu_svm
*svm
= to_svm(vcpu
);
1461 clr_exception_intercept(svm
, DB_VECTOR
);
1462 clr_exception_intercept(svm
, BP_VECTOR
);
1464 if (svm
->nmi_singlestep
)
1465 set_exception_intercept(svm
, DB_VECTOR
);
1467 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1468 if (vcpu
->guest_debug
&
1469 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1470 set_exception_intercept(svm
, DB_VECTOR
);
1471 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1472 set_exception_intercept(svm
, BP_VECTOR
);
1474 vcpu
->guest_debug
= 0;
1477 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1479 struct vcpu_svm
*svm
= to_svm(vcpu
);
1481 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1482 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1484 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1486 mark_dirty(svm
->vmcb
, VMCB_DR
);
1488 update_db_intercept(vcpu
);
1491 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1493 if (sd
->next_asid
> sd
->max_asid
) {
1494 ++sd
->asid_generation
;
1496 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1499 svm
->asid_generation
= sd
->asid_generation
;
1500 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1502 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1505 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1507 struct vcpu_svm
*svm
= to_svm(vcpu
);
1509 svm
->vmcb
->save
.dr7
= value
;
1510 mark_dirty(svm
->vmcb
, VMCB_DR
);
1513 static int pf_interception(struct vcpu_svm
*svm
)
1515 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1519 switch (svm
->apf_reason
) {
1521 error_code
= svm
->vmcb
->control
.exit_info_1
;
1523 trace_kvm_page_fault(fault_address
, error_code
);
1524 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1525 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1526 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1528 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1529 svm
->apf_reason
= 0;
1530 local_irq_disable();
1531 kvm_async_pf_task_wait(fault_address
);
1534 case KVM_PV_REASON_PAGE_READY
:
1535 svm
->apf_reason
= 0;
1536 local_irq_disable();
1537 kvm_async_pf_task_wake(fault_address
);
1544 static int db_interception(struct vcpu_svm
*svm
)
1546 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1548 if (!(svm
->vcpu
.guest_debug
&
1549 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1550 !svm
->nmi_singlestep
) {
1551 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1555 if (svm
->nmi_singlestep
) {
1556 svm
->nmi_singlestep
= false;
1557 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1558 svm
->vmcb
->save
.rflags
&=
1559 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1560 update_db_intercept(&svm
->vcpu
);
1563 if (svm
->vcpu
.guest_debug
&
1564 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1565 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1566 kvm_run
->debug
.arch
.pc
=
1567 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1568 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1575 static int bp_interception(struct vcpu_svm
*svm
)
1577 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1579 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1580 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1581 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1585 static int ud_interception(struct vcpu_svm
*svm
)
1589 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1590 if (er
!= EMULATE_DONE
)
1591 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1595 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1597 struct vcpu_svm
*svm
= to_svm(vcpu
);
1599 clr_exception_intercept(svm
, NM_VECTOR
);
1601 svm
->vcpu
.fpu_active
= 1;
1602 update_cr0_intercept(svm
);
1605 static int nm_interception(struct vcpu_svm
*svm
)
1607 svm_fpu_activate(&svm
->vcpu
);
1611 static bool is_erratum_383(void)
1616 if (!erratum_383_found
)
1619 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1623 /* Bit 62 may or may not be set for this mce */
1624 value
&= ~(1ULL << 62);
1626 if (value
!= 0xb600000000010015ULL
)
1629 /* Clear MCi_STATUS registers */
1630 for (i
= 0; i
< 6; ++i
)
1631 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1633 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1637 value
&= ~(1ULL << 2);
1638 low
= lower_32_bits(value
);
1639 high
= upper_32_bits(value
);
1641 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1644 /* Flush tlb to evict multi-match entries */
1650 static void svm_handle_mce(struct vcpu_svm
*svm
)
1652 if (is_erratum_383()) {
1654 * Erratum 383 triggered. Guest state is corrupt so kill the
1657 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1659 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1665 * On an #MC intercept the MCE handler is not called automatically in
1666 * the host. So do it by hand here.
1670 /* not sure if we ever come back to this point */
1675 static int mc_interception(struct vcpu_svm
*svm
)
1680 static int shutdown_interception(struct vcpu_svm
*svm
)
1682 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1685 * VMCB is undefined after a SHUTDOWN intercept
1686 * so reinitialize it.
1688 clear_page(svm
->vmcb
);
1691 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1695 static int io_interception(struct vcpu_svm
*svm
)
1697 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1698 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1699 int size
, in
, string
;
1702 ++svm
->vcpu
.stat
.io_exits
;
1703 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1704 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1706 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1708 port
= io_info
>> 16;
1709 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1710 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1711 skip_emulated_instruction(&svm
->vcpu
);
1713 return kvm_fast_pio_out(vcpu
, size
, port
);
1716 static int nmi_interception(struct vcpu_svm
*svm
)
1721 static int intr_interception(struct vcpu_svm
*svm
)
1723 ++svm
->vcpu
.stat
.irq_exits
;
1727 static int nop_on_interception(struct vcpu_svm
*svm
)
1732 static int halt_interception(struct vcpu_svm
*svm
)
1734 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1735 skip_emulated_instruction(&svm
->vcpu
);
1736 return kvm_emulate_halt(&svm
->vcpu
);
1739 static int vmmcall_interception(struct vcpu_svm
*svm
)
1741 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1742 skip_emulated_instruction(&svm
->vcpu
);
1743 kvm_emulate_hypercall(&svm
->vcpu
);
1747 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1749 struct vcpu_svm
*svm
= to_svm(vcpu
);
1751 return svm
->nested
.nested_cr3
;
1754 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1757 struct vcpu_svm
*svm
= to_svm(vcpu
);
1759 svm
->vmcb
->control
.nested_cr3
= root
;
1760 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1761 svm_flush_tlb(vcpu
);
1764 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1765 struct x86_exception
*fault
)
1767 struct vcpu_svm
*svm
= to_svm(vcpu
);
1769 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1770 svm
->vmcb
->control
.exit_code_hi
= 0;
1771 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1772 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1774 nested_svm_vmexit(svm
);
1777 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1781 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1783 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1784 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1785 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1786 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1787 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1792 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1794 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1797 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1799 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1800 || !is_paging(&svm
->vcpu
)) {
1801 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1805 if (svm
->vmcb
->save
.cpl
) {
1806 kvm_inject_gp(&svm
->vcpu
, 0);
1813 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1814 bool has_error_code
, u32 error_code
)
1818 if (!is_guest_mode(&svm
->vcpu
))
1821 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1822 svm
->vmcb
->control
.exit_code_hi
= 0;
1823 svm
->vmcb
->control
.exit_info_1
= error_code
;
1824 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1826 vmexit
= nested_svm_intercept(svm
);
1827 if (vmexit
== NESTED_EXIT_DONE
)
1828 svm
->nested
.exit_required
= true;
1833 /* This function returns true if it is save to enable the irq window */
1834 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1836 if (!is_guest_mode(&svm
->vcpu
))
1839 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1842 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1846 * if vmexit was already requested (by intercepted exception
1847 * for instance) do not overwrite it with "external interrupt"
1850 if (svm
->nested
.exit_required
)
1853 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1854 svm
->vmcb
->control
.exit_info_1
= 0;
1855 svm
->vmcb
->control
.exit_info_2
= 0;
1857 if (svm
->nested
.intercept
& 1ULL) {
1859 * The #vmexit can't be emulated here directly because this
1860 * code path runs with irqs and preemtion disabled. A
1861 * #vmexit emulation might sleep. Only signal request for
1864 svm
->nested
.exit_required
= true;
1865 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1872 /* This function returns true if it is save to enable the nmi window */
1873 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1875 if (!is_guest_mode(&svm
->vcpu
))
1878 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1881 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1882 svm
->nested
.exit_required
= true;
1887 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1893 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1894 if (is_error_page(page
))
1902 kvm_release_page_clean(page
);
1903 kvm_inject_gp(&svm
->vcpu
, 0);
1908 static void nested_svm_unmap(struct page
*page
)
1911 kvm_release_page_dirty(page
);
1914 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1920 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1921 return NESTED_EXIT_HOST
;
1923 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1924 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1928 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1931 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1934 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1936 u32 offset
, msr
, value
;
1939 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1940 return NESTED_EXIT_HOST
;
1942 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1943 offset
= svm_msrpm_offset(msr
);
1944 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1945 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1947 if (offset
== MSR_INVALID
)
1948 return NESTED_EXIT_DONE
;
1950 /* Offset is in 32 bit units but need in 8 bit units */
1953 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1954 return NESTED_EXIT_DONE
;
1956 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1959 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1961 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1963 switch (exit_code
) {
1966 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1967 return NESTED_EXIT_HOST
;
1969 /* For now we are always handling NPFs when using them */
1971 return NESTED_EXIT_HOST
;
1973 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1974 /* When we're shadowing, trap PFs, but not async PF */
1975 if (!npt_enabled
&& svm
->apf_reason
== 0)
1976 return NESTED_EXIT_HOST
;
1978 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1979 nm_interception(svm
);
1985 return NESTED_EXIT_CONTINUE
;
1989 * If this function returns true, this #vmexit was already handled
1991 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1993 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1994 int vmexit
= NESTED_EXIT_HOST
;
1996 switch (exit_code
) {
1998 vmexit
= nested_svm_exit_handled_msr(svm
);
2001 vmexit
= nested_svm_intercept_ioio(svm
);
2003 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2004 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2005 if (svm
->nested
.intercept_cr
& bit
)
2006 vmexit
= NESTED_EXIT_DONE
;
2009 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2010 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2011 if (svm
->nested
.intercept_dr
& bit
)
2012 vmexit
= NESTED_EXIT_DONE
;
2015 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2016 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2017 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2018 vmexit
= NESTED_EXIT_DONE
;
2019 /* async page fault always cause vmexit */
2020 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2021 svm
->apf_reason
!= 0)
2022 vmexit
= NESTED_EXIT_DONE
;
2025 case SVM_EXIT_ERR
: {
2026 vmexit
= NESTED_EXIT_DONE
;
2030 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2031 if (svm
->nested
.intercept
& exit_bits
)
2032 vmexit
= NESTED_EXIT_DONE
;
2039 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2043 vmexit
= nested_svm_intercept(svm
);
2045 if (vmexit
== NESTED_EXIT_DONE
)
2046 nested_svm_vmexit(svm
);
2051 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2053 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2054 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2056 dst
->intercept_cr
= from
->intercept_cr
;
2057 dst
->intercept_dr
= from
->intercept_dr
;
2058 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2059 dst
->intercept
= from
->intercept
;
2060 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2061 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2062 dst
->tsc_offset
= from
->tsc_offset
;
2063 dst
->asid
= from
->asid
;
2064 dst
->tlb_ctl
= from
->tlb_ctl
;
2065 dst
->int_ctl
= from
->int_ctl
;
2066 dst
->int_vector
= from
->int_vector
;
2067 dst
->int_state
= from
->int_state
;
2068 dst
->exit_code
= from
->exit_code
;
2069 dst
->exit_code_hi
= from
->exit_code_hi
;
2070 dst
->exit_info_1
= from
->exit_info_1
;
2071 dst
->exit_info_2
= from
->exit_info_2
;
2072 dst
->exit_int_info
= from
->exit_int_info
;
2073 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2074 dst
->nested_ctl
= from
->nested_ctl
;
2075 dst
->event_inj
= from
->event_inj
;
2076 dst
->event_inj_err
= from
->event_inj_err
;
2077 dst
->nested_cr3
= from
->nested_cr3
;
2078 dst
->lbr_ctl
= from
->lbr_ctl
;
2081 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2083 struct vmcb
*nested_vmcb
;
2084 struct vmcb
*hsave
= svm
->nested
.hsave
;
2085 struct vmcb
*vmcb
= svm
->vmcb
;
2088 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2089 vmcb
->control
.exit_info_1
,
2090 vmcb
->control
.exit_info_2
,
2091 vmcb
->control
.exit_int_info
,
2092 vmcb
->control
.exit_int_info_err
);
2094 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2098 /* Exit Guest-Mode */
2099 leave_guest_mode(&svm
->vcpu
);
2100 svm
->nested
.vmcb
= 0;
2102 /* Give the current vmcb to the guest */
2105 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2106 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2107 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2108 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2109 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2110 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2111 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2112 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2113 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2114 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2115 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2116 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
2117 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2118 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2119 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2120 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2121 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2122 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2124 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2125 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2126 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2127 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2128 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2129 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2130 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2131 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2132 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2133 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2136 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2137 * to make sure that we do not lose injected events. So check event_inj
2138 * here and copy it to exit_int_info if it is valid.
2139 * Exit_int_info and event_inj can't be both valid because the case
2140 * below only happens on a VMRUN instruction intercept which has
2141 * no valid exit_int_info set.
2143 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2144 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2146 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2147 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2150 nested_vmcb
->control
.tlb_ctl
= 0;
2151 nested_vmcb
->control
.event_inj
= 0;
2152 nested_vmcb
->control
.event_inj_err
= 0;
2154 /* We always set V_INTR_MASKING and remember the old value in hflags */
2155 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2156 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2158 /* Restore the original control entries */
2159 copy_vmcb_control_area(vmcb
, hsave
);
2161 kvm_clear_exception_queue(&svm
->vcpu
);
2162 kvm_clear_interrupt_queue(&svm
->vcpu
);
2164 svm
->nested
.nested_cr3
= 0;
2166 /* Restore selected save entries */
2167 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2168 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2169 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2170 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2171 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2172 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2173 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
2174 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2175 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2176 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2178 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2179 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2181 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2183 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2184 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2185 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2186 svm
->vmcb
->save
.dr7
= 0;
2187 svm
->vmcb
->save
.cpl
= 0;
2188 svm
->vmcb
->control
.exit_int_info
= 0;
2190 mark_all_dirty(svm
->vmcb
);
2192 nested_svm_unmap(page
);
2194 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2195 kvm_mmu_reset_context(&svm
->vcpu
);
2196 kvm_mmu_load(&svm
->vcpu
);
2201 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2204 * This function merges the msr permission bitmaps of kvm and the
2205 * nested vmcb. It is omptimized in that it only merges the parts where
2206 * the kvm msr permission bitmap may contain zero bits
2210 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2213 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2217 if (msrpm_offsets
[i
] == 0xffffffff)
2220 p
= msrpm_offsets
[i
];
2221 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2223 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2226 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2229 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2234 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2236 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2239 if (vmcb
->control
.asid
== 0)
2242 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2248 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2250 struct vmcb
*nested_vmcb
;
2251 struct vmcb
*hsave
= svm
->nested
.hsave
;
2252 struct vmcb
*vmcb
= svm
->vmcb
;
2256 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2258 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2262 if (!nested_vmcb_checks(nested_vmcb
)) {
2263 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2264 nested_vmcb
->control
.exit_code_hi
= 0;
2265 nested_vmcb
->control
.exit_info_1
= 0;
2266 nested_vmcb
->control
.exit_info_2
= 0;
2268 nested_svm_unmap(page
);
2273 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2274 nested_vmcb
->save
.rip
,
2275 nested_vmcb
->control
.int_ctl
,
2276 nested_vmcb
->control
.event_inj
,
2277 nested_vmcb
->control
.nested_ctl
);
2279 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2280 nested_vmcb
->control
.intercept_cr
>> 16,
2281 nested_vmcb
->control
.intercept_exceptions
,
2282 nested_vmcb
->control
.intercept
);
2284 /* Clear internal status */
2285 kvm_clear_exception_queue(&svm
->vcpu
);
2286 kvm_clear_interrupt_queue(&svm
->vcpu
);
2289 * Save the old vmcb, so we don't need to pick what we save, but can
2290 * restore everything when a VMEXIT occurs
2292 hsave
->save
.es
= vmcb
->save
.es
;
2293 hsave
->save
.cs
= vmcb
->save
.cs
;
2294 hsave
->save
.ss
= vmcb
->save
.ss
;
2295 hsave
->save
.ds
= vmcb
->save
.ds
;
2296 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2297 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2298 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2299 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2300 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2301 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2302 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2303 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2304 hsave
->save
.rax
= vmcb
->save
.rax
;
2306 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2308 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2310 copy_vmcb_control_area(hsave
, vmcb
);
2312 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2313 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2315 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2317 if (nested_vmcb
->control
.nested_ctl
) {
2318 kvm_mmu_unload(&svm
->vcpu
);
2319 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2320 nested_svm_init_mmu_context(&svm
->vcpu
);
2323 /* Load the nested guest state */
2324 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2325 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2326 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2327 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2328 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2329 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2330 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2331 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2332 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2333 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2335 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2336 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2338 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2340 /* Guest paging mode is active - reset mmu */
2341 kvm_mmu_reset_context(&svm
->vcpu
);
2343 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2344 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2345 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2346 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2348 /* In case we don't even reach vcpu_run, the fields are not updated */
2349 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2350 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2351 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2352 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2353 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2354 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2356 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2357 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2359 /* cache intercepts */
2360 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2361 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2362 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2363 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2365 svm_flush_tlb(&svm
->vcpu
);
2366 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2367 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2368 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2370 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2372 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2373 /* We only want the cr8 intercept bits of the guest */
2374 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2375 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2378 /* We don't want to see VMMCALLs from a nested guest */
2379 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2381 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2382 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2383 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2384 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2385 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2386 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2388 nested_svm_unmap(page
);
2390 /* Enter Guest-Mode */
2391 enter_guest_mode(&svm
->vcpu
);
2394 * Merge guest and host intercepts - must be called with vcpu in
2395 * guest-mode to take affect here
2397 recalc_intercepts(svm
);
2399 svm
->nested
.vmcb
= vmcb_gpa
;
2403 mark_all_dirty(svm
->vmcb
);
2408 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2410 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2411 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2412 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2413 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2414 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2415 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2416 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2417 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2418 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2419 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2420 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2421 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2424 static int vmload_interception(struct vcpu_svm
*svm
)
2426 struct vmcb
*nested_vmcb
;
2429 if (nested_svm_check_permissions(svm
))
2432 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2433 skip_emulated_instruction(&svm
->vcpu
);
2435 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2439 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2440 nested_svm_unmap(page
);
2445 static int vmsave_interception(struct vcpu_svm
*svm
)
2447 struct vmcb
*nested_vmcb
;
2450 if (nested_svm_check_permissions(svm
))
2453 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2454 skip_emulated_instruction(&svm
->vcpu
);
2456 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2460 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2461 nested_svm_unmap(page
);
2466 static int vmrun_interception(struct vcpu_svm
*svm
)
2468 if (nested_svm_check_permissions(svm
))
2471 /* Save rip after vmrun instruction */
2472 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2474 if (!nested_svm_vmrun(svm
))
2477 if (!nested_svm_vmrun_msrpm(svm
))
2484 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2485 svm
->vmcb
->control
.exit_code_hi
= 0;
2486 svm
->vmcb
->control
.exit_info_1
= 0;
2487 svm
->vmcb
->control
.exit_info_2
= 0;
2489 nested_svm_vmexit(svm
);
2494 static int stgi_interception(struct vcpu_svm
*svm
)
2496 if (nested_svm_check_permissions(svm
))
2499 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2500 skip_emulated_instruction(&svm
->vcpu
);
2501 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2508 static int clgi_interception(struct vcpu_svm
*svm
)
2510 if (nested_svm_check_permissions(svm
))
2513 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2514 skip_emulated_instruction(&svm
->vcpu
);
2518 /* After a CLGI no interrupts should come */
2519 svm_clear_vintr(svm
);
2520 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2522 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2527 static int invlpga_interception(struct vcpu_svm
*svm
)
2529 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2531 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2532 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2534 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2535 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2537 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2538 skip_emulated_instruction(&svm
->vcpu
);
2542 static int skinit_interception(struct vcpu_svm
*svm
)
2544 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2546 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2550 static int xsetbv_interception(struct vcpu_svm
*svm
)
2552 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2553 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2555 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2556 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2557 skip_emulated_instruction(&svm
->vcpu
);
2563 static int invalid_op_interception(struct vcpu_svm
*svm
)
2565 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2569 static int task_switch_interception(struct vcpu_svm
*svm
)
2573 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2574 SVM_EXITINTINFO_TYPE_MASK
;
2575 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2577 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2579 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2580 bool has_error_code
= false;
2583 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2585 if (svm
->vmcb
->control
.exit_info_2
&
2586 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2587 reason
= TASK_SWITCH_IRET
;
2588 else if (svm
->vmcb
->control
.exit_info_2
&
2589 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2590 reason
= TASK_SWITCH_JMP
;
2592 reason
= TASK_SWITCH_GATE
;
2594 reason
= TASK_SWITCH_CALL
;
2596 if (reason
== TASK_SWITCH_GATE
) {
2598 case SVM_EXITINTINFO_TYPE_NMI
:
2599 svm
->vcpu
.arch
.nmi_injected
= false;
2601 case SVM_EXITINTINFO_TYPE_EXEPT
:
2602 if (svm
->vmcb
->control
.exit_info_2
&
2603 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2604 has_error_code
= true;
2606 (u32
)svm
->vmcb
->control
.exit_info_2
;
2608 kvm_clear_exception_queue(&svm
->vcpu
);
2610 case SVM_EXITINTINFO_TYPE_INTR
:
2611 kvm_clear_interrupt_queue(&svm
->vcpu
);
2618 if (reason
!= TASK_SWITCH_GATE
||
2619 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2620 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2621 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2622 skip_emulated_instruction(&svm
->vcpu
);
2624 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2625 has_error_code
, error_code
) == EMULATE_FAIL
) {
2626 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2627 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2628 svm
->vcpu
.run
->internal
.ndata
= 0;
2634 static int cpuid_interception(struct vcpu_svm
*svm
)
2636 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2637 kvm_emulate_cpuid(&svm
->vcpu
);
2641 static int iret_interception(struct vcpu_svm
*svm
)
2643 ++svm
->vcpu
.stat
.nmi_window_exits
;
2644 clr_intercept(svm
, INTERCEPT_IRET
);
2645 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2649 static int invlpg_interception(struct vcpu_svm
*svm
)
2651 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2654 static int emulate_on_interception(struct vcpu_svm
*svm
)
2656 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2659 static int cr0_write_interception(struct vcpu_svm
*svm
)
2661 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2664 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2666 if (svm
->nested
.vmexit_rip
) {
2667 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2668 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2669 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2670 svm
->nested
.vmexit_rip
= 0;
2673 return r
== EMULATE_DONE
;
2676 static int cr8_write_interception(struct vcpu_svm
*svm
)
2678 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2681 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2682 /* instruction emulation calls kvm_set_cr8() */
2683 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2684 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2685 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2686 return r
== EMULATE_DONE
;
2688 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2689 return r
== EMULATE_DONE
;
2690 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2694 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2696 struct vcpu_svm
*svm
= to_svm(vcpu
);
2699 case MSR_IA32_TSC
: {
2700 struct vmcb
*vmcb
= get_host_vmcb(svm
);
2702 *data
= vmcb
->control
.tsc_offset
+ native_read_tsc();
2706 *data
= svm
->vmcb
->save
.star
;
2708 #ifdef CONFIG_X86_64
2710 *data
= svm
->vmcb
->save
.lstar
;
2713 *data
= svm
->vmcb
->save
.cstar
;
2715 case MSR_KERNEL_GS_BASE
:
2716 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2718 case MSR_SYSCALL_MASK
:
2719 *data
= svm
->vmcb
->save
.sfmask
;
2722 case MSR_IA32_SYSENTER_CS
:
2723 *data
= svm
->vmcb
->save
.sysenter_cs
;
2725 case MSR_IA32_SYSENTER_EIP
:
2726 *data
= svm
->sysenter_eip
;
2728 case MSR_IA32_SYSENTER_ESP
:
2729 *data
= svm
->sysenter_esp
;
2732 * Nobody will change the following 5 values in the VMCB so we can
2733 * safely return them on rdmsr. They will always be 0 until LBRV is
2736 case MSR_IA32_DEBUGCTLMSR
:
2737 *data
= svm
->vmcb
->save
.dbgctl
;
2739 case MSR_IA32_LASTBRANCHFROMIP
:
2740 *data
= svm
->vmcb
->save
.br_from
;
2742 case MSR_IA32_LASTBRANCHTOIP
:
2743 *data
= svm
->vmcb
->save
.br_to
;
2745 case MSR_IA32_LASTINTFROMIP
:
2746 *data
= svm
->vmcb
->save
.last_excp_from
;
2748 case MSR_IA32_LASTINTTOIP
:
2749 *data
= svm
->vmcb
->save
.last_excp_to
;
2751 case MSR_VM_HSAVE_PA
:
2752 *data
= svm
->nested
.hsave_msr
;
2755 *data
= svm
->nested
.vm_cr_msr
;
2757 case MSR_IA32_UCODE_REV
:
2761 return kvm_get_msr_common(vcpu
, ecx
, data
);
2766 static int rdmsr_interception(struct vcpu_svm
*svm
)
2768 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2771 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2772 trace_kvm_msr_read_ex(ecx
);
2773 kvm_inject_gp(&svm
->vcpu
, 0);
2775 trace_kvm_msr_read(ecx
, data
);
2777 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2778 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2779 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2780 skip_emulated_instruction(&svm
->vcpu
);
2785 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2787 struct vcpu_svm
*svm
= to_svm(vcpu
);
2788 int svm_dis
, chg_mask
;
2790 if (data
& ~SVM_VM_CR_VALID_MASK
)
2793 chg_mask
= SVM_VM_CR_VALID_MASK
;
2795 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2796 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2798 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2799 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2801 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2803 /* check for svm_disable while efer.svme is set */
2804 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2810 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2812 struct vcpu_svm
*svm
= to_svm(vcpu
);
2816 kvm_write_tsc(vcpu
, data
);
2819 svm
->vmcb
->save
.star
= data
;
2821 #ifdef CONFIG_X86_64
2823 svm
->vmcb
->save
.lstar
= data
;
2826 svm
->vmcb
->save
.cstar
= data
;
2828 case MSR_KERNEL_GS_BASE
:
2829 svm
->vmcb
->save
.kernel_gs_base
= data
;
2831 case MSR_SYSCALL_MASK
:
2832 svm
->vmcb
->save
.sfmask
= data
;
2835 case MSR_IA32_SYSENTER_CS
:
2836 svm
->vmcb
->save
.sysenter_cs
= data
;
2838 case MSR_IA32_SYSENTER_EIP
:
2839 svm
->sysenter_eip
= data
;
2840 svm
->vmcb
->save
.sysenter_eip
= data
;
2842 case MSR_IA32_SYSENTER_ESP
:
2843 svm
->sysenter_esp
= data
;
2844 svm
->vmcb
->save
.sysenter_esp
= data
;
2846 case MSR_IA32_DEBUGCTLMSR
:
2847 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2848 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2852 if (data
& DEBUGCTL_RESERVED_BITS
)
2855 svm
->vmcb
->save
.dbgctl
= data
;
2856 mark_dirty(svm
->vmcb
, VMCB_LBR
);
2857 if (data
& (1ULL<<0))
2858 svm_enable_lbrv(svm
);
2860 svm_disable_lbrv(svm
);
2862 case MSR_VM_HSAVE_PA
:
2863 svm
->nested
.hsave_msr
= data
;
2866 return svm_set_vm_cr(vcpu
, data
);
2868 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2871 return kvm_set_msr_common(vcpu
, ecx
, data
);
2876 static int wrmsr_interception(struct vcpu_svm
*svm
)
2878 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2879 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2880 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2883 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2884 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2885 trace_kvm_msr_write_ex(ecx
, data
);
2886 kvm_inject_gp(&svm
->vcpu
, 0);
2888 trace_kvm_msr_write(ecx
, data
);
2889 skip_emulated_instruction(&svm
->vcpu
);
2894 static int msr_interception(struct vcpu_svm
*svm
)
2896 if (svm
->vmcb
->control
.exit_info_1
)
2897 return wrmsr_interception(svm
);
2899 return rdmsr_interception(svm
);
2902 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2904 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2906 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2907 svm_clear_vintr(svm
);
2908 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2909 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2911 * If the user space waits to inject interrupts, exit as soon as
2914 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2915 kvm_run
->request_interrupt_window
&&
2916 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2917 ++svm
->vcpu
.stat
.irq_window_exits
;
2918 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2925 static int pause_interception(struct vcpu_svm
*svm
)
2927 kvm_vcpu_on_spin(&(svm
->vcpu
));
2931 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2932 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2933 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2934 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2935 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2936 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2937 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
2938 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2939 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2940 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2941 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2942 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2943 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2944 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2945 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2946 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2947 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2948 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2949 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2950 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2951 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2952 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2953 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2954 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2955 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2956 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2957 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2958 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2959 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2960 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2961 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2962 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2963 [SVM_EXIT_INTR
] = intr_interception
,
2964 [SVM_EXIT_NMI
] = nmi_interception
,
2965 [SVM_EXIT_SMI
] = nop_on_interception
,
2966 [SVM_EXIT_INIT
] = nop_on_interception
,
2967 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2968 [SVM_EXIT_CPUID
] = cpuid_interception
,
2969 [SVM_EXIT_IRET
] = iret_interception
,
2970 [SVM_EXIT_INVD
] = emulate_on_interception
,
2971 [SVM_EXIT_PAUSE
] = pause_interception
,
2972 [SVM_EXIT_HLT
] = halt_interception
,
2973 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2974 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2975 [SVM_EXIT_IOIO
] = io_interception
,
2976 [SVM_EXIT_MSR
] = msr_interception
,
2977 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2978 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2979 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2980 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2981 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2982 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2983 [SVM_EXIT_STGI
] = stgi_interception
,
2984 [SVM_EXIT_CLGI
] = clgi_interception
,
2985 [SVM_EXIT_SKINIT
] = skinit_interception
,
2986 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2987 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2988 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2989 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
2990 [SVM_EXIT_NPF
] = pf_interception
,
2993 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2995 struct vcpu_svm
*svm
= to_svm(vcpu
);
2996 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2997 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2999 pr_err("VMCB Control Area:\n");
3000 pr_err("cr_read: %04x\n", control
->intercept_cr
& 0xffff);
3001 pr_err("cr_write: %04x\n", control
->intercept_cr
>> 16);
3002 pr_err("dr_read: %04x\n", control
->intercept_dr
& 0xffff);
3003 pr_err("dr_write: %04x\n", control
->intercept_dr
>> 16);
3004 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
3005 pr_err("intercepts: %016llx\n", control
->intercept
);
3006 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
3007 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
3008 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
3009 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
3010 pr_err("asid: %d\n", control
->asid
);
3011 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
3012 pr_err("int_ctl: %08x\n", control
->int_ctl
);
3013 pr_err("int_vector: %08x\n", control
->int_vector
);
3014 pr_err("int_state: %08x\n", control
->int_state
);
3015 pr_err("exit_code: %08x\n", control
->exit_code
);
3016 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
3017 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
3018 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
3019 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
3020 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
3021 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
3022 pr_err("event_inj: %08x\n", control
->event_inj
);
3023 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
3024 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
3025 pr_err("next_rip: %016llx\n", control
->next_rip
);
3026 pr_err("VMCB State Save Area:\n");
3027 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3028 save
->es
.selector
, save
->es
.attrib
,
3029 save
->es
.limit
, save
->es
.base
);
3030 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3031 save
->cs
.selector
, save
->cs
.attrib
,
3032 save
->cs
.limit
, save
->cs
.base
);
3033 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3034 save
->ss
.selector
, save
->ss
.attrib
,
3035 save
->ss
.limit
, save
->ss
.base
);
3036 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3037 save
->ds
.selector
, save
->ds
.attrib
,
3038 save
->ds
.limit
, save
->ds
.base
);
3039 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3040 save
->fs
.selector
, save
->fs
.attrib
,
3041 save
->fs
.limit
, save
->fs
.base
);
3042 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3043 save
->gs
.selector
, save
->gs
.attrib
,
3044 save
->gs
.limit
, save
->gs
.base
);
3045 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3046 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3047 save
->gdtr
.limit
, save
->gdtr
.base
);
3048 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3049 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3050 save
->ldtr
.limit
, save
->ldtr
.base
);
3051 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3052 save
->idtr
.selector
, save
->idtr
.attrib
,
3053 save
->idtr
.limit
, save
->idtr
.base
);
3054 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3055 save
->tr
.selector
, save
->tr
.attrib
,
3056 save
->tr
.limit
, save
->tr
.base
);
3057 pr_err("cpl: %d efer: %016llx\n",
3058 save
->cpl
, save
->efer
);
3059 pr_err("cr0: %016llx cr2: %016llx\n",
3060 save
->cr0
, save
->cr2
);
3061 pr_err("cr3: %016llx cr4: %016llx\n",
3062 save
->cr3
, save
->cr4
);
3063 pr_err("dr6: %016llx dr7: %016llx\n",
3064 save
->dr6
, save
->dr7
);
3065 pr_err("rip: %016llx rflags: %016llx\n",
3066 save
->rip
, save
->rflags
);
3067 pr_err("rsp: %016llx rax: %016llx\n",
3068 save
->rsp
, save
->rax
);
3069 pr_err("star: %016llx lstar: %016llx\n",
3070 save
->star
, save
->lstar
);
3071 pr_err("cstar: %016llx sfmask: %016llx\n",
3072 save
->cstar
, save
->sfmask
);
3073 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3074 save
->kernel_gs_base
, save
->sysenter_cs
);
3075 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3076 save
->sysenter_esp
, save
->sysenter_eip
);
3077 pr_err("gpat: %016llx dbgctl: %016llx\n",
3078 save
->g_pat
, save
->dbgctl
);
3079 pr_err("br_from: %016llx br_to: %016llx\n",
3080 save
->br_from
, save
->br_to
);
3081 pr_err("excp_from: %016llx excp_to: %016llx\n",
3082 save
->last_excp_from
, save
->last_excp_to
);
3086 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3088 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3090 *info1
= control
->exit_info_1
;
3091 *info2
= control
->exit_info_2
;
3094 static int handle_exit(struct kvm_vcpu
*vcpu
)
3096 struct vcpu_svm
*svm
= to_svm(vcpu
);
3097 struct kvm_run
*kvm_run
= vcpu
->run
;
3098 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3100 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3102 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3103 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3105 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3107 if (unlikely(svm
->nested
.exit_required
)) {
3108 nested_svm_vmexit(svm
);
3109 svm
->nested
.exit_required
= false;
3114 if (is_guest_mode(vcpu
)) {
3117 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3118 svm
->vmcb
->control
.exit_info_1
,
3119 svm
->vmcb
->control
.exit_info_2
,
3120 svm
->vmcb
->control
.exit_int_info
,
3121 svm
->vmcb
->control
.exit_int_info_err
);
3123 vmexit
= nested_svm_exit_special(svm
);
3125 if (vmexit
== NESTED_EXIT_CONTINUE
)
3126 vmexit
= nested_svm_exit_handled(svm
);
3128 if (vmexit
== NESTED_EXIT_DONE
)
3132 svm_complete_interrupts(svm
);
3134 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3135 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3136 kvm_run
->fail_entry
.hardware_entry_failure_reason
3137 = svm
->vmcb
->control
.exit_code
;
3138 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3143 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3144 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3145 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3146 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3147 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3149 __func__
, svm
->vmcb
->control
.exit_int_info
,
3152 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3153 || !svm_exit_handlers
[exit_code
]) {
3154 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3155 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3159 return svm_exit_handlers
[exit_code
](svm
);
3162 static void reload_tss(struct kvm_vcpu
*vcpu
)
3164 int cpu
= raw_smp_processor_id();
3166 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3167 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3171 static void pre_svm_run(struct vcpu_svm
*svm
)
3173 int cpu
= raw_smp_processor_id();
3175 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3177 /* FIXME: handle wraparound of asid_generation */
3178 if (svm
->asid_generation
!= sd
->asid_generation
)
3182 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3184 struct vcpu_svm
*svm
= to_svm(vcpu
);
3186 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3187 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3188 set_intercept(svm
, INTERCEPT_IRET
);
3189 ++vcpu
->stat
.nmi_injections
;
3192 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3194 struct vmcb_control_area
*control
;
3196 control
= &svm
->vmcb
->control
;
3197 control
->int_vector
= irq
;
3198 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3199 control
->int_ctl
|= V_IRQ_MASK
|
3200 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3201 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3204 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3206 struct vcpu_svm
*svm
= to_svm(vcpu
);
3208 BUG_ON(!(gif_set(svm
)));
3210 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3211 ++vcpu
->stat
.irq_injections
;
3213 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3214 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3217 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3219 struct vcpu_svm
*svm
= to_svm(vcpu
);
3221 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3228 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3231 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3233 struct vcpu_svm
*svm
= to_svm(vcpu
);
3234 struct vmcb
*vmcb
= svm
->vmcb
;
3236 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3237 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3238 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3243 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3245 struct vcpu_svm
*svm
= to_svm(vcpu
);
3247 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3250 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3252 struct vcpu_svm
*svm
= to_svm(vcpu
);
3255 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3256 set_intercept(svm
, INTERCEPT_IRET
);
3258 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3259 clr_intercept(svm
, INTERCEPT_IRET
);
3263 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3265 struct vcpu_svm
*svm
= to_svm(vcpu
);
3266 struct vmcb
*vmcb
= svm
->vmcb
;
3269 if (!gif_set(svm
) ||
3270 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3273 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3275 if (is_guest_mode(vcpu
))
3276 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3281 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3283 struct vcpu_svm
*svm
= to_svm(vcpu
);
3286 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3287 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3288 * get that intercept, this function will be called again though and
3289 * we'll get the vintr intercept.
3291 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3293 svm_inject_irq(svm
, 0x0);
3297 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3299 struct vcpu_svm
*svm
= to_svm(vcpu
);
3301 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3303 return; /* IRET will cause a vm exit */
3306 * Something prevents NMI from been injected. Single step over possible
3307 * problem (IRET or exception injection or interrupt shadow)
3309 svm
->nmi_singlestep
= true;
3310 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3311 update_db_intercept(vcpu
);
3314 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3319 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3321 struct vcpu_svm
*svm
= to_svm(vcpu
);
3323 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3324 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3326 svm
->asid_generation
--;
3329 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3333 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3335 struct vcpu_svm
*svm
= to_svm(vcpu
);
3337 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3340 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3341 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3342 kvm_set_cr8(vcpu
, cr8
);
3346 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3348 struct vcpu_svm
*svm
= to_svm(vcpu
);
3351 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3354 cr8
= kvm_get_cr8(vcpu
);
3355 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3356 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3359 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3363 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3364 unsigned int3_injected
= svm
->int3_injected
;
3366 svm
->int3_injected
= 0;
3368 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) {
3369 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3370 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3373 svm
->vcpu
.arch
.nmi_injected
= false;
3374 kvm_clear_exception_queue(&svm
->vcpu
);
3375 kvm_clear_interrupt_queue(&svm
->vcpu
);
3377 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3380 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3382 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3383 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3386 case SVM_EXITINTINFO_TYPE_NMI
:
3387 svm
->vcpu
.arch
.nmi_injected
= true;
3389 case SVM_EXITINTINFO_TYPE_EXEPT
:
3391 * In case of software exceptions, do not reinject the vector,
3392 * but re-execute the instruction instead. Rewind RIP first
3393 * if we emulated INT3 before.
3395 if (kvm_exception_is_soft(vector
)) {
3396 if (vector
== BP_VECTOR
&& int3_injected
&&
3397 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3398 kvm_rip_write(&svm
->vcpu
,
3399 kvm_rip_read(&svm
->vcpu
) -
3403 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3404 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3405 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3408 kvm_requeue_exception(&svm
->vcpu
, vector
);
3410 case SVM_EXITINTINFO_TYPE_INTR
:
3411 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3418 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3420 struct vcpu_svm
*svm
= to_svm(vcpu
);
3421 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3423 control
->exit_int_info
= control
->event_inj
;
3424 control
->exit_int_info_err
= control
->event_inj_err
;
3425 control
->event_inj
= 0;
3426 svm_complete_interrupts(svm
);
3429 #ifdef CONFIG_X86_64
3435 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3437 struct vcpu_svm
*svm
= to_svm(vcpu
);
3439 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3440 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3441 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3444 * A vmexit emulation is required before the vcpu can be executed
3447 if (unlikely(svm
->nested
.exit_required
))
3452 sync_lapic_to_cr8(vcpu
);
3454 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3461 "push %%"R
"bp; \n\t"
3462 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3463 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3464 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3465 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3466 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3467 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3468 #ifdef CONFIG_X86_64
3469 "mov %c[r8](%[svm]), %%r8 \n\t"
3470 "mov %c[r9](%[svm]), %%r9 \n\t"
3471 "mov %c[r10](%[svm]), %%r10 \n\t"
3472 "mov %c[r11](%[svm]), %%r11 \n\t"
3473 "mov %c[r12](%[svm]), %%r12 \n\t"
3474 "mov %c[r13](%[svm]), %%r13 \n\t"
3475 "mov %c[r14](%[svm]), %%r14 \n\t"
3476 "mov %c[r15](%[svm]), %%r15 \n\t"
3479 /* Enter guest mode */
3481 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3482 __ex(SVM_VMLOAD
) "\n\t"
3483 __ex(SVM_VMRUN
) "\n\t"
3484 __ex(SVM_VMSAVE
) "\n\t"
3487 /* Save guest registers, load host registers */
3488 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3489 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3490 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3491 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3492 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3493 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3494 #ifdef CONFIG_X86_64
3495 "mov %%r8, %c[r8](%[svm]) \n\t"
3496 "mov %%r9, %c[r9](%[svm]) \n\t"
3497 "mov %%r10, %c[r10](%[svm]) \n\t"
3498 "mov %%r11, %c[r11](%[svm]) \n\t"
3499 "mov %%r12, %c[r12](%[svm]) \n\t"
3500 "mov %%r13, %c[r13](%[svm]) \n\t"
3501 "mov %%r14, %c[r14](%[svm]) \n\t"
3502 "mov %%r15, %c[r15](%[svm]) \n\t"
3507 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3508 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3509 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3510 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3511 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3512 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3513 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3514 #ifdef CONFIG_X86_64
3515 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3516 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3517 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3518 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3519 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3520 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3521 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3522 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3525 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3526 #ifdef CONFIG_X86_64
3527 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3531 #ifdef CONFIG_X86_64
3532 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3534 loadsegment(fs
, svm
->host
.fs
);
3539 local_irq_disable();
3543 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3544 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3545 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3546 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3548 sync_cr8_to_lapic(vcpu
);
3552 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3554 /* if exit due to PF check for async PF */
3555 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3556 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3559 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3560 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3564 * We need to handle MC intercepts here before the vcpu has a chance to
3565 * change the physical cpu
3567 if (unlikely(svm
->vmcb
->control
.exit_code
==
3568 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3569 svm_handle_mce(svm
);
3571 mark_all_clean(svm
->vmcb
);
3576 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3578 struct vcpu_svm
*svm
= to_svm(vcpu
);
3580 svm
->vmcb
->save
.cr3
= root
;
3581 mark_dirty(svm
->vmcb
, VMCB_CR
);
3582 svm_flush_tlb(vcpu
);
3585 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3587 struct vcpu_svm
*svm
= to_svm(vcpu
);
3589 svm
->vmcb
->control
.nested_cr3
= root
;
3590 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3592 /* Also sync guest cr3 here in case we live migrate */
3593 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3594 mark_dirty(svm
->vmcb
, VMCB_CR
);
3596 svm_flush_tlb(vcpu
);
3599 static int is_disabled(void)
3603 rdmsrl(MSR_VM_CR
, vm_cr
);
3604 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3611 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3614 * Patch in the VMMCALL instruction:
3616 hypercall
[0] = 0x0f;
3617 hypercall
[1] = 0x01;
3618 hypercall
[2] = 0xd9;
3621 static void svm_check_processor_compat(void *rtn
)
3626 static bool svm_cpu_has_accelerated_tpr(void)
3631 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3636 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3640 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3645 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3648 entry
->eax
= 1; /* SVM revision 1 */
3649 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3650 ASID emulation to nested SVM */
3651 entry
->ecx
= 0; /* Reserved */
3652 entry
->edx
= 0; /* Per default do not support any
3653 additional features */
3655 /* Support next_rip if host supports it */
3656 if (boot_cpu_has(X86_FEATURE_NRIPS
))
3657 entry
->edx
|= SVM_FEATURE_NRIP
;
3659 /* Support NPT for the guest if enabled */
3661 entry
->edx
|= SVM_FEATURE_NPT
;
3667 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3668 { SVM_EXIT_READ_CR0
, "read_cr0" },
3669 { SVM_EXIT_READ_CR3
, "read_cr3" },
3670 { SVM_EXIT_READ_CR4
, "read_cr4" },
3671 { SVM_EXIT_READ_CR8
, "read_cr8" },
3672 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3673 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3674 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3675 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3676 { SVM_EXIT_READ_DR0
, "read_dr0" },
3677 { SVM_EXIT_READ_DR1
, "read_dr1" },
3678 { SVM_EXIT_READ_DR2
, "read_dr2" },
3679 { SVM_EXIT_READ_DR3
, "read_dr3" },
3680 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3681 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3682 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3683 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3684 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3685 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3686 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3687 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3688 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3689 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3690 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3691 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3692 { SVM_EXIT_INTR
, "interrupt" },
3693 { SVM_EXIT_NMI
, "nmi" },
3694 { SVM_EXIT_SMI
, "smi" },
3695 { SVM_EXIT_INIT
, "init" },
3696 { SVM_EXIT_VINTR
, "vintr" },
3697 { SVM_EXIT_CPUID
, "cpuid" },
3698 { SVM_EXIT_INVD
, "invd" },
3699 { SVM_EXIT_HLT
, "hlt" },
3700 { SVM_EXIT_INVLPG
, "invlpg" },
3701 { SVM_EXIT_INVLPGA
, "invlpga" },
3702 { SVM_EXIT_IOIO
, "io" },
3703 { SVM_EXIT_MSR
, "msr" },
3704 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3705 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3706 { SVM_EXIT_VMRUN
, "vmrun" },
3707 { SVM_EXIT_VMMCALL
, "hypercall" },
3708 { SVM_EXIT_VMLOAD
, "vmload" },
3709 { SVM_EXIT_VMSAVE
, "vmsave" },
3710 { SVM_EXIT_STGI
, "stgi" },
3711 { SVM_EXIT_CLGI
, "clgi" },
3712 { SVM_EXIT_SKINIT
, "skinit" },
3713 { SVM_EXIT_WBINVD
, "wbinvd" },
3714 { SVM_EXIT_MONITOR
, "monitor" },
3715 { SVM_EXIT_MWAIT
, "mwait" },
3716 { SVM_EXIT_XSETBV
, "xsetbv" },
3717 { SVM_EXIT_NPF
, "npf" },
3721 static int svm_get_lpage_level(void)
3723 return PT_PDPE_LEVEL
;
3726 static bool svm_rdtscp_supported(void)
3731 static bool svm_has_wbinvd_exit(void)
3736 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3738 struct vcpu_svm
*svm
= to_svm(vcpu
);
3740 set_exception_intercept(svm
, NM_VECTOR
);
3741 update_cr0_intercept(svm
);
3744 static struct kvm_x86_ops svm_x86_ops
= {
3745 .cpu_has_kvm_support
= has_svm
,
3746 .disabled_by_bios
= is_disabled
,
3747 .hardware_setup
= svm_hardware_setup
,
3748 .hardware_unsetup
= svm_hardware_unsetup
,
3749 .check_processor_compatibility
= svm_check_processor_compat
,
3750 .hardware_enable
= svm_hardware_enable
,
3751 .hardware_disable
= svm_hardware_disable
,
3752 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3754 .vcpu_create
= svm_create_vcpu
,
3755 .vcpu_free
= svm_free_vcpu
,
3756 .vcpu_reset
= svm_vcpu_reset
,
3758 .prepare_guest_switch
= svm_prepare_guest_switch
,
3759 .vcpu_load
= svm_vcpu_load
,
3760 .vcpu_put
= svm_vcpu_put
,
3762 .set_guest_debug
= svm_guest_debug
,
3763 .get_msr
= svm_get_msr
,
3764 .set_msr
= svm_set_msr
,
3765 .get_segment_base
= svm_get_segment_base
,
3766 .get_segment
= svm_get_segment
,
3767 .set_segment
= svm_set_segment
,
3768 .get_cpl
= svm_get_cpl
,
3769 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3770 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3771 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3772 .set_cr0
= svm_set_cr0
,
3773 .set_cr3
= svm_set_cr3
,
3774 .set_cr4
= svm_set_cr4
,
3775 .set_efer
= svm_set_efer
,
3776 .get_idt
= svm_get_idt
,
3777 .set_idt
= svm_set_idt
,
3778 .get_gdt
= svm_get_gdt
,
3779 .set_gdt
= svm_set_gdt
,
3780 .set_dr7
= svm_set_dr7
,
3781 .cache_reg
= svm_cache_reg
,
3782 .get_rflags
= svm_get_rflags
,
3783 .set_rflags
= svm_set_rflags
,
3784 .fpu_activate
= svm_fpu_activate
,
3785 .fpu_deactivate
= svm_fpu_deactivate
,
3787 .tlb_flush
= svm_flush_tlb
,
3789 .run
= svm_vcpu_run
,
3790 .handle_exit
= handle_exit
,
3791 .skip_emulated_instruction
= skip_emulated_instruction
,
3792 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3793 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3794 .patch_hypercall
= svm_patch_hypercall
,
3795 .set_irq
= svm_set_irq
,
3796 .set_nmi
= svm_inject_nmi
,
3797 .queue_exception
= svm_queue_exception
,
3798 .cancel_injection
= svm_cancel_injection
,
3799 .interrupt_allowed
= svm_interrupt_allowed
,
3800 .nmi_allowed
= svm_nmi_allowed
,
3801 .get_nmi_mask
= svm_get_nmi_mask
,
3802 .set_nmi_mask
= svm_set_nmi_mask
,
3803 .enable_nmi_window
= enable_nmi_window
,
3804 .enable_irq_window
= enable_irq_window
,
3805 .update_cr8_intercept
= update_cr8_intercept
,
3807 .set_tss_addr
= svm_set_tss_addr
,
3808 .get_tdp_level
= get_npt_level
,
3809 .get_mt_mask
= svm_get_mt_mask
,
3811 .get_exit_info
= svm_get_exit_info
,
3812 .exit_reasons_str
= svm_exit_reasons_str
,
3814 .get_lpage_level
= svm_get_lpage_level
,
3816 .cpuid_update
= svm_cpuid_update
,
3818 .rdtscp_supported
= svm_rdtscp_supported
,
3820 .set_supported_cpuid
= svm_set_supported_cpuid
,
3822 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3824 .write_tsc_offset
= svm_write_tsc_offset
,
3825 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3827 .set_tdp_cr3
= set_tdp_cr3
,
3830 static int __init
svm_init(void)
3832 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3833 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3836 static void __exit
svm_exit(void)
3841 module_init(svm_init
)
3842 module_exit(svm_exit
)