2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
41 #include <asm/perf_event.h>
42 #include <asm/tlbflush.h>
44 #include <asm/debugreg.h>
45 #include <asm/kvm_para.h>
46 #include <asm/irq_remapping.h>
48 #include <asm/virtext.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id svm_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
60 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
62 #define IOPM_ALLOC_ORDER 2
63 #define MSRPM_ALLOC_ORDER 1
65 #define SEG_TYPE_LDT 2
66 #define SEG_TYPE_BUSY_TSS16 3
68 #define SVM_FEATURE_NPT (1 << 0)
69 #define SVM_FEATURE_LBRV (1 << 1)
70 #define SVM_FEATURE_SVML (1 << 2)
71 #define SVM_FEATURE_NRIP (1 << 3)
72 #define SVM_FEATURE_TSC_RATE (1 << 4)
73 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
74 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
75 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
76 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78 #define SVM_AVIC_DOORBELL 0xc001011b
80 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
81 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
82 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
87 #define TSC_RATIO_MIN 0x0000000000000001ULL
88 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
93 * 0xff is broadcast, so the max index allowed for physical APIC ID
94 * table is 0xfe. APIC IDs above 0xff are reserved.
96 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
99 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
100 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102 /* AVIC GATAG is encoded using VM and VCPU IDs */
103 #define AVIC_VCPU_ID_BITS 8
104 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106 #define AVIC_VM_ID_BITS 24
107 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
108 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
111 (y & AVIC_VCPU_ID_MASK))
112 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
113 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115 static bool erratum_383_found __read_mostly
;
117 static const u32 host_save_user_msrs
[] = {
119 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
122 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
126 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130 struct nested_state
{
136 /* These are the merged vectors */
139 /* gpa pointers to the real vectors */
143 /* A VMEXIT is required but not yet emulated */
146 /* cache for intercepts of the guest */
149 u32 intercept_exceptions
;
152 /* Nested Paging related state */
156 #define MSRPM_OFFSETS 16
157 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
160 * Set osvw_len to higher value when updated Revision Guides
161 * are published and we know what the new status bits are
163 static uint64_t osvw_len
= 4, osvw_status
;
166 struct kvm_vcpu vcpu
;
168 unsigned long vmcb_pa
;
169 struct svm_cpu_data
*svm_data
;
170 uint64_t asid_generation
;
171 uint64_t sysenter_esp
;
172 uint64_t sysenter_eip
;
177 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
189 struct nested_state nested
;
193 unsigned int3_injected
;
194 unsigned long int3_rip
;
197 /* cached guest cpuid flags for faster access */
198 bool nrips_enabled
: 1;
201 struct page
*avic_backing_page
;
202 u64
*avic_physical_id_cache
;
203 bool avic_is_running
;
206 * Per-vcpu list of struct amd_svm_iommu_ir:
207 * This is used mainly to store interrupt remapping information used
208 * when update the vcpu affinity. This avoids the need to scan for
209 * IRTE and try to match ga_tag in the IOMMU driver.
211 struct list_head ir_list
;
212 spinlock_t ir_list_lock
;
216 * This is a wrapper of struct amd_iommu_ir_data.
218 struct amd_svm_iommu_ir
{
219 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
220 void *data
; /* Storing pointer to struct amd_ir_data */
223 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
224 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
227 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
228 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
229 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
232 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234 #define MSR_INVALID 0xffffffffU
236 static const struct svm_direct_access_msrs
{
237 u32 index
; /* Index of the MSR */
238 bool always
; /* True if intercept is always on */
239 } direct_access_msrs
[] = {
240 { .index
= MSR_STAR
, .always
= true },
241 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
243 { .index
= MSR_GS_BASE
, .always
= true },
244 { .index
= MSR_FS_BASE
, .always
= true },
245 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
246 { .index
= MSR_LSTAR
, .always
= true },
247 { .index
= MSR_CSTAR
, .always
= true },
248 { .index
= MSR_SYSCALL_MASK
, .always
= true },
250 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
251 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
252 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
253 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
254 { .index
= MSR_INVALID
, .always
= false },
257 /* enable NPT for AMD64 and X86 with PAE */
258 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
259 static bool npt_enabled
= true;
261 static bool npt_enabled
;
264 /* allow nested paging (virtualized MMU) for all guests */
265 static int npt
= true;
266 module_param(npt
, int, S_IRUGO
);
268 /* allow nested virtualization in KVM/SVM */
269 static int nested
= true;
270 module_param(nested
, int, S_IRUGO
);
272 /* enable / disable AVIC */
274 #ifdef CONFIG_X86_LOCAL_APIC
275 module_param(avic
, int, S_IRUGO
);
278 /* AVIC VM ID bit masks and lock */
279 static DECLARE_BITMAP(avic_vm_id_bitmap
, AVIC_VM_ID_NR
);
280 static DEFINE_SPINLOCK(avic_vm_id_lock
);
282 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
283 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
284 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
286 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
287 static int nested_svm_intercept(struct vcpu_svm
*svm
);
288 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
289 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
290 bool has_error_code
, u32 error_code
);
293 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
294 pause filter count */
295 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
296 VMCB_ASID
, /* ASID */
297 VMCB_INTR
, /* int_ctl, int_vector */
298 VMCB_NPT
, /* npt_en, nCR3, gPAT */
299 VMCB_CR
, /* CR0, CR3, CR4, EFER */
300 VMCB_DR
, /* DR6, DR7 */
301 VMCB_DT
, /* GDT, IDT */
302 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
303 VMCB_CR2
, /* CR2 only */
304 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
305 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
306 * AVIC PHYSICAL_TABLE pointer,
307 * AVIC LOGICAL_TABLE pointer
312 /* TPR and CR2 are always written before VMRUN */
313 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
315 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
317 static inline void mark_all_dirty(struct vmcb
*vmcb
)
319 vmcb
->control
.clean
= 0;
322 static inline void mark_all_clean(struct vmcb
*vmcb
)
324 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
325 & ~VMCB_ALWAYS_DIRTY_MASK
;
328 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
330 vmcb
->control
.clean
&= ~(1 << bit
);
333 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
335 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
338 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
340 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
341 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
344 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
346 struct vcpu_svm
*svm
= to_svm(vcpu
);
347 u64
*entry
= svm
->avic_physical_id_cache
;
352 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
355 static void recalc_intercepts(struct vcpu_svm
*svm
)
357 struct vmcb_control_area
*c
, *h
;
358 struct nested_state
*g
;
360 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
362 if (!is_guest_mode(&svm
->vcpu
))
365 c
= &svm
->vmcb
->control
;
366 h
= &svm
->nested
.hsave
->control
;
369 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
370 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
371 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
372 c
->intercept
= h
->intercept
| g
->intercept
;
375 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
377 if (is_guest_mode(&svm
->vcpu
))
378 return svm
->nested
.hsave
;
383 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
385 struct vmcb
*vmcb
= get_host_vmcb(svm
);
387 vmcb
->control
.intercept_cr
|= (1U << bit
);
389 recalc_intercepts(svm
);
392 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
394 struct vmcb
*vmcb
= get_host_vmcb(svm
);
396 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
398 recalc_intercepts(svm
);
401 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
403 struct vmcb
*vmcb
= get_host_vmcb(svm
);
405 return vmcb
->control
.intercept_cr
& (1U << bit
);
408 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
410 struct vmcb
*vmcb
= get_host_vmcb(svm
);
412 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
413 | (1 << INTERCEPT_DR1_READ
)
414 | (1 << INTERCEPT_DR2_READ
)
415 | (1 << INTERCEPT_DR3_READ
)
416 | (1 << INTERCEPT_DR4_READ
)
417 | (1 << INTERCEPT_DR5_READ
)
418 | (1 << INTERCEPT_DR6_READ
)
419 | (1 << INTERCEPT_DR7_READ
)
420 | (1 << INTERCEPT_DR0_WRITE
)
421 | (1 << INTERCEPT_DR1_WRITE
)
422 | (1 << INTERCEPT_DR2_WRITE
)
423 | (1 << INTERCEPT_DR3_WRITE
)
424 | (1 << INTERCEPT_DR4_WRITE
)
425 | (1 << INTERCEPT_DR5_WRITE
)
426 | (1 << INTERCEPT_DR6_WRITE
)
427 | (1 << INTERCEPT_DR7_WRITE
);
429 recalc_intercepts(svm
);
432 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
434 struct vmcb
*vmcb
= get_host_vmcb(svm
);
436 vmcb
->control
.intercept_dr
= 0;
438 recalc_intercepts(svm
);
441 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
443 struct vmcb
*vmcb
= get_host_vmcb(svm
);
445 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
447 recalc_intercepts(svm
);
450 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
452 struct vmcb
*vmcb
= get_host_vmcb(svm
);
454 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
456 recalc_intercepts(svm
);
459 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
461 struct vmcb
*vmcb
= get_host_vmcb(svm
);
463 vmcb
->control
.intercept
|= (1ULL << bit
);
465 recalc_intercepts(svm
);
468 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
470 struct vmcb
*vmcb
= get_host_vmcb(svm
);
472 vmcb
->control
.intercept
&= ~(1ULL << bit
);
474 recalc_intercepts(svm
);
477 static inline void enable_gif(struct vcpu_svm
*svm
)
479 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
482 static inline void disable_gif(struct vcpu_svm
*svm
)
484 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
487 static inline bool gif_set(struct vcpu_svm
*svm
)
489 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
492 static unsigned long iopm_base
;
494 struct kvm_ldttss_desc
{
497 unsigned base1
:8, type
:5, dpl
:2, p
:1;
498 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
501 } __attribute__((packed
));
503 struct svm_cpu_data
{
509 struct kvm_ldttss_desc
*tss_desc
;
511 struct page
*save_area
;
514 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
516 struct svm_init_data
{
521 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
523 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
524 #define MSRS_RANGE_SIZE 2048
525 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
527 static u32
svm_msrpm_offset(u32 msr
)
532 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
533 if (msr
< msrpm_ranges
[i
] ||
534 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
537 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
538 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
540 /* Now we have the u8 offset - but need the u32 offset */
544 /* MSR not in any range */
548 #define MAX_INST_SIZE 15
550 static inline void clgi(void)
552 asm volatile (__ex(SVM_CLGI
));
555 static inline void stgi(void)
557 asm volatile (__ex(SVM_STGI
));
560 static inline void invlpga(unsigned long addr
, u32 asid
)
562 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
565 static int get_npt_level(void)
568 return PT64_ROOT_LEVEL
;
570 return PT32E_ROOT_LEVEL
;
574 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
576 vcpu
->arch
.efer
= efer
;
577 if (!npt_enabled
&& !(efer
& EFER_LMA
))
580 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
581 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
584 static int is_external_interrupt(u32 info
)
586 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
587 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
590 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
592 struct vcpu_svm
*svm
= to_svm(vcpu
);
595 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
596 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
600 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
602 struct vcpu_svm
*svm
= to_svm(vcpu
);
605 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
607 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
611 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
613 struct vcpu_svm
*svm
= to_svm(vcpu
);
615 if (svm
->vmcb
->control
.next_rip
!= 0) {
616 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
617 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
620 if (!svm
->next_rip
) {
621 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
623 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
626 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
627 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
628 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
630 kvm_rip_write(vcpu
, svm
->next_rip
);
631 svm_set_interrupt_shadow(vcpu
, 0);
634 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
635 bool has_error_code
, u32 error_code
,
638 struct vcpu_svm
*svm
= to_svm(vcpu
);
641 * If we are within a nested VM we'd better #VMEXIT and let the guest
642 * handle the exception
645 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
648 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
649 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
652 * For guest debugging where we have to reinject #BP if some
653 * INT3 is guest-owned:
654 * Emulate nRIP by moving RIP forward. Will fail if injection
655 * raises a fault that is not intercepted. Still better than
656 * failing in all cases.
658 skip_emulated_instruction(&svm
->vcpu
);
659 rip
= kvm_rip_read(&svm
->vcpu
);
660 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
661 svm
->int3_injected
= rip
- old_rip
;
664 svm
->vmcb
->control
.event_inj
= nr
666 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
667 | SVM_EVTINJ_TYPE_EXEPT
;
668 svm
->vmcb
->control
.event_inj_err
= error_code
;
671 static void svm_init_erratum_383(void)
677 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
680 /* Use _safe variants to not break nested virtualization */
681 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
687 low
= lower_32_bits(val
);
688 high
= upper_32_bits(val
);
690 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
692 erratum_383_found
= true;
695 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
698 * Guests should see errata 400 and 415 as fixed (assuming that
699 * HLT and IO instructions are intercepted).
701 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
702 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
705 * By increasing VCPU's osvw.length to 3 we are telling the guest that
706 * all osvw.status bits inside that length, including bit 0 (which is
707 * reserved for erratum 298), are valid. However, if host processor's
708 * osvw_len is 0 then osvw_status[0] carries no information. We need to
709 * be conservative here and therefore we tell the guest that erratum 298
710 * is present (because we really don't know).
712 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
713 vcpu
->arch
.osvw
.status
|= 1;
716 static int has_svm(void)
720 if (!cpu_has_svm(&msg
)) {
721 printk(KERN_INFO
"has_svm: %s\n", msg
);
728 static void svm_hardware_disable(void)
730 /* Make sure we clean up behind us */
731 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
732 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
736 amd_pmu_disable_virt();
739 static int svm_hardware_enable(void)
742 struct svm_cpu_data
*sd
;
744 struct desc_ptr gdt_descr
;
745 struct desc_struct
*gdt
;
746 int me
= raw_smp_processor_id();
748 rdmsrl(MSR_EFER
, efer
);
749 if (efer
& EFER_SVME
)
753 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
756 sd
= per_cpu(svm_data
, me
);
758 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
762 sd
->asid_generation
= 1;
763 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
764 sd
->next_asid
= sd
->max_asid
+ 1;
766 native_store_gdt(&gdt_descr
);
767 gdt
= (struct desc_struct
*)gdt_descr
.address
;
768 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
770 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
772 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
774 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
775 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
776 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
783 * Note that it is possible to have a system with mixed processor
784 * revisions and therefore different OSVW bits. If bits are not the same
785 * on different processors then choose the worst case (i.e. if erratum
786 * is present on one processor and not on another then assume that the
787 * erratum is present everywhere).
789 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
790 uint64_t len
, status
= 0;
793 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
795 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
799 osvw_status
= osvw_len
= 0;
803 osvw_status
|= status
;
804 osvw_status
&= (1ULL << osvw_len
) - 1;
807 osvw_status
= osvw_len
= 0;
809 svm_init_erratum_383();
811 amd_pmu_enable_virt();
816 static void svm_cpu_uninit(int cpu
)
818 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
823 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
824 __free_page(sd
->save_area
);
828 static int svm_cpu_init(int cpu
)
830 struct svm_cpu_data
*sd
;
833 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
837 sd
->save_area
= alloc_page(GFP_KERNEL
);
842 per_cpu(svm_data
, cpu
) = sd
;
852 static bool valid_msr_intercept(u32 index
)
856 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
857 if (direct_access_msrs
[i
].index
== index
)
863 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
866 u8 bit_read
, bit_write
;
871 * If this warning triggers extend the direct_access_msrs list at the
872 * beginning of the file
874 WARN_ON(!valid_msr_intercept(msr
));
876 offset
= svm_msrpm_offset(msr
);
877 bit_read
= 2 * (msr
& 0x0f);
878 bit_write
= 2 * (msr
& 0x0f) + 1;
881 BUG_ON(offset
== MSR_INVALID
);
883 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
884 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
889 static void svm_vcpu_init_msrpm(u32
*msrpm
)
893 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
895 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
896 if (!direct_access_msrs
[i
].always
)
899 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
903 static void add_msr_offset(u32 offset
)
907 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
909 /* Offset already in list? */
910 if (msrpm_offsets
[i
] == offset
)
913 /* Slot used by another offset? */
914 if (msrpm_offsets
[i
] != MSR_INVALID
)
917 /* Add offset to list */
918 msrpm_offsets
[i
] = offset
;
924 * If this BUG triggers the msrpm_offsets table has an overflow. Just
925 * increase MSRPM_OFFSETS in this case.
930 static void init_msrpm_offsets(void)
934 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
936 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
939 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
940 BUG_ON(offset
== MSR_INVALID
);
942 add_msr_offset(offset
);
946 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
948 u32
*msrpm
= svm
->msrpm
;
950 svm
->vmcb
->control
.lbr_ctl
= 1;
951 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
952 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
953 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
954 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
957 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
959 u32
*msrpm
= svm
->msrpm
;
961 svm
->vmcb
->control
.lbr_ctl
= 0;
962 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
963 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
964 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
965 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
969 * This hash table is used to map VM_ID to a struct kvm_arch,
970 * when handling AMD IOMMU GALOG notification to schedule in
973 #define SVM_VM_DATA_HASH_BITS 8
974 DECLARE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
975 static spinlock_t svm_vm_data_hash_lock
;
978 * This function is called from IOMMU driver to notify
979 * SVM to schedule in a particular vCPU of a particular VM.
981 static int avic_ga_log_notifier(u32 ga_tag
)
984 struct kvm_arch
*ka
= NULL
;
985 struct kvm_vcpu
*vcpu
= NULL
;
986 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
987 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
989 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
991 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
992 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
993 struct kvm
*kvm
= container_of(ka
, struct kvm
, arch
);
994 struct kvm_arch
*vm_data
= &kvm
->arch
;
996 if (vm_data
->avic_vm_id
!= vm_id
)
998 vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
1001 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1007 * At this point, the IOMMU should have already set the pending
1008 * bit in the vAPIC backing page. So, we just need to schedule
1011 if (vcpu
->mode
== OUTSIDE_GUEST_MODE
)
1012 kvm_vcpu_wake_up(vcpu
);
1017 static __init
int svm_hardware_setup(void)
1020 struct page
*iopm_pages
;
1024 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1029 iopm_va
= page_address(iopm_pages
);
1030 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1031 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1033 init_msrpm_offsets();
1035 if (boot_cpu_has(X86_FEATURE_NX
))
1036 kvm_enable_efer_bits(EFER_NX
);
1038 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1039 kvm_enable_efer_bits(EFER_FFXSR
);
1041 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1042 kvm_has_tsc_control
= true;
1043 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1044 kvm_tsc_scaling_ratio_frac_bits
= 32;
1048 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1049 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1052 for_each_possible_cpu(cpu
) {
1053 r
= svm_cpu_init(cpu
);
1058 if (!boot_cpu_has(X86_FEATURE_NPT
))
1059 npt_enabled
= false;
1061 if (npt_enabled
&& !npt
) {
1062 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1063 npt_enabled
= false;
1067 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1074 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1075 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1078 pr_info("AVIC enabled\n");
1080 hash_init(svm_vm_data_hash
);
1081 spin_lock_init(&svm_vm_data_hash_lock
);
1082 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1089 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1094 static __exit
void svm_hardware_unsetup(void)
1098 for_each_possible_cpu(cpu
)
1099 svm_cpu_uninit(cpu
);
1101 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1105 static void init_seg(struct vmcb_seg
*seg
)
1108 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1109 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1110 seg
->limit
= 0xffff;
1114 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1117 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1118 seg
->limit
= 0xffff;
1122 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1124 struct vcpu_svm
*svm
= to_svm(vcpu
);
1125 u64 g_tsc_offset
= 0;
1127 if (is_guest_mode(vcpu
)) {
1128 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1129 svm
->nested
.hsave
->control
.tsc_offset
;
1130 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1132 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1133 svm
->vmcb
->control
.tsc_offset
,
1136 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1138 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1141 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1143 struct vmcb
*vmcb
= svm
->vmcb
;
1144 struct kvm_arch
*vm_data
= &svm
->vcpu
.kvm
->arch
;
1145 phys_addr_t bpa
= page_to_phys(svm
->avic_backing_page
);
1146 phys_addr_t lpa
= page_to_phys(vm_data
->avic_logical_id_table_page
);
1147 phys_addr_t ppa
= page_to_phys(vm_data
->avic_physical_id_table_page
);
1149 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1150 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1151 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1152 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1153 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1154 svm
->vcpu
.arch
.apicv_active
= true;
1157 static void init_vmcb(struct vcpu_svm
*svm
)
1159 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1160 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1162 svm
->vcpu
.fpu_active
= 1;
1163 svm
->vcpu
.arch
.hflags
= 0;
1165 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1166 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1167 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1168 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1169 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1170 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1171 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1172 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1174 set_dr_intercepts(svm
);
1176 set_exception_intercept(svm
, PF_VECTOR
);
1177 set_exception_intercept(svm
, UD_VECTOR
);
1178 set_exception_intercept(svm
, MC_VECTOR
);
1179 set_exception_intercept(svm
, AC_VECTOR
);
1180 set_exception_intercept(svm
, DB_VECTOR
);
1182 set_intercept(svm
, INTERCEPT_INTR
);
1183 set_intercept(svm
, INTERCEPT_NMI
);
1184 set_intercept(svm
, INTERCEPT_SMI
);
1185 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1186 set_intercept(svm
, INTERCEPT_RDPMC
);
1187 set_intercept(svm
, INTERCEPT_CPUID
);
1188 set_intercept(svm
, INTERCEPT_INVD
);
1189 set_intercept(svm
, INTERCEPT_HLT
);
1190 set_intercept(svm
, INTERCEPT_INVLPG
);
1191 set_intercept(svm
, INTERCEPT_INVLPGA
);
1192 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1193 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1194 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1195 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1196 set_intercept(svm
, INTERCEPT_VMRUN
);
1197 set_intercept(svm
, INTERCEPT_VMMCALL
);
1198 set_intercept(svm
, INTERCEPT_VMLOAD
);
1199 set_intercept(svm
, INTERCEPT_VMSAVE
);
1200 set_intercept(svm
, INTERCEPT_STGI
);
1201 set_intercept(svm
, INTERCEPT_CLGI
);
1202 set_intercept(svm
, INTERCEPT_SKINIT
);
1203 set_intercept(svm
, INTERCEPT_WBINVD
);
1204 set_intercept(svm
, INTERCEPT_MONITOR
);
1205 set_intercept(svm
, INTERCEPT_MWAIT
);
1206 set_intercept(svm
, INTERCEPT_XSETBV
);
1208 control
->iopm_base_pa
= iopm_base
;
1209 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1210 control
->int_ctl
= V_INTR_MASKING_MASK
;
1212 init_seg(&save
->es
);
1213 init_seg(&save
->ss
);
1214 init_seg(&save
->ds
);
1215 init_seg(&save
->fs
);
1216 init_seg(&save
->gs
);
1218 save
->cs
.selector
= 0xf000;
1219 save
->cs
.base
= 0xffff0000;
1220 /* Executable/Readable Code Segment */
1221 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1222 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1223 save
->cs
.limit
= 0xffff;
1225 save
->gdtr
.limit
= 0xffff;
1226 save
->idtr
.limit
= 0xffff;
1228 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1229 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1231 svm_set_efer(&svm
->vcpu
, 0);
1232 save
->dr6
= 0xffff0ff0;
1233 kvm_set_rflags(&svm
->vcpu
, 2);
1234 save
->rip
= 0x0000fff0;
1235 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1238 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1239 * It also updates the guest-visible cr0 value.
1241 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1242 kvm_mmu_reset_context(&svm
->vcpu
);
1244 save
->cr4
= X86_CR4_PAE
;
1248 /* Setup VMCB for Nested Paging */
1249 control
->nested_ctl
= 1;
1250 clr_intercept(svm
, INTERCEPT_INVLPG
);
1251 clr_exception_intercept(svm
, PF_VECTOR
);
1252 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1253 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1254 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1258 svm
->asid_generation
= 0;
1260 svm
->nested
.vmcb
= 0;
1261 svm
->vcpu
.arch
.hflags
= 0;
1263 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1264 control
->pause_filter_count
= 3000;
1265 set_intercept(svm
, INTERCEPT_PAUSE
);
1269 avic_init_vmcb(svm
);
1271 mark_all_dirty(svm
->vmcb
);
1277 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
, int index
)
1279 u64
*avic_physical_id_table
;
1280 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
1282 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1285 avic_physical_id_table
= page_address(vm_data
->avic_physical_id_table_page
);
1287 return &avic_physical_id_table
[index
];
1292 * AVIC hardware walks the nested page table to check permissions,
1293 * but does not use the SPA address specified in the leaf page
1294 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1295 * field of the VMCB. Therefore, we set up the
1296 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1298 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1300 struct kvm
*kvm
= vcpu
->kvm
;
1303 if (kvm
->arch
.apic_access_page_done
)
1306 ret
= x86_set_memory_region(kvm
,
1307 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1308 APIC_DEFAULT_PHYS_BASE
,
1313 kvm
->arch
.apic_access_page_done
= true;
1317 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1320 u64
*entry
, new_entry
;
1321 int id
= vcpu
->vcpu_id
;
1322 struct vcpu_svm
*svm
= to_svm(vcpu
);
1324 ret
= avic_init_access_page(vcpu
);
1328 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1331 if (!svm
->vcpu
.arch
.apic
->regs
)
1334 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1336 /* Setting AVIC backing page address in the phy APIC ID table */
1337 entry
= avic_get_physical_id_entry(vcpu
, id
);
1341 new_entry
= READ_ONCE(*entry
);
1342 new_entry
= (page_to_phys(svm
->avic_backing_page
) &
1343 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1344 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
;
1345 WRITE_ONCE(*entry
, new_entry
);
1347 svm
->avic_physical_id_cache
= entry
;
1352 static inline int avic_get_next_vm_id(void)
1356 spin_lock(&avic_vm_id_lock
);
1358 /* AVIC VM ID is one-based. */
1359 id
= find_next_zero_bit(avic_vm_id_bitmap
, AVIC_VM_ID_NR
, 1);
1360 if (id
<= AVIC_VM_ID_MASK
)
1361 __set_bit(id
, avic_vm_id_bitmap
);
1365 spin_unlock(&avic_vm_id_lock
);
1369 static inline int avic_free_vm_id(int id
)
1371 if (id
<= 0 || id
> AVIC_VM_ID_MASK
)
1374 spin_lock(&avic_vm_id_lock
);
1375 __clear_bit(id
, avic_vm_id_bitmap
);
1376 spin_unlock(&avic_vm_id_lock
);
1380 static void avic_vm_destroy(struct kvm
*kvm
)
1382 unsigned long flags
;
1383 struct kvm_arch
*vm_data
= &kvm
->arch
;
1385 avic_free_vm_id(vm_data
->avic_vm_id
);
1387 if (vm_data
->avic_logical_id_table_page
)
1388 __free_page(vm_data
->avic_logical_id_table_page
);
1389 if (vm_data
->avic_physical_id_table_page
)
1390 __free_page(vm_data
->avic_physical_id_table_page
);
1392 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1393 hash_del(&vm_data
->hnode
);
1394 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1397 static int avic_vm_init(struct kvm
*kvm
)
1399 unsigned long flags
;
1400 int vm_id
, err
= -ENOMEM
;
1401 struct kvm_arch
*vm_data
= &kvm
->arch
;
1402 struct page
*p_page
;
1403 struct page
*l_page
;
1408 vm_id
= avic_get_next_vm_id();
1411 vm_data
->avic_vm_id
= (u32
)vm_id
;
1413 /* Allocating physical APIC ID table (4KB) */
1414 p_page
= alloc_page(GFP_KERNEL
);
1418 vm_data
->avic_physical_id_table_page
= p_page
;
1419 clear_page(page_address(p_page
));
1421 /* Allocating logical APIC ID table (4KB) */
1422 l_page
= alloc_page(GFP_KERNEL
);
1426 vm_data
->avic_logical_id_table_page
= l_page
;
1427 clear_page(page_address(l_page
));
1429 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1430 hash_add(svm_vm_data_hash
, &vm_data
->hnode
, vm_data
->avic_vm_id
);
1431 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1436 avic_vm_destroy(kvm
);
1441 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1444 unsigned long flags
;
1445 struct amd_svm_iommu_ir
*ir
;
1446 struct vcpu_svm
*svm
= to_svm(vcpu
);
1448 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1452 * Here, we go through the per-vcpu ir_list to update all existing
1453 * interrupt remapping table entry targeting this vcpu.
1455 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1457 if (list_empty(&svm
->ir_list
))
1460 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1461 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
1466 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
1470 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1473 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1474 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
1475 struct vcpu_svm
*svm
= to_svm(vcpu
);
1477 if (!kvm_vcpu_apicv_active(vcpu
))
1480 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
1483 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1484 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
1486 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
1487 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
1489 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1490 if (svm
->avic_is_running
)
1491 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1493 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1494 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
1495 svm
->avic_is_running
);
1498 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
1501 struct vcpu_svm
*svm
= to_svm(vcpu
);
1503 if (!kvm_vcpu_apicv_active(vcpu
))
1506 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1507 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
1508 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
1510 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1511 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1515 * This function is called during VCPU halt/unhalt.
1517 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
1519 struct vcpu_svm
*svm
= to_svm(vcpu
);
1521 svm
->avic_is_running
= is_run
;
1523 avic_vcpu_load(vcpu
, vcpu
->cpu
);
1525 avic_vcpu_put(vcpu
);
1528 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1530 struct vcpu_svm
*svm
= to_svm(vcpu
);
1535 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1536 MSR_IA32_APICBASE_ENABLE
;
1537 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1538 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1542 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
);
1543 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1545 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1546 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1549 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1551 struct vcpu_svm
*svm
;
1553 struct page
*msrpm_pages
;
1554 struct page
*hsave_page
;
1555 struct page
*nested_msrpm_pages
;
1558 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1564 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1569 page
= alloc_page(GFP_KERNEL
);
1573 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1577 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1578 if (!nested_msrpm_pages
)
1581 hsave_page
= alloc_page(GFP_KERNEL
);
1586 err
= avic_init_backing_page(&svm
->vcpu
);
1590 INIT_LIST_HEAD(&svm
->ir_list
);
1591 spin_lock_init(&svm
->ir_list_lock
);
1594 /* We initialize this flag to true to make sure that the is_running
1595 * bit would be set the first time the vcpu is loaded.
1597 svm
->avic_is_running
= true;
1599 svm
->nested
.hsave
= page_address(hsave_page
);
1601 svm
->msrpm
= page_address(msrpm_pages
);
1602 svm_vcpu_init_msrpm(svm
->msrpm
);
1604 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1605 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1607 svm
->vmcb
= page_address(page
);
1608 clear_page(svm
->vmcb
);
1609 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1610 svm
->asid_generation
= 0;
1613 svm_init_osvw(&svm
->vcpu
);
1618 __free_page(hsave_page
);
1620 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1622 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1626 kvm_vcpu_uninit(&svm
->vcpu
);
1628 kmem_cache_free(kvm_vcpu_cache
, svm
);
1630 return ERR_PTR(err
);
1633 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1635 struct vcpu_svm
*svm
= to_svm(vcpu
);
1637 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1638 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1639 __free_page(virt_to_page(svm
->nested
.hsave
));
1640 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1641 kvm_vcpu_uninit(vcpu
);
1642 kmem_cache_free(kvm_vcpu_cache
, svm
);
1645 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1647 struct vcpu_svm
*svm
= to_svm(vcpu
);
1650 if (unlikely(cpu
!= vcpu
->cpu
)) {
1651 svm
->asid_generation
= 0;
1652 mark_all_dirty(svm
->vmcb
);
1655 #ifdef CONFIG_X86_64
1656 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1658 savesegment(fs
, svm
->host
.fs
);
1659 savesegment(gs
, svm
->host
.gs
);
1660 svm
->host
.ldt
= kvm_read_ldt();
1662 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1663 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1665 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1666 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1667 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1668 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1669 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1672 /* This assumes that the kernel never uses MSR_TSC_AUX */
1673 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1674 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
1676 avic_vcpu_load(vcpu
, cpu
);
1679 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1681 struct vcpu_svm
*svm
= to_svm(vcpu
);
1684 avic_vcpu_put(vcpu
);
1686 ++vcpu
->stat
.host_state_reload
;
1687 kvm_load_ldt(svm
->host
.ldt
);
1688 #ifdef CONFIG_X86_64
1689 loadsegment(fs
, svm
->host
.fs
);
1690 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
1691 load_gs_index(svm
->host
.gs
);
1693 #ifdef CONFIG_X86_32_LAZY_GS
1694 loadsegment(gs
, svm
->host
.gs
);
1697 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1698 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1701 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
1703 avic_set_running(vcpu
, false);
1706 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
1708 avic_set_running(vcpu
, true);
1711 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1713 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1716 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1719 * Any change of EFLAGS.VM is accompanied by a reload of SS
1720 * (caused by either a task switch or an inter-privilege IRET),
1721 * so we do not need to update the CPL here.
1723 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1726 static u32
svm_get_pkru(struct kvm_vcpu
*vcpu
)
1731 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1734 case VCPU_EXREG_PDPTR
:
1735 BUG_ON(!npt_enabled
);
1736 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1743 static void svm_set_vintr(struct vcpu_svm
*svm
)
1745 set_intercept(svm
, INTERCEPT_VINTR
);
1748 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1750 clr_intercept(svm
, INTERCEPT_VINTR
);
1753 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1755 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1758 case VCPU_SREG_CS
: return &save
->cs
;
1759 case VCPU_SREG_DS
: return &save
->ds
;
1760 case VCPU_SREG_ES
: return &save
->es
;
1761 case VCPU_SREG_FS
: return &save
->fs
;
1762 case VCPU_SREG_GS
: return &save
->gs
;
1763 case VCPU_SREG_SS
: return &save
->ss
;
1764 case VCPU_SREG_TR
: return &save
->tr
;
1765 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1771 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1773 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1778 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1779 struct kvm_segment
*var
, int seg
)
1781 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1783 var
->base
= s
->base
;
1784 var
->limit
= s
->limit
;
1785 var
->selector
= s
->selector
;
1786 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1787 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1788 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1789 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1790 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1791 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1792 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1795 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1796 * However, the SVM spec states that the G bit is not observed by the
1797 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1798 * So let's synthesize a legal G bit for all segments, this helps
1799 * running KVM nested. It also helps cross-vendor migration, because
1800 * Intel's vmentry has a check on the 'G' bit.
1802 var
->g
= s
->limit
> 0xfffff;
1805 * AMD's VMCB does not have an explicit unusable field, so emulate it
1806 * for cross vendor migration purposes by "not present"
1808 var
->unusable
= !var
->present
|| (var
->type
== 0);
1813 * Work around a bug where the busy flag in the tr selector
1823 * The accessed bit must always be set in the segment
1824 * descriptor cache, although it can be cleared in the
1825 * descriptor, the cached bit always remains at 1. Since
1826 * Intel has a check on this, set it here to support
1827 * cross-vendor migration.
1834 * On AMD CPUs sometimes the DB bit in the segment
1835 * descriptor is left as 1, although the whole segment has
1836 * been made unusable. Clear it here to pass an Intel VMX
1837 * entry check when cross vendor migrating.
1841 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1846 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1848 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1853 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1855 struct vcpu_svm
*svm
= to_svm(vcpu
);
1857 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1858 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1861 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1863 struct vcpu_svm
*svm
= to_svm(vcpu
);
1865 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1866 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1867 mark_dirty(svm
->vmcb
, VMCB_DT
);
1870 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1872 struct vcpu_svm
*svm
= to_svm(vcpu
);
1874 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1875 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1878 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1880 struct vcpu_svm
*svm
= to_svm(vcpu
);
1882 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1883 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1884 mark_dirty(svm
->vmcb
, VMCB_DT
);
1887 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1891 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1895 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1899 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1901 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1902 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1904 if (!svm
->vcpu
.fpu_active
)
1905 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1907 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1908 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1910 mark_dirty(svm
->vmcb
, VMCB_CR
);
1912 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1913 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1914 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1916 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1917 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1921 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1923 struct vcpu_svm
*svm
= to_svm(vcpu
);
1925 #ifdef CONFIG_X86_64
1926 if (vcpu
->arch
.efer
& EFER_LME
) {
1927 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1928 vcpu
->arch
.efer
|= EFER_LMA
;
1929 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1932 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1933 vcpu
->arch
.efer
&= ~EFER_LMA
;
1934 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1938 vcpu
->arch
.cr0
= cr0
;
1941 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1943 if (!vcpu
->fpu_active
)
1946 * re-enable caching here because the QEMU bios
1947 * does not do it - this results in some delay at
1950 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
1951 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1952 svm
->vmcb
->save
.cr0
= cr0
;
1953 mark_dirty(svm
->vmcb
, VMCB_CR
);
1954 update_cr0_intercept(svm
);
1957 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1959 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
1960 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1962 if (cr4
& X86_CR4_VMXE
)
1965 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1966 svm_flush_tlb(vcpu
);
1968 vcpu
->arch
.cr4
= cr4
;
1971 cr4
|= host_cr4_mce
;
1972 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1973 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1977 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1978 struct kvm_segment
*var
, int seg
)
1980 struct vcpu_svm
*svm
= to_svm(vcpu
);
1981 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1983 s
->base
= var
->base
;
1984 s
->limit
= var
->limit
;
1985 s
->selector
= var
->selector
;
1989 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1990 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1991 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1992 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1993 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1994 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1995 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1996 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2000 * This is always accurate, except if SYSRET returned to a segment
2001 * with SS.DPL != 3. Intel does not have this quirk, and always
2002 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2003 * would entail passing the CPL to userspace and back.
2005 if (seg
== VCPU_SREG_SS
)
2006 svm
->vmcb
->save
.cpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
2008 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2011 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2013 struct vcpu_svm
*svm
= to_svm(vcpu
);
2015 clr_exception_intercept(svm
, BP_VECTOR
);
2017 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2018 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2019 set_exception_intercept(svm
, BP_VECTOR
);
2021 vcpu
->guest_debug
= 0;
2024 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2026 if (sd
->next_asid
> sd
->max_asid
) {
2027 ++sd
->asid_generation
;
2029 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2032 svm
->asid_generation
= sd
->asid_generation
;
2033 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2035 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2038 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2040 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2043 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2045 struct vcpu_svm
*svm
= to_svm(vcpu
);
2047 svm
->vmcb
->save
.dr6
= value
;
2048 mark_dirty(svm
->vmcb
, VMCB_DR
);
2051 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2053 struct vcpu_svm
*svm
= to_svm(vcpu
);
2055 get_debugreg(vcpu
->arch
.db
[0], 0);
2056 get_debugreg(vcpu
->arch
.db
[1], 1);
2057 get_debugreg(vcpu
->arch
.db
[2], 2);
2058 get_debugreg(vcpu
->arch
.db
[3], 3);
2059 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2060 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2062 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2063 set_dr_intercepts(svm
);
2066 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2068 struct vcpu_svm
*svm
= to_svm(vcpu
);
2070 svm
->vmcb
->save
.dr7
= value
;
2071 mark_dirty(svm
->vmcb
, VMCB_DR
);
2074 static int pf_interception(struct vcpu_svm
*svm
)
2076 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2080 switch (svm
->apf_reason
) {
2082 error_code
= svm
->vmcb
->control
.exit_info_1
;
2084 trace_kvm_page_fault(fault_address
, error_code
);
2085 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
2086 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
2087 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2088 svm
->vmcb
->control
.insn_bytes
,
2089 svm
->vmcb
->control
.insn_len
);
2091 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
2092 svm
->apf_reason
= 0;
2093 local_irq_disable();
2094 kvm_async_pf_task_wait(fault_address
);
2097 case KVM_PV_REASON_PAGE_READY
:
2098 svm
->apf_reason
= 0;
2099 local_irq_disable();
2100 kvm_async_pf_task_wake(fault_address
);
2107 static int db_interception(struct vcpu_svm
*svm
)
2109 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2111 if (!(svm
->vcpu
.guest_debug
&
2112 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2113 !svm
->nmi_singlestep
) {
2114 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2118 if (svm
->nmi_singlestep
) {
2119 svm
->nmi_singlestep
= false;
2120 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
2121 svm
->vmcb
->save
.rflags
&=
2122 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2125 if (svm
->vcpu
.guest_debug
&
2126 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2127 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2128 kvm_run
->debug
.arch
.pc
=
2129 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2130 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2137 static int bp_interception(struct vcpu_svm
*svm
)
2139 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2141 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2142 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2143 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2147 static int ud_interception(struct vcpu_svm
*svm
)
2151 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
2152 if (er
!= EMULATE_DONE
)
2153 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2157 static int ac_interception(struct vcpu_svm
*svm
)
2159 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2163 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
2165 struct vcpu_svm
*svm
= to_svm(vcpu
);
2167 clr_exception_intercept(svm
, NM_VECTOR
);
2169 svm
->vcpu
.fpu_active
= 1;
2170 update_cr0_intercept(svm
);
2173 static int nm_interception(struct vcpu_svm
*svm
)
2175 svm_fpu_activate(&svm
->vcpu
);
2179 static bool is_erratum_383(void)
2184 if (!erratum_383_found
)
2187 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2191 /* Bit 62 may or may not be set for this mce */
2192 value
&= ~(1ULL << 62);
2194 if (value
!= 0xb600000000010015ULL
)
2197 /* Clear MCi_STATUS registers */
2198 for (i
= 0; i
< 6; ++i
)
2199 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2201 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2205 value
&= ~(1ULL << 2);
2206 low
= lower_32_bits(value
);
2207 high
= upper_32_bits(value
);
2209 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2212 /* Flush tlb to evict multi-match entries */
2218 static void svm_handle_mce(struct vcpu_svm
*svm
)
2220 if (is_erratum_383()) {
2222 * Erratum 383 triggered. Guest state is corrupt so kill the
2225 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2227 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2233 * On an #MC intercept the MCE handler is not called automatically in
2234 * the host. So do it by hand here.
2238 /* not sure if we ever come back to this point */
2243 static int mc_interception(struct vcpu_svm
*svm
)
2248 static int shutdown_interception(struct vcpu_svm
*svm
)
2250 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2253 * VMCB is undefined after a SHUTDOWN intercept
2254 * so reinitialize it.
2256 clear_page(svm
->vmcb
);
2259 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2263 static int io_interception(struct vcpu_svm
*svm
)
2265 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2266 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2267 int size
, in
, string
;
2270 ++svm
->vcpu
.stat
.io_exits
;
2271 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2272 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2274 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2276 port
= io_info
>> 16;
2277 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2278 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2279 skip_emulated_instruction(&svm
->vcpu
);
2281 return kvm_fast_pio_out(vcpu
, size
, port
);
2284 static int nmi_interception(struct vcpu_svm
*svm
)
2289 static int intr_interception(struct vcpu_svm
*svm
)
2291 ++svm
->vcpu
.stat
.irq_exits
;
2295 static int nop_on_interception(struct vcpu_svm
*svm
)
2300 static int halt_interception(struct vcpu_svm
*svm
)
2302 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2303 return kvm_emulate_halt(&svm
->vcpu
);
2306 static int vmmcall_interception(struct vcpu_svm
*svm
)
2308 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2309 return kvm_emulate_hypercall(&svm
->vcpu
);
2312 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2314 struct vcpu_svm
*svm
= to_svm(vcpu
);
2316 return svm
->nested
.nested_cr3
;
2319 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2321 struct vcpu_svm
*svm
= to_svm(vcpu
);
2322 u64 cr3
= svm
->nested
.nested_cr3
;
2326 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(cr3
), &pdpte
,
2327 offset_in_page(cr3
) + index
* 8, 8);
2333 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2336 struct vcpu_svm
*svm
= to_svm(vcpu
);
2338 svm
->vmcb
->control
.nested_cr3
= root
;
2339 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2340 svm_flush_tlb(vcpu
);
2343 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2344 struct x86_exception
*fault
)
2346 struct vcpu_svm
*svm
= to_svm(vcpu
);
2348 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2350 * TODO: track the cause of the nested page fault, and
2351 * correctly fill in the high bits of exit_info_1.
2353 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2354 svm
->vmcb
->control
.exit_code_hi
= 0;
2355 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2356 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2359 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2360 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2363 * The present bit is always zero for page structure faults on real
2366 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2367 svm
->vmcb
->control
.exit_info_1
&= ~1;
2369 nested_svm_vmexit(svm
);
2372 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2374 WARN_ON(mmu_is_nested(vcpu
));
2375 kvm_init_shadow_mmu(vcpu
);
2376 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2377 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2378 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2379 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2380 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
2381 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2382 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2385 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2387 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2390 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2392 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
2393 || !is_paging(&svm
->vcpu
)) {
2394 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2398 if (svm
->vmcb
->save
.cpl
) {
2399 kvm_inject_gp(&svm
->vcpu
, 0);
2406 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2407 bool has_error_code
, u32 error_code
)
2411 if (!is_guest_mode(&svm
->vcpu
))
2414 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2415 svm
->vmcb
->control
.exit_code_hi
= 0;
2416 svm
->vmcb
->control
.exit_info_1
= error_code
;
2417 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2419 vmexit
= nested_svm_intercept(svm
);
2420 if (vmexit
== NESTED_EXIT_DONE
)
2421 svm
->nested
.exit_required
= true;
2426 /* This function returns true if it is save to enable the irq window */
2427 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2429 if (!is_guest_mode(&svm
->vcpu
))
2432 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2435 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2439 * if vmexit was already requested (by intercepted exception
2440 * for instance) do not overwrite it with "external interrupt"
2443 if (svm
->nested
.exit_required
)
2446 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2447 svm
->vmcb
->control
.exit_info_1
= 0;
2448 svm
->vmcb
->control
.exit_info_2
= 0;
2450 if (svm
->nested
.intercept
& 1ULL) {
2452 * The #vmexit can't be emulated here directly because this
2453 * code path runs with irqs and preemption disabled. A
2454 * #vmexit emulation might sleep. Only signal request for
2457 svm
->nested
.exit_required
= true;
2458 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2465 /* This function returns true if it is save to enable the nmi window */
2466 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2468 if (!is_guest_mode(&svm
->vcpu
))
2471 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2474 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2475 svm
->nested
.exit_required
= true;
2480 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2486 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2487 if (is_error_page(page
))
2495 kvm_inject_gp(&svm
->vcpu
, 0);
2500 static void nested_svm_unmap(struct page
*page
)
2503 kvm_release_page_dirty(page
);
2506 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2508 unsigned port
, size
, iopm_len
;
2513 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2514 return NESTED_EXIT_HOST
;
2516 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2517 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2518 SVM_IOIO_SIZE_SHIFT
;
2519 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2520 start_bit
= port
% 8;
2521 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2522 mask
= (0xf >> (4 - size
)) << start_bit
;
2525 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2526 return NESTED_EXIT_DONE
;
2528 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2531 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2533 u32 offset
, msr
, value
;
2536 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2537 return NESTED_EXIT_HOST
;
2539 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2540 offset
= svm_msrpm_offset(msr
);
2541 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2542 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2544 if (offset
== MSR_INVALID
)
2545 return NESTED_EXIT_DONE
;
2547 /* Offset is in 32 bit units but need in 8 bit units */
2550 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2551 return NESTED_EXIT_DONE
;
2553 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2556 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2558 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2560 switch (exit_code
) {
2563 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2564 return NESTED_EXIT_HOST
;
2566 /* For now we are always handling NPFs when using them */
2568 return NESTED_EXIT_HOST
;
2570 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2571 /* When we're shadowing, trap PFs, but not async PF */
2572 if (!npt_enabled
&& svm
->apf_reason
== 0)
2573 return NESTED_EXIT_HOST
;
2575 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2576 nm_interception(svm
);
2582 return NESTED_EXIT_CONTINUE
;
2586 * If this function returns true, this #vmexit was already handled
2588 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2590 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2591 int vmexit
= NESTED_EXIT_HOST
;
2593 switch (exit_code
) {
2595 vmexit
= nested_svm_exit_handled_msr(svm
);
2598 vmexit
= nested_svm_intercept_ioio(svm
);
2600 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2601 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2602 if (svm
->nested
.intercept_cr
& bit
)
2603 vmexit
= NESTED_EXIT_DONE
;
2606 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2607 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2608 if (svm
->nested
.intercept_dr
& bit
)
2609 vmexit
= NESTED_EXIT_DONE
;
2612 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2613 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2614 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2615 vmexit
= NESTED_EXIT_DONE
;
2616 /* async page fault always cause vmexit */
2617 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2618 svm
->apf_reason
!= 0)
2619 vmexit
= NESTED_EXIT_DONE
;
2622 case SVM_EXIT_ERR
: {
2623 vmexit
= NESTED_EXIT_DONE
;
2627 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2628 if (svm
->nested
.intercept
& exit_bits
)
2629 vmexit
= NESTED_EXIT_DONE
;
2636 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2640 vmexit
= nested_svm_intercept(svm
);
2642 if (vmexit
== NESTED_EXIT_DONE
)
2643 nested_svm_vmexit(svm
);
2648 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2650 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2651 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2653 dst
->intercept_cr
= from
->intercept_cr
;
2654 dst
->intercept_dr
= from
->intercept_dr
;
2655 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2656 dst
->intercept
= from
->intercept
;
2657 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2658 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2659 dst
->tsc_offset
= from
->tsc_offset
;
2660 dst
->asid
= from
->asid
;
2661 dst
->tlb_ctl
= from
->tlb_ctl
;
2662 dst
->int_ctl
= from
->int_ctl
;
2663 dst
->int_vector
= from
->int_vector
;
2664 dst
->int_state
= from
->int_state
;
2665 dst
->exit_code
= from
->exit_code
;
2666 dst
->exit_code_hi
= from
->exit_code_hi
;
2667 dst
->exit_info_1
= from
->exit_info_1
;
2668 dst
->exit_info_2
= from
->exit_info_2
;
2669 dst
->exit_int_info
= from
->exit_int_info
;
2670 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2671 dst
->nested_ctl
= from
->nested_ctl
;
2672 dst
->event_inj
= from
->event_inj
;
2673 dst
->event_inj_err
= from
->event_inj_err
;
2674 dst
->nested_cr3
= from
->nested_cr3
;
2675 dst
->lbr_ctl
= from
->lbr_ctl
;
2678 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2680 struct vmcb
*nested_vmcb
;
2681 struct vmcb
*hsave
= svm
->nested
.hsave
;
2682 struct vmcb
*vmcb
= svm
->vmcb
;
2685 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2686 vmcb
->control
.exit_info_1
,
2687 vmcb
->control
.exit_info_2
,
2688 vmcb
->control
.exit_int_info
,
2689 vmcb
->control
.exit_int_info_err
,
2692 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2696 /* Exit Guest-Mode */
2697 leave_guest_mode(&svm
->vcpu
);
2698 svm
->nested
.vmcb
= 0;
2700 /* Give the current vmcb to the guest */
2703 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2704 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2705 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2706 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2707 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2708 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2709 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2710 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2711 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2712 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2713 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2714 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2715 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2716 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2717 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2718 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2719 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2720 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2722 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2723 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2724 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2725 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2726 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2727 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2728 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2729 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2730 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2732 if (svm
->nrips_enabled
)
2733 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2736 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2737 * to make sure that we do not lose injected events. So check event_inj
2738 * here and copy it to exit_int_info if it is valid.
2739 * Exit_int_info and event_inj can't be both valid because the case
2740 * below only happens on a VMRUN instruction intercept which has
2741 * no valid exit_int_info set.
2743 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2744 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2746 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2747 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2750 nested_vmcb
->control
.tlb_ctl
= 0;
2751 nested_vmcb
->control
.event_inj
= 0;
2752 nested_vmcb
->control
.event_inj_err
= 0;
2754 /* We always set V_INTR_MASKING and remember the old value in hflags */
2755 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2756 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2758 /* Restore the original control entries */
2759 copy_vmcb_control_area(vmcb
, hsave
);
2761 kvm_clear_exception_queue(&svm
->vcpu
);
2762 kvm_clear_interrupt_queue(&svm
->vcpu
);
2764 svm
->nested
.nested_cr3
= 0;
2766 /* Restore selected save entries */
2767 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2768 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2769 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2770 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2771 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2772 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2773 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2774 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2775 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2776 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2778 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2779 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2781 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2783 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2784 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2785 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2786 svm
->vmcb
->save
.dr7
= 0;
2787 svm
->vmcb
->save
.cpl
= 0;
2788 svm
->vmcb
->control
.exit_int_info
= 0;
2790 mark_all_dirty(svm
->vmcb
);
2792 nested_svm_unmap(page
);
2794 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2795 kvm_mmu_reset_context(&svm
->vcpu
);
2796 kvm_mmu_load(&svm
->vcpu
);
2801 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2804 * This function merges the msr permission bitmaps of kvm and the
2805 * nested vmcb. It is optimized in that it only merges the parts where
2806 * the kvm msr permission bitmap may contain zero bits
2810 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2813 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2817 if (msrpm_offsets
[i
] == 0xffffffff)
2820 p
= msrpm_offsets
[i
];
2821 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2823 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2826 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2829 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2834 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2836 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2839 if (vmcb
->control
.asid
== 0)
2842 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2848 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2850 struct vmcb
*nested_vmcb
;
2851 struct vmcb
*hsave
= svm
->nested
.hsave
;
2852 struct vmcb
*vmcb
= svm
->vmcb
;
2856 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2858 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2862 if (!nested_vmcb_checks(nested_vmcb
)) {
2863 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2864 nested_vmcb
->control
.exit_code_hi
= 0;
2865 nested_vmcb
->control
.exit_info_1
= 0;
2866 nested_vmcb
->control
.exit_info_2
= 0;
2868 nested_svm_unmap(page
);
2873 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2874 nested_vmcb
->save
.rip
,
2875 nested_vmcb
->control
.int_ctl
,
2876 nested_vmcb
->control
.event_inj
,
2877 nested_vmcb
->control
.nested_ctl
);
2879 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2880 nested_vmcb
->control
.intercept_cr
>> 16,
2881 nested_vmcb
->control
.intercept_exceptions
,
2882 nested_vmcb
->control
.intercept
);
2884 /* Clear internal status */
2885 kvm_clear_exception_queue(&svm
->vcpu
);
2886 kvm_clear_interrupt_queue(&svm
->vcpu
);
2889 * Save the old vmcb, so we don't need to pick what we save, but can
2890 * restore everything when a VMEXIT occurs
2892 hsave
->save
.es
= vmcb
->save
.es
;
2893 hsave
->save
.cs
= vmcb
->save
.cs
;
2894 hsave
->save
.ss
= vmcb
->save
.ss
;
2895 hsave
->save
.ds
= vmcb
->save
.ds
;
2896 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2897 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2898 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2899 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2900 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2901 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2902 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2903 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2904 hsave
->save
.rax
= vmcb
->save
.rax
;
2906 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2908 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2910 copy_vmcb_control_area(hsave
, vmcb
);
2912 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2913 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2915 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2917 if (nested_vmcb
->control
.nested_ctl
) {
2918 kvm_mmu_unload(&svm
->vcpu
);
2919 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2920 nested_svm_init_mmu_context(&svm
->vcpu
);
2923 /* Load the nested guest state */
2924 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2925 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2926 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2927 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2928 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2929 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2930 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2931 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2932 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2933 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2935 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2936 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2938 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2940 /* Guest paging mode is active - reset mmu */
2941 kvm_mmu_reset_context(&svm
->vcpu
);
2943 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2944 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2945 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2946 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2948 /* In case we don't even reach vcpu_run, the fields are not updated */
2949 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2950 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2951 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2952 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2953 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2954 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2956 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2957 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2959 /* cache intercepts */
2960 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2961 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2962 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2963 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2965 svm_flush_tlb(&svm
->vcpu
);
2966 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2967 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2968 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2970 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2972 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2973 /* We only want the cr8 intercept bits of the guest */
2974 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2975 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2978 /* We don't want to see VMMCALLs from a nested guest */
2979 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2981 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2982 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2983 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2984 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2985 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2986 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2988 nested_svm_unmap(page
);
2990 /* Enter Guest-Mode */
2991 enter_guest_mode(&svm
->vcpu
);
2994 * Merge guest and host intercepts - must be called with vcpu in
2995 * guest-mode to take affect here
2997 recalc_intercepts(svm
);
2999 svm
->nested
.vmcb
= vmcb_gpa
;
3003 mark_all_dirty(svm
->vmcb
);
3008 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3010 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3011 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3012 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3013 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3014 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3015 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3016 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3017 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3018 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3019 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3020 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3021 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3024 static int vmload_interception(struct vcpu_svm
*svm
)
3026 struct vmcb
*nested_vmcb
;
3029 if (nested_svm_check_permissions(svm
))
3032 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3036 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3037 skip_emulated_instruction(&svm
->vcpu
);
3039 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3040 nested_svm_unmap(page
);
3045 static int vmsave_interception(struct vcpu_svm
*svm
)
3047 struct vmcb
*nested_vmcb
;
3050 if (nested_svm_check_permissions(svm
))
3053 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3057 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3058 skip_emulated_instruction(&svm
->vcpu
);
3060 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3061 nested_svm_unmap(page
);
3066 static int vmrun_interception(struct vcpu_svm
*svm
)
3068 if (nested_svm_check_permissions(svm
))
3071 /* Save rip after vmrun instruction */
3072 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3074 if (!nested_svm_vmrun(svm
))
3077 if (!nested_svm_vmrun_msrpm(svm
))
3084 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3085 svm
->vmcb
->control
.exit_code_hi
= 0;
3086 svm
->vmcb
->control
.exit_info_1
= 0;
3087 svm
->vmcb
->control
.exit_info_2
= 0;
3089 nested_svm_vmexit(svm
);
3094 static int stgi_interception(struct vcpu_svm
*svm
)
3096 if (nested_svm_check_permissions(svm
))
3099 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3100 skip_emulated_instruction(&svm
->vcpu
);
3101 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3108 static int clgi_interception(struct vcpu_svm
*svm
)
3110 if (nested_svm_check_permissions(svm
))
3113 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3114 skip_emulated_instruction(&svm
->vcpu
);
3118 /* After a CLGI no interrupts should come */
3119 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3120 svm_clear_vintr(svm
);
3121 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3122 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3128 static int invlpga_interception(struct vcpu_svm
*svm
)
3130 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3132 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3133 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3135 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3136 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3138 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3139 skip_emulated_instruction(&svm
->vcpu
);
3143 static int skinit_interception(struct vcpu_svm
*svm
)
3145 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3147 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3151 static int wbinvd_interception(struct vcpu_svm
*svm
)
3153 kvm_emulate_wbinvd(&svm
->vcpu
);
3157 static int xsetbv_interception(struct vcpu_svm
*svm
)
3159 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3160 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3162 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3163 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3164 skip_emulated_instruction(&svm
->vcpu
);
3170 static int task_switch_interception(struct vcpu_svm
*svm
)
3174 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3175 SVM_EXITINTINFO_TYPE_MASK
;
3176 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3178 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3180 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3181 bool has_error_code
= false;
3184 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3186 if (svm
->vmcb
->control
.exit_info_2
&
3187 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3188 reason
= TASK_SWITCH_IRET
;
3189 else if (svm
->vmcb
->control
.exit_info_2
&
3190 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3191 reason
= TASK_SWITCH_JMP
;
3193 reason
= TASK_SWITCH_GATE
;
3195 reason
= TASK_SWITCH_CALL
;
3197 if (reason
== TASK_SWITCH_GATE
) {
3199 case SVM_EXITINTINFO_TYPE_NMI
:
3200 svm
->vcpu
.arch
.nmi_injected
= false;
3202 case SVM_EXITINTINFO_TYPE_EXEPT
:
3203 if (svm
->vmcb
->control
.exit_info_2
&
3204 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3205 has_error_code
= true;
3207 (u32
)svm
->vmcb
->control
.exit_info_2
;
3209 kvm_clear_exception_queue(&svm
->vcpu
);
3211 case SVM_EXITINTINFO_TYPE_INTR
:
3212 kvm_clear_interrupt_queue(&svm
->vcpu
);
3219 if (reason
!= TASK_SWITCH_GATE
||
3220 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3221 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3222 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3223 skip_emulated_instruction(&svm
->vcpu
);
3225 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3228 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3229 has_error_code
, error_code
) == EMULATE_FAIL
) {
3230 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3231 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3232 svm
->vcpu
.run
->internal
.ndata
= 0;
3238 static int cpuid_interception(struct vcpu_svm
*svm
)
3240 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3241 kvm_emulate_cpuid(&svm
->vcpu
);
3245 static int iret_interception(struct vcpu_svm
*svm
)
3247 ++svm
->vcpu
.stat
.nmi_window_exits
;
3248 clr_intercept(svm
, INTERCEPT_IRET
);
3249 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3250 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3251 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3255 static int invlpg_interception(struct vcpu_svm
*svm
)
3257 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3258 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3260 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3261 skip_emulated_instruction(&svm
->vcpu
);
3265 static int emulate_on_interception(struct vcpu_svm
*svm
)
3267 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3270 static int rdpmc_interception(struct vcpu_svm
*svm
)
3274 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3275 return emulate_on_interception(svm
);
3277 err
= kvm_rdpmc(&svm
->vcpu
);
3278 kvm_complete_insn_gp(&svm
->vcpu
, err
);
3283 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3286 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3290 intercept
= svm
->nested
.intercept
;
3292 if (!is_guest_mode(&svm
->vcpu
) ||
3293 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3296 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3297 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3300 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3301 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3307 #define CR_VALID (1ULL << 63)
3309 static int cr_interception(struct vcpu_svm
*svm
)
3315 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3316 return emulate_on_interception(svm
);
3318 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3319 return emulate_on_interception(svm
);
3321 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3322 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3323 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3325 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3328 if (cr
>= 16) { /* mov to cr */
3330 val
= kvm_register_read(&svm
->vcpu
, reg
);
3333 if (!check_selective_cr0_intercepted(svm
, val
))
3334 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3340 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3343 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3346 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3349 WARN(1, "unhandled write to CR%d", cr
);
3350 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3353 } else { /* mov from cr */
3356 val
= kvm_read_cr0(&svm
->vcpu
);
3359 val
= svm
->vcpu
.arch
.cr2
;
3362 val
= kvm_read_cr3(&svm
->vcpu
);
3365 val
= kvm_read_cr4(&svm
->vcpu
);
3368 val
= kvm_get_cr8(&svm
->vcpu
);
3371 WARN(1, "unhandled read from CR%d", cr
);
3372 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3375 kvm_register_write(&svm
->vcpu
, reg
, val
);
3377 kvm_complete_insn_gp(&svm
->vcpu
, err
);
3382 static int dr_interception(struct vcpu_svm
*svm
)
3387 if (svm
->vcpu
.guest_debug
== 0) {
3389 * No more DR vmexits; force a reload of the debug registers
3390 * and reenter on this instruction. The next vmexit will
3391 * retrieve the full state of the debug registers.
3393 clr_dr_intercepts(svm
);
3394 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3398 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3399 return emulate_on_interception(svm
);
3401 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3402 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3404 if (dr
>= 16) { /* mov to DRn */
3405 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3407 val
= kvm_register_read(&svm
->vcpu
, reg
);
3408 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3410 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3412 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3413 kvm_register_write(&svm
->vcpu
, reg
, val
);
3416 skip_emulated_instruction(&svm
->vcpu
);
3421 static int cr8_write_interception(struct vcpu_svm
*svm
)
3423 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3426 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3427 /* instruction emulation calls kvm_set_cr8() */
3428 r
= cr_interception(svm
);
3429 if (lapic_in_kernel(&svm
->vcpu
))
3431 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3433 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3437 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3439 struct vcpu_svm
*svm
= to_svm(vcpu
);
3441 switch (msr_info
->index
) {
3442 case MSR_IA32_TSC
: {
3443 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
3444 kvm_scale_tsc(vcpu
, rdtsc());
3449 msr_info
->data
= svm
->vmcb
->save
.star
;
3451 #ifdef CONFIG_X86_64
3453 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3456 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3458 case MSR_KERNEL_GS_BASE
:
3459 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3461 case MSR_SYSCALL_MASK
:
3462 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3465 case MSR_IA32_SYSENTER_CS
:
3466 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3468 case MSR_IA32_SYSENTER_EIP
:
3469 msr_info
->data
= svm
->sysenter_eip
;
3471 case MSR_IA32_SYSENTER_ESP
:
3472 msr_info
->data
= svm
->sysenter_esp
;
3475 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3477 msr_info
->data
= svm
->tsc_aux
;
3480 * Nobody will change the following 5 values in the VMCB so we can
3481 * safely return them on rdmsr. They will always be 0 until LBRV is
3484 case MSR_IA32_DEBUGCTLMSR
:
3485 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3487 case MSR_IA32_LASTBRANCHFROMIP
:
3488 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3490 case MSR_IA32_LASTBRANCHTOIP
:
3491 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3493 case MSR_IA32_LASTINTFROMIP
:
3494 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3496 case MSR_IA32_LASTINTTOIP
:
3497 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3499 case MSR_VM_HSAVE_PA
:
3500 msr_info
->data
= svm
->nested
.hsave_msr
;
3503 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3505 case MSR_IA32_UCODE_REV
:
3506 msr_info
->data
= 0x01000065;
3508 case MSR_F15H_IC_CFG
: {
3512 family
= guest_cpuid_family(vcpu
);
3513 model
= guest_cpuid_model(vcpu
);
3515 if (family
< 0 || model
< 0)
3516 return kvm_get_msr_common(vcpu
, msr_info
);
3520 if (family
== 0x15 &&
3521 (model
>= 0x2 && model
< 0x20))
3522 msr_info
->data
= 0x1E;
3526 return kvm_get_msr_common(vcpu
, msr_info
);
3531 static int rdmsr_interception(struct vcpu_svm
*svm
)
3533 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3534 struct msr_data msr_info
;
3536 msr_info
.index
= ecx
;
3537 msr_info
.host_initiated
= false;
3538 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3539 trace_kvm_msr_read_ex(ecx
);
3540 kvm_inject_gp(&svm
->vcpu
, 0);
3542 trace_kvm_msr_read(ecx
, msr_info
.data
);
3544 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3545 msr_info
.data
& 0xffffffff);
3546 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3547 msr_info
.data
>> 32);
3548 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3549 skip_emulated_instruction(&svm
->vcpu
);
3554 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3556 struct vcpu_svm
*svm
= to_svm(vcpu
);
3557 int svm_dis
, chg_mask
;
3559 if (data
& ~SVM_VM_CR_VALID_MASK
)
3562 chg_mask
= SVM_VM_CR_VALID_MASK
;
3564 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3565 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3567 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3568 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3570 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3572 /* check for svm_disable while efer.svme is set */
3573 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3579 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3581 struct vcpu_svm
*svm
= to_svm(vcpu
);
3583 u32 ecx
= msr
->index
;
3584 u64 data
= msr
->data
;
3587 kvm_write_tsc(vcpu
, msr
);
3590 svm
->vmcb
->save
.star
= data
;
3592 #ifdef CONFIG_X86_64
3594 svm
->vmcb
->save
.lstar
= data
;
3597 svm
->vmcb
->save
.cstar
= data
;
3599 case MSR_KERNEL_GS_BASE
:
3600 svm
->vmcb
->save
.kernel_gs_base
= data
;
3602 case MSR_SYSCALL_MASK
:
3603 svm
->vmcb
->save
.sfmask
= data
;
3606 case MSR_IA32_SYSENTER_CS
:
3607 svm
->vmcb
->save
.sysenter_cs
= data
;
3609 case MSR_IA32_SYSENTER_EIP
:
3610 svm
->sysenter_eip
= data
;
3611 svm
->vmcb
->save
.sysenter_eip
= data
;
3613 case MSR_IA32_SYSENTER_ESP
:
3614 svm
->sysenter_esp
= data
;
3615 svm
->vmcb
->save
.sysenter_esp
= data
;
3618 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3622 * This is rare, so we update the MSR here instead of using
3623 * direct_access_msrs. Doing that would require a rdmsr in
3626 svm
->tsc_aux
= data
;
3627 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
3629 case MSR_IA32_DEBUGCTLMSR
:
3630 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3631 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3635 if (data
& DEBUGCTL_RESERVED_BITS
)
3638 svm
->vmcb
->save
.dbgctl
= data
;
3639 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3640 if (data
& (1ULL<<0))
3641 svm_enable_lbrv(svm
);
3643 svm_disable_lbrv(svm
);
3645 case MSR_VM_HSAVE_PA
:
3646 svm
->nested
.hsave_msr
= data
;
3649 return svm_set_vm_cr(vcpu
, data
);
3651 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3653 case MSR_IA32_APICBASE
:
3654 if (kvm_vcpu_apicv_active(vcpu
))
3655 avic_update_vapic_bar(to_svm(vcpu
), data
);
3656 /* Follow through */
3658 return kvm_set_msr_common(vcpu
, msr
);
3663 static int wrmsr_interception(struct vcpu_svm
*svm
)
3665 struct msr_data msr
;
3666 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3667 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3671 msr
.host_initiated
= false;
3673 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3674 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3675 trace_kvm_msr_write_ex(ecx
, data
);
3676 kvm_inject_gp(&svm
->vcpu
, 0);
3678 trace_kvm_msr_write(ecx
, data
);
3679 skip_emulated_instruction(&svm
->vcpu
);
3684 static int msr_interception(struct vcpu_svm
*svm
)
3686 if (svm
->vmcb
->control
.exit_info_1
)
3687 return wrmsr_interception(svm
);
3689 return rdmsr_interception(svm
);
3692 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3694 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3695 svm_clear_vintr(svm
);
3696 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3697 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3698 ++svm
->vcpu
.stat
.irq_window_exits
;
3702 static int pause_interception(struct vcpu_svm
*svm
)
3704 kvm_vcpu_on_spin(&(svm
->vcpu
));
3708 static int nop_interception(struct vcpu_svm
*svm
)
3710 skip_emulated_instruction(&(svm
->vcpu
));
3714 static int monitor_interception(struct vcpu_svm
*svm
)
3716 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3717 return nop_interception(svm
);
3720 static int mwait_interception(struct vcpu_svm
*svm
)
3722 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3723 return nop_interception(svm
);
3726 enum avic_ipi_failure_cause
{
3727 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
3728 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
3729 AVIC_IPI_FAILURE_INVALID_TARGET
,
3730 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
3733 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
3735 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
3736 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
3737 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
3738 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
3739 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3741 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
3744 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
3746 * AVIC hardware handles the generation of
3747 * IPIs when the specified Message Type is Fixed
3748 * (also known as fixed delivery mode) and
3749 * the Trigger Mode is edge-triggered. The hardware
3750 * also supports self and broadcast delivery modes
3751 * specified via the Destination Shorthand(DSH)
3752 * field of the ICRL. Logical and physical APIC ID
3753 * formats are supported. All other IPI types cause
3754 * a #VMEXIT, which needs to emulated.
3756 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
3757 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
3759 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
3761 struct kvm_vcpu
*vcpu
;
3762 struct kvm
*kvm
= svm
->vcpu
.kvm
;
3763 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3766 * At this point, we expect that the AVIC HW has already
3767 * set the appropriate IRR bits on the valid target
3768 * vcpus. So, we just need to kick the appropriate vcpu.
3770 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
3771 bool m
= kvm_apic_match_dest(vcpu
, apic
,
3772 icrl
& KVM_APIC_SHORT_MASK
,
3773 GET_APIC_DEST_FIELD(icrh
),
3774 icrl
& KVM_APIC_DEST_MASK
);
3776 if (m
&& !avic_vcpu_is_running(vcpu
))
3777 kvm_vcpu_wake_up(vcpu
);
3781 case AVIC_IPI_FAILURE_INVALID_TARGET
:
3783 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
3784 WARN_ONCE(1, "Invalid backing page\n");
3787 pr_err("Unknown IPI interception\n");
3793 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
3795 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3797 u32
*logical_apic_id_table
;
3798 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
3803 if (flat
) { /* flat */
3804 index
= ffs(dlid
) - 1;
3807 } else { /* cluster */
3808 int cluster
= (dlid
& 0xf0) >> 4;
3809 int apic
= ffs(dlid
& 0x0f) - 1;
3811 if ((apic
< 0) || (apic
> 7) ||
3814 index
= (cluster
<< 2) + apic
;
3817 logical_apic_id_table
= (u32
*) page_address(vm_data
->avic_logical_id_table_page
);
3819 return &logical_apic_id_table
[index
];
3822 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
3826 u32
*entry
, new_entry
;
3828 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
3829 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
3833 new_entry
= READ_ONCE(*entry
);
3834 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
3835 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
3837 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3839 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3840 WRITE_ONCE(*entry
, new_entry
);
3845 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
3848 struct vcpu_svm
*svm
= to_svm(vcpu
);
3849 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
3854 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
3855 if (ret
&& svm
->ldr_reg
) {
3856 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
3864 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
3867 struct vcpu_svm
*svm
= to_svm(vcpu
);
3868 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
3869 u32 id
= (apic_id_reg
>> 24) & 0xff;
3871 if (vcpu
->vcpu_id
== id
)
3874 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
3875 new = avic_get_physical_id_entry(vcpu
, id
);
3879 /* We need to move physical_id_entry to new offset */
3882 to_svm(vcpu
)->avic_physical_id_cache
= new;
3885 * Also update the guest physical APIC ID in the logical
3886 * APIC ID table entry if already setup the LDR.
3889 avic_handle_ldr_update(vcpu
);
3894 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
3896 struct vcpu_svm
*svm
= to_svm(vcpu
);
3897 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3898 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
3899 u32 mod
= (dfr
>> 28) & 0xf;
3902 * We assume that all local APICs are using the same type.
3903 * If this changes, we need to flush the AVIC logical
3906 if (vm_data
->ldr_mode
== mod
)
3909 clear_page(page_address(vm_data
->avic_logical_id_table_page
));
3910 vm_data
->ldr_mode
= mod
;
3913 avic_handle_ldr_update(vcpu
);
3917 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
3919 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3920 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
3921 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
3925 if (avic_handle_apic_id_update(&svm
->vcpu
))
3929 if (avic_handle_ldr_update(&svm
->vcpu
))
3933 avic_handle_dfr_update(&svm
->vcpu
);
3939 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
3944 static bool is_avic_unaccelerated_access_trap(u32 offset
)
3973 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
3976 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
3977 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
3978 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
3979 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
3980 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
3981 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
3982 bool trap
= is_avic_unaccelerated_access_trap(offset
);
3984 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
3985 trap
, write
, vector
);
3988 WARN_ONCE(!write
, "svm: Handling trap read.\n");
3989 ret
= avic_unaccel_trap_write(svm
);
3991 /* Handling Fault */
3992 ret
= (emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
3998 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3999 [SVM_EXIT_READ_CR0
] = cr_interception
,
4000 [SVM_EXIT_READ_CR3
] = cr_interception
,
4001 [SVM_EXIT_READ_CR4
] = cr_interception
,
4002 [SVM_EXIT_READ_CR8
] = cr_interception
,
4003 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4004 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4005 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4006 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4007 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4008 [SVM_EXIT_READ_DR0
] = dr_interception
,
4009 [SVM_EXIT_READ_DR1
] = dr_interception
,
4010 [SVM_EXIT_READ_DR2
] = dr_interception
,
4011 [SVM_EXIT_READ_DR3
] = dr_interception
,
4012 [SVM_EXIT_READ_DR4
] = dr_interception
,
4013 [SVM_EXIT_READ_DR5
] = dr_interception
,
4014 [SVM_EXIT_READ_DR6
] = dr_interception
,
4015 [SVM_EXIT_READ_DR7
] = dr_interception
,
4016 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4017 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4018 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4019 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4020 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4021 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4022 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4023 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4024 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4025 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4026 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4027 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4028 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
4029 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4030 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4031 [SVM_EXIT_INTR
] = intr_interception
,
4032 [SVM_EXIT_NMI
] = nmi_interception
,
4033 [SVM_EXIT_SMI
] = nop_on_interception
,
4034 [SVM_EXIT_INIT
] = nop_on_interception
,
4035 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4036 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4037 [SVM_EXIT_CPUID
] = cpuid_interception
,
4038 [SVM_EXIT_IRET
] = iret_interception
,
4039 [SVM_EXIT_INVD
] = emulate_on_interception
,
4040 [SVM_EXIT_PAUSE
] = pause_interception
,
4041 [SVM_EXIT_HLT
] = halt_interception
,
4042 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4043 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4044 [SVM_EXIT_IOIO
] = io_interception
,
4045 [SVM_EXIT_MSR
] = msr_interception
,
4046 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4047 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4048 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4049 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4050 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4051 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4052 [SVM_EXIT_STGI
] = stgi_interception
,
4053 [SVM_EXIT_CLGI
] = clgi_interception
,
4054 [SVM_EXIT_SKINIT
] = skinit_interception
,
4055 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4056 [SVM_EXIT_MONITOR
] = monitor_interception
,
4057 [SVM_EXIT_MWAIT
] = mwait_interception
,
4058 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4059 [SVM_EXIT_NPF
] = pf_interception
,
4060 [SVM_EXIT_RSM
] = emulate_on_interception
,
4061 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4062 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4065 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4067 struct vcpu_svm
*svm
= to_svm(vcpu
);
4068 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4069 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4071 pr_err("VMCB Control Area:\n");
4072 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4073 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4074 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4075 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4076 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4077 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4078 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4079 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4080 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4081 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4082 pr_err("%-20s%d\n", "asid:", control
->asid
);
4083 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4084 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4085 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4086 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4087 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4088 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4089 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4090 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4091 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4092 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4093 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4094 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4095 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4096 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4097 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
4098 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4099 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4100 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4101 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4102 pr_err("VMCB State Save Area:\n");
4103 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4105 save
->es
.selector
, save
->es
.attrib
,
4106 save
->es
.limit
, save
->es
.base
);
4107 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4109 save
->cs
.selector
, save
->cs
.attrib
,
4110 save
->cs
.limit
, save
->cs
.base
);
4111 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4113 save
->ss
.selector
, save
->ss
.attrib
,
4114 save
->ss
.limit
, save
->ss
.base
);
4115 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4117 save
->ds
.selector
, save
->ds
.attrib
,
4118 save
->ds
.limit
, save
->ds
.base
);
4119 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4121 save
->fs
.selector
, save
->fs
.attrib
,
4122 save
->fs
.limit
, save
->fs
.base
);
4123 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4125 save
->gs
.selector
, save
->gs
.attrib
,
4126 save
->gs
.limit
, save
->gs
.base
);
4127 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4129 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4130 save
->gdtr
.limit
, save
->gdtr
.base
);
4131 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4133 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4134 save
->ldtr
.limit
, save
->ldtr
.base
);
4135 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4137 save
->idtr
.selector
, save
->idtr
.attrib
,
4138 save
->idtr
.limit
, save
->idtr
.base
);
4139 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4141 save
->tr
.selector
, save
->tr
.attrib
,
4142 save
->tr
.limit
, save
->tr
.base
);
4143 pr_err("cpl: %d efer: %016llx\n",
4144 save
->cpl
, save
->efer
);
4145 pr_err("%-15s %016llx %-13s %016llx\n",
4146 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4147 pr_err("%-15s %016llx %-13s %016llx\n",
4148 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4149 pr_err("%-15s %016llx %-13s %016llx\n",
4150 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4151 pr_err("%-15s %016llx %-13s %016llx\n",
4152 "rip:", save
->rip
, "rflags:", save
->rflags
);
4153 pr_err("%-15s %016llx %-13s %016llx\n",
4154 "rsp:", save
->rsp
, "rax:", save
->rax
);
4155 pr_err("%-15s %016llx %-13s %016llx\n",
4156 "star:", save
->star
, "lstar:", save
->lstar
);
4157 pr_err("%-15s %016llx %-13s %016llx\n",
4158 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4159 pr_err("%-15s %016llx %-13s %016llx\n",
4160 "kernel_gs_base:", save
->kernel_gs_base
,
4161 "sysenter_cs:", save
->sysenter_cs
);
4162 pr_err("%-15s %016llx %-13s %016llx\n",
4163 "sysenter_esp:", save
->sysenter_esp
,
4164 "sysenter_eip:", save
->sysenter_eip
);
4165 pr_err("%-15s %016llx %-13s %016llx\n",
4166 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4167 pr_err("%-15s %016llx %-13s %016llx\n",
4168 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4169 pr_err("%-15s %016llx %-13s %016llx\n",
4170 "excp_from:", save
->last_excp_from
,
4171 "excp_to:", save
->last_excp_to
);
4174 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4176 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4178 *info1
= control
->exit_info_1
;
4179 *info2
= control
->exit_info_2
;
4182 static int handle_exit(struct kvm_vcpu
*vcpu
)
4184 struct vcpu_svm
*svm
= to_svm(vcpu
);
4185 struct kvm_run
*kvm_run
= vcpu
->run
;
4186 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4188 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4190 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4191 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4193 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4195 if (unlikely(svm
->nested
.exit_required
)) {
4196 nested_svm_vmexit(svm
);
4197 svm
->nested
.exit_required
= false;
4202 if (is_guest_mode(vcpu
)) {
4205 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4206 svm
->vmcb
->control
.exit_info_1
,
4207 svm
->vmcb
->control
.exit_info_2
,
4208 svm
->vmcb
->control
.exit_int_info
,
4209 svm
->vmcb
->control
.exit_int_info_err
,
4212 vmexit
= nested_svm_exit_special(svm
);
4214 if (vmexit
== NESTED_EXIT_CONTINUE
)
4215 vmexit
= nested_svm_exit_handled(svm
);
4217 if (vmexit
== NESTED_EXIT_DONE
)
4221 svm_complete_interrupts(svm
);
4223 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4224 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4225 kvm_run
->fail_entry
.hardware_entry_failure_reason
4226 = svm
->vmcb
->control
.exit_code
;
4227 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4232 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4233 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4234 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4235 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4236 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4238 __func__
, svm
->vmcb
->control
.exit_int_info
,
4241 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4242 || !svm_exit_handlers
[exit_code
]) {
4243 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4244 kvm_queue_exception(vcpu
, UD_VECTOR
);
4248 return svm_exit_handlers
[exit_code
](svm
);
4251 static void reload_tss(struct kvm_vcpu
*vcpu
)
4253 int cpu
= raw_smp_processor_id();
4255 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4256 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4260 static void pre_svm_run(struct vcpu_svm
*svm
)
4262 int cpu
= raw_smp_processor_id();
4264 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4266 /* FIXME: handle wraparound of asid_generation */
4267 if (svm
->asid_generation
!= sd
->asid_generation
)
4271 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
4273 struct vcpu_svm
*svm
= to_svm(vcpu
);
4275 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
4276 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
4277 set_intercept(svm
, INTERCEPT_IRET
);
4278 ++vcpu
->stat
.nmi_injections
;
4281 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
4283 struct vmcb_control_area
*control
;
4285 /* The following fields are ignored when AVIC is enabled */
4286 control
= &svm
->vmcb
->control
;
4287 control
->int_vector
= irq
;
4288 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
4289 control
->int_ctl
|= V_IRQ_MASK
|
4290 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
4291 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4294 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
4296 struct vcpu_svm
*svm
= to_svm(vcpu
);
4298 BUG_ON(!(gif_set(svm
)));
4300 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
4301 ++vcpu
->stat
.irq_injections
;
4303 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
4304 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
4307 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
4309 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
4312 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
4314 struct vcpu_svm
*svm
= to_svm(vcpu
);
4316 if (svm_nested_virtualize_tpr(vcpu
) ||
4317 kvm_vcpu_apicv_active(vcpu
))
4320 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4326 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4329 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
4334 static bool svm_get_enable_apicv(void)
4339 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
4343 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
4347 /* Note: Currently only used by Hyper-V. */
4348 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4350 struct vcpu_svm
*svm
= to_svm(vcpu
);
4351 struct vmcb
*vmcb
= svm
->vmcb
;
4356 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
4357 mark_dirty(vmcb
, VMCB_INTR
);
4360 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
4365 static void svm_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4370 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
4372 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
4373 smp_mb__after_atomic();
4375 if (avic_vcpu_is_running(vcpu
))
4376 wrmsrl(SVM_AVIC_DOORBELL
,
4377 kvm_cpu_get_apicid(vcpu
->cpu
));
4379 kvm_vcpu_wake_up(vcpu
);
4382 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4384 unsigned long flags
;
4385 struct amd_svm_iommu_ir
*cur
;
4387 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4388 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
4389 if (cur
->data
!= pi
->ir_data
)
4391 list_del(&cur
->node
);
4395 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4398 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4401 unsigned long flags
;
4402 struct amd_svm_iommu_ir
*ir
;
4405 * In some cases, the existing irte is updaed and re-set,
4406 * so we need to check here if it's already been * added
4409 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
4410 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4411 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
4412 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
4413 struct vcpu_svm
*prev_svm
;
4420 prev_svm
= to_svm(prev_vcpu
);
4421 svm_ir_list_del(prev_svm
, pi
);
4425 * Allocating new amd_iommu_pi_data, which will get
4426 * add to the per-vcpu ir_list.
4428 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
4433 ir
->data
= pi
->ir_data
;
4435 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4436 list_add(&ir
->node
, &svm
->ir_list
);
4437 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4444 * The HW cannot support posting multicast/broadcast
4445 * interrupts to a vCPU. So, we still use legacy interrupt
4446 * remapping for these kind of interrupts.
4448 * For lowest-priority interrupts, we only support
4449 * those with single CPU as the destination, e.g. user
4450 * configures the interrupts via /proc/irq or uses
4451 * irqbalance to make the interrupts single-CPU.
4454 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
4455 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
4457 struct kvm_lapic_irq irq
;
4458 struct kvm_vcpu
*vcpu
= NULL
;
4460 kvm_set_msi_irq(kvm
, e
, &irq
);
4462 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
4463 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4464 __func__
, irq
.vector
);
4468 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
4470 *svm
= to_svm(vcpu
);
4471 vcpu_info
->pi_desc_addr
= page_to_phys((*svm
)->avic_backing_page
);
4472 vcpu_info
->vector
= irq
.vector
;
4478 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4481 * @host_irq: host irq of the interrupt
4482 * @guest_irq: gsi of the interrupt
4483 * @set: set or unset PI
4484 * returns 0 on success, < 0 on failure
4486 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
4487 uint32_t guest_irq
, bool set
)
4489 struct kvm_kernel_irq_routing_entry
*e
;
4490 struct kvm_irq_routing_table
*irq_rt
;
4491 int idx
, ret
= -EINVAL
;
4493 if (!kvm_arch_has_assigned_device(kvm
) ||
4494 !irq_remapping_cap(IRQ_POSTING_CAP
))
4497 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4498 __func__
, host_irq
, guest_irq
, set
);
4500 idx
= srcu_read_lock(&kvm
->irq_srcu
);
4501 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
4502 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
4504 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
4505 struct vcpu_data vcpu_info
;
4506 struct vcpu_svm
*svm
= NULL
;
4508 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
4512 * Here, we setup with legacy mode in the following cases:
4513 * 1. When cannot target interrupt to a specific vcpu.
4514 * 2. Unsetting posted interrupt.
4515 * 3. APIC virtialization is disabled for the vcpu.
4517 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
4518 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
4519 struct amd_iommu_pi_data pi
;
4521 /* Try to enable guest_mode in IRTE */
4522 pi
.base
= page_to_phys(svm
->avic_backing_page
) & AVIC_HPA_MASK
;
4523 pi
.ga_tag
= AVIC_GATAG(kvm
->arch
.avic_vm_id
,
4525 pi
.is_guest_mode
= true;
4526 pi
.vcpu_data
= &vcpu_info
;
4527 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4530 * Here, we successfully setting up vcpu affinity in
4531 * IOMMU guest mode. Now, we need to store the posted
4532 * interrupt information in a per-vcpu ir_list so that
4533 * we can reference to them directly when we update vcpu
4534 * scheduling information in IOMMU irte.
4536 if (!ret
&& pi
.is_guest_mode
)
4537 svm_ir_list_add(svm
, &pi
);
4539 /* Use legacy mode in IRTE */
4540 struct amd_iommu_pi_data pi
;
4543 * Here, pi is used to:
4544 * - Tell IOMMU to use legacy mode for this interrupt.
4545 * - Retrieve ga_tag of prior interrupt remapping data.
4547 pi
.is_guest_mode
= false;
4548 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4551 * Check if the posted interrupt was previously
4552 * setup with the guest_mode by checking if the ga_tag
4553 * was cached. If so, we need to clean up the per-vcpu
4556 if (!ret
&& pi
.prev_ga_tag
) {
4557 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
4558 struct kvm_vcpu
*vcpu
;
4560 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
4562 svm_ir_list_del(to_svm(vcpu
), &pi
);
4567 trace_kvm_pi_irte_update(svm
->vcpu
.vcpu_id
,
4570 vcpu_info
.pi_desc_addr
, set
);
4574 pr_err("%s: failed to update PI IRTE\n", __func__
);
4581 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
4585 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
4587 struct vcpu_svm
*svm
= to_svm(vcpu
);
4588 struct vmcb
*vmcb
= svm
->vmcb
;
4590 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
4591 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4592 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
4597 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4599 struct vcpu_svm
*svm
= to_svm(vcpu
);
4601 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4604 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4606 struct vcpu_svm
*svm
= to_svm(vcpu
);
4609 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
4610 set_intercept(svm
, INTERCEPT_IRET
);
4612 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
4613 clr_intercept(svm
, INTERCEPT_IRET
);
4617 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4619 struct vcpu_svm
*svm
= to_svm(vcpu
);
4620 struct vmcb
*vmcb
= svm
->vmcb
;
4623 if (!gif_set(svm
) ||
4624 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
4627 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
4629 if (is_guest_mode(vcpu
))
4630 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
4635 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4637 struct vcpu_svm
*svm
= to_svm(vcpu
);
4639 if (kvm_vcpu_apicv_active(vcpu
))
4643 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4644 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4645 * get that intercept, this function will be called again though and
4646 * we'll get the vintr intercept.
4648 if (gif_set(svm
) && nested_svm_intr(svm
)) {
4650 svm_inject_irq(svm
, 0x0);
4654 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4656 struct vcpu_svm
*svm
= to_svm(vcpu
);
4658 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
4660 return; /* IRET will cause a vm exit */
4663 * Something prevents NMI from been injected. Single step over possible
4664 * problem (IRET or exception injection or interrupt shadow)
4666 svm
->nmi_singlestep
= true;
4667 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
4670 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4675 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
4677 struct vcpu_svm
*svm
= to_svm(vcpu
);
4679 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
4680 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4682 svm
->asid_generation
--;
4685 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
4689 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
4691 struct vcpu_svm
*svm
= to_svm(vcpu
);
4693 if (svm_nested_virtualize_tpr(vcpu
))
4696 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
4697 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
4698 kvm_set_cr8(vcpu
, cr8
);
4702 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
4704 struct vcpu_svm
*svm
= to_svm(vcpu
);
4707 if (svm_nested_virtualize_tpr(vcpu
) ||
4708 kvm_vcpu_apicv_active(vcpu
))
4711 cr8
= kvm_get_cr8(vcpu
);
4712 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
4713 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
4716 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
4720 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
4721 unsigned int3_injected
= svm
->int3_injected
;
4723 svm
->int3_injected
= 0;
4726 * If we've made progress since setting HF_IRET_MASK, we've
4727 * executed an IRET and can allow NMI injection.
4729 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
4730 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
4731 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
4732 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4735 svm
->vcpu
.arch
.nmi_injected
= false;
4736 kvm_clear_exception_queue(&svm
->vcpu
);
4737 kvm_clear_interrupt_queue(&svm
->vcpu
);
4739 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
4742 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4744 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
4745 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
4748 case SVM_EXITINTINFO_TYPE_NMI
:
4749 svm
->vcpu
.arch
.nmi_injected
= true;
4751 case SVM_EXITINTINFO_TYPE_EXEPT
:
4753 * In case of software exceptions, do not reinject the vector,
4754 * but re-execute the instruction instead. Rewind RIP first
4755 * if we emulated INT3 before.
4757 if (kvm_exception_is_soft(vector
)) {
4758 if (vector
== BP_VECTOR
&& int3_injected
&&
4759 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
4760 kvm_rip_write(&svm
->vcpu
,
4761 kvm_rip_read(&svm
->vcpu
) -
4765 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
4766 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
4767 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
4770 kvm_requeue_exception(&svm
->vcpu
, vector
);
4772 case SVM_EXITINTINFO_TYPE_INTR
:
4773 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
4780 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
4782 struct vcpu_svm
*svm
= to_svm(vcpu
);
4783 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4785 control
->exit_int_info
= control
->event_inj
;
4786 control
->exit_int_info_err
= control
->event_inj_err
;
4787 control
->event_inj
= 0;
4788 svm_complete_interrupts(svm
);
4791 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
4793 struct vcpu_svm
*svm
= to_svm(vcpu
);
4795 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
4796 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
4797 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
4800 * A vmexit emulation is required before the vcpu can be executed
4803 if (unlikely(svm
->nested
.exit_required
))
4808 sync_lapic_to_cr8(vcpu
);
4810 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
4817 "push %%" _ASM_BP
"; \n\t"
4818 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
4819 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
4820 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
4821 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
4822 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
4823 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
4824 #ifdef CONFIG_X86_64
4825 "mov %c[r8](%[svm]), %%r8 \n\t"
4826 "mov %c[r9](%[svm]), %%r9 \n\t"
4827 "mov %c[r10](%[svm]), %%r10 \n\t"
4828 "mov %c[r11](%[svm]), %%r11 \n\t"
4829 "mov %c[r12](%[svm]), %%r12 \n\t"
4830 "mov %c[r13](%[svm]), %%r13 \n\t"
4831 "mov %c[r14](%[svm]), %%r14 \n\t"
4832 "mov %c[r15](%[svm]), %%r15 \n\t"
4835 /* Enter guest mode */
4836 "push %%" _ASM_AX
" \n\t"
4837 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
4838 __ex(SVM_VMLOAD
) "\n\t"
4839 __ex(SVM_VMRUN
) "\n\t"
4840 __ex(SVM_VMSAVE
) "\n\t"
4841 "pop %%" _ASM_AX
" \n\t"
4843 /* Save guest registers, load host registers */
4844 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
4845 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
4846 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
4847 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
4848 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
4849 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
4850 #ifdef CONFIG_X86_64
4851 "mov %%r8, %c[r8](%[svm]) \n\t"
4852 "mov %%r9, %c[r9](%[svm]) \n\t"
4853 "mov %%r10, %c[r10](%[svm]) \n\t"
4854 "mov %%r11, %c[r11](%[svm]) \n\t"
4855 "mov %%r12, %c[r12](%[svm]) \n\t"
4856 "mov %%r13, %c[r13](%[svm]) \n\t"
4857 "mov %%r14, %c[r14](%[svm]) \n\t"
4858 "mov %%r15, %c[r15](%[svm]) \n\t"
4863 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
4864 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4865 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4866 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4867 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4868 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4869 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
4870 #ifdef CONFIG_X86_64
4871 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4872 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4873 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4874 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4875 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4876 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4877 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4878 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
4881 #ifdef CONFIG_X86_64
4882 , "rbx", "rcx", "rdx", "rsi", "rdi"
4883 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4885 , "ebx", "ecx", "edx", "esi", "edi"
4889 #ifdef CONFIG_X86_64
4890 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
4892 loadsegment(fs
, svm
->host
.fs
);
4893 #ifndef CONFIG_X86_32_LAZY_GS
4894 loadsegment(gs
, svm
->host
.gs
);
4900 local_irq_disable();
4902 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
4903 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
4904 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
4905 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
4907 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
4908 kvm_before_handle_nmi(&svm
->vcpu
);
4912 /* Any pending NMI will happen here */
4914 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
4915 kvm_after_handle_nmi(&svm
->vcpu
);
4917 sync_cr8_to_lapic(vcpu
);
4921 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
4923 /* if exit due to PF check for async PF */
4924 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
4925 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
4928 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
4929 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
4933 * We need to handle MC intercepts here before the vcpu has a chance to
4934 * change the physical cpu
4936 if (unlikely(svm
->vmcb
->control
.exit_code
==
4937 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
4938 svm_handle_mce(svm
);
4940 mark_all_clean(svm
->vmcb
);
4943 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4945 struct vcpu_svm
*svm
= to_svm(vcpu
);
4947 svm
->vmcb
->save
.cr3
= root
;
4948 mark_dirty(svm
->vmcb
, VMCB_CR
);
4949 svm_flush_tlb(vcpu
);
4952 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4954 struct vcpu_svm
*svm
= to_svm(vcpu
);
4956 svm
->vmcb
->control
.nested_cr3
= root
;
4957 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4959 /* Also sync guest cr3 here in case we live migrate */
4960 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
4961 mark_dirty(svm
->vmcb
, VMCB_CR
);
4963 svm_flush_tlb(vcpu
);
4966 static int is_disabled(void)
4970 rdmsrl(MSR_VM_CR
, vm_cr
);
4971 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
4978 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4981 * Patch in the VMMCALL instruction:
4983 hypercall
[0] = 0x0f;
4984 hypercall
[1] = 0x01;
4985 hypercall
[2] = 0xd9;
4988 static void svm_check_processor_compat(void *rtn
)
4993 static bool svm_cpu_has_accelerated_tpr(void)
4998 static bool svm_has_high_real_mode_segbase(void)
5003 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5008 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5010 struct vcpu_svm
*svm
= to_svm(vcpu
);
5011 struct kvm_cpuid_entry2
*entry
;
5013 /* Update nrips enabled cache */
5014 svm
->nrips_enabled
= !!guest_cpuid_has_nrips(&svm
->vcpu
);
5016 if (!kvm_vcpu_apicv_active(vcpu
))
5019 entry
= kvm_find_cpuid_entry(vcpu
, 1, 0);
5021 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5024 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5029 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5033 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5036 entry
->eax
= 1; /* SVM revision 1 */
5037 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5038 ASID emulation to nested SVM */
5039 entry
->ecx
= 0; /* Reserved */
5040 entry
->edx
= 0; /* Per default do not support any
5041 additional features */
5043 /* Support next_rip if host supports it */
5044 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5045 entry
->edx
|= SVM_FEATURE_NRIP
;
5047 /* Support NPT for the guest if enabled */
5049 entry
->edx
|= SVM_FEATURE_NPT
;
5055 static int svm_get_lpage_level(void)
5057 return PT_PDPE_LEVEL
;
5060 static bool svm_rdtscp_supported(void)
5062 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5065 static bool svm_invpcid_supported(void)
5070 static bool svm_mpx_supported(void)
5075 static bool svm_xsaves_supported(void)
5080 static bool svm_has_wbinvd_exit(void)
5085 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
5087 struct vcpu_svm
*svm
= to_svm(vcpu
);
5089 set_exception_intercept(svm
, NM_VECTOR
);
5090 update_cr0_intercept(svm
);
5093 #define PRE_EX(exit) { .exit_code = (exit), \
5094 .stage = X86_ICPT_PRE_EXCEPT, }
5095 #define POST_EX(exit) { .exit_code = (exit), \
5096 .stage = X86_ICPT_POST_EXCEPT, }
5097 #define POST_MEM(exit) { .exit_code = (exit), \
5098 .stage = X86_ICPT_POST_MEMACCESS, }
5100 static const struct __x86_intercept
{
5102 enum x86_intercept_stage stage
;
5103 } x86_intercept_map
[] = {
5104 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5105 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5106 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5107 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5108 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5109 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5110 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5111 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5112 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5113 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5114 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5115 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5116 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5117 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5118 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5119 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5120 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5121 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5122 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5123 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5124 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5125 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5126 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5127 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5128 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5129 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5130 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5131 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5132 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5133 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5134 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5135 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5136 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5137 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5138 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5139 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5140 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5141 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5142 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5143 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5144 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5145 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5146 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5147 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5148 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5149 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5156 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5157 struct x86_instruction_info
*info
,
5158 enum x86_intercept_stage stage
)
5160 struct vcpu_svm
*svm
= to_svm(vcpu
);
5161 int vmexit
, ret
= X86EMUL_CONTINUE
;
5162 struct __x86_intercept icpt_info
;
5163 struct vmcb
*vmcb
= svm
->vmcb
;
5165 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5168 icpt_info
= x86_intercept_map
[info
->intercept
];
5170 if (stage
!= icpt_info
.stage
)
5173 switch (icpt_info
.exit_code
) {
5174 case SVM_EXIT_READ_CR0
:
5175 if (info
->intercept
== x86_intercept_cr_read
)
5176 icpt_info
.exit_code
+= info
->modrm_reg
;
5178 case SVM_EXIT_WRITE_CR0
: {
5179 unsigned long cr0
, val
;
5182 if (info
->intercept
== x86_intercept_cr_write
)
5183 icpt_info
.exit_code
+= info
->modrm_reg
;
5185 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
5186 info
->intercept
== x86_intercept_clts
)
5189 intercept
= svm
->nested
.intercept
;
5191 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
5194 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
5195 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
5197 if (info
->intercept
== x86_intercept_lmsw
) {
5200 /* lmsw can't clear PE - catch this here */
5201 if (cr0
& X86_CR0_PE
)
5206 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
5210 case SVM_EXIT_READ_DR0
:
5211 case SVM_EXIT_WRITE_DR0
:
5212 icpt_info
.exit_code
+= info
->modrm_reg
;
5215 if (info
->intercept
== x86_intercept_wrmsr
)
5216 vmcb
->control
.exit_info_1
= 1;
5218 vmcb
->control
.exit_info_1
= 0;
5220 case SVM_EXIT_PAUSE
:
5222 * We get this for NOP only, but pause
5223 * is rep not, check this here
5225 if (info
->rep_prefix
!= REPE_PREFIX
)
5227 case SVM_EXIT_IOIO
: {
5231 if (info
->intercept
== x86_intercept_in
||
5232 info
->intercept
== x86_intercept_ins
) {
5233 exit_info
= ((info
->src_val
& 0xffff) << 16) |
5235 bytes
= info
->dst_bytes
;
5237 exit_info
= (info
->dst_val
& 0xffff) << 16;
5238 bytes
= info
->src_bytes
;
5241 if (info
->intercept
== x86_intercept_outs
||
5242 info
->intercept
== x86_intercept_ins
)
5243 exit_info
|= SVM_IOIO_STR_MASK
;
5245 if (info
->rep_prefix
)
5246 exit_info
|= SVM_IOIO_REP_MASK
;
5248 bytes
= min(bytes
, 4u);
5250 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
5252 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
5254 vmcb
->control
.exit_info_1
= exit_info
;
5255 vmcb
->control
.exit_info_2
= info
->next_rip
;
5263 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5264 if (static_cpu_has(X86_FEATURE_NRIPS
))
5265 vmcb
->control
.next_rip
= info
->next_rip
;
5266 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
5267 vmexit
= nested_svm_exit_handled(svm
);
5269 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
5276 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
5280 * We must have an instruction with interrupts enabled, so
5281 * the timer interrupt isn't delayed by the interrupt shadow.
5284 local_irq_disable();
5287 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
5291 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
5293 if (avic_handle_apic_id_update(vcpu
) != 0)
5295 if (avic_handle_dfr_update(vcpu
) != 0)
5297 avic_handle_ldr_update(vcpu
);
5300 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
5301 .cpu_has_kvm_support
= has_svm
,
5302 .disabled_by_bios
= is_disabled
,
5303 .hardware_setup
= svm_hardware_setup
,
5304 .hardware_unsetup
= svm_hardware_unsetup
,
5305 .check_processor_compatibility
= svm_check_processor_compat
,
5306 .hardware_enable
= svm_hardware_enable
,
5307 .hardware_disable
= svm_hardware_disable
,
5308 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
5309 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
5311 .vcpu_create
= svm_create_vcpu
,
5312 .vcpu_free
= svm_free_vcpu
,
5313 .vcpu_reset
= svm_vcpu_reset
,
5315 .vm_init
= avic_vm_init
,
5316 .vm_destroy
= avic_vm_destroy
,
5318 .prepare_guest_switch
= svm_prepare_guest_switch
,
5319 .vcpu_load
= svm_vcpu_load
,
5320 .vcpu_put
= svm_vcpu_put
,
5321 .vcpu_blocking
= svm_vcpu_blocking
,
5322 .vcpu_unblocking
= svm_vcpu_unblocking
,
5324 .update_bp_intercept
= update_bp_intercept
,
5325 .get_msr
= svm_get_msr
,
5326 .set_msr
= svm_set_msr
,
5327 .get_segment_base
= svm_get_segment_base
,
5328 .get_segment
= svm_get_segment
,
5329 .set_segment
= svm_set_segment
,
5330 .get_cpl
= svm_get_cpl
,
5331 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
5332 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
5333 .decache_cr3
= svm_decache_cr3
,
5334 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
5335 .set_cr0
= svm_set_cr0
,
5336 .set_cr3
= svm_set_cr3
,
5337 .set_cr4
= svm_set_cr4
,
5338 .set_efer
= svm_set_efer
,
5339 .get_idt
= svm_get_idt
,
5340 .set_idt
= svm_set_idt
,
5341 .get_gdt
= svm_get_gdt
,
5342 .set_gdt
= svm_set_gdt
,
5343 .get_dr6
= svm_get_dr6
,
5344 .set_dr6
= svm_set_dr6
,
5345 .set_dr7
= svm_set_dr7
,
5346 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
5347 .cache_reg
= svm_cache_reg
,
5348 .get_rflags
= svm_get_rflags
,
5349 .set_rflags
= svm_set_rflags
,
5351 .get_pkru
= svm_get_pkru
,
5353 .fpu_activate
= svm_fpu_activate
,
5354 .fpu_deactivate
= svm_fpu_deactivate
,
5356 .tlb_flush
= svm_flush_tlb
,
5358 .run
= svm_vcpu_run
,
5359 .handle_exit
= handle_exit
,
5360 .skip_emulated_instruction
= skip_emulated_instruction
,
5361 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
5362 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
5363 .patch_hypercall
= svm_patch_hypercall
,
5364 .set_irq
= svm_set_irq
,
5365 .set_nmi
= svm_inject_nmi
,
5366 .queue_exception
= svm_queue_exception
,
5367 .cancel_injection
= svm_cancel_injection
,
5368 .interrupt_allowed
= svm_interrupt_allowed
,
5369 .nmi_allowed
= svm_nmi_allowed
,
5370 .get_nmi_mask
= svm_get_nmi_mask
,
5371 .set_nmi_mask
= svm_set_nmi_mask
,
5372 .enable_nmi_window
= enable_nmi_window
,
5373 .enable_irq_window
= enable_irq_window
,
5374 .update_cr8_intercept
= update_cr8_intercept
,
5375 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
5376 .get_enable_apicv
= svm_get_enable_apicv
,
5377 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
5378 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
5379 .sync_pir_to_irr
= svm_sync_pir_to_irr
,
5380 .hwapic_irr_update
= svm_hwapic_irr_update
,
5381 .hwapic_isr_update
= svm_hwapic_isr_update
,
5382 .apicv_post_state_restore
= avic_post_state_restore
,
5384 .set_tss_addr
= svm_set_tss_addr
,
5385 .get_tdp_level
= get_npt_level
,
5386 .get_mt_mask
= svm_get_mt_mask
,
5388 .get_exit_info
= svm_get_exit_info
,
5390 .get_lpage_level
= svm_get_lpage_level
,
5392 .cpuid_update
= svm_cpuid_update
,
5394 .rdtscp_supported
= svm_rdtscp_supported
,
5395 .invpcid_supported
= svm_invpcid_supported
,
5396 .mpx_supported
= svm_mpx_supported
,
5397 .xsaves_supported
= svm_xsaves_supported
,
5399 .set_supported_cpuid
= svm_set_supported_cpuid
,
5401 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
5403 .write_tsc_offset
= svm_write_tsc_offset
,
5405 .set_tdp_cr3
= set_tdp_cr3
,
5407 .check_intercept
= svm_check_intercept
,
5408 .handle_external_intr
= svm_handle_external_intr
,
5410 .sched_in
= svm_sched_in
,
5412 .pmu_ops
= &amd_pmu_ops
,
5413 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
5414 .update_pi_irte
= svm_update_pi_irte
,
5417 static int __init
svm_init(void)
5419 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
5420 __alignof__(struct vcpu_svm
), THIS_MODULE
);
5423 static void __exit
svm_exit(void)
5428 module_init(svm_init
)
5429 module_exit(svm_exit
)