2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
31 #include <asm/virtext.h>
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 #define IOPM_ALLOC_ORDER 2
39 #define MSRPM_ALLOC_ORDER 1
41 #define SEG_TYPE_LDT 2
42 #define SEG_TYPE_BUSY_TSS16 3
44 #define SVM_FEATURE_NPT (1 << 0)
45 #define SVM_FEATURE_LBRV (1 << 1)
46 #define SVM_FEATURE_SVML (1 << 2)
48 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50 /* Turn on to get debugging output*/
51 /* #define NESTED_DEBUG */
54 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56 #define nsvm_printk(fmt, args...) do {} while(0)
59 static const u32 host_save_user_msrs
[] = {
61 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
64 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74 unsigned long vmcb_pa
;
75 struct svm_cpu_data
*svm_data
;
76 uint64_t asid_generation
;
77 uint64_t sysenter_esp
;
78 uint64_t sysenter_eip
;
82 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
84 unsigned long host_cr2
;
92 /* These are the merged vectors */
95 /* gpa pointers to the real vectors */
96 u64 nested_vmcb_msrpm
;
99 /* enable NPT for AMD64 and X86 with PAE */
100 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
101 static bool npt_enabled
= true;
103 static bool npt_enabled
= false;
107 module_param(npt
, int, S_IRUGO
);
109 static int nested
= 0;
110 module_param(nested
, int, S_IRUGO
);
112 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
114 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
);
115 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
116 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
117 void *arg2
, void *opaque
);
118 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
119 bool has_error_code
, u32 error_code
);
121 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
123 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
126 static inline bool is_nested(struct vcpu_svm
*svm
)
128 return svm
->nested_vmcb
;
131 static unsigned long iopm_base
;
133 struct kvm_ldttss_desc
{
136 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
137 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
140 } __attribute__((packed
));
142 struct svm_cpu_data
{
148 struct kvm_ldttss_desc
*tss_desc
;
150 struct page
*save_area
;
153 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
154 static uint32_t svm_features
;
156 struct svm_init_data
{
161 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
163 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
164 #define MSRS_RANGE_SIZE 2048
165 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
167 #define MAX_INST_SIZE 15
169 static inline u32
svm_has(u32 feat
)
171 return svm_features
& feat
;
174 static inline void clgi(void)
176 asm volatile (__ex(SVM_CLGI
));
179 static inline void stgi(void)
181 asm volatile (__ex(SVM_STGI
));
184 static inline void invlpga(unsigned long addr
, u32 asid
)
186 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
189 static inline unsigned long kvm_read_cr2(void)
193 asm volatile ("mov %%cr2, %0" : "=r" (cr2
));
197 static inline void kvm_write_cr2(unsigned long val
)
199 asm volatile ("mov %0, %%cr2" :: "r" (val
));
202 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
204 to_svm(vcpu
)->asid_generation
--;
207 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
209 force_new_asid(vcpu
);
212 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
214 if (!npt_enabled
&& !(efer
& EFER_LMA
))
217 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
218 vcpu
->arch
.shadow_efer
= efer
;
221 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
222 bool has_error_code
, u32 error_code
)
224 struct vcpu_svm
*svm
= to_svm(vcpu
);
226 /* If we are within a nested VM we'd better #VMEXIT and let the
227 guest handle the exception */
228 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
231 svm
->vmcb
->control
.event_inj
= nr
233 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
234 | SVM_EVTINJ_TYPE_EXEPT
;
235 svm
->vmcb
->control
.event_inj_err
= error_code
;
238 static int is_external_interrupt(u32 info
)
240 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
241 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
244 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
246 struct vcpu_svm
*svm
= to_svm(vcpu
);
249 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
250 ret
|= X86_SHADOW_INT_STI
| X86_SHADOW_INT_MOV_SS
;
254 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
256 struct vcpu_svm
*svm
= to_svm(vcpu
);
259 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
261 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
265 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
267 struct vcpu_svm
*svm
= to_svm(vcpu
);
269 if (!svm
->next_rip
) {
270 if (emulate_instruction(vcpu
, vcpu
->run
, 0, 0, EMULTYPE_SKIP
) !=
272 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
275 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
276 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
277 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
279 kvm_rip_write(vcpu
, svm
->next_rip
);
280 svm_set_interrupt_shadow(vcpu
, 0);
283 static int has_svm(void)
287 if (!cpu_has_svm(&msg
)) {
288 printk(KERN_INFO
"has_svm: %s\n", msg
);
295 static void svm_hardware_disable(void *garbage
)
300 static void svm_hardware_enable(void *garbage
)
303 struct svm_cpu_data
*svm_data
;
305 struct desc_ptr gdt_descr
;
306 struct desc_struct
*gdt
;
307 int me
= raw_smp_processor_id();
310 printk(KERN_ERR
"svm_cpu_init: err EOPNOTSUPP on %d\n", me
);
313 svm_data
= per_cpu(svm_data
, me
);
316 printk(KERN_ERR
"svm_cpu_init: svm_data is NULL on %d\n",
321 svm_data
->asid_generation
= 1;
322 svm_data
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
323 svm_data
->next_asid
= svm_data
->max_asid
+ 1;
325 asm volatile ("sgdt %0" : "=m"(gdt_descr
));
326 gdt
= (struct desc_struct
*)gdt_descr
.address
;
327 svm_data
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
329 rdmsrl(MSR_EFER
, efer
);
330 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
332 wrmsrl(MSR_VM_HSAVE_PA
,
333 page_to_pfn(svm_data
->save_area
) << PAGE_SHIFT
);
336 static void svm_cpu_uninit(int cpu
)
338 struct svm_cpu_data
*svm_data
339 = per_cpu(svm_data
, raw_smp_processor_id());
344 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
345 __free_page(svm_data
->save_area
);
349 static int svm_cpu_init(int cpu
)
351 struct svm_cpu_data
*svm_data
;
354 svm_data
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
358 svm_data
->save_area
= alloc_page(GFP_KERNEL
);
360 if (!svm_data
->save_area
)
363 per_cpu(svm_data
, cpu
) = svm_data
;
373 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
378 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
379 if (msr
>= msrpm_ranges
[i
] &&
380 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
381 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
382 msrpm_ranges
[i
]) * 2;
384 u32
*base
= msrpm
+ (msr_offset
/ 32);
385 u32 msr_shift
= msr_offset
% 32;
386 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
387 *base
= (*base
& ~(0x3 << msr_shift
)) |
395 static void svm_vcpu_init_msrpm(u32
*msrpm
)
397 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
400 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
401 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
402 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
403 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
404 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
405 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
407 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
408 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
411 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
413 u32
*msrpm
= svm
->msrpm
;
415 svm
->vmcb
->control
.lbr_ctl
= 1;
416 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
417 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
418 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
419 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
422 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
424 u32
*msrpm
= svm
->msrpm
;
426 svm
->vmcb
->control
.lbr_ctl
= 0;
427 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
428 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
429 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
430 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
433 static __init
int svm_hardware_setup(void)
436 struct page
*iopm_pages
;
440 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
445 iopm_va
= page_address(iopm_pages
);
446 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
447 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
449 if (boot_cpu_has(X86_FEATURE_NX
))
450 kvm_enable_efer_bits(EFER_NX
);
452 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
453 kvm_enable_efer_bits(EFER_FFXSR
);
456 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
457 kvm_enable_efer_bits(EFER_SVME
);
460 for_each_online_cpu(cpu
) {
461 r
= svm_cpu_init(cpu
);
466 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
468 if (!svm_has(SVM_FEATURE_NPT
))
471 if (npt_enabled
&& !npt
) {
472 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
477 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
485 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
490 static __exit
void svm_hardware_unsetup(void)
494 for_each_online_cpu(cpu
)
497 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
501 static void init_seg(struct vmcb_seg
*seg
)
504 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
505 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
510 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
513 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
518 static void init_vmcb(struct vcpu_svm
*svm
)
520 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
521 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
523 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
527 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
532 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
537 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
544 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
549 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
550 (1ULL << INTERCEPT_NMI
) |
551 (1ULL << INTERCEPT_SMI
) |
552 (1ULL << INTERCEPT_CPUID
) |
553 (1ULL << INTERCEPT_INVD
) |
554 (1ULL << INTERCEPT_HLT
) |
555 (1ULL << INTERCEPT_INVLPG
) |
556 (1ULL << INTERCEPT_INVLPGA
) |
557 (1ULL << INTERCEPT_IOIO_PROT
) |
558 (1ULL << INTERCEPT_MSR_PROT
) |
559 (1ULL << INTERCEPT_TASK_SWITCH
) |
560 (1ULL << INTERCEPT_SHUTDOWN
) |
561 (1ULL << INTERCEPT_VMRUN
) |
562 (1ULL << INTERCEPT_VMMCALL
) |
563 (1ULL << INTERCEPT_VMLOAD
) |
564 (1ULL << INTERCEPT_VMSAVE
) |
565 (1ULL << INTERCEPT_STGI
) |
566 (1ULL << INTERCEPT_CLGI
) |
567 (1ULL << INTERCEPT_SKINIT
) |
568 (1ULL << INTERCEPT_WBINVD
) |
569 (1ULL << INTERCEPT_MONITOR
) |
570 (1ULL << INTERCEPT_MWAIT
);
572 control
->iopm_base_pa
= iopm_base
;
573 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
574 control
->tsc_offset
= 0;
575 control
->int_ctl
= V_INTR_MASKING_MASK
;
583 save
->cs
.selector
= 0xf000;
584 /* Executable/Readable Code Segment */
585 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
586 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
587 save
->cs
.limit
= 0xffff;
589 * cs.base should really be 0xffff0000, but vmx can't handle that, so
590 * be consistent with it.
592 * Replace when we have real mode working for vmx.
594 save
->cs
.base
= 0xf0000;
596 save
->gdtr
.limit
= 0xffff;
597 save
->idtr
.limit
= 0xffff;
599 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
600 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
602 save
->efer
= EFER_SVME
;
603 save
->dr6
= 0xffff0ff0;
606 save
->rip
= 0x0000fff0;
607 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
610 * cr0 val on cpu init should be 0x60000010, we enable cpu
611 * cache by default. the orderly way is to enable cache in bios.
613 save
->cr0
= 0x00000010 | X86_CR0_PG
| X86_CR0_WP
;
614 save
->cr4
= X86_CR4_PAE
;
618 /* Setup VMCB for Nested Paging */
619 control
->nested_ctl
= 1;
620 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
621 (1ULL << INTERCEPT_INVLPG
));
622 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
623 control
->intercept_cr_read
&= ~(INTERCEPT_CR0_MASK
|
625 control
->intercept_cr_write
&= ~(INTERCEPT_CR0_MASK
|
627 save
->g_pat
= 0x0007040600070406ULL
;
628 /* enable caching because the QEMU Bios doesn't enable it */
629 save
->cr0
= X86_CR0_ET
;
633 force_new_asid(&svm
->vcpu
);
635 svm
->nested_vmcb
= 0;
636 svm
->vcpu
.arch
.hflags
= HF_GIF_MASK
;
639 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
641 struct vcpu_svm
*svm
= to_svm(vcpu
);
645 if (vcpu
->vcpu_id
!= 0) {
646 kvm_rip_write(vcpu
, 0);
647 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
648 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
650 vcpu
->arch
.regs_avail
= ~0;
651 vcpu
->arch
.regs_dirty
= ~0;
656 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
658 struct vcpu_svm
*svm
;
660 struct page
*msrpm_pages
;
661 struct page
*hsave_page
;
662 struct page
*nested_msrpm_pages
;
665 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
671 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
675 page
= alloc_page(GFP_KERNEL
);
682 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
686 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
687 if (!nested_msrpm_pages
)
690 svm
->msrpm
= page_address(msrpm_pages
);
691 svm_vcpu_init_msrpm(svm
->msrpm
);
693 hsave_page
= alloc_page(GFP_KERNEL
);
696 svm
->hsave
= page_address(hsave_page
);
698 svm
->nested_msrpm
= page_address(nested_msrpm_pages
);
700 svm
->vmcb
= page_address(page
);
701 clear_page(svm
->vmcb
);
702 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
703 svm
->asid_generation
= 0;
707 svm
->vcpu
.fpu_active
= 1;
708 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
709 if (svm
->vcpu
.vcpu_id
== 0)
710 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
715 kvm_vcpu_uninit(&svm
->vcpu
);
717 kmem_cache_free(kvm_vcpu_cache
, svm
);
722 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
724 struct vcpu_svm
*svm
= to_svm(vcpu
);
726 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
727 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
728 __free_page(virt_to_page(svm
->hsave
));
729 __free_pages(virt_to_page(svm
->nested_msrpm
), MSRPM_ALLOC_ORDER
);
730 kvm_vcpu_uninit(vcpu
);
731 kmem_cache_free(kvm_vcpu_cache
, svm
);
734 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
736 struct vcpu_svm
*svm
= to_svm(vcpu
);
739 if (unlikely(cpu
!= vcpu
->cpu
)) {
743 * Make sure that the guest sees a monotonically
747 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
748 svm
->vmcb
->control
.tsc_offset
+= delta
;
750 kvm_migrate_timers(vcpu
);
751 svm
->asid_generation
= 0;
754 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
755 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
758 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
760 struct vcpu_svm
*svm
= to_svm(vcpu
);
763 ++vcpu
->stat
.host_state_reload
;
764 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
765 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
767 rdtscll(vcpu
->arch
.host_tsc
);
770 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
772 return to_svm(vcpu
)->vmcb
->save
.rflags
;
775 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
777 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
780 static void svm_set_vintr(struct vcpu_svm
*svm
)
782 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
785 static void svm_clear_vintr(struct vcpu_svm
*svm
)
787 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
790 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
792 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
795 case VCPU_SREG_CS
: return &save
->cs
;
796 case VCPU_SREG_DS
: return &save
->ds
;
797 case VCPU_SREG_ES
: return &save
->es
;
798 case VCPU_SREG_FS
: return &save
->fs
;
799 case VCPU_SREG_GS
: return &save
->gs
;
800 case VCPU_SREG_SS
: return &save
->ss
;
801 case VCPU_SREG_TR
: return &save
->tr
;
802 case VCPU_SREG_LDTR
: return &save
->ldtr
;
808 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
810 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
815 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
816 struct kvm_segment
*var
, int seg
)
818 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
821 var
->limit
= s
->limit
;
822 var
->selector
= s
->selector
;
823 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
824 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
825 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
826 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
827 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
828 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
829 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
830 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
832 /* AMD's VMCB does not have an explicit unusable field, so emulate it
833 * for cross vendor migration purposes by "not present"
835 var
->unusable
= !var
->present
|| (var
->type
== 0);
840 * SVM always stores 0 for the 'G' bit in the CS selector in
841 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
842 * Intel's VMENTRY has a check on the 'G' bit.
844 var
->g
= s
->limit
> 0xfffff;
848 * Work around a bug where the busy flag in the tr selector
858 * The accessed bit must always be set in the segment
859 * descriptor cache, although it can be cleared in the
860 * descriptor, the cached bit always remains at 1. Since
861 * Intel has a check on this, set it here to support
862 * cross-vendor migration.
868 /* On AMD CPUs sometimes the DB bit in the segment
869 * descriptor is left as 1, although the whole segment has
870 * been made unusable. Clear it here to pass an Intel VMX
871 * entry check when cross vendor migrating.
879 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
881 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
886 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
888 struct vcpu_svm
*svm
= to_svm(vcpu
);
890 dt
->limit
= svm
->vmcb
->save
.idtr
.limit
;
891 dt
->base
= svm
->vmcb
->save
.idtr
.base
;
894 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
896 struct vcpu_svm
*svm
= to_svm(vcpu
);
898 svm
->vmcb
->save
.idtr
.limit
= dt
->limit
;
899 svm
->vmcb
->save
.idtr
.base
= dt
->base
;
902 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
904 struct vcpu_svm
*svm
= to_svm(vcpu
);
906 dt
->limit
= svm
->vmcb
->save
.gdtr
.limit
;
907 dt
->base
= svm
->vmcb
->save
.gdtr
.base
;
910 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
912 struct vcpu_svm
*svm
= to_svm(vcpu
);
914 svm
->vmcb
->save
.gdtr
.limit
= dt
->limit
;
915 svm
->vmcb
->save
.gdtr
.base
= dt
->base
;
918 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
922 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
924 struct vcpu_svm
*svm
= to_svm(vcpu
);
927 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
928 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
929 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
930 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
933 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
934 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
935 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
942 if ((vcpu
->arch
.cr0
& X86_CR0_TS
) && !(cr0
& X86_CR0_TS
)) {
943 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
944 vcpu
->fpu_active
= 1;
947 vcpu
->arch
.cr0
= cr0
;
948 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
949 if (!vcpu
->fpu_active
) {
950 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
955 * re-enable caching here because the QEMU bios
956 * does not do it - this results in some delay at
959 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
960 svm
->vmcb
->save
.cr0
= cr0
;
963 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
965 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
966 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
968 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
969 force_new_asid(vcpu
);
971 vcpu
->arch
.cr4
= cr4
;
975 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
978 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
979 struct kvm_segment
*var
, int seg
)
981 struct vcpu_svm
*svm
= to_svm(vcpu
);
982 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
985 s
->limit
= var
->limit
;
986 s
->selector
= var
->selector
;
990 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
991 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
992 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
993 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
994 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
995 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
996 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
997 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
999 if (seg
== VCPU_SREG_CS
)
1001 = (svm
->vmcb
->save
.cs
.attrib
1002 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1006 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1008 struct vcpu_svm
*svm
= to_svm(vcpu
);
1010 svm
->vmcb
->control
.intercept_exceptions
&=
1011 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1013 if (vcpu
->arch
.singlestep
)
1014 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1016 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1017 if (vcpu
->guest_debug
&
1018 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1019 svm
->vmcb
->control
.intercept_exceptions
|=
1021 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1022 svm
->vmcb
->control
.intercept_exceptions
|=
1025 vcpu
->guest_debug
= 0;
1028 static int svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1030 int old_debug
= vcpu
->guest_debug
;
1031 struct vcpu_svm
*svm
= to_svm(vcpu
);
1033 vcpu
->guest_debug
= dbg
->control
;
1035 update_db_intercept(vcpu
);
1037 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1038 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1040 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1042 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1043 svm
->vmcb
->save
.rflags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1044 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1045 svm
->vmcb
->save
.rflags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1050 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1052 #ifdef CONFIG_X86_64
1053 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1057 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1059 #ifdef CONFIG_X86_64
1060 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1064 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*svm_data
)
1066 if (svm_data
->next_asid
> svm_data
->max_asid
) {
1067 ++svm_data
->asid_generation
;
1068 svm_data
->next_asid
= 1;
1069 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1072 svm
->asid_generation
= svm_data
->asid_generation
;
1073 svm
->vmcb
->control
.asid
= svm_data
->next_asid
++;
1076 static unsigned long svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
)
1078 struct vcpu_svm
*svm
= to_svm(vcpu
);
1083 val
= vcpu
->arch
.db
[dr
];
1086 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1087 val
= vcpu
->arch
.dr6
;
1089 val
= svm
->vmcb
->save
.dr6
;
1092 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1093 val
= vcpu
->arch
.dr7
;
1095 val
= svm
->vmcb
->save
.dr7
;
1101 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
1105 static void svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
,
1108 struct vcpu_svm
*svm
= to_svm(vcpu
);
1110 KVMTRACE_2D(DR_WRITE
, vcpu
, (u32
)dr
, (u32
)value
, handler
);
1116 vcpu
->arch
.db
[dr
] = value
;
1117 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
1118 vcpu
->arch
.eff_db
[dr
] = value
;
1121 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
1122 *exception
= UD_VECTOR
;
1125 if (value
& 0xffffffff00000000ULL
) {
1126 *exception
= GP_VECTOR
;
1129 vcpu
->arch
.dr6
= (value
& DR6_VOLATILE
) | DR6_FIXED_1
;
1132 if (value
& 0xffffffff00000000ULL
) {
1133 *exception
= GP_VECTOR
;
1136 vcpu
->arch
.dr7
= (value
& DR7_VOLATILE
) | DR7_FIXED_1
;
1137 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
1138 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1139 vcpu
->arch
.switch_db_regs
= (value
& DR7_BP_EN_MASK
);
1143 /* FIXME: Possible case? */
1144 printk(KERN_DEBUG
"%s: unexpected dr %u\n",
1146 *exception
= UD_VECTOR
;
1151 static int pf_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1156 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1157 error_code
= svm
->vmcb
->control
.exit_info_1
;
1160 KVMTRACE_3D(PAGE_FAULT
, &svm
->vcpu
, error_code
,
1161 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1164 KVMTRACE_3D(TDP_FAULT
, &svm
->vcpu
, error_code
,
1165 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1168 * FIXME: Tis shouldn't be necessary here, but there is a flush
1169 * missing in the MMU code. Until we find this bug, flush the
1170 * complete TLB here on an NPF
1173 svm_flush_tlb(&svm
->vcpu
);
1175 if (kvm_event_needs_reinjection(&svm
->vcpu
))
1176 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1178 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1181 static int db_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1183 if (!(svm
->vcpu
.guest_debug
&
1184 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1185 !svm
->vcpu
.arch
.singlestep
) {
1186 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1190 if (svm
->vcpu
.arch
.singlestep
) {
1191 svm
->vcpu
.arch
.singlestep
= false;
1192 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1193 svm
->vmcb
->save
.rflags
&=
1194 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1195 update_db_intercept(&svm
->vcpu
);
1198 if (svm
->vcpu
.guest_debug
&
1199 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)){
1200 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1201 kvm_run
->debug
.arch
.pc
=
1202 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1203 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1210 static int bp_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1212 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1213 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1214 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1218 static int ud_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1222 er
= emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1223 if (er
!= EMULATE_DONE
)
1224 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1228 static int nm_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1230 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1231 if (!(svm
->vcpu
.arch
.cr0
& X86_CR0_TS
))
1232 svm
->vmcb
->save
.cr0
&= ~X86_CR0_TS
;
1233 svm
->vcpu
.fpu_active
= 1;
1238 static int mc_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1241 * On an #MC intercept the MCE handler is not called automatically in
1242 * the host. So do it by hand here.
1246 /* not sure if we ever come back to this point */
1251 static int shutdown_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1254 * VMCB is undefined after a SHUTDOWN intercept
1255 * so reinitialize it.
1257 clear_page(svm
->vmcb
);
1260 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1264 static int io_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1266 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1267 int size
, in
, string
;
1270 ++svm
->vcpu
.stat
.io_exits
;
1272 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1274 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1277 if (emulate_instruction(&svm
->vcpu
,
1278 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1283 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1284 port
= io_info
>> 16;
1285 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1287 skip_emulated_instruction(&svm
->vcpu
);
1288 return kvm_emulate_pio(&svm
->vcpu
, kvm_run
, in
, size
, port
);
1291 static int nmi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1293 KVMTRACE_0D(NMI
, &svm
->vcpu
, handler
);
1297 static int intr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1299 ++svm
->vcpu
.stat
.irq_exits
;
1300 KVMTRACE_0D(INTR
, &svm
->vcpu
, handler
);
1304 static int nop_on_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1309 static int halt_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1311 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1312 skip_emulated_instruction(&svm
->vcpu
);
1313 return kvm_emulate_halt(&svm
->vcpu
);
1316 static int vmmcall_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1318 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1319 skip_emulated_instruction(&svm
->vcpu
);
1320 kvm_emulate_hypercall(&svm
->vcpu
);
1324 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1326 if (!(svm
->vcpu
.arch
.shadow_efer
& EFER_SVME
)
1327 || !is_paging(&svm
->vcpu
)) {
1328 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1332 if (svm
->vmcb
->save
.cpl
) {
1333 kvm_inject_gp(&svm
->vcpu
, 0);
1340 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1341 bool has_error_code
, u32 error_code
)
1343 if (is_nested(svm
)) {
1344 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1345 svm
->vmcb
->control
.exit_code_hi
= 0;
1346 svm
->vmcb
->control
.exit_info_1
= error_code
;
1347 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1348 if (nested_svm_exit_handled(svm
, false)) {
1349 nsvm_printk("VMexit -> EXCP 0x%x\n", nr
);
1351 nested_svm_vmexit(svm
);
1359 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1361 if (is_nested(svm
)) {
1362 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1365 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1368 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1370 if (nested_svm_exit_handled(svm
, false)) {
1371 nsvm_printk("VMexit -> INTR\n");
1372 nested_svm_vmexit(svm
);
1380 static struct page
*nested_svm_get_page(struct vcpu_svm
*svm
, u64 gpa
)
1384 down_read(¤t
->mm
->mmap_sem
);
1385 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1386 up_read(¤t
->mm
->mmap_sem
);
1388 if (is_error_page(page
)) {
1389 printk(KERN_INFO
"%s: could not find page at 0x%llx\n",
1391 kvm_release_page_clean(page
);
1392 kvm_inject_gp(&svm
->vcpu
, 0);
1398 static int nested_svm_do(struct vcpu_svm
*svm
,
1399 u64 arg1_gpa
, u64 arg2_gpa
, void *opaque
,
1400 int (*handler
)(struct vcpu_svm
*svm
,
1405 struct page
*arg1_page
;
1406 struct page
*arg2_page
= NULL
;
1411 arg1_page
= nested_svm_get_page(svm
, arg1_gpa
);
1412 if(arg1_page
== NULL
)
1416 arg2_page
= nested_svm_get_page(svm
, arg2_gpa
);
1417 if(arg2_page
== NULL
) {
1418 kvm_release_page_clean(arg1_page
);
1423 arg1
= kmap_atomic(arg1_page
, KM_USER0
);
1425 arg2
= kmap_atomic(arg2_page
, KM_USER1
);
1427 retval
= handler(svm
, arg1
, arg2
, opaque
);
1429 kunmap_atomic(arg1
, KM_USER0
);
1431 kunmap_atomic(arg2
, KM_USER1
);
1433 kvm_release_page_dirty(arg1_page
);
1435 kvm_release_page_dirty(arg2_page
);
1440 static int nested_svm_exit_handled_real(struct vcpu_svm
*svm
,
1445 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1446 bool kvm_overrides
= *(bool *)opaque
;
1447 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1449 if (kvm_overrides
) {
1450 switch (exit_code
) {
1454 /* For now we are always handling NPFs when using them */
1459 /* When we're shadowing, trap PFs */
1460 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1469 switch (exit_code
) {
1470 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1471 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1472 if (nested_vmcb
->control
.intercept_cr_read
& cr_bits
)
1476 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1477 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1478 if (nested_vmcb
->control
.intercept_cr_write
& cr_bits
)
1482 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1483 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1484 if (nested_vmcb
->control
.intercept_dr_read
& dr_bits
)
1488 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1489 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1490 if (nested_vmcb
->control
.intercept_dr_write
& dr_bits
)
1494 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1495 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1496 if (nested_vmcb
->control
.intercept_exceptions
& excp_bits
)
1501 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1502 nsvm_printk("exit code: 0x%x\n", exit_code
);
1503 if (nested_vmcb
->control
.intercept
& exit_bits
)
1511 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
,
1512 void *arg1
, void *arg2
,
1515 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1516 u8
*msrpm
= (u8
*)arg2
;
1518 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1519 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1521 if (!(nested_vmcb
->control
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1529 case 0xc0000000 ... 0xc0001fff:
1530 t0
= (8192 + msr
- 0xc0000000) * 2;
1534 case 0xc0010000 ... 0xc0011fff:
1535 t0
= (16384 + msr
- 0xc0010000) * 2;
1543 if (msrpm
[t1
] & ((1 << param
) << t0
))
1549 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
)
1551 bool k
= kvm_override
;
1553 switch (svm
->vmcb
->control
.exit_code
) {
1555 return nested_svm_do(svm
, svm
->nested_vmcb
,
1556 svm
->nested_vmcb_msrpm
, NULL
,
1557 nested_svm_exit_handled_msr
);
1561 return nested_svm_do(svm
, svm
->nested_vmcb
, 0, &k
,
1562 nested_svm_exit_handled_real
);
1565 static int nested_svm_vmexit_real(struct vcpu_svm
*svm
, void *arg1
,
1566 void *arg2
, void *opaque
)
1568 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1569 struct vmcb
*hsave
= svm
->hsave
;
1570 u64 nested_save
[] = { nested_vmcb
->save
.cr0
,
1571 nested_vmcb
->save
.cr3
,
1572 nested_vmcb
->save
.cr4
,
1573 nested_vmcb
->save
.efer
,
1574 nested_vmcb
->control
.intercept_cr_read
,
1575 nested_vmcb
->control
.intercept_cr_write
,
1576 nested_vmcb
->control
.intercept_dr_read
,
1577 nested_vmcb
->control
.intercept_dr_write
,
1578 nested_vmcb
->control
.intercept_exceptions
,
1579 nested_vmcb
->control
.intercept
,
1580 nested_vmcb
->control
.msrpm_base_pa
,
1581 nested_vmcb
->control
.iopm_base_pa
,
1582 nested_vmcb
->control
.tsc_offset
};
1584 /* Give the current vmcb to the guest */
1585 memcpy(nested_vmcb
, svm
->vmcb
, sizeof(struct vmcb
));
1586 nested_vmcb
->save
.cr0
= nested_save
[0];
1588 nested_vmcb
->save
.cr3
= nested_save
[1];
1589 nested_vmcb
->save
.cr4
= nested_save
[2];
1590 nested_vmcb
->save
.efer
= nested_save
[3];
1591 nested_vmcb
->control
.intercept_cr_read
= nested_save
[4];
1592 nested_vmcb
->control
.intercept_cr_write
= nested_save
[5];
1593 nested_vmcb
->control
.intercept_dr_read
= nested_save
[6];
1594 nested_vmcb
->control
.intercept_dr_write
= nested_save
[7];
1595 nested_vmcb
->control
.intercept_exceptions
= nested_save
[8];
1596 nested_vmcb
->control
.intercept
= nested_save
[9];
1597 nested_vmcb
->control
.msrpm_base_pa
= nested_save
[10];
1598 nested_vmcb
->control
.iopm_base_pa
= nested_save
[11];
1599 nested_vmcb
->control
.tsc_offset
= nested_save
[12];
1601 /* We always set V_INTR_MASKING and remember the old value in hflags */
1602 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1603 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1605 if ((nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) &&
1606 (nested_vmcb
->control
.int_vector
)) {
1607 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1608 nested_vmcb
->control
.int_vector
);
1611 /* Restore the original control entries */
1612 svm
->vmcb
->control
= hsave
->control
;
1614 /* Kill any pending exceptions */
1615 if (svm
->vcpu
.arch
.exception
.pending
== true)
1616 nsvm_printk("WARNING: Pending Exception\n");
1617 svm
->vcpu
.arch
.exception
.pending
= false;
1619 /* Restore selected save entries */
1620 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1621 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1622 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1623 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1624 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1625 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1626 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1627 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1628 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1629 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1631 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1632 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1634 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1636 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1637 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1638 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1639 svm
->vmcb
->save
.dr7
= 0;
1640 svm
->vmcb
->save
.cpl
= 0;
1641 svm
->vmcb
->control
.exit_int_info
= 0;
1643 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1644 /* Exit nested SVM mode */
1645 svm
->nested_vmcb
= 0;
1650 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1652 nsvm_printk("VMexit\n");
1653 if (nested_svm_do(svm
, svm
->nested_vmcb
, 0,
1654 NULL
, nested_svm_vmexit_real
))
1657 kvm_mmu_reset_context(&svm
->vcpu
);
1658 kvm_mmu_load(&svm
->vcpu
);
1663 static int nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
, void *arg1
,
1664 void *arg2
, void *opaque
)
1667 u32
*nested_msrpm
= (u32
*)arg1
;
1668 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1669 svm
->nested_msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1670 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested_msrpm
);
1675 static int nested_svm_vmrun(struct vcpu_svm
*svm
, void *arg1
,
1676 void *arg2
, void *opaque
)
1678 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1679 struct vmcb
*hsave
= svm
->hsave
;
1681 /* nested_vmcb is our indicator if nested SVM is activated */
1682 svm
->nested_vmcb
= svm
->vmcb
->save
.rax
;
1684 /* Clear internal status */
1685 svm
->vcpu
.arch
.exception
.pending
= false;
1687 /* Save the old vmcb, so we don't need to pick what we save, but
1688 can restore everything when a VMEXIT occurs */
1689 memcpy(hsave
, svm
->vmcb
, sizeof(struct vmcb
));
1690 /* We need to remember the original CR3 in the SPT case */
1692 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1693 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1694 hsave
->save
.rip
= svm
->next_rip
;
1696 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1697 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1699 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1701 /* Load the nested guest state */
1702 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1703 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1704 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1705 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1706 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1707 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1708 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1709 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1710 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1711 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1713 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1714 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1716 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1717 kvm_mmu_reset_context(&svm
->vcpu
);
1719 svm
->vmcb
->save
.cr2
= nested_vmcb
->save
.cr2
;
1720 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1721 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1722 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1723 /* In case we don't even reach vcpu_run, the fields are not updated */
1724 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1725 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1726 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1727 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1728 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1729 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1731 /* We don't want a nested guest to be more powerful than the guest,
1732 so all intercepts are ORed */
1733 svm
->vmcb
->control
.intercept_cr_read
|=
1734 nested_vmcb
->control
.intercept_cr_read
;
1735 svm
->vmcb
->control
.intercept_cr_write
|=
1736 nested_vmcb
->control
.intercept_cr_write
;
1737 svm
->vmcb
->control
.intercept_dr_read
|=
1738 nested_vmcb
->control
.intercept_dr_read
;
1739 svm
->vmcb
->control
.intercept_dr_write
|=
1740 nested_vmcb
->control
.intercept_dr_write
;
1741 svm
->vmcb
->control
.intercept_exceptions
|=
1742 nested_vmcb
->control
.intercept_exceptions
;
1744 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1746 svm
->nested_vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1748 force_new_asid(&svm
->vcpu
);
1749 svm
->vmcb
->control
.exit_int_info
= nested_vmcb
->control
.exit_int_info
;
1750 svm
->vmcb
->control
.exit_int_info_err
= nested_vmcb
->control
.exit_int_info_err
;
1751 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1752 if (nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) {
1753 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1754 nested_vmcb
->control
.int_ctl
);
1756 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1757 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1759 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1761 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1762 nested_vmcb
->control
.exit_int_info
,
1763 nested_vmcb
->control
.int_state
);
1765 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1766 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1767 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1768 if (nested_vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)
1769 nsvm_printk("Injecting Event: 0x%x\n",
1770 nested_vmcb
->control
.event_inj
);
1771 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1772 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1774 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1779 static int nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1781 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1782 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1783 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1784 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1785 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1786 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1787 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1788 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1789 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1790 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1791 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1792 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1797 static int nested_svm_vmload(struct vcpu_svm
*svm
, void *nested_vmcb
,
1798 void *arg2
, void *opaque
)
1800 return nested_svm_vmloadsave((struct vmcb
*)nested_vmcb
, svm
->vmcb
);
1803 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
1804 void *arg2
, void *opaque
)
1806 return nested_svm_vmloadsave(svm
->vmcb
, (struct vmcb
*)nested_vmcb
);
1809 static int vmload_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1811 if (nested_svm_check_permissions(svm
))
1814 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1815 skip_emulated_instruction(&svm
->vcpu
);
1817 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmload
);
1822 static int vmsave_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1824 if (nested_svm_check_permissions(svm
))
1827 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1828 skip_emulated_instruction(&svm
->vcpu
);
1830 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmsave
);
1835 static int vmrun_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1837 nsvm_printk("VMrun\n");
1838 if (nested_svm_check_permissions(svm
))
1841 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1842 skip_emulated_instruction(&svm
->vcpu
);
1844 if (nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0,
1845 NULL
, nested_svm_vmrun
))
1848 if (nested_svm_do(svm
, svm
->nested_vmcb_msrpm
, 0,
1849 NULL
, nested_svm_vmrun_msrpm
))
1855 static int stgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1857 if (nested_svm_check_permissions(svm
))
1860 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1861 skip_emulated_instruction(&svm
->vcpu
);
1863 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1868 static int clgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1870 if (nested_svm_check_permissions(svm
))
1873 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1874 skip_emulated_instruction(&svm
->vcpu
);
1876 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1878 /* After a CLGI no interrupts should come */
1879 svm_clear_vintr(svm
);
1880 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
1885 static int invalid_op_interception(struct vcpu_svm
*svm
,
1886 struct kvm_run
*kvm_run
)
1888 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1892 static int task_switch_interception(struct vcpu_svm
*svm
,
1893 struct kvm_run
*kvm_run
)
1897 int int_type
= svm
->vmcb
->control
.exit_int_info
&
1898 SVM_EXITINTINFO_TYPE_MASK
;
1899 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
1901 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
1903 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
1905 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
1907 if (svm
->vmcb
->control
.exit_info_2
&
1908 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
1909 reason
= TASK_SWITCH_IRET
;
1910 else if (svm
->vmcb
->control
.exit_info_2
&
1911 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
1912 reason
= TASK_SWITCH_JMP
;
1914 reason
= TASK_SWITCH_GATE
;
1916 reason
= TASK_SWITCH_CALL
;
1918 if (reason
== TASK_SWITCH_GATE
) {
1920 case SVM_EXITINTINFO_TYPE_NMI
:
1921 svm
->vcpu
.arch
.nmi_injected
= false;
1923 case SVM_EXITINTINFO_TYPE_EXEPT
:
1924 kvm_clear_exception_queue(&svm
->vcpu
);
1926 case SVM_EXITINTINFO_TYPE_INTR
:
1927 kvm_clear_interrupt_queue(&svm
->vcpu
);
1934 if (reason
!= TASK_SWITCH_GATE
||
1935 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
1936 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
1937 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
1938 skip_emulated_instruction(&svm
->vcpu
);
1940 return kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
);
1943 static int cpuid_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1945 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1946 kvm_emulate_cpuid(&svm
->vcpu
);
1950 static int iret_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1952 ++svm
->vcpu
.stat
.nmi_window_exits
;
1953 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
1954 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
1958 static int invlpg_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1960 if (emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, 0) != EMULATE_DONE
)
1961 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1965 static int emulate_on_interception(struct vcpu_svm
*svm
,
1966 struct kvm_run
*kvm_run
)
1968 if (emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0) != EMULATE_DONE
)
1969 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1973 static int cr8_write_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1975 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
1976 /* instruction emulation calls kvm_set_cr8() */
1977 emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0);
1978 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
1979 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
1982 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
1984 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
1988 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
1990 struct vcpu_svm
*svm
= to_svm(vcpu
);
1993 case MSR_IA32_TSC
: {
1997 *data
= svm
->vmcb
->control
.tsc_offset
+ tsc
;
2001 *data
= svm
->vmcb
->save
.star
;
2003 #ifdef CONFIG_X86_64
2005 *data
= svm
->vmcb
->save
.lstar
;
2008 *data
= svm
->vmcb
->save
.cstar
;
2010 case MSR_KERNEL_GS_BASE
:
2011 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2013 case MSR_SYSCALL_MASK
:
2014 *data
= svm
->vmcb
->save
.sfmask
;
2017 case MSR_IA32_SYSENTER_CS
:
2018 *data
= svm
->vmcb
->save
.sysenter_cs
;
2020 case MSR_IA32_SYSENTER_EIP
:
2021 *data
= svm
->sysenter_eip
;
2023 case MSR_IA32_SYSENTER_ESP
:
2024 *data
= svm
->sysenter_esp
;
2026 /* Nobody will change the following 5 values in the VMCB so
2027 we can safely return them on rdmsr. They will always be 0
2028 until LBRV is implemented. */
2029 case MSR_IA32_DEBUGCTLMSR
:
2030 *data
= svm
->vmcb
->save
.dbgctl
;
2032 case MSR_IA32_LASTBRANCHFROMIP
:
2033 *data
= svm
->vmcb
->save
.br_from
;
2035 case MSR_IA32_LASTBRANCHTOIP
:
2036 *data
= svm
->vmcb
->save
.br_to
;
2038 case MSR_IA32_LASTINTFROMIP
:
2039 *data
= svm
->vmcb
->save
.last_excp_from
;
2041 case MSR_IA32_LASTINTTOIP
:
2042 *data
= svm
->vmcb
->save
.last_excp_to
;
2044 case MSR_VM_HSAVE_PA
:
2045 *data
= svm
->hsave_msr
;
2050 case MSR_IA32_UCODE_REV
:
2054 return kvm_get_msr_common(vcpu
, ecx
, data
);
2059 static int rdmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2061 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2064 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
))
2065 kvm_inject_gp(&svm
->vcpu
, 0);
2067 KVMTRACE_3D(MSR_READ
, &svm
->vcpu
, ecx
, (u32
)data
,
2068 (u32
)(data
>> 32), handler
);
2070 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2071 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2072 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2073 skip_emulated_instruction(&svm
->vcpu
);
2078 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2080 struct vcpu_svm
*svm
= to_svm(vcpu
);
2083 case MSR_IA32_TSC
: {
2087 svm
->vmcb
->control
.tsc_offset
= data
- tsc
;
2091 svm
->vmcb
->save
.star
= data
;
2093 #ifdef CONFIG_X86_64
2095 svm
->vmcb
->save
.lstar
= data
;
2098 svm
->vmcb
->save
.cstar
= data
;
2100 case MSR_KERNEL_GS_BASE
:
2101 svm
->vmcb
->save
.kernel_gs_base
= data
;
2103 case MSR_SYSCALL_MASK
:
2104 svm
->vmcb
->save
.sfmask
= data
;
2107 case MSR_IA32_SYSENTER_CS
:
2108 svm
->vmcb
->save
.sysenter_cs
= data
;
2110 case MSR_IA32_SYSENTER_EIP
:
2111 svm
->sysenter_eip
= data
;
2112 svm
->vmcb
->save
.sysenter_eip
= data
;
2114 case MSR_IA32_SYSENTER_ESP
:
2115 svm
->sysenter_esp
= data
;
2116 svm
->vmcb
->save
.sysenter_esp
= data
;
2118 case MSR_IA32_DEBUGCTLMSR
:
2119 if (!svm_has(SVM_FEATURE_LBRV
)) {
2120 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2124 if (data
& DEBUGCTL_RESERVED_BITS
)
2127 svm
->vmcb
->save
.dbgctl
= data
;
2128 if (data
& (1ULL<<0))
2129 svm_enable_lbrv(svm
);
2131 svm_disable_lbrv(svm
);
2133 case MSR_K7_EVNTSEL0
:
2134 case MSR_K7_EVNTSEL1
:
2135 case MSR_K7_EVNTSEL2
:
2136 case MSR_K7_EVNTSEL3
:
2137 case MSR_K7_PERFCTR0
:
2138 case MSR_K7_PERFCTR1
:
2139 case MSR_K7_PERFCTR2
:
2140 case MSR_K7_PERFCTR3
:
2142 * Just discard all writes to the performance counters; this
2143 * should keep both older linux and windows 64-bit guests
2146 pr_unimpl(vcpu
, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2149 case MSR_VM_HSAVE_PA
:
2150 svm
->hsave_msr
= data
;
2153 return kvm_set_msr_common(vcpu
, ecx
, data
);
2158 static int wrmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2160 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2161 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2162 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2164 KVMTRACE_3D(MSR_WRITE
, &svm
->vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2167 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2168 if (svm_set_msr(&svm
->vcpu
, ecx
, data
))
2169 kvm_inject_gp(&svm
->vcpu
, 0);
2171 skip_emulated_instruction(&svm
->vcpu
);
2175 static int msr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2177 if (svm
->vmcb
->control
.exit_info_1
)
2178 return wrmsr_interception(svm
, kvm_run
);
2180 return rdmsr_interception(svm
, kvm_run
);
2183 static int interrupt_window_interception(struct vcpu_svm
*svm
,
2184 struct kvm_run
*kvm_run
)
2186 KVMTRACE_0D(PEND_INTR
, &svm
->vcpu
, handler
);
2188 svm_clear_vintr(svm
);
2189 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2191 * If the user space waits to inject interrupts, exit as soon as
2194 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2195 kvm_run
->request_interrupt_window
&&
2196 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2197 ++svm
->vcpu
.stat
.irq_window_exits
;
2198 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2205 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
,
2206 struct kvm_run
*kvm_run
) = {
2207 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2208 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2209 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2210 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2212 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2213 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2214 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2215 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2216 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2217 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2218 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2219 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2220 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2221 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2222 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2223 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2224 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2225 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2226 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2227 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2228 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2229 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2230 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2231 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2232 [SVM_EXIT_INTR
] = intr_interception
,
2233 [SVM_EXIT_NMI
] = nmi_interception
,
2234 [SVM_EXIT_SMI
] = nop_on_interception
,
2235 [SVM_EXIT_INIT
] = nop_on_interception
,
2236 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2237 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2238 [SVM_EXIT_CPUID
] = cpuid_interception
,
2239 [SVM_EXIT_IRET
] = iret_interception
,
2240 [SVM_EXIT_INVD
] = emulate_on_interception
,
2241 [SVM_EXIT_HLT
] = halt_interception
,
2242 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2243 [SVM_EXIT_INVLPGA
] = invalid_op_interception
,
2244 [SVM_EXIT_IOIO
] = io_interception
,
2245 [SVM_EXIT_MSR
] = msr_interception
,
2246 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2247 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2248 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2249 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2250 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2251 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2252 [SVM_EXIT_STGI
] = stgi_interception
,
2253 [SVM_EXIT_CLGI
] = clgi_interception
,
2254 [SVM_EXIT_SKINIT
] = invalid_op_interception
,
2255 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2256 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2257 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2258 [SVM_EXIT_NPF
] = pf_interception
,
2261 static int handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2263 struct vcpu_svm
*svm
= to_svm(vcpu
);
2264 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2266 KVMTRACE_3D(VMEXIT
, vcpu
, exit_code
, (u32
)svm
->vmcb
->save
.rip
,
2267 (u32
)((u64
)svm
->vmcb
->save
.rip
>> 32), entryexit
);
2269 if (is_nested(svm
)) {
2270 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2271 exit_code
, svm
->vmcb
->control
.exit_info_1
,
2272 svm
->vmcb
->control
.exit_info_2
, svm
->vmcb
->save
.rip
);
2273 if (nested_svm_exit_handled(svm
, true)) {
2274 nested_svm_vmexit(svm
);
2275 nsvm_printk("-> #VMEXIT\n");
2282 if ((vcpu
->arch
.cr0
^ svm
->vmcb
->save
.cr0
) & X86_CR0_PG
) {
2283 svm_set_cr0(vcpu
, svm
->vmcb
->save
.cr0
);
2286 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2287 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2288 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2289 if (!load_pdptrs(vcpu
, vcpu
->arch
.cr3
)) {
2290 kvm_inject_gp(vcpu
, 0);
2295 kvm_mmu_reset_context(vcpu
);
2301 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2302 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2303 kvm_run
->fail_entry
.hardware_entry_failure_reason
2304 = svm
->vmcb
->control
.exit_code
;
2308 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2309 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2310 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2311 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2313 __func__
, svm
->vmcb
->control
.exit_int_info
,
2316 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2317 || !svm_exit_handlers
[exit_code
]) {
2318 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2319 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2323 return svm_exit_handlers
[exit_code
](svm
, kvm_run
);
2326 static void reload_tss(struct kvm_vcpu
*vcpu
)
2328 int cpu
= raw_smp_processor_id();
2330 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2331 svm_data
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2335 static void pre_svm_run(struct vcpu_svm
*svm
)
2337 int cpu
= raw_smp_processor_id();
2339 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2341 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2342 /* FIXME: handle wraparound of asid_generation */
2343 if (svm
->asid_generation
!= svm_data
->asid_generation
)
2344 new_asid(svm
, svm_data
);
2347 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2349 struct vcpu_svm
*svm
= to_svm(vcpu
);
2351 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2352 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2353 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2354 ++vcpu
->stat
.nmi_injections
;
2357 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2359 struct vmcb_control_area
*control
;
2361 KVMTRACE_1D(INJ_VIRQ
, &svm
->vcpu
, (u32
)irq
, handler
);
2363 ++svm
->vcpu
.stat
.irq_injections
;
2364 control
= &svm
->vmcb
->control
;
2365 control
->int_vector
= irq
;
2366 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2367 control
->int_ctl
|= V_IRQ_MASK
|
2368 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2371 static void svm_queue_irq(struct kvm_vcpu
*vcpu
, unsigned nr
)
2373 struct vcpu_svm
*svm
= to_svm(vcpu
);
2375 svm
->vmcb
->control
.event_inj
= nr
|
2376 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2379 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2381 struct vcpu_svm
*svm
= to_svm(vcpu
);
2383 nested_svm_intr(svm
);
2385 svm_queue_irq(vcpu
, vcpu
->arch
.interrupt
.nr
);
2388 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2390 struct vcpu_svm
*svm
= to_svm(vcpu
);
2396 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2399 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2401 struct vcpu_svm
*svm
= to_svm(vcpu
);
2402 struct vmcb
*vmcb
= svm
->vmcb
;
2403 return !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2404 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2407 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2409 struct vcpu_svm
*svm
= to_svm(vcpu
);
2410 struct vmcb
*vmcb
= svm
->vmcb
;
2411 return (vmcb
->save
.rflags
& X86_EFLAGS_IF
) &&
2412 !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2413 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
2416 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2418 svm_set_vintr(to_svm(vcpu
));
2419 svm_inject_irq(to_svm(vcpu
), 0x0);
2422 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2424 struct vcpu_svm
*svm
= to_svm(vcpu
);
2426 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2428 return; /* IRET will cause a vm exit */
2430 /* Something prevents NMI from been injected. Single step over
2431 possible problem (IRET or exception injection or interrupt
2433 vcpu
->arch
.singlestep
= true;
2434 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2435 update_db_intercept(vcpu
);
2438 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2443 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2445 force_new_asid(vcpu
);
2448 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2452 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2454 struct vcpu_svm
*svm
= to_svm(vcpu
);
2456 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2457 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2458 kvm_set_cr8(vcpu
, cr8
);
2462 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2464 struct vcpu_svm
*svm
= to_svm(vcpu
);
2467 cr8
= kvm_get_cr8(vcpu
);
2468 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2469 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2472 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2476 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2478 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2479 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2481 svm
->vcpu
.arch
.nmi_injected
= false;
2482 kvm_clear_exception_queue(&svm
->vcpu
);
2483 kvm_clear_interrupt_queue(&svm
->vcpu
);
2485 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2488 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2489 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2492 case SVM_EXITINTINFO_TYPE_NMI
:
2493 svm
->vcpu
.arch
.nmi_injected
= true;
2495 case SVM_EXITINTINFO_TYPE_EXEPT
:
2496 /* In case of software exception do not reinject an exception
2497 vector, but re-execute and instruction instead */
2498 if (kvm_exception_is_soft(vector
))
2500 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2501 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2502 kvm_queue_exception_e(&svm
->vcpu
, vector
, err
);
2505 kvm_queue_exception(&svm
->vcpu
, vector
);
2507 case SVM_EXITINTINFO_TYPE_INTR
:
2508 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2515 #ifdef CONFIG_X86_64
2521 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2523 struct vcpu_svm
*svm
= to_svm(vcpu
);
2528 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2529 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2530 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2534 sync_lapic_to_cr8(vcpu
);
2536 save_host_msrs(vcpu
);
2537 fs_selector
= kvm_read_fs();
2538 gs_selector
= kvm_read_gs();
2539 ldt_selector
= kvm_read_ldt();
2540 svm
->host_cr2
= kvm_read_cr2();
2541 if (!is_nested(svm
))
2542 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2543 /* required for live migration with NPT */
2545 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2552 "push %%"R
"bp; \n\t"
2553 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2554 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2555 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2556 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2557 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2558 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2559 #ifdef CONFIG_X86_64
2560 "mov %c[r8](%[svm]), %%r8 \n\t"
2561 "mov %c[r9](%[svm]), %%r9 \n\t"
2562 "mov %c[r10](%[svm]), %%r10 \n\t"
2563 "mov %c[r11](%[svm]), %%r11 \n\t"
2564 "mov %c[r12](%[svm]), %%r12 \n\t"
2565 "mov %c[r13](%[svm]), %%r13 \n\t"
2566 "mov %c[r14](%[svm]), %%r14 \n\t"
2567 "mov %c[r15](%[svm]), %%r15 \n\t"
2570 /* Enter guest mode */
2572 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2573 __ex(SVM_VMLOAD
) "\n\t"
2574 __ex(SVM_VMRUN
) "\n\t"
2575 __ex(SVM_VMSAVE
) "\n\t"
2578 /* Save guest registers, load host registers */
2579 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2580 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2581 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2582 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2583 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2584 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2585 #ifdef CONFIG_X86_64
2586 "mov %%r8, %c[r8](%[svm]) \n\t"
2587 "mov %%r9, %c[r9](%[svm]) \n\t"
2588 "mov %%r10, %c[r10](%[svm]) \n\t"
2589 "mov %%r11, %c[r11](%[svm]) \n\t"
2590 "mov %%r12, %c[r12](%[svm]) \n\t"
2591 "mov %%r13, %c[r13](%[svm]) \n\t"
2592 "mov %%r14, %c[r14](%[svm]) \n\t"
2593 "mov %%r15, %c[r15](%[svm]) \n\t"
2598 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2599 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2600 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2601 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2602 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2603 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2604 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2605 #ifdef CONFIG_X86_64
2606 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2607 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2608 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2609 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2610 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2611 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2612 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2613 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2616 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2617 #ifdef CONFIG_X86_64
2618 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2622 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2623 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2624 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2625 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2627 kvm_write_cr2(svm
->host_cr2
);
2629 kvm_load_fs(fs_selector
);
2630 kvm_load_gs(gs_selector
);
2631 kvm_load_ldt(ldt_selector
);
2632 load_host_msrs(vcpu
);
2636 local_irq_disable();
2640 sync_cr8_to_lapic(vcpu
);
2644 svm_complete_interrupts(svm
);
2649 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2651 struct vcpu_svm
*svm
= to_svm(vcpu
);
2654 svm
->vmcb
->control
.nested_cr3
= root
;
2655 force_new_asid(vcpu
);
2659 svm
->vmcb
->save
.cr3
= root
;
2660 force_new_asid(vcpu
);
2662 if (vcpu
->fpu_active
) {
2663 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
2664 svm
->vmcb
->save
.cr0
|= X86_CR0_TS
;
2665 vcpu
->fpu_active
= 0;
2669 static int is_disabled(void)
2673 rdmsrl(MSR_VM_CR
, vm_cr
);
2674 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2681 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2684 * Patch in the VMMCALL instruction:
2686 hypercall
[0] = 0x0f;
2687 hypercall
[1] = 0x01;
2688 hypercall
[2] = 0xd9;
2691 static void svm_check_processor_compat(void *rtn
)
2696 static bool svm_cpu_has_accelerated_tpr(void)
2701 static int get_npt_level(void)
2703 #ifdef CONFIG_X86_64
2704 return PT64_ROOT_LEVEL
;
2706 return PT32E_ROOT_LEVEL
;
2710 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
2715 static struct kvm_x86_ops svm_x86_ops
= {
2716 .cpu_has_kvm_support
= has_svm
,
2717 .disabled_by_bios
= is_disabled
,
2718 .hardware_setup
= svm_hardware_setup
,
2719 .hardware_unsetup
= svm_hardware_unsetup
,
2720 .check_processor_compatibility
= svm_check_processor_compat
,
2721 .hardware_enable
= svm_hardware_enable
,
2722 .hardware_disable
= svm_hardware_disable
,
2723 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2725 .vcpu_create
= svm_create_vcpu
,
2726 .vcpu_free
= svm_free_vcpu
,
2727 .vcpu_reset
= svm_vcpu_reset
,
2729 .prepare_guest_switch
= svm_prepare_guest_switch
,
2730 .vcpu_load
= svm_vcpu_load
,
2731 .vcpu_put
= svm_vcpu_put
,
2733 .set_guest_debug
= svm_guest_debug
,
2734 .get_msr
= svm_get_msr
,
2735 .set_msr
= svm_set_msr
,
2736 .get_segment_base
= svm_get_segment_base
,
2737 .get_segment
= svm_get_segment
,
2738 .set_segment
= svm_set_segment
,
2739 .get_cpl
= svm_get_cpl
,
2740 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
2741 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
2742 .set_cr0
= svm_set_cr0
,
2743 .set_cr3
= svm_set_cr3
,
2744 .set_cr4
= svm_set_cr4
,
2745 .set_efer
= svm_set_efer
,
2746 .get_idt
= svm_get_idt
,
2747 .set_idt
= svm_set_idt
,
2748 .get_gdt
= svm_get_gdt
,
2749 .set_gdt
= svm_set_gdt
,
2750 .get_dr
= svm_get_dr
,
2751 .set_dr
= svm_set_dr
,
2752 .get_rflags
= svm_get_rflags
,
2753 .set_rflags
= svm_set_rflags
,
2755 .tlb_flush
= svm_flush_tlb
,
2757 .run
= svm_vcpu_run
,
2758 .handle_exit
= handle_exit
,
2759 .skip_emulated_instruction
= skip_emulated_instruction
,
2760 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
2761 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
2762 .patch_hypercall
= svm_patch_hypercall
,
2763 .set_irq
= svm_set_irq
,
2764 .set_nmi
= svm_inject_nmi
,
2765 .queue_exception
= svm_queue_exception
,
2766 .interrupt_allowed
= svm_interrupt_allowed
,
2767 .nmi_allowed
= svm_nmi_allowed
,
2768 .enable_nmi_window
= enable_nmi_window
,
2769 .enable_irq_window
= enable_irq_window
,
2770 .update_cr8_intercept
= update_cr8_intercept
,
2772 .set_tss_addr
= svm_set_tss_addr
,
2773 .get_tdp_level
= get_npt_level
,
2774 .get_mt_mask
= svm_get_mt_mask
,
2777 static int __init
svm_init(void)
2779 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
2783 static void __exit
svm_exit(void)
2788 module_init(svm_init
)
2789 module_exit(svm_exit
)