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KVM: Convert intx_mask_lock to spin lock
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
59
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
63
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
65
66 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
67 #define TSC_RATIO_MIN 0x0000000000000001ULL
68 #define TSC_RATIO_MAX 0x000000ffffffffffULL
69
70 static bool erratum_383_found __read_mostly;
71
72 static const u32 host_save_user_msrs[] = {
73 #ifdef CONFIG_X86_64
74 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
75 MSR_FS_BASE,
76 #endif
77 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
78 };
79
80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81
82 struct kvm_vcpu;
83
84 struct nested_state {
85 struct vmcb *hsave;
86 u64 hsave_msr;
87 u64 vm_cr_msr;
88 u64 vmcb;
89
90 /* These are the merged vectors */
91 u32 *msrpm;
92
93 /* gpa pointers to the real vectors */
94 u64 vmcb_msrpm;
95 u64 vmcb_iopm;
96
97 /* A VMEXIT is required but not yet emulated */
98 bool exit_required;
99
100 /* cache for intercepts of the guest */
101 u32 intercept_cr;
102 u32 intercept_dr;
103 u32 intercept_exceptions;
104 u64 intercept;
105
106 /* Nested Paging related state */
107 u64 nested_cr3;
108 };
109
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
113 /*
114 * Set osvw_len to higher value when updated Revision Guides
115 * are published and we know what the new status bits are
116 */
117 static uint64_t osvw_len = 4, osvw_status;
118
119 struct vcpu_svm {
120 struct kvm_vcpu vcpu;
121 struct vmcb *vmcb;
122 unsigned long vmcb_pa;
123 struct svm_cpu_data *svm_data;
124 uint64_t asid_generation;
125 uint64_t sysenter_esp;
126 uint64_t sysenter_eip;
127
128 u64 next_rip;
129
130 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
131 struct {
132 u16 fs;
133 u16 gs;
134 u16 ldt;
135 u64 gs_base;
136 } host;
137
138 u32 *msrpm;
139
140 ulong nmi_iret_rip;
141
142 struct nested_state nested;
143
144 bool nmi_singlestep;
145
146 unsigned int3_injected;
147 unsigned long int3_rip;
148 u32 apf_reason;
149
150 u64 tsc_ratio;
151 };
152
153 static DEFINE_PER_CPU(u64, current_tsc_ratio);
154 #define TSC_RATIO_DEFAULT 0x0100000000ULL
155
156 #define MSR_INVALID 0xffffffffU
157
158 static struct svm_direct_access_msrs {
159 u32 index; /* Index of the MSR */
160 bool always; /* True if intercept is always on */
161 } direct_access_msrs[] = {
162 { .index = MSR_STAR, .always = true },
163 { .index = MSR_IA32_SYSENTER_CS, .always = true },
164 #ifdef CONFIG_X86_64
165 { .index = MSR_GS_BASE, .always = true },
166 { .index = MSR_FS_BASE, .always = true },
167 { .index = MSR_KERNEL_GS_BASE, .always = true },
168 { .index = MSR_LSTAR, .always = true },
169 { .index = MSR_CSTAR, .always = true },
170 { .index = MSR_SYSCALL_MASK, .always = true },
171 #endif
172 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
173 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
174 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
175 { .index = MSR_IA32_LASTINTTOIP, .always = false },
176 { .index = MSR_INVALID, .always = false },
177 };
178
179 /* enable NPT for AMD64 and X86 with PAE */
180 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
181 static bool npt_enabled = true;
182 #else
183 static bool npt_enabled;
184 #endif
185
186 /* allow nested paging (virtualized MMU) for all guests */
187 static int npt = true;
188 module_param(npt, int, S_IRUGO);
189
190 /* allow nested virtualization in KVM/SVM */
191 static int nested = true;
192 module_param(nested, int, S_IRUGO);
193
194 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
195 static void svm_complete_interrupts(struct vcpu_svm *svm);
196
197 static int nested_svm_exit_handled(struct vcpu_svm *svm);
198 static int nested_svm_intercept(struct vcpu_svm *svm);
199 static int nested_svm_vmexit(struct vcpu_svm *svm);
200 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
201 bool has_error_code, u32 error_code);
202 static u64 __scale_tsc(u64 ratio, u64 tsc);
203
204 enum {
205 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
206 pause filter count */
207 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
208 VMCB_ASID, /* ASID */
209 VMCB_INTR, /* int_ctl, int_vector */
210 VMCB_NPT, /* npt_en, nCR3, gPAT */
211 VMCB_CR, /* CR0, CR3, CR4, EFER */
212 VMCB_DR, /* DR6, DR7 */
213 VMCB_DT, /* GDT, IDT */
214 VMCB_SEG, /* CS, DS, SS, ES, CPL */
215 VMCB_CR2, /* CR2 only */
216 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
217 VMCB_DIRTY_MAX,
218 };
219
220 /* TPR and CR2 are always written before VMRUN */
221 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
222
223 static inline void mark_all_dirty(struct vmcb *vmcb)
224 {
225 vmcb->control.clean = 0;
226 }
227
228 static inline void mark_all_clean(struct vmcb *vmcb)
229 {
230 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
231 & ~VMCB_ALWAYS_DIRTY_MASK;
232 }
233
234 static inline void mark_dirty(struct vmcb *vmcb, int bit)
235 {
236 vmcb->control.clean &= ~(1 << bit);
237 }
238
239 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
240 {
241 return container_of(vcpu, struct vcpu_svm, vcpu);
242 }
243
244 static void recalc_intercepts(struct vcpu_svm *svm)
245 {
246 struct vmcb_control_area *c, *h;
247 struct nested_state *g;
248
249 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
250
251 if (!is_guest_mode(&svm->vcpu))
252 return;
253
254 c = &svm->vmcb->control;
255 h = &svm->nested.hsave->control;
256 g = &svm->nested;
257
258 c->intercept_cr = h->intercept_cr | g->intercept_cr;
259 c->intercept_dr = h->intercept_dr | g->intercept_dr;
260 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
261 c->intercept = h->intercept | g->intercept;
262 }
263
264 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
265 {
266 if (is_guest_mode(&svm->vcpu))
267 return svm->nested.hsave;
268 else
269 return svm->vmcb;
270 }
271
272 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
273 {
274 struct vmcb *vmcb = get_host_vmcb(svm);
275
276 vmcb->control.intercept_cr |= (1U << bit);
277
278 recalc_intercepts(svm);
279 }
280
281 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_cr &= ~(1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 return vmcb->control.intercept_cr & (1U << bit);
295 }
296
297 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
298 {
299 struct vmcb *vmcb = get_host_vmcb(svm);
300
301 vmcb->control.intercept_dr |= (1U << bit);
302
303 recalc_intercepts(svm);
304 }
305
306 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
307 {
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept_dr &= ~(1U << bit);
311
312 recalc_intercepts(svm);
313 }
314
315 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
316 {
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept_exceptions |= (1U << bit);
320
321 recalc_intercepts(svm);
322 }
323
324 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
325 {
326 struct vmcb *vmcb = get_host_vmcb(svm);
327
328 vmcb->control.intercept_exceptions &= ~(1U << bit);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void set_intercept(struct vcpu_svm *svm, int bit)
334 {
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept |= (1ULL << bit);
338
339 recalc_intercepts(svm);
340 }
341
342 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
343 {
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept &= ~(1ULL << bit);
347
348 recalc_intercepts(svm);
349 }
350
351 static inline void enable_gif(struct vcpu_svm *svm)
352 {
353 svm->vcpu.arch.hflags |= HF_GIF_MASK;
354 }
355
356 static inline void disable_gif(struct vcpu_svm *svm)
357 {
358 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
359 }
360
361 static inline bool gif_set(struct vcpu_svm *svm)
362 {
363 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
364 }
365
366 static unsigned long iopm_base;
367
368 struct kvm_ldttss_desc {
369 u16 limit0;
370 u16 base0;
371 unsigned base1:8, type:5, dpl:2, p:1;
372 unsigned limit1:4, zero0:3, g:1, base2:8;
373 u32 base3;
374 u32 zero1;
375 } __attribute__((packed));
376
377 struct svm_cpu_data {
378 int cpu;
379
380 u64 asid_generation;
381 u32 max_asid;
382 u32 next_asid;
383 struct kvm_ldttss_desc *tss_desc;
384
385 struct page *save_area;
386 };
387
388 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
389
390 struct svm_init_data {
391 int cpu;
392 int r;
393 };
394
395 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
396
397 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
398 #define MSRS_RANGE_SIZE 2048
399 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
400
401 static u32 svm_msrpm_offset(u32 msr)
402 {
403 u32 offset;
404 int i;
405
406 for (i = 0; i < NUM_MSR_MAPS; i++) {
407 if (msr < msrpm_ranges[i] ||
408 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
409 continue;
410
411 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
412 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
413
414 /* Now we have the u8 offset - but need the u32 offset */
415 return offset / 4;
416 }
417
418 /* MSR not in any range */
419 return MSR_INVALID;
420 }
421
422 #define MAX_INST_SIZE 15
423
424 static inline void clgi(void)
425 {
426 asm volatile (__ex(SVM_CLGI));
427 }
428
429 static inline void stgi(void)
430 {
431 asm volatile (__ex(SVM_STGI));
432 }
433
434 static inline void invlpga(unsigned long addr, u32 asid)
435 {
436 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
437 }
438
439 static int get_npt_level(void)
440 {
441 #ifdef CONFIG_X86_64
442 return PT64_ROOT_LEVEL;
443 #else
444 return PT32E_ROOT_LEVEL;
445 #endif
446 }
447
448 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
449 {
450 vcpu->arch.efer = efer;
451 if (!npt_enabled && !(efer & EFER_LMA))
452 efer &= ~EFER_LME;
453
454 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
455 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
456 }
457
458 static int is_external_interrupt(u32 info)
459 {
460 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
461 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
462 }
463
464 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
465 {
466 struct vcpu_svm *svm = to_svm(vcpu);
467 u32 ret = 0;
468
469 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
470 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
471 return ret & mask;
472 }
473
474 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
475 {
476 struct vcpu_svm *svm = to_svm(vcpu);
477
478 if (mask == 0)
479 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
480 else
481 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
482
483 }
484
485 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
486 {
487 struct vcpu_svm *svm = to_svm(vcpu);
488
489 if (svm->vmcb->control.next_rip != 0)
490 svm->next_rip = svm->vmcb->control.next_rip;
491
492 if (!svm->next_rip) {
493 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
494 EMULATE_DONE)
495 printk(KERN_DEBUG "%s: NOP\n", __func__);
496 return;
497 }
498 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
499 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
500 __func__, kvm_rip_read(vcpu), svm->next_rip);
501
502 kvm_rip_write(vcpu, svm->next_rip);
503 svm_set_interrupt_shadow(vcpu, 0);
504 }
505
506 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
507 bool has_error_code, u32 error_code,
508 bool reinject)
509 {
510 struct vcpu_svm *svm = to_svm(vcpu);
511
512 /*
513 * If we are within a nested VM we'd better #VMEXIT and let the guest
514 * handle the exception
515 */
516 if (!reinject &&
517 nested_svm_check_exception(svm, nr, has_error_code, error_code))
518 return;
519
520 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
521 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
522
523 /*
524 * For guest debugging where we have to reinject #BP if some
525 * INT3 is guest-owned:
526 * Emulate nRIP by moving RIP forward. Will fail if injection
527 * raises a fault that is not intercepted. Still better than
528 * failing in all cases.
529 */
530 skip_emulated_instruction(&svm->vcpu);
531 rip = kvm_rip_read(&svm->vcpu);
532 svm->int3_rip = rip + svm->vmcb->save.cs.base;
533 svm->int3_injected = rip - old_rip;
534 }
535
536 svm->vmcb->control.event_inj = nr
537 | SVM_EVTINJ_VALID
538 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
539 | SVM_EVTINJ_TYPE_EXEPT;
540 svm->vmcb->control.event_inj_err = error_code;
541 }
542
543 static void svm_init_erratum_383(void)
544 {
545 u32 low, high;
546 int err;
547 u64 val;
548
549 if (!cpu_has_amd_erratum(amd_erratum_383))
550 return;
551
552 /* Use _safe variants to not break nested virtualization */
553 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
554 if (err)
555 return;
556
557 val |= (1ULL << 47);
558
559 low = lower_32_bits(val);
560 high = upper_32_bits(val);
561
562 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
563
564 erratum_383_found = true;
565 }
566
567 static void svm_init_osvw(struct kvm_vcpu *vcpu)
568 {
569 /*
570 * Guests should see errata 400 and 415 as fixed (assuming that
571 * HLT and IO instructions are intercepted).
572 */
573 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
574 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
575
576 /*
577 * By increasing VCPU's osvw.length to 3 we are telling the guest that
578 * all osvw.status bits inside that length, including bit 0 (which is
579 * reserved for erratum 298), are valid. However, if host processor's
580 * osvw_len is 0 then osvw_status[0] carries no information. We need to
581 * be conservative here and therefore we tell the guest that erratum 298
582 * is present (because we really don't know).
583 */
584 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
585 vcpu->arch.osvw.status |= 1;
586 }
587
588 static int has_svm(void)
589 {
590 const char *msg;
591
592 if (!cpu_has_svm(&msg)) {
593 printk(KERN_INFO "has_svm: %s\n", msg);
594 return 0;
595 }
596
597 return 1;
598 }
599
600 static void svm_hardware_disable(void *garbage)
601 {
602 /* Make sure we clean up behind us */
603 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
604 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
605
606 cpu_svm_disable();
607 }
608
609 static int svm_hardware_enable(void *garbage)
610 {
611
612 struct svm_cpu_data *sd;
613 uint64_t efer;
614 struct desc_ptr gdt_descr;
615 struct desc_struct *gdt;
616 int me = raw_smp_processor_id();
617
618 rdmsrl(MSR_EFER, efer);
619 if (efer & EFER_SVME)
620 return -EBUSY;
621
622 if (!has_svm()) {
623 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
624 me);
625 return -EINVAL;
626 }
627 sd = per_cpu(svm_data, me);
628
629 if (!sd) {
630 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
631 me);
632 return -EINVAL;
633 }
634
635 sd->asid_generation = 1;
636 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
637 sd->next_asid = sd->max_asid + 1;
638
639 native_store_gdt(&gdt_descr);
640 gdt = (struct desc_struct *)gdt_descr.address;
641 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
642
643 wrmsrl(MSR_EFER, efer | EFER_SVME);
644
645 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
646
647 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
648 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
649 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
650 }
651
652
653 /*
654 * Get OSVW bits.
655 *
656 * Note that it is possible to have a system with mixed processor
657 * revisions and therefore different OSVW bits. If bits are not the same
658 * on different processors then choose the worst case (i.e. if erratum
659 * is present on one processor and not on another then assume that the
660 * erratum is present everywhere).
661 */
662 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
663 uint64_t len, status = 0;
664 int err;
665
666 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
667 if (!err)
668 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
669 &err);
670
671 if (err)
672 osvw_status = osvw_len = 0;
673 else {
674 if (len < osvw_len)
675 osvw_len = len;
676 osvw_status |= status;
677 osvw_status &= (1ULL << osvw_len) - 1;
678 }
679 } else
680 osvw_status = osvw_len = 0;
681
682 svm_init_erratum_383();
683
684 return 0;
685 }
686
687 static void svm_cpu_uninit(int cpu)
688 {
689 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
690
691 if (!sd)
692 return;
693
694 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
695 __free_page(sd->save_area);
696 kfree(sd);
697 }
698
699 static int svm_cpu_init(int cpu)
700 {
701 struct svm_cpu_data *sd;
702 int r;
703
704 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
705 if (!sd)
706 return -ENOMEM;
707 sd->cpu = cpu;
708 sd->save_area = alloc_page(GFP_KERNEL);
709 r = -ENOMEM;
710 if (!sd->save_area)
711 goto err_1;
712
713 per_cpu(svm_data, cpu) = sd;
714
715 return 0;
716
717 err_1:
718 kfree(sd);
719 return r;
720
721 }
722
723 static bool valid_msr_intercept(u32 index)
724 {
725 int i;
726
727 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
728 if (direct_access_msrs[i].index == index)
729 return true;
730
731 return false;
732 }
733
734 static void set_msr_interception(u32 *msrpm, unsigned msr,
735 int read, int write)
736 {
737 u8 bit_read, bit_write;
738 unsigned long tmp;
739 u32 offset;
740
741 /*
742 * If this warning triggers extend the direct_access_msrs list at the
743 * beginning of the file
744 */
745 WARN_ON(!valid_msr_intercept(msr));
746
747 offset = svm_msrpm_offset(msr);
748 bit_read = 2 * (msr & 0x0f);
749 bit_write = 2 * (msr & 0x0f) + 1;
750 tmp = msrpm[offset];
751
752 BUG_ON(offset == MSR_INVALID);
753
754 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
755 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
756
757 msrpm[offset] = tmp;
758 }
759
760 static void svm_vcpu_init_msrpm(u32 *msrpm)
761 {
762 int i;
763
764 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
765
766 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
767 if (!direct_access_msrs[i].always)
768 continue;
769
770 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
771 }
772 }
773
774 static void add_msr_offset(u32 offset)
775 {
776 int i;
777
778 for (i = 0; i < MSRPM_OFFSETS; ++i) {
779
780 /* Offset already in list? */
781 if (msrpm_offsets[i] == offset)
782 return;
783
784 /* Slot used by another offset? */
785 if (msrpm_offsets[i] != MSR_INVALID)
786 continue;
787
788 /* Add offset to list */
789 msrpm_offsets[i] = offset;
790
791 return;
792 }
793
794 /*
795 * If this BUG triggers the msrpm_offsets table has an overflow. Just
796 * increase MSRPM_OFFSETS in this case.
797 */
798 BUG();
799 }
800
801 static void init_msrpm_offsets(void)
802 {
803 int i;
804
805 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
806
807 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
808 u32 offset;
809
810 offset = svm_msrpm_offset(direct_access_msrs[i].index);
811 BUG_ON(offset == MSR_INVALID);
812
813 add_msr_offset(offset);
814 }
815 }
816
817 static void svm_enable_lbrv(struct vcpu_svm *svm)
818 {
819 u32 *msrpm = svm->msrpm;
820
821 svm->vmcb->control.lbr_ctl = 1;
822 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
823 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
824 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
825 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
826 }
827
828 static void svm_disable_lbrv(struct vcpu_svm *svm)
829 {
830 u32 *msrpm = svm->msrpm;
831
832 svm->vmcb->control.lbr_ctl = 0;
833 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
834 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
835 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
836 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
837 }
838
839 static __init int svm_hardware_setup(void)
840 {
841 int cpu;
842 struct page *iopm_pages;
843 void *iopm_va;
844 int r;
845
846 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
847
848 if (!iopm_pages)
849 return -ENOMEM;
850
851 iopm_va = page_address(iopm_pages);
852 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
853 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
854
855 init_msrpm_offsets();
856
857 if (boot_cpu_has(X86_FEATURE_NX))
858 kvm_enable_efer_bits(EFER_NX);
859
860 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
861 kvm_enable_efer_bits(EFER_FFXSR);
862
863 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
864 u64 max;
865
866 kvm_has_tsc_control = true;
867
868 /*
869 * Make sure the user can only configure tsc_khz values that
870 * fit into a signed integer.
871 * A min value is not calculated needed because it will always
872 * be 1 on all machines and a value of 0 is used to disable
873 * tsc-scaling for the vcpu.
874 */
875 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
876
877 kvm_max_guest_tsc_khz = max;
878 }
879
880 if (nested) {
881 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
882 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
883 }
884
885 for_each_possible_cpu(cpu) {
886 r = svm_cpu_init(cpu);
887 if (r)
888 goto err;
889 }
890
891 if (!boot_cpu_has(X86_FEATURE_NPT))
892 npt_enabled = false;
893
894 if (npt_enabled && !npt) {
895 printk(KERN_INFO "kvm: Nested Paging disabled\n");
896 npt_enabled = false;
897 }
898
899 if (npt_enabled) {
900 printk(KERN_INFO "kvm: Nested Paging enabled\n");
901 kvm_enable_tdp();
902 } else
903 kvm_disable_tdp();
904
905 return 0;
906
907 err:
908 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
909 iopm_base = 0;
910 return r;
911 }
912
913 static __exit void svm_hardware_unsetup(void)
914 {
915 int cpu;
916
917 for_each_possible_cpu(cpu)
918 svm_cpu_uninit(cpu);
919
920 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
921 iopm_base = 0;
922 }
923
924 static void init_seg(struct vmcb_seg *seg)
925 {
926 seg->selector = 0;
927 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
928 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
929 seg->limit = 0xffff;
930 seg->base = 0;
931 }
932
933 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
934 {
935 seg->selector = 0;
936 seg->attrib = SVM_SELECTOR_P_MASK | type;
937 seg->limit = 0xffff;
938 seg->base = 0;
939 }
940
941 static u64 __scale_tsc(u64 ratio, u64 tsc)
942 {
943 u64 mult, frac, _tsc;
944
945 mult = ratio >> 32;
946 frac = ratio & ((1ULL << 32) - 1);
947
948 _tsc = tsc;
949 _tsc *= mult;
950 _tsc += (tsc >> 32) * frac;
951 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
952
953 return _tsc;
954 }
955
956 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
957 {
958 struct vcpu_svm *svm = to_svm(vcpu);
959 u64 _tsc = tsc;
960
961 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
962 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
963
964 return _tsc;
965 }
966
967 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
968 {
969 struct vcpu_svm *svm = to_svm(vcpu);
970 u64 ratio;
971 u64 khz;
972
973 /* Guest TSC same frequency as host TSC? */
974 if (!scale) {
975 svm->tsc_ratio = TSC_RATIO_DEFAULT;
976 return;
977 }
978
979 /* TSC scaling supported? */
980 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
981 if (user_tsc_khz > tsc_khz) {
982 vcpu->arch.tsc_catchup = 1;
983 vcpu->arch.tsc_always_catchup = 1;
984 } else
985 WARN(1, "user requested TSC rate below hardware speed\n");
986 return;
987 }
988
989 khz = user_tsc_khz;
990
991 /* TSC scaling required - calculate ratio */
992 ratio = khz << 32;
993 do_div(ratio, tsc_khz);
994
995 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
996 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
997 user_tsc_khz);
998 return;
999 }
1000 svm->tsc_ratio = ratio;
1001 }
1002
1003 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1004 {
1005 struct vcpu_svm *svm = to_svm(vcpu);
1006 u64 g_tsc_offset = 0;
1007
1008 if (is_guest_mode(vcpu)) {
1009 g_tsc_offset = svm->vmcb->control.tsc_offset -
1010 svm->nested.hsave->control.tsc_offset;
1011 svm->nested.hsave->control.tsc_offset = offset;
1012 }
1013
1014 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1015
1016 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1017 }
1018
1019 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1020 {
1021 struct vcpu_svm *svm = to_svm(vcpu);
1022
1023 WARN_ON(adjustment < 0);
1024 if (host)
1025 adjustment = svm_scale_tsc(vcpu, adjustment);
1026
1027 svm->vmcb->control.tsc_offset += adjustment;
1028 if (is_guest_mode(vcpu))
1029 svm->nested.hsave->control.tsc_offset += adjustment;
1030 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1031 }
1032
1033 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1034 {
1035 u64 tsc;
1036
1037 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1038
1039 return target_tsc - tsc;
1040 }
1041
1042 static void init_vmcb(struct vcpu_svm *svm)
1043 {
1044 struct vmcb_control_area *control = &svm->vmcb->control;
1045 struct vmcb_save_area *save = &svm->vmcb->save;
1046
1047 svm->vcpu.fpu_active = 1;
1048 svm->vcpu.arch.hflags = 0;
1049
1050 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1051 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1052 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1053 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1054 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1055 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1056 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1057
1058 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1059 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1060 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1061 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1062 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1063 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1064 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1065 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1066
1067 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1068 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1069 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1070 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1071 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1072 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1073 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1074 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1075
1076 set_exception_intercept(svm, PF_VECTOR);
1077 set_exception_intercept(svm, UD_VECTOR);
1078 set_exception_intercept(svm, MC_VECTOR);
1079
1080 set_intercept(svm, INTERCEPT_INTR);
1081 set_intercept(svm, INTERCEPT_NMI);
1082 set_intercept(svm, INTERCEPT_SMI);
1083 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1084 set_intercept(svm, INTERCEPT_RDPMC);
1085 set_intercept(svm, INTERCEPT_CPUID);
1086 set_intercept(svm, INTERCEPT_INVD);
1087 set_intercept(svm, INTERCEPT_HLT);
1088 set_intercept(svm, INTERCEPT_INVLPG);
1089 set_intercept(svm, INTERCEPT_INVLPGA);
1090 set_intercept(svm, INTERCEPT_IOIO_PROT);
1091 set_intercept(svm, INTERCEPT_MSR_PROT);
1092 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1093 set_intercept(svm, INTERCEPT_SHUTDOWN);
1094 set_intercept(svm, INTERCEPT_VMRUN);
1095 set_intercept(svm, INTERCEPT_VMMCALL);
1096 set_intercept(svm, INTERCEPT_VMLOAD);
1097 set_intercept(svm, INTERCEPT_VMSAVE);
1098 set_intercept(svm, INTERCEPT_STGI);
1099 set_intercept(svm, INTERCEPT_CLGI);
1100 set_intercept(svm, INTERCEPT_SKINIT);
1101 set_intercept(svm, INTERCEPT_WBINVD);
1102 set_intercept(svm, INTERCEPT_MONITOR);
1103 set_intercept(svm, INTERCEPT_MWAIT);
1104 set_intercept(svm, INTERCEPT_XSETBV);
1105
1106 control->iopm_base_pa = iopm_base;
1107 control->msrpm_base_pa = __pa(svm->msrpm);
1108 control->int_ctl = V_INTR_MASKING_MASK;
1109
1110 init_seg(&save->es);
1111 init_seg(&save->ss);
1112 init_seg(&save->ds);
1113 init_seg(&save->fs);
1114 init_seg(&save->gs);
1115
1116 save->cs.selector = 0xf000;
1117 /* Executable/Readable Code Segment */
1118 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1119 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1120 save->cs.limit = 0xffff;
1121 /*
1122 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1123 * be consistent with it.
1124 *
1125 * Replace when we have real mode working for vmx.
1126 */
1127 save->cs.base = 0xf0000;
1128
1129 save->gdtr.limit = 0xffff;
1130 save->idtr.limit = 0xffff;
1131
1132 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1133 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1134
1135 svm_set_efer(&svm->vcpu, 0);
1136 save->dr6 = 0xffff0ff0;
1137 save->dr7 = 0x400;
1138 kvm_set_rflags(&svm->vcpu, 2);
1139 save->rip = 0x0000fff0;
1140 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1141
1142 /*
1143 * This is the guest-visible cr0 value.
1144 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1145 */
1146 svm->vcpu.arch.cr0 = 0;
1147 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1148
1149 save->cr4 = X86_CR4_PAE;
1150 /* rdx = ?? */
1151
1152 if (npt_enabled) {
1153 /* Setup VMCB for Nested Paging */
1154 control->nested_ctl = 1;
1155 clr_intercept(svm, INTERCEPT_INVLPG);
1156 clr_exception_intercept(svm, PF_VECTOR);
1157 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1158 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1159 save->g_pat = 0x0007040600070406ULL;
1160 save->cr3 = 0;
1161 save->cr4 = 0;
1162 }
1163 svm->asid_generation = 0;
1164
1165 svm->nested.vmcb = 0;
1166 svm->vcpu.arch.hflags = 0;
1167
1168 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1169 control->pause_filter_count = 3000;
1170 set_intercept(svm, INTERCEPT_PAUSE);
1171 }
1172
1173 mark_all_dirty(svm->vmcb);
1174
1175 enable_gif(svm);
1176 }
1177
1178 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1179 {
1180 struct vcpu_svm *svm = to_svm(vcpu);
1181
1182 init_vmcb(svm);
1183
1184 if (!kvm_vcpu_is_bsp(vcpu)) {
1185 kvm_rip_write(vcpu, 0);
1186 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1187 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1188 }
1189 vcpu->arch.regs_avail = ~0;
1190 vcpu->arch.regs_dirty = ~0;
1191
1192 return 0;
1193 }
1194
1195 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1196 {
1197 struct vcpu_svm *svm;
1198 struct page *page;
1199 struct page *msrpm_pages;
1200 struct page *hsave_page;
1201 struct page *nested_msrpm_pages;
1202 int err;
1203
1204 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1205 if (!svm) {
1206 err = -ENOMEM;
1207 goto out;
1208 }
1209
1210 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1211
1212 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1213 if (err)
1214 goto free_svm;
1215
1216 err = -ENOMEM;
1217 page = alloc_page(GFP_KERNEL);
1218 if (!page)
1219 goto uninit;
1220
1221 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1222 if (!msrpm_pages)
1223 goto free_page1;
1224
1225 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1226 if (!nested_msrpm_pages)
1227 goto free_page2;
1228
1229 hsave_page = alloc_page(GFP_KERNEL);
1230 if (!hsave_page)
1231 goto free_page3;
1232
1233 svm->nested.hsave = page_address(hsave_page);
1234
1235 svm->msrpm = page_address(msrpm_pages);
1236 svm_vcpu_init_msrpm(svm->msrpm);
1237
1238 svm->nested.msrpm = page_address(nested_msrpm_pages);
1239 svm_vcpu_init_msrpm(svm->nested.msrpm);
1240
1241 svm->vmcb = page_address(page);
1242 clear_page(svm->vmcb);
1243 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1244 svm->asid_generation = 0;
1245 init_vmcb(svm);
1246 kvm_write_tsc(&svm->vcpu, 0);
1247
1248 err = fx_init(&svm->vcpu);
1249 if (err)
1250 goto free_page4;
1251
1252 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1253 if (kvm_vcpu_is_bsp(&svm->vcpu))
1254 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1255
1256 svm_init_osvw(&svm->vcpu);
1257
1258 return &svm->vcpu;
1259
1260 free_page4:
1261 __free_page(hsave_page);
1262 free_page3:
1263 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1264 free_page2:
1265 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1266 free_page1:
1267 __free_page(page);
1268 uninit:
1269 kvm_vcpu_uninit(&svm->vcpu);
1270 free_svm:
1271 kmem_cache_free(kvm_vcpu_cache, svm);
1272 out:
1273 return ERR_PTR(err);
1274 }
1275
1276 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1277 {
1278 struct vcpu_svm *svm = to_svm(vcpu);
1279
1280 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1281 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1282 __free_page(virt_to_page(svm->nested.hsave));
1283 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1284 kvm_vcpu_uninit(vcpu);
1285 kmem_cache_free(kvm_vcpu_cache, svm);
1286 }
1287
1288 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1289 {
1290 struct vcpu_svm *svm = to_svm(vcpu);
1291 int i;
1292
1293 if (unlikely(cpu != vcpu->cpu)) {
1294 svm->asid_generation = 0;
1295 mark_all_dirty(svm->vmcb);
1296 }
1297
1298 #ifdef CONFIG_X86_64
1299 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1300 #endif
1301 savesegment(fs, svm->host.fs);
1302 savesegment(gs, svm->host.gs);
1303 svm->host.ldt = kvm_read_ldt();
1304
1305 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1306 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1307
1308 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1309 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1310 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1311 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1312 }
1313 }
1314
1315 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1316 {
1317 struct vcpu_svm *svm = to_svm(vcpu);
1318 int i;
1319
1320 ++vcpu->stat.host_state_reload;
1321 kvm_load_ldt(svm->host.ldt);
1322 #ifdef CONFIG_X86_64
1323 loadsegment(fs, svm->host.fs);
1324 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1325 load_gs_index(svm->host.gs);
1326 #else
1327 #ifdef CONFIG_X86_32_LAZY_GS
1328 loadsegment(gs, svm->host.gs);
1329 #endif
1330 #endif
1331 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1332 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1333 }
1334
1335 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1336 {
1337 struct vcpu_svm *svm = to_svm(vcpu);
1338 int cpl;
1339
1340 if (!is_protmode(vcpu))
1341 cpl = 0;
1342 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1343 cpl = 3;
1344 else
1345 cpl = svm->vmcb->save.cs.selector & 0x3;
1346
1347 svm->vmcb->save.cpl = cpl;
1348 }
1349
1350 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1351 {
1352 return to_svm(vcpu)->vmcb->save.rflags;
1353 }
1354
1355 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1356 {
1357 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1358
1359 to_svm(vcpu)->vmcb->save.rflags = rflags;
1360 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1361 svm_update_cpl(vcpu);
1362 }
1363
1364 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1365 {
1366 switch (reg) {
1367 case VCPU_EXREG_PDPTR:
1368 BUG_ON(!npt_enabled);
1369 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1370 break;
1371 default:
1372 BUG();
1373 }
1374 }
1375
1376 static void svm_set_vintr(struct vcpu_svm *svm)
1377 {
1378 set_intercept(svm, INTERCEPT_VINTR);
1379 }
1380
1381 static void svm_clear_vintr(struct vcpu_svm *svm)
1382 {
1383 clr_intercept(svm, INTERCEPT_VINTR);
1384 }
1385
1386 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1387 {
1388 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1389
1390 switch (seg) {
1391 case VCPU_SREG_CS: return &save->cs;
1392 case VCPU_SREG_DS: return &save->ds;
1393 case VCPU_SREG_ES: return &save->es;
1394 case VCPU_SREG_FS: return &save->fs;
1395 case VCPU_SREG_GS: return &save->gs;
1396 case VCPU_SREG_SS: return &save->ss;
1397 case VCPU_SREG_TR: return &save->tr;
1398 case VCPU_SREG_LDTR: return &save->ldtr;
1399 }
1400 BUG();
1401 return NULL;
1402 }
1403
1404 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1405 {
1406 struct vmcb_seg *s = svm_seg(vcpu, seg);
1407
1408 return s->base;
1409 }
1410
1411 static void svm_get_segment(struct kvm_vcpu *vcpu,
1412 struct kvm_segment *var, int seg)
1413 {
1414 struct vmcb_seg *s = svm_seg(vcpu, seg);
1415
1416 var->base = s->base;
1417 var->limit = s->limit;
1418 var->selector = s->selector;
1419 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1420 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1421 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1422 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1423 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1424 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1425 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1426 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1427
1428 /*
1429 * AMD's VMCB does not have an explicit unusable field, so emulate it
1430 * for cross vendor migration purposes by "not present"
1431 */
1432 var->unusable = !var->present || (var->type == 0);
1433
1434 switch (seg) {
1435 case VCPU_SREG_CS:
1436 /*
1437 * SVM always stores 0 for the 'G' bit in the CS selector in
1438 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1439 * Intel's VMENTRY has a check on the 'G' bit.
1440 */
1441 var->g = s->limit > 0xfffff;
1442 break;
1443 case VCPU_SREG_TR:
1444 /*
1445 * Work around a bug where the busy flag in the tr selector
1446 * isn't exposed
1447 */
1448 var->type |= 0x2;
1449 break;
1450 case VCPU_SREG_DS:
1451 case VCPU_SREG_ES:
1452 case VCPU_SREG_FS:
1453 case VCPU_SREG_GS:
1454 /*
1455 * The accessed bit must always be set in the segment
1456 * descriptor cache, although it can be cleared in the
1457 * descriptor, the cached bit always remains at 1. Since
1458 * Intel has a check on this, set it here to support
1459 * cross-vendor migration.
1460 */
1461 if (!var->unusable)
1462 var->type |= 0x1;
1463 break;
1464 case VCPU_SREG_SS:
1465 /*
1466 * On AMD CPUs sometimes the DB bit in the segment
1467 * descriptor is left as 1, although the whole segment has
1468 * been made unusable. Clear it here to pass an Intel VMX
1469 * entry check when cross vendor migrating.
1470 */
1471 if (var->unusable)
1472 var->db = 0;
1473 break;
1474 }
1475 }
1476
1477 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1478 {
1479 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1480
1481 return save->cpl;
1482 }
1483
1484 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1485 {
1486 struct vcpu_svm *svm = to_svm(vcpu);
1487
1488 dt->size = svm->vmcb->save.idtr.limit;
1489 dt->address = svm->vmcb->save.idtr.base;
1490 }
1491
1492 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1493 {
1494 struct vcpu_svm *svm = to_svm(vcpu);
1495
1496 svm->vmcb->save.idtr.limit = dt->size;
1497 svm->vmcb->save.idtr.base = dt->address ;
1498 mark_dirty(svm->vmcb, VMCB_DT);
1499 }
1500
1501 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1502 {
1503 struct vcpu_svm *svm = to_svm(vcpu);
1504
1505 dt->size = svm->vmcb->save.gdtr.limit;
1506 dt->address = svm->vmcb->save.gdtr.base;
1507 }
1508
1509 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1510 {
1511 struct vcpu_svm *svm = to_svm(vcpu);
1512
1513 svm->vmcb->save.gdtr.limit = dt->size;
1514 svm->vmcb->save.gdtr.base = dt->address ;
1515 mark_dirty(svm->vmcb, VMCB_DT);
1516 }
1517
1518 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1519 {
1520 }
1521
1522 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1523 {
1524 }
1525
1526 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1527 {
1528 }
1529
1530 static void update_cr0_intercept(struct vcpu_svm *svm)
1531 {
1532 ulong gcr0 = svm->vcpu.arch.cr0;
1533 u64 *hcr0 = &svm->vmcb->save.cr0;
1534
1535 if (!svm->vcpu.fpu_active)
1536 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1537 else
1538 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1539 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1540
1541 mark_dirty(svm->vmcb, VMCB_CR);
1542
1543 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1544 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1545 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546 } else {
1547 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1548 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1549 }
1550 }
1551
1552 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1553 {
1554 struct vcpu_svm *svm = to_svm(vcpu);
1555
1556 #ifdef CONFIG_X86_64
1557 if (vcpu->arch.efer & EFER_LME) {
1558 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1559 vcpu->arch.efer |= EFER_LMA;
1560 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1561 }
1562
1563 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1564 vcpu->arch.efer &= ~EFER_LMA;
1565 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1566 }
1567 }
1568 #endif
1569 vcpu->arch.cr0 = cr0;
1570
1571 if (!npt_enabled)
1572 cr0 |= X86_CR0_PG | X86_CR0_WP;
1573
1574 if (!vcpu->fpu_active)
1575 cr0 |= X86_CR0_TS;
1576 /*
1577 * re-enable caching here because the QEMU bios
1578 * does not do it - this results in some delay at
1579 * reboot
1580 */
1581 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1582 svm->vmcb->save.cr0 = cr0;
1583 mark_dirty(svm->vmcb, VMCB_CR);
1584 update_cr0_intercept(svm);
1585 }
1586
1587 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1588 {
1589 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1590 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1591
1592 if (cr4 & X86_CR4_VMXE)
1593 return 1;
1594
1595 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1596 svm_flush_tlb(vcpu);
1597
1598 vcpu->arch.cr4 = cr4;
1599 if (!npt_enabled)
1600 cr4 |= X86_CR4_PAE;
1601 cr4 |= host_cr4_mce;
1602 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1603 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1604 return 0;
1605 }
1606
1607 static void svm_set_segment(struct kvm_vcpu *vcpu,
1608 struct kvm_segment *var, int seg)
1609 {
1610 struct vcpu_svm *svm = to_svm(vcpu);
1611 struct vmcb_seg *s = svm_seg(vcpu, seg);
1612
1613 s->base = var->base;
1614 s->limit = var->limit;
1615 s->selector = var->selector;
1616 if (var->unusable)
1617 s->attrib = 0;
1618 else {
1619 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1620 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1621 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1622 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1623 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1624 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1625 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1626 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1627 }
1628 if (seg == VCPU_SREG_CS)
1629 svm_update_cpl(vcpu);
1630
1631 mark_dirty(svm->vmcb, VMCB_SEG);
1632 }
1633
1634 static void update_db_intercept(struct kvm_vcpu *vcpu)
1635 {
1636 struct vcpu_svm *svm = to_svm(vcpu);
1637
1638 clr_exception_intercept(svm, DB_VECTOR);
1639 clr_exception_intercept(svm, BP_VECTOR);
1640
1641 if (svm->nmi_singlestep)
1642 set_exception_intercept(svm, DB_VECTOR);
1643
1644 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1645 if (vcpu->guest_debug &
1646 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1647 set_exception_intercept(svm, DB_VECTOR);
1648 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1649 set_exception_intercept(svm, BP_VECTOR);
1650 } else
1651 vcpu->guest_debug = 0;
1652 }
1653
1654 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1655 {
1656 struct vcpu_svm *svm = to_svm(vcpu);
1657
1658 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1659 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1660 else
1661 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1662
1663 mark_dirty(svm->vmcb, VMCB_DR);
1664
1665 update_db_intercept(vcpu);
1666 }
1667
1668 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1669 {
1670 if (sd->next_asid > sd->max_asid) {
1671 ++sd->asid_generation;
1672 sd->next_asid = 1;
1673 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1674 }
1675
1676 svm->asid_generation = sd->asid_generation;
1677 svm->vmcb->control.asid = sd->next_asid++;
1678
1679 mark_dirty(svm->vmcb, VMCB_ASID);
1680 }
1681
1682 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1683 {
1684 struct vcpu_svm *svm = to_svm(vcpu);
1685
1686 svm->vmcb->save.dr7 = value;
1687 mark_dirty(svm->vmcb, VMCB_DR);
1688 }
1689
1690 static int pf_interception(struct vcpu_svm *svm)
1691 {
1692 u64 fault_address = svm->vmcb->control.exit_info_2;
1693 u32 error_code;
1694 int r = 1;
1695
1696 switch (svm->apf_reason) {
1697 default:
1698 error_code = svm->vmcb->control.exit_info_1;
1699
1700 trace_kvm_page_fault(fault_address, error_code);
1701 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1702 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1703 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1704 svm->vmcb->control.insn_bytes,
1705 svm->vmcb->control.insn_len);
1706 break;
1707 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1708 svm->apf_reason = 0;
1709 local_irq_disable();
1710 kvm_async_pf_task_wait(fault_address);
1711 local_irq_enable();
1712 break;
1713 case KVM_PV_REASON_PAGE_READY:
1714 svm->apf_reason = 0;
1715 local_irq_disable();
1716 kvm_async_pf_task_wake(fault_address);
1717 local_irq_enable();
1718 break;
1719 }
1720 return r;
1721 }
1722
1723 static int db_interception(struct vcpu_svm *svm)
1724 {
1725 struct kvm_run *kvm_run = svm->vcpu.run;
1726
1727 if (!(svm->vcpu.guest_debug &
1728 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1729 !svm->nmi_singlestep) {
1730 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1731 return 1;
1732 }
1733
1734 if (svm->nmi_singlestep) {
1735 svm->nmi_singlestep = false;
1736 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1737 svm->vmcb->save.rflags &=
1738 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1739 update_db_intercept(&svm->vcpu);
1740 }
1741
1742 if (svm->vcpu.guest_debug &
1743 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1744 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1745 kvm_run->debug.arch.pc =
1746 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1747 kvm_run->debug.arch.exception = DB_VECTOR;
1748 return 0;
1749 }
1750
1751 return 1;
1752 }
1753
1754 static int bp_interception(struct vcpu_svm *svm)
1755 {
1756 struct kvm_run *kvm_run = svm->vcpu.run;
1757
1758 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1759 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1760 kvm_run->debug.arch.exception = BP_VECTOR;
1761 return 0;
1762 }
1763
1764 static int ud_interception(struct vcpu_svm *svm)
1765 {
1766 int er;
1767
1768 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1769 if (er != EMULATE_DONE)
1770 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1771 return 1;
1772 }
1773
1774 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1775 {
1776 struct vcpu_svm *svm = to_svm(vcpu);
1777
1778 clr_exception_intercept(svm, NM_VECTOR);
1779
1780 svm->vcpu.fpu_active = 1;
1781 update_cr0_intercept(svm);
1782 }
1783
1784 static int nm_interception(struct vcpu_svm *svm)
1785 {
1786 svm_fpu_activate(&svm->vcpu);
1787 return 1;
1788 }
1789
1790 static bool is_erratum_383(void)
1791 {
1792 int err, i;
1793 u64 value;
1794
1795 if (!erratum_383_found)
1796 return false;
1797
1798 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1799 if (err)
1800 return false;
1801
1802 /* Bit 62 may or may not be set for this mce */
1803 value &= ~(1ULL << 62);
1804
1805 if (value != 0xb600000000010015ULL)
1806 return false;
1807
1808 /* Clear MCi_STATUS registers */
1809 for (i = 0; i < 6; ++i)
1810 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1811
1812 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1813 if (!err) {
1814 u32 low, high;
1815
1816 value &= ~(1ULL << 2);
1817 low = lower_32_bits(value);
1818 high = upper_32_bits(value);
1819
1820 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1821 }
1822
1823 /* Flush tlb to evict multi-match entries */
1824 __flush_tlb_all();
1825
1826 return true;
1827 }
1828
1829 static void svm_handle_mce(struct vcpu_svm *svm)
1830 {
1831 if (is_erratum_383()) {
1832 /*
1833 * Erratum 383 triggered. Guest state is corrupt so kill the
1834 * guest.
1835 */
1836 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1837
1838 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1839
1840 return;
1841 }
1842
1843 /*
1844 * On an #MC intercept the MCE handler is not called automatically in
1845 * the host. So do it by hand here.
1846 */
1847 asm volatile (
1848 "int $0x12\n");
1849 /* not sure if we ever come back to this point */
1850
1851 return;
1852 }
1853
1854 static int mc_interception(struct vcpu_svm *svm)
1855 {
1856 return 1;
1857 }
1858
1859 static int shutdown_interception(struct vcpu_svm *svm)
1860 {
1861 struct kvm_run *kvm_run = svm->vcpu.run;
1862
1863 /*
1864 * VMCB is undefined after a SHUTDOWN intercept
1865 * so reinitialize it.
1866 */
1867 clear_page(svm->vmcb);
1868 init_vmcb(svm);
1869
1870 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1871 return 0;
1872 }
1873
1874 static int io_interception(struct vcpu_svm *svm)
1875 {
1876 struct kvm_vcpu *vcpu = &svm->vcpu;
1877 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1878 int size, in, string;
1879 unsigned port;
1880
1881 ++svm->vcpu.stat.io_exits;
1882 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1883 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1884 if (string || in)
1885 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1886
1887 port = io_info >> 16;
1888 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1889 svm->next_rip = svm->vmcb->control.exit_info_2;
1890 skip_emulated_instruction(&svm->vcpu);
1891
1892 return kvm_fast_pio_out(vcpu, size, port);
1893 }
1894
1895 static int nmi_interception(struct vcpu_svm *svm)
1896 {
1897 return 1;
1898 }
1899
1900 static int intr_interception(struct vcpu_svm *svm)
1901 {
1902 ++svm->vcpu.stat.irq_exits;
1903 return 1;
1904 }
1905
1906 static int nop_on_interception(struct vcpu_svm *svm)
1907 {
1908 return 1;
1909 }
1910
1911 static int halt_interception(struct vcpu_svm *svm)
1912 {
1913 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1914 skip_emulated_instruction(&svm->vcpu);
1915 return kvm_emulate_halt(&svm->vcpu);
1916 }
1917
1918 static int vmmcall_interception(struct vcpu_svm *svm)
1919 {
1920 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1921 skip_emulated_instruction(&svm->vcpu);
1922 kvm_emulate_hypercall(&svm->vcpu);
1923 return 1;
1924 }
1925
1926 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1927 {
1928 struct vcpu_svm *svm = to_svm(vcpu);
1929
1930 return svm->nested.nested_cr3;
1931 }
1932
1933 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1934 {
1935 struct vcpu_svm *svm = to_svm(vcpu);
1936 u64 cr3 = svm->nested.nested_cr3;
1937 u64 pdpte;
1938 int ret;
1939
1940 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1941 offset_in_page(cr3) + index * 8, 8);
1942 if (ret)
1943 return 0;
1944 return pdpte;
1945 }
1946
1947 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1948 unsigned long root)
1949 {
1950 struct vcpu_svm *svm = to_svm(vcpu);
1951
1952 svm->vmcb->control.nested_cr3 = root;
1953 mark_dirty(svm->vmcb, VMCB_NPT);
1954 svm_flush_tlb(vcpu);
1955 }
1956
1957 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1958 struct x86_exception *fault)
1959 {
1960 struct vcpu_svm *svm = to_svm(vcpu);
1961
1962 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1963 svm->vmcb->control.exit_code_hi = 0;
1964 svm->vmcb->control.exit_info_1 = fault->error_code;
1965 svm->vmcb->control.exit_info_2 = fault->address;
1966
1967 nested_svm_vmexit(svm);
1968 }
1969
1970 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1971 {
1972 int r;
1973
1974 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1975
1976 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1977 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1978 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1979 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1980 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1981 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1982
1983 return r;
1984 }
1985
1986 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1987 {
1988 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1989 }
1990
1991 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1992 {
1993 if (!(svm->vcpu.arch.efer & EFER_SVME)
1994 || !is_paging(&svm->vcpu)) {
1995 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1996 return 1;
1997 }
1998
1999 if (svm->vmcb->save.cpl) {
2000 kvm_inject_gp(&svm->vcpu, 0);
2001 return 1;
2002 }
2003
2004 return 0;
2005 }
2006
2007 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2008 bool has_error_code, u32 error_code)
2009 {
2010 int vmexit;
2011
2012 if (!is_guest_mode(&svm->vcpu))
2013 return 0;
2014
2015 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2016 svm->vmcb->control.exit_code_hi = 0;
2017 svm->vmcb->control.exit_info_1 = error_code;
2018 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2019
2020 vmexit = nested_svm_intercept(svm);
2021 if (vmexit == NESTED_EXIT_DONE)
2022 svm->nested.exit_required = true;
2023
2024 return vmexit;
2025 }
2026
2027 /* This function returns true if it is save to enable the irq window */
2028 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2029 {
2030 if (!is_guest_mode(&svm->vcpu))
2031 return true;
2032
2033 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2034 return true;
2035
2036 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2037 return false;
2038
2039 /*
2040 * if vmexit was already requested (by intercepted exception
2041 * for instance) do not overwrite it with "external interrupt"
2042 * vmexit.
2043 */
2044 if (svm->nested.exit_required)
2045 return false;
2046
2047 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2048 svm->vmcb->control.exit_info_1 = 0;
2049 svm->vmcb->control.exit_info_2 = 0;
2050
2051 if (svm->nested.intercept & 1ULL) {
2052 /*
2053 * The #vmexit can't be emulated here directly because this
2054 * code path runs with irqs and preemtion disabled. A
2055 * #vmexit emulation might sleep. Only signal request for
2056 * the #vmexit here.
2057 */
2058 svm->nested.exit_required = true;
2059 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2060 return false;
2061 }
2062
2063 return true;
2064 }
2065
2066 /* This function returns true if it is save to enable the nmi window */
2067 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2068 {
2069 if (!is_guest_mode(&svm->vcpu))
2070 return true;
2071
2072 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2073 return true;
2074
2075 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2076 svm->nested.exit_required = true;
2077
2078 return false;
2079 }
2080
2081 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2082 {
2083 struct page *page;
2084
2085 might_sleep();
2086
2087 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2088 if (is_error_page(page))
2089 goto error;
2090
2091 *_page = page;
2092
2093 return kmap(page);
2094
2095 error:
2096 kvm_release_page_clean(page);
2097 kvm_inject_gp(&svm->vcpu, 0);
2098
2099 return NULL;
2100 }
2101
2102 static void nested_svm_unmap(struct page *page)
2103 {
2104 kunmap(page);
2105 kvm_release_page_dirty(page);
2106 }
2107
2108 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2109 {
2110 unsigned port;
2111 u8 val, bit;
2112 u64 gpa;
2113
2114 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2115 return NESTED_EXIT_HOST;
2116
2117 port = svm->vmcb->control.exit_info_1 >> 16;
2118 gpa = svm->nested.vmcb_iopm + (port / 8);
2119 bit = port % 8;
2120 val = 0;
2121
2122 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2123 val &= (1 << bit);
2124
2125 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2126 }
2127
2128 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2129 {
2130 u32 offset, msr, value;
2131 int write, mask;
2132
2133 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2134 return NESTED_EXIT_HOST;
2135
2136 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2137 offset = svm_msrpm_offset(msr);
2138 write = svm->vmcb->control.exit_info_1 & 1;
2139 mask = 1 << ((2 * (msr & 0xf)) + write);
2140
2141 if (offset == MSR_INVALID)
2142 return NESTED_EXIT_DONE;
2143
2144 /* Offset is in 32 bit units but need in 8 bit units */
2145 offset *= 4;
2146
2147 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2148 return NESTED_EXIT_DONE;
2149
2150 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2151 }
2152
2153 static int nested_svm_exit_special(struct vcpu_svm *svm)
2154 {
2155 u32 exit_code = svm->vmcb->control.exit_code;
2156
2157 switch (exit_code) {
2158 case SVM_EXIT_INTR:
2159 case SVM_EXIT_NMI:
2160 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2161 return NESTED_EXIT_HOST;
2162 case SVM_EXIT_NPF:
2163 /* For now we are always handling NPFs when using them */
2164 if (npt_enabled)
2165 return NESTED_EXIT_HOST;
2166 break;
2167 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2168 /* When we're shadowing, trap PFs, but not async PF */
2169 if (!npt_enabled && svm->apf_reason == 0)
2170 return NESTED_EXIT_HOST;
2171 break;
2172 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2173 nm_interception(svm);
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 return NESTED_EXIT_CONTINUE;
2180 }
2181
2182 /*
2183 * If this function returns true, this #vmexit was already handled
2184 */
2185 static int nested_svm_intercept(struct vcpu_svm *svm)
2186 {
2187 u32 exit_code = svm->vmcb->control.exit_code;
2188 int vmexit = NESTED_EXIT_HOST;
2189
2190 switch (exit_code) {
2191 case SVM_EXIT_MSR:
2192 vmexit = nested_svm_exit_handled_msr(svm);
2193 break;
2194 case SVM_EXIT_IOIO:
2195 vmexit = nested_svm_intercept_ioio(svm);
2196 break;
2197 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2198 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2199 if (svm->nested.intercept_cr & bit)
2200 vmexit = NESTED_EXIT_DONE;
2201 break;
2202 }
2203 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2204 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2205 if (svm->nested.intercept_dr & bit)
2206 vmexit = NESTED_EXIT_DONE;
2207 break;
2208 }
2209 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2210 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2211 if (svm->nested.intercept_exceptions & excp_bits)
2212 vmexit = NESTED_EXIT_DONE;
2213 /* async page fault always cause vmexit */
2214 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2215 svm->apf_reason != 0)
2216 vmexit = NESTED_EXIT_DONE;
2217 break;
2218 }
2219 case SVM_EXIT_ERR: {
2220 vmexit = NESTED_EXIT_DONE;
2221 break;
2222 }
2223 default: {
2224 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2225 if (svm->nested.intercept & exit_bits)
2226 vmexit = NESTED_EXIT_DONE;
2227 }
2228 }
2229
2230 return vmexit;
2231 }
2232
2233 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2234 {
2235 int vmexit;
2236
2237 vmexit = nested_svm_intercept(svm);
2238
2239 if (vmexit == NESTED_EXIT_DONE)
2240 nested_svm_vmexit(svm);
2241
2242 return vmexit;
2243 }
2244
2245 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2246 {
2247 struct vmcb_control_area *dst = &dst_vmcb->control;
2248 struct vmcb_control_area *from = &from_vmcb->control;
2249
2250 dst->intercept_cr = from->intercept_cr;
2251 dst->intercept_dr = from->intercept_dr;
2252 dst->intercept_exceptions = from->intercept_exceptions;
2253 dst->intercept = from->intercept;
2254 dst->iopm_base_pa = from->iopm_base_pa;
2255 dst->msrpm_base_pa = from->msrpm_base_pa;
2256 dst->tsc_offset = from->tsc_offset;
2257 dst->asid = from->asid;
2258 dst->tlb_ctl = from->tlb_ctl;
2259 dst->int_ctl = from->int_ctl;
2260 dst->int_vector = from->int_vector;
2261 dst->int_state = from->int_state;
2262 dst->exit_code = from->exit_code;
2263 dst->exit_code_hi = from->exit_code_hi;
2264 dst->exit_info_1 = from->exit_info_1;
2265 dst->exit_info_2 = from->exit_info_2;
2266 dst->exit_int_info = from->exit_int_info;
2267 dst->exit_int_info_err = from->exit_int_info_err;
2268 dst->nested_ctl = from->nested_ctl;
2269 dst->event_inj = from->event_inj;
2270 dst->event_inj_err = from->event_inj_err;
2271 dst->nested_cr3 = from->nested_cr3;
2272 dst->lbr_ctl = from->lbr_ctl;
2273 }
2274
2275 static int nested_svm_vmexit(struct vcpu_svm *svm)
2276 {
2277 struct vmcb *nested_vmcb;
2278 struct vmcb *hsave = svm->nested.hsave;
2279 struct vmcb *vmcb = svm->vmcb;
2280 struct page *page;
2281
2282 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2283 vmcb->control.exit_info_1,
2284 vmcb->control.exit_info_2,
2285 vmcb->control.exit_int_info,
2286 vmcb->control.exit_int_info_err,
2287 KVM_ISA_SVM);
2288
2289 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2290 if (!nested_vmcb)
2291 return 1;
2292
2293 /* Exit Guest-Mode */
2294 leave_guest_mode(&svm->vcpu);
2295 svm->nested.vmcb = 0;
2296
2297 /* Give the current vmcb to the guest */
2298 disable_gif(svm);
2299
2300 nested_vmcb->save.es = vmcb->save.es;
2301 nested_vmcb->save.cs = vmcb->save.cs;
2302 nested_vmcb->save.ss = vmcb->save.ss;
2303 nested_vmcb->save.ds = vmcb->save.ds;
2304 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2305 nested_vmcb->save.idtr = vmcb->save.idtr;
2306 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2307 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2308 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2309 nested_vmcb->save.cr2 = vmcb->save.cr2;
2310 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2311 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2312 nested_vmcb->save.rip = vmcb->save.rip;
2313 nested_vmcb->save.rsp = vmcb->save.rsp;
2314 nested_vmcb->save.rax = vmcb->save.rax;
2315 nested_vmcb->save.dr7 = vmcb->save.dr7;
2316 nested_vmcb->save.dr6 = vmcb->save.dr6;
2317 nested_vmcb->save.cpl = vmcb->save.cpl;
2318
2319 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2320 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2321 nested_vmcb->control.int_state = vmcb->control.int_state;
2322 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2323 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2324 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2325 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2326 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2327 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2328 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2329
2330 /*
2331 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2332 * to make sure that we do not lose injected events. So check event_inj
2333 * here and copy it to exit_int_info if it is valid.
2334 * Exit_int_info and event_inj can't be both valid because the case
2335 * below only happens on a VMRUN instruction intercept which has
2336 * no valid exit_int_info set.
2337 */
2338 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2339 struct vmcb_control_area *nc = &nested_vmcb->control;
2340
2341 nc->exit_int_info = vmcb->control.event_inj;
2342 nc->exit_int_info_err = vmcb->control.event_inj_err;
2343 }
2344
2345 nested_vmcb->control.tlb_ctl = 0;
2346 nested_vmcb->control.event_inj = 0;
2347 nested_vmcb->control.event_inj_err = 0;
2348
2349 /* We always set V_INTR_MASKING and remember the old value in hflags */
2350 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2351 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2352
2353 /* Restore the original control entries */
2354 copy_vmcb_control_area(vmcb, hsave);
2355
2356 kvm_clear_exception_queue(&svm->vcpu);
2357 kvm_clear_interrupt_queue(&svm->vcpu);
2358
2359 svm->nested.nested_cr3 = 0;
2360
2361 /* Restore selected save entries */
2362 svm->vmcb->save.es = hsave->save.es;
2363 svm->vmcb->save.cs = hsave->save.cs;
2364 svm->vmcb->save.ss = hsave->save.ss;
2365 svm->vmcb->save.ds = hsave->save.ds;
2366 svm->vmcb->save.gdtr = hsave->save.gdtr;
2367 svm->vmcb->save.idtr = hsave->save.idtr;
2368 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2369 svm_set_efer(&svm->vcpu, hsave->save.efer);
2370 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2371 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2372 if (npt_enabled) {
2373 svm->vmcb->save.cr3 = hsave->save.cr3;
2374 svm->vcpu.arch.cr3 = hsave->save.cr3;
2375 } else {
2376 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2377 }
2378 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2379 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2380 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2381 svm->vmcb->save.dr7 = 0;
2382 svm->vmcb->save.cpl = 0;
2383 svm->vmcb->control.exit_int_info = 0;
2384
2385 mark_all_dirty(svm->vmcb);
2386
2387 nested_svm_unmap(page);
2388
2389 nested_svm_uninit_mmu_context(&svm->vcpu);
2390 kvm_mmu_reset_context(&svm->vcpu);
2391 kvm_mmu_load(&svm->vcpu);
2392
2393 return 0;
2394 }
2395
2396 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2397 {
2398 /*
2399 * This function merges the msr permission bitmaps of kvm and the
2400 * nested vmcb. It is omptimized in that it only merges the parts where
2401 * the kvm msr permission bitmap may contain zero bits
2402 */
2403 int i;
2404
2405 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2406 return true;
2407
2408 for (i = 0; i < MSRPM_OFFSETS; i++) {
2409 u32 value, p;
2410 u64 offset;
2411
2412 if (msrpm_offsets[i] == 0xffffffff)
2413 break;
2414
2415 p = msrpm_offsets[i];
2416 offset = svm->nested.vmcb_msrpm + (p * 4);
2417
2418 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2419 return false;
2420
2421 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2422 }
2423
2424 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2425
2426 return true;
2427 }
2428
2429 static bool nested_vmcb_checks(struct vmcb *vmcb)
2430 {
2431 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2432 return false;
2433
2434 if (vmcb->control.asid == 0)
2435 return false;
2436
2437 if (vmcb->control.nested_ctl && !npt_enabled)
2438 return false;
2439
2440 return true;
2441 }
2442
2443 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2444 {
2445 struct vmcb *nested_vmcb;
2446 struct vmcb *hsave = svm->nested.hsave;
2447 struct vmcb *vmcb = svm->vmcb;
2448 struct page *page;
2449 u64 vmcb_gpa;
2450
2451 vmcb_gpa = svm->vmcb->save.rax;
2452
2453 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2454 if (!nested_vmcb)
2455 return false;
2456
2457 if (!nested_vmcb_checks(nested_vmcb)) {
2458 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2459 nested_vmcb->control.exit_code_hi = 0;
2460 nested_vmcb->control.exit_info_1 = 0;
2461 nested_vmcb->control.exit_info_2 = 0;
2462
2463 nested_svm_unmap(page);
2464
2465 return false;
2466 }
2467
2468 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2469 nested_vmcb->save.rip,
2470 nested_vmcb->control.int_ctl,
2471 nested_vmcb->control.event_inj,
2472 nested_vmcb->control.nested_ctl);
2473
2474 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2475 nested_vmcb->control.intercept_cr >> 16,
2476 nested_vmcb->control.intercept_exceptions,
2477 nested_vmcb->control.intercept);
2478
2479 /* Clear internal status */
2480 kvm_clear_exception_queue(&svm->vcpu);
2481 kvm_clear_interrupt_queue(&svm->vcpu);
2482
2483 /*
2484 * Save the old vmcb, so we don't need to pick what we save, but can
2485 * restore everything when a VMEXIT occurs
2486 */
2487 hsave->save.es = vmcb->save.es;
2488 hsave->save.cs = vmcb->save.cs;
2489 hsave->save.ss = vmcb->save.ss;
2490 hsave->save.ds = vmcb->save.ds;
2491 hsave->save.gdtr = vmcb->save.gdtr;
2492 hsave->save.idtr = vmcb->save.idtr;
2493 hsave->save.efer = svm->vcpu.arch.efer;
2494 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2495 hsave->save.cr4 = svm->vcpu.arch.cr4;
2496 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2497 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2498 hsave->save.rsp = vmcb->save.rsp;
2499 hsave->save.rax = vmcb->save.rax;
2500 if (npt_enabled)
2501 hsave->save.cr3 = vmcb->save.cr3;
2502 else
2503 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2504
2505 copy_vmcb_control_area(hsave, vmcb);
2506
2507 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2508 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2509 else
2510 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2511
2512 if (nested_vmcb->control.nested_ctl) {
2513 kvm_mmu_unload(&svm->vcpu);
2514 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2515 nested_svm_init_mmu_context(&svm->vcpu);
2516 }
2517
2518 /* Load the nested guest state */
2519 svm->vmcb->save.es = nested_vmcb->save.es;
2520 svm->vmcb->save.cs = nested_vmcb->save.cs;
2521 svm->vmcb->save.ss = nested_vmcb->save.ss;
2522 svm->vmcb->save.ds = nested_vmcb->save.ds;
2523 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2524 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2525 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2526 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2527 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2528 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2529 if (npt_enabled) {
2530 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2531 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2532 } else
2533 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2534
2535 /* Guest paging mode is active - reset mmu */
2536 kvm_mmu_reset_context(&svm->vcpu);
2537
2538 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2539 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2540 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2541 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2542
2543 /* In case we don't even reach vcpu_run, the fields are not updated */
2544 svm->vmcb->save.rax = nested_vmcb->save.rax;
2545 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2546 svm->vmcb->save.rip = nested_vmcb->save.rip;
2547 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2548 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2549 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2550
2551 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2552 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2553
2554 /* cache intercepts */
2555 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2556 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2557 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2558 svm->nested.intercept = nested_vmcb->control.intercept;
2559
2560 svm_flush_tlb(&svm->vcpu);
2561 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2562 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2563 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2564 else
2565 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2566
2567 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2568 /* We only want the cr8 intercept bits of the guest */
2569 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2570 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2571 }
2572
2573 /* We don't want to see VMMCALLs from a nested guest */
2574 clr_intercept(svm, INTERCEPT_VMMCALL);
2575
2576 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2577 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2578 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2579 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2580 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2581 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2582
2583 nested_svm_unmap(page);
2584
2585 /* Enter Guest-Mode */
2586 enter_guest_mode(&svm->vcpu);
2587
2588 /*
2589 * Merge guest and host intercepts - must be called with vcpu in
2590 * guest-mode to take affect here
2591 */
2592 recalc_intercepts(svm);
2593
2594 svm->nested.vmcb = vmcb_gpa;
2595
2596 enable_gif(svm);
2597
2598 mark_all_dirty(svm->vmcb);
2599
2600 return true;
2601 }
2602
2603 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2604 {
2605 to_vmcb->save.fs = from_vmcb->save.fs;
2606 to_vmcb->save.gs = from_vmcb->save.gs;
2607 to_vmcb->save.tr = from_vmcb->save.tr;
2608 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2609 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2610 to_vmcb->save.star = from_vmcb->save.star;
2611 to_vmcb->save.lstar = from_vmcb->save.lstar;
2612 to_vmcb->save.cstar = from_vmcb->save.cstar;
2613 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2614 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2615 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2616 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2617 }
2618
2619 static int vmload_interception(struct vcpu_svm *svm)
2620 {
2621 struct vmcb *nested_vmcb;
2622 struct page *page;
2623
2624 if (nested_svm_check_permissions(svm))
2625 return 1;
2626
2627 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2628 if (!nested_vmcb)
2629 return 1;
2630
2631 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2632 skip_emulated_instruction(&svm->vcpu);
2633
2634 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2635 nested_svm_unmap(page);
2636
2637 return 1;
2638 }
2639
2640 static int vmsave_interception(struct vcpu_svm *svm)
2641 {
2642 struct vmcb *nested_vmcb;
2643 struct page *page;
2644
2645 if (nested_svm_check_permissions(svm))
2646 return 1;
2647
2648 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2649 if (!nested_vmcb)
2650 return 1;
2651
2652 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2653 skip_emulated_instruction(&svm->vcpu);
2654
2655 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2656 nested_svm_unmap(page);
2657
2658 return 1;
2659 }
2660
2661 static int vmrun_interception(struct vcpu_svm *svm)
2662 {
2663 if (nested_svm_check_permissions(svm))
2664 return 1;
2665
2666 /* Save rip after vmrun instruction */
2667 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2668
2669 if (!nested_svm_vmrun(svm))
2670 return 1;
2671
2672 if (!nested_svm_vmrun_msrpm(svm))
2673 goto failed;
2674
2675 return 1;
2676
2677 failed:
2678
2679 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2680 svm->vmcb->control.exit_code_hi = 0;
2681 svm->vmcb->control.exit_info_1 = 0;
2682 svm->vmcb->control.exit_info_2 = 0;
2683
2684 nested_svm_vmexit(svm);
2685
2686 return 1;
2687 }
2688
2689 static int stgi_interception(struct vcpu_svm *svm)
2690 {
2691 if (nested_svm_check_permissions(svm))
2692 return 1;
2693
2694 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2695 skip_emulated_instruction(&svm->vcpu);
2696 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2697
2698 enable_gif(svm);
2699
2700 return 1;
2701 }
2702
2703 static int clgi_interception(struct vcpu_svm *svm)
2704 {
2705 if (nested_svm_check_permissions(svm))
2706 return 1;
2707
2708 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2709 skip_emulated_instruction(&svm->vcpu);
2710
2711 disable_gif(svm);
2712
2713 /* After a CLGI no interrupts should come */
2714 svm_clear_vintr(svm);
2715 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2716
2717 mark_dirty(svm->vmcb, VMCB_INTR);
2718
2719 return 1;
2720 }
2721
2722 static int invlpga_interception(struct vcpu_svm *svm)
2723 {
2724 struct kvm_vcpu *vcpu = &svm->vcpu;
2725
2726 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2727 vcpu->arch.regs[VCPU_REGS_RAX]);
2728
2729 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2730 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2731
2732 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2733 skip_emulated_instruction(&svm->vcpu);
2734 return 1;
2735 }
2736
2737 static int skinit_interception(struct vcpu_svm *svm)
2738 {
2739 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2740
2741 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2742 return 1;
2743 }
2744
2745 static int xsetbv_interception(struct vcpu_svm *svm)
2746 {
2747 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2748 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2749
2750 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2751 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2752 skip_emulated_instruction(&svm->vcpu);
2753 }
2754
2755 return 1;
2756 }
2757
2758 static int invalid_op_interception(struct vcpu_svm *svm)
2759 {
2760 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2761 return 1;
2762 }
2763
2764 static int task_switch_interception(struct vcpu_svm *svm)
2765 {
2766 u16 tss_selector;
2767 int reason;
2768 int int_type = svm->vmcb->control.exit_int_info &
2769 SVM_EXITINTINFO_TYPE_MASK;
2770 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2771 uint32_t type =
2772 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2773 uint32_t idt_v =
2774 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2775 bool has_error_code = false;
2776 u32 error_code = 0;
2777
2778 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2779
2780 if (svm->vmcb->control.exit_info_2 &
2781 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2782 reason = TASK_SWITCH_IRET;
2783 else if (svm->vmcb->control.exit_info_2 &
2784 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2785 reason = TASK_SWITCH_JMP;
2786 else if (idt_v)
2787 reason = TASK_SWITCH_GATE;
2788 else
2789 reason = TASK_SWITCH_CALL;
2790
2791 if (reason == TASK_SWITCH_GATE) {
2792 switch (type) {
2793 case SVM_EXITINTINFO_TYPE_NMI:
2794 svm->vcpu.arch.nmi_injected = false;
2795 break;
2796 case SVM_EXITINTINFO_TYPE_EXEPT:
2797 if (svm->vmcb->control.exit_info_2 &
2798 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2799 has_error_code = true;
2800 error_code =
2801 (u32)svm->vmcb->control.exit_info_2;
2802 }
2803 kvm_clear_exception_queue(&svm->vcpu);
2804 break;
2805 case SVM_EXITINTINFO_TYPE_INTR:
2806 kvm_clear_interrupt_queue(&svm->vcpu);
2807 break;
2808 default:
2809 break;
2810 }
2811 }
2812
2813 if (reason != TASK_SWITCH_GATE ||
2814 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2815 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2816 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2817 skip_emulated_instruction(&svm->vcpu);
2818
2819 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2820 int_vec = -1;
2821
2822 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2823 has_error_code, error_code) == EMULATE_FAIL) {
2824 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2825 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2826 svm->vcpu.run->internal.ndata = 0;
2827 return 0;
2828 }
2829 return 1;
2830 }
2831
2832 static int cpuid_interception(struct vcpu_svm *svm)
2833 {
2834 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2835 kvm_emulate_cpuid(&svm->vcpu);
2836 return 1;
2837 }
2838
2839 static int iret_interception(struct vcpu_svm *svm)
2840 {
2841 ++svm->vcpu.stat.nmi_window_exits;
2842 clr_intercept(svm, INTERCEPT_IRET);
2843 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2844 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2845 return 1;
2846 }
2847
2848 static int invlpg_interception(struct vcpu_svm *svm)
2849 {
2850 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2851 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2852
2853 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2854 skip_emulated_instruction(&svm->vcpu);
2855 return 1;
2856 }
2857
2858 static int emulate_on_interception(struct vcpu_svm *svm)
2859 {
2860 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2861 }
2862
2863 static int rdpmc_interception(struct vcpu_svm *svm)
2864 {
2865 int err;
2866
2867 if (!static_cpu_has(X86_FEATURE_NRIPS))
2868 return emulate_on_interception(svm);
2869
2870 err = kvm_rdpmc(&svm->vcpu);
2871 kvm_complete_insn_gp(&svm->vcpu, err);
2872
2873 return 1;
2874 }
2875
2876 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2877 {
2878 unsigned long cr0 = svm->vcpu.arch.cr0;
2879 bool ret = false;
2880 u64 intercept;
2881
2882 intercept = svm->nested.intercept;
2883
2884 if (!is_guest_mode(&svm->vcpu) ||
2885 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2886 return false;
2887
2888 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2889 val &= ~SVM_CR0_SELECTIVE_MASK;
2890
2891 if (cr0 ^ val) {
2892 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2893 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2894 }
2895
2896 return ret;
2897 }
2898
2899 #define CR_VALID (1ULL << 63)
2900
2901 static int cr_interception(struct vcpu_svm *svm)
2902 {
2903 int reg, cr;
2904 unsigned long val;
2905 int err;
2906
2907 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2908 return emulate_on_interception(svm);
2909
2910 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2911 return emulate_on_interception(svm);
2912
2913 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2914 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2915
2916 err = 0;
2917 if (cr >= 16) { /* mov to cr */
2918 cr -= 16;
2919 val = kvm_register_read(&svm->vcpu, reg);
2920 switch (cr) {
2921 case 0:
2922 if (!check_selective_cr0_intercepted(svm, val))
2923 err = kvm_set_cr0(&svm->vcpu, val);
2924 else
2925 return 1;
2926
2927 break;
2928 case 3:
2929 err = kvm_set_cr3(&svm->vcpu, val);
2930 break;
2931 case 4:
2932 err = kvm_set_cr4(&svm->vcpu, val);
2933 break;
2934 case 8:
2935 err = kvm_set_cr8(&svm->vcpu, val);
2936 break;
2937 default:
2938 WARN(1, "unhandled write to CR%d", cr);
2939 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2940 return 1;
2941 }
2942 } else { /* mov from cr */
2943 switch (cr) {
2944 case 0:
2945 val = kvm_read_cr0(&svm->vcpu);
2946 break;
2947 case 2:
2948 val = svm->vcpu.arch.cr2;
2949 break;
2950 case 3:
2951 val = kvm_read_cr3(&svm->vcpu);
2952 break;
2953 case 4:
2954 val = kvm_read_cr4(&svm->vcpu);
2955 break;
2956 case 8:
2957 val = kvm_get_cr8(&svm->vcpu);
2958 break;
2959 default:
2960 WARN(1, "unhandled read from CR%d", cr);
2961 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2962 return 1;
2963 }
2964 kvm_register_write(&svm->vcpu, reg, val);
2965 }
2966 kvm_complete_insn_gp(&svm->vcpu, err);
2967
2968 return 1;
2969 }
2970
2971 static int dr_interception(struct vcpu_svm *svm)
2972 {
2973 int reg, dr;
2974 unsigned long val;
2975 int err;
2976
2977 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2978 return emulate_on_interception(svm);
2979
2980 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2981 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2982
2983 if (dr >= 16) { /* mov to DRn */
2984 val = kvm_register_read(&svm->vcpu, reg);
2985 kvm_set_dr(&svm->vcpu, dr - 16, val);
2986 } else {
2987 err = kvm_get_dr(&svm->vcpu, dr, &val);
2988 if (!err)
2989 kvm_register_write(&svm->vcpu, reg, val);
2990 }
2991
2992 skip_emulated_instruction(&svm->vcpu);
2993
2994 return 1;
2995 }
2996
2997 static int cr8_write_interception(struct vcpu_svm *svm)
2998 {
2999 struct kvm_run *kvm_run = svm->vcpu.run;
3000 int r;
3001
3002 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3003 /* instruction emulation calls kvm_set_cr8() */
3004 r = cr_interception(svm);
3005 if (irqchip_in_kernel(svm->vcpu.kvm)) {
3006 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3007 return r;
3008 }
3009 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3010 return r;
3011 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3012 return 0;
3013 }
3014
3015 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
3016 {
3017 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3018 return vmcb->control.tsc_offset +
3019 svm_scale_tsc(vcpu, native_read_tsc());
3020 }
3021
3022 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3023 {
3024 struct vcpu_svm *svm = to_svm(vcpu);
3025
3026 switch (ecx) {
3027 case MSR_IA32_TSC: {
3028 *data = svm->vmcb->control.tsc_offset +
3029 svm_scale_tsc(vcpu, native_read_tsc());
3030
3031 break;
3032 }
3033 case MSR_STAR:
3034 *data = svm->vmcb->save.star;
3035 break;
3036 #ifdef CONFIG_X86_64
3037 case MSR_LSTAR:
3038 *data = svm->vmcb->save.lstar;
3039 break;
3040 case MSR_CSTAR:
3041 *data = svm->vmcb->save.cstar;
3042 break;
3043 case MSR_KERNEL_GS_BASE:
3044 *data = svm->vmcb->save.kernel_gs_base;
3045 break;
3046 case MSR_SYSCALL_MASK:
3047 *data = svm->vmcb->save.sfmask;
3048 break;
3049 #endif
3050 case MSR_IA32_SYSENTER_CS:
3051 *data = svm->vmcb->save.sysenter_cs;
3052 break;
3053 case MSR_IA32_SYSENTER_EIP:
3054 *data = svm->sysenter_eip;
3055 break;
3056 case MSR_IA32_SYSENTER_ESP:
3057 *data = svm->sysenter_esp;
3058 break;
3059 /*
3060 * Nobody will change the following 5 values in the VMCB so we can
3061 * safely return them on rdmsr. They will always be 0 until LBRV is
3062 * implemented.
3063 */
3064 case MSR_IA32_DEBUGCTLMSR:
3065 *data = svm->vmcb->save.dbgctl;
3066 break;
3067 case MSR_IA32_LASTBRANCHFROMIP:
3068 *data = svm->vmcb->save.br_from;
3069 break;
3070 case MSR_IA32_LASTBRANCHTOIP:
3071 *data = svm->vmcb->save.br_to;
3072 break;
3073 case MSR_IA32_LASTINTFROMIP:
3074 *data = svm->vmcb->save.last_excp_from;
3075 break;
3076 case MSR_IA32_LASTINTTOIP:
3077 *data = svm->vmcb->save.last_excp_to;
3078 break;
3079 case MSR_VM_HSAVE_PA:
3080 *data = svm->nested.hsave_msr;
3081 break;
3082 case MSR_VM_CR:
3083 *data = svm->nested.vm_cr_msr;
3084 break;
3085 case MSR_IA32_UCODE_REV:
3086 *data = 0x01000065;
3087 break;
3088 default:
3089 return kvm_get_msr_common(vcpu, ecx, data);
3090 }
3091 return 0;
3092 }
3093
3094 static int rdmsr_interception(struct vcpu_svm *svm)
3095 {
3096 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3097 u64 data;
3098
3099 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3100 trace_kvm_msr_read_ex(ecx);
3101 kvm_inject_gp(&svm->vcpu, 0);
3102 } else {
3103 trace_kvm_msr_read(ecx, data);
3104
3105 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3106 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3107 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3108 skip_emulated_instruction(&svm->vcpu);
3109 }
3110 return 1;
3111 }
3112
3113 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3114 {
3115 struct vcpu_svm *svm = to_svm(vcpu);
3116 int svm_dis, chg_mask;
3117
3118 if (data & ~SVM_VM_CR_VALID_MASK)
3119 return 1;
3120
3121 chg_mask = SVM_VM_CR_VALID_MASK;
3122
3123 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3124 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3125
3126 svm->nested.vm_cr_msr &= ~chg_mask;
3127 svm->nested.vm_cr_msr |= (data & chg_mask);
3128
3129 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3130
3131 /* check for svm_disable while efer.svme is set */
3132 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3133 return 1;
3134
3135 return 0;
3136 }
3137
3138 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3139 {
3140 struct vcpu_svm *svm = to_svm(vcpu);
3141
3142 switch (ecx) {
3143 case MSR_IA32_TSC:
3144 kvm_write_tsc(vcpu, data);
3145 break;
3146 case MSR_STAR:
3147 svm->vmcb->save.star = data;
3148 break;
3149 #ifdef CONFIG_X86_64
3150 case MSR_LSTAR:
3151 svm->vmcb->save.lstar = data;
3152 break;
3153 case MSR_CSTAR:
3154 svm->vmcb->save.cstar = data;
3155 break;
3156 case MSR_KERNEL_GS_BASE:
3157 svm->vmcb->save.kernel_gs_base = data;
3158 break;
3159 case MSR_SYSCALL_MASK:
3160 svm->vmcb->save.sfmask = data;
3161 break;
3162 #endif
3163 case MSR_IA32_SYSENTER_CS:
3164 svm->vmcb->save.sysenter_cs = data;
3165 break;
3166 case MSR_IA32_SYSENTER_EIP:
3167 svm->sysenter_eip = data;
3168 svm->vmcb->save.sysenter_eip = data;
3169 break;
3170 case MSR_IA32_SYSENTER_ESP:
3171 svm->sysenter_esp = data;
3172 svm->vmcb->save.sysenter_esp = data;
3173 break;
3174 case MSR_IA32_DEBUGCTLMSR:
3175 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3176 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3177 __func__, data);
3178 break;
3179 }
3180 if (data & DEBUGCTL_RESERVED_BITS)
3181 return 1;
3182
3183 svm->vmcb->save.dbgctl = data;
3184 mark_dirty(svm->vmcb, VMCB_LBR);
3185 if (data & (1ULL<<0))
3186 svm_enable_lbrv(svm);
3187 else
3188 svm_disable_lbrv(svm);
3189 break;
3190 case MSR_VM_HSAVE_PA:
3191 svm->nested.hsave_msr = data;
3192 break;
3193 case MSR_VM_CR:
3194 return svm_set_vm_cr(vcpu, data);
3195 case MSR_VM_IGNNE:
3196 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3197 break;
3198 default:
3199 return kvm_set_msr_common(vcpu, ecx, data);
3200 }
3201 return 0;
3202 }
3203
3204 static int wrmsr_interception(struct vcpu_svm *svm)
3205 {
3206 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3207 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3208 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3209
3210
3211 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3212 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3213 trace_kvm_msr_write_ex(ecx, data);
3214 kvm_inject_gp(&svm->vcpu, 0);
3215 } else {
3216 trace_kvm_msr_write(ecx, data);
3217 skip_emulated_instruction(&svm->vcpu);
3218 }
3219 return 1;
3220 }
3221
3222 static int msr_interception(struct vcpu_svm *svm)
3223 {
3224 if (svm->vmcb->control.exit_info_1)
3225 return wrmsr_interception(svm);
3226 else
3227 return rdmsr_interception(svm);
3228 }
3229
3230 static int interrupt_window_interception(struct vcpu_svm *svm)
3231 {
3232 struct kvm_run *kvm_run = svm->vcpu.run;
3233
3234 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3235 svm_clear_vintr(svm);
3236 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3237 mark_dirty(svm->vmcb, VMCB_INTR);
3238 /*
3239 * If the user space waits to inject interrupts, exit as soon as
3240 * possible
3241 */
3242 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3243 kvm_run->request_interrupt_window &&
3244 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3245 ++svm->vcpu.stat.irq_window_exits;
3246 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3247 return 0;
3248 }
3249
3250 return 1;
3251 }
3252
3253 static int pause_interception(struct vcpu_svm *svm)
3254 {
3255 kvm_vcpu_on_spin(&(svm->vcpu));
3256 return 1;
3257 }
3258
3259 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3260 [SVM_EXIT_READ_CR0] = cr_interception,
3261 [SVM_EXIT_READ_CR3] = cr_interception,
3262 [SVM_EXIT_READ_CR4] = cr_interception,
3263 [SVM_EXIT_READ_CR8] = cr_interception,
3264 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3265 [SVM_EXIT_WRITE_CR0] = cr_interception,
3266 [SVM_EXIT_WRITE_CR3] = cr_interception,
3267 [SVM_EXIT_WRITE_CR4] = cr_interception,
3268 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3269 [SVM_EXIT_READ_DR0] = dr_interception,
3270 [SVM_EXIT_READ_DR1] = dr_interception,
3271 [SVM_EXIT_READ_DR2] = dr_interception,
3272 [SVM_EXIT_READ_DR3] = dr_interception,
3273 [SVM_EXIT_READ_DR4] = dr_interception,
3274 [SVM_EXIT_READ_DR5] = dr_interception,
3275 [SVM_EXIT_READ_DR6] = dr_interception,
3276 [SVM_EXIT_READ_DR7] = dr_interception,
3277 [SVM_EXIT_WRITE_DR0] = dr_interception,
3278 [SVM_EXIT_WRITE_DR1] = dr_interception,
3279 [SVM_EXIT_WRITE_DR2] = dr_interception,
3280 [SVM_EXIT_WRITE_DR3] = dr_interception,
3281 [SVM_EXIT_WRITE_DR4] = dr_interception,
3282 [SVM_EXIT_WRITE_DR5] = dr_interception,
3283 [SVM_EXIT_WRITE_DR6] = dr_interception,
3284 [SVM_EXIT_WRITE_DR7] = dr_interception,
3285 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3286 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3287 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3288 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3289 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3290 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3291 [SVM_EXIT_INTR] = intr_interception,
3292 [SVM_EXIT_NMI] = nmi_interception,
3293 [SVM_EXIT_SMI] = nop_on_interception,
3294 [SVM_EXIT_INIT] = nop_on_interception,
3295 [SVM_EXIT_VINTR] = interrupt_window_interception,
3296 [SVM_EXIT_RDPMC] = rdpmc_interception,
3297 [SVM_EXIT_CPUID] = cpuid_interception,
3298 [SVM_EXIT_IRET] = iret_interception,
3299 [SVM_EXIT_INVD] = emulate_on_interception,
3300 [SVM_EXIT_PAUSE] = pause_interception,
3301 [SVM_EXIT_HLT] = halt_interception,
3302 [SVM_EXIT_INVLPG] = invlpg_interception,
3303 [SVM_EXIT_INVLPGA] = invlpga_interception,
3304 [SVM_EXIT_IOIO] = io_interception,
3305 [SVM_EXIT_MSR] = msr_interception,
3306 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3307 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3308 [SVM_EXIT_VMRUN] = vmrun_interception,
3309 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3310 [SVM_EXIT_VMLOAD] = vmload_interception,
3311 [SVM_EXIT_VMSAVE] = vmsave_interception,
3312 [SVM_EXIT_STGI] = stgi_interception,
3313 [SVM_EXIT_CLGI] = clgi_interception,
3314 [SVM_EXIT_SKINIT] = skinit_interception,
3315 [SVM_EXIT_WBINVD] = emulate_on_interception,
3316 [SVM_EXIT_MONITOR] = invalid_op_interception,
3317 [SVM_EXIT_MWAIT] = invalid_op_interception,
3318 [SVM_EXIT_XSETBV] = xsetbv_interception,
3319 [SVM_EXIT_NPF] = pf_interception,
3320 };
3321
3322 static void dump_vmcb(struct kvm_vcpu *vcpu)
3323 {
3324 struct vcpu_svm *svm = to_svm(vcpu);
3325 struct vmcb_control_area *control = &svm->vmcb->control;
3326 struct vmcb_save_area *save = &svm->vmcb->save;
3327
3328 pr_err("VMCB Control Area:\n");
3329 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3330 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3331 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3332 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3333 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3334 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3335 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3336 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3337 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3338 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3339 pr_err("%-20s%d\n", "asid:", control->asid);
3340 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3341 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3342 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3343 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3344 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3345 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3346 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3347 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3348 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3349 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3350 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3351 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3352 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3353 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3354 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3355 pr_err("VMCB State Save Area:\n");
3356 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3357 "es:",
3358 save->es.selector, save->es.attrib,
3359 save->es.limit, save->es.base);
3360 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3361 "cs:",
3362 save->cs.selector, save->cs.attrib,
3363 save->cs.limit, save->cs.base);
3364 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3365 "ss:",
3366 save->ss.selector, save->ss.attrib,
3367 save->ss.limit, save->ss.base);
3368 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3369 "ds:",
3370 save->ds.selector, save->ds.attrib,
3371 save->ds.limit, save->ds.base);
3372 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3373 "fs:",
3374 save->fs.selector, save->fs.attrib,
3375 save->fs.limit, save->fs.base);
3376 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3377 "gs:",
3378 save->gs.selector, save->gs.attrib,
3379 save->gs.limit, save->gs.base);
3380 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3381 "gdtr:",
3382 save->gdtr.selector, save->gdtr.attrib,
3383 save->gdtr.limit, save->gdtr.base);
3384 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3385 "ldtr:",
3386 save->ldtr.selector, save->ldtr.attrib,
3387 save->ldtr.limit, save->ldtr.base);
3388 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3389 "idtr:",
3390 save->idtr.selector, save->idtr.attrib,
3391 save->idtr.limit, save->idtr.base);
3392 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3393 "tr:",
3394 save->tr.selector, save->tr.attrib,
3395 save->tr.limit, save->tr.base);
3396 pr_err("cpl: %d efer: %016llx\n",
3397 save->cpl, save->efer);
3398 pr_err("%-15s %016llx %-13s %016llx\n",
3399 "cr0:", save->cr0, "cr2:", save->cr2);
3400 pr_err("%-15s %016llx %-13s %016llx\n",
3401 "cr3:", save->cr3, "cr4:", save->cr4);
3402 pr_err("%-15s %016llx %-13s %016llx\n",
3403 "dr6:", save->dr6, "dr7:", save->dr7);
3404 pr_err("%-15s %016llx %-13s %016llx\n",
3405 "rip:", save->rip, "rflags:", save->rflags);
3406 pr_err("%-15s %016llx %-13s %016llx\n",
3407 "rsp:", save->rsp, "rax:", save->rax);
3408 pr_err("%-15s %016llx %-13s %016llx\n",
3409 "star:", save->star, "lstar:", save->lstar);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "cstar:", save->cstar, "sfmask:", save->sfmask);
3412 pr_err("%-15s %016llx %-13s %016llx\n",
3413 "kernel_gs_base:", save->kernel_gs_base,
3414 "sysenter_cs:", save->sysenter_cs);
3415 pr_err("%-15s %016llx %-13s %016llx\n",
3416 "sysenter_esp:", save->sysenter_esp,
3417 "sysenter_eip:", save->sysenter_eip);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3420 pr_err("%-15s %016llx %-13s %016llx\n",
3421 "br_from:", save->br_from, "br_to:", save->br_to);
3422 pr_err("%-15s %016llx %-13s %016llx\n",
3423 "excp_from:", save->last_excp_from,
3424 "excp_to:", save->last_excp_to);
3425 }
3426
3427 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3428 {
3429 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3430
3431 *info1 = control->exit_info_1;
3432 *info2 = control->exit_info_2;
3433 }
3434
3435 static int handle_exit(struct kvm_vcpu *vcpu)
3436 {
3437 struct vcpu_svm *svm = to_svm(vcpu);
3438 struct kvm_run *kvm_run = vcpu->run;
3439 u32 exit_code = svm->vmcb->control.exit_code;
3440
3441 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3442 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3443 if (npt_enabled)
3444 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3445
3446 if (unlikely(svm->nested.exit_required)) {
3447 nested_svm_vmexit(svm);
3448 svm->nested.exit_required = false;
3449
3450 return 1;
3451 }
3452
3453 if (is_guest_mode(vcpu)) {
3454 int vmexit;
3455
3456 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3457 svm->vmcb->control.exit_info_1,
3458 svm->vmcb->control.exit_info_2,
3459 svm->vmcb->control.exit_int_info,
3460 svm->vmcb->control.exit_int_info_err,
3461 KVM_ISA_SVM);
3462
3463 vmexit = nested_svm_exit_special(svm);
3464
3465 if (vmexit == NESTED_EXIT_CONTINUE)
3466 vmexit = nested_svm_exit_handled(svm);
3467
3468 if (vmexit == NESTED_EXIT_DONE)
3469 return 1;
3470 }
3471
3472 svm_complete_interrupts(svm);
3473
3474 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3475 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3476 kvm_run->fail_entry.hardware_entry_failure_reason
3477 = svm->vmcb->control.exit_code;
3478 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3479 dump_vmcb(vcpu);
3480 return 0;
3481 }
3482
3483 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3484 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3485 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3486 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3487 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3488 "exit_code 0x%x\n",
3489 __func__, svm->vmcb->control.exit_int_info,
3490 exit_code);
3491
3492 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3493 || !svm_exit_handlers[exit_code]) {
3494 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3495 kvm_run->hw.hardware_exit_reason = exit_code;
3496 return 0;
3497 }
3498
3499 return svm_exit_handlers[exit_code](svm);
3500 }
3501
3502 static void reload_tss(struct kvm_vcpu *vcpu)
3503 {
3504 int cpu = raw_smp_processor_id();
3505
3506 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3507 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3508 load_TR_desc();
3509 }
3510
3511 static void pre_svm_run(struct vcpu_svm *svm)
3512 {
3513 int cpu = raw_smp_processor_id();
3514
3515 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3516
3517 /* FIXME: handle wraparound of asid_generation */
3518 if (svm->asid_generation != sd->asid_generation)
3519 new_asid(svm, sd);
3520 }
3521
3522 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3523 {
3524 struct vcpu_svm *svm = to_svm(vcpu);
3525
3526 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3527 vcpu->arch.hflags |= HF_NMI_MASK;
3528 set_intercept(svm, INTERCEPT_IRET);
3529 ++vcpu->stat.nmi_injections;
3530 }
3531
3532 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3533 {
3534 struct vmcb_control_area *control;
3535
3536 control = &svm->vmcb->control;
3537 control->int_vector = irq;
3538 control->int_ctl &= ~V_INTR_PRIO_MASK;
3539 control->int_ctl |= V_IRQ_MASK |
3540 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3541 mark_dirty(svm->vmcb, VMCB_INTR);
3542 }
3543
3544 static void svm_set_irq(struct kvm_vcpu *vcpu)
3545 {
3546 struct vcpu_svm *svm = to_svm(vcpu);
3547
3548 BUG_ON(!(gif_set(svm)));
3549
3550 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3551 ++vcpu->stat.irq_injections;
3552
3553 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3554 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3555 }
3556
3557 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3558 {
3559 struct vcpu_svm *svm = to_svm(vcpu);
3560
3561 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3562 return;
3563
3564 if (irr == -1)
3565 return;
3566
3567 if (tpr >= irr)
3568 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3569 }
3570
3571 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3572 {
3573 struct vcpu_svm *svm = to_svm(vcpu);
3574 struct vmcb *vmcb = svm->vmcb;
3575 int ret;
3576 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3577 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3578 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3579
3580 return ret;
3581 }
3582
3583 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3584 {
3585 struct vcpu_svm *svm = to_svm(vcpu);
3586
3587 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3588 }
3589
3590 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3591 {
3592 struct vcpu_svm *svm = to_svm(vcpu);
3593
3594 if (masked) {
3595 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3596 set_intercept(svm, INTERCEPT_IRET);
3597 } else {
3598 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3599 clr_intercept(svm, INTERCEPT_IRET);
3600 }
3601 }
3602
3603 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3604 {
3605 struct vcpu_svm *svm = to_svm(vcpu);
3606 struct vmcb *vmcb = svm->vmcb;
3607 int ret;
3608
3609 if (!gif_set(svm) ||
3610 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3611 return 0;
3612
3613 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3614
3615 if (is_guest_mode(vcpu))
3616 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3617
3618 return ret;
3619 }
3620
3621 static void enable_irq_window(struct kvm_vcpu *vcpu)
3622 {
3623 struct vcpu_svm *svm = to_svm(vcpu);
3624
3625 /*
3626 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3627 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3628 * get that intercept, this function will be called again though and
3629 * we'll get the vintr intercept.
3630 */
3631 if (gif_set(svm) && nested_svm_intr(svm)) {
3632 svm_set_vintr(svm);
3633 svm_inject_irq(svm, 0x0);
3634 }
3635 }
3636
3637 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3638 {
3639 struct vcpu_svm *svm = to_svm(vcpu);
3640
3641 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3642 == HF_NMI_MASK)
3643 return; /* IRET will cause a vm exit */
3644
3645 /*
3646 * Something prevents NMI from been injected. Single step over possible
3647 * problem (IRET or exception injection or interrupt shadow)
3648 */
3649 svm->nmi_singlestep = true;
3650 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3651 update_db_intercept(vcpu);
3652 }
3653
3654 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3655 {
3656 return 0;
3657 }
3658
3659 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3660 {
3661 struct vcpu_svm *svm = to_svm(vcpu);
3662
3663 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3664 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3665 else
3666 svm->asid_generation--;
3667 }
3668
3669 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3670 {
3671 }
3672
3673 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3674 {
3675 struct vcpu_svm *svm = to_svm(vcpu);
3676
3677 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3678 return;
3679
3680 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3681 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3682 kvm_set_cr8(vcpu, cr8);
3683 }
3684 }
3685
3686 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3687 {
3688 struct vcpu_svm *svm = to_svm(vcpu);
3689 u64 cr8;
3690
3691 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3692 return;
3693
3694 cr8 = kvm_get_cr8(vcpu);
3695 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3696 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3697 }
3698
3699 static void svm_complete_interrupts(struct vcpu_svm *svm)
3700 {
3701 u8 vector;
3702 int type;
3703 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3704 unsigned int3_injected = svm->int3_injected;
3705
3706 svm->int3_injected = 0;
3707
3708 /*
3709 * If we've made progress since setting HF_IRET_MASK, we've
3710 * executed an IRET and can allow NMI injection.
3711 */
3712 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3713 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3714 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3715 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3716 }
3717
3718 svm->vcpu.arch.nmi_injected = false;
3719 kvm_clear_exception_queue(&svm->vcpu);
3720 kvm_clear_interrupt_queue(&svm->vcpu);
3721
3722 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3723 return;
3724
3725 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3726
3727 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3728 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3729
3730 switch (type) {
3731 case SVM_EXITINTINFO_TYPE_NMI:
3732 svm->vcpu.arch.nmi_injected = true;
3733 break;
3734 case SVM_EXITINTINFO_TYPE_EXEPT:
3735 /*
3736 * In case of software exceptions, do not reinject the vector,
3737 * but re-execute the instruction instead. Rewind RIP first
3738 * if we emulated INT3 before.
3739 */
3740 if (kvm_exception_is_soft(vector)) {
3741 if (vector == BP_VECTOR && int3_injected &&
3742 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3743 kvm_rip_write(&svm->vcpu,
3744 kvm_rip_read(&svm->vcpu) -
3745 int3_injected);
3746 break;
3747 }
3748 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3749 u32 err = svm->vmcb->control.exit_int_info_err;
3750 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3751
3752 } else
3753 kvm_requeue_exception(&svm->vcpu, vector);
3754 break;
3755 case SVM_EXITINTINFO_TYPE_INTR:
3756 kvm_queue_interrupt(&svm->vcpu, vector, false);
3757 break;
3758 default:
3759 break;
3760 }
3761 }
3762
3763 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3764 {
3765 struct vcpu_svm *svm = to_svm(vcpu);
3766 struct vmcb_control_area *control = &svm->vmcb->control;
3767
3768 control->exit_int_info = control->event_inj;
3769 control->exit_int_info_err = control->event_inj_err;
3770 control->event_inj = 0;
3771 svm_complete_interrupts(svm);
3772 }
3773
3774 #ifdef CONFIG_X86_64
3775 #define R "r"
3776 #else
3777 #define R "e"
3778 #endif
3779
3780 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3781 {
3782 struct vcpu_svm *svm = to_svm(vcpu);
3783
3784 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3785 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3786 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3787
3788 /*
3789 * A vmexit emulation is required before the vcpu can be executed
3790 * again.
3791 */
3792 if (unlikely(svm->nested.exit_required))
3793 return;
3794
3795 pre_svm_run(svm);
3796
3797 sync_lapic_to_cr8(vcpu);
3798
3799 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3800
3801 clgi();
3802
3803 local_irq_enable();
3804
3805 asm volatile (
3806 "push %%"R"bp; \n\t"
3807 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3808 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3809 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3810 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3811 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3812 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3813 #ifdef CONFIG_X86_64
3814 "mov %c[r8](%[svm]), %%r8 \n\t"
3815 "mov %c[r9](%[svm]), %%r9 \n\t"
3816 "mov %c[r10](%[svm]), %%r10 \n\t"
3817 "mov %c[r11](%[svm]), %%r11 \n\t"
3818 "mov %c[r12](%[svm]), %%r12 \n\t"
3819 "mov %c[r13](%[svm]), %%r13 \n\t"
3820 "mov %c[r14](%[svm]), %%r14 \n\t"
3821 "mov %c[r15](%[svm]), %%r15 \n\t"
3822 #endif
3823
3824 /* Enter guest mode */
3825 "push %%"R"ax \n\t"
3826 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3827 __ex(SVM_VMLOAD) "\n\t"
3828 __ex(SVM_VMRUN) "\n\t"
3829 __ex(SVM_VMSAVE) "\n\t"
3830 "pop %%"R"ax \n\t"
3831
3832 /* Save guest registers, load host registers */
3833 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3834 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3835 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3836 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3837 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3838 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3839 #ifdef CONFIG_X86_64
3840 "mov %%r8, %c[r8](%[svm]) \n\t"
3841 "mov %%r9, %c[r9](%[svm]) \n\t"
3842 "mov %%r10, %c[r10](%[svm]) \n\t"
3843 "mov %%r11, %c[r11](%[svm]) \n\t"
3844 "mov %%r12, %c[r12](%[svm]) \n\t"
3845 "mov %%r13, %c[r13](%[svm]) \n\t"
3846 "mov %%r14, %c[r14](%[svm]) \n\t"
3847 "mov %%r15, %c[r15](%[svm]) \n\t"
3848 #endif
3849 "pop %%"R"bp"
3850 :
3851 : [svm]"a"(svm),
3852 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3853 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3854 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3855 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3856 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3857 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3858 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3859 #ifdef CONFIG_X86_64
3860 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3861 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3862 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3863 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3864 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3865 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3866 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3867 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3868 #endif
3869 : "cc", "memory"
3870 , R"bx", R"cx", R"dx", R"si", R"di"
3871 #ifdef CONFIG_X86_64
3872 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3873 #endif
3874 );
3875
3876 #ifdef CONFIG_X86_64
3877 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3878 #else
3879 loadsegment(fs, svm->host.fs);
3880 #ifndef CONFIG_X86_32_LAZY_GS
3881 loadsegment(gs, svm->host.gs);
3882 #endif
3883 #endif
3884
3885 reload_tss(vcpu);
3886
3887 local_irq_disable();
3888
3889 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3890 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3891 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3892 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3893
3894 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3895
3896 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3897 kvm_before_handle_nmi(&svm->vcpu);
3898
3899 stgi();
3900
3901 /* Any pending NMI will happen here */
3902
3903 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3904 kvm_after_handle_nmi(&svm->vcpu);
3905
3906 sync_cr8_to_lapic(vcpu);
3907
3908 svm->next_rip = 0;
3909
3910 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3911
3912 /* if exit due to PF check for async PF */
3913 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3914 svm->apf_reason = kvm_read_and_reset_pf_reason();
3915
3916 if (npt_enabled) {
3917 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3918 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3919 }
3920
3921 /*
3922 * We need to handle MC intercepts here before the vcpu has a chance to
3923 * change the physical cpu
3924 */
3925 if (unlikely(svm->vmcb->control.exit_code ==
3926 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3927 svm_handle_mce(svm);
3928
3929 mark_all_clean(svm->vmcb);
3930 }
3931
3932 #undef R
3933
3934 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3935 {
3936 struct vcpu_svm *svm = to_svm(vcpu);
3937
3938 svm->vmcb->save.cr3 = root;
3939 mark_dirty(svm->vmcb, VMCB_CR);
3940 svm_flush_tlb(vcpu);
3941 }
3942
3943 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3944 {
3945 struct vcpu_svm *svm = to_svm(vcpu);
3946
3947 svm->vmcb->control.nested_cr3 = root;
3948 mark_dirty(svm->vmcb, VMCB_NPT);
3949
3950 /* Also sync guest cr3 here in case we live migrate */
3951 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3952 mark_dirty(svm->vmcb, VMCB_CR);
3953
3954 svm_flush_tlb(vcpu);
3955 }
3956
3957 static int is_disabled(void)
3958 {
3959 u64 vm_cr;
3960
3961 rdmsrl(MSR_VM_CR, vm_cr);
3962 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3963 return 1;
3964
3965 return 0;
3966 }
3967
3968 static void
3969 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3970 {
3971 /*
3972 * Patch in the VMMCALL instruction:
3973 */
3974 hypercall[0] = 0x0f;
3975 hypercall[1] = 0x01;
3976 hypercall[2] = 0xd9;
3977 }
3978
3979 static void svm_check_processor_compat(void *rtn)
3980 {
3981 *(int *)rtn = 0;
3982 }
3983
3984 static bool svm_cpu_has_accelerated_tpr(void)
3985 {
3986 return false;
3987 }
3988
3989 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3990 {
3991 return 0;
3992 }
3993
3994 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3995 {
3996 }
3997
3998 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3999 {
4000 switch (func) {
4001 case 0x80000001:
4002 if (nested)
4003 entry->ecx |= (1 << 2); /* Set SVM bit */
4004 break;
4005 case 0x8000000A:
4006 entry->eax = 1; /* SVM revision 1 */
4007 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4008 ASID emulation to nested SVM */
4009 entry->ecx = 0; /* Reserved */
4010 entry->edx = 0; /* Per default do not support any
4011 additional features */
4012
4013 /* Support next_rip if host supports it */
4014 if (boot_cpu_has(X86_FEATURE_NRIPS))
4015 entry->edx |= SVM_FEATURE_NRIP;
4016
4017 /* Support NPT for the guest if enabled */
4018 if (npt_enabled)
4019 entry->edx |= SVM_FEATURE_NPT;
4020
4021 break;
4022 }
4023 }
4024
4025 static int svm_get_lpage_level(void)
4026 {
4027 return PT_PDPE_LEVEL;
4028 }
4029
4030 static bool svm_rdtscp_supported(void)
4031 {
4032 return false;
4033 }
4034
4035 static bool svm_has_wbinvd_exit(void)
4036 {
4037 return true;
4038 }
4039
4040 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4041 {
4042 struct vcpu_svm *svm = to_svm(vcpu);
4043
4044 set_exception_intercept(svm, NM_VECTOR);
4045 update_cr0_intercept(svm);
4046 }
4047
4048 #define PRE_EX(exit) { .exit_code = (exit), \
4049 .stage = X86_ICPT_PRE_EXCEPT, }
4050 #define POST_EX(exit) { .exit_code = (exit), \
4051 .stage = X86_ICPT_POST_EXCEPT, }
4052 #define POST_MEM(exit) { .exit_code = (exit), \
4053 .stage = X86_ICPT_POST_MEMACCESS, }
4054
4055 static struct __x86_intercept {
4056 u32 exit_code;
4057 enum x86_intercept_stage stage;
4058 } x86_intercept_map[] = {
4059 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4060 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4061 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4062 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4063 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4064 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4065 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4066 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4067 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4068 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4069 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4070 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4071 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4072 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4073 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4074 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4075 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4076 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4077 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4078 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4079 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4080 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4081 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4082 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4083 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4084 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4085 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4086 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4087 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4088 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4089 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4090 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4091 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4092 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4093 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4094 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4095 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4096 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4097 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4098 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4099 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4100 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4101 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4102 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4103 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4104 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4105 };
4106
4107 #undef PRE_EX
4108 #undef POST_EX
4109 #undef POST_MEM
4110
4111 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4112 struct x86_instruction_info *info,
4113 enum x86_intercept_stage stage)
4114 {
4115 struct vcpu_svm *svm = to_svm(vcpu);
4116 int vmexit, ret = X86EMUL_CONTINUE;
4117 struct __x86_intercept icpt_info;
4118 struct vmcb *vmcb = svm->vmcb;
4119
4120 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4121 goto out;
4122
4123 icpt_info = x86_intercept_map[info->intercept];
4124
4125 if (stage != icpt_info.stage)
4126 goto out;
4127
4128 switch (icpt_info.exit_code) {
4129 case SVM_EXIT_READ_CR0:
4130 if (info->intercept == x86_intercept_cr_read)
4131 icpt_info.exit_code += info->modrm_reg;
4132 break;
4133 case SVM_EXIT_WRITE_CR0: {
4134 unsigned long cr0, val;
4135 u64 intercept;
4136
4137 if (info->intercept == x86_intercept_cr_write)
4138 icpt_info.exit_code += info->modrm_reg;
4139
4140 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4141 break;
4142
4143 intercept = svm->nested.intercept;
4144
4145 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4146 break;
4147
4148 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4149 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4150
4151 if (info->intercept == x86_intercept_lmsw) {
4152 cr0 &= 0xfUL;
4153 val &= 0xfUL;
4154 /* lmsw can't clear PE - catch this here */
4155 if (cr0 & X86_CR0_PE)
4156 val |= X86_CR0_PE;
4157 }
4158
4159 if (cr0 ^ val)
4160 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4161
4162 break;
4163 }
4164 case SVM_EXIT_READ_DR0:
4165 case SVM_EXIT_WRITE_DR0:
4166 icpt_info.exit_code += info->modrm_reg;
4167 break;
4168 case SVM_EXIT_MSR:
4169 if (info->intercept == x86_intercept_wrmsr)
4170 vmcb->control.exit_info_1 = 1;
4171 else
4172 vmcb->control.exit_info_1 = 0;
4173 break;
4174 case SVM_EXIT_PAUSE:
4175 /*
4176 * We get this for NOP only, but pause
4177 * is rep not, check this here
4178 */
4179 if (info->rep_prefix != REPE_PREFIX)
4180 goto out;
4181 case SVM_EXIT_IOIO: {
4182 u64 exit_info;
4183 u32 bytes;
4184
4185 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4186
4187 if (info->intercept == x86_intercept_in ||
4188 info->intercept == x86_intercept_ins) {
4189 exit_info |= SVM_IOIO_TYPE_MASK;
4190 bytes = info->src_bytes;
4191 } else {
4192 bytes = info->dst_bytes;
4193 }
4194
4195 if (info->intercept == x86_intercept_outs ||
4196 info->intercept == x86_intercept_ins)
4197 exit_info |= SVM_IOIO_STR_MASK;
4198
4199 if (info->rep_prefix)
4200 exit_info |= SVM_IOIO_REP_MASK;
4201
4202 bytes = min(bytes, 4u);
4203
4204 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4205
4206 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4207
4208 vmcb->control.exit_info_1 = exit_info;
4209 vmcb->control.exit_info_2 = info->next_rip;
4210
4211 break;
4212 }
4213 default:
4214 break;
4215 }
4216
4217 vmcb->control.next_rip = info->next_rip;
4218 vmcb->control.exit_code = icpt_info.exit_code;
4219 vmexit = nested_svm_exit_handled(svm);
4220
4221 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4222 : X86EMUL_CONTINUE;
4223
4224 out:
4225 return ret;
4226 }
4227
4228 static struct kvm_x86_ops svm_x86_ops = {
4229 .cpu_has_kvm_support = has_svm,
4230 .disabled_by_bios = is_disabled,
4231 .hardware_setup = svm_hardware_setup,
4232 .hardware_unsetup = svm_hardware_unsetup,
4233 .check_processor_compatibility = svm_check_processor_compat,
4234 .hardware_enable = svm_hardware_enable,
4235 .hardware_disable = svm_hardware_disable,
4236 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4237
4238 .vcpu_create = svm_create_vcpu,
4239 .vcpu_free = svm_free_vcpu,
4240 .vcpu_reset = svm_vcpu_reset,
4241
4242 .prepare_guest_switch = svm_prepare_guest_switch,
4243 .vcpu_load = svm_vcpu_load,
4244 .vcpu_put = svm_vcpu_put,
4245
4246 .set_guest_debug = svm_guest_debug,
4247 .get_msr = svm_get_msr,
4248 .set_msr = svm_set_msr,
4249 .get_segment_base = svm_get_segment_base,
4250 .get_segment = svm_get_segment,
4251 .set_segment = svm_set_segment,
4252 .get_cpl = svm_get_cpl,
4253 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4254 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4255 .decache_cr3 = svm_decache_cr3,
4256 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4257 .set_cr0 = svm_set_cr0,
4258 .set_cr3 = svm_set_cr3,
4259 .set_cr4 = svm_set_cr4,
4260 .set_efer = svm_set_efer,
4261 .get_idt = svm_get_idt,
4262 .set_idt = svm_set_idt,
4263 .get_gdt = svm_get_gdt,
4264 .set_gdt = svm_set_gdt,
4265 .set_dr7 = svm_set_dr7,
4266 .cache_reg = svm_cache_reg,
4267 .get_rflags = svm_get_rflags,
4268 .set_rflags = svm_set_rflags,
4269 .fpu_activate = svm_fpu_activate,
4270 .fpu_deactivate = svm_fpu_deactivate,
4271
4272 .tlb_flush = svm_flush_tlb,
4273
4274 .run = svm_vcpu_run,
4275 .handle_exit = handle_exit,
4276 .skip_emulated_instruction = skip_emulated_instruction,
4277 .set_interrupt_shadow = svm_set_interrupt_shadow,
4278 .get_interrupt_shadow = svm_get_interrupt_shadow,
4279 .patch_hypercall = svm_patch_hypercall,
4280 .set_irq = svm_set_irq,
4281 .set_nmi = svm_inject_nmi,
4282 .queue_exception = svm_queue_exception,
4283 .cancel_injection = svm_cancel_injection,
4284 .interrupt_allowed = svm_interrupt_allowed,
4285 .nmi_allowed = svm_nmi_allowed,
4286 .get_nmi_mask = svm_get_nmi_mask,
4287 .set_nmi_mask = svm_set_nmi_mask,
4288 .enable_nmi_window = enable_nmi_window,
4289 .enable_irq_window = enable_irq_window,
4290 .update_cr8_intercept = update_cr8_intercept,
4291
4292 .set_tss_addr = svm_set_tss_addr,
4293 .get_tdp_level = get_npt_level,
4294 .get_mt_mask = svm_get_mt_mask,
4295
4296 .get_exit_info = svm_get_exit_info,
4297
4298 .get_lpage_level = svm_get_lpage_level,
4299
4300 .cpuid_update = svm_cpuid_update,
4301
4302 .rdtscp_supported = svm_rdtscp_supported,
4303
4304 .set_supported_cpuid = svm_set_supported_cpuid,
4305
4306 .has_wbinvd_exit = svm_has_wbinvd_exit,
4307
4308 .set_tsc_khz = svm_set_tsc_khz,
4309 .write_tsc_offset = svm_write_tsc_offset,
4310 .adjust_tsc_offset = svm_adjust_tsc_offset,
4311 .compute_tsc_offset = svm_compute_tsc_offset,
4312 .read_l1_tsc = svm_read_l1_tsc,
4313
4314 .set_tdp_cr3 = set_tdp_cr3,
4315
4316 .check_intercept = svm_check_intercept,
4317 };
4318
4319 static int __init svm_init(void)
4320 {
4321 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4322 __alignof__(struct vcpu_svm), THIS_MODULE);
4323 }
4324
4325 static void __exit svm_exit(void)
4326 {
4327 kvm_exit();
4328 }
4329
4330 module_init(svm_init)
4331 module_exit(svm_exit)
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