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KVM: SVM: Add tracepoint for skinit instruction
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49
50 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
54 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
56 /* Turn on to get debugging output*/
57 /* #define NESTED_DEBUG */
58
59 #ifdef NESTED_DEBUG
60 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61 #else
62 #define nsvm_printk(fmt, args...) do {} while(0)
63 #endif
64
65 static const u32 host_save_user_msrs[] = {
66 #ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69 #endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71 };
72
73 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75 struct kvm_vcpu;
76
77 struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
87
88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
99 };
100
101 struct vcpu_svm {
102 struct kvm_vcpu vcpu;
103 struct vmcb *vmcb;
104 unsigned long vmcb_pa;
105 struct svm_cpu_data *svm_data;
106 uint64_t asid_generation;
107 uint64_t sysenter_esp;
108 uint64_t sysenter_eip;
109
110 u64 next_rip;
111
112 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
113 u64 host_gs_base;
114
115 u32 *msrpm;
116
117 struct nested_state nested;
118 };
119
120 /* enable NPT for AMD64 and X86 with PAE */
121 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
122 static bool npt_enabled = true;
123 #else
124 static bool npt_enabled = false;
125 #endif
126 static int npt = 1;
127
128 module_param(npt, int, S_IRUGO);
129
130 static int nested = 1;
131 module_param(nested, int, S_IRUGO);
132
133 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
134 static void svm_complete_interrupts(struct vcpu_svm *svm);
135
136 static int nested_svm_exit_handled(struct vcpu_svm *svm);
137 static int nested_svm_vmexit(struct vcpu_svm *svm);
138 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
139 bool has_error_code, u32 error_code);
140
141 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
142 {
143 return container_of(vcpu, struct vcpu_svm, vcpu);
144 }
145
146 static inline bool is_nested(struct vcpu_svm *svm)
147 {
148 return svm->nested.vmcb;
149 }
150
151 static inline void enable_gif(struct vcpu_svm *svm)
152 {
153 svm->vcpu.arch.hflags |= HF_GIF_MASK;
154 }
155
156 static inline void disable_gif(struct vcpu_svm *svm)
157 {
158 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
159 }
160
161 static inline bool gif_set(struct vcpu_svm *svm)
162 {
163 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
164 }
165
166 static unsigned long iopm_base;
167
168 struct kvm_ldttss_desc {
169 u16 limit0;
170 u16 base0;
171 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
172 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
173 u32 base3;
174 u32 zero1;
175 } __attribute__((packed));
176
177 struct svm_cpu_data {
178 int cpu;
179
180 u64 asid_generation;
181 u32 max_asid;
182 u32 next_asid;
183 struct kvm_ldttss_desc *tss_desc;
184
185 struct page *save_area;
186 };
187
188 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
189 static uint32_t svm_features;
190
191 struct svm_init_data {
192 int cpu;
193 int r;
194 };
195
196 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
197
198 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
199 #define MSRS_RANGE_SIZE 2048
200 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
201
202 #define MAX_INST_SIZE 15
203
204 static inline u32 svm_has(u32 feat)
205 {
206 return svm_features & feat;
207 }
208
209 static inline void clgi(void)
210 {
211 asm volatile (__ex(SVM_CLGI));
212 }
213
214 static inline void stgi(void)
215 {
216 asm volatile (__ex(SVM_STGI));
217 }
218
219 static inline void invlpga(unsigned long addr, u32 asid)
220 {
221 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
222 }
223
224 static inline void force_new_asid(struct kvm_vcpu *vcpu)
225 {
226 to_svm(vcpu)->asid_generation--;
227 }
228
229 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
230 {
231 force_new_asid(vcpu);
232 }
233
234 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
235 {
236 if (!npt_enabled && !(efer & EFER_LMA))
237 efer &= ~EFER_LME;
238
239 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
240 vcpu->arch.shadow_efer = efer;
241 }
242
243 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
244 bool has_error_code, u32 error_code)
245 {
246 struct vcpu_svm *svm = to_svm(vcpu);
247
248 /* If we are within a nested VM we'd better #VMEXIT and let the
249 guest handle the exception */
250 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
251 return;
252
253 svm->vmcb->control.event_inj = nr
254 | SVM_EVTINJ_VALID
255 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
256 | SVM_EVTINJ_TYPE_EXEPT;
257 svm->vmcb->control.event_inj_err = error_code;
258 }
259
260 static int is_external_interrupt(u32 info)
261 {
262 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
263 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
264 }
265
266 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
267 {
268 struct vcpu_svm *svm = to_svm(vcpu);
269 u32 ret = 0;
270
271 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
272 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
273 return ret & mask;
274 }
275
276 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
277 {
278 struct vcpu_svm *svm = to_svm(vcpu);
279
280 if (mask == 0)
281 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
282 else
283 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
284
285 }
286
287 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
288 {
289 struct vcpu_svm *svm = to_svm(vcpu);
290
291 if (!svm->next_rip) {
292 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
293 EMULATE_DONE)
294 printk(KERN_DEBUG "%s: NOP\n", __func__);
295 return;
296 }
297 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
298 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
299 __func__, kvm_rip_read(vcpu), svm->next_rip);
300
301 kvm_rip_write(vcpu, svm->next_rip);
302 svm_set_interrupt_shadow(vcpu, 0);
303 }
304
305 static int has_svm(void)
306 {
307 const char *msg;
308
309 if (!cpu_has_svm(&msg)) {
310 printk(KERN_INFO "has_svm: %s\n", msg);
311 return 0;
312 }
313
314 return 1;
315 }
316
317 static void svm_hardware_disable(void *garbage)
318 {
319 cpu_svm_disable();
320 }
321
322 static int svm_hardware_enable(void *garbage)
323 {
324
325 struct svm_cpu_data *svm_data;
326 uint64_t efer;
327 struct descriptor_table gdt_descr;
328 struct desc_struct *gdt;
329 int me = raw_smp_processor_id();
330
331 rdmsrl(MSR_EFER, efer);
332 if (efer & EFER_SVME)
333 return -EBUSY;
334
335 if (!has_svm()) {
336 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
337 me);
338 return -EINVAL;
339 }
340 svm_data = per_cpu(svm_data, me);
341
342 if (!svm_data) {
343 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
344 me);
345 return -EINVAL;
346 }
347
348 svm_data->asid_generation = 1;
349 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
350 svm_data->next_asid = svm_data->max_asid + 1;
351
352 kvm_get_gdt(&gdt_descr);
353 gdt = (struct desc_struct *)gdt_descr.base;
354 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
355
356 wrmsrl(MSR_EFER, efer | EFER_SVME);
357
358 wrmsrl(MSR_VM_HSAVE_PA,
359 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
360
361 return 0;
362 }
363
364 static void svm_cpu_uninit(int cpu)
365 {
366 struct svm_cpu_data *svm_data
367 = per_cpu(svm_data, raw_smp_processor_id());
368
369 if (!svm_data)
370 return;
371
372 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
373 __free_page(svm_data->save_area);
374 kfree(svm_data);
375 }
376
377 static int svm_cpu_init(int cpu)
378 {
379 struct svm_cpu_data *svm_data;
380 int r;
381
382 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
383 if (!svm_data)
384 return -ENOMEM;
385 svm_data->cpu = cpu;
386 svm_data->save_area = alloc_page(GFP_KERNEL);
387 r = -ENOMEM;
388 if (!svm_data->save_area)
389 goto err_1;
390
391 per_cpu(svm_data, cpu) = svm_data;
392
393 return 0;
394
395 err_1:
396 kfree(svm_data);
397 return r;
398
399 }
400
401 static void set_msr_interception(u32 *msrpm, unsigned msr,
402 int read, int write)
403 {
404 int i;
405
406 for (i = 0; i < NUM_MSR_MAPS; i++) {
407 if (msr >= msrpm_ranges[i] &&
408 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
409 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
410 msrpm_ranges[i]) * 2;
411
412 u32 *base = msrpm + (msr_offset / 32);
413 u32 msr_shift = msr_offset % 32;
414 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
415 *base = (*base & ~(0x3 << msr_shift)) |
416 (mask << msr_shift);
417 return;
418 }
419 }
420 BUG();
421 }
422
423 static void svm_vcpu_init_msrpm(u32 *msrpm)
424 {
425 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
426
427 #ifdef CONFIG_X86_64
428 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
429 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
430 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
431 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
432 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
433 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
434 #endif
435 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
437 }
438
439 static void svm_enable_lbrv(struct vcpu_svm *svm)
440 {
441 u32 *msrpm = svm->msrpm;
442
443 svm->vmcb->control.lbr_ctl = 1;
444 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
445 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
446 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
447 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
448 }
449
450 static void svm_disable_lbrv(struct vcpu_svm *svm)
451 {
452 u32 *msrpm = svm->msrpm;
453
454 svm->vmcb->control.lbr_ctl = 0;
455 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
456 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
457 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
458 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
459 }
460
461 static __init int svm_hardware_setup(void)
462 {
463 int cpu;
464 struct page *iopm_pages;
465 void *iopm_va;
466 int r;
467
468 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
469
470 if (!iopm_pages)
471 return -ENOMEM;
472
473 iopm_va = page_address(iopm_pages);
474 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
475 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
476
477 if (boot_cpu_has(X86_FEATURE_NX))
478 kvm_enable_efer_bits(EFER_NX);
479
480 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
481 kvm_enable_efer_bits(EFER_FFXSR);
482
483 if (nested) {
484 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
485 kvm_enable_efer_bits(EFER_SVME);
486 }
487
488 for_each_possible_cpu(cpu) {
489 r = svm_cpu_init(cpu);
490 if (r)
491 goto err;
492 }
493
494 svm_features = cpuid_edx(SVM_CPUID_FUNC);
495
496 if (!svm_has(SVM_FEATURE_NPT))
497 npt_enabled = false;
498
499 if (npt_enabled && !npt) {
500 printk(KERN_INFO "kvm: Nested Paging disabled\n");
501 npt_enabled = false;
502 }
503
504 if (npt_enabled) {
505 printk(KERN_INFO "kvm: Nested Paging enabled\n");
506 kvm_enable_tdp();
507 } else
508 kvm_disable_tdp();
509
510 return 0;
511
512 err:
513 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
514 iopm_base = 0;
515 return r;
516 }
517
518 static __exit void svm_hardware_unsetup(void)
519 {
520 int cpu;
521
522 for_each_possible_cpu(cpu)
523 svm_cpu_uninit(cpu);
524
525 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
526 iopm_base = 0;
527 }
528
529 static void init_seg(struct vmcb_seg *seg)
530 {
531 seg->selector = 0;
532 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
533 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
534 seg->limit = 0xffff;
535 seg->base = 0;
536 }
537
538 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
539 {
540 seg->selector = 0;
541 seg->attrib = SVM_SELECTOR_P_MASK | type;
542 seg->limit = 0xffff;
543 seg->base = 0;
544 }
545
546 static void init_vmcb(struct vcpu_svm *svm)
547 {
548 struct vmcb_control_area *control = &svm->vmcb->control;
549 struct vmcb_save_area *save = &svm->vmcb->save;
550
551 control->intercept_cr_read = INTERCEPT_CR0_MASK |
552 INTERCEPT_CR3_MASK |
553 INTERCEPT_CR4_MASK;
554
555 control->intercept_cr_write = INTERCEPT_CR0_MASK |
556 INTERCEPT_CR3_MASK |
557 INTERCEPT_CR4_MASK |
558 INTERCEPT_CR8_MASK;
559
560 control->intercept_dr_read = INTERCEPT_DR0_MASK |
561 INTERCEPT_DR1_MASK |
562 INTERCEPT_DR2_MASK |
563 INTERCEPT_DR3_MASK;
564
565 control->intercept_dr_write = INTERCEPT_DR0_MASK |
566 INTERCEPT_DR1_MASK |
567 INTERCEPT_DR2_MASK |
568 INTERCEPT_DR3_MASK |
569 INTERCEPT_DR5_MASK |
570 INTERCEPT_DR7_MASK;
571
572 control->intercept_exceptions = (1 << PF_VECTOR) |
573 (1 << UD_VECTOR) |
574 (1 << MC_VECTOR);
575
576
577 control->intercept = (1ULL << INTERCEPT_INTR) |
578 (1ULL << INTERCEPT_NMI) |
579 (1ULL << INTERCEPT_SMI) |
580 (1ULL << INTERCEPT_CPUID) |
581 (1ULL << INTERCEPT_INVD) |
582 (1ULL << INTERCEPT_HLT) |
583 (1ULL << INTERCEPT_INVLPG) |
584 (1ULL << INTERCEPT_INVLPGA) |
585 (1ULL << INTERCEPT_IOIO_PROT) |
586 (1ULL << INTERCEPT_MSR_PROT) |
587 (1ULL << INTERCEPT_TASK_SWITCH) |
588 (1ULL << INTERCEPT_SHUTDOWN) |
589 (1ULL << INTERCEPT_VMRUN) |
590 (1ULL << INTERCEPT_VMMCALL) |
591 (1ULL << INTERCEPT_VMLOAD) |
592 (1ULL << INTERCEPT_VMSAVE) |
593 (1ULL << INTERCEPT_STGI) |
594 (1ULL << INTERCEPT_CLGI) |
595 (1ULL << INTERCEPT_SKINIT) |
596 (1ULL << INTERCEPT_WBINVD) |
597 (1ULL << INTERCEPT_MONITOR) |
598 (1ULL << INTERCEPT_MWAIT);
599
600 control->iopm_base_pa = iopm_base;
601 control->msrpm_base_pa = __pa(svm->msrpm);
602 control->tsc_offset = 0;
603 control->int_ctl = V_INTR_MASKING_MASK;
604
605 init_seg(&save->es);
606 init_seg(&save->ss);
607 init_seg(&save->ds);
608 init_seg(&save->fs);
609 init_seg(&save->gs);
610
611 save->cs.selector = 0xf000;
612 /* Executable/Readable Code Segment */
613 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
614 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
615 save->cs.limit = 0xffff;
616 /*
617 * cs.base should really be 0xffff0000, but vmx can't handle that, so
618 * be consistent with it.
619 *
620 * Replace when we have real mode working for vmx.
621 */
622 save->cs.base = 0xf0000;
623
624 save->gdtr.limit = 0xffff;
625 save->idtr.limit = 0xffff;
626
627 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
628 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
629
630 save->efer = EFER_SVME;
631 save->dr6 = 0xffff0ff0;
632 save->dr7 = 0x400;
633 save->rflags = 2;
634 save->rip = 0x0000fff0;
635 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
636
637 /*
638 * cr0 val on cpu init should be 0x60000010, we enable cpu
639 * cache by default. the orderly way is to enable cache in bios.
640 */
641 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
642 save->cr4 = X86_CR4_PAE;
643 /* rdx = ?? */
644
645 if (npt_enabled) {
646 /* Setup VMCB for Nested Paging */
647 control->nested_ctl = 1;
648 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
649 (1ULL << INTERCEPT_INVLPG));
650 control->intercept_exceptions &= ~(1 << PF_VECTOR);
651 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
652 INTERCEPT_CR3_MASK);
653 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
654 INTERCEPT_CR3_MASK);
655 save->g_pat = 0x0007040600070406ULL;
656 /* enable caching because the QEMU Bios doesn't enable it */
657 save->cr0 = X86_CR0_ET;
658 save->cr3 = 0;
659 save->cr4 = 0;
660 }
661 force_new_asid(&svm->vcpu);
662
663 svm->nested.vmcb = 0;
664 svm->vcpu.arch.hflags = 0;
665
666 enable_gif(svm);
667 }
668
669 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
670 {
671 struct vcpu_svm *svm = to_svm(vcpu);
672
673 init_vmcb(svm);
674
675 if (!kvm_vcpu_is_bsp(vcpu)) {
676 kvm_rip_write(vcpu, 0);
677 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
678 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
679 }
680 vcpu->arch.regs_avail = ~0;
681 vcpu->arch.regs_dirty = ~0;
682
683 return 0;
684 }
685
686 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
687 {
688 struct vcpu_svm *svm;
689 struct page *page;
690 struct page *msrpm_pages;
691 struct page *hsave_page;
692 struct page *nested_msrpm_pages;
693 int err;
694
695 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
696 if (!svm) {
697 err = -ENOMEM;
698 goto out;
699 }
700
701 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
702 if (err)
703 goto free_svm;
704
705 page = alloc_page(GFP_KERNEL);
706 if (!page) {
707 err = -ENOMEM;
708 goto uninit;
709 }
710
711 err = -ENOMEM;
712 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!msrpm_pages)
714 goto uninit;
715
716 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
717 if (!nested_msrpm_pages)
718 goto uninit;
719
720 svm->msrpm = page_address(msrpm_pages);
721 svm_vcpu_init_msrpm(svm->msrpm);
722
723 hsave_page = alloc_page(GFP_KERNEL);
724 if (!hsave_page)
725 goto uninit;
726 svm->nested.hsave = page_address(hsave_page);
727
728 svm->nested.msrpm = page_address(nested_msrpm_pages);
729
730 svm->vmcb = page_address(page);
731 clear_page(svm->vmcb);
732 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
733 svm->asid_generation = 0;
734 init_vmcb(svm);
735
736 fx_init(&svm->vcpu);
737 svm->vcpu.fpu_active = 1;
738 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
739 if (kvm_vcpu_is_bsp(&svm->vcpu))
740 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
741
742 return &svm->vcpu;
743
744 uninit:
745 kvm_vcpu_uninit(&svm->vcpu);
746 free_svm:
747 kmem_cache_free(kvm_vcpu_cache, svm);
748 out:
749 return ERR_PTR(err);
750 }
751
752 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
753 {
754 struct vcpu_svm *svm = to_svm(vcpu);
755
756 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
757 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
758 __free_page(virt_to_page(svm->nested.hsave));
759 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
760 kvm_vcpu_uninit(vcpu);
761 kmem_cache_free(kvm_vcpu_cache, svm);
762 }
763
764 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
765 {
766 struct vcpu_svm *svm = to_svm(vcpu);
767 int i;
768
769 if (unlikely(cpu != vcpu->cpu)) {
770 u64 delta;
771
772 /*
773 * Make sure that the guest sees a monotonically
774 * increasing TSC.
775 */
776 delta = vcpu->arch.host_tsc - native_read_tsc();
777 svm->vmcb->control.tsc_offset += delta;
778 if (is_nested(svm))
779 svm->nested.hsave->control.tsc_offset += delta;
780 vcpu->cpu = cpu;
781 kvm_migrate_timers(vcpu);
782 svm->asid_generation = 0;
783 }
784
785 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
786 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
787 }
788
789 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
790 {
791 struct vcpu_svm *svm = to_svm(vcpu);
792 int i;
793
794 ++vcpu->stat.host_state_reload;
795 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
796 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
797
798 vcpu->arch.host_tsc = native_read_tsc();
799 }
800
801 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
802 {
803 return to_svm(vcpu)->vmcb->save.rflags;
804 }
805
806 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
807 {
808 to_svm(vcpu)->vmcb->save.rflags = rflags;
809 }
810
811 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
812 {
813 switch (reg) {
814 case VCPU_EXREG_PDPTR:
815 BUG_ON(!npt_enabled);
816 load_pdptrs(vcpu, vcpu->arch.cr3);
817 break;
818 default:
819 BUG();
820 }
821 }
822
823 static void svm_set_vintr(struct vcpu_svm *svm)
824 {
825 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
826 }
827
828 static void svm_clear_vintr(struct vcpu_svm *svm)
829 {
830 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
831 }
832
833 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
834 {
835 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
836
837 switch (seg) {
838 case VCPU_SREG_CS: return &save->cs;
839 case VCPU_SREG_DS: return &save->ds;
840 case VCPU_SREG_ES: return &save->es;
841 case VCPU_SREG_FS: return &save->fs;
842 case VCPU_SREG_GS: return &save->gs;
843 case VCPU_SREG_SS: return &save->ss;
844 case VCPU_SREG_TR: return &save->tr;
845 case VCPU_SREG_LDTR: return &save->ldtr;
846 }
847 BUG();
848 return NULL;
849 }
850
851 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
852 {
853 struct vmcb_seg *s = svm_seg(vcpu, seg);
854
855 return s->base;
856 }
857
858 static void svm_get_segment(struct kvm_vcpu *vcpu,
859 struct kvm_segment *var, int seg)
860 {
861 struct vmcb_seg *s = svm_seg(vcpu, seg);
862
863 var->base = s->base;
864 var->limit = s->limit;
865 var->selector = s->selector;
866 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
867 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
868 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
869 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
870 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
871 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
872 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
873 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
874
875 /* AMD's VMCB does not have an explicit unusable field, so emulate it
876 * for cross vendor migration purposes by "not present"
877 */
878 var->unusable = !var->present || (var->type == 0);
879
880 switch (seg) {
881 case VCPU_SREG_CS:
882 /*
883 * SVM always stores 0 for the 'G' bit in the CS selector in
884 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
885 * Intel's VMENTRY has a check on the 'G' bit.
886 */
887 var->g = s->limit > 0xfffff;
888 break;
889 case VCPU_SREG_TR:
890 /*
891 * Work around a bug where the busy flag in the tr selector
892 * isn't exposed
893 */
894 var->type |= 0x2;
895 break;
896 case VCPU_SREG_DS:
897 case VCPU_SREG_ES:
898 case VCPU_SREG_FS:
899 case VCPU_SREG_GS:
900 /*
901 * The accessed bit must always be set in the segment
902 * descriptor cache, although it can be cleared in the
903 * descriptor, the cached bit always remains at 1. Since
904 * Intel has a check on this, set it here to support
905 * cross-vendor migration.
906 */
907 if (!var->unusable)
908 var->type |= 0x1;
909 break;
910 case VCPU_SREG_SS:
911 /* On AMD CPUs sometimes the DB bit in the segment
912 * descriptor is left as 1, although the whole segment has
913 * been made unusable. Clear it here to pass an Intel VMX
914 * entry check when cross vendor migrating.
915 */
916 if (var->unusable)
917 var->db = 0;
918 break;
919 }
920 }
921
922 static int svm_get_cpl(struct kvm_vcpu *vcpu)
923 {
924 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
925
926 return save->cpl;
927 }
928
929 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
930 {
931 struct vcpu_svm *svm = to_svm(vcpu);
932
933 dt->limit = svm->vmcb->save.idtr.limit;
934 dt->base = svm->vmcb->save.idtr.base;
935 }
936
937 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
938 {
939 struct vcpu_svm *svm = to_svm(vcpu);
940
941 svm->vmcb->save.idtr.limit = dt->limit;
942 svm->vmcb->save.idtr.base = dt->base ;
943 }
944
945 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
946 {
947 struct vcpu_svm *svm = to_svm(vcpu);
948
949 dt->limit = svm->vmcb->save.gdtr.limit;
950 dt->base = svm->vmcb->save.gdtr.base;
951 }
952
953 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
954 {
955 struct vcpu_svm *svm = to_svm(vcpu);
956
957 svm->vmcb->save.gdtr.limit = dt->limit;
958 svm->vmcb->save.gdtr.base = dt->base ;
959 }
960
961 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
962 {
963 }
964
965 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
966 {
967 struct vcpu_svm *svm = to_svm(vcpu);
968
969 #ifdef CONFIG_X86_64
970 if (vcpu->arch.shadow_efer & EFER_LME) {
971 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
972 vcpu->arch.shadow_efer |= EFER_LMA;
973 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
974 }
975
976 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
977 vcpu->arch.shadow_efer &= ~EFER_LMA;
978 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
979 }
980 }
981 #endif
982 if (npt_enabled)
983 goto set;
984
985 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
986 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
987 vcpu->fpu_active = 1;
988 }
989
990 vcpu->arch.cr0 = cr0;
991 cr0 |= X86_CR0_PG | X86_CR0_WP;
992 if (!vcpu->fpu_active) {
993 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
994 cr0 |= X86_CR0_TS;
995 }
996 set:
997 /*
998 * re-enable caching here because the QEMU bios
999 * does not do it - this results in some delay at
1000 * reboot
1001 */
1002 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1003 svm->vmcb->save.cr0 = cr0;
1004 }
1005
1006 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1007 {
1008 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1009 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1010
1011 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1012 force_new_asid(vcpu);
1013
1014 vcpu->arch.cr4 = cr4;
1015 if (!npt_enabled)
1016 cr4 |= X86_CR4_PAE;
1017 cr4 |= host_cr4_mce;
1018 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1019 }
1020
1021 static void svm_set_segment(struct kvm_vcpu *vcpu,
1022 struct kvm_segment *var, int seg)
1023 {
1024 struct vcpu_svm *svm = to_svm(vcpu);
1025 struct vmcb_seg *s = svm_seg(vcpu, seg);
1026
1027 s->base = var->base;
1028 s->limit = var->limit;
1029 s->selector = var->selector;
1030 if (var->unusable)
1031 s->attrib = 0;
1032 else {
1033 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1034 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1035 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1036 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1037 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1038 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1039 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1040 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1041 }
1042 if (seg == VCPU_SREG_CS)
1043 svm->vmcb->save.cpl
1044 = (svm->vmcb->save.cs.attrib
1045 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1046
1047 }
1048
1049 static void update_db_intercept(struct kvm_vcpu *vcpu)
1050 {
1051 struct vcpu_svm *svm = to_svm(vcpu);
1052
1053 svm->vmcb->control.intercept_exceptions &=
1054 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1055
1056 if (vcpu->arch.singlestep)
1057 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1058
1059 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1060 if (vcpu->guest_debug &
1061 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1062 svm->vmcb->control.intercept_exceptions |=
1063 1 << DB_VECTOR;
1064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1065 svm->vmcb->control.intercept_exceptions |=
1066 1 << BP_VECTOR;
1067 } else
1068 vcpu->guest_debug = 0;
1069 }
1070
1071 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1072 {
1073 struct vcpu_svm *svm = to_svm(vcpu);
1074
1075 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1076 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1077 else
1078 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1079
1080 update_db_intercept(vcpu);
1081 }
1082
1083 static void load_host_msrs(struct kvm_vcpu *vcpu)
1084 {
1085 #ifdef CONFIG_X86_64
1086 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1087 #endif
1088 }
1089
1090 static void save_host_msrs(struct kvm_vcpu *vcpu)
1091 {
1092 #ifdef CONFIG_X86_64
1093 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1094 #endif
1095 }
1096
1097 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1098 {
1099 if (svm_data->next_asid > svm_data->max_asid) {
1100 ++svm_data->asid_generation;
1101 svm_data->next_asid = 1;
1102 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1103 }
1104
1105 svm->asid_generation = svm_data->asid_generation;
1106 svm->vmcb->control.asid = svm_data->next_asid++;
1107 }
1108
1109 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1110 {
1111 struct vcpu_svm *svm = to_svm(vcpu);
1112 unsigned long val;
1113
1114 switch (dr) {
1115 case 0 ... 3:
1116 val = vcpu->arch.db[dr];
1117 break;
1118 case 6:
1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 val = vcpu->arch.dr6;
1121 else
1122 val = svm->vmcb->save.dr6;
1123 break;
1124 case 7:
1125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1126 val = vcpu->arch.dr7;
1127 else
1128 val = svm->vmcb->save.dr7;
1129 break;
1130 default:
1131 val = 0;
1132 }
1133
1134 return val;
1135 }
1136
1137 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1138 int *exception)
1139 {
1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
1142 *exception = 0;
1143
1144 switch (dr) {
1145 case 0 ... 3:
1146 vcpu->arch.db[dr] = value;
1147 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1148 vcpu->arch.eff_db[dr] = value;
1149 return;
1150 case 4 ... 5:
1151 if (vcpu->arch.cr4 & X86_CR4_DE)
1152 *exception = UD_VECTOR;
1153 return;
1154 case 6:
1155 if (value & 0xffffffff00000000ULL) {
1156 *exception = GP_VECTOR;
1157 return;
1158 }
1159 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1160 return;
1161 case 7:
1162 if (value & 0xffffffff00000000ULL) {
1163 *exception = GP_VECTOR;
1164 return;
1165 }
1166 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1167 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1168 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1169 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1170 }
1171 return;
1172 default:
1173 /* FIXME: Possible case? */
1174 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1175 __func__, dr);
1176 *exception = UD_VECTOR;
1177 return;
1178 }
1179 }
1180
1181 static int pf_interception(struct vcpu_svm *svm)
1182 {
1183 u64 fault_address;
1184 u32 error_code;
1185
1186 fault_address = svm->vmcb->control.exit_info_2;
1187 error_code = svm->vmcb->control.exit_info_1;
1188
1189 trace_kvm_page_fault(fault_address, error_code);
1190 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1191 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1192 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1193 }
1194
1195 static int db_interception(struct vcpu_svm *svm)
1196 {
1197 struct kvm_run *kvm_run = svm->vcpu.run;
1198
1199 if (!(svm->vcpu.guest_debug &
1200 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1201 !svm->vcpu.arch.singlestep) {
1202 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1203 return 1;
1204 }
1205
1206 if (svm->vcpu.arch.singlestep) {
1207 svm->vcpu.arch.singlestep = false;
1208 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1209 svm->vmcb->save.rflags &=
1210 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1211 update_db_intercept(&svm->vcpu);
1212 }
1213
1214 if (svm->vcpu.guest_debug &
1215 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1216 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1217 kvm_run->debug.arch.pc =
1218 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1219 kvm_run->debug.arch.exception = DB_VECTOR;
1220 return 0;
1221 }
1222
1223 return 1;
1224 }
1225
1226 static int bp_interception(struct vcpu_svm *svm)
1227 {
1228 struct kvm_run *kvm_run = svm->vcpu.run;
1229
1230 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1231 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1232 kvm_run->debug.arch.exception = BP_VECTOR;
1233 return 0;
1234 }
1235
1236 static int ud_interception(struct vcpu_svm *svm)
1237 {
1238 int er;
1239
1240 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1241 if (er != EMULATE_DONE)
1242 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1243 return 1;
1244 }
1245
1246 static int nm_interception(struct vcpu_svm *svm)
1247 {
1248 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1249 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1250 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1251 svm->vcpu.fpu_active = 1;
1252
1253 return 1;
1254 }
1255
1256 static int mc_interception(struct vcpu_svm *svm)
1257 {
1258 /*
1259 * On an #MC intercept the MCE handler is not called automatically in
1260 * the host. So do it by hand here.
1261 */
1262 asm volatile (
1263 "int $0x12\n");
1264 /* not sure if we ever come back to this point */
1265
1266 return 1;
1267 }
1268
1269 static int shutdown_interception(struct vcpu_svm *svm)
1270 {
1271 struct kvm_run *kvm_run = svm->vcpu.run;
1272
1273 /*
1274 * VMCB is undefined after a SHUTDOWN intercept
1275 * so reinitialize it.
1276 */
1277 clear_page(svm->vmcb);
1278 init_vmcb(svm);
1279
1280 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1281 return 0;
1282 }
1283
1284 static int io_interception(struct vcpu_svm *svm)
1285 {
1286 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1287 int size, in, string;
1288 unsigned port;
1289
1290 ++svm->vcpu.stat.io_exits;
1291
1292 svm->next_rip = svm->vmcb->control.exit_info_2;
1293
1294 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1295
1296 if (string) {
1297 if (emulate_instruction(&svm->vcpu,
1298 0, 0, 0) == EMULATE_DO_MMIO)
1299 return 0;
1300 return 1;
1301 }
1302
1303 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1304 port = io_info >> 16;
1305 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1306
1307 skip_emulated_instruction(&svm->vcpu);
1308 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1309 }
1310
1311 static int nmi_interception(struct vcpu_svm *svm)
1312 {
1313 return 1;
1314 }
1315
1316 static int intr_interception(struct vcpu_svm *svm)
1317 {
1318 ++svm->vcpu.stat.irq_exits;
1319 return 1;
1320 }
1321
1322 static int nop_on_interception(struct vcpu_svm *svm)
1323 {
1324 return 1;
1325 }
1326
1327 static int halt_interception(struct vcpu_svm *svm)
1328 {
1329 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1330 skip_emulated_instruction(&svm->vcpu);
1331 return kvm_emulate_halt(&svm->vcpu);
1332 }
1333
1334 static int vmmcall_interception(struct vcpu_svm *svm)
1335 {
1336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1337 skip_emulated_instruction(&svm->vcpu);
1338 kvm_emulate_hypercall(&svm->vcpu);
1339 return 1;
1340 }
1341
1342 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1343 {
1344 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1345 || !is_paging(&svm->vcpu)) {
1346 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1347 return 1;
1348 }
1349
1350 if (svm->vmcb->save.cpl) {
1351 kvm_inject_gp(&svm->vcpu, 0);
1352 return 1;
1353 }
1354
1355 return 0;
1356 }
1357
1358 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1359 bool has_error_code, u32 error_code)
1360 {
1361 if (!is_nested(svm))
1362 return 0;
1363
1364 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1365 svm->vmcb->control.exit_code_hi = 0;
1366 svm->vmcb->control.exit_info_1 = error_code;
1367 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1368
1369 return nested_svm_exit_handled(svm);
1370 }
1371
1372 static inline int nested_svm_intr(struct vcpu_svm *svm)
1373 {
1374 if (!is_nested(svm))
1375 return 0;
1376
1377 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1378 return 0;
1379
1380 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1381 return 0;
1382
1383 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1384
1385 if (svm->nested.intercept & 1ULL) {
1386 /*
1387 * The #vmexit can't be emulated here directly because this
1388 * code path runs with irqs and preemtion disabled. A
1389 * #vmexit emulation might sleep. Only signal request for
1390 * the #vmexit here.
1391 */
1392 svm->nested.exit_required = true;
1393 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1394 return 1;
1395 }
1396
1397 return 0;
1398 }
1399
1400 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1401 {
1402 struct page *page;
1403
1404 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1405 if (is_error_page(page))
1406 goto error;
1407
1408 return kmap_atomic(page, idx);
1409
1410 error:
1411 kvm_release_page_clean(page);
1412 kvm_inject_gp(&svm->vcpu, 0);
1413
1414 return NULL;
1415 }
1416
1417 static void nested_svm_unmap(void *addr, enum km_type idx)
1418 {
1419 struct page *page;
1420
1421 if (!addr)
1422 return;
1423
1424 page = kmap_atomic_to_page(addr);
1425
1426 kunmap_atomic(addr, idx);
1427 kvm_release_page_dirty(page);
1428 }
1429
1430 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1431 {
1432 u32 param = svm->vmcb->control.exit_info_1 & 1;
1433 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1434 bool ret = false;
1435 u32 t0, t1;
1436 u8 *msrpm;
1437
1438 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1439 return false;
1440
1441 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1442
1443 if (!msrpm)
1444 goto out;
1445
1446 switch (msr) {
1447 case 0 ... 0x1fff:
1448 t0 = (msr * 2) % 8;
1449 t1 = msr / 8;
1450 break;
1451 case 0xc0000000 ... 0xc0001fff:
1452 t0 = (8192 + msr - 0xc0000000) * 2;
1453 t1 = (t0 / 8);
1454 t0 %= 8;
1455 break;
1456 case 0xc0010000 ... 0xc0011fff:
1457 t0 = (16384 + msr - 0xc0010000) * 2;
1458 t1 = (t0 / 8);
1459 t0 %= 8;
1460 break;
1461 default:
1462 ret = true;
1463 goto out;
1464 }
1465
1466 ret = msrpm[t1] & ((1 << param) << t0);
1467
1468 out:
1469 nested_svm_unmap(msrpm, KM_USER0);
1470
1471 return ret;
1472 }
1473
1474 static int nested_svm_exit_special(struct vcpu_svm *svm)
1475 {
1476 u32 exit_code = svm->vmcb->control.exit_code;
1477
1478 switch (exit_code) {
1479 case SVM_EXIT_INTR:
1480 case SVM_EXIT_NMI:
1481 return NESTED_EXIT_HOST;
1482 /* For now we are always handling NPFs when using them */
1483 case SVM_EXIT_NPF:
1484 if (npt_enabled)
1485 return NESTED_EXIT_HOST;
1486 break;
1487 /* When we're shadowing, trap PFs */
1488 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1489 if (!npt_enabled)
1490 return NESTED_EXIT_HOST;
1491 break;
1492 default:
1493 break;
1494 }
1495
1496 return NESTED_EXIT_CONTINUE;
1497 }
1498
1499 /*
1500 * If this function returns true, this #vmexit was already handled
1501 */
1502 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1503 {
1504 u32 exit_code = svm->vmcb->control.exit_code;
1505 int vmexit = NESTED_EXIT_HOST;
1506
1507 switch (exit_code) {
1508 case SVM_EXIT_MSR:
1509 vmexit = nested_svm_exit_handled_msr(svm);
1510 break;
1511 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1512 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1513 if (svm->nested.intercept_cr_read & cr_bits)
1514 vmexit = NESTED_EXIT_DONE;
1515 break;
1516 }
1517 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1518 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1519 if (svm->nested.intercept_cr_write & cr_bits)
1520 vmexit = NESTED_EXIT_DONE;
1521 break;
1522 }
1523 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1524 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1525 if (svm->nested.intercept_dr_read & dr_bits)
1526 vmexit = NESTED_EXIT_DONE;
1527 break;
1528 }
1529 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1530 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1531 if (svm->nested.intercept_dr_write & dr_bits)
1532 vmexit = NESTED_EXIT_DONE;
1533 break;
1534 }
1535 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1536 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1537 if (svm->nested.intercept_exceptions & excp_bits)
1538 vmexit = NESTED_EXIT_DONE;
1539 break;
1540 }
1541 default: {
1542 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1543 nsvm_printk("exit code: 0x%x\n", exit_code);
1544 if (svm->nested.intercept & exit_bits)
1545 vmexit = NESTED_EXIT_DONE;
1546 }
1547 }
1548
1549 if (vmexit == NESTED_EXIT_DONE) {
1550 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1551 nested_svm_vmexit(svm);
1552 }
1553
1554 return vmexit;
1555 }
1556
1557 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1558 {
1559 struct vmcb_control_area *dst = &dst_vmcb->control;
1560 struct vmcb_control_area *from = &from_vmcb->control;
1561
1562 dst->intercept_cr_read = from->intercept_cr_read;
1563 dst->intercept_cr_write = from->intercept_cr_write;
1564 dst->intercept_dr_read = from->intercept_dr_read;
1565 dst->intercept_dr_write = from->intercept_dr_write;
1566 dst->intercept_exceptions = from->intercept_exceptions;
1567 dst->intercept = from->intercept;
1568 dst->iopm_base_pa = from->iopm_base_pa;
1569 dst->msrpm_base_pa = from->msrpm_base_pa;
1570 dst->tsc_offset = from->tsc_offset;
1571 dst->asid = from->asid;
1572 dst->tlb_ctl = from->tlb_ctl;
1573 dst->int_ctl = from->int_ctl;
1574 dst->int_vector = from->int_vector;
1575 dst->int_state = from->int_state;
1576 dst->exit_code = from->exit_code;
1577 dst->exit_code_hi = from->exit_code_hi;
1578 dst->exit_info_1 = from->exit_info_1;
1579 dst->exit_info_2 = from->exit_info_2;
1580 dst->exit_int_info = from->exit_int_info;
1581 dst->exit_int_info_err = from->exit_int_info_err;
1582 dst->nested_ctl = from->nested_ctl;
1583 dst->event_inj = from->event_inj;
1584 dst->event_inj_err = from->event_inj_err;
1585 dst->nested_cr3 = from->nested_cr3;
1586 dst->lbr_ctl = from->lbr_ctl;
1587 }
1588
1589 static int nested_svm_vmexit(struct vcpu_svm *svm)
1590 {
1591 struct vmcb *nested_vmcb;
1592 struct vmcb *hsave = svm->nested.hsave;
1593 struct vmcb *vmcb = svm->vmcb;
1594
1595 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1596 vmcb->control.exit_info_1,
1597 vmcb->control.exit_info_2,
1598 vmcb->control.exit_int_info,
1599 vmcb->control.exit_int_info_err);
1600
1601 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1602 if (!nested_vmcb)
1603 return 1;
1604
1605 /* Give the current vmcb to the guest */
1606 disable_gif(svm);
1607
1608 nested_vmcb->save.es = vmcb->save.es;
1609 nested_vmcb->save.cs = vmcb->save.cs;
1610 nested_vmcb->save.ss = vmcb->save.ss;
1611 nested_vmcb->save.ds = vmcb->save.ds;
1612 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1613 nested_vmcb->save.idtr = vmcb->save.idtr;
1614 if (npt_enabled)
1615 nested_vmcb->save.cr3 = vmcb->save.cr3;
1616 nested_vmcb->save.cr2 = vmcb->save.cr2;
1617 nested_vmcb->save.rflags = vmcb->save.rflags;
1618 nested_vmcb->save.rip = vmcb->save.rip;
1619 nested_vmcb->save.rsp = vmcb->save.rsp;
1620 nested_vmcb->save.rax = vmcb->save.rax;
1621 nested_vmcb->save.dr7 = vmcb->save.dr7;
1622 nested_vmcb->save.dr6 = vmcb->save.dr6;
1623 nested_vmcb->save.cpl = vmcb->save.cpl;
1624
1625 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1626 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1627 nested_vmcb->control.int_state = vmcb->control.int_state;
1628 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1629 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1630 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1631 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1632 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1633 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1634
1635 /*
1636 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1637 * to make sure that we do not lose injected events. So check event_inj
1638 * here and copy it to exit_int_info if it is valid.
1639 * Exit_int_info and event_inj can't be both valid because the case
1640 * below only happens on a VMRUN instruction intercept which has
1641 * no valid exit_int_info set.
1642 */
1643 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1644 struct vmcb_control_area *nc = &nested_vmcb->control;
1645
1646 nc->exit_int_info = vmcb->control.event_inj;
1647 nc->exit_int_info_err = vmcb->control.event_inj_err;
1648 }
1649
1650 nested_vmcb->control.tlb_ctl = 0;
1651 nested_vmcb->control.event_inj = 0;
1652 nested_vmcb->control.event_inj_err = 0;
1653
1654 /* We always set V_INTR_MASKING and remember the old value in hflags */
1655 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1656 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1657
1658 /* Restore the original control entries */
1659 copy_vmcb_control_area(vmcb, hsave);
1660
1661 /* Kill any pending exceptions */
1662 if (svm->vcpu.arch.exception.pending == true)
1663 nsvm_printk("WARNING: Pending Exception\n");
1664
1665 kvm_clear_exception_queue(&svm->vcpu);
1666 kvm_clear_interrupt_queue(&svm->vcpu);
1667
1668 /* Restore selected save entries */
1669 svm->vmcb->save.es = hsave->save.es;
1670 svm->vmcb->save.cs = hsave->save.cs;
1671 svm->vmcb->save.ss = hsave->save.ss;
1672 svm->vmcb->save.ds = hsave->save.ds;
1673 svm->vmcb->save.gdtr = hsave->save.gdtr;
1674 svm->vmcb->save.idtr = hsave->save.idtr;
1675 svm->vmcb->save.rflags = hsave->save.rflags;
1676 svm_set_efer(&svm->vcpu, hsave->save.efer);
1677 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1678 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1679 if (npt_enabled) {
1680 svm->vmcb->save.cr3 = hsave->save.cr3;
1681 svm->vcpu.arch.cr3 = hsave->save.cr3;
1682 } else {
1683 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1684 }
1685 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1686 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1687 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1688 svm->vmcb->save.dr7 = 0;
1689 svm->vmcb->save.cpl = 0;
1690 svm->vmcb->control.exit_int_info = 0;
1691
1692 /* Exit nested SVM mode */
1693 svm->nested.vmcb = 0;
1694
1695 nested_svm_unmap(nested_vmcb, KM_USER0);
1696
1697 kvm_mmu_reset_context(&svm->vcpu);
1698 kvm_mmu_load(&svm->vcpu);
1699
1700 return 0;
1701 }
1702
1703 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1704 {
1705 u32 *nested_msrpm;
1706 int i;
1707
1708 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1709 if (!nested_msrpm)
1710 return false;
1711
1712 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1713 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1714
1715 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1716
1717 nested_svm_unmap(nested_msrpm, KM_USER0);
1718
1719 return true;
1720 }
1721
1722 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1723 {
1724 struct vmcb *nested_vmcb;
1725 struct vmcb *hsave = svm->nested.hsave;
1726 struct vmcb *vmcb = svm->vmcb;
1727
1728 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1729 if (!nested_vmcb)
1730 return false;
1731
1732 /* nested_vmcb is our indicator if nested SVM is activated */
1733 svm->nested.vmcb = svm->vmcb->save.rax;
1734
1735 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1736 nested_vmcb->save.rip,
1737 nested_vmcb->control.int_ctl,
1738 nested_vmcb->control.event_inj,
1739 nested_vmcb->control.nested_ctl);
1740
1741 /* Clear internal status */
1742 kvm_clear_exception_queue(&svm->vcpu);
1743 kvm_clear_interrupt_queue(&svm->vcpu);
1744
1745 /* Save the old vmcb, so we don't need to pick what we save, but
1746 can restore everything when a VMEXIT occurs */
1747 hsave->save.es = vmcb->save.es;
1748 hsave->save.cs = vmcb->save.cs;
1749 hsave->save.ss = vmcb->save.ss;
1750 hsave->save.ds = vmcb->save.ds;
1751 hsave->save.gdtr = vmcb->save.gdtr;
1752 hsave->save.idtr = vmcb->save.idtr;
1753 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1754 hsave->save.cr0 = svm->vcpu.arch.cr0;
1755 hsave->save.cr4 = svm->vcpu.arch.cr4;
1756 hsave->save.rflags = vmcb->save.rflags;
1757 hsave->save.rip = svm->next_rip;
1758 hsave->save.rsp = vmcb->save.rsp;
1759 hsave->save.rax = vmcb->save.rax;
1760 if (npt_enabled)
1761 hsave->save.cr3 = vmcb->save.cr3;
1762 else
1763 hsave->save.cr3 = svm->vcpu.arch.cr3;
1764
1765 copy_vmcb_control_area(hsave, vmcb);
1766
1767 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1768 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1769 else
1770 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1771
1772 /* Load the nested guest state */
1773 svm->vmcb->save.es = nested_vmcb->save.es;
1774 svm->vmcb->save.cs = nested_vmcb->save.cs;
1775 svm->vmcb->save.ss = nested_vmcb->save.ss;
1776 svm->vmcb->save.ds = nested_vmcb->save.ds;
1777 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1778 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1779 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1780 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1781 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1782 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1783 if (npt_enabled) {
1784 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1785 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1786 } else {
1787 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1788 kvm_mmu_reset_context(&svm->vcpu);
1789 }
1790 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1791 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1792 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1793 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1794 /* In case we don't even reach vcpu_run, the fields are not updated */
1795 svm->vmcb->save.rax = nested_vmcb->save.rax;
1796 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1797 svm->vmcb->save.rip = nested_vmcb->save.rip;
1798 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1799 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1800 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1801
1802 /* We don't want a nested guest to be more powerful than the guest,
1803 so all intercepts are ORed */
1804 svm->vmcb->control.intercept_cr_read |=
1805 nested_vmcb->control.intercept_cr_read;
1806 svm->vmcb->control.intercept_cr_write |=
1807 nested_vmcb->control.intercept_cr_write;
1808 svm->vmcb->control.intercept_dr_read |=
1809 nested_vmcb->control.intercept_dr_read;
1810 svm->vmcb->control.intercept_dr_write |=
1811 nested_vmcb->control.intercept_dr_write;
1812 svm->vmcb->control.intercept_exceptions |=
1813 nested_vmcb->control.intercept_exceptions;
1814
1815 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1816
1817 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1818
1819 /* cache intercepts */
1820 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1821 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1822 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1823 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1824 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1825 svm->nested.intercept = nested_vmcb->control.intercept;
1826
1827 force_new_asid(&svm->vcpu);
1828 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1829 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1830 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1831 nested_vmcb->control.int_ctl);
1832 }
1833 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1834 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1835 else
1836 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1837
1838 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1839 nested_vmcb->control.exit_int_info,
1840 nested_vmcb->control.int_state);
1841
1842 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1843 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1844 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1845 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1846 nsvm_printk("Injecting Event: 0x%x\n",
1847 nested_vmcb->control.event_inj);
1848 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1849 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1850
1851 nested_svm_unmap(nested_vmcb, KM_USER0);
1852
1853 enable_gif(svm);
1854
1855 return true;
1856 }
1857
1858 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1859 {
1860 to_vmcb->save.fs = from_vmcb->save.fs;
1861 to_vmcb->save.gs = from_vmcb->save.gs;
1862 to_vmcb->save.tr = from_vmcb->save.tr;
1863 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1864 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1865 to_vmcb->save.star = from_vmcb->save.star;
1866 to_vmcb->save.lstar = from_vmcb->save.lstar;
1867 to_vmcb->save.cstar = from_vmcb->save.cstar;
1868 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1869 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1870 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1871 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1872 }
1873
1874 static int vmload_interception(struct vcpu_svm *svm)
1875 {
1876 struct vmcb *nested_vmcb;
1877
1878 if (nested_svm_check_permissions(svm))
1879 return 1;
1880
1881 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1882 skip_emulated_instruction(&svm->vcpu);
1883
1884 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1885 if (!nested_vmcb)
1886 return 1;
1887
1888 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1889 nested_svm_unmap(nested_vmcb, KM_USER0);
1890
1891 return 1;
1892 }
1893
1894 static int vmsave_interception(struct vcpu_svm *svm)
1895 {
1896 struct vmcb *nested_vmcb;
1897
1898 if (nested_svm_check_permissions(svm))
1899 return 1;
1900
1901 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1902 skip_emulated_instruction(&svm->vcpu);
1903
1904 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1905 if (!nested_vmcb)
1906 return 1;
1907
1908 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1909 nested_svm_unmap(nested_vmcb, KM_USER0);
1910
1911 return 1;
1912 }
1913
1914 static int vmrun_interception(struct vcpu_svm *svm)
1915 {
1916 nsvm_printk("VMrun\n");
1917
1918 if (nested_svm_check_permissions(svm))
1919 return 1;
1920
1921 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1922 skip_emulated_instruction(&svm->vcpu);
1923
1924 if (!nested_svm_vmrun(svm))
1925 return 1;
1926
1927 if (!nested_svm_vmrun_msrpm(svm))
1928 goto failed;
1929
1930 return 1;
1931
1932 failed:
1933
1934 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1935 svm->vmcb->control.exit_code_hi = 0;
1936 svm->vmcb->control.exit_info_1 = 0;
1937 svm->vmcb->control.exit_info_2 = 0;
1938
1939 nested_svm_vmexit(svm);
1940
1941 return 1;
1942 }
1943
1944 static int stgi_interception(struct vcpu_svm *svm)
1945 {
1946 if (nested_svm_check_permissions(svm))
1947 return 1;
1948
1949 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1950 skip_emulated_instruction(&svm->vcpu);
1951
1952 enable_gif(svm);
1953
1954 return 1;
1955 }
1956
1957 static int clgi_interception(struct vcpu_svm *svm)
1958 {
1959 if (nested_svm_check_permissions(svm))
1960 return 1;
1961
1962 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1963 skip_emulated_instruction(&svm->vcpu);
1964
1965 disable_gif(svm);
1966
1967 /* After a CLGI no interrupts should come */
1968 svm_clear_vintr(svm);
1969 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1970
1971 return 1;
1972 }
1973
1974 static int invlpga_interception(struct vcpu_svm *svm)
1975 {
1976 struct kvm_vcpu *vcpu = &svm->vcpu;
1977 nsvm_printk("INVLPGA\n");
1978
1979 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1980 vcpu->arch.regs[VCPU_REGS_RAX]);
1981
1982 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1983 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1984
1985 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1986 skip_emulated_instruction(&svm->vcpu);
1987 return 1;
1988 }
1989
1990 static int skinit_interception(struct vcpu_svm *svm)
1991 {
1992 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1993
1994 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1995 return 1;
1996 }
1997
1998 static int invalid_op_interception(struct vcpu_svm *svm)
1999 {
2000 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2001 return 1;
2002 }
2003
2004 static int task_switch_interception(struct vcpu_svm *svm)
2005 {
2006 u16 tss_selector;
2007 int reason;
2008 int int_type = svm->vmcb->control.exit_int_info &
2009 SVM_EXITINTINFO_TYPE_MASK;
2010 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2011 uint32_t type =
2012 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2013 uint32_t idt_v =
2014 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2015
2016 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2017
2018 if (svm->vmcb->control.exit_info_2 &
2019 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2020 reason = TASK_SWITCH_IRET;
2021 else if (svm->vmcb->control.exit_info_2 &
2022 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2023 reason = TASK_SWITCH_JMP;
2024 else if (idt_v)
2025 reason = TASK_SWITCH_GATE;
2026 else
2027 reason = TASK_SWITCH_CALL;
2028
2029 if (reason == TASK_SWITCH_GATE) {
2030 switch (type) {
2031 case SVM_EXITINTINFO_TYPE_NMI:
2032 svm->vcpu.arch.nmi_injected = false;
2033 break;
2034 case SVM_EXITINTINFO_TYPE_EXEPT:
2035 kvm_clear_exception_queue(&svm->vcpu);
2036 break;
2037 case SVM_EXITINTINFO_TYPE_INTR:
2038 kvm_clear_interrupt_queue(&svm->vcpu);
2039 break;
2040 default:
2041 break;
2042 }
2043 }
2044
2045 if (reason != TASK_SWITCH_GATE ||
2046 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2047 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2048 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2049 skip_emulated_instruction(&svm->vcpu);
2050
2051 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2052 }
2053
2054 static int cpuid_interception(struct vcpu_svm *svm)
2055 {
2056 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2057 kvm_emulate_cpuid(&svm->vcpu);
2058 return 1;
2059 }
2060
2061 static int iret_interception(struct vcpu_svm *svm)
2062 {
2063 ++svm->vcpu.stat.nmi_window_exits;
2064 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2065 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2066 return 1;
2067 }
2068
2069 static int invlpg_interception(struct vcpu_svm *svm)
2070 {
2071 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2072 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2073 return 1;
2074 }
2075
2076 static int emulate_on_interception(struct vcpu_svm *svm)
2077 {
2078 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2079 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2080 return 1;
2081 }
2082
2083 static int cr8_write_interception(struct vcpu_svm *svm)
2084 {
2085 struct kvm_run *kvm_run = svm->vcpu.run;
2086
2087 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2088 /* instruction emulation calls kvm_set_cr8() */
2089 emulate_instruction(&svm->vcpu, 0, 0, 0);
2090 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2091 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2092 return 1;
2093 }
2094 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2095 return 1;
2096 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2097 return 0;
2098 }
2099
2100 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2101 {
2102 struct vcpu_svm *svm = to_svm(vcpu);
2103
2104 switch (ecx) {
2105 case MSR_IA32_TSC: {
2106 u64 tsc_offset;
2107
2108 if (is_nested(svm))
2109 tsc_offset = svm->nested.hsave->control.tsc_offset;
2110 else
2111 tsc_offset = svm->vmcb->control.tsc_offset;
2112
2113 *data = tsc_offset + native_read_tsc();
2114 break;
2115 }
2116 case MSR_K6_STAR:
2117 *data = svm->vmcb->save.star;
2118 break;
2119 #ifdef CONFIG_X86_64
2120 case MSR_LSTAR:
2121 *data = svm->vmcb->save.lstar;
2122 break;
2123 case MSR_CSTAR:
2124 *data = svm->vmcb->save.cstar;
2125 break;
2126 case MSR_KERNEL_GS_BASE:
2127 *data = svm->vmcb->save.kernel_gs_base;
2128 break;
2129 case MSR_SYSCALL_MASK:
2130 *data = svm->vmcb->save.sfmask;
2131 break;
2132 #endif
2133 case MSR_IA32_SYSENTER_CS:
2134 *data = svm->vmcb->save.sysenter_cs;
2135 break;
2136 case MSR_IA32_SYSENTER_EIP:
2137 *data = svm->sysenter_eip;
2138 break;
2139 case MSR_IA32_SYSENTER_ESP:
2140 *data = svm->sysenter_esp;
2141 break;
2142 /* Nobody will change the following 5 values in the VMCB so
2143 we can safely return them on rdmsr. They will always be 0
2144 until LBRV is implemented. */
2145 case MSR_IA32_DEBUGCTLMSR:
2146 *data = svm->vmcb->save.dbgctl;
2147 break;
2148 case MSR_IA32_LASTBRANCHFROMIP:
2149 *data = svm->vmcb->save.br_from;
2150 break;
2151 case MSR_IA32_LASTBRANCHTOIP:
2152 *data = svm->vmcb->save.br_to;
2153 break;
2154 case MSR_IA32_LASTINTFROMIP:
2155 *data = svm->vmcb->save.last_excp_from;
2156 break;
2157 case MSR_IA32_LASTINTTOIP:
2158 *data = svm->vmcb->save.last_excp_to;
2159 break;
2160 case MSR_VM_HSAVE_PA:
2161 *data = svm->nested.hsave_msr;
2162 break;
2163 case MSR_VM_CR:
2164 *data = 0;
2165 break;
2166 case MSR_IA32_UCODE_REV:
2167 *data = 0x01000065;
2168 break;
2169 default:
2170 return kvm_get_msr_common(vcpu, ecx, data);
2171 }
2172 return 0;
2173 }
2174
2175 static int rdmsr_interception(struct vcpu_svm *svm)
2176 {
2177 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2178 u64 data;
2179
2180 if (svm_get_msr(&svm->vcpu, ecx, &data))
2181 kvm_inject_gp(&svm->vcpu, 0);
2182 else {
2183 trace_kvm_msr_read(ecx, data);
2184
2185 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2186 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2187 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2188 skip_emulated_instruction(&svm->vcpu);
2189 }
2190 return 1;
2191 }
2192
2193 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2194 {
2195 struct vcpu_svm *svm = to_svm(vcpu);
2196
2197 switch (ecx) {
2198 case MSR_IA32_TSC: {
2199 u64 tsc_offset = data - native_read_tsc();
2200 u64 g_tsc_offset = 0;
2201
2202 if (is_nested(svm)) {
2203 g_tsc_offset = svm->vmcb->control.tsc_offset -
2204 svm->nested.hsave->control.tsc_offset;
2205 svm->nested.hsave->control.tsc_offset = tsc_offset;
2206 }
2207
2208 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2209
2210 break;
2211 }
2212 case MSR_K6_STAR:
2213 svm->vmcb->save.star = data;
2214 break;
2215 #ifdef CONFIG_X86_64
2216 case MSR_LSTAR:
2217 svm->vmcb->save.lstar = data;
2218 break;
2219 case MSR_CSTAR:
2220 svm->vmcb->save.cstar = data;
2221 break;
2222 case MSR_KERNEL_GS_BASE:
2223 svm->vmcb->save.kernel_gs_base = data;
2224 break;
2225 case MSR_SYSCALL_MASK:
2226 svm->vmcb->save.sfmask = data;
2227 break;
2228 #endif
2229 case MSR_IA32_SYSENTER_CS:
2230 svm->vmcb->save.sysenter_cs = data;
2231 break;
2232 case MSR_IA32_SYSENTER_EIP:
2233 svm->sysenter_eip = data;
2234 svm->vmcb->save.sysenter_eip = data;
2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
2237 svm->sysenter_esp = data;
2238 svm->vmcb->save.sysenter_esp = data;
2239 break;
2240 case MSR_IA32_DEBUGCTLMSR:
2241 if (!svm_has(SVM_FEATURE_LBRV)) {
2242 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2243 __func__, data);
2244 break;
2245 }
2246 if (data & DEBUGCTL_RESERVED_BITS)
2247 return 1;
2248
2249 svm->vmcb->save.dbgctl = data;
2250 if (data & (1ULL<<0))
2251 svm_enable_lbrv(svm);
2252 else
2253 svm_disable_lbrv(svm);
2254 break;
2255 case MSR_VM_HSAVE_PA:
2256 svm->nested.hsave_msr = data;
2257 break;
2258 case MSR_VM_CR:
2259 case MSR_VM_IGNNE:
2260 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2261 break;
2262 default:
2263 return kvm_set_msr_common(vcpu, ecx, data);
2264 }
2265 return 0;
2266 }
2267
2268 static int wrmsr_interception(struct vcpu_svm *svm)
2269 {
2270 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2271 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2272 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2273
2274 trace_kvm_msr_write(ecx, data);
2275
2276 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2277 if (svm_set_msr(&svm->vcpu, ecx, data))
2278 kvm_inject_gp(&svm->vcpu, 0);
2279 else
2280 skip_emulated_instruction(&svm->vcpu);
2281 return 1;
2282 }
2283
2284 static int msr_interception(struct vcpu_svm *svm)
2285 {
2286 if (svm->vmcb->control.exit_info_1)
2287 return wrmsr_interception(svm);
2288 else
2289 return rdmsr_interception(svm);
2290 }
2291
2292 static int interrupt_window_interception(struct vcpu_svm *svm)
2293 {
2294 struct kvm_run *kvm_run = svm->vcpu.run;
2295
2296 svm_clear_vintr(svm);
2297 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2298 /*
2299 * If the user space waits to inject interrupts, exit as soon as
2300 * possible
2301 */
2302 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2303 kvm_run->request_interrupt_window &&
2304 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2305 ++svm->vcpu.stat.irq_window_exits;
2306 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2307 return 0;
2308 }
2309
2310 return 1;
2311 }
2312
2313 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2314 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2315 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2316 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2317 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2318 /* for now: */
2319 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2320 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2321 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2322 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2323 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2324 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2325 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2326 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2327 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2328 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2329 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2330 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2331 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2332 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2333 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2334 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2335 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2336 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2337 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2338 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2339 [SVM_EXIT_INTR] = intr_interception,
2340 [SVM_EXIT_NMI] = nmi_interception,
2341 [SVM_EXIT_SMI] = nop_on_interception,
2342 [SVM_EXIT_INIT] = nop_on_interception,
2343 [SVM_EXIT_VINTR] = interrupt_window_interception,
2344 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2345 [SVM_EXIT_CPUID] = cpuid_interception,
2346 [SVM_EXIT_IRET] = iret_interception,
2347 [SVM_EXIT_INVD] = emulate_on_interception,
2348 [SVM_EXIT_HLT] = halt_interception,
2349 [SVM_EXIT_INVLPG] = invlpg_interception,
2350 [SVM_EXIT_INVLPGA] = invlpga_interception,
2351 [SVM_EXIT_IOIO] = io_interception,
2352 [SVM_EXIT_MSR] = msr_interception,
2353 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2354 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2355 [SVM_EXIT_VMRUN] = vmrun_interception,
2356 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2357 [SVM_EXIT_VMLOAD] = vmload_interception,
2358 [SVM_EXIT_VMSAVE] = vmsave_interception,
2359 [SVM_EXIT_STGI] = stgi_interception,
2360 [SVM_EXIT_CLGI] = clgi_interception,
2361 [SVM_EXIT_SKINIT] = skinit_interception,
2362 [SVM_EXIT_WBINVD] = emulate_on_interception,
2363 [SVM_EXIT_MONITOR] = invalid_op_interception,
2364 [SVM_EXIT_MWAIT] = invalid_op_interception,
2365 [SVM_EXIT_NPF] = pf_interception,
2366 };
2367
2368 static int handle_exit(struct kvm_vcpu *vcpu)
2369 {
2370 struct vcpu_svm *svm = to_svm(vcpu);
2371 struct kvm_run *kvm_run = vcpu->run;
2372 u32 exit_code = svm->vmcb->control.exit_code;
2373
2374 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2375
2376 if (unlikely(svm->nested.exit_required)) {
2377 nested_svm_vmexit(svm);
2378 svm->nested.exit_required = false;
2379
2380 return 1;
2381 }
2382
2383 if (is_nested(svm)) {
2384 int vmexit;
2385
2386 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2387 svm->vmcb->control.exit_info_1,
2388 svm->vmcb->control.exit_info_2,
2389 svm->vmcb->control.exit_int_info,
2390 svm->vmcb->control.exit_int_info_err);
2391
2392 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2393 exit_code, svm->vmcb->control.exit_info_1,
2394 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2395
2396 vmexit = nested_svm_exit_special(svm);
2397
2398 if (vmexit == NESTED_EXIT_CONTINUE)
2399 vmexit = nested_svm_exit_handled(svm);
2400
2401 if (vmexit == NESTED_EXIT_DONE)
2402 return 1;
2403 }
2404
2405 svm_complete_interrupts(svm);
2406
2407 if (npt_enabled) {
2408 int mmu_reload = 0;
2409 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2410 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2411 mmu_reload = 1;
2412 }
2413 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2414 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2415 if (mmu_reload) {
2416 kvm_mmu_reset_context(vcpu);
2417 kvm_mmu_load(vcpu);
2418 }
2419 }
2420
2421
2422 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2423 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2424 kvm_run->fail_entry.hardware_entry_failure_reason
2425 = svm->vmcb->control.exit_code;
2426 return 0;
2427 }
2428
2429 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2430 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2431 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2432 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2433 "exit_code 0x%x\n",
2434 __func__, svm->vmcb->control.exit_int_info,
2435 exit_code);
2436
2437 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2438 || !svm_exit_handlers[exit_code]) {
2439 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2440 kvm_run->hw.hardware_exit_reason = exit_code;
2441 return 0;
2442 }
2443
2444 return svm_exit_handlers[exit_code](svm);
2445 }
2446
2447 static void reload_tss(struct kvm_vcpu *vcpu)
2448 {
2449 int cpu = raw_smp_processor_id();
2450
2451 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2452 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2453 load_TR_desc();
2454 }
2455
2456 static void pre_svm_run(struct vcpu_svm *svm)
2457 {
2458 int cpu = raw_smp_processor_id();
2459
2460 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2461
2462 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2463 /* FIXME: handle wraparound of asid_generation */
2464 if (svm->asid_generation != svm_data->asid_generation)
2465 new_asid(svm, svm_data);
2466 }
2467
2468 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2469 {
2470 struct vcpu_svm *svm = to_svm(vcpu);
2471
2472 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2473 vcpu->arch.hflags |= HF_NMI_MASK;
2474 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2475 ++vcpu->stat.nmi_injections;
2476 }
2477
2478 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2479 {
2480 struct vmcb_control_area *control;
2481
2482 trace_kvm_inj_virq(irq);
2483
2484 ++svm->vcpu.stat.irq_injections;
2485 control = &svm->vmcb->control;
2486 control->int_vector = irq;
2487 control->int_ctl &= ~V_INTR_PRIO_MASK;
2488 control->int_ctl |= V_IRQ_MASK |
2489 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2490 }
2491
2492 static void svm_set_irq(struct kvm_vcpu *vcpu)
2493 {
2494 struct vcpu_svm *svm = to_svm(vcpu);
2495
2496 BUG_ON(!(gif_set(svm)));
2497
2498 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2499 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2500 }
2501
2502 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2503 {
2504 struct vcpu_svm *svm = to_svm(vcpu);
2505
2506 if (irr == -1)
2507 return;
2508
2509 if (tpr >= irr)
2510 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2511 }
2512
2513 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2514 {
2515 struct vcpu_svm *svm = to_svm(vcpu);
2516 struct vmcb *vmcb = svm->vmcb;
2517 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2518 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2519 }
2520
2521 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2522 {
2523 struct vcpu_svm *svm = to_svm(vcpu);
2524 struct vmcb *vmcb = svm->vmcb;
2525 int ret;
2526
2527 if (!gif_set(svm) ||
2528 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2529 return 0;
2530
2531 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2532
2533 if (is_nested(svm))
2534 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2535
2536 return ret;
2537 }
2538
2539 static void enable_irq_window(struct kvm_vcpu *vcpu)
2540 {
2541 struct vcpu_svm *svm = to_svm(vcpu);
2542 nsvm_printk("Trying to open IRQ window\n");
2543
2544 nested_svm_intr(svm);
2545
2546 /* In case GIF=0 we can't rely on the CPU to tell us when
2547 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2548 * The next time we get that intercept, this function will be
2549 * called again though and we'll get the vintr intercept. */
2550 if (gif_set(svm)) {
2551 svm_set_vintr(svm);
2552 svm_inject_irq(svm, 0x0);
2553 }
2554 }
2555
2556 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2557 {
2558 struct vcpu_svm *svm = to_svm(vcpu);
2559
2560 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2561 == HF_NMI_MASK)
2562 return; /* IRET will cause a vm exit */
2563
2564 /* Something prevents NMI from been injected. Single step over
2565 possible problem (IRET or exception injection or interrupt
2566 shadow) */
2567 vcpu->arch.singlestep = true;
2568 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2569 update_db_intercept(vcpu);
2570 }
2571
2572 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2573 {
2574 return 0;
2575 }
2576
2577 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2578 {
2579 force_new_asid(vcpu);
2580 }
2581
2582 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2583 {
2584 }
2585
2586 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2587 {
2588 struct vcpu_svm *svm = to_svm(vcpu);
2589
2590 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2591 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2592 kvm_set_cr8(vcpu, cr8);
2593 }
2594 }
2595
2596 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2597 {
2598 struct vcpu_svm *svm = to_svm(vcpu);
2599 u64 cr8;
2600
2601 cr8 = kvm_get_cr8(vcpu);
2602 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2603 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2604 }
2605
2606 static void svm_complete_interrupts(struct vcpu_svm *svm)
2607 {
2608 u8 vector;
2609 int type;
2610 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2611
2612 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2613 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2614
2615 svm->vcpu.arch.nmi_injected = false;
2616 kvm_clear_exception_queue(&svm->vcpu);
2617 kvm_clear_interrupt_queue(&svm->vcpu);
2618
2619 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2620 return;
2621
2622 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2623 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2624
2625 switch (type) {
2626 case SVM_EXITINTINFO_TYPE_NMI:
2627 svm->vcpu.arch.nmi_injected = true;
2628 break;
2629 case SVM_EXITINTINFO_TYPE_EXEPT:
2630 /* In case of software exception do not reinject an exception
2631 vector, but re-execute and instruction instead */
2632 if (is_nested(svm))
2633 break;
2634 if (kvm_exception_is_soft(vector))
2635 break;
2636 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2637 u32 err = svm->vmcb->control.exit_int_info_err;
2638 kvm_queue_exception_e(&svm->vcpu, vector, err);
2639
2640 } else
2641 kvm_queue_exception(&svm->vcpu, vector);
2642 break;
2643 case SVM_EXITINTINFO_TYPE_INTR:
2644 kvm_queue_interrupt(&svm->vcpu, vector, false);
2645 break;
2646 default:
2647 break;
2648 }
2649 }
2650
2651 #ifdef CONFIG_X86_64
2652 #define R "r"
2653 #else
2654 #define R "e"
2655 #endif
2656
2657 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2658 {
2659 struct vcpu_svm *svm = to_svm(vcpu);
2660 u16 fs_selector;
2661 u16 gs_selector;
2662 u16 ldt_selector;
2663
2664 /*
2665 * A vmexit emulation is required before the vcpu can be executed
2666 * again.
2667 */
2668 if (unlikely(svm->nested.exit_required))
2669 return;
2670
2671 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2672 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2673 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2674
2675 pre_svm_run(svm);
2676
2677 sync_lapic_to_cr8(vcpu);
2678
2679 save_host_msrs(vcpu);
2680 fs_selector = kvm_read_fs();
2681 gs_selector = kvm_read_gs();
2682 ldt_selector = kvm_read_ldt();
2683 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2684 /* required for live migration with NPT */
2685 if (npt_enabled)
2686 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2687
2688 clgi();
2689
2690 local_irq_enable();
2691
2692 asm volatile (
2693 "push %%"R"bp; \n\t"
2694 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2695 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2696 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2697 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2698 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2699 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2700 #ifdef CONFIG_X86_64
2701 "mov %c[r8](%[svm]), %%r8 \n\t"
2702 "mov %c[r9](%[svm]), %%r9 \n\t"
2703 "mov %c[r10](%[svm]), %%r10 \n\t"
2704 "mov %c[r11](%[svm]), %%r11 \n\t"
2705 "mov %c[r12](%[svm]), %%r12 \n\t"
2706 "mov %c[r13](%[svm]), %%r13 \n\t"
2707 "mov %c[r14](%[svm]), %%r14 \n\t"
2708 "mov %c[r15](%[svm]), %%r15 \n\t"
2709 #endif
2710
2711 /* Enter guest mode */
2712 "push %%"R"ax \n\t"
2713 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2714 __ex(SVM_VMLOAD) "\n\t"
2715 __ex(SVM_VMRUN) "\n\t"
2716 __ex(SVM_VMSAVE) "\n\t"
2717 "pop %%"R"ax \n\t"
2718
2719 /* Save guest registers, load host registers */
2720 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2721 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2722 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2723 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2724 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2725 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2726 #ifdef CONFIG_X86_64
2727 "mov %%r8, %c[r8](%[svm]) \n\t"
2728 "mov %%r9, %c[r9](%[svm]) \n\t"
2729 "mov %%r10, %c[r10](%[svm]) \n\t"
2730 "mov %%r11, %c[r11](%[svm]) \n\t"
2731 "mov %%r12, %c[r12](%[svm]) \n\t"
2732 "mov %%r13, %c[r13](%[svm]) \n\t"
2733 "mov %%r14, %c[r14](%[svm]) \n\t"
2734 "mov %%r15, %c[r15](%[svm]) \n\t"
2735 #endif
2736 "pop %%"R"bp"
2737 :
2738 : [svm]"a"(svm),
2739 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2740 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2741 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2742 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2743 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2744 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2745 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2746 #ifdef CONFIG_X86_64
2747 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2748 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2749 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2750 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2751 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2752 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2753 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2754 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2755 #endif
2756 : "cc", "memory"
2757 , R"bx", R"cx", R"dx", R"si", R"di"
2758 #ifdef CONFIG_X86_64
2759 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2760 #endif
2761 );
2762
2763 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2764 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2765 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2766 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2767
2768 kvm_load_fs(fs_selector);
2769 kvm_load_gs(gs_selector);
2770 kvm_load_ldt(ldt_selector);
2771 load_host_msrs(vcpu);
2772
2773 reload_tss(vcpu);
2774
2775 local_irq_disable();
2776
2777 stgi();
2778
2779 sync_cr8_to_lapic(vcpu);
2780
2781 svm->next_rip = 0;
2782
2783 if (npt_enabled) {
2784 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2785 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2786 }
2787 }
2788
2789 #undef R
2790
2791 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2792 {
2793 struct vcpu_svm *svm = to_svm(vcpu);
2794
2795 if (npt_enabled) {
2796 svm->vmcb->control.nested_cr3 = root;
2797 force_new_asid(vcpu);
2798 return;
2799 }
2800
2801 svm->vmcb->save.cr3 = root;
2802 force_new_asid(vcpu);
2803
2804 if (vcpu->fpu_active) {
2805 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2806 svm->vmcb->save.cr0 |= X86_CR0_TS;
2807 vcpu->fpu_active = 0;
2808 }
2809 }
2810
2811 static int is_disabled(void)
2812 {
2813 u64 vm_cr;
2814
2815 rdmsrl(MSR_VM_CR, vm_cr);
2816 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2817 return 1;
2818
2819 return 0;
2820 }
2821
2822 static void
2823 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2824 {
2825 /*
2826 * Patch in the VMMCALL instruction:
2827 */
2828 hypercall[0] = 0x0f;
2829 hypercall[1] = 0x01;
2830 hypercall[2] = 0xd9;
2831 }
2832
2833 static void svm_check_processor_compat(void *rtn)
2834 {
2835 *(int *)rtn = 0;
2836 }
2837
2838 static bool svm_cpu_has_accelerated_tpr(void)
2839 {
2840 return false;
2841 }
2842
2843 static int get_npt_level(void)
2844 {
2845 #ifdef CONFIG_X86_64
2846 return PT64_ROOT_LEVEL;
2847 #else
2848 return PT32E_ROOT_LEVEL;
2849 #endif
2850 }
2851
2852 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2853 {
2854 return 0;
2855 }
2856
2857 static const struct trace_print_flags svm_exit_reasons_str[] = {
2858 { SVM_EXIT_READ_CR0, "read_cr0" },
2859 { SVM_EXIT_READ_CR3, "read_cr3" },
2860 { SVM_EXIT_READ_CR4, "read_cr4" },
2861 { SVM_EXIT_READ_CR8, "read_cr8" },
2862 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2863 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2864 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2865 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2866 { SVM_EXIT_READ_DR0, "read_dr0" },
2867 { SVM_EXIT_READ_DR1, "read_dr1" },
2868 { SVM_EXIT_READ_DR2, "read_dr2" },
2869 { SVM_EXIT_READ_DR3, "read_dr3" },
2870 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2871 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2872 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2873 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2874 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2875 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2876 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2877 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2878 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2879 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2880 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2881 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2882 { SVM_EXIT_INTR, "interrupt" },
2883 { SVM_EXIT_NMI, "nmi" },
2884 { SVM_EXIT_SMI, "smi" },
2885 { SVM_EXIT_INIT, "init" },
2886 { SVM_EXIT_VINTR, "vintr" },
2887 { SVM_EXIT_CPUID, "cpuid" },
2888 { SVM_EXIT_INVD, "invd" },
2889 { SVM_EXIT_HLT, "hlt" },
2890 { SVM_EXIT_INVLPG, "invlpg" },
2891 { SVM_EXIT_INVLPGA, "invlpga" },
2892 { SVM_EXIT_IOIO, "io" },
2893 { SVM_EXIT_MSR, "msr" },
2894 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2895 { SVM_EXIT_SHUTDOWN, "shutdown" },
2896 { SVM_EXIT_VMRUN, "vmrun" },
2897 { SVM_EXIT_VMMCALL, "hypercall" },
2898 { SVM_EXIT_VMLOAD, "vmload" },
2899 { SVM_EXIT_VMSAVE, "vmsave" },
2900 { SVM_EXIT_STGI, "stgi" },
2901 { SVM_EXIT_CLGI, "clgi" },
2902 { SVM_EXIT_SKINIT, "skinit" },
2903 { SVM_EXIT_WBINVD, "wbinvd" },
2904 { SVM_EXIT_MONITOR, "monitor" },
2905 { SVM_EXIT_MWAIT, "mwait" },
2906 { SVM_EXIT_NPF, "npf" },
2907 { -1, NULL }
2908 };
2909
2910 static bool svm_gb_page_enable(void)
2911 {
2912 return true;
2913 }
2914
2915 static struct kvm_x86_ops svm_x86_ops = {
2916 .cpu_has_kvm_support = has_svm,
2917 .disabled_by_bios = is_disabled,
2918 .hardware_setup = svm_hardware_setup,
2919 .hardware_unsetup = svm_hardware_unsetup,
2920 .check_processor_compatibility = svm_check_processor_compat,
2921 .hardware_enable = svm_hardware_enable,
2922 .hardware_disable = svm_hardware_disable,
2923 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2924
2925 .vcpu_create = svm_create_vcpu,
2926 .vcpu_free = svm_free_vcpu,
2927 .vcpu_reset = svm_vcpu_reset,
2928
2929 .prepare_guest_switch = svm_prepare_guest_switch,
2930 .vcpu_load = svm_vcpu_load,
2931 .vcpu_put = svm_vcpu_put,
2932
2933 .set_guest_debug = svm_guest_debug,
2934 .get_msr = svm_get_msr,
2935 .set_msr = svm_set_msr,
2936 .get_segment_base = svm_get_segment_base,
2937 .get_segment = svm_get_segment,
2938 .set_segment = svm_set_segment,
2939 .get_cpl = svm_get_cpl,
2940 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2941 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2942 .set_cr0 = svm_set_cr0,
2943 .set_cr3 = svm_set_cr3,
2944 .set_cr4 = svm_set_cr4,
2945 .set_efer = svm_set_efer,
2946 .get_idt = svm_get_idt,
2947 .set_idt = svm_set_idt,
2948 .get_gdt = svm_get_gdt,
2949 .set_gdt = svm_set_gdt,
2950 .get_dr = svm_get_dr,
2951 .set_dr = svm_set_dr,
2952 .cache_reg = svm_cache_reg,
2953 .get_rflags = svm_get_rflags,
2954 .set_rflags = svm_set_rflags,
2955
2956 .tlb_flush = svm_flush_tlb,
2957
2958 .run = svm_vcpu_run,
2959 .handle_exit = handle_exit,
2960 .skip_emulated_instruction = skip_emulated_instruction,
2961 .set_interrupt_shadow = svm_set_interrupt_shadow,
2962 .get_interrupt_shadow = svm_get_interrupt_shadow,
2963 .patch_hypercall = svm_patch_hypercall,
2964 .set_irq = svm_set_irq,
2965 .set_nmi = svm_inject_nmi,
2966 .queue_exception = svm_queue_exception,
2967 .interrupt_allowed = svm_interrupt_allowed,
2968 .nmi_allowed = svm_nmi_allowed,
2969 .enable_nmi_window = enable_nmi_window,
2970 .enable_irq_window = enable_irq_window,
2971 .update_cr8_intercept = update_cr8_intercept,
2972
2973 .set_tss_addr = svm_set_tss_addr,
2974 .get_tdp_level = get_npt_level,
2975 .get_mt_mask = svm_get_mt_mask,
2976
2977 .exit_reasons_str = svm_exit_reasons_str,
2978 .gb_page_enable = svm_gb_page_enable,
2979 };
2980
2981 static int __init svm_init(void)
2982 {
2983 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2984 THIS_MODULE);
2985 }
2986
2987 static void __exit svm_exit(void)
2988 {
2989 kvm_exit();
2990 }
2991
2992 module_init(svm_init)
2993 module_exit(svm_exit)
Ubuntu Artful kernel mirror