2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
49 #include <asm/virtext.h>
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
54 MODULE_AUTHOR("Qumranet");
55 MODULE_LICENSE("GPL");
57 static const struct x86_cpu_id svm_cpu_id
[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
61 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
63 #define IOPM_ALLOC_ORDER 2
64 #define MSRPM_ALLOC_ORDER 1
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
69 #define SVM_FEATURE_NPT (1 << 0)
70 #define SVM_FEATURE_LBRV (1 << 1)
71 #define SVM_FEATURE_SVML (1 << 2)
72 #define SVM_FEATURE_NRIP (1 << 3)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
79 #define SVM_AVIC_DOORBELL 0xc001011b
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
116 static bool erratum_383_found __read_mostly
;
118 static const u32 host_save_user_msrs
[] = {
120 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
123 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
131 struct nested_state
{
137 /* These are the merged vectors */
140 /* gpa pointers to the real vectors */
144 /* A VMEXIT is required but not yet emulated */
147 /* cache for intercepts of the guest */
150 u32 intercept_exceptions
;
153 /* Nested Paging related state */
157 #define MSRPM_OFFSETS 16
158 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
161 * Set osvw_len to higher value when updated Revision Guides
162 * are published and we know what the new status bits are
164 static uint64_t osvw_len
= 4, osvw_status
;
167 struct kvm_vcpu vcpu
;
169 unsigned long vmcb_pa
;
170 struct svm_cpu_data
*svm_data
;
171 uint64_t asid_generation
;
172 uint64_t sysenter_esp
;
173 uint64_t sysenter_eip
;
178 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
190 struct nested_state nested
;
193 u64 nmi_singlestep_guest_rflags
;
195 unsigned int3_injected
;
196 unsigned long int3_rip
;
198 /* cached guest cpuid flags for faster access */
199 bool nrips_enabled
: 1;
202 struct page
*avic_backing_page
;
203 u64
*avic_physical_id_cache
;
204 bool avic_is_running
;
207 * Per-vcpu list of struct amd_svm_iommu_ir:
208 * This is used mainly to store interrupt remapping information used
209 * when update the vcpu affinity. This avoids the need to scan for
210 * IRTE and try to match ga_tag in the IOMMU driver.
212 struct list_head ir_list
;
213 spinlock_t ir_list_lock
;
217 * This is a wrapper of struct amd_iommu_ir_data.
219 struct amd_svm_iommu_ir
{
220 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
221 void *data
; /* Storing pointer to struct amd_ir_data */
224 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
225 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
227 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
228 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
229 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
230 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
232 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
233 #define TSC_RATIO_DEFAULT 0x0100000000ULL
235 #define MSR_INVALID 0xffffffffU
237 static const struct svm_direct_access_msrs
{
238 u32 index
; /* Index of the MSR */
239 bool always
; /* True if intercept is always on */
240 } direct_access_msrs
[] = {
241 { .index
= MSR_STAR
, .always
= true },
242 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
244 { .index
= MSR_GS_BASE
, .always
= true },
245 { .index
= MSR_FS_BASE
, .always
= true },
246 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
247 { .index
= MSR_LSTAR
, .always
= true },
248 { .index
= MSR_CSTAR
, .always
= true },
249 { .index
= MSR_SYSCALL_MASK
, .always
= true },
251 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
252 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
253 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
254 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
255 { .index
= MSR_INVALID
, .always
= false },
258 /* enable NPT for AMD64 and X86 with PAE */
259 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
260 static bool npt_enabled
= true;
262 static bool npt_enabled
;
265 /* allow nested paging (virtualized MMU) for all guests */
266 static int npt
= true;
267 module_param(npt
, int, S_IRUGO
);
269 /* allow nested virtualization in KVM/SVM */
270 static int nested
= true;
271 module_param(nested
, int, S_IRUGO
);
273 /* enable / disable AVIC */
275 #ifdef CONFIG_X86_LOCAL_APIC
276 module_param(avic
, int, S_IRUGO
);
279 /* enable/disable Virtual VMLOAD VMSAVE */
280 static int vls
= true;
281 module_param(vls
, int, 0444);
283 /* enable/disable Virtual GIF */
284 static int vgif
= true;
285 module_param(vgif
, int, 0444);
287 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
288 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
289 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
291 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
292 static int nested_svm_intercept(struct vcpu_svm
*svm
);
293 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
294 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
295 bool has_error_code
, u32 error_code
);
298 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
299 pause filter count */
300 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
301 VMCB_ASID
, /* ASID */
302 VMCB_INTR
, /* int_ctl, int_vector */
303 VMCB_NPT
, /* npt_en, nCR3, gPAT */
304 VMCB_CR
, /* CR0, CR3, CR4, EFER */
305 VMCB_DR
, /* DR6, DR7 */
306 VMCB_DT
, /* GDT, IDT */
307 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
308 VMCB_CR2
, /* CR2 only */
309 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
310 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
311 * AVIC PHYSICAL_TABLE pointer,
312 * AVIC LOGICAL_TABLE pointer
317 /* TPR and CR2 are always written before VMRUN */
318 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
320 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
322 static inline void mark_all_dirty(struct vmcb
*vmcb
)
324 vmcb
->control
.clean
= 0;
327 static inline void mark_all_clean(struct vmcb
*vmcb
)
329 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
330 & ~VMCB_ALWAYS_DIRTY_MASK
;
333 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
335 vmcb
->control
.clean
&= ~(1 << bit
);
338 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
340 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
343 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
345 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
346 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
349 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
351 struct vcpu_svm
*svm
= to_svm(vcpu
);
352 u64
*entry
= svm
->avic_physical_id_cache
;
357 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
360 static void recalc_intercepts(struct vcpu_svm
*svm
)
362 struct vmcb_control_area
*c
, *h
;
363 struct nested_state
*g
;
365 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
367 if (!is_guest_mode(&svm
->vcpu
))
370 c
= &svm
->vmcb
->control
;
371 h
= &svm
->nested
.hsave
->control
;
374 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
375 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
376 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
377 c
->intercept
= h
->intercept
| g
->intercept
;
380 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
382 if (is_guest_mode(&svm
->vcpu
))
383 return svm
->nested
.hsave
;
388 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
390 struct vmcb
*vmcb
= get_host_vmcb(svm
);
392 vmcb
->control
.intercept_cr
|= (1U << bit
);
394 recalc_intercepts(svm
);
397 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
399 struct vmcb
*vmcb
= get_host_vmcb(svm
);
401 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
403 recalc_intercepts(svm
);
406 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
408 struct vmcb
*vmcb
= get_host_vmcb(svm
);
410 return vmcb
->control
.intercept_cr
& (1U << bit
);
413 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
415 struct vmcb
*vmcb
= get_host_vmcb(svm
);
417 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
418 | (1 << INTERCEPT_DR1_READ
)
419 | (1 << INTERCEPT_DR2_READ
)
420 | (1 << INTERCEPT_DR3_READ
)
421 | (1 << INTERCEPT_DR4_READ
)
422 | (1 << INTERCEPT_DR5_READ
)
423 | (1 << INTERCEPT_DR6_READ
)
424 | (1 << INTERCEPT_DR7_READ
)
425 | (1 << INTERCEPT_DR0_WRITE
)
426 | (1 << INTERCEPT_DR1_WRITE
)
427 | (1 << INTERCEPT_DR2_WRITE
)
428 | (1 << INTERCEPT_DR3_WRITE
)
429 | (1 << INTERCEPT_DR4_WRITE
)
430 | (1 << INTERCEPT_DR5_WRITE
)
431 | (1 << INTERCEPT_DR6_WRITE
)
432 | (1 << INTERCEPT_DR7_WRITE
);
434 recalc_intercepts(svm
);
437 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
439 struct vmcb
*vmcb
= get_host_vmcb(svm
);
441 vmcb
->control
.intercept_dr
= 0;
443 recalc_intercepts(svm
);
446 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
448 struct vmcb
*vmcb
= get_host_vmcb(svm
);
450 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
452 recalc_intercepts(svm
);
455 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
457 struct vmcb
*vmcb
= get_host_vmcb(svm
);
459 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
461 recalc_intercepts(svm
);
464 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
466 struct vmcb
*vmcb
= get_host_vmcb(svm
);
468 vmcb
->control
.intercept
|= (1ULL << bit
);
470 recalc_intercepts(svm
);
473 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
475 struct vmcb
*vmcb
= get_host_vmcb(svm
);
477 vmcb
->control
.intercept
&= ~(1ULL << bit
);
479 recalc_intercepts(svm
);
482 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
484 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
487 static inline void enable_gif(struct vcpu_svm
*svm
)
489 if (vgif_enabled(svm
))
490 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
492 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
495 static inline void disable_gif(struct vcpu_svm
*svm
)
497 if (vgif_enabled(svm
))
498 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
500 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
503 static inline bool gif_set(struct vcpu_svm
*svm
)
505 if (vgif_enabled(svm
))
506 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
508 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
511 static unsigned long iopm_base
;
513 struct kvm_ldttss_desc
{
516 unsigned base1
:8, type
:5, dpl
:2, p
:1;
517 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
520 } __attribute__((packed
));
522 struct svm_cpu_data
{
528 struct kvm_ldttss_desc
*tss_desc
;
530 struct page
*save_area
;
533 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
535 struct svm_init_data
{
540 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
542 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
543 #define MSRS_RANGE_SIZE 2048
544 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
546 static u32
svm_msrpm_offset(u32 msr
)
551 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
552 if (msr
< msrpm_ranges
[i
] ||
553 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
556 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
557 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
559 /* Now we have the u8 offset - but need the u32 offset */
563 /* MSR not in any range */
567 #define MAX_INST_SIZE 15
569 static inline void clgi(void)
571 asm volatile (__ex(SVM_CLGI
));
574 static inline void stgi(void)
576 asm volatile (__ex(SVM_STGI
));
579 static inline void invlpga(unsigned long addr
, u32 asid
)
581 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
584 static int get_npt_level(struct kvm_vcpu
*vcpu
)
587 return PT64_ROOT_4LEVEL
;
589 return PT32E_ROOT_LEVEL
;
593 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
595 vcpu
->arch
.efer
= efer
;
596 if (!npt_enabled
&& !(efer
& EFER_LMA
))
599 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
600 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
603 static int is_external_interrupt(u32 info
)
605 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
606 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
609 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
611 struct vcpu_svm
*svm
= to_svm(vcpu
);
614 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
615 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
619 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
621 struct vcpu_svm
*svm
= to_svm(vcpu
);
624 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
626 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
630 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
632 struct vcpu_svm
*svm
= to_svm(vcpu
);
634 if (svm
->vmcb
->control
.next_rip
!= 0) {
635 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
636 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
639 if (!svm
->next_rip
) {
640 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
642 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
645 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
646 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
647 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
649 kvm_rip_write(vcpu
, svm
->next_rip
);
650 svm_set_interrupt_shadow(vcpu
, 0);
653 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
655 struct vcpu_svm
*svm
= to_svm(vcpu
);
656 unsigned nr
= vcpu
->arch
.exception
.nr
;
657 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
658 bool reinject
= vcpu
->arch
.exception
.injected
;
659 u32 error_code
= vcpu
->arch
.exception
.error_code
;
662 * If we are within a nested VM we'd better #VMEXIT and let the guest
663 * handle the exception
666 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
669 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
670 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
673 * For guest debugging where we have to reinject #BP if some
674 * INT3 is guest-owned:
675 * Emulate nRIP by moving RIP forward. Will fail if injection
676 * raises a fault that is not intercepted. Still better than
677 * failing in all cases.
679 skip_emulated_instruction(&svm
->vcpu
);
680 rip
= kvm_rip_read(&svm
->vcpu
);
681 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
682 svm
->int3_injected
= rip
- old_rip
;
685 svm
->vmcb
->control
.event_inj
= nr
687 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
688 | SVM_EVTINJ_TYPE_EXEPT
;
689 svm
->vmcb
->control
.event_inj_err
= error_code
;
692 static void svm_init_erratum_383(void)
698 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
701 /* Use _safe variants to not break nested virtualization */
702 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
708 low
= lower_32_bits(val
);
709 high
= upper_32_bits(val
);
711 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
713 erratum_383_found
= true;
716 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
719 * Guests should see errata 400 and 415 as fixed (assuming that
720 * HLT and IO instructions are intercepted).
722 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
723 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
726 * By increasing VCPU's osvw.length to 3 we are telling the guest that
727 * all osvw.status bits inside that length, including bit 0 (which is
728 * reserved for erratum 298), are valid. However, if host processor's
729 * osvw_len is 0 then osvw_status[0] carries no information. We need to
730 * be conservative here and therefore we tell the guest that erratum 298
731 * is present (because we really don't know).
733 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
734 vcpu
->arch
.osvw
.status
|= 1;
737 static int has_svm(void)
741 if (!cpu_has_svm(&msg
)) {
742 printk(KERN_INFO
"has_svm: %s\n", msg
);
749 static void svm_hardware_disable(void)
751 /* Make sure we clean up behind us */
752 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
753 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
757 amd_pmu_disable_virt();
760 static int svm_hardware_enable(void)
763 struct svm_cpu_data
*sd
;
765 struct desc_struct
*gdt
;
766 int me
= raw_smp_processor_id();
768 rdmsrl(MSR_EFER
, efer
);
769 if (efer
& EFER_SVME
)
773 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
776 sd
= per_cpu(svm_data
, me
);
778 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
782 sd
->asid_generation
= 1;
783 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
784 sd
->next_asid
= sd
->max_asid
+ 1;
786 gdt
= get_current_gdt_rw();
787 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
789 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
791 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
793 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
794 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
795 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
802 * Note that it is possible to have a system with mixed processor
803 * revisions and therefore different OSVW bits. If bits are not the same
804 * on different processors then choose the worst case (i.e. if erratum
805 * is present on one processor and not on another then assume that the
806 * erratum is present everywhere).
808 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
809 uint64_t len
, status
= 0;
812 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
814 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
818 osvw_status
= osvw_len
= 0;
822 osvw_status
|= status
;
823 osvw_status
&= (1ULL << osvw_len
) - 1;
826 osvw_status
= osvw_len
= 0;
828 svm_init_erratum_383();
830 amd_pmu_enable_virt();
835 static void svm_cpu_uninit(int cpu
)
837 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
842 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
843 __free_page(sd
->save_area
);
847 static int svm_cpu_init(int cpu
)
849 struct svm_cpu_data
*sd
;
852 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
856 sd
->save_area
= alloc_page(GFP_KERNEL
);
861 per_cpu(svm_data
, cpu
) = sd
;
871 static bool valid_msr_intercept(u32 index
)
875 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
876 if (direct_access_msrs
[i
].index
== index
)
882 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
885 u8 bit_read
, bit_write
;
890 * If this warning triggers extend the direct_access_msrs list at the
891 * beginning of the file
893 WARN_ON(!valid_msr_intercept(msr
));
895 offset
= svm_msrpm_offset(msr
);
896 bit_read
= 2 * (msr
& 0x0f);
897 bit_write
= 2 * (msr
& 0x0f) + 1;
900 BUG_ON(offset
== MSR_INVALID
);
902 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
903 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
908 static void svm_vcpu_init_msrpm(u32
*msrpm
)
912 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
914 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
915 if (!direct_access_msrs
[i
].always
)
918 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
922 static void add_msr_offset(u32 offset
)
926 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
928 /* Offset already in list? */
929 if (msrpm_offsets
[i
] == offset
)
932 /* Slot used by another offset? */
933 if (msrpm_offsets
[i
] != MSR_INVALID
)
936 /* Add offset to list */
937 msrpm_offsets
[i
] = offset
;
943 * If this BUG triggers the msrpm_offsets table has an overflow. Just
944 * increase MSRPM_OFFSETS in this case.
949 static void init_msrpm_offsets(void)
953 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
955 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
958 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
959 BUG_ON(offset
== MSR_INVALID
);
961 add_msr_offset(offset
);
965 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
967 u32
*msrpm
= svm
->msrpm
;
969 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
970 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
971 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
972 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
973 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
976 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
978 u32
*msrpm
= svm
->msrpm
;
980 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
981 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
982 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
983 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
984 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
987 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
989 svm
->nmi_singlestep
= false;
991 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
992 /* Clear our flags if they were not set by the guest */
993 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
994 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
995 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
996 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1001 * This hash table is used to map VM_ID to a struct kvm_arch,
1002 * when handling AMD IOMMU GALOG notification to schedule in
1003 * a particular vCPU.
1005 #define SVM_VM_DATA_HASH_BITS 8
1006 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1007 static u32 next_vm_id
= 0;
1008 static bool next_vm_id_wrapped
= 0;
1009 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1012 * This function is called from IOMMU driver to notify
1013 * SVM to schedule in a particular vCPU of a particular VM.
1015 static int avic_ga_log_notifier(u32 ga_tag
)
1017 unsigned long flags
;
1018 struct kvm_arch
*ka
= NULL
;
1019 struct kvm_vcpu
*vcpu
= NULL
;
1020 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1021 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1023 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1025 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1026 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
1027 struct kvm
*kvm
= container_of(ka
, struct kvm
, arch
);
1028 struct kvm_arch
*vm_data
= &kvm
->arch
;
1030 if (vm_data
->avic_vm_id
!= vm_id
)
1032 vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
1035 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1038 * At this point, the IOMMU should have already set the pending
1039 * bit in the vAPIC backing page. So, we just need to schedule
1043 kvm_vcpu_wake_up(vcpu
);
1048 static __init
int svm_hardware_setup(void)
1051 struct page
*iopm_pages
;
1055 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1060 iopm_va
= page_address(iopm_pages
);
1061 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1062 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1064 init_msrpm_offsets();
1066 if (boot_cpu_has(X86_FEATURE_NX
))
1067 kvm_enable_efer_bits(EFER_NX
);
1069 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1070 kvm_enable_efer_bits(EFER_FFXSR
);
1072 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1073 kvm_has_tsc_control
= true;
1074 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1075 kvm_tsc_scaling_ratio_frac_bits
= 32;
1079 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1080 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1083 for_each_possible_cpu(cpu
) {
1084 r
= svm_cpu_init(cpu
);
1089 if (!boot_cpu_has(X86_FEATURE_NPT
))
1090 npt_enabled
= false;
1092 if (npt_enabled
&& !npt
) {
1093 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1094 npt_enabled
= false;
1098 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1105 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1106 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1109 pr_info("AVIC enabled\n");
1111 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1117 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1118 !IS_ENABLED(CONFIG_X86_64
)) {
1121 pr_info("Virtual VMLOAD VMSAVE supported\n");
1126 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1129 pr_info("Virtual GIF supported\n");
1135 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1140 static __exit
void svm_hardware_unsetup(void)
1144 for_each_possible_cpu(cpu
)
1145 svm_cpu_uninit(cpu
);
1147 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1151 static void init_seg(struct vmcb_seg
*seg
)
1154 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1155 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1156 seg
->limit
= 0xffff;
1160 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1163 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1164 seg
->limit
= 0xffff;
1168 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1170 struct vcpu_svm
*svm
= to_svm(vcpu
);
1171 u64 g_tsc_offset
= 0;
1173 if (is_guest_mode(vcpu
)) {
1174 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1175 svm
->nested
.hsave
->control
.tsc_offset
;
1176 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1178 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1179 svm
->vmcb
->control
.tsc_offset
,
1182 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1184 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1187 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1189 struct vmcb
*vmcb
= svm
->vmcb
;
1190 struct kvm_arch
*vm_data
= &svm
->vcpu
.kvm
->arch
;
1191 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1192 phys_addr_t lpa
= __sme_set(page_to_phys(vm_data
->avic_logical_id_table_page
));
1193 phys_addr_t ppa
= __sme_set(page_to_phys(vm_data
->avic_physical_id_table_page
));
1195 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1196 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1197 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1198 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1199 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1202 static void init_vmcb(struct vcpu_svm
*svm
)
1204 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1205 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1207 svm
->vcpu
.arch
.hflags
= 0;
1209 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1210 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1211 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1212 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1213 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1214 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1215 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1216 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1218 set_dr_intercepts(svm
);
1220 set_exception_intercept(svm
, PF_VECTOR
);
1221 set_exception_intercept(svm
, UD_VECTOR
);
1222 set_exception_intercept(svm
, MC_VECTOR
);
1223 set_exception_intercept(svm
, AC_VECTOR
);
1224 set_exception_intercept(svm
, DB_VECTOR
);
1226 set_intercept(svm
, INTERCEPT_INTR
);
1227 set_intercept(svm
, INTERCEPT_NMI
);
1228 set_intercept(svm
, INTERCEPT_SMI
);
1229 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1230 set_intercept(svm
, INTERCEPT_RDPMC
);
1231 set_intercept(svm
, INTERCEPT_CPUID
);
1232 set_intercept(svm
, INTERCEPT_INVD
);
1233 set_intercept(svm
, INTERCEPT_HLT
);
1234 set_intercept(svm
, INTERCEPT_INVLPG
);
1235 set_intercept(svm
, INTERCEPT_INVLPGA
);
1236 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1237 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1238 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1239 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1240 set_intercept(svm
, INTERCEPT_VMRUN
);
1241 set_intercept(svm
, INTERCEPT_VMMCALL
);
1242 set_intercept(svm
, INTERCEPT_VMLOAD
);
1243 set_intercept(svm
, INTERCEPT_VMSAVE
);
1244 set_intercept(svm
, INTERCEPT_STGI
);
1245 set_intercept(svm
, INTERCEPT_CLGI
);
1246 set_intercept(svm
, INTERCEPT_SKINIT
);
1247 set_intercept(svm
, INTERCEPT_WBINVD
);
1248 set_intercept(svm
, INTERCEPT_XSETBV
);
1250 if (!kvm_mwait_in_guest()) {
1251 set_intercept(svm
, INTERCEPT_MONITOR
);
1252 set_intercept(svm
, INTERCEPT_MWAIT
);
1255 control
->iopm_base_pa
= __sme_set(iopm_base
);
1256 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1257 control
->int_ctl
= V_INTR_MASKING_MASK
;
1259 init_seg(&save
->es
);
1260 init_seg(&save
->ss
);
1261 init_seg(&save
->ds
);
1262 init_seg(&save
->fs
);
1263 init_seg(&save
->gs
);
1265 save
->cs
.selector
= 0xf000;
1266 save
->cs
.base
= 0xffff0000;
1267 /* Executable/Readable Code Segment */
1268 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1269 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1270 save
->cs
.limit
= 0xffff;
1272 save
->gdtr
.limit
= 0xffff;
1273 save
->idtr
.limit
= 0xffff;
1275 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1276 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1278 svm_set_efer(&svm
->vcpu
, 0);
1279 save
->dr6
= 0xffff0ff0;
1280 kvm_set_rflags(&svm
->vcpu
, 2);
1281 save
->rip
= 0x0000fff0;
1282 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1285 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1286 * It also updates the guest-visible cr0 value.
1288 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1289 kvm_mmu_reset_context(&svm
->vcpu
);
1291 save
->cr4
= X86_CR4_PAE
;
1295 /* Setup VMCB for Nested Paging */
1296 control
->nested_ctl
= 1;
1297 clr_intercept(svm
, INTERCEPT_INVLPG
);
1298 clr_exception_intercept(svm
, PF_VECTOR
);
1299 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1300 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1301 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1305 svm
->asid_generation
= 0;
1307 svm
->nested
.vmcb
= 0;
1308 svm
->vcpu
.arch
.hflags
= 0;
1310 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1311 control
->pause_filter_count
= 3000;
1312 set_intercept(svm
, INTERCEPT_PAUSE
);
1315 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1316 avic_init_vmcb(svm
);
1319 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1320 * in VMCB and clear intercepts to avoid #VMEXIT.
1323 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1324 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1325 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1329 clr_intercept(svm
, INTERCEPT_STGI
);
1330 clr_intercept(svm
, INTERCEPT_CLGI
);
1331 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1334 mark_all_dirty(svm
->vmcb
);
1340 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1343 u64
*avic_physical_id_table
;
1344 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
1346 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1349 avic_physical_id_table
= page_address(vm_data
->avic_physical_id_table_page
);
1351 return &avic_physical_id_table
[index
];
1356 * AVIC hardware walks the nested page table to check permissions,
1357 * but does not use the SPA address specified in the leaf page
1358 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1359 * field of the VMCB. Therefore, we set up the
1360 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1362 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1364 struct kvm
*kvm
= vcpu
->kvm
;
1367 if (kvm
->arch
.apic_access_page_done
)
1370 ret
= x86_set_memory_region(kvm
,
1371 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1372 APIC_DEFAULT_PHYS_BASE
,
1377 kvm
->arch
.apic_access_page_done
= true;
1381 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1384 u64
*entry
, new_entry
;
1385 int id
= vcpu
->vcpu_id
;
1386 struct vcpu_svm
*svm
= to_svm(vcpu
);
1388 ret
= avic_init_access_page(vcpu
);
1392 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1395 if (!svm
->vcpu
.arch
.apic
->regs
)
1398 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1400 /* Setting AVIC backing page address in the phy APIC ID table */
1401 entry
= avic_get_physical_id_entry(vcpu
, id
);
1405 new_entry
= READ_ONCE(*entry
);
1406 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1407 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1408 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1409 WRITE_ONCE(*entry
, new_entry
);
1411 svm
->avic_physical_id_cache
= entry
;
1416 static void avic_vm_destroy(struct kvm
*kvm
)
1418 unsigned long flags
;
1419 struct kvm_arch
*vm_data
= &kvm
->arch
;
1424 if (vm_data
->avic_logical_id_table_page
)
1425 __free_page(vm_data
->avic_logical_id_table_page
);
1426 if (vm_data
->avic_physical_id_table_page
)
1427 __free_page(vm_data
->avic_physical_id_table_page
);
1429 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1430 hash_del(&vm_data
->hnode
);
1431 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1434 static int avic_vm_init(struct kvm
*kvm
)
1436 unsigned long flags
;
1438 struct kvm_arch
*vm_data
= &kvm
->arch
;
1439 struct page
*p_page
;
1440 struct page
*l_page
;
1441 struct kvm_arch
*ka
;
1447 /* Allocating physical APIC ID table (4KB) */
1448 p_page
= alloc_page(GFP_KERNEL
);
1452 vm_data
->avic_physical_id_table_page
= p_page
;
1453 clear_page(page_address(p_page
));
1455 /* Allocating logical APIC ID table (4KB) */
1456 l_page
= alloc_page(GFP_KERNEL
);
1460 vm_data
->avic_logical_id_table_page
= l_page
;
1461 clear_page(page_address(l_page
));
1463 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1465 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1466 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1467 next_vm_id_wrapped
= 1;
1470 /* Is it still in use? Only possible if wrapped at least once */
1471 if (next_vm_id_wrapped
) {
1472 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
1473 struct kvm
*k2
= container_of(ka
, struct kvm
, arch
);
1474 struct kvm_arch
*vd2
= &k2
->arch
;
1475 if (vd2
->avic_vm_id
== vm_id
)
1479 vm_data
->avic_vm_id
= vm_id
;
1480 hash_add(svm_vm_data_hash
, &vm_data
->hnode
, vm_data
->avic_vm_id
);
1481 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1486 avic_vm_destroy(kvm
);
1491 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1494 unsigned long flags
;
1495 struct amd_svm_iommu_ir
*ir
;
1496 struct vcpu_svm
*svm
= to_svm(vcpu
);
1498 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1502 * Here, we go through the per-vcpu ir_list to update all existing
1503 * interrupt remapping table entry targeting this vcpu.
1505 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1507 if (list_empty(&svm
->ir_list
))
1510 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1511 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
1516 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
1520 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1523 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1524 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
1525 struct vcpu_svm
*svm
= to_svm(vcpu
);
1527 if (!kvm_vcpu_apicv_active(vcpu
))
1530 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
1533 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1534 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
1536 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
1537 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
1539 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1540 if (svm
->avic_is_running
)
1541 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1543 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1544 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
1545 svm
->avic_is_running
);
1548 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
1551 struct vcpu_svm
*svm
= to_svm(vcpu
);
1553 if (!kvm_vcpu_apicv_active(vcpu
))
1556 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1557 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
1558 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
1560 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1561 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1565 * This function is called during VCPU halt/unhalt.
1567 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
1569 struct vcpu_svm
*svm
= to_svm(vcpu
);
1571 svm
->avic_is_running
= is_run
;
1573 avic_vcpu_load(vcpu
, vcpu
->cpu
);
1575 avic_vcpu_put(vcpu
);
1578 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1580 struct vcpu_svm
*svm
= to_svm(vcpu
);
1585 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1586 MSR_IA32_APICBASE_ENABLE
;
1587 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1588 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1592 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
1593 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1595 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1596 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1599 static int avic_init_vcpu(struct vcpu_svm
*svm
)
1603 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1606 ret
= avic_init_backing_page(&svm
->vcpu
);
1610 INIT_LIST_HEAD(&svm
->ir_list
);
1611 spin_lock_init(&svm
->ir_list_lock
);
1616 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1618 struct vcpu_svm
*svm
;
1620 struct page
*msrpm_pages
;
1621 struct page
*hsave_page
;
1622 struct page
*nested_msrpm_pages
;
1625 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1631 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1636 page
= alloc_page(GFP_KERNEL
);
1640 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1644 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1645 if (!nested_msrpm_pages
)
1648 hsave_page
= alloc_page(GFP_KERNEL
);
1652 err
= avic_init_vcpu(svm
);
1656 /* We initialize this flag to true to make sure that the is_running
1657 * bit would be set the first time the vcpu is loaded.
1659 svm
->avic_is_running
= true;
1661 svm
->nested
.hsave
= page_address(hsave_page
);
1663 svm
->msrpm
= page_address(msrpm_pages
);
1664 svm_vcpu_init_msrpm(svm
->msrpm
);
1666 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1667 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1669 svm
->vmcb
= page_address(page
);
1670 clear_page(svm
->vmcb
);
1671 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
1672 svm
->asid_generation
= 0;
1675 svm_init_osvw(&svm
->vcpu
);
1680 __free_page(hsave_page
);
1682 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1684 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1688 kvm_vcpu_uninit(&svm
->vcpu
);
1690 kmem_cache_free(kvm_vcpu_cache
, svm
);
1692 return ERR_PTR(err
);
1695 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1697 struct vcpu_svm
*svm
= to_svm(vcpu
);
1699 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
1700 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1701 __free_page(virt_to_page(svm
->nested
.hsave
));
1702 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1703 kvm_vcpu_uninit(vcpu
);
1704 kmem_cache_free(kvm_vcpu_cache
, svm
);
1707 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1709 struct vcpu_svm
*svm
= to_svm(vcpu
);
1712 if (unlikely(cpu
!= vcpu
->cpu
)) {
1713 svm
->asid_generation
= 0;
1714 mark_all_dirty(svm
->vmcb
);
1717 #ifdef CONFIG_X86_64
1718 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1720 savesegment(fs
, svm
->host
.fs
);
1721 savesegment(gs
, svm
->host
.gs
);
1722 svm
->host
.ldt
= kvm_read_ldt();
1724 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1725 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1727 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1728 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1729 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1730 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1731 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1734 /* This assumes that the kernel never uses MSR_TSC_AUX */
1735 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1736 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
1738 avic_vcpu_load(vcpu
, cpu
);
1741 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1743 struct vcpu_svm
*svm
= to_svm(vcpu
);
1746 avic_vcpu_put(vcpu
);
1748 ++vcpu
->stat
.host_state_reload
;
1749 kvm_load_ldt(svm
->host
.ldt
);
1750 #ifdef CONFIG_X86_64
1751 loadsegment(fs
, svm
->host
.fs
);
1752 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
1753 load_gs_index(svm
->host
.gs
);
1755 #ifdef CONFIG_X86_32_LAZY_GS
1756 loadsegment(gs
, svm
->host
.gs
);
1759 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1760 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1763 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
1765 avic_set_running(vcpu
, false);
1768 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
1770 avic_set_running(vcpu
, true);
1773 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1775 struct vcpu_svm
*svm
= to_svm(vcpu
);
1776 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
1778 if (svm
->nmi_singlestep
) {
1779 /* Hide our flags if they were not set by the guest */
1780 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1781 rflags
&= ~X86_EFLAGS_TF
;
1782 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1783 rflags
&= ~X86_EFLAGS_RF
;
1788 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1790 if (to_svm(vcpu
)->nmi_singlestep
)
1791 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1794 * Any change of EFLAGS.VM is accompanied by a reload of SS
1795 * (caused by either a task switch or an inter-privilege IRET),
1796 * so we do not need to update the CPL here.
1798 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1801 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1804 case VCPU_EXREG_PDPTR
:
1805 BUG_ON(!npt_enabled
);
1806 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1813 static void svm_set_vintr(struct vcpu_svm
*svm
)
1815 set_intercept(svm
, INTERCEPT_VINTR
);
1818 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1820 clr_intercept(svm
, INTERCEPT_VINTR
);
1823 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1825 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1828 case VCPU_SREG_CS
: return &save
->cs
;
1829 case VCPU_SREG_DS
: return &save
->ds
;
1830 case VCPU_SREG_ES
: return &save
->es
;
1831 case VCPU_SREG_FS
: return &save
->fs
;
1832 case VCPU_SREG_GS
: return &save
->gs
;
1833 case VCPU_SREG_SS
: return &save
->ss
;
1834 case VCPU_SREG_TR
: return &save
->tr
;
1835 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1841 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1843 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1848 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1849 struct kvm_segment
*var
, int seg
)
1851 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1853 var
->base
= s
->base
;
1854 var
->limit
= s
->limit
;
1855 var
->selector
= s
->selector
;
1856 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1857 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1858 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1859 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1860 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1861 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1862 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1865 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1866 * However, the SVM spec states that the G bit is not observed by the
1867 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1868 * So let's synthesize a legal G bit for all segments, this helps
1869 * running KVM nested. It also helps cross-vendor migration, because
1870 * Intel's vmentry has a check on the 'G' bit.
1872 var
->g
= s
->limit
> 0xfffff;
1875 * AMD's VMCB does not have an explicit unusable field, so emulate it
1876 * for cross vendor migration purposes by "not present"
1878 var
->unusable
= !var
->present
;
1883 * Work around a bug where the busy flag in the tr selector
1893 * The accessed bit must always be set in the segment
1894 * descriptor cache, although it can be cleared in the
1895 * descriptor, the cached bit always remains at 1. Since
1896 * Intel has a check on this, set it here to support
1897 * cross-vendor migration.
1904 * On AMD CPUs sometimes the DB bit in the segment
1905 * descriptor is left as 1, although the whole segment has
1906 * been made unusable. Clear it here to pass an Intel VMX
1907 * entry check when cross vendor migrating.
1911 /* This is symmetric with svm_set_segment() */
1912 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1917 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1919 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1924 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1926 struct vcpu_svm
*svm
= to_svm(vcpu
);
1928 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1929 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1932 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1934 struct vcpu_svm
*svm
= to_svm(vcpu
);
1936 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1937 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1938 mark_dirty(svm
->vmcb
, VMCB_DT
);
1941 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1943 struct vcpu_svm
*svm
= to_svm(vcpu
);
1945 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1946 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1949 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1951 struct vcpu_svm
*svm
= to_svm(vcpu
);
1953 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1954 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1955 mark_dirty(svm
->vmcb
, VMCB_DT
);
1958 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1962 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1966 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1970 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1972 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1973 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1975 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1976 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1978 mark_dirty(svm
->vmcb
, VMCB_CR
);
1980 if (gcr0
== *hcr0
) {
1981 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1982 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1984 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1985 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1989 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1991 struct vcpu_svm
*svm
= to_svm(vcpu
);
1993 #ifdef CONFIG_X86_64
1994 if (vcpu
->arch
.efer
& EFER_LME
) {
1995 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1996 vcpu
->arch
.efer
|= EFER_LMA
;
1997 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2000 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2001 vcpu
->arch
.efer
&= ~EFER_LMA
;
2002 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2006 vcpu
->arch
.cr0
= cr0
;
2009 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2012 * re-enable caching here because the QEMU bios
2013 * does not do it - this results in some delay at
2016 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2017 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2018 svm
->vmcb
->save
.cr0
= cr0
;
2019 mark_dirty(svm
->vmcb
, VMCB_CR
);
2020 update_cr0_intercept(svm
);
2023 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2025 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2026 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2028 if (cr4
& X86_CR4_VMXE
)
2031 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2032 svm_flush_tlb(vcpu
);
2034 vcpu
->arch
.cr4
= cr4
;
2037 cr4
|= host_cr4_mce
;
2038 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2039 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2043 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2044 struct kvm_segment
*var
, int seg
)
2046 struct vcpu_svm
*svm
= to_svm(vcpu
);
2047 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2049 s
->base
= var
->base
;
2050 s
->limit
= var
->limit
;
2051 s
->selector
= var
->selector
;
2052 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2053 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2054 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2055 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2056 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2057 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2058 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2059 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2062 * This is always accurate, except if SYSRET returned to a segment
2063 * with SS.DPL != 3. Intel does not have this quirk, and always
2064 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2065 * would entail passing the CPL to userspace and back.
2067 if (seg
== VCPU_SREG_SS
)
2068 /* This is symmetric with svm_get_segment() */
2069 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2071 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2074 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2076 struct vcpu_svm
*svm
= to_svm(vcpu
);
2078 clr_exception_intercept(svm
, BP_VECTOR
);
2080 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2081 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2082 set_exception_intercept(svm
, BP_VECTOR
);
2084 vcpu
->guest_debug
= 0;
2087 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2089 if (sd
->next_asid
> sd
->max_asid
) {
2090 ++sd
->asid_generation
;
2092 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2095 svm
->asid_generation
= sd
->asid_generation
;
2096 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2098 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2101 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2103 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2106 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2108 struct vcpu_svm
*svm
= to_svm(vcpu
);
2110 svm
->vmcb
->save
.dr6
= value
;
2111 mark_dirty(svm
->vmcb
, VMCB_DR
);
2114 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2116 struct vcpu_svm
*svm
= to_svm(vcpu
);
2118 get_debugreg(vcpu
->arch
.db
[0], 0);
2119 get_debugreg(vcpu
->arch
.db
[1], 1);
2120 get_debugreg(vcpu
->arch
.db
[2], 2);
2121 get_debugreg(vcpu
->arch
.db
[3], 3);
2122 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2123 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2125 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2126 set_dr_intercepts(svm
);
2129 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2131 struct vcpu_svm
*svm
= to_svm(vcpu
);
2133 svm
->vmcb
->save
.dr7
= value
;
2134 mark_dirty(svm
->vmcb
, VMCB_DR
);
2137 static int pf_interception(struct vcpu_svm
*svm
)
2139 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2140 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2142 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2143 svm
->vmcb
->control
.insn_bytes
,
2144 svm
->vmcb
->control
.insn_len
);
2147 static int npf_interception(struct vcpu_svm
*svm
)
2149 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2150 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2152 trace_kvm_page_fault(fault_address
, error_code
);
2153 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2154 svm
->vmcb
->control
.insn_bytes
,
2155 svm
->vmcb
->control
.insn_len
);
2158 static int db_interception(struct vcpu_svm
*svm
)
2160 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2162 if (!(svm
->vcpu
.guest_debug
&
2163 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2164 !svm
->nmi_singlestep
) {
2165 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2169 if (svm
->nmi_singlestep
) {
2170 disable_nmi_singlestep(svm
);
2173 if (svm
->vcpu
.guest_debug
&
2174 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2175 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2176 kvm_run
->debug
.arch
.pc
=
2177 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2178 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2185 static int bp_interception(struct vcpu_svm
*svm
)
2187 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2189 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2190 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2191 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2195 static int ud_interception(struct vcpu_svm
*svm
)
2199 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
2200 if (er
!= EMULATE_DONE
)
2201 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2205 static int ac_interception(struct vcpu_svm
*svm
)
2207 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2211 static bool is_erratum_383(void)
2216 if (!erratum_383_found
)
2219 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2223 /* Bit 62 may or may not be set for this mce */
2224 value
&= ~(1ULL << 62);
2226 if (value
!= 0xb600000000010015ULL
)
2229 /* Clear MCi_STATUS registers */
2230 for (i
= 0; i
< 6; ++i
)
2231 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2233 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2237 value
&= ~(1ULL << 2);
2238 low
= lower_32_bits(value
);
2239 high
= upper_32_bits(value
);
2241 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2244 /* Flush tlb to evict multi-match entries */
2250 static void svm_handle_mce(struct vcpu_svm
*svm
)
2252 if (is_erratum_383()) {
2254 * Erratum 383 triggered. Guest state is corrupt so kill the
2257 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2259 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2265 * On an #MC intercept the MCE handler is not called automatically in
2266 * the host. So do it by hand here.
2270 /* not sure if we ever come back to this point */
2275 static int mc_interception(struct vcpu_svm
*svm
)
2280 static int shutdown_interception(struct vcpu_svm
*svm
)
2282 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2285 * VMCB is undefined after a SHUTDOWN intercept
2286 * so reinitialize it.
2288 clear_page(svm
->vmcb
);
2291 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2295 static int io_interception(struct vcpu_svm
*svm
)
2297 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2298 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2299 int size
, in
, string
, ret
;
2302 ++svm
->vcpu
.stat
.io_exits
;
2303 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2304 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2306 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2308 port
= io_info
>> 16;
2309 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2310 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2311 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2314 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2315 * KVM_EXIT_DEBUG here.
2318 return kvm_fast_pio_in(vcpu
, size
, port
) && ret
;
2320 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
2323 static int nmi_interception(struct vcpu_svm
*svm
)
2328 static int intr_interception(struct vcpu_svm
*svm
)
2330 ++svm
->vcpu
.stat
.irq_exits
;
2334 static int nop_on_interception(struct vcpu_svm
*svm
)
2339 static int halt_interception(struct vcpu_svm
*svm
)
2341 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2342 return kvm_emulate_halt(&svm
->vcpu
);
2345 static int vmmcall_interception(struct vcpu_svm
*svm
)
2347 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2348 return kvm_emulate_hypercall(&svm
->vcpu
);
2351 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2353 struct vcpu_svm
*svm
= to_svm(vcpu
);
2355 return svm
->nested
.nested_cr3
;
2358 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2360 struct vcpu_svm
*svm
= to_svm(vcpu
);
2361 u64 cr3
= svm
->nested
.nested_cr3
;
2365 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2366 offset_in_page(cr3
) + index
* 8, 8);
2372 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2375 struct vcpu_svm
*svm
= to_svm(vcpu
);
2377 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2378 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2379 svm_flush_tlb(vcpu
);
2382 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2383 struct x86_exception
*fault
)
2385 struct vcpu_svm
*svm
= to_svm(vcpu
);
2387 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2389 * TODO: track the cause of the nested page fault, and
2390 * correctly fill in the high bits of exit_info_1.
2392 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2393 svm
->vmcb
->control
.exit_code_hi
= 0;
2394 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2395 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2398 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2399 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2402 * The present bit is always zero for page structure faults on real
2405 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2406 svm
->vmcb
->control
.exit_info_1
&= ~1;
2408 nested_svm_vmexit(svm
);
2411 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2413 WARN_ON(mmu_is_nested(vcpu
));
2414 kvm_init_shadow_mmu(vcpu
);
2415 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2416 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2417 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2418 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2419 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level(vcpu
);
2420 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2421 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2424 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2426 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2429 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2431 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2432 !is_paging(&svm
->vcpu
)) {
2433 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2437 if (svm
->vmcb
->save
.cpl
) {
2438 kvm_inject_gp(&svm
->vcpu
, 0);
2445 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2446 bool has_error_code
, u32 error_code
)
2450 if (!is_guest_mode(&svm
->vcpu
))
2453 vmexit
= nested_svm_intercept(svm
);
2454 if (vmexit
!= NESTED_EXIT_DONE
)
2457 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2458 svm
->vmcb
->control
.exit_code_hi
= 0;
2459 svm
->vmcb
->control
.exit_info_1
= error_code
;
2462 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2463 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2464 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2465 * written only when inject_pending_event runs (DR6 would written here
2466 * too). This should be conditional on a new capability---if the
2467 * capability is disabled, kvm_multiple_exception would write the
2468 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2470 if (svm
->vcpu
.arch
.exception
.nested_apf
)
2471 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
2473 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2475 svm
->nested
.exit_required
= true;
2479 /* This function returns true if it is save to enable the irq window */
2480 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2482 if (!is_guest_mode(&svm
->vcpu
))
2485 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2488 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2492 * if vmexit was already requested (by intercepted exception
2493 * for instance) do not overwrite it with "external interrupt"
2496 if (svm
->nested
.exit_required
)
2499 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2500 svm
->vmcb
->control
.exit_info_1
= 0;
2501 svm
->vmcb
->control
.exit_info_2
= 0;
2503 if (svm
->nested
.intercept
& 1ULL) {
2505 * The #vmexit can't be emulated here directly because this
2506 * code path runs with irqs and preemption disabled. A
2507 * #vmexit emulation might sleep. Only signal request for
2510 svm
->nested
.exit_required
= true;
2511 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2518 /* This function returns true if it is save to enable the nmi window */
2519 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2521 if (!is_guest_mode(&svm
->vcpu
))
2524 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2527 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2528 svm
->nested
.exit_required
= true;
2533 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2539 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2540 if (is_error_page(page
))
2548 kvm_inject_gp(&svm
->vcpu
, 0);
2553 static void nested_svm_unmap(struct page
*page
)
2556 kvm_release_page_dirty(page
);
2559 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2561 unsigned port
, size
, iopm_len
;
2566 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2567 return NESTED_EXIT_HOST
;
2569 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2570 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2571 SVM_IOIO_SIZE_SHIFT
;
2572 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2573 start_bit
= port
% 8;
2574 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2575 mask
= (0xf >> (4 - size
)) << start_bit
;
2578 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2579 return NESTED_EXIT_DONE
;
2581 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2584 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2586 u32 offset
, msr
, value
;
2589 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2590 return NESTED_EXIT_HOST
;
2592 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2593 offset
= svm_msrpm_offset(msr
);
2594 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2595 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2597 if (offset
== MSR_INVALID
)
2598 return NESTED_EXIT_DONE
;
2600 /* Offset is in 32 bit units but need in 8 bit units */
2603 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2604 return NESTED_EXIT_DONE
;
2606 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2609 /* DB exceptions for our internal use must not cause vmexit */
2610 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
2614 /* if we're not singlestepping, it's not ours */
2615 if (!svm
->nmi_singlestep
)
2616 return NESTED_EXIT_DONE
;
2618 /* if it's not a singlestep exception, it's not ours */
2619 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
2620 return NESTED_EXIT_DONE
;
2621 if (!(dr6
& DR6_BS
))
2622 return NESTED_EXIT_DONE
;
2624 /* if the guest is singlestepping, it should get the vmexit */
2625 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
2626 disable_nmi_singlestep(svm
);
2627 return NESTED_EXIT_DONE
;
2630 /* it's ours, the nested hypervisor must not see this one */
2631 return NESTED_EXIT_HOST
;
2634 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2636 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2638 switch (exit_code
) {
2641 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2642 return NESTED_EXIT_HOST
;
2644 /* For now we are always handling NPFs when using them */
2646 return NESTED_EXIT_HOST
;
2648 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2649 /* When we're shadowing, trap PFs, but not async PF */
2650 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
2651 return NESTED_EXIT_HOST
;
2657 return NESTED_EXIT_CONTINUE
;
2661 * If this function returns true, this #vmexit was already handled
2663 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2665 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2666 int vmexit
= NESTED_EXIT_HOST
;
2668 switch (exit_code
) {
2670 vmexit
= nested_svm_exit_handled_msr(svm
);
2673 vmexit
= nested_svm_intercept_ioio(svm
);
2675 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2676 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2677 if (svm
->nested
.intercept_cr
& bit
)
2678 vmexit
= NESTED_EXIT_DONE
;
2681 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2682 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2683 if (svm
->nested
.intercept_dr
& bit
)
2684 vmexit
= NESTED_EXIT_DONE
;
2687 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2688 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2689 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
2690 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
2691 vmexit
= nested_svm_intercept_db(svm
);
2693 vmexit
= NESTED_EXIT_DONE
;
2695 /* async page fault always cause vmexit */
2696 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2697 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
2698 vmexit
= NESTED_EXIT_DONE
;
2701 case SVM_EXIT_ERR
: {
2702 vmexit
= NESTED_EXIT_DONE
;
2706 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2707 if (svm
->nested
.intercept
& exit_bits
)
2708 vmexit
= NESTED_EXIT_DONE
;
2715 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2719 vmexit
= nested_svm_intercept(svm
);
2721 if (vmexit
== NESTED_EXIT_DONE
)
2722 nested_svm_vmexit(svm
);
2727 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2729 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2730 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2732 dst
->intercept_cr
= from
->intercept_cr
;
2733 dst
->intercept_dr
= from
->intercept_dr
;
2734 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2735 dst
->intercept
= from
->intercept
;
2736 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2737 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2738 dst
->tsc_offset
= from
->tsc_offset
;
2739 dst
->asid
= from
->asid
;
2740 dst
->tlb_ctl
= from
->tlb_ctl
;
2741 dst
->int_ctl
= from
->int_ctl
;
2742 dst
->int_vector
= from
->int_vector
;
2743 dst
->int_state
= from
->int_state
;
2744 dst
->exit_code
= from
->exit_code
;
2745 dst
->exit_code_hi
= from
->exit_code_hi
;
2746 dst
->exit_info_1
= from
->exit_info_1
;
2747 dst
->exit_info_2
= from
->exit_info_2
;
2748 dst
->exit_int_info
= from
->exit_int_info
;
2749 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2750 dst
->nested_ctl
= from
->nested_ctl
;
2751 dst
->event_inj
= from
->event_inj
;
2752 dst
->event_inj_err
= from
->event_inj_err
;
2753 dst
->nested_cr3
= from
->nested_cr3
;
2754 dst
->virt_ext
= from
->virt_ext
;
2757 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2759 struct vmcb
*nested_vmcb
;
2760 struct vmcb
*hsave
= svm
->nested
.hsave
;
2761 struct vmcb
*vmcb
= svm
->vmcb
;
2764 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2765 vmcb
->control
.exit_info_1
,
2766 vmcb
->control
.exit_info_2
,
2767 vmcb
->control
.exit_int_info
,
2768 vmcb
->control
.exit_int_info_err
,
2771 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2775 /* Exit Guest-Mode */
2776 leave_guest_mode(&svm
->vcpu
);
2777 svm
->nested
.vmcb
= 0;
2779 /* Give the current vmcb to the guest */
2782 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2783 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2784 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2785 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2786 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2787 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2788 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2789 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2790 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2791 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2792 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2793 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2794 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2795 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2796 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2797 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2798 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2799 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2801 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2802 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2803 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2804 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2805 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2806 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2807 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2808 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2809 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2811 if (svm
->nrips_enabled
)
2812 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2815 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2816 * to make sure that we do not lose injected events. So check event_inj
2817 * here and copy it to exit_int_info if it is valid.
2818 * Exit_int_info and event_inj can't be both valid because the case
2819 * below only happens on a VMRUN instruction intercept which has
2820 * no valid exit_int_info set.
2822 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2823 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2825 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2826 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2829 nested_vmcb
->control
.tlb_ctl
= 0;
2830 nested_vmcb
->control
.event_inj
= 0;
2831 nested_vmcb
->control
.event_inj_err
= 0;
2833 /* We always set V_INTR_MASKING and remember the old value in hflags */
2834 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2835 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2837 /* Restore the original control entries */
2838 copy_vmcb_control_area(vmcb
, hsave
);
2840 kvm_clear_exception_queue(&svm
->vcpu
);
2841 kvm_clear_interrupt_queue(&svm
->vcpu
);
2843 svm
->nested
.nested_cr3
= 0;
2845 /* Restore selected save entries */
2846 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2847 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2848 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2849 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2850 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2851 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2852 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2853 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2854 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2855 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2857 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2858 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2860 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2862 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2863 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2864 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2865 svm
->vmcb
->save
.dr7
= 0;
2866 svm
->vmcb
->save
.cpl
= 0;
2867 svm
->vmcb
->control
.exit_int_info
= 0;
2869 mark_all_dirty(svm
->vmcb
);
2871 nested_svm_unmap(page
);
2873 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2874 kvm_mmu_reset_context(&svm
->vcpu
);
2875 kvm_mmu_load(&svm
->vcpu
);
2880 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2883 * This function merges the msr permission bitmaps of kvm and the
2884 * nested vmcb. It is optimized in that it only merges the parts where
2885 * the kvm msr permission bitmap may contain zero bits
2889 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2892 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2896 if (msrpm_offsets
[i
] == 0xffffffff)
2899 p
= msrpm_offsets
[i
];
2900 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2902 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2905 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2908 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
2913 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2915 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2918 if (vmcb
->control
.asid
== 0)
2921 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2927 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
2928 struct vmcb
*nested_vmcb
, struct page
*page
)
2930 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2931 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2933 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2935 if (nested_vmcb
->control
.nested_ctl
) {
2936 kvm_mmu_unload(&svm
->vcpu
);
2937 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2938 nested_svm_init_mmu_context(&svm
->vcpu
);
2941 /* Load the nested guest state */
2942 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2943 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2944 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2945 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2946 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2947 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2948 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2949 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2950 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2951 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2953 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2954 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2956 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2958 /* Guest paging mode is active - reset mmu */
2959 kvm_mmu_reset_context(&svm
->vcpu
);
2961 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2962 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2963 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2964 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2966 /* In case we don't even reach vcpu_run, the fields are not updated */
2967 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2968 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2969 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2970 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2971 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2972 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2974 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2975 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2977 /* cache intercepts */
2978 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2979 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2980 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2981 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2983 svm_flush_tlb(&svm
->vcpu
);
2984 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2985 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2986 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2988 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2990 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2991 /* We only want the cr8 intercept bits of the guest */
2992 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2993 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2996 /* We don't want to see VMMCALLs from a nested guest */
2997 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2999 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3000 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3001 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3002 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3003 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3004 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3006 nested_svm_unmap(page
);
3008 /* Enter Guest-Mode */
3009 enter_guest_mode(&svm
->vcpu
);
3012 * Merge guest and host intercepts - must be called with vcpu in
3013 * guest-mode to take affect here
3015 recalc_intercepts(svm
);
3017 svm
->nested
.vmcb
= vmcb_gpa
;
3021 mark_all_dirty(svm
->vmcb
);
3024 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3026 struct vmcb
*nested_vmcb
;
3027 struct vmcb
*hsave
= svm
->nested
.hsave
;
3028 struct vmcb
*vmcb
= svm
->vmcb
;
3032 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3034 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3038 if (!nested_vmcb_checks(nested_vmcb
)) {
3039 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3040 nested_vmcb
->control
.exit_code_hi
= 0;
3041 nested_vmcb
->control
.exit_info_1
= 0;
3042 nested_vmcb
->control
.exit_info_2
= 0;
3044 nested_svm_unmap(page
);
3049 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3050 nested_vmcb
->save
.rip
,
3051 nested_vmcb
->control
.int_ctl
,
3052 nested_vmcb
->control
.event_inj
,
3053 nested_vmcb
->control
.nested_ctl
);
3055 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3056 nested_vmcb
->control
.intercept_cr
>> 16,
3057 nested_vmcb
->control
.intercept_exceptions
,
3058 nested_vmcb
->control
.intercept
);
3060 /* Clear internal status */
3061 kvm_clear_exception_queue(&svm
->vcpu
);
3062 kvm_clear_interrupt_queue(&svm
->vcpu
);
3065 * Save the old vmcb, so we don't need to pick what we save, but can
3066 * restore everything when a VMEXIT occurs
3068 hsave
->save
.es
= vmcb
->save
.es
;
3069 hsave
->save
.cs
= vmcb
->save
.cs
;
3070 hsave
->save
.ss
= vmcb
->save
.ss
;
3071 hsave
->save
.ds
= vmcb
->save
.ds
;
3072 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3073 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3074 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3075 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3076 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3077 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3078 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3079 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3080 hsave
->save
.rax
= vmcb
->save
.rax
;
3082 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3084 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3086 copy_vmcb_control_area(hsave
, vmcb
);
3088 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, page
);
3093 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3095 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3096 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3097 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3098 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3099 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3100 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3101 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3102 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3103 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3104 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3105 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3106 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3109 static int vmload_interception(struct vcpu_svm
*svm
)
3111 struct vmcb
*nested_vmcb
;
3115 if (nested_svm_check_permissions(svm
))
3118 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3122 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3123 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3125 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3126 nested_svm_unmap(page
);
3131 static int vmsave_interception(struct vcpu_svm
*svm
)
3133 struct vmcb
*nested_vmcb
;
3137 if (nested_svm_check_permissions(svm
))
3140 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3144 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3145 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3147 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3148 nested_svm_unmap(page
);
3153 static int vmrun_interception(struct vcpu_svm
*svm
)
3155 if (nested_svm_check_permissions(svm
))
3158 /* Save rip after vmrun instruction */
3159 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3161 if (!nested_svm_vmrun(svm
))
3164 if (!nested_svm_vmrun_msrpm(svm
))
3171 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3172 svm
->vmcb
->control
.exit_code_hi
= 0;
3173 svm
->vmcb
->control
.exit_info_1
= 0;
3174 svm
->vmcb
->control
.exit_info_2
= 0;
3176 nested_svm_vmexit(svm
);
3181 static int stgi_interception(struct vcpu_svm
*svm
)
3185 if (nested_svm_check_permissions(svm
))
3189 * If VGIF is enabled, the STGI intercept is only added to
3190 * detect the opening of the SMI/NMI window; remove it now.
3192 if (vgif_enabled(svm
))
3193 clr_intercept(svm
, INTERCEPT_STGI
);
3195 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3196 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3197 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3204 static int clgi_interception(struct vcpu_svm
*svm
)
3208 if (nested_svm_check_permissions(svm
))
3211 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3212 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3216 /* After a CLGI no interrupts should come */
3217 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3218 svm_clear_vintr(svm
);
3219 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3220 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3226 static int invlpga_interception(struct vcpu_svm
*svm
)
3228 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3230 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3231 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3233 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3234 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3236 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3237 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3240 static int skinit_interception(struct vcpu_svm
*svm
)
3242 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3244 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3248 static int wbinvd_interception(struct vcpu_svm
*svm
)
3250 return kvm_emulate_wbinvd(&svm
->vcpu
);
3253 static int xsetbv_interception(struct vcpu_svm
*svm
)
3255 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3256 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3258 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3259 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3260 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3266 static int task_switch_interception(struct vcpu_svm
*svm
)
3270 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3271 SVM_EXITINTINFO_TYPE_MASK
;
3272 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3274 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3276 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3277 bool has_error_code
= false;
3280 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3282 if (svm
->vmcb
->control
.exit_info_2
&
3283 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3284 reason
= TASK_SWITCH_IRET
;
3285 else if (svm
->vmcb
->control
.exit_info_2
&
3286 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3287 reason
= TASK_SWITCH_JMP
;
3289 reason
= TASK_SWITCH_GATE
;
3291 reason
= TASK_SWITCH_CALL
;
3293 if (reason
== TASK_SWITCH_GATE
) {
3295 case SVM_EXITINTINFO_TYPE_NMI
:
3296 svm
->vcpu
.arch
.nmi_injected
= false;
3298 case SVM_EXITINTINFO_TYPE_EXEPT
:
3299 if (svm
->vmcb
->control
.exit_info_2
&
3300 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3301 has_error_code
= true;
3303 (u32
)svm
->vmcb
->control
.exit_info_2
;
3305 kvm_clear_exception_queue(&svm
->vcpu
);
3307 case SVM_EXITINTINFO_TYPE_INTR
:
3308 kvm_clear_interrupt_queue(&svm
->vcpu
);
3315 if (reason
!= TASK_SWITCH_GATE
||
3316 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3317 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3318 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3319 skip_emulated_instruction(&svm
->vcpu
);
3321 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3324 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3325 has_error_code
, error_code
) == EMULATE_FAIL
) {
3326 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3327 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3328 svm
->vcpu
.run
->internal
.ndata
= 0;
3334 static int cpuid_interception(struct vcpu_svm
*svm
)
3336 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3337 return kvm_emulate_cpuid(&svm
->vcpu
);
3340 static int iret_interception(struct vcpu_svm
*svm
)
3342 ++svm
->vcpu
.stat
.nmi_window_exits
;
3343 clr_intercept(svm
, INTERCEPT_IRET
);
3344 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3345 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3346 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3350 static int invlpg_interception(struct vcpu_svm
*svm
)
3352 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3353 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3355 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3356 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3359 static int emulate_on_interception(struct vcpu_svm
*svm
)
3361 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3364 static int rdpmc_interception(struct vcpu_svm
*svm
)
3368 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3369 return emulate_on_interception(svm
);
3371 err
= kvm_rdpmc(&svm
->vcpu
);
3372 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3375 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3378 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3382 intercept
= svm
->nested
.intercept
;
3384 if (!is_guest_mode(&svm
->vcpu
) ||
3385 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3388 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3389 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3392 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3393 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3399 #define CR_VALID (1ULL << 63)
3401 static int cr_interception(struct vcpu_svm
*svm
)
3407 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3408 return emulate_on_interception(svm
);
3410 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3411 return emulate_on_interception(svm
);
3413 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3414 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3415 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3417 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3420 if (cr
>= 16) { /* mov to cr */
3422 val
= kvm_register_read(&svm
->vcpu
, reg
);
3425 if (!check_selective_cr0_intercepted(svm
, val
))
3426 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3432 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3435 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3438 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3441 WARN(1, "unhandled write to CR%d", cr
);
3442 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3445 } else { /* mov from cr */
3448 val
= kvm_read_cr0(&svm
->vcpu
);
3451 val
= svm
->vcpu
.arch
.cr2
;
3454 val
= kvm_read_cr3(&svm
->vcpu
);
3457 val
= kvm_read_cr4(&svm
->vcpu
);
3460 val
= kvm_get_cr8(&svm
->vcpu
);
3463 WARN(1, "unhandled read from CR%d", cr
);
3464 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3467 kvm_register_write(&svm
->vcpu
, reg
, val
);
3469 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3472 static int dr_interception(struct vcpu_svm
*svm
)
3477 if (svm
->vcpu
.guest_debug
== 0) {
3479 * No more DR vmexits; force a reload of the debug registers
3480 * and reenter on this instruction. The next vmexit will
3481 * retrieve the full state of the debug registers.
3483 clr_dr_intercepts(svm
);
3484 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3488 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3489 return emulate_on_interception(svm
);
3491 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3492 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3494 if (dr
>= 16) { /* mov to DRn */
3495 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3497 val
= kvm_register_read(&svm
->vcpu
, reg
);
3498 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3500 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3502 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3503 kvm_register_write(&svm
->vcpu
, reg
, val
);
3506 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3509 static int cr8_write_interception(struct vcpu_svm
*svm
)
3511 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3514 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3515 /* instruction emulation calls kvm_set_cr8() */
3516 r
= cr_interception(svm
);
3517 if (lapic_in_kernel(&svm
->vcpu
))
3519 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3521 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3525 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3527 struct vcpu_svm
*svm
= to_svm(vcpu
);
3529 switch (msr_info
->index
) {
3530 case MSR_IA32_TSC
: {
3531 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
3532 kvm_scale_tsc(vcpu
, rdtsc());
3537 msr_info
->data
= svm
->vmcb
->save
.star
;
3539 #ifdef CONFIG_X86_64
3541 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3544 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3546 case MSR_KERNEL_GS_BASE
:
3547 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3549 case MSR_SYSCALL_MASK
:
3550 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3553 case MSR_IA32_SYSENTER_CS
:
3554 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3556 case MSR_IA32_SYSENTER_EIP
:
3557 msr_info
->data
= svm
->sysenter_eip
;
3559 case MSR_IA32_SYSENTER_ESP
:
3560 msr_info
->data
= svm
->sysenter_esp
;
3563 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3565 msr_info
->data
= svm
->tsc_aux
;
3568 * Nobody will change the following 5 values in the VMCB so we can
3569 * safely return them on rdmsr. They will always be 0 until LBRV is
3572 case MSR_IA32_DEBUGCTLMSR
:
3573 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3575 case MSR_IA32_LASTBRANCHFROMIP
:
3576 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3578 case MSR_IA32_LASTBRANCHTOIP
:
3579 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3581 case MSR_IA32_LASTINTFROMIP
:
3582 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3584 case MSR_IA32_LASTINTTOIP
:
3585 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3587 case MSR_VM_HSAVE_PA
:
3588 msr_info
->data
= svm
->nested
.hsave_msr
;
3591 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3593 case MSR_IA32_UCODE_REV
:
3594 msr_info
->data
= 0x01000065;
3596 case MSR_F15H_IC_CFG
: {
3600 family
= guest_cpuid_family(vcpu
);
3601 model
= guest_cpuid_model(vcpu
);
3603 if (family
< 0 || model
< 0)
3604 return kvm_get_msr_common(vcpu
, msr_info
);
3608 if (family
== 0x15 &&
3609 (model
>= 0x2 && model
< 0x20))
3610 msr_info
->data
= 0x1E;
3614 return kvm_get_msr_common(vcpu
, msr_info
);
3619 static int rdmsr_interception(struct vcpu_svm
*svm
)
3621 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3622 struct msr_data msr_info
;
3624 msr_info
.index
= ecx
;
3625 msr_info
.host_initiated
= false;
3626 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3627 trace_kvm_msr_read_ex(ecx
);
3628 kvm_inject_gp(&svm
->vcpu
, 0);
3631 trace_kvm_msr_read(ecx
, msr_info
.data
);
3633 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3634 msr_info
.data
& 0xffffffff);
3635 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3636 msr_info
.data
>> 32);
3637 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3638 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3642 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3644 struct vcpu_svm
*svm
= to_svm(vcpu
);
3645 int svm_dis
, chg_mask
;
3647 if (data
& ~SVM_VM_CR_VALID_MASK
)
3650 chg_mask
= SVM_VM_CR_VALID_MASK
;
3652 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3653 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3655 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3656 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3658 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3660 /* check for svm_disable while efer.svme is set */
3661 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3667 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3669 struct vcpu_svm
*svm
= to_svm(vcpu
);
3671 u32 ecx
= msr
->index
;
3672 u64 data
= msr
->data
;
3675 kvm_write_tsc(vcpu
, msr
);
3678 svm
->vmcb
->save
.star
= data
;
3680 #ifdef CONFIG_X86_64
3682 svm
->vmcb
->save
.lstar
= data
;
3685 svm
->vmcb
->save
.cstar
= data
;
3687 case MSR_KERNEL_GS_BASE
:
3688 svm
->vmcb
->save
.kernel_gs_base
= data
;
3690 case MSR_SYSCALL_MASK
:
3691 svm
->vmcb
->save
.sfmask
= data
;
3694 case MSR_IA32_SYSENTER_CS
:
3695 svm
->vmcb
->save
.sysenter_cs
= data
;
3697 case MSR_IA32_SYSENTER_EIP
:
3698 svm
->sysenter_eip
= data
;
3699 svm
->vmcb
->save
.sysenter_eip
= data
;
3701 case MSR_IA32_SYSENTER_ESP
:
3702 svm
->sysenter_esp
= data
;
3703 svm
->vmcb
->save
.sysenter_esp
= data
;
3706 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3710 * This is rare, so we update the MSR here instead of using
3711 * direct_access_msrs. Doing that would require a rdmsr in
3714 svm
->tsc_aux
= data
;
3715 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
3717 case MSR_IA32_DEBUGCTLMSR
:
3718 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3719 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3723 if (data
& DEBUGCTL_RESERVED_BITS
)
3726 svm
->vmcb
->save
.dbgctl
= data
;
3727 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3728 if (data
& (1ULL<<0))
3729 svm_enable_lbrv(svm
);
3731 svm_disable_lbrv(svm
);
3733 case MSR_VM_HSAVE_PA
:
3734 svm
->nested
.hsave_msr
= data
;
3737 return svm_set_vm_cr(vcpu
, data
);
3739 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3741 case MSR_IA32_APICBASE
:
3742 if (kvm_vcpu_apicv_active(vcpu
))
3743 avic_update_vapic_bar(to_svm(vcpu
), data
);
3744 /* Follow through */
3746 return kvm_set_msr_common(vcpu
, msr
);
3751 static int wrmsr_interception(struct vcpu_svm
*svm
)
3753 struct msr_data msr
;
3754 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3755 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3759 msr
.host_initiated
= false;
3761 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3762 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3763 trace_kvm_msr_write_ex(ecx
, data
);
3764 kvm_inject_gp(&svm
->vcpu
, 0);
3767 trace_kvm_msr_write(ecx
, data
);
3768 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3772 static int msr_interception(struct vcpu_svm
*svm
)
3774 if (svm
->vmcb
->control
.exit_info_1
)
3775 return wrmsr_interception(svm
);
3777 return rdmsr_interception(svm
);
3780 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3782 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3783 svm_clear_vintr(svm
);
3784 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3785 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3786 ++svm
->vcpu
.stat
.irq_window_exits
;
3790 static int pause_interception(struct vcpu_svm
*svm
)
3792 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3793 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
3795 kvm_vcpu_on_spin(vcpu
, in_kernel
);
3799 static int nop_interception(struct vcpu_svm
*svm
)
3801 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
3804 static int monitor_interception(struct vcpu_svm
*svm
)
3806 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3807 return nop_interception(svm
);
3810 static int mwait_interception(struct vcpu_svm
*svm
)
3812 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3813 return nop_interception(svm
);
3816 enum avic_ipi_failure_cause
{
3817 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
3818 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
3819 AVIC_IPI_FAILURE_INVALID_TARGET
,
3820 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
3823 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
3825 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
3826 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
3827 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
3828 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
3829 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3831 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
3834 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
3836 * AVIC hardware handles the generation of
3837 * IPIs when the specified Message Type is Fixed
3838 * (also known as fixed delivery mode) and
3839 * the Trigger Mode is edge-triggered. The hardware
3840 * also supports self and broadcast delivery modes
3841 * specified via the Destination Shorthand(DSH)
3842 * field of the ICRL. Logical and physical APIC ID
3843 * formats are supported. All other IPI types cause
3844 * a #VMEXIT, which needs to emulated.
3846 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
3847 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
3849 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
3851 struct kvm_vcpu
*vcpu
;
3852 struct kvm
*kvm
= svm
->vcpu
.kvm
;
3853 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3856 * At this point, we expect that the AVIC HW has already
3857 * set the appropriate IRR bits on the valid target
3858 * vcpus. So, we just need to kick the appropriate vcpu.
3860 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
3861 bool m
= kvm_apic_match_dest(vcpu
, apic
,
3862 icrl
& KVM_APIC_SHORT_MASK
,
3863 GET_APIC_DEST_FIELD(icrh
),
3864 icrl
& KVM_APIC_DEST_MASK
);
3866 if (m
&& !avic_vcpu_is_running(vcpu
))
3867 kvm_vcpu_wake_up(vcpu
);
3871 case AVIC_IPI_FAILURE_INVALID_TARGET
:
3873 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
3874 WARN_ONCE(1, "Invalid backing page\n");
3877 pr_err("Unknown IPI interception\n");
3883 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
3885 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3887 u32
*logical_apic_id_table
;
3888 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
3893 if (flat
) { /* flat */
3894 index
= ffs(dlid
) - 1;
3897 } else { /* cluster */
3898 int cluster
= (dlid
& 0xf0) >> 4;
3899 int apic
= ffs(dlid
& 0x0f) - 1;
3901 if ((apic
< 0) || (apic
> 7) ||
3904 index
= (cluster
<< 2) + apic
;
3907 logical_apic_id_table
= (u32
*) page_address(vm_data
->avic_logical_id_table_page
);
3909 return &logical_apic_id_table
[index
];
3912 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
3916 u32
*entry
, new_entry
;
3918 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
3919 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
3923 new_entry
= READ_ONCE(*entry
);
3924 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
3925 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
3927 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3929 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3930 WRITE_ONCE(*entry
, new_entry
);
3935 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
3938 struct vcpu_svm
*svm
= to_svm(vcpu
);
3939 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
3944 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
3945 if (ret
&& svm
->ldr_reg
) {
3946 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
3954 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
3957 struct vcpu_svm
*svm
= to_svm(vcpu
);
3958 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
3959 u32 id
= (apic_id_reg
>> 24) & 0xff;
3961 if (vcpu
->vcpu_id
== id
)
3964 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
3965 new = avic_get_physical_id_entry(vcpu
, id
);
3969 /* We need to move physical_id_entry to new offset */
3972 to_svm(vcpu
)->avic_physical_id_cache
= new;
3975 * Also update the guest physical APIC ID in the logical
3976 * APIC ID table entry if already setup the LDR.
3979 avic_handle_ldr_update(vcpu
);
3984 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
3986 struct vcpu_svm
*svm
= to_svm(vcpu
);
3987 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3988 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
3989 u32 mod
= (dfr
>> 28) & 0xf;
3992 * We assume that all local APICs are using the same type.
3993 * If this changes, we need to flush the AVIC logical
3996 if (vm_data
->ldr_mode
== mod
)
3999 clear_page(page_address(vm_data
->avic_logical_id_table_page
));
4000 vm_data
->ldr_mode
= mod
;
4003 avic_handle_ldr_update(vcpu
);
4007 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4009 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4010 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4011 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4015 if (avic_handle_apic_id_update(&svm
->vcpu
))
4019 if (avic_handle_ldr_update(&svm
->vcpu
))
4023 avic_handle_dfr_update(&svm
->vcpu
);
4029 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4034 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4063 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4066 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4067 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4068 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4069 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4070 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4071 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4072 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4074 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4075 trap
, write
, vector
);
4078 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4079 ret
= avic_unaccel_trap_write(svm
);
4081 /* Handling Fault */
4082 ret
= (emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4088 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4089 [SVM_EXIT_READ_CR0
] = cr_interception
,
4090 [SVM_EXIT_READ_CR3
] = cr_interception
,
4091 [SVM_EXIT_READ_CR4
] = cr_interception
,
4092 [SVM_EXIT_READ_CR8
] = cr_interception
,
4093 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4094 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4095 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4096 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4097 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4098 [SVM_EXIT_READ_DR0
] = dr_interception
,
4099 [SVM_EXIT_READ_DR1
] = dr_interception
,
4100 [SVM_EXIT_READ_DR2
] = dr_interception
,
4101 [SVM_EXIT_READ_DR3
] = dr_interception
,
4102 [SVM_EXIT_READ_DR4
] = dr_interception
,
4103 [SVM_EXIT_READ_DR5
] = dr_interception
,
4104 [SVM_EXIT_READ_DR6
] = dr_interception
,
4105 [SVM_EXIT_READ_DR7
] = dr_interception
,
4106 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4107 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4108 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4109 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4110 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4111 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4112 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4113 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4114 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4115 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4116 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4117 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4118 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4119 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4120 [SVM_EXIT_INTR
] = intr_interception
,
4121 [SVM_EXIT_NMI
] = nmi_interception
,
4122 [SVM_EXIT_SMI
] = nop_on_interception
,
4123 [SVM_EXIT_INIT
] = nop_on_interception
,
4124 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4125 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4126 [SVM_EXIT_CPUID
] = cpuid_interception
,
4127 [SVM_EXIT_IRET
] = iret_interception
,
4128 [SVM_EXIT_INVD
] = emulate_on_interception
,
4129 [SVM_EXIT_PAUSE
] = pause_interception
,
4130 [SVM_EXIT_HLT
] = halt_interception
,
4131 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4132 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4133 [SVM_EXIT_IOIO
] = io_interception
,
4134 [SVM_EXIT_MSR
] = msr_interception
,
4135 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4136 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4137 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4138 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4139 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4140 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4141 [SVM_EXIT_STGI
] = stgi_interception
,
4142 [SVM_EXIT_CLGI
] = clgi_interception
,
4143 [SVM_EXIT_SKINIT
] = skinit_interception
,
4144 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4145 [SVM_EXIT_MONITOR
] = monitor_interception
,
4146 [SVM_EXIT_MWAIT
] = mwait_interception
,
4147 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4148 [SVM_EXIT_NPF
] = npf_interception
,
4149 [SVM_EXIT_RSM
] = emulate_on_interception
,
4150 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4151 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4154 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4156 struct vcpu_svm
*svm
= to_svm(vcpu
);
4157 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4158 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4160 pr_err("VMCB Control Area:\n");
4161 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4162 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4163 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4164 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4165 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4166 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4167 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4168 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4169 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4170 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4171 pr_err("%-20s%d\n", "asid:", control
->asid
);
4172 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4173 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4174 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4175 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4176 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4177 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4178 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4179 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4180 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4181 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4182 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4183 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4184 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4185 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4186 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4187 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4188 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4189 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4190 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4191 pr_err("VMCB State Save Area:\n");
4192 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4194 save
->es
.selector
, save
->es
.attrib
,
4195 save
->es
.limit
, save
->es
.base
);
4196 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4198 save
->cs
.selector
, save
->cs
.attrib
,
4199 save
->cs
.limit
, save
->cs
.base
);
4200 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4202 save
->ss
.selector
, save
->ss
.attrib
,
4203 save
->ss
.limit
, save
->ss
.base
);
4204 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4206 save
->ds
.selector
, save
->ds
.attrib
,
4207 save
->ds
.limit
, save
->ds
.base
);
4208 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4210 save
->fs
.selector
, save
->fs
.attrib
,
4211 save
->fs
.limit
, save
->fs
.base
);
4212 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4214 save
->gs
.selector
, save
->gs
.attrib
,
4215 save
->gs
.limit
, save
->gs
.base
);
4216 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4218 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4219 save
->gdtr
.limit
, save
->gdtr
.base
);
4220 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4222 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4223 save
->ldtr
.limit
, save
->ldtr
.base
);
4224 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4226 save
->idtr
.selector
, save
->idtr
.attrib
,
4227 save
->idtr
.limit
, save
->idtr
.base
);
4228 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4230 save
->tr
.selector
, save
->tr
.attrib
,
4231 save
->tr
.limit
, save
->tr
.base
);
4232 pr_err("cpl: %d efer: %016llx\n",
4233 save
->cpl
, save
->efer
);
4234 pr_err("%-15s %016llx %-13s %016llx\n",
4235 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4236 pr_err("%-15s %016llx %-13s %016llx\n",
4237 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4238 pr_err("%-15s %016llx %-13s %016llx\n",
4239 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4240 pr_err("%-15s %016llx %-13s %016llx\n",
4241 "rip:", save
->rip
, "rflags:", save
->rflags
);
4242 pr_err("%-15s %016llx %-13s %016llx\n",
4243 "rsp:", save
->rsp
, "rax:", save
->rax
);
4244 pr_err("%-15s %016llx %-13s %016llx\n",
4245 "star:", save
->star
, "lstar:", save
->lstar
);
4246 pr_err("%-15s %016llx %-13s %016llx\n",
4247 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4248 pr_err("%-15s %016llx %-13s %016llx\n",
4249 "kernel_gs_base:", save
->kernel_gs_base
,
4250 "sysenter_cs:", save
->sysenter_cs
);
4251 pr_err("%-15s %016llx %-13s %016llx\n",
4252 "sysenter_esp:", save
->sysenter_esp
,
4253 "sysenter_eip:", save
->sysenter_eip
);
4254 pr_err("%-15s %016llx %-13s %016llx\n",
4255 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4256 pr_err("%-15s %016llx %-13s %016llx\n",
4257 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4258 pr_err("%-15s %016llx %-13s %016llx\n",
4259 "excp_from:", save
->last_excp_from
,
4260 "excp_to:", save
->last_excp_to
);
4263 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4265 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4267 *info1
= control
->exit_info_1
;
4268 *info2
= control
->exit_info_2
;
4271 static int handle_exit(struct kvm_vcpu
*vcpu
)
4273 struct vcpu_svm
*svm
= to_svm(vcpu
);
4274 struct kvm_run
*kvm_run
= vcpu
->run
;
4275 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4277 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4279 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4280 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4282 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4284 if (unlikely(svm
->nested
.exit_required
)) {
4285 nested_svm_vmexit(svm
);
4286 svm
->nested
.exit_required
= false;
4291 if (is_guest_mode(vcpu
)) {
4294 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4295 svm
->vmcb
->control
.exit_info_1
,
4296 svm
->vmcb
->control
.exit_info_2
,
4297 svm
->vmcb
->control
.exit_int_info
,
4298 svm
->vmcb
->control
.exit_int_info_err
,
4301 vmexit
= nested_svm_exit_special(svm
);
4303 if (vmexit
== NESTED_EXIT_CONTINUE
)
4304 vmexit
= nested_svm_exit_handled(svm
);
4306 if (vmexit
== NESTED_EXIT_DONE
)
4310 svm_complete_interrupts(svm
);
4312 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4313 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4314 kvm_run
->fail_entry
.hardware_entry_failure_reason
4315 = svm
->vmcb
->control
.exit_code
;
4316 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4321 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4322 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4323 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4324 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4325 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4327 __func__
, svm
->vmcb
->control
.exit_int_info
,
4330 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4331 || !svm_exit_handlers
[exit_code
]) {
4332 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4333 kvm_queue_exception(vcpu
, UD_VECTOR
);
4337 return svm_exit_handlers
[exit_code
](svm
);
4340 static void reload_tss(struct kvm_vcpu
*vcpu
)
4342 int cpu
= raw_smp_processor_id();
4344 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4345 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4349 static void pre_svm_run(struct vcpu_svm
*svm
)
4351 int cpu
= raw_smp_processor_id();
4353 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4355 /* FIXME: handle wraparound of asid_generation */
4356 if (svm
->asid_generation
!= sd
->asid_generation
)
4360 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
4362 struct vcpu_svm
*svm
= to_svm(vcpu
);
4364 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
4365 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
4366 set_intercept(svm
, INTERCEPT_IRET
);
4367 ++vcpu
->stat
.nmi_injections
;
4370 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
4372 struct vmcb_control_area
*control
;
4374 /* The following fields are ignored when AVIC is enabled */
4375 control
= &svm
->vmcb
->control
;
4376 control
->int_vector
= irq
;
4377 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
4378 control
->int_ctl
|= V_IRQ_MASK
|
4379 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
4380 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4383 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
4385 struct vcpu_svm
*svm
= to_svm(vcpu
);
4387 BUG_ON(!(gif_set(svm
)));
4389 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
4390 ++vcpu
->stat
.irq_injections
;
4392 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
4393 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
4396 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
4398 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
4401 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
4403 struct vcpu_svm
*svm
= to_svm(vcpu
);
4405 if (svm_nested_virtualize_tpr(vcpu
) ||
4406 kvm_vcpu_apicv_active(vcpu
))
4409 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4415 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4418 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
4423 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
4425 return avic
&& irqchip_split(vcpu
->kvm
);
4428 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
4432 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
4436 /* Note: Currently only used by Hyper-V. */
4437 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4439 struct vcpu_svm
*svm
= to_svm(vcpu
);
4440 struct vmcb
*vmcb
= svm
->vmcb
;
4442 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
4445 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
4446 mark_dirty(vmcb
, VMCB_INTR
);
4449 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
4454 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
4456 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
4457 smp_mb__after_atomic();
4459 if (avic_vcpu_is_running(vcpu
))
4460 wrmsrl(SVM_AVIC_DOORBELL
,
4461 kvm_cpu_get_apicid(vcpu
->cpu
));
4463 kvm_vcpu_wake_up(vcpu
);
4466 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4468 unsigned long flags
;
4469 struct amd_svm_iommu_ir
*cur
;
4471 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4472 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
4473 if (cur
->data
!= pi
->ir_data
)
4475 list_del(&cur
->node
);
4479 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4482 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4485 unsigned long flags
;
4486 struct amd_svm_iommu_ir
*ir
;
4489 * In some cases, the existing irte is updaed and re-set,
4490 * so we need to check here if it's already been * added
4493 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
4494 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4495 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
4496 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
4497 struct vcpu_svm
*prev_svm
;
4504 prev_svm
= to_svm(prev_vcpu
);
4505 svm_ir_list_del(prev_svm
, pi
);
4509 * Allocating new amd_iommu_pi_data, which will get
4510 * add to the per-vcpu ir_list.
4512 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
4517 ir
->data
= pi
->ir_data
;
4519 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4520 list_add(&ir
->node
, &svm
->ir_list
);
4521 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4528 * The HW cannot support posting multicast/broadcast
4529 * interrupts to a vCPU. So, we still use legacy interrupt
4530 * remapping for these kind of interrupts.
4532 * For lowest-priority interrupts, we only support
4533 * those with single CPU as the destination, e.g. user
4534 * configures the interrupts via /proc/irq or uses
4535 * irqbalance to make the interrupts single-CPU.
4538 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
4539 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
4541 struct kvm_lapic_irq irq
;
4542 struct kvm_vcpu
*vcpu
= NULL
;
4544 kvm_set_msi_irq(kvm
, e
, &irq
);
4546 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
4547 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4548 __func__
, irq
.vector
);
4552 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
4554 *svm
= to_svm(vcpu
);
4555 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
4556 vcpu_info
->vector
= irq
.vector
;
4562 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4565 * @host_irq: host irq of the interrupt
4566 * @guest_irq: gsi of the interrupt
4567 * @set: set or unset PI
4568 * returns 0 on success, < 0 on failure
4570 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
4571 uint32_t guest_irq
, bool set
)
4573 struct kvm_kernel_irq_routing_entry
*e
;
4574 struct kvm_irq_routing_table
*irq_rt
;
4575 int idx
, ret
= -EINVAL
;
4577 if (!kvm_arch_has_assigned_device(kvm
) ||
4578 !irq_remapping_cap(IRQ_POSTING_CAP
))
4581 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4582 __func__
, host_irq
, guest_irq
, set
);
4584 idx
= srcu_read_lock(&kvm
->irq_srcu
);
4585 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
4586 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
4588 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
4589 struct vcpu_data vcpu_info
;
4590 struct vcpu_svm
*svm
= NULL
;
4592 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
4596 * Here, we setup with legacy mode in the following cases:
4597 * 1. When cannot target interrupt to a specific vcpu.
4598 * 2. Unsetting posted interrupt.
4599 * 3. APIC virtialization is disabled for the vcpu.
4601 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
4602 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
4603 struct amd_iommu_pi_data pi
;
4605 /* Try to enable guest_mode in IRTE */
4606 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
4608 pi
.ga_tag
= AVIC_GATAG(kvm
->arch
.avic_vm_id
,
4610 pi
.is_guest_mode
= true;
4611 pi
.vcpu_data
= &vcpu_info
;
4612 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4615 * Here, we successfully setting up vcpu affinity in
4616 * IOMMU guest mode. Now, we need to store the posted
4617 * interrupt information in a per-vcpu ir_list so that
4618 * we can reference to them directly when we update vcpu
4619 * scheduling information in IOMMU irte.
4621 if (!ret
&& pi
.is_guest_mode
)
4622 svm_ir_list_add(svm
, &pi
);
4624 /* Use legacy mode in IRTE */
4625 struct amd_iommu_pi_data pi
;
4628 * Here, pi is used to:
4629 * - Tell IOMMU to use legacy mode for this interrupt.
4630 * - Retrieve ga_tag of prior interrupt remapping data.
4632 pi
.is_guest_mode
= false;
4633 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4636 * Check if the posted interrupt was previously
4637 * setup with the guest_mode by checking if the ga_tag
4638 * was cached. If so, we need to clean up the per-vcpu
4641 if (!ret
&& pi
.prev_ga_tag
) {
4642 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
4643 struct kvm_vcpu
*vcpu
;
4645 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
4647 svm_ir_list_del(to_svm(vcpu
), &pi
);
4652 trace_kvm_pi_irte_update(svm
->vcpu
.vcpu_id
,
4655 vcpu_info
.pi_desc_addr
, set
);
4659 pr_err("%s: failed to update PI IRTE\n", __func__
);
4666 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
4670 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
4672 struct vcpu_svm
*svm
= to_svm(vcpu
);
4673 struct vmcb
*vmcb
= svm
->vmcb
;
4675 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
4676 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4677 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
4682 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4684 struct vcpu_svm
*svm
= to_svm(vcpu
);
4686 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4689 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4691 struct vcpu_svm
*svm
= to_svm(vcpu
);
4694 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
4695 set_intercept(svm
, INTERCEPT_IRET
);
4697 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
4698 clr_intercept(svm
, INTERCEPT_IRET
);
4702 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4704 struct vcpu_svm
*svm
= to_svm(vcpu
);
4705 struct vmcb
*vmcb
= svm
->vmcb
;
4708 if (!gif_set(svm
) ||
4709 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
4712 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
4714 if (is_guest_mode(vcpu
))
4715 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
4720 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4722 struct vcpu_svm
*svm
= to_svm(vcpu
);
4724 if (kvm_vcpu_apicv_active(vcpu
))
4728 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4729 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4730 * get that intercept, this function will be called again though and
4731 * we'll get the vintr intercept. However, if the vGIF feature is
4732 * enabled, the STGI interception will not occur. Enable the irq
4733 * window under the assumption that the hardware will set the GIF.
4735 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
4737 svm_inject_irq(svm
, 0x0);
4741 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4743 struct vcpu_svm
*svm
= to_svm(vcpu
);
4745 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
4747 return; /* IRET will cause a vm exit */
4749 if (!gif_set(svm
)) {
4750 if (vgif_enabled(svm
))
4751 set_intercept(svm
, INTERCEPT_STGI
);
4752 return; /* STGI will cause a vm exit */
4755 if (svm
->nested
.exit_required
)
4756 return; /* we're not going to run the guest yet */
4759 * Something prevents NMI from been injected. Single step over possible
4760 * problem (IRET or exception injection or interrupt shadow)
4762 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
4763 svm
->nmi_singlestep
= true;
4764 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
4767 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4772 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
4774 struct vcpu_svm
*svm
= to_svm(vcpu
);
4776 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
4777 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4779 svm
->asid_generation
--;
4782 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
4786 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
4788 struct vcpu_svm
*svm
= to_svm(vcpu
);
4790 if (svm_nested_virtualize_tpr(vcpu
))
4793 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
4794 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
4795 kvm_set_cr8(vcpu
, cr8
);
4799 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
4801 struct vcpu_svm
*svm
= to_svm(vcpu
);
4804 if (svm_nested_virtualize_tpr(vcpu
) ||
4805 kvm_vcpu_apicv_active(vcpu
))
4808 cr8
= kvm_get_cr8(vcpu
);
4809 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
4810 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
4813 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
4817 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
4818 unsigned int3_injected
= svm
->int3_injected
;
4820 svm
->int3_injected
= 0;
4823 * If we've made progress since setting HF_IRET_MASK, we've
4824 * executed an IRET and can allow NMI injection.
4826 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
4827 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
4828 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
4829 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4832 svm
->vcpu
.arch
.nmi_injected
= false;
4833 kvm_clear_exception_queue(&svm
->vcpu
);
4834 kvm_clear_interrupt_queue(&svm
->vcpu
);
4836 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
4839 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4841 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
4842 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
4845 case SVM_EXITINTINFO_TYPE_NMI
:
4846 svm
->vcpu
.arch
.nmi_injected
= true;
4848 case SVM_EXITINTINFO_TYPE_EXEPT
:
4850 * In case of software exceptions, do not reinject the vector,
4851 * but re-execute the instruction instead. Rewind RIP first
4852 * if we emulated INT3 before.
4854 if (kvm_exception_is_soft(vector
)) {
4855 if (vector
== BP_VECTOR
&& int3_injected
&&
4856 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
4857 kvm_rip_write(&svm
->vcpu
,
4858 kvm_rip_read(&svm
->vcpu
) -
4862 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
4863 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
4864 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
4867 kvm_requeue_exception(&svm
->vcpu
, vector
);
4869 case SVM_EXITINTINFO_TYPE_INTR
:
4870 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
4877 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
4879 struct vcpu_svm
*svm
= to_svm(vcpu
);
4880 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4882 control
->exit_int_info
= control
->event_inj
;
4883 control
->exit_int_info_err
= control
->event_inj_err
;
4884 control
->event_inj
= 0;
4885 svm_complete_interrupts(svm
);
4888 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
4890 struct vcpu_svm
*svm
= to_svm(vcpu
);
4892 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
4893 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
4894 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
4897 * A vmexit emulation is required before the vcpu can be executed
4900 if (unlikely(svm
->nested
.exit_required
))
4904 * Disable singlestep if we're injecting an interrupt/exception.
4905 * We don't want our modified rflags to be pushed on the stack where
4906 * we might not be able to easily reset them if we disabled NMI
4909 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
4911 * Event injection happens before external interrupts cause a
4912 * vmexit and interrupts are disabled here, so smp_send_reschedule
4913 * is enough to force an immediate vmexit.
4915 disable_nmi_singlestep(svm
);
4916 smp_send_reschedule(vcpu
->cpu
);
4921 sync_lapic_to_cr8(vcpu
);
4923 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
4930 "push %%" _ASM_BP
"; \n\t"
4931 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
4932 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
4933 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
4934 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
4935 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
4936 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
4937 #ifdef CONFIG_X86_64
4938 "mov %c[r8](%[svm]), %%r8 \n\t"
4939 "mov %c[r9](%[svm]), %%r9 \n\t"
4940 "mov %c[r10](%[svm]), %%r10 \n\t"
4941 "mov %c[r11](%[svm]), %%r11 \n\t"
4942 "mov %c[r12](%[svm]), %%r12 \n\t"
4943 "mov %c[r13](%[svm]), %%r13 \n\t"
4944 "mov %c[r14](%[svm]), %%r14 \n\t"
4945 "mov %c[r15](%[svm]), %%r15 \n\t"
4948 /* Enter guest mode */
4949 "push %%" _ASM_AX
" \n\t"
4950 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
4951 __ex(SVM_VMLOAD
) "\n\t"
4952 __ex(SVM_VMRUN
) "\n\t"
4953 __ex(SVM_VMSAVE
) "\n\t"
4954 "pop %%" _ASM_AX
" \n\t"
4956 /* Save guest registers, load host registers */
4957 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
4958 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
4959 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
4960 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
4961 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
4962 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
4963 #ifdef CONFIG_X86_64
4964 "mov %%r8, %c[r8](%[svm]) \n\t"
4965 "mov %%r9, %c[r9](%[svm]) \n\t"
4966 "mov %%r10, %c[r10](%[svm]) \n\t"
4967 "mov %%r11, %c[r11](%[svm]) \n\t"
4968 "mov %%r12, %c[r12](%[svm]) \n\t"
4969 "mov %%r13, %c[r13](%[svm]) \n\t"
4970 "mov %%r14, %c[r14](%[svm]) \n\t"
4971 "mov %%r15, %c[r15](%[svm]) \n\t"
4976 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
4977 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4978 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4979 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4980 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4981 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4982 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
4983 #ifdef CONFIG_X86_64
4984 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4985 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4986 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4987 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4988 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4989 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4990 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4991 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
4994 #ifdef CONFIG_X86_64
4995 , "rbx", "rcx", "rdx", "rsi", "rdi"
4996 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4998 , "ebx", "ecx", "edx", "esi", "edi"
5002 #ifdef CONFIG_X86_64
5003 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5005 loadsegment(fs
, svm
->host
.fs
);
5006 #ifndef CONFIG_X86_32_LAZY_GS
5007 loadsegment(gs
, svm
->host
.gs
);
5013 local_irq_disable();
5015 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5016 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5017 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5018 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5020 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5021 kvm_before_handle_nmi(&svm
->vcpu
);
5025 /* Any pending NMI will happen here */
5027 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5028 kvm_after_handle_nmi(&svm
->vcpu
);
5030 sync_cr8_to_lapic(vcpu
);
5034 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5036 /* if exit due to PF check for async PF */
5037 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5038 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5041 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5042 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5046 * We need to handle MC intercepts here before the vcpu has a chance to
5047 * change the physical cpu
5049 if (unlikely(svm
->vmcb
->control
.exit_code
==
5050 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5051 svm_handle_mce(svm
);
5053 mark_all_clean(svm
->vmcb
);
5055 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5057 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5059 struct vcpu_svm
*svm
= to_svm(vcpu
);
5061 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5062 mark_dirty(svm
->vmcb
, VMCB_CR
);
5063 svm_flush_tlb(vcpu
);
5066 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5068 struct vcpu_svm
*svm
= to_svm(vcpu
);
5070 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5071 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5073 /* Also sync guest cr3 here in case we live migrate */
5074 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5075 mark_dirty(svm
->vmcb
, VMCB_CR
);
5077 svm_flush_tlb(vcpu
);
5080 static int is_disabled(void)
5084 rdmsrl(MSR_VM_CR
, vm_cr
);
5085 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5092 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5095 * Patch in the VMMCALL instruction:
5097 hypercall
[0] = 0x0f;
5098 hypercall
[1] = 0x01;
5099 hypercall
[2] = 0xd9;
5102 static void svm_check_processor_compat(void *rtn
)
5107 static bool svm_cpu_has_accelerated_tpr(void)
5112 static bool svm_has_high_real_mode_segbase(void)
5117 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5122 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5124 struct vcpu_svm
*svm
= to_svm(vcpu
);
5126 /* Update nrips enabled cache */
5127 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5129 if (!kvm_vcpu_apicv_active(vcpu
))
5132 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5135 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5140 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5144 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5147 entry
->eax
= 1; /* SVM revision 1 */
5148 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5149 ASID emulation to nested SVM */
5150 entry
->ecx
= 0; /* Reserved */
5151 entry
->edx
= 0; /* Per default do not support any
5152 additional features */
5154 /* Support next_rip if host supports it */
5155 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5156 entry
->edx
|= SVM_FEATURE_NRIP
;
5158 /* Support NPT for the guest if enabled */
5160 entry
->edx
|= SVM_FEATURE_NPT
;
5166 static int svm_get_lpage_level(void)
5168 return PT_PDPE_LEVEL
;
5171 static bool svm_rdtscp_supported(void)
5173 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5176 static bool svm_invpcid_supported(void)
5181 static bool svm_mpx_supported(void)
5186 static bool svm_xsaves_supported(void)
5191 static bool svm_has_wbinvd_exit(void)
5196 #define PRE_EX(exit) { .exit_code = (exit), \
5197 .stage = X86_ICPT_PRE_EXCEPT, }
5198 #define POST_EX(exit) { .exit_code = (exit), \
5199 .stage = X86_ICPT_POST_EXCEPT, }
5200 #define POST_MEM(exit) { .exit_code = (exit), \
5201 .stage = X86_ICPT_POST_MEMACCESS, }
5203 static const struct __x86_intercept
{
5205 enum x86_intercept_stage stage
;
5206 } x86_intercept_map
[] = {
5207 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5208 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5209 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5210 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5211 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5212 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5213 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5214 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5215 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5216 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5217 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5218 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5219 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5220 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5221 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5222 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5223 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5224 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5225 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5226 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5227 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5228 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5229 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5230 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5231 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5232 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5233 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5234 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5235 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5236 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5237 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5238 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5239 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5240 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5241 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5242 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5243 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5244 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5245 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5246 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5247 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5248 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5249 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5250 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5251 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5252 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5259 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5260 struct x86_instruction_info
*info
,
5261 enum x86_intercept_stage stage
)
5263 struct vcpu_svm
*svm
= to_svm(vcpu
);
5264 int vmexit
, ret
= X86EMUL_CONTINUE
;
5265 struct __x86_intercept icpt_info
;
5266 struct vmcb
*vmcb
= svm
->vmcb
;
5268 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5271 icpt_info
= x86_intercept_map
[info
->intercept
];
5273 if (stage
!= icpt_info
.stage
)
5276 switch (icpt_info
.exit_code
) {
5277 case SVM_EXIT_READ_CR0
:
5278 if (info
->intercept
== x86_intercept_cr_read
)
5279 icpt_info
.exit_code
+= info
->modrm_reg
;
5281 case SVM_EXIT_WRITE_CR0
: {
5282 unsigned long cr0
, val
;
5285 if (info
->intercept
== x86_intercept_cr_write
)
5286 icpt_info
.exit_code
+= info
->modrm_reg
;
5288 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
5289 info
->intercept
== x86_intercept_clts
)
5292 intercept
= svm
->nested
.intercept
;
5294 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
5297 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
5298 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
5300 if (info
->intercept
== x86_intercept_lmsw
) {
5303 /* lmsw can't clear PE - catch this here */
5304 if (cr0
& X86_CR0_PE
)
5309 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
5313 case SVM_EXIT_READ_DR0
:
5314 case SVM_EXIT_WRITE_DR0
:
5315 icpt_info
.exit_code
+= info
->modrm_reg
;
5318 if (info
->intercept
== x86_intercept_wrmsr
)
5319 vmcb
->control
.exit_info_1
= 1;
5321 vmcb
->control
.exit_info_1
= 0;
5323 case SVM_EXIT_PAUSE
:
5325 * We get this for NOP only, but pause
5326 * is rep not, check this here
5328 if (info
->rep_prefix
!= REPE_PREFIX
)
5331 case SVM_EXIT_IOIO
: {
5335 if (info
->intercept
== x86_intercept_in
||
5336 info
->intercept
== x86_intercept_ins
) {
5337 exit_info
= ((info
->src_val
& 0xffff) << 16) |
5339 bytes
= info
->dst_bytes
;
5341 exit_info
= (info
->dst_val
& 0xffff) << 16;
5342 bytes
= info
->src_bytes
;
5345 if (info
->intercept
== x86_intercept_outs
||
5346 info
->intercept
== x86_intercept_ins
)
5347 exit_info
|= SVM_IOIO_STR_MASK
;
5349 if (info
->rep_prefix
)
5350 exit_info
|= SVM_IOIO_REP_MASK
;
5352 bytes
= min(bytes
, 4u);
5354 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
5356 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
5358 vmcb
->control
.exit_info_1
= exit_info
;
5359 vmcb
->control
.exit_info_2
= info
->next_rip
;
5367 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5368 if (static_cpu_has(X86_FEATURE_NRIPS
))
5369 vmcb
->control
.next_rip
= info
->next_rip
;
5370 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
5371 vmexit
= nested_svm_exit_handled(svm
);
5373 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
5380 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
5384 * We must have an instruction with interrupts enabled, so
5385 * the timer interrupt isn't delayed by the interrupt shadow.
5388 local_irq_disable();
5391 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
5395 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
5397 if (avic_handle_apic_id_update(vcpu
) != 0)
5399 if (avic_handle_dfr_update(vcpu
) != 0)
5401 avic_handle_ldr_update(vcpu
);
5404 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
5406 /* [63:9] are reserved. */
5407 vcpu
->arch
.mcg_cap
&= 0x1ff;
5410 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
5412 struct vcpu_svm
*svm
= to_svm(vcpu
);
5414 /* Per APM Vol.2 15.22.2 "Response to SMI" */
5418 if (is_guest_mode(&svm
->vcpu
) &&
5419 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
5420 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
5421 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
5422 svm
->nested
.exit_required
= true;
5429 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
5431 struct vcpu_svm
*svm
= to_svm(vcpu
);
5434 if (is_guest_mode(vcpu
)) {
5435 /* FED8h - SVM Guest */
5436 put_smstate(u64
, smstate
, 0x7ed8, 1);
5437 /* FEE0h - SVM Guest VMCB Physical Address */
5438 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
5440 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5441 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5442 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5444 ret
= nested_svm_vmexit(svm
);
5451 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
5453 struct vcpu_svm
*svm
= to_svm(vcpu
);
5454 struct vmcb
*nested_vmcb
;
5462 ret
= kvm_vcpu_read_guest(vcpu
, smbase
+ 0xfed8, &svm_state_save
,
5463 sizeof(svm_state_save
));
5467 if (svm_state_save
.guest
) {
5468 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
5469 nested_vmcb
= nested_svm_map(svm
, svm_state_save
.vmcb
, &page
);
5471 enter_svm_guest_mode(svm
, svm_state_save
.vmcb
, nested_vmcb
, page
);
5474 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
5479 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
5481 struct vcpu_svm
*svm
= to_svm(vcpu
);
5483 if (!gif_set(svm
)) {
5484 if (vgif_enabled(svm
))
5485 set_intercept(svm
, INTERCEPT_STGI
);
5486 /* STGI will cause a vm exit */
5492 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
5493 .cpu_has_kvm_support
= has_svm
,
5494 .disabled_by_bios
= is_disabled
,
5495 .hardware_setup
= svm_hardware_setup
,
5496 .hardware_unsetup
= svm_hardware_unsetup
,
5497 .check_processor_compatibility
= svm_check_processor_compat
,
5498 .hardware_enable
= svm_hardware_enable
,
5499 .hardware_disable
= svm_hardware_disable
,
5500 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
5501 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
5503 .vcpu_create
= svm_create_vcpu
,
5504 .vcpu_free
= svm_free_vcpu
,
5505 .vcpu_reset
= svm_vcpu_reset
,
5507 .vm_init
= avic_vm_init
,
5508 .vm_destroy
= avic_vm_destroy
,
5510 .prepare_guest_switch
= svm_prepare_guest_switch
,
5511 .vcpu_load
= svm_vcpu_load
,
5512 .vcpu_put
= svm_vcpu_put
,
5513 .vcpu_blocking
= svm_vcpu_blocking
,
5514 .vcpu_unblocking
= svm_vcpu_unblocking
,
5516 .update_bp_intercept
= update_bp_intercept
,
5517 .get_msr
= svm_get_msr
,
5518 .set_msr
= svm_set_msr
,
5519 .get_segment_base
= svm_get_segment_base
,
5520 .get_segment
= svm_get_segment
,
5521 .set_segment
= svm_set_segment
,
5522 .get_cpl
= svm_get_cpl
,
5523 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
5524 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
5525 .decache_cr3
= svm_decache_cr3
,
5526 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
5527 .set_cr0
= svm_set_cr0
,
5528 .set_cr3
= svm_set_cr3
,
5529 .set_cr4
= svm_set_cr4
,
5530 .set_efer
= svm_set_efer
,
5531 .get_idt
= svm_get_idt
,
5532 .set_idt
= svm_set_idt
,
5533 .get_gdt
= svm_get_gdt
,
5534 .set_gdt
= svm_set_gdt
,
5535 .get_dr6
= svm_get_dr6
,
5536 .set_dr6
= svm_set_dr6
,
5537 .set_dr7
= svm_set_dr7
,
5538 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
5539 .cache_reg
= svm_cache_reg
,
5540 .get_rflags
= svm_get_rflags
,
5541 .set_rflags
= svm_set_rflags
,
5543 .tlb_flush
= svm_flush_tlb
,
5545 .run
= svm_vcpu_run
,
5546 .handle_exit
= handle_exit
,
5547 .skip_emulated_instruction
= skip_emulated_instruction
,
5548 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
5549 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
5550 .patch_hypercall
= svm_patch_hypercall
,
5551 .set_irq
= svm_set_irq
,
5552 .set_nmi
= svm_inject_nmi
,
5553 .queue_exception
= svm_queue_exception
,
5554 .cancel_injection
= svm_cancel_injection
,
5555 .interrupt_allowed
= svm_interrupt_allowed
,
5556 .nmi_allowed
= svm_nmi_allowed
,
5557 .get_nmi_mask
= svm_get_nmi_mask
,
5558 .set_nmi_mask
= svm_set_nmi_mask
,
5559 .enable_nmi_window
= enable_nmi_window
,
5560 .enable_irq_window
= enable_irq_window
,
5561 .update_cr8_intercept
= update_cr8_intercept
,
5562 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
5563 .get_enable_apicv
= svm_get_enable_apicv
,
5564 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
5565 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
5566 .hwapic_irr_update
= svm_hwapic_irr_update
,
5567 .hwapic_isr_update
= svm_hwapic_isr_update
,
5568 .apicv_post_state_restore
= avic_post_state_restore
,
5570 .set_tss_addr
= svm_set_tss_addr
,
5571 .get_tdp_level
= get_npt_level
,
5572 .get_mt_mask
= svm_get_mt_mask
,
5574 .get_exit_info
= svm_get_exit_info
,
5576 .get_lpage_level
= svm_get_lpage_level
,
5578 .cpuid_update
= svm_cpuid_update
,
5580 .rdtscp_supported
= svm_rdtscp_supported
,
5581 .invpcid_supported
= svm_invpcid_supported
,
5582 .mpx_supported
= svm_mpx_supported
,
5583 .xsaves_supported
= svm_xsaves_supported
,
5585 .set_supported_cpuid
= svm_set_supported_cpuid
,
5587 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
5589 .write_tsc_offset
= svm_write_tsc_offset
,
5591 .set_tdp_cr3
= set_tdp_cr3
,
5593 .check_intercept
= svm_check_intercept
,
5594 .handle_external_intr
= svm_handle_external_intr
,
5596 .sched_in
= svm_sched_in
,
5598 .pmu_ops
= &amd_pmu_ops
,
5599 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
5600 .update_pi_irte
= svm_update_pi_irte
,
5601 .setup_mce
= svm_setup_mce
,
5603 .smi_allowed
= svm_smi_allowed
,
5604 .pre_enter_smm
= svm_pre_enter_smm
,
5605 .pre_leave_smm
= svm_pre_leave_smm
,
5606 .enable_smi_window
= enable_smi_window
,
5609 static int __init
svm_init(void)
5611 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
5612 __alignof__(struct vcpu_svm
), THIS_MODULE
);
5615 static void __exit
svm_exit(void)
5620 module_init(svm_init
)
5621 module_exit(svm_exit
)