2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/mod_devicetable.h>
26 #include <linux/kernel.h>
27 #include <linux/vmalloc.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/ftrace_event.h>
31 #include <linux/slab.h>
33 #include <asm/perf_event.h>
34 #include <asm/tlbflush.h>
36 #include <asm/kvm_para.h>
38 #include <asm/virtext.h>
41 #define __ex(x) __kvm_handle_fault_on_reboot(x)
43 MODULE_AUTHOR("Qumranet");
44 MODULE_LICENSE("GPL");
46 static const struct x86_cpu_id svm_cpu_id
[] = {
47 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
50 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
52 #define IOPM_ALLOC_ORDER 2
53 #define MSRPM_ALLOC_ORDER 1
55 #define SEG_TYPE_LDT 2
56 #define SEG_TYPE_BUSY_TSS16 3
58 #define SVM_FEATURE_NPT (1 << 0)
59 #define SVM_FEATURE_LBRV (1 << 1)
60 #define SVM_FEATURE_SVML (1 << 2)
61 #define SVM_FEATURE_NRIP (1 << 3)
62 #define SVM_FEATURE_TSC_RATE (1 << 4)
63 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
64 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
65 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
66 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
68 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
69 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
70 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly
;
80 static const u32 host_save_user_msrs
[] = {
82 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
85 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
88 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
98 /* These are the merged vectors */
101 /* gpa pointers to the real vectors */
105 /* A VMEXIT is required but not yet emulated */
108 /* cache for intercepts of the guest */
111 u32 intercept_exceptions
;
114 /* Nested Paging related state */
118 #define MSRPM_OFFSETS 16
119 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
122 * Set osvw_len to higher value when updated Revision Guides
123 * are published and we know what the new status bits are
125 static uint64_t osvw_len
= 4, osvw_status
;
128 struct kvm_vcpu vcpu
;
130 unsigned long vmcb_pa
;
131 struct svm_cpu_data
*svm_data
;
132 uint64_t asid_generation
;
133 uint64_t sysenter_esp
;
134 uint64_t sysenter_eip
;
138 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
150 struct nested_state nested
;
154 unsigned int3_injected
;
155 unsigned long int3_rip
;
161 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
162 #define TSC_RATIO_DEFAULT 0x0100000000ULL
164 #define MSR_INVALID 0xffffffffU
166 static struct svm_direct_access_msrs
{
167 u32 index
; /* Index of the MSR */
168 bool always
; /* True if intercept is always on */
169 } direct_access_msrs
[] = {
170 { .index
= MSR_STAR
, .always
= true },
171 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
173 { .index
= MSR_GS_BASE
, .always
= true },
174 { .index
= MSR_FS_BASE
, .always
= true },
175 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
176 { .index
= MSR_LSTAR
, .always
= true },
177 { .index
= MSR_CSTAR
, .always
= true },
178 { .index
= MSR_SYSCALL_MASK
, .always
= true },
180 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
181 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
182 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
183 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
184 { .index
= MSR_INVALID
, .always
= false },
187 /* enable NPT for AMD64 and X86 with PAE */
188 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
189 static bool npt_enabled
= true;
191 static bool npt_enabled
;
194 /* allow nested paging (virtualized MMU) for all guests */
195 static int npt
= true;
196 module_param(npt
, int, S_IRUGO
);
198 /* allow nested virtualization in KVM/SVM */
199 static int nested
= true;
200 module_param(nested
, int, S_IRUGO
);
202 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
203 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
205 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
206 static int nested_svm_intercept(struct vcpu_svm
*svm
);
207 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
208 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
209 bool has_error_code
, u32 error_code
);
210 static u64
__scale_tsc(u64 ratio
, u64 tsc
);
213 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
214 pause filter count */
215 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
216 VMCB_ASID
, /* ASID */
217 VMCB_INTR
, /* int_ctl, int_vector */
218 VMCB_NPT
, /* npt_en, nCR3, gPAT */
219 VMCB_CR
, /* CR0, CR3, CR4, EFER */
220 VMCB_DR
, /* DR6, DR7 */
221 VMCB_DT
, /* GDT, IDT */
222 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
223 VMCB_CR2
, /* CR2 only */
224 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
228 /* TPR and CR2 are always written before VMRUN */
229 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
231 static inline void mark_all_dirty(struct vmcb
*vmcb
)
233 vmcb
->control
.clean
= 0;
236 static inline void mark_all_clean(struct vmcb
*vmcb
)
238 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
239 & ~VMCB_ALWAYS_DIRTY_MASK
;
242 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
244 vmcb
->control
.clean
&= ~(1 << bit
);
247 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
249 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
252 static void recalc_intercepts(struct vcpu_svm
*svm
)
254 struct vmcb_control_area
*c
, *h
;
255 struct nested_state
*g
;
257 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
259 if (!is_guest_mode(&svm
->vcpu
))
262 c
= &svm
->vmcb
->control
;
263 h
= &svm
->nested
.hsave
->control
;
266 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
267 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
268 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
269 c
->intercept
= h
->intercept
| g
->intercept
;
272 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
274 if (is_guest_mode(&svm
->vcpu
))
275 return svm
->nested
.hsave
;
280 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
282 struct vmcb
*vmcb
= get_host_vmcb(svm
);
284 vmcb
->control
.intercept_cr
|= (1U << bit
);
286 recalc_intercepts(svm
);
289 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
291 struct vmcb
*vmcb
= get_host_vmcb(svm
);
293 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
295 recalc_intercepts(svm
);
298 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
300 struct vmcb
*vmcb
= get_host_vmcb(svm
);
302 return vmcb
->control
.intercept_cr
& (1U << bit
);
305 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
307 struct vmcb
*vmcb
= get_host_vmcb(svm
);
309 vmcb
->control
.intercept_dr
|= (1U << bit
);
311 recalc_intercepts(svm
);
314 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
316 struct vmcb
*vmcb
= get_host_vmcb(svm
);
318 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
320 recalc_intercepts(svm
);
323 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
325 struct vmcb
*vmcb
= get_host_vmcb(svm
);
327 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
329 recalc_intercepts(svm
);
332 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
334 struct vmcb
*vmcb
= get_host_vmcb(svm
);
336 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
338 recalc_intercepts(svm
);
341 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
343 struct vmcb
*vmcb
= get_host_vmcb(svm
);
345 vmcb
->control
.intercept
|= (1ULL << bit
);
347 recalc_intercepts(svm
);
350 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
352 struct vmcb
*vmcb
= get_host_vmcb(svm
);
354 vmcb
->control
.intercept
&= ~(1ULL << bit
);
356 recalc_intercepts(svm
);
359 static inline void enable_gif(struct vcpu_svm
*svm
)
361 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
364 static inline void disable_gif(struct vcpu_svm
*svm
)
366 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
369 static inline bool gif_set(struct vcpu_svm
*svm
)
371 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
374 static unsigned long iopm_base
;
376 struct kvm_ldttss_desc
{
379 unsigned base1
:8, type
:5, dpl
:2, p
:1;
380 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
383 } __attribute__((packed
));
385 struct svm_cpu_data
{
391 struct kvm_ldttss_desc
*tss_desc
;
393 struct page
*save_area
;
396 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
398 struct svm_init_data
{
403 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
405 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
406 #define MSRS_RANGE_SIZE 2048
407 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
409 static u32
svm_msrpm_offset(u32 msr
)
414 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
415 if (msr
< msrpm_ranges
[i
] ||
416 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
419 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
420 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
422 /* Now we have the u8 offset - but need the u32 offset */
426 /* MSR not in any range */
430 #define MAX_INST_SIZE 15
432 static inline void clgi(void)
434 asm volatile (__ex(SVM_CLGI
));
437 static inline void stgi(void)
439 asm volatile (__ex(SVM_STGI
));
442 static inline void invlpga(unsigned long addr
, u32 asid
)
444 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
447 static int get_npt_level(void)
450 return PT64_ROOT_LEVEL
;
452 return PT32E_ROOT_LEVEL
;
456 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
458 vcpu
->arch
.efer
= efer
;
459 if (!npt_enabled
&& !(efer
& EFER_LMA
))
462 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
463 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
466 static int is_external_interrupt(u32 info
)
468 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
469 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
472 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
474 struct vcpu_svm
*svm
= to_svm(vcpu
);
477 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
478 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
482 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
484 struct vcpu_svm
*svm
= to_svm(vcpu
);
487 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
489 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
493 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
495 struct vcpu_svm
*svm
= to_svm(vcpu
);
497 if (svm
->vmcb
->control
.next_rip
!= 0)
498 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
500 if (!svm
->next_rip
) {
501 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
503 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
506 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
507 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
508 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
510 kvm_rip_write(vcpu
, svm
->next_rip
);
511 svm_set_interrupt_shadow(vcpu
, 0);
514 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
515 bool has_error_code
, u32 error_code
,
518 struct vcpu_svm
*svm
= to_svm(vcpu
);
521 * If we are within a nested VM we'd better #VMEXIT and let the guest
522 * handle the exception
525 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
528 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
529 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
532 * For guest debugging where we have to reinject #BP if some
533 * INT3 is guest-owned:
534 * Emulate nRIP by moving RIP forward. Will fail if injection
535 * raises a fault that is not intercepted. Still better than
536 * failing in all cases.
538 skip_emulated_instruction(&svm
->vcpu
);
539 rip
= kvm_rip_read(&svm
->vcpu
);
540 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
541 svm
->int3_injected
= rip
- old_rip
;
544 svm
->vmcb
->control
.event_inj
= nr
546 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
547 | SVM_EVTINJ_TYPE_EXEPT
;
548 svm
->vmcb
->control
.event_inj_err
= error_code
;
551 static void svm_init_erratum_383(void)
557 if (!cpu_has_amd_erratum(amd_erratum_383
))
560 /* Use _safe variants to not break nested virtualization */
561 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
567 low
= lower_32_bits(val
);
568 high
= upper_32_bits(val
);
570 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
572 erratum_383_found
= true;
575 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
578 * Guests should see errata 400 and 415 as fixed (assuming that
579 * HLT and IO instructions are intercepted).
581 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
582 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
585 * By increasing VCPU's osvw.length to 3 we are telling the guest that
586 * all osvw.status bits inside that length, including bit 0 (which is
587 * reserved for erratum 298), are valid. However, if host processor's
588 * osvw_len is 0 then osvw_status[0] carries no information. We need to
589 * be conservative here and therefore we tell the guest that erratum 298
590 * is present (because we really don't know).
592 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
593 vcpu
->arch
.osvw
.status
|= 1;
596 static int has_svm(void)
600 if (!cpu_has_svm(&msg
)) {
601 printk(KERN_INFO
"has_svm: %s\n", msg
);
608 static void svm_hardware_disable(void *garbage
)
610 /* Make sure we clean up behind us */
611 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
612 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
616 amd_pmu_disable_virt();
619 static int svm_hardware_enable(void *garbage
)
622 struct svm_cpu_data
*sd
;
624 struct desc_ptr gdt_descr
;
625 struct desc_struct
*gdt
;
626 int me
= raw_smp_processor_id();
628 rdmsrl(MSR_EFER
, efer
);
629 if (efer
& EFER_SVME
)
633 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
637 sd
= per_cpu(svm_data
, me
);
640 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
645 sd
->asid_generation
= 1;
646 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
647 sd
->next_asid
= sd
->max_asid
+ 1;
649 native_store_gdt(&gdt_descr
);
650 gdt
= (struct desc_struct
*)gdt_descr
.address
;
651 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
653 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
655 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
657 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
658 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
659 __get_cpu_var(current_tsc_ratio
) = TSC_RATIO_DEFAULT
;
666 * Note that it is possible to have a system with mixed processor
667 * revisions and therefore different OSVW bits. If bits are not the same
668 * on different processors then choose the worst case (i.e. if erratum
669 * is present on one processor and not on another then assume that the
670 * erratum is present everywhere).
672 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
673 uint64_t len
, status
= 0;
676 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
678 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
682 osvw_status
= osvw_len
= 0;
686 osvw_status
|= status
;
687 osvw_status
&= (1ULL << osvw_len
) - 1;
690 osvw_status
= osvw_len
= 0;
692 svm_init_erratum_383();
694 amd_pmu_enable_virt();
699 static void svm_cpu_uninit(int cpu
)
701 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
706 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
707 __free_page(sd
->save_area
);
711 static int svm_cpu_init(int cpu
)
713 struct svm_cpu_data
*sd
;
716 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
720 sd
->save_area
= alloc_page(GFP_KERNEL
);
725 per_cpu(svm_data
, cpu
) = sd
;
735 static bool valid_msr_intercept(u32 index
)
739 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
740 if (direct_access_msrs
[i
].index
== index
)
746 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
749 u8 bit_read
, bit_write
;
754 * If this warning triggers extend the direct_access_msrs list at the
755 * beginning of the file
757 WARN_ON(!valid_msr_intercept(msr
));
759 offset
= svm_msrpm_offset(msr
);
760 bit_read
= 2 * (msr
& 0x0f);
761 bit_write
= 2 * (msr
& 0x0f) + 1;
764 BUG_ON(offset
== MSR_INVALID
);
766 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
767 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
772 static void svm_vcpu_init_msrpm(u32
*msrpm
)
776 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
778 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
779 if (!direct_access_msrs
[i
].always
)
782 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
786 static void add_msr_offset(u32 offset
)
790 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
792 /* Offset already in list? */
793 if (msrpm_offsets
[i
] == offset
)
796 /* Slot used by another offset? */
797 if (msrpm_offsets
[i
] != MSR_INVALID
)
800 /* Add offset to list */
801 msrpm_offsets
[i
] = offset
;
807 * If this BUG triggers the msrpm_offsets table has an overflow. Just
808 * increase MSRPM_OFFSETS in this case.
813 static void init_msrpm_offsets(void)
817 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
819 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
822 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
823 BUG_ON(offset
== MSR_INVALID
);
825 add_msr_offset(offset
);
829 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
831 u32
*msrpm
= svm
->msrpm
;
833 svm
->vmcb
->control
.lbr_ctl
= 1;
834 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
835 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
836 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
837 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
840 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
842 u32
*msrpm
= svm
->msrpm
;
844 svm
->vmcb
->control
.lbr_ctl
= 0;
845 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
846 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
847 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
848 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
851 static __init
int svm_hardware_setup(void)
854 struct page
*iopm_pages
;
858 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
863 iopm_va
= page_address(iopm_pages
);
864 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
865 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
867 init_msrpm_offsets();
869 if (boot_cpu_has(X86_FEATURE_NX
))
870 kvm_enable_efer_bits(EFER_NX
);
872 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
873 kvm_enable_efer_bits(EFER_FFXSR
);
875 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
878 kvm_has_tsc_control
= true;
881 * Make sure the user can only configure tsc_khz values that
882 * fit into a signed integer.
883 * A min value is not calculated needed because it will always
884 * be 1 on all machines and a value of 0 is used to disable
885 * tsc-scaling for the vcpu.
887 max
= min(0x7fffffffULL
, __scale_tsc(tsc_khz
, TSC_RATIO_MAX
));
889 kvm_max_guest_tsc_khz
= max
;
893 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
894 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
897 for_each_possible_cpu(cpu
) {
898 r
= svm_cpu_init(cpu
);
903 if (!boot_cpu_has(X86_FEATURE_NPT
))
906 if (npt_enabled
&& !npt
) {
907 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
912 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
920 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
925 static __exit
void svm_hardware_unsetup(void)
929 for_each_possible_cpu(cpu
)
932 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
936 static void init_seg(struct vmcb_seg
*seg
)
939 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
940 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
945 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
948 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
953 static u64
__scale_tsc(u64 ratio
, u64 tsc
)
955 u64 mult
, frac
, _tsc
;
958 frac
= ratio
& ((1ULL << 32) - 1);
962 _tsc
+= (tsc
>> 32) * frac
;
963 _tsc
+= ((tsc
& ((1ULL << 32) - 1)) * frac
) >> 32;
968 static u64
svm_scale_tsc(struct kvm_vcpu
*vcpu
, u64 tsc
)
970 struct vcpu_svm
*svm
= to_svm(vcpu
);
973 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
974 _tsc
= __scale_tsc(svm
->tsc_ratio
, tsc
);
979 static void svm_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
981 struct vcpu_svm
*svm
= to_svm(vcpu
);
985 /* Guest TSC same frequency as host TSC? */
987 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
991 /* TSC scaling supported? */
992 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
993 if (user_tsc_khz
> tsc_khz
) {
994 vcpu
->arch
.tsc_catchup
= 1;
995 vcpu
->arch
.tsc_always_catchup
= 1;
997 WARN(1, "user requested TSC rate below hardware speed\n");
1003 /* TSC scaling required - calculate ratio */
1005 do_div(ratio
, tsc_khz
);
1007 if (ratio
== 0 || ratio
& TSC_RATIO_RSVD
) {
1008 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1012 svm
->tsc_ratio
= ratio
;
1015 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1017 struct vcpu_svm
*svm
= to_svm(vcpu
);
1018 u64 g_tsc_offset
= 0;
1020 if (is_guest_mode(vcpu
)) {
1021 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1022 svm
->nested
.hsave
->control
.tsc_offset
;
1023 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1026 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1028 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1031 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1033 struct vcpu_svm
*svm
= to_svm(vcpu
);
1035 WARN_ON(adjustment
< 0);
1037 adjustment
= svm_scale_tsc(vcpu
, adjustment
);
1039 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
1040 if (is_guest_mode(vcpu
))
1041 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
1042 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1045 static u64
svm_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1049 tsc
= svm_scale_tsc(vcpu
, native_read_tsc());
1051 return target_tsc
- tsc
;
1054 static void init_vmcb(struct vcpu_svm
*svm
)
1056 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1057 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1059 svm
->vcpu
.fpu_active
= 1;
1060 svm
->vcpu
.arch
.hflags
= 0;
1062 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1063 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1064 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1065 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1066 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1067 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1068 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1070 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
1071 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
1072 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
1073 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
1074 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
1075 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
1076 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
1077 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
1079 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
1080 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
1081 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
1082 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
1083 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
1084 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
1085 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
1086 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
1088 set_exception_intercept(svm
, PF_VECTOR
);
1089 set_exception_intercept(svm
, UD_VECTOR
);
1090 set_exception_intercept(svm
, MC_VECTOR
);
1092 set_intercept(svm
, INTERCEPT_INTR
);
1093 set_intercept(svm
, INTERCEPT_NMI
);
1094 set_intercept(svm
, INTERCEPT_SMI
);
1095 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1096 set_intercept(svm
, INTERCEPT_RDPMC
);
1097 set_intercept(svm
, INTERCEPT_CPUID
);
1098 set_intercept(svm
, INTERCEPT_INVD
);
1099 set_intercept(svm
, INTERCEPT_HLT
);
1100 set_intercept(svm
, INTERCEPT_INVLPG
);
1101 set_intercept(svm
, INTERCEPT_INVLPGA
);
1102 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1103 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1104 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1105 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1106 set_intercept(svm
, INTERCEPT_VMRUN
);
1107 set_intercept(svm
, INTERCEPT_VMMCALL
);
1108 set_intercept(svm
, INTERCEPT_VMLOAD
);
1109 set_intercept(svm
, INTERCEPT_VMSAVE
);
1110 set_intercept(svm
, INTERCEPT_STGI
);
1111 set_intercept(svm
, INTERCEPT_CLGI
);
1112 set_intercept(svm
, INTERCEPT_SKINIT
);
1113 set_intercept(svm
, INTERCEPT_WBINVD
);
1114 set_intercept(svm
, INTERCEPT_MONITOR
);
1115 set_intercept(svm
, INTERCEPT_MWAIT
);
1116 set_intercept(svm
, INTERCEPT_XSETBV
);
1118 control
->iopm_base_pa
= iopm_base
;
1119 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1120 control
->int_ctl
= V_INTR_MASKING_MASK
;
1122 init_seg(&save
->es
);
1123 init_seg(&save
->ss
);
1124 init_seg(&save
->ds
);
1125 init_seg(&save
->fs
);
1126 init_seg(&save
->gs
);
1128 save
->cs
.selector
= 0xf000;
1129 /* Executable/Readable Code Segment */
1130 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1131 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1132 save
->cs
.limit
= 0xffff;
1134 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1135 * be consistent with it.
1137 * Replace when we have real mode working for vmx.
1139 save
->cs
.base
= 0xf0000;
1141 save
->gdtr
.limit
= 0xffff;
1142 save
->idtr
.limit
= 0xffff;
1144 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1145 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1147 svm_set_efer(&svm
->vcpu
, 0);
1148 save
->dr6
= 0xffff0ff0;
1150 kvm_set_rflags(&svm
->vcpu
, 2);
1151 save
->rip
= 0x0000fff0;
1152 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1155 * This is the guest-visible cr0 value.
1156 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1158 svm
->vcpu
.arch
.cr0
= 0;
1159 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1161 save
->cr4
= X86_CR4_PAE
;
1165 /* Setup VMCB for Nested Paging */
1166 control
->nested_ctl
= 1;
1167 clr_intercept(svm
, INTERCEPT_INVLPG
);
1168 clr_exception_intercept(svm
, PF_VECTOR
);
1169 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1170 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1171 save
->g_pat
= 0x0007040600070406ULL
;
1175 svm
->asid_generation
= 0;
1177 svm
->nested
.vmcb
= 0;
1178 svm
->vcpu
.arch
.hflags
= 0;
1180 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1181 control
->pause_filter_count
= 3000;
1182 set_intercept(svm
, INTERCEPT_PAUSE
);
1185 mark_all_dirty(svm
->vmcb
);
1190 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1192 struct vcpu_svm
*svm
= to_svm(vcpu
);
1196 if (!kvm_vcpu_is_bsp(vcpu
)) {
1197 kvm_rip_write(vcpu
, 0);
1198 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1199 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1201 vcpu
->arch
.regs_avail
= ~0;
1202 vcpu
->arch
.regs_dirty
= ~0;
1207 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1209 struct vcpu_svm
*svm
;
1211 struct page
*msrpm_pages
;
1212 struct page
*hsave_page
;
1213 struct page
*nested_msrpm_pages
;
1216 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1222 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1224 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1229 page
= alloc_page(GFP_KERNEL
);
1233 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1237 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1238 if (!nested_msrpm_pages
)
1241 hsave_page
= alloc_page(GFP_KERNEL
);
1245 svm
->nested
.hsave
= page_address(hsave_page
);
1247 svm
->msrpm
= page_address(msrpm_pages
);
1248 svm_vcpu_init_msrpm(svm
->msrpm
);
1250 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1251 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1253 svm
->vmcb
= page_address(page
);
1254 clear_page(svm
->vmcb
);
1255 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1256 svm
->asid_generation
= 0;
1258 kvm_write_tsc(&svm
->vcpu
, 0);
1260 err
= fx_init(&svm
->vcpu
);
1264 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1265 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1266 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1268 svm_init_osvw(&svm
->vcpu
);
1273 __free_page(hsave_page
);
1275 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1277 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1281 kvm_vcpu_uninit(&svm
->vcpu
);
1283 kmem_cache_free(kvm_vcpu_cache
, svm
);
1285 return ERR_PTR(err
);
1288 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1290 struct vcpu_svm
*svm
= to_svm(vcpu
);
1292 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1293 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1294 __free_page(virt_to_page(svm
->nested
.hsave
));
1295 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1296 kvm_vcpu_uninit(vcpu
);
1297 kmem_cache_free(kvm_vcpu_cache
, svm
);
1300 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1302 struct vcpu_svm
*svm
= to_svm(vcpu
);
1305 if (unlikely(cpu
!= vcpu
->cpu
)) {
1306 svm
->asid_generation
= 0;
1307 mark_all_dirty(svm
->vmcb
);
1310 #ifdef CONFIG_X86_64
1311 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1313 savesegment(fs
, svm
->host
.fs
);
1314 savesegment(gs
, svm
->host
.gs
);
1315 svm
->host
.ldt
= kvm_read_ldt();
1317 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1318 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1320 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
) &&
1321 svm
->tsc_ratio
!= __get_cpu_var(current_tsc_ratio
)) {
1322 __get_cpu_var(current_tsc_ratio
) = svm
->tsc_ratio
;
1323 wrmsrl(MSR_AMD64_TSC_RATIO
, svm
->tsc_ratio
);
1327 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1329 struct vcpu_svm
*svm
= to_svm(vcpu
);
1332 ++vcpu
->stat
.host_state_reload
;
1333 kvm_load_ldt(svm
->host
.ldt
);
1334 #ifdef CONFIG_X86_64
1335 loadsegment(fs
, svm
->host
.fs
);
1336 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1337 load_gs_index(svm
->host
.gs
);
1339 #ifdef CONFIG_X86_32_LAZY_GS
1340 loadsegment(gs
, svm
->host
.gs
);
1343 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1344 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1347 static void svm_update_cpl(struct kvm_vcpu
*vcpu
)
1349 struct vcpu_svm
*svm
= to_svm(vcpu
);
1352 if (!is_protmode(vcpu
))
1354 else if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_VM
)
1357 cpl
= svm
->vmcb
->save
.cs
.selector
& 0x3;
1359 svm
->vmcb
->save
.cpl
= cpl
;
1362 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1364 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1367 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1369 unsigned long old_rflags
= to_svm(vcpu
)->vmcb
->save
.rflags
;
1371 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1372 if ((old_rflags
^ rflags
) & X86_EFLAGS_VM
)
1373 svm_update_cpl(vcpu
);
1376 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1379 case VCPU_EXREG_PDPTR
:
1380 BUG_ON(!npt_enabled
);
1381 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1388 static void svm_set_vintr(struct vcpu_svm
*svm
)
1390 set_intercept(svm
, INTERCEPT_VINTR
);
1393 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1395 clr_intercept(svm
, INTERCEPT_VINTR
);
1398 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1400 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1403 case VCPU_SREG_CS
: return &save
->cs
;
1404 case VCPU_SREG_DS
: return &save
->ds
;
1405 case VCPU_SREG_ES
: return &save
->es
;
1406 case VCPU_SREG_FS
: return &save
->fs
;
1407 case VCPU_SREG_GS
: return &save
->gs
;
1408 case VCPU_SREG_SS
: return &save
->ss
;
1409 case VCPU_SREG_TR
: return &save
->tr
;
1410 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1416 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1418 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1423 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1424 struct kvm_segment
*var
, int seg
)
1426 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1428 var
->base
= s
->base
;
1429 var
->limit
= s
->limit
;
1430 var
->selector
= s
->selector
;
1431 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1432 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1433 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1434 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1435 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1436 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1437 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1438 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1441 * AMD's VMCB does not have an explicit unusable field, so emulate it
1442 * for cross vendor migration purposes by "not present"
1444 var
->unusable
= !var
->present
|| (var
->type
== 0);
1449 * SVM always stores 0 for the 'G' bit in the CS selector in
1450 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1451 * Intel's VMENTRY has a check on the 'G' bit.
1453 var
->g
= s
->limit
> 0xfffff;
1457 * Work around a bug where the busy flag in the tr selector
1467 * The accessed bit must always be set in the segment
1468 * descriptor cache, although it can be cleared in the
1469 * descriptor, the cached bit always remains at 1. Since
1470 * Intel has a check on this, set it here to support
1471 * cross-vendor migration.
1478 * On AMD CPUs sometimes the DB bit in the segment
1479 * descriptor is left as 1, although the whole segment has
1480 * been made unusable. Clear it here to pass an Intel VMX
1481 * entry check when cross vendor migrating.
1489 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1491 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1496 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1498 struct vcpu_svm
*svm
= to_svm(vcpu
);
1500 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1501 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1504 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1506 struct vcpu_svm
*svm
= to_svm(vcpu
);
1508 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1509 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1510 mark_dirty(svm
->vmcb
, VMCB_DT
);
1513 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1515 struct vcpu_svm
*svm
= to_svm(vcpu
);
1517 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1518 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1521 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1523 struct vcpu_svm
*svm
= to_svm(vcpu
);
1525 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1526 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1527 mark_dirty(svm
->vmcb
, VMCB_DT
);
1530 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1534 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1538 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1542 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1544 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1545 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1547 if (!svm
->vcpu
.fpu_active
)
1548 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1550 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1551 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1553 mark_dirty(svm
->vmcb
, VMCB_CR
);
1555 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1556 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1557 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1559 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1560 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1564 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1566 struct vcpu_svm
*svm
= to_svm(vcpu
);
1568 #ifdef CONFIG_X86_64
1569 if (vcpu
->arch
.efer
& EFER_LME
) {
1570 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1571 vcpu
->arch
.efer
|= EFER_LMA
;
1572 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1575 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1576 vcpu
->arch
.efer
&= ~EFER_LMA
;
1577 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1581 vcpu
->arch
.cr0
= cr0
;
1584 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1586 if (!vcpu
->fpu_active
)
1589 * re-enable caching here because the QEMU bios
1590 * does not do it - this results in some delay at
1593 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1594 svm
->vmcb
->save
.cr0
= cr0
;
1595 mark_dirty(svm
->vmcb
, VMCB_CR
);
1596 update_cr0_intercept(svm
);
1599 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1601 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1602 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1604 if (cr4
& X86_CR4_VMXE
)
1607 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1608 svm_flush_tlb(vcpu
);
1610 vcpu
->arch
.cr4
= cr4
;
1613 cr4
|= host_cr4_mce
;
1614 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1615 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1619 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1620 struct kvm_segment
*var
, int seg
)
1622 struct vcpu_svm
*svm
= to_svm(vcpu
);
1623 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1625 s
->base
= var
->base
;
1626 s
->limit
= var
->limit
;
1627 s
->selector
= var
->selector
;
1631 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1632 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1633 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1634 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1635 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1636 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1637 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1638 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1640 if (seg
== VCPU_SREG_CS
)
1641 svm_update_cpl(vcpu
);
1643 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1646 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1648 struct vcpu_svm
*svm
= to_svm(vcpu
);
1650 clr_exception_intercept(svm
, DB_VECTOR
);
1651 clr_exception_intercept(svm
, BP_VECTOR
);
1653 if (svm
->nmi_singlestep
)
1654 set_exception_intercept(svm
, DB_VECTOR
);
1656 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1657 if (vcpu
->guest_debug
&
1658 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1659 set_exception_intercept(svm
, DB_VECTOR
);
1660 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1661 set_exception_intercept(svm
, BP_VECTOR
);
1663 vcpu
->guest_debug
= 0;
1666 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1668 struct vcpu_svm
*svm
= to_svm(vcpu
);
1670 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1671 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1673 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1675 mark_dirty(svm
->vmcb
, VMCB_DR
);
1677 update_db_intercept(vcpu
);
1680 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1682 if (sd
->next_asid
> sd
->max_asid
) {
1683 ++sd
->asid_generation
;
1685 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1688 svm
->asid_generation
= sd
->asid_generation
;
1689 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1691 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1694 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1696 struct vcpu_svm
*svm
= to_svm(vcpu
);
1698 svm
->vmcb
->save
.dr7
= value
;
1699 mark_dirty(svm
->vmcb
, VMCB_DR
);
1702 static int pf_interception(struct vcpu_svm
*svm
)
1704 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1708 switch (svm
->apf_reason
) {
1710 error_code
= svm
->vmcb
->control
.exit_info_1
;
1712 trace_kvm_page_fault(fault_address
, error_code
);
1713 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1714 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1715 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1716 svm
->vmcb
->control
.insn_bytes
,
1717 svm
->vmcb
->control
.insn_len
);
1719 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1720 svm
->apf_reason
= 0;
1721 local_irq_disable();
1722 kvm_async_pf_task_wait(fault_address
);
1725 case KVM_PV_REASON_PAGE_READY
:
1726 svm
->apf_reason
= 0;
1727 local_irq_disable();
1728 kvm_async_pf_task_wake(fault_address
);
1735 static int db_interception(struct vcpu_svm
*svm
)
1737 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1739 if (!(svm
->vcpu
.guest_debug
&
1740 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1741 !svm
->nmi_singlestep
) {
1742 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1746 if (svm
->nmi_singlestep
) {
1747 svm
->nmi_singlestep
= false;
1748 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1749 svm
->vmcb
->save
.rflags
&=
1750 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1751 update_db_intercept(&svm
->vcpu
);
1754 if (svm
->vcpu
.guest_debug
&
1755 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1756 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1757 kvm_run
->debug
.arch
.pc
=
1758 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1759 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1766 static int bp_interception(struct vcpu_svm
*svm
)
1768 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1770 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1771 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1772 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1776 static int ud_interception(struct vcpu_svm
*svm
)
1780 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1781 if (er
!= EMULATE_DONE
)
1782 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1786 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1788 struct vcpu_svm
*svm
= to_svm(vcpu
);
1790 clr_exception_intercept(svm
, NM_VECTOR
);
1792 svm
->vcpu
.fpu_active
= 1;
1793 update_cr0_intercept(svm
);
1796 static int nm_interception(struct vcpu_svm
*svm
)
1798 svm_fpu_activate(&svm
->vcpu
);
1802 static bool is_erratum_383(void)
1807 if (!erratum_383_found
)
1810 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1814 /* Bit 62 may or may not be set for this mce */
1815 value
&= ~(1ULL << 62);
1817 if (value
!= 0xb600000000010015ULL
)
1820 /* Clear MCi_STATUS registers */
1821 for (i
= 0; i
< 6; ++i
)
1822 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1824 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1828 value
&= ~(1ULL << 2);
1829 low
= lower_32_bits(value
);
1830 high
= upper_32_bits(value
);
1832 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1835 /* Flush tlb to evict multi-match entries */
1841 static void svm_handle_mce(struct vcpu_svm
*svm
)
1843 if (is_erratum_383()) {
1845 * Erratum 383 triggered. Guest state is corrupt so kill the
1848 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1850 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1856 * On an #MC intercept the MCE handler is not called automatically in
1857 * the host. So do it by hand here.
1861 /* not sure if we ever come back to this point */
1866 static int mc_interception(struct vcpu_svm
*svm
)
1871 static int shutdown_interception(struct vcpu_svm
*svm
)
1873 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1876 * VMCB is undefined after a SHUTDOWN intercept
1877 * so reinitialize it.
1879 clear_page(svm
->vmcb
);
1882 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1886 static int io_interception(struct vcpu_svm
*svm
)
1888 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1889 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1890 int size
, in
, string
;
1893 ++svm
->vcpu
.stat
.io_exits
;
1894 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1895 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1897 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
1899 port
= io_info
>> 16;
1900 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1901 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1902 skip_emulated_instruction(&svm
->vcpu
);
1904 return kvm_fast_pio_out(vcpu
, size
, port
);
1907 static int nmi_interception(struct vcpu_svm
*svm
)
1912 static int intr_interception(struct vcpu_svm
*svm
)
1914 ++svm
->vcpu
.stat
.irq_exits
;
1918 static int nop_on_interception(struct vcpu_svm
*svm
)
1923 static int halt_interception(struct vcpu_svm
*svm
)
1925 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1926 skip_emulated_instruction(&svm
->vcpu
);
1927 return kvm_emulate_halt(&svm
->vcpu
);
1930 static int vmmcall_interception(struct vcpu_svm
*svm
)
1932 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1933 skip_emulated_instruction(&svm
->vcpu
);
1934 kvm_emulate_hypercall(&svm
->vcpu
);
1938 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1940 struct vcpu_svm
*svm
= to_svm(vcpu
);
1942 return svm
->nested
.nested_cr3
;
1945 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
1947 struct vcpu_svm
*svm
= to_svm(vcpu
);
1948 u64 cr3
= svm
->nested
.nested_cr3
;
1952 ret
= kvm_read_guest_page(vcpu
->kvm
, gpa_to_gfn(cr3
), &pdpte
,
1953 offset_in_page(cr3
) + index
* 8, 8);
1959 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1962 struct vcpu_svm
*svm
= to_svm(vcpu
);
1964 svm
->vmcb
->control
.nested_cr3
= root
;
1965 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1966 svm_flush_tlb(vcpu
);
1969 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1970 struct x86_exception
*fault
)
1972 struct vcpu_svm
*svm
= to_svm(vcpu
);
1974 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1975 svm
->vmcb
->control
.exit_code_hi
= 0;
1976 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1977 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1979 nested_svm_vmexit(svm
);
1982 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1986 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1988 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1989 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1990 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
1991 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1992 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1993 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1998 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2000 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2003 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2005 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
2006 || !is_paging(&svm
->vcpu
)) {
2007 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2011 if (svm
->vmcb
->save
.cpl
) {
2012 kvm_inject_gp(&svm
->vcpu
, 0);
2019 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2020 bool has_error_code
, u32 error_code
)
2024 if (!is_guest_mode(&svm
->vcpu
))
2027 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2028 svm
->vmcb
->control
.exit_code_hi
= 0;
2029 svm
->vmcb
->control
.exit_info_1
= error_code
;
2030 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2032 vmexit
= nested_svm_intercept(svm
);
2033 if (vmexit
== NESTED_EXIT_DONE
)
2034 svm
->nested
.exit_required
= true;
2039 /* This function returns true if it is save to enable the irq window */
2040 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2042 if (!is_guest_mode(&svm
->vcpu
))
2045 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2048 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2052 * if vmexit was already requested (by intercepted exception
2053 * for instance) do not overwrite it with "external interrupt"
2056 if (svm
->nested
.exit_required
)
2059 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2060 svm
->vmcb
->control
.exit_info_1
= 0;
2061 svm
->vmcb
->control
.exit_info_2
= 0;
2063 if (svm
->nested
.intercept
& 1ULL) {
2065 * The #vmexit can't be emulated here directly because this
2066 * code path runs with irqs and preemtion disabled. A
2067 * #vmexit emulation might sleep. Only signal request for
2070 svm
->nested
.exit_required
= true;
2071 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2078 /* This function returns true if it is save to enable the nmi window */
2079 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2081 if (!is_guest_mode(&svm
->vcpu
))
2084 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2087 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2088 svm
->nested
.exit_required
= true;
2093 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2099 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
2100 if (is_error_page(page
))
2108 kvm_release_page_clean(page
);
2109 kvm_inject_gp(&svm
->vcpu
, 0);
2114 static void nested_svm_unmap(struct page
*page
)
2117 kvm_release_page_dirty(page
);
2120 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2126 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2127 return NESTED_EXIT_HOST
;
2129 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2130 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2134 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
2137 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2140 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2142 u32 offset
, msr
, value
;
2145 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2146 return NESTED_EXIT_HOST
;
2148 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2149 offset
= svm_msrpm_offset(msr
);
2150 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2151 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2153 if (offset
== MSR_INVALID
)
2154 return NESTED_EXIT_DONE
;
2156 /* Offset is in 32 bit units but need in 8 bit units */
2159 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2160 return NESTED_EXIT_DONE
;
2162 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2165 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2167 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2169 switch (exit_code
) {
2172 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2173 return NESTED_EXIT_HOST
;
2175 /* For now we are always handling NPFs when using them */
2177 return NESTED_EXIT_HOST
;
2179 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2180 /* When we're shadowing, trap PFs, but not async PF */
2181 if (!npt_enabled
&& svm
->apf_reason
== 0)
2182 return NESTED_EXIT_HOST
;
2184 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2185 nm_interception(svm
);
2191 return NESTED_EXIT_CONTINUE
;
2195 * If this function returns true, this #vmexit was already handled
2197 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2199 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2200 int vmexit
= NESTED_EXIT_HOST
;
2202 switch (exit_code
) {
2204 vmexit
= nested_svm_exit_handled_msr(svm
);
2207 vmexit
= nested_svm_intercept_ioio(svm
);
2209 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2210 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2211 if (svm
->nested
.intercept_cr
& bit
)
2212 vmexit
= NESTED_EXIT_DONE
;
2215 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2216 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2217 if (svm
->nested
.intercept_dr
& bit
)
2218 vmexit
= NESTED_EXIT_DONE
;
2221 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2222 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2223 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2224 vmexit
= NESTED_EXIT_DONE
;
2225 /* async page fault always cause vmexit */
2226 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2227 svm
->apf_reason
!= 0)
2228 vmexit
= NESTED_EXIT_DONE
;
2231 case SVM_EXIT_ERR
: {
2232 vmexit
= NESTED_EXIT_DONE
;
2236 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2237 if (svm
->nested
.intercept
& exit_bits
)
2238 vmexit
= NESTED_EXIT_DONE
;
2245 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2249 vmexit
= nested_svm_intercept(svm
);
2251 if (vmexit
== NESTED_EXIT_DONE
)
2252 nested_svm_vmexit(svm
);
2257 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2259 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2260 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2262 dst
->intercept_cr
= from
->intercept_cr
;
2263 dst
->intercept_dr
= from
->intercept_dr
;
2264 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2265 dst
->intercept
= from
->intercept
;
2266 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2267 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2268 dst
->tsc_offset
= from
->tsc_offset
;
2269 dst
->asid
= from
->asid
;
2270 dst
->tlb_ctl
= from
->tlb_ctl
;
2271 dst
->int_ctl
= from
->int_ctl
;
2272 dst
->int_vector
= from
->int_vector
;
2273 dst
->int_state
= from
->int_state
;
2274 dst
->exit_code
= from
->exit_code
;
2275 dst
->exit_code_hi
= from
->exit_code_hi
;
2276 dst
->exit_info_1
= from
->exit_info_1
;
2277 dst
->exit_info_2
= from
->exit_info_2
;
2278 dst
->exit_int_info
= from
->exit_int_info
;
2279 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2280 dst
->nested_ctl
= from
->nested_ctl
;
2281 dst
->event_inj
= from
->event_inj
;
2282 dst
->event_inj_err
= from
->event_inj_err
;
2283 dst
->nested_cr3
= from
->nested_cr3
;
2284 dst
->lbr_ctl
= from
->lbr_ctl
;
2287 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2289 struct vmcb
*nested_vmcb
;
2290 struct vmcb
*hsave
= svm
->nested
.hsave
;
2291 struct vmcb
*vmcb
= svm
->vmcb
;
2294 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2295 vmcb
->control
.exit_info_1
,
2296 vmcb
->control
.exit_info_2
,
2297 vmcb
->control
.exit_int_info
,
2298 vmcb
->control
.exit_int_info_err
,
2301 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2305 /* Exit Guest-Mode */
2306 leave_guest_mode(&svm
->vcpu
);
2307 svm
->nested
.vmcb
= 0;
2309 /* Give the current vmcb to the guest */
2312 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2313 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2314 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2315 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2316 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2317 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2318 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2319 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2320 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2321 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2322 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2323 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2324 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2325 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2326 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2327 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2328 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2329 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2331 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2332 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2333 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2334 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2335 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2336 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2337 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2338 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2339 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2340 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2343 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2344 * to make sure that we do not lose injected events. So check event_inj
2345 * here and copy it to exit_int_info if it is valid.
2346 * Exit_int_info and event_inj can't be both valid because the case
2347 * below only happens on a VMRUN instruction intercept which has
2348 * no valid exit_int_info set.
2350 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2351 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2353 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2354 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2357 nested_vmcb
->control
.tlb_ctl
= 0;
2358 nested_vmcb
->control
.event_inj
= 0;
2359 nested_vmcb
->control
.event_inj_err
= 0;
2361 /* We always set V_INTR_MASKING and remember the old value in hflags */
2362 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2363 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2365 /* Restore the original control entries */
2366 copy_vmcb_control_area(vmcb
, hsave
);
2368 kvm_clear_exception_queue(&svm
->vcpu
);
2369 kvm_clear_interrupt_queue(&svm
->vcpu
);
2371 svm
->nested
.nested_cr3
= 0;
2373 /* Restore selected save entries */
2374 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2375 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2376 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2377 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2378 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2379 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2380 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2381 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2382 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2383 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2385 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2386 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2388 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2390 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2391 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2392 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2393 svm
->vmcb
->save
.dr7
= 0;
2394 svm
->vmcb
->save
.cpl
= 0;
2395 svm
->vmcb
->control
.exit_int_info
= 0;
2397 mark_all_dirty(svm
->vmcb
);
2399 nested_svm_unmap(page
);
2401 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2402 kvm_mmu_reset_context(&svm
->vcpu
);
2403 kvm_mmu_load(&svm
->vcpu
);
2408 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2411 * This function merges the msr permission bitmaps of kvm and the
2412 * nested vmcb. It is omptimized in that it only merges the parts where
2413 * the kvm msr permission bitmap may contain zero bits
2417 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2420 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2424 if (msrpm_offsets
[i
] == 0xffffffff)
2427 p
= msrpm_offsets
[i
];
2428 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2430 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2433 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2436 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2441 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2443 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2446 if (vmcb
->control
.asid
== 0)
2449 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2455 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2457 struct vmcb
*nested_vmcb
;
2458 struct vmcb
*hsave
= svm
->nested
.hsave
;
2459 struct vmcb
*vmcb
= svm
->vmcb
;
2463 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2465 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2469 if (!nested_vmcb_checks(nested_vmcb
)) {
2470 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2471 nested_vmcb
->control
.exit_code_hi
= 0;
2472 nested_vmcb
->control
.exit_info_1
= 0;
2473 nested_vmcb
->control
.exit_info_2
= 0;
2475 nested_svm_unmap(page
);
2480 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2481 nested_vmcb
->save
.rip
,
2482 nested_vmcb
->control
.int_ctl
,
2483 nested_vmcb
->control
.event_inj
,
2484 nested_vmcb
->control
.nested_ctl
);
2486 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2487 nested_vmcb
->control
.intercept_cr
>> 16,
2488 nested_vmcb
->control
.intercept_exceptions
,
2489 nested_vmcb
->control
.intercept
);
2491 /* Clear internal status */
2492 kvm_clear_exception_queue(&svm
->vcpu
);
2493 kvm_clear_interrupt_queue(&svm
->vcpu
);
2496 * Save the old vmcb, so we don't need to pick what we save, but can
2497 * restore everything when a VMEXIT occurs
2499 hsave
->save
.es
= vmcb
->save
.es
;
2500 hsave
->save
.cs
= vmcb
->save
.cs
;
2501 hsave
->save
.ss
= vmcb
->save
.ss
;
2502 hsave
->save
.ds
= vmcb
->save
.ds
;
2503 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2504 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2505 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2506 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2507 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2508 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2509 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2510 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2511 hsave
->save
.rax
= vmcb
->save
.rax
;
2513 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2515 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2517 copy_vmcb_control_area(hsave
, vmcb
);
2519 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2520 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2522 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2524 if (nested_vmcb
->control
.nested_ctl
) {
2525 kvm_mmu_unload(&svm
->vcpu
);
2526 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2527 nested_svm_init_mmu_context(&svm
->vcpu
);
2530 /* Load the nested guest state */
2531 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2532 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2533 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2534 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2535 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2536 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2537 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2538 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2539 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2540 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2542 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2543 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2545 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2547 /* Guest paging mode is active - reset mmu */
2548 kvm_mmu_reset_context(&svm
->vcpu
);
2550 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2551 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2552 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2553 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2555 /* In case we don't even reach vcpu_run, the fields are not updated */
2556 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2557 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2558 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2559 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2560 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2561 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2563 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2564 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2566 /* cache intercepts */
2567 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2568 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2569 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2570 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2572 svm_flush_tlb(&svm
->vcpu
);
2573 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2574 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2575 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2577 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2579 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2580 /* We only want the cr8 intercept bits of the guest */
2581 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2582 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2585 /* We don't want to see VMMCALLs from a nested guest */
2586 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2588 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2589 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2590 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2591 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2592 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2593 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2595 nested_svm_unmap(page
);
2597 /* Enter Guest-Mode */
2598 enter_guest_mode(&svm
->vcpu
);
2601 * Merge guest and host intercepts - must be called with vcpu in
2602 * guest-mode to take affect here
2604 recalc_intercepts(svm
);
2606 svm
->nested
.vmcb
= vmcb_gpa
;
2610 mark_all_dirty(svm
->vmcb
);
2615 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2617 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2618 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2619 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2620 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2621 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2622 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2623 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2624 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2625 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2626 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2627 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2628 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2631 static int vmload_interception(struct vcpu_svm
*svm
)
2633 struct vmcb
*nested_vmcb
;
2636 if (nested_svm_check_permissions(svm
))
2639 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2643 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2644 skip_emulated_instruction(&svm
->vcpu
);
2646 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2647 nested_svm_unmap(page
);
2652 static int vmsave_interception(struct vcpu_svm
*svm
)
2654 struct vmcb
*nested_vmcb
;
2657 if (nested_svm_check_permissions(svm
))
2660 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2664 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2665 skip_emulated_instruction(&svm
->vcpu
);
2667 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2668 nested_svm_unmap(page
);
2673 static int vmrun_interception(struct vcpu_svm
*svm
)
2675 if (nested_svm_check_permissions(svm
))
2678 /* Save rip after vmrun instruction */
2679 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2681 if (!nested_svm_vmrun(svm
))
2684 if (!nested_svm_vmrun_msrpm(svm
))
2691 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2692 svm
->vmcb
->control
.exit_code_hi
= 0;
2693 svm
->vmcb
->control
.exit_info_1
= 0;
2694 svm
->vmcb
->control
.exit_info_2
= 0;
2696 nested_svm_vmexit(svm
);
2701 static int stgi_interception(struct vcpu_svm
*svm
)
2703 if (nested_svm_check_permissions(svm
))
2706 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2707 skip_emulated_instruction(&svm
->vcpu
);
2708 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2715 static int clgi_interception(struct vcpu_svm
*svm
)
2717 if (nested_svm_check_permissions(svm
))
2720 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2721 skip_emulated_instruction(&svm
->vcpu
);
2725 /* After a CLGI no interrupts should come */
2726 svm_clear_vintr(svm
);
2727 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2729 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2734 static int invlpga_interception(struct vcpu_svm
*svm
)
2736 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2738 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2739 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2741 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2742 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2744 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2745 skip_emulated_instruction(&svm
->vcpu
);
2749 static int skinit_interception(struct vcpu_svm
*svm
)
2751 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2753 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2757 static int xsetbv_interception(struct vcpu_svm
*svm
)
2759 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2760 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2762 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2763 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2764 skip_emulated_instruction(&svm
->vcpu
);
2770 static int invalid_op_interception(struct vcpu_svm
*svm
)
2772 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2776 static int task_switch_interception(struct vcpu_svm
*svm
)
2780 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2781 SVM_EXITINTINFO_TYPE_MASK
;
2782 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2784 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2786 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2787 bool has_error_code
= false;
2790 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2792 if (svm
->vmcb
->control
.exit_info_2
&
2793 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2794 reason
= TASK_SWITCH_IRET
;
2795 else if (svm
->vmcb
->control
.exit_info_2
&
2796 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2797 reason
= TASK_SWITCH_JMP
;
2799 reason
= TASK_SWITCH_GATE
;
2801 reason
= TASK_SWITCH_CALL
;
2803 if (reason
== TASK_SWITCH_GATE
) {
2805 case SVM_EXITINTINFO_TYPE_NMI
:
2806 svm
->vcpu
.arch
.nmi_injected
= false;
2808 case SVM_EXITINTINFO_TYPE_EXEPT
:
2809 if (svm
->vmcb
->control
.exit_info_2
&
2810 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2811 has_error_code
= true;
2813 (u32
)svm
->vmcb
->control
.exit_info_2
;
2815 kvm_clear_exception_queue(&svm
->vcpu
);
2817 case SVM_EXITINTINFO_TYPE_INTR
:
2818 kvm_clear_interrupt_queue(&svm
->vcpu
);
2825 if (reason
!= TASK_SWITCH_GATE
||
2826 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2827 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2828 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2829 skip_emulated_instruction(&svm
->vcpu
);
2831 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2834 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
2835 has_error_code
, error_code
) == EMULATE_FAIL
) {
2836 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2837 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2838 svm
->vcpu
.run
->internal
.ndata
= 0;
2844 static int cpuid_interception(struct vcpu_svm
*svm
)
2846 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2847 kvm_emulate_cpuid(&svm
->vcpu
);
2851 static int iret_interception(struct vcpu_svm
*svm
)
2853 ++svm
->vcpu
.stat
.nmi_window_exits
;
2854 clr_intercept(svm
, INTERCEPT_IRET
);
2855 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2856 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2860 static int invlpg_interception(struct vcpu_svm
*svm
)
2862 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2863 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2865 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2866 skip_emulated_instruction(&svm
->vcpu
);
2870 static int emulate_on_interception(struct vcpu_svm
*svm
)
2872 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2875 static int rdpmc_interception(struct vcpu_svm
*svm
)
2879 if (!static_cpu_has(X86_FEATURE_NRIPS
))
2880 return emulate_on_interception(svm
);
2882 err
= kvm_rdpmc(&svm
->vcpu
);
2883 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2888 bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
, unsigned long val
)
2890 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
2894 intercept
= svm
->nested
.intercept
;
2896 if (!is_guest_mode(&svm
->vcpu
) ||
2897 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
2900 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2901 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2904 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2905 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2911 #define CR_VALID (1ULL << 63)
2913 static int cr_interception(struct vcpu_svm
*svm
)
2919 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2920 return emulate_on_interception(svm
);
2922 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2923 return emulate_on_interception(svm
);
2925 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2926 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2929 if (cr
>= 16) { /* mov to cr */
2931 val
= kvm_register_read(&svm
->vcpu
, reg
);
2934 if (!check_selective_cr0_intercepted(svm
, val
))
2935 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2941 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2944 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2947 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2950 WARN(1, "unhandled write to CR%d", cr
);
2951 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2954 } else { /* mov from cr */
2957 val
= kvm_read_cr0(&svm
->vcpu
);
2960 val
= svm
->vcpu
.arch
.cr2
;
2963 val
= kvm_read_cr3(&svm
->vcpu
);
2966 val
= kvm_read_cr4(&svm
->vcpu
);
2969 val
= kvm_get_cr8(&svm
->vcpu
);
2972 WARN(1, "unhandled read from CR%d", cr
);
2973 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2976 kvm_register_write(&svm
->vcpu
, reg
, val
);
2978 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2983 static int dr_interception(struct vcpu_svm
*svm
)
2989 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2990 return emulate_on_interception(svm
);
2992 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2993 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2995 if (dr
>= 16) { /* mov to DRn */
2996 val
= kvm_register_read(&svm
->vcpu
, reg
);
2997 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
2999 err
= kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3001 kvm_register_write(&svm
->vcpu
, reg
, val
);
3004 skip_emulated_instruction(&svm
->vcpu
);
3009 static int cr8_write_interception(struct vcpu_svm
*svm
)
3011 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3014 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3015 /* instruction emulation calls kvm_set_cr8() */
3016 r
= cr_interception(svm
);
3017 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
3018 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3021 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3023 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3027 u64
svm_read_l1_tsc(struct kvm_vcpu
*vcpu
)
3029 struct vmcb
*vmcb
= get_host_vmcb(to_svm(vcpu
));
3030 return vmcb
->control
.tsc_offset
+
3031 svm_scale_tsc(vcpu
, native_read_tsc());
3034 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
3036 struct vcpu_svm
*svm
= to_svm(vcpu
);
3039 case MSR_IA32_TSC
: {
3040 *data
= svm
->vmcb
->control
.tsc_offset
+
3041 svm_scale_tsc(vcpu
, native_read_tsc());
3046 *data
= svm
->vmcb
->save
.star
;
3048 #ifdef CONFIG_X86_64
3050 *data
= svm
->vmcb
->save
.lstar
;
3053 *data
= svm
->vmcb
->save
.cstar
;
3055 case MSR_KERNEL_GS_BASE
:
3056 *data
= svm
->vmcb
->save
.kernel_gs_base
;
3058 case MSR_SYSCALL_MASK
:
3059 *data
= svm
->vmcb
->save
.sfmask
;
3062 case MSR_IA32_SYSENTER_CS
:
3063 *data
= svm
->vmcb
->save
.sysenter_cs
;
3065 case MSR_IA32_SYSENTER_EIP
:
3066 *data
= svm
->sysenter_eip
;
3068 case MSR_IA32_SYSENTER_ESP
:
3069 *data
= svm
->sysenter_esp
;
3072 * Nobody will change the following 5 values in the VMCB so we can
3073 * safely return them on rdmsr. They will always be 0 until LBRV is
3076 case MSR_IA32_DEBUGCTLMSR
:
3077 *data
= svm
->vmcb
->save
.dbgctl
;
3079 case MSR_IA32_LASTBRANCHFROMIP
:
3080 *data
= svm
->vmcb
->save
.br_from
;
3082 case MSR_IA32_LASTBRANCHTOIP
:
3083 *data
= svm
->vmcb
->save
.br_to
;
3085 case MSR_IA32_LASTINTFROMIP
:
3086 *data
= svm
->vmcb
->save
.last_excp_from
;
3088 case MSR_IA32_LASTINTTOIP
:
3089 *data
= svm
->vmcb
->save
.last_excp_to
;
3091 case MSR_VM_HSAVE_PA
:
3092 *data
= svm
->nested
.hsave_msr
;
3095 *data
= svm
->nested
.vm_cr_msr
;
3097 case MSR_IA32_UCODE_REV
:
3101 return kvm_get_msr_common(vcpu
, ecx
, data
);
3106 static int rdmsr_interception(struct vcpu_svm
*svm
)
3108 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3111 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
3112 trace_kvm_msr_read_ex(ecx
);
3113 kvm_inject_gp(&svm
->vcpu
, 0);
3115 trace_kvm_msr_read(ecx
, data
);
3117 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
3118 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
3119 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3120 skip_emulated_instruction(&svm
->vcpu
);
3125 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3127 struct vcpu_svm
*svm
= to_svm(vcpu
);
3128 int svm_dis
, chg_mask
;
3130 if (data
& ~SVM_VM_CR_VALID_MASK
)
3133 chg_mask
= SVM_VM_CR_VALID_MASK
;
3135 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3136 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3138 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3139 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3141 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3143 /* check for svm_disable while efer.svme is set */
3144 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3150 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
3152 struct vcpu_svm
*svm
= to_svm(vcpu
);
3156 kvm_write_tsc(vcpu
, data
);
3159 svm
->vmcb
->save
.star
= data
;
3161 #ifdef CONFIG_X86_64
3163 svm
->vmcb
->save
.lstar
= data
;
3166 svm
->vmcb
->save
.cstar
= data
;
3168 case MSR_KERNEL_GS_BASE
:
3169 svm
->vmcb
->save
.kernel_gs_base
= data
;
3171 case MSR_SYSCALL_MASK
:
3172 svm
->vmcb
->save
.sfmask
= data
;
3175 case MSR_IA32_SYSENTER_CS
:
3176 svm
->vmcb
->save
.sysenter_cs
= data
;
3178 case MSR_IA32_SYSENTER_EIP
:
3179 svm
->sysenter_eip
= data
;
3180 svm
->vmcb
->save
.sysenter_eip
= data
;
3182 case MSR_IA32_SYSENTER_ESP
:
3183 svm
->sysenter_esp
= data
;
3184 svm
->vmcb
->save
.sysenter_esp
= data
;
3186 case MSR_IA32_DEBUGCTLMSR
:
3187 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3188 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3192 if (data
& DEBUGCTL_RESERVED_BITS
)
3195 svm
->vmcb
->save
.dbgctl
= data
;
3196 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3197 if (data
& (1ULL<<0))
3198 svm_enable_lbrv(svm
);
3200 svm_disable_lbrv(svm
);
3202 case MSR_VM_HSAVE_PA
:
3203 svm
->nested
.hsave_msr
= data
;
3206 return svm_set_vm_cr(vcpu
, data
);
3208 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3211 return kvm_set_msr_common(vcpu
, ecx
, data
);
3216 static int wrmsr_interception(struct vcpu_svm
*svm
)
3218 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3219 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
3220 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3223 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3224 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
3225 trace_kvm_msr_write_ex(ecx
, data
);
3226 kvm_inject_gp(&svm
->vcpu
, 0);
3228 trace_kvm_msr_write(ecx
, data
);
3229 skip_emulated_instruction(&svm
->vcpu
);
3234 static int msr_interception(struct vcpu_svm
*svm
)
3236 if (svm
->vmcb
->control
.exit_info_1
)
3237 return wrmsr_interception(svm
);
3239 return rdmsr_interception(svm
);
3242 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3244 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3246 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3247 svm_clear_vintr(svm
);
3248 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3249 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3250 ++svm
->vcpu
.stat
.irq_window_exits
;
3252 * If the user space waits to inject interrupts, exit as soon as
3255 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
3256 kvm_run
->request_interrupt_window
&&
3257 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
3258 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3265 static int pause_interception(struct vcpu_svm
*svm
)
3267 kvm_vcpu_on_spin(&(svm
->vcpu
));
3271 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3272 [SVM_EXIT_READ_CR0
] = cr_interception
,
3273 [SVM_EXIT_READ_CR3
] = cr_interception
,
3274 [SVM_EXIT_READ_CR4
] = cr_interception
,
3275 [SVM_EXIT_READ_CR8
] = cr_interception
,
3276 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
3277 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3278 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3279 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3280 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3281 [SVM_EXIT_READ_DR0
] = dr_interception
,
3282 [SVM_EXIT_READ_DR1
] = dr_interception
,
3283 [SVM_EXIT_READ_DR2
] = dr_interception
,
3284 [SVM_EXIT_READ_DR3
] = dr_interception
,
3285 [SVM_EXIT_READ_DR4
] = dr_interception
,
3286 [SVM_EXIT_READ_DR5
] = dr_interception
,
3287 [SVM_EXIT_READ_DR6
] = dr_interception
,
3288 [SVM_EXIT_READ_DR7
] = dr_interception
,
3289 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3290 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3291 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3292 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3293 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3294 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3295 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3296 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3297 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3298 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3299 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3300 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3301 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3302 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3303 [SVM_EXIT_INTR
] = intr_interception
,
3304 [SVM_EXIT_NMI
] = nmi_interception
,
3305 [SVM_EXIT_SMI
] = nop_on_interception
,
3306 [SVM_EXIT_INIT
] = nop_on_interception
,
3307 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3308 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3309 [SVM_EXIT_CPUID
] = cpuid_interception
,
3310 [SVM_EXIT_IRET
] = iret_interception
,
3311 [SVM_EXIT_INVD
] = emulate_on_interception
,
3312 [SVM_EXIT_PAUSE
] = pause_interception
,
3313 [SVM_EXIT_HLT
] = halt_interception
,
3314 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3315 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3316 [SVM_EXIT_IOIO
] = io_interception
,
3317 [SVM_EXIT_MSR
] = msr_interception
,
3318 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3319 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3320 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3321 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3322 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3323 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3324 [SVM_EXIT_STGI
] = stgi_interception
,
3325 [SVM_EXIT_CLGI
] = clgi_interception
,
3326 [SVM_EXIT_SKINIT
] = skinit_interception
,
3327 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
3328 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
3329 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
3330 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3331 [SVM_EXIT_NPF
] = pf_interception
,
3334 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3336 struct vcpu_svm
*svm
= to_svm(vcpu
);
3337 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3338 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3340 pr_err("VMCB Control Area:\n");
3341 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
3342 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
3343 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
3344 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
3345 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
3346 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
3347 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3348 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3349 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3350 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3351 pr_err("%-20s%d\n", "asid:", control
->asid
);
3352 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3353 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3354 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3355 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3356 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3357 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3358 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3359 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3360 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3361 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3362 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3363 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3364 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3365 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
3366 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3367 pr_err("VMCB State Save Area:\n");
3368 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3370 save
->es
.selector
, save
->es
.attrib
,
3371 save
->es
.limit
, save
->es
.base
);
3372 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3374 save
->cs
.selector
, save
->cs
.attrib
,
3375 save
->cs
.limit
, save
->cs
.base
);
3376 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3378 save
->ss
.selector
, save
->ss
.attrib
,
3379 save
->ss
.limit
, save
->ss
.base
);
3380 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3382 save
->ds
.selector
, save
->ds
.attrib
,
3383 save
->ds
.limit
, save
->ds
.base
);
3384 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3386 save
->fs
.selector
, save
->fs
.attrib
,
3387 save
->fs
.limit
, save
->fs
.base
);
3388 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3390 save
->gs
.selector
, save
->gs
.attrib
,
3391 save
->gs
.limit
, save
->gs
.base
);
3392 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3394 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3395 save
->gdtr
.limit
, save
->gdtr
.base
);
3396 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3398 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3399 save
->ldtr
.limit
, save
->ldtr
.base
);
3400 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3402 save
->idtr
.selector
, save
->idtr
.attrib
,
3403 save
->idtr
.limit
, save
->idtr
.base
);
3404 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3406 save
->tr
.selector
, save
->tr
.attrib
,
3407 save
->tr
.limit
, save
->tr
.base
);
3408 pr_err("cpl: %d efer: %016llx\n",
3409 save
->cpl
, save
->efer
);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3412 pr_err("%-15s %016llx %-13s %016llx\n",
3413 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3414 pr_err("%-15s %016llx %-13s %016llx\n",
3415 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3416 pr_err("%-15s %016llx %-13s %016llx\n",
3417 "rip:", save
->rip
, "rflags:", save
->rflags
);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "rsp:", save
->rsp
, "rax:", save
->rax
);
3420 pr_err("%-15s %016llx %-13s %016llx\n",
3421 "star:", save
->star
, "lstar:", save
->lstar
);
3422 pr_err("%-15s %016llx %-13s %016llx\n",
3423 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3424 pr_err("%-15s %016llx %-13s %016llx\n",
3425 "kernel_gs_base:", save
->kernel_gs_base
,
3426 "sysenter_cs:", save
->sysenter_cs
);
3427 pr_err("%-15s %016llx %-13s %016llx\n",
3428 "sysenter_esp:", save
->sysenter_esp
,
3429 "sysenter_eip:", save
->sysenter_eip
);
3430 pr_err("%-15s %016llx %-13s %016llx\n",
3431 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3432 pr_err("%-15s %016llx %-13s %016llx\n",
3433 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3434 pr_err("%-15s %016llx %-13s %016llx\n",
3435 "excp_from:", save
->last_excp_from
,
3436 "excp_to:", save
->last_excp_to
);
3439 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3441 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3443 *info1
= control
->exit_info_1
;
3444 *info2
= control
->exit_info_2
;
3447 static int handle_exit(struct kvm_vcpu
*vcpu
)
3449 struct vcpu_svm
*svm
= to_svm(vcpu
);
3450 struct kvm_run
*kvm_run
= vcpu
->run
;
3451 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3453 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3454 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3456 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3458 if (unlikely(svm
->nested
.exit_required
)) {
3459 nested_svm_vmexit(svm
);
3460 svm
->nested
.exit_required
= false;
3465 if (is_guest_mode(vcpu
)) {
3468 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3469 svm
->vmcb
->control
.exit_info_1
,
3470 svm
->vmcb
->control
.exit_info_2
,
3471 svm
->vmcb
->control
.exit_int_info
,
3472 svm
->vmcb
->control
.exit_int_info_err
,
3475 vmexit
= nested_svm_exit_special(svm
);
3477 if (vmexit
== NESTED_EXIT_CONTINUE
)
3478 vmexit
= nested_svm_exit_handled(svm
);
3480 if (vmexit
== NESTED_EXIT_DONE
)
3484 svm_complete_interrupts(svm
);
3486 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3487 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3488 kvm_run
->fail_entry
.hardware_entry_failure_reason
3489 = svm
->vmcb
->control
.exit_code
;
3490 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3495 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3496 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3497 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3498 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3499 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3501 __func__
, svm
->vmcb
->control
.exit_int_info
,
3504 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3505 || !svm_exit_handlers
[exit_code
]) {
3506 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3507 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3511 return svm_exit_handlers
[exit_code
](svm
);
3514 static void reload_tss(struct kvm_vcpu
*vcpu
)
3516 int cpu
= raw_smp_processor_id();
3518 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3519 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3523 static void pre_svm_run(struct vcpu_svm
*svm
)
3525 int cpu
= raw_smp_processor_id();
3527 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3529 /* FIXME: handle wraparound of asid_generation */
3530 if (svm
->asid_generation
!= sd
->asid_generation
)
3534 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3536 struct vcpu_svm
*svm
= to_svm(vcpu
);
3538 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3539 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3540 set_intercept(svm
, INTERCEPT_IRET
);
3541 ++vcpu
->stat
.nmi_injections
;
3544 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3546 struct vmcb_control_area
*control
;
3548 control
= &svm
->vmcb
->control
;
3549 control
->int_vector
= irq
;
3550 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3551 control
->int_ctl
|= V_IRQ_MASK
|
3552 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3553 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3556 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3558 struct vcpu_svm
*svm
= to_svm(vcpu
);
3560 BUG_ON(!(gif_set(svm
)));
3562 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3563 ++vcpu
->stat
.irq_injections
;
3565 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3566 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3569 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3571 struct vcpu_svm
*svm
= to_svm(vcpu
);
3573 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3580 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3583 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3585 struct vcpu_svm
*svm
= to_svm(vcpu
);
3586 struct vmcb
*vmcb
= svm
->vmcb
;
3588 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3589 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3590 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3595 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3597 struct vcpu_svm
*svm
= to_svm(vcpu
);
3599 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3602 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3604 struct vcpu_svm
*svm
= to_svm(vcpu
);
3607 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3608 set_intercept(svm
, INTERCEPT_IRET
);
3610 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3611 clr_intercept(svm
, INTERCEPT_IRET
);
3615 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3617 struct vcpu_svm
*svm
= to_svm(vcpu
);
3618 struct vmcb
*vmcb
= svm
->vmcb
;
3621 if (!gif_set(svm
) ||
3622 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3625 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
3627 if (is_guest_mode(vcpu
))
3628 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3633 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3635 struct vcpu_svm
*svm
= to_svm(vcpu
);
3638 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3639 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3640 * get that intercept, this function will be called again though and
3641 * we'll get the vintr intercept.
3643 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3645 svm_inject_irq(svm
, 0x0);
3649 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3651 struct vcpu_svm
*svm
= to_svm(vcpu
);
3653 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3655 return; /* IRET will cause a vm exit */
3658 * Something prevents NMI from been injected. Single step over possible
3659 * problem (IRET or exception injection or interrupt shadow)
3661 svm
->nmi_singlestep
= true;
3662 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3663 update_db_intercept(vcpu
);
3666 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3671 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3673 struct vcpu_svm
*svm
= to_svm(vcpu
);
3675 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3676 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3678 svm
->asid_generation
--;
3681 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3685 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3687 struct vcpu_svm
*svm
= to_svm(vcpu
);
3689 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3692 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3693 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3694 kvm_set_cr8(vcpu
, cr8
);
3698 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3700 struct vcpu_svm
*svm
= to_svm(vcpu
);
3703 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3706 cr8
= kvm_get_cr8(vcpu
);
3707 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3708 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3711 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3715 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3716 unsigned int3_injected
= svm
->int3_injected
;
3718 svm
->int3_injected
= 0;
3721 * If we've made progress since setting HF_IRET_MASK, we've
3722 * executed an IRET and can allow NMI injection.
3724 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3725 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
3726 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3727 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3730 svm
->vcpu
.arch
.nmi_injected
= false;
3731 kvm_clear_exception_queue(&svm
->vcpu
);
3732 kvm_clear_interrupt_queue(&svm
->vcpu
);
3734 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3737 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3739 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3740 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3743 case SVM_EXITINTINFO_TYPE_NMI
:
3744 svm
->vcpu
.arch
.nmi_injected
= true;
3746 case SVM_EXITINTINFO_TYPE_EXEPT
:
3748 * In case of software exceptions, do not reinject the vector,
3749 * but re-execute the instruction instead. Rewind RIP first
3750 * if we emulated INT3 before.
3752 if (kvm_exception_is_soft(vector
)) {
3753 if (vector
== BP_VECTOR
&& int3_injected
&&
3754 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3755 kvm_rip_write(&svm
->vcpu
,
3756 kvm_rip_read(&svm
->vcpu
) -
3760 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3761 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3762 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3765 kvm_requeue_exception(&svm
->vcpu
, vector
);
3767 case SVM_EXITINTINFO_TYPE_INTR
:
3768 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3775 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3777 struct vcpu_svm
*svm
= to_svm(vcpu
);
3778 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3780 control
->exit_int_info
= control
->event_inj
;
3781 control
->exit_int_info_err
= control
->event_inj_err
;
3782 control
->event_inj
= 0;
3783 svm_complete_interrupts(svm
);
3786 #ifdef CONFIG_X86_64
3792 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3794 struct vcpu_svm
*svm
= to_svm(vcpu
);
3796 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3797 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3798 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3801 * A vmexit emulation is required before the vcpu can be executed
3804 if (unlikely(svm
->nested
.exit_required
))
3809 sync_lapic_to_cr8(vcpu
);
3811 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3818 "push %%"R
"bp; \n\t"
3819 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3820 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3821 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3822 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3823 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3824 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3825 #ifdef CONFIG_X86_64
3826 "mov %c[r8](%[svm]), %%r8 \n\t"
3827 "mov %c[r9](%[svm]), %%r9 \n\t"
3828 "mov %c[r10](%[svm]), %%r10 \n\t"
3829 "mov %c[r11](%[svm]), %%r11 \n\t"
3830 "mov %c[r12](%[svm]), %%r12 \n\t"
3831 "mov %c[r13](%[svm]), %%r13 \n\t"
3832 "mov %c[r14](%[svm]), %%r14 \n\t"
3833 "mov %c[r15](%[svm]), %%r15 \n\t"
3836 /* Enter guest mode */
3838 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3839 __ex(SVM_VMLOAD
) "\n\t"
3840 __ex(SVM_VMRUN
) "\n\t"
3841 __ex(SVM_VMSAVE
) "\n\t"
3844 /* Save guest registers, load host registers */
3845 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3846 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3847 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3848 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3849 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3850 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3851 #ifdef CONFIG_X86_64
3852 "mov %%r8, %c[r8](%[svm]) \n\t"
3853 "mov %%r9, %c[r9](%[svm]) \n\t"
3854 "mov %%r10, %c[r10](%[svm]) \n\t"
3855 "mov %%r11, %c[r11](%[svm]) \n\t"
3856 "mov %%r12, %c[r12](%[svm]) \n\t"
3857 "mov %%r13, %c[r13](%[svm]) \n\t"
3858 "mov %%r14, %c[r14](%[svm]) \n\t"
3859 "mov %%r15, %c[r15](%[svm]) \n\t"
3864 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3865 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3866 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3867 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3868 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3869 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3870 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3871 #ifdef CONFIG_X86_64
3872 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3873 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3874 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3875 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3876 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3877 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3878 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3879 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3882 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3883 #ifdef CONFIG_X86_64
3884 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3888 #ifdef CONFIG_X86_64
3889 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3891 loadsegment(fs
, svm
->host
.fs
);
3892 #ifndef CONFIG_X86_32_LAZY_GS
3893 loadsegment(gs
, svm
->host
.gs
);
3899 local_irq_disable();
3901 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3902 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3903 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3904 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3906 trace_kvm_exit(svm
->vmcb
->control
.exit_code
, vcpu
, KVM_ISA_SVM
);
3908 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3909 kvm_before_handle_nmi(&svm
->vcpu
);
3913 /* Any pending NMI will happen here */
3915 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3916 kvm_after_handle_nmi(&svm
->vcpu
);
3918 sync_cr8_to_lapic(vcpu
);
3922 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3924 /* if exit due to PF check for async PF */
3925 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3926 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3929 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3930 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3934 * We need to handle MC intercepts here before the vcpu has a chance to
3935 * change the physical cpu
3937 if (unlikely(svm
->vmcb
->control
.exit_code
==
3938 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3939 svm_handle_mce(svm
);
3941 mark_all_clean(svm
->vmcb
);
3946 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3948 struct vcpu_svm
*svm
= to_svm(vcpu
);
3950 svm
->vmcb
->save
.cr3
= root
;
3951 mark_dirty(svm
->vmcb
, VMCB_CR
);
3952 svm_flush_tlb(vcpu
);
3955 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3957 struct vcpu_svm
*svm
= to_svm(vcpu
);
3959 svm
->vmcb
->control
.nested_cr3
= root
;
3960 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3962 /* Also sync guest cr3 here in case we live migrate */
3963 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
3964 mark_dirty(svm
->vmcb
, VMCB_CR
);
3966 svm_flush_tlb(vcpu
);
3969 static int is_disabled(void)
3973 rdmsrl(MSR_VM_CR
, vm_cr
);
3974 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3981 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3984 * Patch in the VMMCALL instruction:
3986 hypercall
[0] = 0x0f;
3987 hypercall
[1] = 0x01;
3988 hypercall
[2] = 0xd9;
3991 static void svm_check_processor_compat(void *rtn
)
3996 static bool svm_cpu_has_accelerated_tpr(void)
4001 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4006 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
4010 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4015 entry
->ecx
|= (1 << 2); /* Set SVM bit */
4018 entry
->eax
= 1; /* SVM revision 1 */
4019 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
4020 ASID emulation to nested SVM */
4021 entry
->ecx
= 0; /* Reserved */
4022 entry
->edx
= 0; /* Per default do not support any
4023 additional features */
4025 /* Support next_rip if host supports it */
4026 if (boot_cpu_has(X86_FEATURE_NRIPS
))
4027 entry
->edx
|= SVM_FEATURE_NRIP
;
4029 /* Support NPT for the guest if enabled */
4031 entry
->edx
|= SVM_FEATURE_NPT
;
4037 static int svm_get_lpage_level(void)
4039 return PT_PDPE_LEVEL
;
4042 static bool svm_rdtscp_supported(void)
4047 static bool svm_invpcid_supported(void)
4052 static bool svm_has_wbinvd_exit(void)
4057 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
4059 struct vcpu_svm
*svm
= to_svm(vcpu
);
4061 set_exception_intercept(svm
, NM_VECTOR
);
4062 update_cr0_intercept(svm
);
4065 #define PRE_EX(exit) { .exit_code = (exit), \
4066 .stage = X86_ICPT_PRE_EXCEPT, }
4067 #define POST_EX(exit) { .exit_code = (exit), \
4068 .stage = X86_ICPT_POST_EXCEPT, }
4069 #define POST_MEM(exit) { .exit_code = (exit), \
4070 .stage = X86_ICPT_POST_MEMACCESS, }
4072 static struct __x86_intercept
{
4074 enum x86_intercept_stage stage
;
4075 } x86_intercept_map
[] = {
4076 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4077 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4078 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4079 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4080 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4081 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4082 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4083 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4084 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4085 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4086 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4087 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4088 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4089 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4090 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4091 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4092 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4093 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4094 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4095 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4096 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4097 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4098 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4099 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4100 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4101 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4102 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4103 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4104 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4105 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4106 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4107 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4108 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4109 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4110 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4111 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4112 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4113 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4114 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4115 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4116 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4117 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4118 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4119 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4120 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4121 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4128 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4129 struct x86_instruction_info
*info
,
4130 enum x86_intercept_stage stage
)
4132 struct vcpu_svm
*svm
= to_svm(vcpu
);
4133 int vmexit
, ret
= X86EMUL_CONTINUE
;
4134 struct __x86_intercept icpt_info
;
4135 struct vmcb
*vmcb
= svm
->vmcb
;
4137 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4140 icpt_info
= x86_intercept_map
[info
->intercept
];
4142 if (stage
!= icpt_info
.stage
)
4145 switch (icpt_info
.exit_code
) {
4146 case SVM_EXIT_READ_CR0
:
4147 if (info
->intercept
== x86_intercept_cr_read
)
4148 icpt_info
.exit_code
+= info
->modrm_reg
;
4150 case SVM_EXIT_WRITE_CR0
: {
4151 unsigned long cr0
, val
;
4154 if (info
->intercept
== x86_intercept_cr_write
)
4155 icpt_info
.exit_code
+= info
->modrm_reg
;
4157 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
)
4160 intercept
= svm
->nested
.intercept
;
4162 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
4165 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4166 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4168 if (info
->intercept
== x86_intercept_lmsw
) {
4171 /* lmsw can't clear PE - catch this here */
4172 if (cr0
& X86_CR0_PE
)
4177 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4181 case SVM_EXIT_READ_DR0
:
4182 case SVM_EXIT_WRITE_DR0
:
4183 icpt_info
.exit_code
+= info
->modrm_reg
;
4186 if (info
->intercept
== x86_intercept_wrmsr
)
4187 vmcb
->control
.exit_info_1
= 1;
4189 vmcb
->control
.exit_info_1
= 0;
4191 case SVM_EXIT_PAUSE
:
4193 * We get this for NOP only, but pause
4194 * is rep not, check this here
4196 if (info
->rep_prefix
!= REPE_PREFIX
)
4198 case SVM_EXIT_IOIO
: {
4202 exit_info
= (vcpu
->arch
.regs
[VCPU_REGS_RDX
] & 0xffff) << 16;
4204 if (info
->intercept
== x86_intercept_in
||
4205 info
->intercept
== x86_intercept_ins
) {
4206 exit_info
|= SVM_IOIO_TYPE_MASK
;
4207 bytes
= info
->src_bytes
;
4209 bytes
= info
->dst_bytes
;
4212 if (info
->intercept
== x86_intercept_outs
||
4213 info
->intercept
== x86_intercept_ins
)
4214 exit_info
|= SVM_IOIO_STR_MASK
;
4216 if (info
->rep_prefix
)
4217 exit_info
|= SVM_IOIO_REP_MASK
;
4219 bytes
= min(bytes
, 4u);
4221 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4223 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4225 vmcb
->control
.exit_info_1
= exit_info
;
4226 vmcb
->control
.exit_info_2
= info
->next_rip
;
4234 vmcb
->control
.next_rip
= info
->next_rip
;
4235 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4236 vmexit
= nested_svm_exit_handled(svm
);
4238 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4245 static struct kvm_x86_ops svm_x86_ops
= {
4246 .cpu_has_kvm_support
= has_svm
,
4247 .disabled_by_bios
= is_disabled
,
4248 .hardware_setup
= svm_hardware_setup
,
4249 .hardware_unsetup
= svm_hardware_unsetup
,
4250 .check_processor_compatibility
= svm_check_processor_compat
,
4251 .hardware_enable
= svm_hardware_enable
,
4252 .hardware_disable
= svm_hardware_disable
,
4253 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4255 .vcpu_create
= svm_create_vcpu
,
4256 .vcpu_free
= svm_free_vcpu
,
4257 .vcpu_reset
= svm_vcpu_reset
,
4259 .prepare_guest_switch
= svm_prepare_guest_switch
,
4260 .vcpu_load
= svm_vcpu_load
,
4261 .vcpu_put
= svm_vcpu_put
,
4263 .set_guest_debug
= svm_guest_debug
,
4264 .get_msr
= svm_get_msr
,
4265 .set_msr
= svm_set_msr
,
4266 .get_segment_base
= svm_get_segment_base
,
4267 .get_segment
= svm_get_segment
,
4268 .set_segment
= svm_set_segment
,
4269 .get_cpl
= svm_get_cpl
,
4270 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4271 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
4272 .decache_cr3
= svm_decache_cr3
,
4273 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
4274 .set_cr0
= svm_set_cr0
,
4275 .set_cr3
= svm_set_cr3
,
4276 .set_cr4
= svm_set_cr4
,
4277 .set_efer
= svm_set_efer
,
4278 .get_idt
= svm_get_idt
,
4279 .set_idt
= svm_set_idt
,
4280 .get_gdt
= svm_get_gdt
,
4281 .set_gdt
= svm_set_gdt
,
4282 .set_dr7
= svm_set_dr7
,
4283 .cache_reg
= svm_cache_reg
,
4284 .get_rflags
= svm_get_rflags
,
4285 .set_rflags
= svm_set_rflags
,
4286 .fpu_activate
= svm_fpu_activate
,
4287 .fpu_deactivate
= svm_fpu_deactivate
,
4289 .tlb_flush
= svm_flush_tlb
,
4291 .run
= svm_vcpu_run
,
4292 .handle_exit
= handle_exit
,
4293 .skip_emulated_instruction
= skip_emulated_instruction
,
4294 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4295 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4296 .patch_hypercall
= svm_patch_hypercall
,
4297 .set_irq
= svm_set_irq
,
4298 .set_nmi
= svm_inject_nmi
,
4299 .queue_exception
= svm_queue_exception
,
4300 .cancel_injection
= svm_cancel_injection
,
4301 .interrupt_allowed
= svm_interrupt_allowed
,
4302 .nmi_allowed
= svm_nmi_allowed
,
4303 .get_nmi_mask
= svm_get_nmi_mask
,
4304 .set_nmi_mask
= svm_set_nmi_mask
,
4305 .enable_nmi_window
= enable_nmi_window
,
4306 .enable_irq_window
= enable_irq_window
,
4307 .update_cr8_intercept
= update_cr8_intercept
,
4309 .set_tss_addr
= svm_set_tss_addr
,
4310 .get_tdp_level
= get_npt_level
,
4311 .get_mt_mask
= svm_get_mt_mask
,
4313 .get_exit_info
= svm_get_exit_info
,
4315 .get_lpage_level
= svm_get_lpage_level
,
4317 .cpuid_update
= svm_cpuid_update
,
4319 .rdtscp_supported
= svm_rdtscp_supported
,
4320 .invpcid_supported
= svm_invpcid_supported
,
4322 .set_supported_cpuid
= svm_set_supported_cpuid
,
4324 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4326 .set_tsc_khz
= svm_set_tsc_khz
,
4327 .write_tsc_offset
= svm_write_tsc_offset
,
4328 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
4329 .compute_tsc_offset
= svm_compute_tsc_offset
,
4330 .read_l1_tsc
= svm_read_l1_tsc
,
4332 .set_tdp_cr3
= set_tdp_cr3
,
4334 .check_intercept
= svm_check_intercept
,
4337 static int __init
svm_init(void)
4339 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
4340 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4343 static void __exit
svm_exit(void)
4348 module_init(svm_init
)
4349 module_exit(svm_exit
)