2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
66 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly
;
123 static const u32 host_save_user_msrs
[] = {
125 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
128 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info
{
135 bool active
; /* SEV enabled guest */
136 unsigned int asid
; /* ASID used for this guest */
137 unsigned int handle
; /* SEV firmware handle */
138 int fd
; /* SEV device fd */
139 unsigned long pages_locked
; /* Number of pages locked */
140 struct list_head regions_list
; /* List of registered regions */
146 /* Struct members for AVIC */
149 struct page
*avic_logical_id_table_page
;
150 struct page
*avic_physical_id_table_page
;
151 struct hlist_node hnode
;
153 struct kvm_sev_info sev_info
;
158 struct nested_state
{
164 /* These are the merged vectors */
167 /* gpa pointers to the real vectors */
171 /* A VMEXIT is required but not yet emulated */
174 /* cache for intercepts of the guest */
177 u32 intercept_exceptions
;
180 /* Nested Paging related state */
184 #define MSRPM_OFFSETS 16
185 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
188 * Set osvw_len to higher value when updated Revision Guides
189 * are published and we know what the new status bits are
191 static uint64_t osvw_len
= 4, osvw_status
;
194 struct kvm_vcpu vcpu
;
196 unsigned long vmcb_pa
;
197 struct svm_cpu_data
*svm_data
;
198 uint64_t asid_generation
;
199 uint64_t sysenter_esp
;
200 uint64_t sysenter_eip
;
207 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
217 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
218 * translated into the appropriate L2_CFG bits on the host to
219 * perform speculative control.
227 struct nested_state nested
;
230 u64 nmi_singlestep_guest_rflags
;
232 unsigned int3_injected
;
233 unsigned long int3_rip
;
235 /* cached guest cpuid flags for faster access */
236 bool nrips_enabled
: 1;
239 struct page
*avic_backing_page
;
240 u64
*avic_physical_id_cache
;
241 bool avic_is_running
;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list
;
250 spinlock_t ir_list_lock
;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu
;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir
{
260 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
261 void *data
; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
272 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
273 #define TSC_RATIO_DEFAULT 0x0100000000ULL
275 #define MSR_INVALID 0xffffffffU
277 static const struct svm_direct_access_msrs
{
278 u32 index
; /* Index of the MSR */
279 bool always
; /* True if intercept is always on */
280 } direct_access_msrs
[] = {
281 { .index
= MSR_STAR
, .always
= true },
282 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
284 { .index
= MSR_GS_BASE
, .always
= true },
285 { .index
= MSR_FS_BASE
, .always
= true },
286 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
287 { .index
= MSR_LSTAR
, .always
= true },
288 { .index
= MSR_CSTAR
, .always
= true },
289 { .index
= MSR_SYSCALL_MASK
, .always
= true },
291 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
292 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
293 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
294 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
295 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
296 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
297 { .index
= MSR_INVALID
, .always
= false },
300 /* enable NPT for AMD64 and X86 with PAE */
301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
302 static bool npt_enabled
= true;
304 static bool npt_enabled
;
308 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
309 * pause_filter_count: On processors that support Pause filtering(indicated
310 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
311 * count value. On VMRUN this value is loaded into an internal counter.
312 * Each time a pause instruction is executed, this counter is decremented
313 * until it reaches zero at which time a #VMEXIT is generated if pause
314 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
315 * Intercept Filtering for more details.
316 * This also indicate if ple logic enabled.
318 * pause_filter_thresh: In addition, some processor families support advanced
319 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
320 * the amount of time a guest is allowed to execute in a pause loop.
321 * In this mode, a 16-bit pause filter threshold field is added in the
322 * VMCB. The threshold value is a cycle count that is used to reset the
323 * pause counter. As with simple pause filtering, VMRUN loads the pause
324 * count value from VMCB into an internal counter. Then, on each pause
325 * instruction the hardware checks the elapsed number of cycles since
326 * the most recent pause instruction against the pause filter threshold.
327 * If the elapsed cycle count is greater than the pause filter threshold,
328 * then the internal pause count is reloaded from the VMCB and execution
329 * continues. If the elapsed cycle count is less than the pause filter
330 * threshold, then the internal pause count is decremented. If the count
331 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
332 * triggered. If advanced pause filtering is supported and pause filter
333 * threshold field is set to zero, the filter will operate in the simpler,
337 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
338 module_param(pause_filter_thresh
, ushort
, 0444);
340 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
341 module_param(pause_filter_count
, ushort
, 0444);
343 /* Default doubles per-vcpu window every exit. */
344 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
345 module_param(pause_filter_count_grow
, ushort
, 0444);
347 /* Default resets per-vcpu window every exit to pause_filter_count. */
348 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
349 module_param(pause_filter_count_shrink
, ushort
, 0444);
351 /* Default is to compute the maximum so we can never overflow. */
352 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
353 module_param(pause_filter_count_max
, ushort
, 0444);
355 /* allow nested paging (virtualized MMU) for all guests */
356 static int npt
= true;
357 module_param(npt
, int, S_IRUGO
);
359 /* allow nested virtualization in KVM/SVM */
360 static int nested
= true;
361 module_param(nested
, int, S_IRUGO
);
363 /* enable / disable AVIC */
365 #ifdef CONFIG_X86_LOCAL_APIC
366 module_param(avic
, int, S_IRUGO
);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls
= true;
371 module_param(vls
, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif
= true;
375 module_param(vgif
, int, 0444);
377 /* enable/disable SEV support */
378 static int sev
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
379 module_param(sev
, int, 0444);
381 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
383 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
384 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
);
385 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
387 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
388 static int nested_svm_intercept(struct vcpu_svm
*svm
);
389 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
390 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
391 bool has_error_code
, u32 error_code
);
394 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
395 pause filter count */
396 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
397 VMCB_ASID
, /* ASID */
398 VMCB_INTR
, /* int_ctl, int_vector */
399 VMCB_NPT
, /* npt_en, nCR3, gPAT */
400 VMCB_CR
, /* CR0, CR3, CR4, EFER */
401 VMCB_DR
, /* DR6, DR7 */
402 VMCB_DT
, /* GDT, IDT */
403 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
404 VMCB_CR2
, /* CR2 only */
405 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
406 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
407 * AVIC PHYSICAL_TABLE pointer,
408 * AVIC LOGICAL_TABLE pointer
413 /* TPR and CR2 are always written before VMRUN */
414 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
416 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
418 static unsigned int max_sev_asid
;
419 static unsigned int min_sev_asid
;
420 static unsigned long *sev_asid_bitmap
;
421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
424 struct list_head list
;
425 unsigned long npages
;
432 static inline struct kvm_svm
*to_kvm_svm(struct kvm
*kvm
)
434 return container_of(kvm
, struct kvm_svm
, kvm
);
437 static inline bool svm_sev_enabled(void)
439 return IS_ENABLED(CONFIG_KVM_AMD_SEV
) ? max_sev_asid
: 0;
442 static inline bool sev_guest(struct kvm
*kvm
)
444 #ifdef CONFIG_KVM_AMD_SEV
445 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
453 static inline int sev_get_asid(struct kvm
*kvm
)
455 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
460 static inline void mark_all_dirty(struct vmcb
*vmcb
)
462 vmcb
->control
.clean
= 0;
465 static inline void mark_all_clean(struct vmcb
*vmcb
)
467 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
468 & ~VMCB_ALWAYS_DIRTY_MASK
;
471 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
473 vmcb
->control
.clean
&= ~(1 << bit
);
476 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
478 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
481 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
483 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
484 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
487 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
489 struct vcpu_svm
*svm
= to_svm(vcpu
);
490 u64
*entry
= svm
->avic_physical_id_cache
;
495 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
498 static void recalc_intercepts(struct vcpu_svm
*svm
)
500 struct vmcb_control_area
*c
, *h
;
501 struct nested_state
*g
;
503 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
505 if (!is_guest_mode(&svm
->vcpu
))
508 c
= &svm
->vmcb
->control
;
509 h
= &svm
->nested
.hsave
->control
;
512 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
513 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
514 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
515 c
->intercept
= h
->intercept
| g
->intercept
;
518 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
520 if (is_guest_mode(&svm
->vcpu
))
521 return svm
->nested
.hsave
;
526 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
528 struct vmcb
*vmcb
= get_host_vmcb(svm
);
530 vmcb
->control
.intercept_cr
|= (1U << bit
);
532 recalc_intercepts(svm
);
535 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
537 struct vmcb
*vmcb
= get_host_vmcb(svm
);
539 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
541 recalc_intercepts(svm
);
544 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
546 struct vmcb
*vmcb
= get_host_vmcb(svm
);
548 return vmcb
->control
.intercept_cr
& (1U << bit
);
551 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
553 struct vmcb
*vmcb
= get_host_vmcb(svm
);
555 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
556 | (1 << INTERCEPT_DR1_READ
)
557 | (1 << INTERCEPT_DR2_READ
)
558 | (1 << INTERCEPT_DR3_READ
)
559 | (1 << INTERCEPT_DR4_READ
)
560 | (1 << INTERCEPT_DR5_READ
)
561 | (1 << INTERCEPT_DR6_READ
)
562 | (1 << INTERCEPT_DR7_READ
)
563 | (1 << INTERCEPT_DR0_WRITE
)
564 | (1 << INTERCEPT_DR1_WRITE
)
565 | (1 << INTERCEPT_DR2_WRITE
)
566 | (1 << INTERCEPT_DR3_WRITE
)
567 | (1 << INTERCEPT_DR4_WRITE
)
568 | (1 << INTERCEPT_DR5_WRITE
)
569 | (1 << INTERCEPT_DR6_WRITE
)
570 | (1 << INTERCEPT_DR7_WRITE
);
572 recalc_intercepts(svm
);
575 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
577 struct vmcb
*vmcb
= get_host_vmcb(svm
);
579 vmcb
->control
.intercept_dr
= 0;
581 recalc_intercepts(svm
);
584 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
586 struct vmcb
*vmcb
= get_host_vmcb(svm
);
588 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
590 recalc_intercepts(svm
);
593 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
595 struct vmcb
*vmcb
= get_host_vmcb(svm
);
597 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
599 recalc_intercepts(svm
);
602 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
604 struct vmcb
*vmcb
= get_host_vmcb(svm
);
606 vmcb
->control
.intercept
|= (1ULL << bit
);
608 recalc_intercepts(svm
);
611 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
613 struct vmcb
*vmcb
= get_host_vmcb(svm
);
615 vmcb
->control
.intercept
&= ~(1ULL << bit
);
617 recalc_intercepts(svm
);
620 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
622 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
625 static inline void enable_gif(struct vcpu_svm
*svm
)
627 if (vgif_enabled(svm
))
628 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
630 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
633 static inline void disable_gif(struct vcpu_svm
*svm
)
635 if (vgif_enabled(svm
))
636 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
638 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
641 static inline bool gif_set(struct vcpu_svm
*svm
)
643 if (vgif_enabled(svm
))
644 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
646 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
649 static unsigned long iopm_base
;
651 struct kvm_ldttss_desc
{
654 unsigned base1
:8, type
:5, dpl
:2, p
:1;
655 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
658 } __attribute__((packed
));
660 struct svm_cpu_data
{
667 struct kvm_ldttss_desc
*tss_desc
;
669 struct page
*save_area
;
670 struct vmcb
*current_vmcb
;
672 /* index = sev_asid, value = vmcb pointer */
673 struct vmcb
**sev_vmcbs
;
676 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
678 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
680 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
681 #define MSRS_RANGE_SIZE 2048
682 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
684 static u32
svm_msrpm_offset(u32 msr
)
689 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
690 if (msr
< msrpm_ranges
[i
] ||
691 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
694 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
695 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
697 /* Now we have the u8 offset - but need the u32 offset */
701 /* MSR not in any range */
705 #define MAX_INST_SIZE 15
707 static inline void clgi(void)
709 asm volatile (__ex("clgi"));
712 static inline void stgi(void)
714 asm volatile (__ex("stgi"));
717 static inline void invlpga(unsigned long addr
, u32 asid
)
719 asm volatile (__ex("invlpga %1, %0") : : "c"(asid
), "a"(addr
));
722 static int get_npt_level(struct kvm_vcpu
*vcpu
)
725 return PT64_ROOT_4LEVEL
;
727 return PT32E_ROOT_LEVEL
;
731 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
733 vcpu
->arch
.efer
= efer
;
734 if (!npt_enabled
&& !(efer
& EFER_LMA
))
737 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
738 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
741 static int is_external_interrupt(u32 info
)
743 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
744 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
747 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
749 struct vcpu_svm
*svm
= to_svm(vcpu
);
752 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
753 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
757 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
759 struct vcpu_svm
*svm
= to_svm(vcpu
);
762 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
764 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
768 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
770 struct vcpu_svm
*svm
= to_svm(vcpu
);
772 if (svm
->vmcb
->control
.next_rip
!= 0) {
773 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
774 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
777 if (!svm
->next_rip
) {
778 if (kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
780 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
783 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
784 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
785 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
787 kvm_rip_write(vcpu
, svm
->next_rip
);
788 svm_set_interrupt_shadow(vcpu
, 0);
791 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
793 struct vcpu_svm
*svm
= to_svm(vcpu
);
794 unsigned nr
= vcpu
->arch
.exception
.nr
;
795 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
796 bool reinject
= vcpu
->arch
.exception
.injected
;
797 u32 error_code
= vcpu
->arch
.exception
.error_code
;
800 * If we are within a nested VM we'd better #VMEXIT and let the guest
801 * handle the exception
804 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
807 kvm_deliver_exception_payload(&svm
->vcpu
);
809 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
810 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
813 * For guest debugging where we have to reinject #BP if some
814 * INT3 is guest-owned:
815 * Emulate nRIP by moving RIP forward. Will fail if injection
816 * raises a fault that is not intercepted. Still better than
817 * failing in all cases.
819 skip_emulated_instruction(&svm
->vcpu
);
820 rip
= kvm_rip_read(&svm
->vcpu
);
821 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
822 svm
->int3_injected
= rip
- old_rip
;
825 svm
->vmcb
->control
.event_inj
= nr
827 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
828 | SVM_EVTINJ_TYPE_EXEPT
;
829 svm
->vmcb
->control
.event_inj_err
= error_code
;
832 static void svm_init_erratum_383(void)
838 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
841 /* Use _safe variants to not break nested virtualization */
842 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
848 low
= lower_32_bits(val
);
849 high
= upper_32_bits(val
);
851 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
853 erratum_383_found
= true;
856 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
859 * Guests should see errata 400 and 415 as fixed (assuming that
860 * HLT and IO instructions are intercepted).
862 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
863 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
866 * By increasing VCPU's osvw.length to 3 we are telling the guest that
867 * all osvw.status bits inside that length, including bit 0 (which is
868 * reserved for erratum 298), are valid. However, if host processor's
869 * osvw_len is 0 then osvw_status[0] carries no information. We need to
870 * be conservative here and therefore we tell the guest that erratum 298
871 * is present (because we really don't know).
873 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
874 vcpu
->arch
.osvw
.status
|= 1;
877 static int has_svm(void)
881 if (!cpu_has_svm(&msg
)) {
882 printk(KERN_INFO
"has_svm: %s\n", msg
);
889 static void svm_hardware_disable(void)
891 /* Make sure we clean up behind us */
892 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
893 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
897 amd_pmu_disable_virt();
900 static int svm_hardware_enable(void)
903 struct svm_cpu_data
*sd
;
905 struct desc_struct
*gdt
;
906 int me
= raw_smp_processor_id();
908 rdmsrl(MSR_EFER
, efer
);
909 if (efer
& EFER_SVME
)
913 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
916 sd
= per_cpu(svm_data
, me
);
918 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
922 sd
->asid_generation
= 1;
923 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
924 sd
->next_asid
= sd
->max_asid
+ 1;
925 sd
->min_asid
= max_sev_asid
+ 1;
927 gdt
= get_current_gdt_rw();
928 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
930 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
932 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
934 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
935 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
936 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
943 * Note that it is possible to have a system with mixed processor
944 * revisions and therefore different OSVW bits. If bits are not the same
945 * on different processors then choose the worst case (i.e. if erratum
946 * is present on one processor and not on another then assume that the
947 * erratum is present everywhere).
949 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
950 uint64_t len
, status
= 0;
953 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
955 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
959 osvw_status
= osvw_len
= 0;
963 osvw_status
|= status
;
964 osvw_status
&= (1ULL << osvw_len
) - 1;
967 osvw_status
= osvw_len
= 0;
969 svm_init_erratum_383();
971 amd_pmu_enable_virt();
976 static void svm_cpu_uninit(int cpu
)
978 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
983 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
984 kfree(sd
->sev_vmcbs
);
985 __free_page(sd
->save_area
);
989 static int svm_cpu_init(int cpu
)
991 struct svm_cpu_data
*sd
;
994 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
999 sd
->save_area
= alloc_page(GFP_KERNEL
);
1003 if (svm_sev_enabled()) {
1005 sd
->sev_vmcbs
= kmalloc_array(max_sev_asid
+ 1,
1012 per_cpu(svm_data
, cpu
) = sd
;
1022 static bool valid_msr_intercept(u32 index
)
1026 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
1027 if (direct_access_msrs
[i
].index
== index
)
1033 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, unsigned msr
)
1040 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
1041 to_svm(vcpu
)->msrpm
;
1043 offset
= svm_msrpm_offset(msr
);
1044 bit_write
= 2 * (msr
& 0x0f) + 1;
1045 tmp
= msrpm
[offset
];
1047 BUG_ON(offset
== MSR_INVALID
);
1049 return !!test_bit(bit_write
, &tmp
);
1052 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
1053 int read
, int write
)
1055 u8 bit_read
, bit_write
;
1060 * If this warning triggers extend the direct_access_msrs list at the
1061 * beginning of the file
1063 WARN_ON(!valid_msr_intercept(msr
));
1065 offset
= svm_msrpm_offset(msr
);
1066 bit_read
= 2 * (msr
& 0x0f);
1067 bit_write
= 2 * (msr
& 0x0f) + 1;
1068 tmp
= msrpm
[offset
];
1070 BUG_ON(offset
== MSR_INVALID
);
1072 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
1073 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
1075 msrpm
[offset
] = tmp
;
1078 static void svm_vcpu_init_msrpm(u32
*msrpm
)
1082 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
1084 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1085 if (!direct_access_msrs
[i
].always
)
1088 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
1092 static void add_msr_offset(u32 offset
)
1096 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
1098 /* Offset already in list? */
1099 if (msrpm_offsets
[i
] == offset
)
1102 /* Slot used by another offset? */
1103 if (msrpm_offsets
[i
] != MSR_INVALID
)
1106 /* Add offset to list */
1107 msrpm_offsets
[i
] = offset
;
1113 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1114 * increase MSRPM_OFFSETS in this case.
1119 static void init_msrpm_offsets(void)
1123 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
1125 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1128 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
1129 BUG_ON(offset
== MSR_INVALID
);
1131 add_msr_offset(offset
);
1135 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
1137 u32
*msrpm
= svm
->msrpm
;
1139 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
1140 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
1141 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
1142 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
1143 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
1146 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
1148 u32
*msrpm
= svm
->msrpm
;
1150 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
1151 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
1152 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
1153 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
1154 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
1157 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
1159 svm
->nmi_singlestep
= false;
1161 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
1162 /* Clear our flags if they were not set by the guest */
1163 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1164 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
1165 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1166 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1171 * This hash table is used to map VM_ID to a struct kvm_svm,
1172 * when handling AMD IOMMU GALOG notification to schedule in
1173 * a particular vCPU.
1175 #define SVM_VM_DATA_HASH_BITS 8
1176 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1177 static u32 next_vm_id
= 0;
1178 static bool next_vm_id_wrapped
= 0;
1179 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1182 * This function is called from IOMMU driver to notify
1183 * SVM to schedule in a particular vCPU of a particular VM.
1185 static int avic_ga_log_notifier(u32 ga_tag
)
1187 unsigned long flags
;
1188 struct kvm_svm
*kvm_svm
;
1189 struct kvm_vcpu
*vcpu
= NULL
;
1190 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1191 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1193 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1195 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1196 hash_for_each_possible(svm_vm_data_hash
, kvm_svm
, hnode
, vm_id
) {
1197 if (kvm_svm
->avic_vm_id
!= vm_id
)
1199 vcpu
= kvm_get_vcpu_by_id(&kvm_svm
->kvm
, vcpu_id
);
1202 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1205 * At this point, the IOMMU should have already set the pending
1206 * bit in the vAPIC backing page. So, we just need to schedule
1210 kvm_vcpu_wake_up(vcpu
);
1215 static __init
int sev_hardware_setup(void)
1217 struct sev_user_data_status
*status
;
1220 /* Maximum number of encrypted guests supported simultaneously */
1221 max_sev_asid
= cpuid_ecx(0x8000001F);
1226 /* Minimum ASID value that should be used for SEV guest */
1227 min_sev_asid
= cpuid_edx(0x8000001F);
1229 /* Initialize SEV ASID bitmap */
1230 sev_asid_bitmap
= bitmap_zalloc(max_sev_asid
, GFP_KERNEL
);
1231 if (!sev_asid_bitmap
)
1234 status
= kmalloc(sizeof(*status
), GFP_KERNEL
);
1239 * Check SEV platform status.
1241 * PLATFORM_STATUS can be called in any state, if we failed to query
1242 * the PLATFORM status then either PSP firmware does not support SEV
1243 * feature or SEV firmware is dead.
1245 rc
= sev_platform_status(status
, NULL
);
1249 pr_info("SEV supported\n");
1256 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
1258 struct vcpu_svm
*svm
= to_svm(vcpu
);
1259 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1260 int old
= control
->pause_filter_count
;
1262 control
->pause_filter_count
= __grow_ple_window(old
,
1264 pause_filter_count_grow
,
1265 pause_filter_count_max
);
1267 if (control
->pause_filter_count
!= old
)
1268 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1270 trace_kvm_ple_window_grow(vcpu
->vcpu_id
,
1271 control
->pause_filter_count
, old
);
1274 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
1276 struct vcpu_svm
*svm
= to_svm(vcpu
);
1277 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1278 int old
= control
->pause_filter_count
;
1280 control
->pause_filter_count
=
1281 __shrink_ple_window(old
,
1283 pause_filter_count_shrink
,
1284 pause_filter_count
);
1285 if (control
->pause_filter_count
!= old
)
1286 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1288 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
,
1289 control
->pause_filter_count
, old
);
1292 static __init
int svm_hardware_setup(void)
1295 struct page
*iopm_pages
;
1299 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1304 iopm_va
= page_address(iopm_pages
);
1305 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1306 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1308 init_msrpm_offsets();
1310 if (boot_cpu_has(X86_FEATURE_NX
))
1311 kvm_enable_efer_bits(EFER_NX
);
1313 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1314 kvm_enable_efer_bits(EFER_FFXSR
);
1316 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1317 kvm_has_tsc_control
= true;
1318 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1319 kvm_tsc_scaling_ratio_frac_bits
= 32;
1322 /* Check for pause filtering support */
1323 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1324 pause_filter_count
= 0;
1325 pause_filter_thresh
= 0;
1326 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
1327 pause_filter_thresh
= 0;
1331 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1332 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1336 if (boot_cpu_has(X86_FEATURE_SEV
) &&
1337 IS_ENABLED(CONFIG_KVM_AMD_SEV
)) {
1338 r
= sev_hardware_setup();
1346 for_each_possible_cpu(cpu
) {
1347 r
= svm_cpu_init(cpu
);
1352 if (!boot_cpu_has(X86_FEATURE_NPT
))
1353 npt_enabled
= false;
1355 if (npt_enabled
&& !npt
) {
1356 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1357 npt_enabled
= false;
1361 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1368 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1369 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1372 pr_info("AVIC enabled\n");
1374 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1380 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1381 !IS_ENABLED(CONFIG_X86_64
)) {
1384 pr_info("Virtual VMLOAD VMSAVE supported\n");
1389 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1392 pr_info("Virtual GIF supported\n");
1398 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1403 static __exit
void svm_hardware_unsetup(void)
1407 if (svm_sev_enabled())
1408 bitmap_free(sev_asid_bitmap
);
1410 for_each_possible_cpu(cpu
)
1411 svm_cpu_uninit(cpu
);
1413 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1417 static void init_seg(struct vmcb_seg
*seg
)
1420 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1421 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1422 seg
->limit
= 0xffff;
1426 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1429 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1430 seg
->limit
= 0xffff;
1434 static u64
svm_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
1436 struct vcpu_svm
*svm
= to_svm(vcpu
);
1438 if (is_guest_mode(vcpu
))
1439 return svm
->nested
.hsave
->control
.tsc_offset
;
1441 return vcpu
->arch
.tsc_offset
;
1444 static u64
svm_write_l1_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1446 struct vcpu_svm
*svm
= to_svm(vcpu
);
1447 u64 g_tsc_offset
= 0;
1449 if (is_guest_mode(vcpu
)) {
1450 /* Write L1's TSC offset. */
1451 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1452 svm
->nested
.hsave
->control
.tsc_offset
;
1453 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1456 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1457 svm
->vmcb
->control
.tsc_offset
- g_tsc_offset
,
1460 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1462 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1463 return svm
->vmcb
->control
.tsc_offset
;
1466 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1468 struct vmcb
*vmcb
= svm
->vmcb
;
1469 struct kvm_svm
*kvm_svm
= to_kvm_svm(svm
->vcpu
.kvm
);
1470 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1471 phys_addr_t lpa
= __sme_set(page_to_phys(kvm_svm
->avic_logical_id_table_page
));
1472 phys_addr_t ppa
= __sme_set(page_to_phys(kvm_svm
->avic_physical_id_table_page
));
1474 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1475 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1476 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1477 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1478 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1481 static void init_vmcb(struct vcpu_svm
*svm
)
1483 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1484 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1486 svm
->vcpu
.arch
.hflags
= 0;
1488 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1489 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1490 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1491 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1492 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1493 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1494 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1495 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1497 set_dr_intercepts(svm
);
1499 set_exception_intercept(svm
, PF_VECTOR
);
1500 set_exception_intercept(svm
, UD_VECTOR
);
1501 set_exception_intercept(svm
, MC_VECTOR
);
1502 set_exception_intercept(svm
, AC_VECTOR
);
1503 set_exception_intercept(svm
, DB_VECTOR
);
1505 * Guest access to VMware backdoor ports could legitimately
1506 * trigger #GP because of TSS I/O permission bitmap.
1507 * We intercept those #GP and allow access to them anyway
1510 if (enable_vmware_backdoor
)
1511 set_exception_intercept(svm
, GP_VECTOR
);
1513 set_intercept(svm
, INTERCEPT_INTR
);
1514 set_intercept(svm
, INTERCEPT_NMI
);
1515 set_intercept(svm
, INTERCEPT_SMI
);
1516 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1517 set_intercept(svm
, INTERCEPT_RDPMC
);
1518 set_intercept(svm
, INTERCEPT_CPUID
);
1519 set_intercept(svm
, INTERCEPT_INVD
);
1520 set_intercept(svm
, INTERCEPT_INVLPG
);
1521 set_intercept(svm
, INTERCEPT_INVLPGA
);
1522 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1523 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1524 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1525 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1526 set_intercept(svm
, INTERCEPT_VMRUN
);
1527 set_intercept(svm
, INTERCEPT_VMMCALL
);
1528 set_intercept(svm
, INTERCEPT_VMLOAD
);
1529 set_intercept(svm
, INTERCEPT_VMSAVE
);
1530 set_intercept(svm
, INTERCEPT_STGI
);
1531 set_intercept(svm
, INTERCEPT_CLGI
);
1532 set_intercept(svm
, INTERCEPT_SKINIT
);
1533 set_intercept(svm
, INTERCEPT_WBINVD
);
1534 set_intercept(svm
, INTERCEPT_XSETBV
);
1535 set_intercept(svm
, INTERCEPT_RSM
);
1537 if (!kvm_mwait_in_guest(svm
->vcpu
.kvm
)) {
1538 set_intercept(svm
, INTERCEPT_MONITOR
);
1539 set_intercept(svm
, INTERCEPT_MWAIT
);
1542 if (!kvm_hlt_in_guest(svm
->vcpu
.kvm
))
1543 set_intercept(svm
, INTERCEPT_HLT
);
1545 control
->iopm_base_pa
= __sme_set(iopm_base
);
1546 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1547 control
->int_ctl
= V_INTR_MASKING_MASK
;
1549 init_seg(&save
->es
);
1550 init_seg(&save
->ss
);
1551 init_seg(&save
->ds
);
1552 init_seg(&save
->fs
);
1553 init_seg(&save
->gs
);
1555 save
->cs
.selector
= 0xf000;
1556 save
->cs
.base
= 0xffff0000;
1557 /* Executable/Readable Code Segment */
1558 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1559 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1560 save
->cs
.limit
= 0xffff;
1562 save
->gdtr
.limit
= 0xffff;
1563 save
->idtr
.limit
= 0xffff;
1565 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1566 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1568 svm_set_efer(&svm
->vcpu
, 0);
1569 save
->dr6
= 0xffff0ff0;
1570 kvm_set_rflags(&svm
->vcpu
, 2);
1571 save
->rip
= 0x0000fff0;
1572 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1575 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1576 * It also updates the guest-visible cr0 value.
1578 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1579 kvm_mmu_reset_context(&svm
->vcpu
);
1581 save
->cr4
= X86_CR4_PAE
;
1585 /* Setup VMCB for Nested Paging */
1586 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1587 clr_intercept(svm
, INTERCEPT_INVLPG
);
1588 clr_exception_intercept(svm
, PF_VECTOR
);
1589 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1590 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1591 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1595 svm
->asid_generation
= 0;
1597 svm
->nested
.vmcb
= 0;
1598 svm
->vcpu
.arch
.hflags
= 0;
1600 if (pause_filter_count
) {
1601 control
->pause_filter_count
= pause_filter_count
;
1602 if (pause_filter_thresh
)
1603 control
->pause_filter_thresh
= pause_filter_thresh
;
1604 set_intercept(svm
, INTERCEPT_PAUSE
);
1606 clr_intercept(svm
, INTERCEPT_PAUSE
);
1609 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1610 avic_init_vmcb(svm
);
1613 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1614 * in VMCB and clear intercepts to avoid #VMEXIT.
1617 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1618 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1619 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1623 clr_intercept(svm
, INTERCEPT_STGI
);
1624 clr_intercept(svm
, INTERCEPT_CLGI
);
1625 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1628 if (sev_guest(svm
->vcpu
.kvm
)) {
1629 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1630 clr_exception_intercept(svm
, UD_VECTOR
);
1633 mark_all_dirty(svm
->vmcb
);
1639 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1642 u64
*avic_physical_id_table
;
1643 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
1645 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1648 avic_physical_id_table
= page_address(kvm_svm
->avic_physical_id_table_page
);
1650 return &avic_physical_id_table
[index
];
1655 * AVIC hardware walks the nested page table to check permissions,
1656 * but does not use the SPA address specified in the leaf page
1657 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1658 * field of the VMCB. Therefore, we set up the
1659 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1661 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1663 struct kvm
*kvm
= vcpu
->kvm
;
1666 mutex_lock(&kvm
->slots_lock
);
1667 if (kvm
->arch
.apic_access_page_done
)
1670 ret
= __x86_set_memory_region(kvm
,
1671 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1672 APIC_DEFAULT_PHYS_BASE
,
1677 kvm
->arch
.apic_access_page_done
= true;
1679 mutex_unlock(&kvm
->slots_lock
);
1683 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1686 u64
*entry
, new_entry
;
1687 int id
= vcpu
->vcpu_id
;
1688 struct vcpu_svm
*svm
= to_svm(vcpu
);
1690 ret
= avic_init_access_page(vcpu
);
1694 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1697 if (!svm
->vcpu
.arch
.apic
->regs
)
1700 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1702 /* Setting AVIC backing page address in the phy APIC ID table */
1703 entry
= avic_get_physical_id_entry(vcpu
, id
);
1707 new_entry
= READ_ONCE(*entry
);
1708 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1709 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1710 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1711 WRITE_ONCE(*entry
, new_entry
);
1713 svm
->avic_physical_id_cache
= entry
;
1718 static void __sev_asid_free(int asid
)
1720 struct svm_cpu_data
*sd
;
1724 clear_bit(pos
, sev_asid_bitmap
);
1726 for_each_possible_cpu(cpu
) {
1727 sd
= per_cpu(svm_data
, cpu
);
1728 sd
->sev_vmcbs
[pos
] = NULL
;
1732 static void sev_asid_free(struct kvm
*kvm
)
1734 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1736 __sev_asid_free(sev
->asid
);
1739 static void sev_unbind_asid(struct kvm
*kvm
, unsigned int handle
)
1741 struct sev_data_decommission
*decommission
;
1742 struct sev_data_deactivate
*data
;
1747 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1751 /* deactivate handle */
1752 data
->handle
= handle
;
1753 sev_guest_deactivate(data
, NULL
);
1755 wbinvd_on_all_cpus();
1756 sev_guest_df_flush(NULL
);
1759 decommission
= kzalloc(sizeof(*decommission
), GFP_KERNEL
);
1763 /* decommission handle */
1764 decommission
->handle
= handle
;
1765 sev_guest_decommission(decommission
, NULL
);
1767 kfree(decommission
);
1770 static struct page
**sev_pin_memory(struct kvm
*kvm
, unsigned long uaddr
,
1771 unsigned long ulen
, unsigned long *n
,
1774 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1775 unsigned long npages
, npinned
, size
;
1776 unsigned long locked
, lock_limit
;
1777 struct page
**pages
;
1778 unsigned long first
, last
;
1780 if (ulen
== 0 || uaddr
+ ulen
< uaddr
)
1783 /* Calculate number of pages. */
1784 first
= (uaddr
& PAGE_MASK
) >> PAGE_SHIFT
;
1785 last
= ((uaddr
+ ulen
- 1) & PAGE_MASK
) >> PAGE_SHIFT
;
1786 npages
= (last
- first
+ 1);
1788 locked
= sev
->pages_locked
+ npages
;
1789 lock_limit
= rlimit(RLIMIT_MEMLOCK
) >> PAGE_SHIFT
;
1790 if (locked
> lock_limit
&& !capable(CAP_IPC_LOCK
)) {
1791 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked
, lock_limit
);
1795 /* Avoid using vmalloc for smaller buffers. */
1796 size
= npages
* sizeof(struct page
*);
1797 if (size
> PAGE_SIZE
)
1798 pages
= vmalloc(size
);
1800 pages
= kmalloc(size
, GFP_KERNEL
);
1805 /* Pin the user virtual address. */
1806 npinned
= get_user_pages_fast(uaddr
, npages
, write
? FOLL_WRITE
: 0, pages
);
1807 if (npinned
!= npages
) {
1808 pr_err("SEV: Failure locking %lu pages.\n", npages
);
1813 sev
->pages_locked
= locked
;
1819 release_pages(pages
, npinned
);
1825 static void sev_unpin_memory(struct kvm
*kvm
, struct page
**pages
,
1826 unsigned long npages
)
1828 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1830 release_pages(pages
, npages
);
1832 sev
->pages_locked
-= npages
;
1835 static void sev_clflush_pages(struct page
*pages
[], unsigned long npages
)
1837 uint8_t *page_virtual
;
1840 if (npages
== 0 || pages
== NULL
)
1843 for (i
= 0; i
< npages
; i
++) {
1844 page_virtual
= kmap_atomic(pages
[i
]);
1845 clflush_cache_range(page_virtual
, PAGE_SIZE
);
1846 kunmap_atomic(page_virtual
);
1850 static void __unregister_enc_region_locked(struct kvm
*kvm
,
1851 struct enc_region
*region
)
1854 * The guest may change the memory encryption attribute from C=0 -> C=1
1855 * or vice versa for this memory range. Lets make sure caches are
1856 * flushed to ensure that guest data gets written into memory with
1859 sev_clflush_pages(region
->pages
, region
->npages
);
1861 sev_unpin_memory(kvm
, region
->pages
, region
->npages
);
1862 list_del(®ion
->list
);
1866 static struct kvm
*svm_vm_alloc(void)
1868 struct kvm_svm
*kvm_svm
= vzalloc(sizeof(struct kvm_svm
));
1869 return &kvm_svm
->kvm
;
1872 static void svm_vm_free(struct kvm
*kvm
)
1874 vfree(to_kvm_svm(kvm
));
1877 static void sev_vm_destroy(struct kvm
*kvm
)
1879 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1880 struct list_head
*head
= &sev
->regions_list
;
1881 struct list_head
*pos
, *q
;
1883 if (!sev_guest(kvm
))
1886 mutex_lock(&kvm
->lock
);
1889 * if userspace was terminated before unregistering the memory regions
1890 * then lets unpin all the registered memory.
1892 if (!list_empty(head
)) {
1893 list_for_each_safe(pos
, q
, head
) {
1894 __unregister_enc_region_locked(kvm
,
1895 list_entry(pos
, struct enc_region
, list
));
1899 mutex_unlock(&kvm
->lock
);
1901 sev_unbind_asid(kvm
, sev
->handle
);
1905 static void avic_vm_destroy(struct kvm
*kvm
)
1907 unsigned long flags
;
1908 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1913 if (kvm_svm
->avic_logical_id_table_page
)
1914 __free_page(kvm_svm
->avic_logical_id_table_page
);
1915 if (kvm_svm
->avic_physical_id_table_page
)
1916 __free_page(kvm_svm
->avic_physical_id_table_page
);
1918 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1919 hash_del(&kvm_svm
->hnode
);
1920 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1923 static void svm_vm_destroy(struct kvm
*kvm
)
1925 avic_vm_destroy(kvm
);
1926 sev_vm_destroy(kvm
);
1929 static int avic_vm_init(struct kvm
*kvm
)
1931 unsigned long flags
;
1933 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1935 struct page
*p_page
;
1936 struct page
*l_page
;
1942 /* Allocating physical APIC ID table (4KB) */
1943 p_page
= alloc_page(GFP_KERNEL
);
1947 kvm_svm
->avic_physical_id_table_page
= p_page
;
1948 clear_page(page_address(p_page
));
1950 /* Allocating logical APIC ID table (4KB) */
1951 l_page
= alloc_page(GFP_KERNEL
);
1955 kvm_svm
->avic_logical_id_table_page
= l_page
;
1956 clear_page(page_address(l_page
));
1958 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1960 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1961 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1962 next_vm_id_wrapped
= 1;
1965 /* Is it still in use? Only possible if wrapped at least once */
1966 if (next_vm_id_wrapped
) {
1967 hash_for_each_possible(svm_vm_data_hash
, k2
, hnode
, vm_id
) {
1968 if (k2
->avic_vm_id
== vm_id
)
1972 kvm_svm
->avic_vm_id
= vm_id
;
1973 hash_add(svm_vm_data_hash
, &kvm_svm
->hnode
, kvm_svm
->avic_vm_id
);
1974 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1979 avic_vm_destroy(kvm
);
1984 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1987 unsigned long flags
;
1988 struct amd_svm_iommu_ir
*ir
;
1989 struct vcpu_svm
*svm
= to_svm(vcpu
);
1991 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1995 * Here, we go through the per-vcpu ir_list to update all existing
1996 * interrupt remapping table entry targeting this vcpu.
1998 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
2000 if (list_empty(&svm
->ir_list
))
2003 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
2004 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
2009 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
2013 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2016 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2017 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
2018 struct vcpu_svm
*svm
= to_svm(vcpu
);
2020 if (!kvm_vcpu_apicv_active(vcpu
))
2023 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
2026 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2027 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
2029 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
2030 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
2032 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2033 if (svm
->avic_is_running
)
2034 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2036 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2037 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
2038 svm
->avic_is_running
);
2041 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
2044 struct vcpu_svm
*svm
= to_svm(vcpu
);
2046 if (!kvm_vcpu_apicv_active(vcpu
))
2049 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2050 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
2051 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
2053 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2054 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2058 * This function is called during VCPU halt/unhalt.
2060 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
2062 struct vcpu_svm
*svm
= to_svm(vcpu
);
2064 svm
->avic_is_running
= is_run
;
2066 avic_vcpu_load(vcpu
, vcpu
->cpu
);
2068 avic_vcpu_put(vcpu
);
2071 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
2073 struct vcpu_svm
*svm
= to_svm(vcpu
);
2077 vcpu
->arch
.microcode_version
= 0x01000065;
2079 svm
->virt_spec_ctrl
= 0;
2082 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
2083 MSR_IA32_APICBASE_ENABLE
;
2084 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
2085 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
2089 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
2090 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
2092 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
2093 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
2096 static int avic_init_vcpu(struct vcpu_svm
*svm
)
2100 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
2103 ret
= avic_init_backing_page(&svm
->vcpu
);
2107 INIT_LIST_HEAD(&svm
->ir_list
);
2108 spin_lock_init(&svm
->ir_list_lock
);
2113 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2115 struct vcpu_svm
*svm
;
2117 struct page
*msrpm_pages
;
2118 struct page
*hsave_page
;
2119 struct page
*nested_msrpm_pages
;
2122 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2128 svm
->vcpu
.arch
.guest_fpu
= kmem_cache_zalloc(x86_fpu_cache
, GFP_KERNEL
);
2129 if (!svm
->vcpu
.arch
.guest_fpu
) {
2130 printk(KERN_ERR
"kvm: failed to allocate vcpu's fpu\n");
2132 goto free_partial_svm
;
2135 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
2140 page
= alloc_page(GFP_KERNEL
);
2144 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2148 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2149 if (!nested_msrpm_pages
)
2152 hsave_page
= alloc_page(GFP_KERNEL
);
2156 err
= avic_init_vcpu(svm
);
2160 /* We initialize this flag to true to make sure that the is_running
2161 * bit would be set the first time the vcpu is loaded.
2163 svm
->avic_is_running
= true;
2165 svm
->nested
.hsave
= page_address(hsave_page
);
2167 svm
->msrpm
= page_address(msrpm_pages
);
2168 svm_vcpu_init_msrpm(svm
->msrpm
);
2170 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
2171 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
2173 svm
->vmcb
= page_address(page
);
2174 clear_page(svm
->vmcb
);
2175 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
2176 svm
->asid_generation
= 0;
2179 svm_init_osvw(&svm
->vcpu
);
2184 __free_page(hsave_page
);
2186 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
2188 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
2192 kvm_vcpu_uninit(&svm
->vcpu
);
2194 kmem_cache_free(x86_fpu_cache
, svm
->vcpu
.arch
.guest_fpu
);
2196 kmem_cache_free(kvm_vcpu_cache
, svm
);
2198 return ERR_PTR(err
);
2201 static void svm_clear_current_vmcb(struct vmcb
*vmcb
)
2205 for_each_online_cpu(i
)
2206 cmpxchg(&per_cpu(svm_data
, i
)->current_vmcb
, vmcb
, NULL
);
2209 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
2211 struct vcpu_svm
*svm
= to_svm(vcpu
);
2214 * The vmcb page can be recycled, causing a false negative in
2215 * svm_vcpu_load(). So, ensure that no logical CPU has this
2216 * vmcb page recorded as its current vmcb.
2218 svm_clear_current_vmcb(svm
->vmcb
);
2220 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
2221 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
2222 __free_page(virt_to_page(svm
->nested
.hsave
));
2223 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
2224 kvm_vcpu_uninit(vcpu
);
2225 kmem_cache_free(x86_fpu_cache
, svm
->vcpu
.arch
.guest_fpu
);
2226 kmem_cache_free(kvm_vcpu_cache
, svm
);
2229 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2231 struct vcpu_svm
*svm
= to_svm(vcpu
);
2232 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2235 if (unlikely(cpu
!= vcpu
->cpu
)) {
2236 svm
->asid_generation
= 0;
2237 mark_all_dirty(svm
->vmcb
);
2240 #ifdef CONFIG_X86_64
2241 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
2243 savesegment(fs
, svm
->host
.fs
);
2244 savesegment(gs
, svm
->host
.gs
);
2245 svm
->host
.ldt
= kvm_read_ldt();
2247 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2248 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2250 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
2251 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2252 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
2253 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
2254 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
2257 /* This assumes that the kernel never uses MSR_TSC_AUX */
2258 if (static_cpu_has(X86_FEATURE_RDTSCP
))
2259 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
2261 if (sd
->current_vmcb
!= svm
->vmcb
) {
2262 sd
->current_vmcb
= svm
->vmcb
;
2263 indirect_branch_prediction_barrier();
2265 avic_vcpu_load(vcpu
, cpu
);
2268 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
2270 struct vcpu_svm
*svm
= to_svm(vcpu
);
2273 avic_vcpu_put(vcpu
);
2275 ++vcpu
->stat
.host_state_reload
;
2276 kvm_load_ldt(svm
->host
.ldt
);
2277 #ifdef CONFIG_X86_64
2278 loadsegment(fs
, svm
->host
.fs
);
2279 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
2280 load_gs_index(svm
->host
.gs
);
2282 #ifdef CONFIG_X86_32_LAZY_GS
2283 loadsegment(gs
, svm
->host
.gs
);
2286 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2287 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2290 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
2292 avic_set_running(vcpu
, false);
2295 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
2297 avic_set_running(vcpu
, true);
2300 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
2302 struct vcpu_svm
*svm
= to_svm(vcpu
);
2303 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
2305 if (svm
->nmi_singlestep
) {
2306 /* Hide our flags if they were not set by the guest */
2307 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
2308 rflags
&= ~X86_EFLAGS_TF
;
2309 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
2310 rflags
&= ~X86_EFLAGS_RF
;
2315 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2317 if (to_svm(vcpu
)->nmi_singlestep
)
2318 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2321 * Any change of EFLAGS.VM is accompanied by a reload of SS
2322 * (caused by either a task switch or an inter-privilege IRET),
2323 * so we do not need to update the CPL here.
2325 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
2328 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2331 case VCPU_EXREG_PDPTR
:
2332 BUG_ON(!npt_enabled
);
2333 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
2340 static void svm_set_vintr(struct vcpu_svm
*svm
)
2342 set_intercept(svm
, INTERCEPT_VINTR
);
2345 static void svm_clear_vintr(struct vcpu_svm
*svm
)
2347 clr_intercept(svm
, INTERCEPT_VINTR
);
2350 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
2352 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2355 case VCPU_SREG_CS
: return &save
->cs
;
2356 case VCPU_SREG_DS
: return &save
->ds
;
2357 case VCPU_SREG_ES
: return &save
->es
;
2358 case VCPU_SREG_FS
: return &save
->fs
;
2359 case VCPU_SREG_GS
: return &save
->gs
;
2360 case VCPU_SREG_SS
: return &save
->ss
;
2361 case VCPU_SREG_TR
: return &save
->tr
;
2362 case VCPU_SREG_LDTR
: return &save
->ldtr
;
2368 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2370 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2375 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
2376 struct kvm_segment
*var
, int seg
)
2378 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2380 var
->base
= s
->base
;
2381 var
->limit
= s
->limit
;
2382 var
->selector
= s
->selector
;
2383 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
2384 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
2385 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
2386 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
2387 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
2388 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
2389 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
2392 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2393 * However, the SVM spec states that the G bit is not observed by the
2394 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2395 * So let's synthesize a legal G bit for all segments, this helps
2396 * running KVM nested. It also helps cross-vendor migration, because
2397 * Intel's vmentry has a check on the 'G' bit.
2399 var
->g
= s
->limit
> 0xfffff;
2402 * AMD's VMCB does not have an explicit unusable field, so emulate it
2403 * for cross vendor migration purposes by "not present"
2405 var
->unusable
= !var
->present
;
2410 * Work around a bug where the busy flag in the tr selector
2420 * The accessed bit must always be set in the segment
2421 * descriptor cache, although it can be cleared in the
2422 * descriptor, the cached bit always remains at 1. Since
2423 * Intel has a check on this, set it here to support
2424 * cross-vendor migration.
2431 * On AMD CPUs sometimes the DB bit in the segment
2432 * descriptor is left as 1, although the whole segment has
2433 * been made unusable. Clear it here to pass an Intel VMX
2434 * entry check when cross vendor migrating.
2438 /* This is symmetric with svm_set_segment() */
2439 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
2444 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
2446 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2451 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2453 struct vcpu_svm
*svm
= to_svm(vcpu
);
2455 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
2456 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
2459 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2461 struct vcpu_svm
*svm
= to_svm(vcpu
);
2463 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
2464 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
2465 mark_dirty(svm
->vmcb
, VMCB_DT
);
2468 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2470 struct vcpu_svm
*svm
= to_svm(vcpu
);
2472 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
2473 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
2476 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2478 struct vcpu_svm
*svm
= to_svm(vcpu
);
2480 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
2481 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
2482 mark_dirty(svm
->vmcb
, VMCB_DT
);
2485 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2489 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
2493 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2497 static void update_cr0_intercept(struct vcpu_svm
*svm
)
2499 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
2500 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
2502 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
2503 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
2505 mark_dirty(svm
->vmcb
, VMCB_CR
);
2507 if (gcr0
== *hcr0
) {
2508 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2509 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2511 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2512 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2516 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2518 struct vcpu_svm
*svm
= to_svm(vcpu
);
2520 #ifdef CONFIG_X86_64
2521 if (vcpu
->arch
.efer
& EFER_LME
) {
2522 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
2523 vcpu
->arch
.efer
|= EFER_LMA
;
2524 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2527 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2528 vcpu
->arch
.efer
&= ~EFER_LMA
;
2529 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2533 vcpu
->arch
.cr0
= cr0
;
2536 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2539 * re-enable caching here because the QEMU bios
2540 * does not do it - this results in some delay at
2543 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2544 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2545 svm
->vmcb
->save
.cr0
= cr0
;
2546 mark_dirty(svm
->vmcb
, VMCB_CR
);
2547 update_cr0_intercept(svm
);
2550 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2552 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2553 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2555 if (cr4
& X86_CR4_VMXE
)
2558 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2559 svm_flush_tlb(vcpu
, true);
2561 vcpu
->arch
.cr4
= cr4
;
2564 cr4
|= host_cr4_mce
;
2565 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2566 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2570 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2571 struct kvm_segment
*var
, int seg
)
2573 struct vcpu_svm
*svm
= to_svm(vcpu
);
2574 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2576 s
->base
= var
->base
;
2577 s
->limit
= var
->limit
;
2578 s
->selector
= var
->selector
;
2579 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2580 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2581 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2582 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2583 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2584 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2585 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2586 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2589 * This is always accurate, except if SYSRET returned to a segment
2590 * with SS.DPL != 3. Intel does not have this quirk, and always
2591 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2592 * would entail passing the CPL to userspace and back.
2594 if (seg
== VCPU_SREG_SS
)
2595 /* This is symmetric with svm_get_segment() */
2596 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2598 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2601 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2603 struct vcpu_svm
*svm
= to_svm(vcpu
);
2605 clr_exception_intercept(svm
, BP_VECTOR
);
2607 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2608 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2609 set_exception_intercept(svm
, BP_VECTOR
);
2611 vcpu
->guest_debug
= 0;
2614 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2616 if (sd
->next_asid
> sd
->max_asid
) {
2617 ++sd
->asid_generation
;
2618 sd
->next_asid
= sd
->min_asid
;
2619 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2622 svm
->asid_generation
= sd
->asid_generation
;
2623 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2625 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2628 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2630 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2633 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2635 struct vcpu_svm
*svm
= to_svm(vcpu
);
2637 svm
->vmcb
->save
.dr6
= value
;
2638 mark_dirty(svm
->vmcb
, VMCB_DR
);
2641 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2643 struct vcpu_svm
*svm
= to_svm(vcpu
);
2645 get_debugreg(vcpu
->arch
.db
[0], 0);
2646 get_debugreg(vcpu
->arch
.db
[1], 1);
2647 get_debugreg(vcpu
->arch
.db
[2], 2);
2648 get_debugreg(vcpu
->arch
.db
[3], 3);
2649 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2650 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2652 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2653 set_dr_intercepts(svm
);
2656 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2658 struct vcpu_svm
*svm
= to_svm(vcpu
);
2660 svm
->vmcb
->save
.dr7
= value
;
2661 mark_dirty(svm
->vmcb
, VMCB_DR
);
2664 static int pf_interception(struct vcpu_svm
*svm
)
2666 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2667 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2669 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2670 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2671 svm
->vmcb
->control
.insn_bytes
: NULL
,
2672 svm
->vmcb
->control
.insn_len
);
2675 static int npf_interception(struct vcpu_svm
*svm
)
2677 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2678 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2680 trace_kvm_page_fault(fault_address
, error_code
);
2681 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2682 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2683 svm
->vmcb
->control
.insn_bytes
: NULL
,
2684 svm
->vmcb
->control
.insn_len
);
2687 static int db_interception(struct vcpu_svm
*svm
)
2689 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2691 if (!(svm
->vcpu
.guest_debug
&
2692 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2693 !svm
->nmi_singlestep
) {
2694 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2698 if (svm
->nmi_singlestep
) {
2699 disable_nmi_singlestep(svm
);
2702 if (svm
->vcpu
.guest_debug
&
2703 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2704 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2705 kvm_run
->debug
.arch
.pc
=
2706 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2707 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2714 static int bp_interception(struct vcpu_svm
*svm
)
2716 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2718 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2719 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2720 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2724 static int ud_interception(struct vcpu_svm
*svm
)
2726 return handle_ud(&svm
->vcpu
);
2729 static int ac_interception(struct vcpu_svm
*svm
)
2731 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2735 static int gp_interception(struct vcpu_svm
*svm
)
2737 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2738 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
2741 WARN_ON_ONCE(!enable_vmware_backdoor
);
2743 er
= kvm_emulate_instruction(vcpu
,
2744 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
2745 if (er
== EMULATE_USER_EXIT
)
2747 else if (er
!= EMULATE_DONE
)
2748 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
2752 static bool is_erratum_383(void)
2757 if (!erratum_383_found
)
2760 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2764 /* Bit 62 may or may not be set for this mce */
2765 value
&= ~(1ULL << 62);
2767 if (value
!= 0xb600000000010015ULL
)
2770 /* Clear MCi_STATUS registers */
2771 for (i
= 0; i
< 6; ++i
)
2772 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2774 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2778 value
&= ~(1ULL << 2);
2779 low
= lower_32_bits(value
);
2780 high
= upper_32_bits(value
);
2782 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2785 /* Flush tlb to evict multi-match entries */
2791 static void svm_handle_mce(struct vcpu_svm
*svm
)
2793 if (is_erratum_383()) {
2795 * Erratum 383 triggered. Guest state is corrupt so kill the
2798 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2800 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2806 * On an #MC intercept the MCE handler is not called automatically in
2807 * the host. So do it by hand here.
2811 /* not sure if we ever come back to this point */
2816 static int mc_interception(struct vcpu_svm
*svm
)
2821 static int shutdown_interception(struct vcpu_svm
*svm
)
2823 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2826 * VMCB is undefined after a SHUTDOWN intercept
2827 * so reinitialize it.
2829 clear_page(svm
->vmcb
);
2832 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2836 static int io_interception(struct vcpu_svm
*svm
)
2838 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2839 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2840 int size
, in
, string
;
2843 ++svm
->vcpu
.stat
.io_exits
;
2844 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2845 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2847 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2849 port
= io_info
>> 16;
2850 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2851 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2853 return kvm_fast_pio(&svm
->vcpu
, size
, port
, in
);
2856 static int nmi_interception(struct vcpu_svm
*svm
)
2861 static int intr_interception(struct vcpu_svm
*svm
)
2863 ++svm
->vcpu
.stat
.irq_exits
;
2867 static int nop_on_interception(struct vcpu_svm
*svm
)
2872 static int halt_interception(struct vcpu_svm
*svm
)
2874 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2875 return kvm_emulate_halt(&svm
->vcpu
);
2878 static int vmmcall_interception(struct vcpu_svm
*svm
)
2880 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2881 return kvm_emulate_hypercall(&svm
->vcpu
);
2884 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2886 struct vcpu_svm
*svm
= to_svm(vcpu
);
2888 return svm
->nested
.nested_cr3
;
2891 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2893 struct vcpu_svm
*svm
= to_svm(vcpu
);
2894 u64 cr3
= svm
->nested
.nested_cr3
;
2898 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2899 offset_in_page(cr3
) + index
* 8, 8);
2905 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2908 struct vcpu_svm
*svm
= to_svm(vcpu
);
2910 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2911 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2914 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2915 struct x86_exception
*fault
)
2917 struct vcpu_svm
*svm
= to_svm(vcpu
);
2919 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2921 * TODO: track the cause of the nested page fault, and
2922 * correctly fill in the high bits of exit_info_1.
2924 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2925 svm
->vmcb
->control
.exit_code_hi
= 0;
2926 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2927 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2930 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2931 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2934 * The present bit is always zero for page structure faults on real
2937 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2938 svm
->vmcb
->control
.exit_info_1
&= ~1;
2940 nested_svm_vmexit(svm
);
2943 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2945 WARN_ON(mmu_is_nested(vcpu
));
2947 vcpu
->arch
.mmu
= &vcpu
->arch
.guest_mmu
;
2948 kvm_init_shadow_mmu(vcpu
);
2949 vcpu
->arch
.mmu
->set_cr3
= nested_svm_set_tdp_cr3
;
2950 vcpu
->arch
.mmu
->get_cr3
= nested_svm_get_tdp_cr3
;
2951 vcpu
->arch
.mmu
->get_pdptr
= nested_svm_get_tdp_pdptr
;
2952 vcpu
->arch
.mmu
->inject_page_fault
= nested_svm_inject_npf_exit
;
2953 vcpu
->arch
.mmu
->shadow_root_level
= get_npt_level(vcpu
);
2954 reset_shadow_zero_bits_mask(vcpu
, vcpu
->arch
.mmu
);
2955 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2958 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2960 vcpu
->arch
.mmu
= &vcpu
->arch
.root_mmu
;
2961 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.root_mmu
;
2964 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2966 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2967 !is_paging(&svm
->vcpu
)) {
2968 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2972 if (svm
->vmcb
->save
.cpl
) {
2973 kvm_inject_gp(&svm
->vcpu
, 0);
2980 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2981 bool has_error_code
, u32 error_code
)
2985 if (!is_guest_mode(&svm
->vcpu
))
2988 vmexit
= nested_svm_intercept(svm
);
2989 if (vmexit
!= NESTED_EXIT_DONE
)
2992 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2993 svm
->vmcb
->control
.exit_code_hi
= 0;
2994 svm
->vmcb
->control
.exit_info_1
= error_code
;
2997 * EXITINFO2 is undefined for all exception intercepts other
3000 if (svm
->vcpu
.arch
.exception
.nested_apf
)
3001 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
3002 else if (svm
->vcpu
.arch
.exception
.has_payload
)
3003 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.exception
.payload
;
3005 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
3007 svm
->nested
.exit_required
= true;
3011 /* This function returns true if it is save to enable the irq window */
3012 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
3014 if (!is_guest_mode(&svm
->vcpu
))
3017 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3020 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
3024 * if vmexit was already requested (by intercepted exception
3025 * for instance) do not overwrite it with "external interrupt"
3028 if (svm
->nested
.exit_required
)
3031 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
3032 svm
->vmcb
->control
.exit_info_1
= 0;
3033 svm
->vmcb
->control
.exit_info_2
= 0;
3035 if (svm
->nested
.intercept
& 1ULL) {
3037 * The #vmexit can't be emulated here directly because this
3038 * code path runs with irqs and preemption disabled. A
3039 * #vmexit emulation might sleep. Only signal request for
3042 svm
->nested
.exit_required
= true;
3043 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
3050 /* This function returns true if it is save to enable the nmi window */
3051 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
3053 if (!is_guest_mode(&svm
->vcpu
))
3056 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
3059 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
3060 svm
->nested
.exit_required
= true;
3065 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
3071 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
3072 if (is_error_page(page
))
3080 kvm_inject_gp(&svm
->vcpu
, 0);
3085 static void nested_svm_unmap(struct page
*page
)
3088 kvm_release_page_dirty(page
);
3091 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
3093 unsigned port
, size
, iopm_len
;
3098 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
3099 return NESTED_EXIT_HOST
;
3101 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
3102 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
3103 SVM_IOIO_SIZE_SHIFT
;
3104 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
3105 start_bit
= port
% 8;
3106 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
3107 mask
= (0xf >> (4 - size
)) << start_bit
;
3110 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
3111 return NESTED_EXIT_DONE
;
3113 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3116 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
3118 u32 offset
, msr
, value
;
3121 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3122 return NESTED_EXIT_HOST
;
3124 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3125 offset
= svm_msrpm_offset(msr
);
3126 write
= svm
->vmcb
->control
.exit_info_1
& 1;
3127 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
3129 if (offset
== MSR_INVALID
)
3130 return NESTED_EXIT_DONE
;
3132 /* Offset is in 32 bit units but need in 8 bit units */
3135 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
3136 return NESTED_EXIT_DONE
;
3138 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3141 /* DB exceptions for our internal use must not cause vmexit */
3142 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
3146 /* if we're not singlestepping, it's not ours */
3147 if (!svm
->nmi_singlestep
)
3148 return NESTED_EXIT_DONE
;
3150 /* if it's not a singlestep exception, it's not ours */
3151 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
3152 return NESTED_EXIT_DONE
;
3153 if (!(dr6
& DR6_BS
))
3154 return NESTED_EXIT_DONE
;
3156 /* if the guest is singlestepping, it should get the vmexit */
3157 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
3158 disable_nmi_singlestep(svm
);
3159 return NESTED_EXIT_DONE
;
3162 /* it's ours, the nested hypervisor must not see this one */
3163 return NESTED_EXIT_HOST
;
3166 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
3168 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3170 switch (exit_code
) {
3173 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
3174 return NESTED_EXIT_HOST
;
3176 /* For now we are always handling NPFs when using them */
3178 return NESTED_EXIT_HOST
;
3180 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
3181 /* When we're shadowing, trap PFs, but not async PF */
3182 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
3183 return NESTED_EXIT_HOST
;
3189 return NESTED_EXIT_CONTINUE
;
3193 * If this function returns true, this #vmexit was already handled
3195 static int nested_svm_intercept(struct vcpu_svm
*svm
)
3197 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3198 int vmexit
= NESTED_EXIT_HOST
;
3200 switch (exit_code
) {
3202 vmexit
= nested_svm_exit_handled_msr(svm
);
3205 vmexit
= nested_svm_intercept_ioio(svm
);
3207 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
3208 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
3209 if (svm
->nested
.intercept_cr
& bit
)
3210 vmexit
= NESTED_EXIT_DONE
;
3213 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
3214 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
3215 if (svm
->nested
.intercept_dr
& bit
)
3216 vmexit
= NESTED_EXIT_DONE
;
3219 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
3220 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
3221 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
3222 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
3223 vmexit
= nested_svm_intercept_db(svm
);
3225 vmexit
= NESTED_EXIT_DONE
;
3227 /* async page fault always cause vmexit */
3228 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
3229 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
3230 vmexit
= NESTED_EXIT_DONE
;
3233 case SVM_EXIT_ERR
: {
3234 vmexit
= NESTED_EXIT_DONE
;
3238 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
3239 if (svm
->nested
.intercept
& exit_bits
)
3240 vmexit
= NESTED_EXIT_DONE
;
3247 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
3251 vmexit
= nested_svm_intercept(svm
);
3253 if (vmexit
== NESTED_EXIT_DONE
)
3254 nested_svm_vmexit(svm
);
3259 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
3261 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
3262 struct vmcb_control_area
*from
= &from_vmcb
->control
;
3264 dst
->intercept_cr
= from
->intercept_cr
;
3265 dst
->intercept_dr
= from
->intercept_dr
;
3266 dst
->intercept_exceptions
= from
->intercept_exceptions
;
3267 dst
->intercept
= from
->intercept
;
3268 dst
->iopm_base_pa
= from
->iopm_base_pa
;
3269 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
3270 dst
->tsc_offset
= from
->tsc_offset
;
3271 dst
->asid
= from
->asid
;
3272 dst
->tlb_ctl
= from
->tlb_ctl
;
3273 dst
->int_ctl
= from
->int_ctl
;
3274 dst
->int_vector
= from
->int_vector
;
3275 dst
->int_state
= from
->int_state
;
3276 dst
->exit_code
= from
->exit_code
;
3277 dst
->exit_code_hi
= from
->exit_code_hi
;
3278 dst
->exit_info_1
= from
->exit_info_1
;
3279 dst
->exit_info_2
= from
->exit_info_2
;
3280 dst
->exit_int_info
= from
->exit_int_info
;
3281 dst
->exit_int_info_err
= from
->exit_int_info_err
;
3282 dst
->nested_ctl
= from
->nested_ctl
;
3283 dst
->event_inj
= from
->event_inj
;
3284 dst
->event_inj_err
= from
->event_inj_err
;
3285 dst
->nested_cr3
= from
->nested_cr3
;
3286 dst
->virt_ext
= from
->virt_ext
;
3287 dst
->pause_filter_count
= from
->pause_filter_count
;
3288 dst
->pause_filter_thresh
= from
->pause_filter_thresh
;
3291 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
3293 struct vmcb
*nested_vmcb
;
3294 struct vmcb
*hsave
= svm
->nested
.hsave
;
3295 struct vmcb
*vmcb
= svm
->vmcb
;
3298 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
3299 vmcb
->control
.exit_info_1
,
3300 vmcb
->control
.exit_info_2
,
3301 vmcb
->control
.exit_int_info
,
3302 vmcb
->control
.exit_int_info_err
,
3305 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
3309 /* Exit Guest-Mode */
3310 leave_guest_mode(&svm
->vcpu
);
3311 svm
->nested
.vmcb
= 0;
3313 /* Give the current vmcb to the guest */
3316 nested_vmcb
->save
.es
= vmcb
->save
.es
;
3317 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
3318 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
3319 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
3320 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
3321 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
3322 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
3323 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3324 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3325 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
3326 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3327 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3328 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
3329 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
3330 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
3331 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
3332 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
3333 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
3335 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
3336 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
3337 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
3338 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
3339 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
3340 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
3341 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
3342 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
3343 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
3345 if (svm
->nrips_enabled
)
3346 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
3349 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3350 * to make sure that we do not lose injected events. So check event_inj
3351 * here and copy it to exit_int_info if it is valid.
3352 * Exit_int_info and event_inj can't be both valid because the case
3353 * below only happens on a VMRUN instruction intercept which has
3354 * no valid exit_int_info set.
3356 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
3357 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
3359 nc
->exit_int_info
= vmcb
->control
.event_inj
;
3360 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
3363 nested_vmcb
->control
.tlb_ctl
= 0;
3364 nested_vmcb
->control
.event_inj
= 0;
3365 nested_vmcb
->control
.event_inj_err
= 0;
3367 nested_vmcb
->control
.pause_filter_count
=
3368 svm
->vmcb
->control
.pause_filter_count
;
3369 nested_vmcb
->control
.pause_filter_thresh
=
3370 svm
->vmcb
->control
.pause_filter_thresh
;
3372 /* We always set V_INTR_MASKING and remember the old value in hflags */
3373 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3374 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
3376 /* Restore the original control entries */
3377 copy_vmcb_control_area(vmcb
, hsave
);
3379 svm
->vcpu
.arch
.tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
3380 kvm_clear_exception_queue(&svm
->vcpu
);
3381 kvm_clear_interrupt_queue(&svm
->vcpu
);
3383 svm
->nested
.nested_cr3
= 0;
3385 /* Restore selected save entries */
3386 svm
->vmcb
->save
.es
= hsave
->save
.es
;
3387 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
3388 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
3389 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
3390 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
3391 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
3392 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
3393 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
3394 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
3395 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
3397 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
3398 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
3400 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
3402 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
3403 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
3404 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
3405 svm
->vmcb
->save
.dr7
= 0;
3406 svm
->vmcb
->save
.cpl
= 0;
3407 svm
->vmcb
->control
.exit_int_info
= 0;
3409 mark_all_dirty(svm
->vmcb
);
3411 nested_svm_unmap(page
);
3413 nested_svm_uninit_mmu_context(&svm
->vcpu
);
3414 kvm_mmu_reset_context(&svm
->vcpu
);
3415 kvm_mmu_load(&svm
->vcpu
);
3418 * Drop what we picked up for L2 via svm_complete_interrupts() so it
3419 * doesn't end up in L1.
3421 svm
->vcpu
.arch
.nmi_injected
= false;
3422 kvm_clear_exception_queue(&svm
->vcpu
);
3423 kvm_clear_interrupt_queue(&svm
->vcpu
);
3428 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
3431 * This function merges the msr permission bitmaps of kvm and the
3432 * nested vmcb. It is optimized in that it only merges the parts where
3433 * the kvm msr permission bitmap may contain zero bits
3437 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3440 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
3444 if (msrpm_offsets
[i
] == 0xffffffff)
3447 p
= msrpm_offsets
[i
];
3448 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
3450 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
3453 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
3456 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
3461 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
3463 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
3466 if (vmcb
->control
.asid
== 0)
3469 if ((vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) &&
3476 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
3477 struct vmcb
*nested_vmcb
, struct page
*page
)
3479 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
3480 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
3482 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
3484 if (nested_vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) {
3485 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
3486 nested_svm_init_mmu_context(&svm
->vcpu
);
3489 /* Load the nested guest state */
3490 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
3491 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
3492 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
3493 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
3494 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
3495 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
3496 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
3497 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3498 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3499 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3501 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3502 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3504 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3506 /* Guest paging mode is active - reset mmu */
3507 kvm_mmu_reset_context(&svm
->vcpu
);
3509 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3510 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
3511 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
3512 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
3514 /* In case we don't even reach vcpu_run, the fields are not updated */
3515 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3516 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3517 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3518 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3519 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3520 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3522 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3523 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3525 /* cache intercepts */
3526 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3527 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3528 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3529 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3531 svm_flush_tlb(&svm
->vcpu
, true);
3532 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3533 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3534 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3536 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3538 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3539 /* We only want the cr8 intercept bits of the guest */
3540 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3541 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3544 /* We don't want to see VMMCALLs from a nested guest */
3545 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3547 svm
->vcpu
.arch
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3548 svm
->vmcb
->control
.tsc_offset
= svm
->vcpu
.arch
.tsc_offset
;
3550 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3551 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3552 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3553 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3554 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3556 svm
->vmcb
->control
.pause_filter_count
=
3557 nested_vmcb
->control
.pause_filter_count
;
3558 svm
->vmcb
->control
.pause_filter_thresh
=
3559 nested_vmcb
->control
.pause_filter_thresh
;
3561 nested_svm_unmap(page
);
3563 /* Enter Guest-Mode */
3564 enter_guest_mode(&svm
->vcpu
);
3567 * Merge guest and host intercepts - must be called with vcpu in
3568 * guest-mode to take affect here
3570 recalc_intercepts(svm
);
3572 svm
->nested
.vmcb
= vmcb_gpa
;
3576 mark_all_dirty(svm
->vmcb
);
3579 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3581 struct vmcb
*nested_vmcb
;
3582 struct vmcb
*hsave
= svm
->nested
.hsave
;
3583 struct vmcb
*vmcb
= svm
->vmcb
;
3587 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3589 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3593 if (!nested_vmcb_checks(nested_vmcb
)) {
3594 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3595 nested_vmcb
->control
.exit_code_hi
= 0;
3596 nested_vmcb
->control
.exit_info_1
= 0;
3597 nested_vmcb
->control
.exit_info_2
= 0;
3599 nested_svm_unmap(page
);
3604 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3605 nested_vmcb
->save
.rip
,
3606 nested_vmcb
->control
.int_ctl
,
3607 nested_vmcb
->control
.event_inj
,
3608 nested_vmcb
->control
.nested_ctl
);
3610 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3611 nested_vmcb
->control
.intercept_cr
>> 16,
3612 nested_vmcb
->control
.intercept_exceptions
,
3613 nested_vmcb
->control
.intercept
);
3615 /* Clear internal status */
3616 kvm_clear_exception_queue(&svm
->vcpu
);
3617 kvm_clear_interrupt_queue(&svm
->vcpu
);
3620 * Save the old vmcb, so we don't need to pick what we save, but can
3621 * restore everything when a VMEXIT occurs
3623 hsave
->save
.es
= vmcb
->save
.es
;
3624 hsave
->save
.cs
= vmcb
->save
.cs
;
3625 hsave
->save
.ss
= vmcb
->save
.ss
;
3626 hsave
->save
.ds
= vmcb
->save
.ds
;
3627 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3628 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3629 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3630 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3631 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3632 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3633 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3634 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3635 hsave
->save
.rax
= vmcb
->save
.rax
;
3637 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3639 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3641 copy_vmcb_control_area(hsave
, vmcb
);
3643 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, page
);
3648 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3650 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3651 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3652 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3653 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3654 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3655 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3656 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3657 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3658 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3659 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3660 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3661 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3664 static int vmload_interception(struct vcpu_svm
*svm
)
3666 struct vmcb
*nested_vmcb
;
3670 if (nested_svm_check_permissions(svm
))
3673 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3677 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3678 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3680 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3681 nested_svm_unmap(page
);
3686 static int vmsave_interception(struct vcpu_svm
*svm
)
3688 struct vmcb
*nested_vmcb
;
3692 if (nested_svm_check_permissions(svm
))
3695 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3699 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3700 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3702 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3703 nested_svm_unmap(page
);
3708 static int vmrun_interception(struct vcpu_svm
*svm
)
3710 if (nested_svm_check_permissions(svm
))
3713 /* Save rip after vmrun instruction */
3714 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3716 if (!nested_svm_vmrun(svm
))
3719 if (!nested_svm_vmrun_msrpm(svm
))
3726 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3727 svm
->vmcb
->control
.exit_code_hi
= 0;
3728 svm
->vmcb
->control
.exit_info_1
= 0;
3729 svm
->vmcb
->control
.exit_info_2
= 0;
3731 nested_svm_vmexit(svm
);
3736 static int stgi_interception(struct vcpu_svm
*svm
)
3740 if (nested_svm_check_permissions(svm
))
3744 * If VGIF is enabled, the STGI intercept is only added to
3745 * detect the opening of the SMI/NMI window; remove it now.
3747 if (vgif_enabled(svm
))
3748 clr_intercept(svm
, INTERCEPT_STGI
);
3750 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3751 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3752 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3759 static int clgi_interception(struct vcpu_svm
*svm
)
3763 if (nested_svm_check_permissions(svm
))
3766 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3767 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3771 /* After a CLGI no interrupts should come */
3772 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3773 svm_clear_vintr(svm
);
3774 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3775 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3781 static int invlpga_interception(struct vcpu_svm
*svm
)
3783 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3785 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3786 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3788 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3789 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3791 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3792 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3795 static int skinit_interception(struct vcpu_svm
*svm
)
3797 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3799 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3803 static int wbinvd_interception(struct vcpu_svm
*svm
)
3805 return kvm_emulate_wbinvd(&svm
->vcpu
);
3808 static int xsetbv_interception(struct vcpu_svm
*svm
)
3810 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3811 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3813 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3814 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3815 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3821 static int task_switch_interception(struct vcpu_svm
*svm
)
3825 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3826 SVM_EXITINTINFO_TYPE_MASK
;
3827 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3829 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3831 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3832 bool has_error_code
= false;
3835 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3837 if (svm
->vmcb
->control
.exit_info_2
&
3838 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3839 reason
= TASK_SWITCH_IRET
;
3840 else if (svm
->vmcb
->control
.exit_info_2
&
3841 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3842 reason
= TASK_SWITCH_JMP
;
3844 reason
= TASK_SWITCH_GATE
;
3846 reason
= TASK_SWITCH_CALL
;
3848 if (reason
== TASK_SWITCH_GATE
) {
3850 case SVM_EXITINTINFO_TYPE_NMI
:
3851 svm
->vcpu
.arch
.nmi_injected
= false;
3853 case SVM_EXITINTINFO_TYPE_EXEPT
:
3854 if (svm
->vmcb
->control
.exit_info_2
&
3855 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3856 has_error_code
= true;
3858 (u32
)svm
->vmcb
->control
.exit_info_2
;
3860 kvm_clear_exception_queue(&svm
->vcpu
);
3862 case SVM_EXITINTINFO_TYPE_INTR
:
3863 kvm_clear_interrupt_queue(&svm
->vcpu
);
3870 if (reason
!= TASK_SWITCH_GATE
||
3871 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3872 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3873 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3874 skip_emulated_instruction(&svm
->vcpu
);
3876 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3879 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3880 has_error_code
, error_code
) == EMULATE_FAIL
) {
3881 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3882 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3883 svm
->vcpu
.run
->internal
.ndata
= 0;
3889 static int cpuid_interception(struct vcpu_svm
*svm
)
3891 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3892 return kvm_emulate_cpuid(&svm
->vcpu
);
3895 static int iret_interception(struct vcpu_svm
*svm
)
3897 ++svm
->vcpu
.stat
.nmi_window_exits
;
3898 clr_intercept(svm
, INTERCEPT_IRET
);
3899 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3900 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3901 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3905 static int invlpg_interception(struct vcpu_svm
*svm
)
3907 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3908 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3910 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3911 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3914 static int emulate_on_interception(struct vcpu_svm
*svm
)
3916 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3919 static int rsm_interception(struct vcpu_svm
*svm
)
3921 return kvm_emulate_instruction_from_buffer(&svm
->vcpu
,
3922 rsm_ins_bytes
, 2) == EMULATE_DONE
;
3925 static int rdpmc_interception(struct vcpu_svm
*svm
)
3929 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3930 return emulate_on_interception(svm
);
3932 err
= kvm_rdpmc(&svm
->vcpu
);
3933 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3936 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3939 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3943 intercept
= svm
->nested
.intercept
;
3945 if (!is_guest_mode(&svm
->vcpu
) ||
3946 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3949 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3950 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3953 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3954 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3960 #define CR_VALID (1ULL << 63)
3962 static int cr_interception(struct vcpu_svm
*svm
)
3968 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3969 return emulate_on_interception(svm
);
3971 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3972 return emulate_on_interception(svm
);
3974 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3975 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3976 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3978 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3981 if (cr
>= 16) { /* mov to cr */
3983 val
= kvm_register_read(&svm
->vcpu
, reg
);
3986 if (!check_selective_cr0_intercepted(svm
, val
))
3987 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3993 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3996 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3999 err
= kvm_set_cr8(&svm
->vcpu
, val
);
4002 WARN(1, "unhandled write to CR%d", cr
);
4003 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
4006 } else { /* mov from cr */
4009 val
= kvm_read_cr0(&svm
->vcpu
);
4012 val
= svm
->vcpu
.arch
.cr2
;
4015 val
= kvm_read_cr3(&svm
->vcpu
);
4018 val
= kvm_read_cr4(&svm
->vcpu
);
4021 val
= kvm_get_cr8(&svm
->vcpu
);
4024 WARN(1, "unhandled read from CR%d", cr
);
4025 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
4028 kvm_register_write(&svm
->vcpu
, reg
, val
);
4030 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
4033 static int dr_interception(struct vcpu_svm
*svm
)
4038 if (svm
->vcpu
.guest_debug
== 0) {
4040 * No more DR vmexits; force a reload of the debug registers
4041 * and reenter on this instruction. The next vmexit will
4042 * retrieve the full state of the debug registers.
4044 clr_dr_intercepts(svm
);
4045 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
4049 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
4050 return emulate_on_interception(svm
);
4052 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
4053 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
4055 if (dr
>= 16) { /* mov to DRn */
4056 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
4058 val
= kvm_register_read(&svm
->vcpu
, reg
);
4059 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
4061 if (!kvm_require_dr(&svm
->vcpu
, dr
))
4063 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
4064 kvm_register_write(&svm
->vcpu
, reg
, val
);
4067 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4070 static int cr8_write_interception(struct vcpu_svm
*svm
)
4072 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
4075 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
4076 /* instruction emulation calls kvm_set_cr8() */
4077 r
= cr_interception(svm
);
4078 if (lapic_in_kernel(&svm
->vcpu
))
4080 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
4082 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
4086 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
4090 switch (msr
->index
) {
4091 case MSR_F10H_DECFG
:
4092 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
4093 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
4102 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4104 struct vcpu_svm
*svm
= to_svm(vcpu
);
4106 switch (msr_info
->index
) {
4108 msr_info
->data
= svm
->vmcb
->save
.star
;
4110 #ifdef CONFIG_X86_64
4112 msr_info
->data
= svm
->vmcb
->save
.lstar
;
4115 msr_info
->data
= svm
->vmcb
->save
.cstar
;
4117 case MSR_KERNEL_GS_BASE
:
4118 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
4120 case MSR_SYSCALL_MASK
:
4121 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
4124 case MSR_IA32_SYSENTER_CS
:
4125 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
4127 case MSR_IA32_SYSENTER_EIP
:
4128 msr_info
->data
= svm
->sysenter_eip
;
4130 case MSR_IA32_SYSENTER_ESP
:
4131 msr_info
->data
= svm
->sysenter_esp
;
4134 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4136 msr_info
->data
= svm
->tsc_aux
;
4139 * Nobody will change the following 5 values in the VMCB so we can
4140 * safely return them on rdmsr. They will always be 0 until LBRV is
4143 case MSR_IA32_DEBUGCTLMSR
:
4144 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
4146 case MSR_IA32_LASTBRANCHFROMIP
:
4147 msr_info
->data
= svm
->vmcb
->save
.br_from
;
4149 case MSR_IA32_LASTBRANCHTOIP
:
4150 msr_info
->data
= svm
->vmcb
->save
.br_to
;
4152 case MSR_IA32_LASTINTFROMIP
:
4153 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
4155 case MSR_IA32_LASTINTTOIP
:
4156 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
4158 case MSR_VM_HSAVE_PA
:
4159 msr_info
->data
= svm
->nested
.hsave_msr
;
4162 msr_info
->data
= svm
->nested
.vm_cr_msr
;
4164 case MSR_IA32_SPEC_CTRL
:
4165 if (!msr_info
->host_initiated
&&
4166 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4167 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4170 msr_info
->data
= svm
->spec_ctrl
;
4172 case MSR_AMD64_VIRT_SPEC_CTRL
:
4173 if (!msr_info
->host_initiated
&&
4174 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4177 msr_info
->data
= svm
->virt_spec_ctrl
;
4179 case MSR_F15H_IC_CFG
: {
4183 family
= guest_cpuid_family(vcpu
);
4184 model
= guest_cpuid_model(vcpu
);
4186 if (family
< 0 || model
< 0)
4187 return kvm_get_msr_common(vcpu
, msr_info
);
4191 if (family
== 0x15 &&
4192 (model
>= 0x2 && model
< 0x20))
4193 msr_info
->data
= 0x1E;
4196 case MSR_F10H_DECFG
:
4197 msr_info
->data
= svm
->msr_decfg
;
4200 return kvm_get_msr_common(vcpu
, msr_info
);
4205 static int rdmsr_interception(struct vcpu_svm
*svm
)
4207 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4208 struct msr_data msr_info
;
4210 msr_info
.index
= ecx
;
4211 msr_info
.host_initiated
= false;
4212 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
4213 trace_kvm_msr_read_ex(ecx
);
4214 kvm_inject_gp(&svm
->vcpu
, 0);
4217 trace_kvm_msr_read(ecx
, msr_info
.data
);
4219 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
4220 msr_info
.data
& 0xffffffff);
4221 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
4222 msr_info
.data
>> 32);
4223 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4224 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4228 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
4230 struct vcpu_svm
*svm
= to_svm(vcpu
);
4231 int svm_dis
, chg_mask
;
4233 if (data
& ~SVM_VM_CR_VALID_MASK
)
4236 chg_mask
= SVM_VM_CR_VALID_MASK
;
4238 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
4239 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
4241 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
4242 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
4244 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
4246 /* check for svm_disable while efer.svme is set */
4247 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
4253 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
4255 struct vcpu_svm
*svm
= to_svm(vcpu
);
4257 u32 ecx
= msr
->index
;
4258 u64 data
= msr
->data
;
4260 case MSR_IA32_CR_PAT
:
4261 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
4263 vcpu
->arch
.pat
= data
;
4264 svm
->vmcb
->save
.g_pat
= data
;
4265 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4267 case MSR_IA32_SPEC_CTRL
:
4268 if (!msr
->host_initiated
&&
4269 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4270 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4273 /* The STIBP bit doesn't fault even if it's not advertised */
4274 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
4277 svm
->spec_ctrl
= data
;
4284 * When it's written (to non-zero) for the first time, pass
4288 * The handling of the MSR bitmap for L2 guests is done in
4289 * nested_svm_vmrun_msrpm.
4290 * We update the L1 MSR bit as well since it will end up
4291 * touching the MSR anyway now.
4293 set_msr_interception(svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
4295 case MSR_IA32_PRED_CMD
:
4296 if (!msr
->host_initiated
&&
4297 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBPB
))
4300 if (data
& ~PRED_CMD_IBPB
)
4306 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
4307 if (is_guest_mode(vcpu
))
4309 set_msr_interception(svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
4311 case MSR_AMD64_VIRT_SPEC_CTRL
:
4312 if (!msr
->host_initiated
&&
4313 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4316 if (data
& ~SPEC_CTRL_SSBD
)
4319 svm
->virt_spec_ctrl
= data
;
4322 svm
->vmcb
->save
.star
= data
;
4324 #ifdef CONFIG_X86_64
4326 svm
->vmcb
->save
.lstar
= data
;
4329 svm
->vmcb
->save
.cstar
= data
;
4331 case MSR_KERNEL_GS_BASE
:
4332 svm
->vmcb
->save
.kernel_gs_base
= data
;
4334 case MSR_SYSCALL_MASK
:
4335 svm
->vmcb
->save
.sfmask
= data
;
4338 case MSR_IA32_SYSENTER_CS
:
4339 svm
->vmcb
->save
.sysenter_cs
= data
;
4341 case MSR_IA32_SYSENTER_EIP
:
4342 svm
->sysenter_eip
= data
;
4343 svm
->vmcb
->save
.sysenter_eip
= data
;
4345 case MSR_IA32_SYSENTER_ESP
:
4346 svm
->sysenter_esp
= data
;
4347 svm
->vmcb
->save
.sysenter_esp
= data
;
4350 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4354 * This is rare, so we update the MSR here instead of using
4355 * direct_access_msrs. Doing that would require a rdmsr in
4358 svm
->tsc_aux
= data
;
4359 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
4361 case MSR_IA32_DEBUGCTLMSR
:
4362 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
4363 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4367 if (data
& DEBUGCTL_RESERVED_BITS
)
4370 svm
->vmcb
->save
.dbgctl
= data
;
4371 mark_dirty(svm
->vmcb
, VMCB_LBR
);
4372 if (data
& (1ULL<<0))
4373 svm_enable_lbrv(svm
);
4375 svm_disable_lbrv(svm
);
4377 case MSR_VM_HSAVE_PA
:
4378 svm
->nested
.hsave_msr
= data
;
4381 return svm_set_vm_cr(vcpu
, data
);
4383 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
4385 case MSR_F10H_DECFG
: {
4386 struct kvm_msr_entry msr_entry
;
4388 msr_entry
.index
= msr
->index
;
4389 if (svm_get_msr_feature(&msr_entry
))
4392 /* Check the supported bits */
4393 if (data
& ~msr_entry
.data
)
4396 /* Don't allow the guest to change a bit, #GP */
4397 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
4400 svm
->msr_decfg
= data
;
4403 case MSR_IA32_APICBASE
:
4404 if (kvm_vcpu_apicv_active(vcpu
))
4405 avic_update_vapic_bar(to_svm(vcpu
), data
);
4408 return kvm_set_msr_common(vcpu
, msr
);
4413 static int wrmsr_interception(struct vcpu_svm
*svm
)
4415 struct msr_data msr
;
4416 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4417 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
4421 msr
.host_initiated
= false;
4423 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4424 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
4425 trace_kvm_msr_write_ex(ecx
, data
);
4426 kvm_inject_gp(&svm
->vcpu
, 0);
4429 trace_kvm_msr_write(ecx
, data
);
4430 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4434 static int msr_interception(struct vcpu_svm
*svm
)
4436 if (svm
->vmcb
->control
.exit_info_1
)
4437 return wrmsr_interception(svm
);
4439 return rdmsr_interception(svm
);
4442 static int interrupt_window_interception(struct vcpu_svm
*svm
)
4444 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4445 svm_clear_vintr(svm
);
4446 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
4447 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4448 ++svm
->vcpu
.stat
.irq_window_exits
;
4452 static int pause_interception(struct vcpu_svm
*svm
)
4454 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
4455 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
4457 if (pause_filter_thresh
)
4458 grow_ple_window(vcpu
);
4460 kvm_vcpu_on_spin(vcpu
, in_kernel
);
4464 static int nop_interception(struct vcpu_svm
*svm
)
4466 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
4469 static int monitor_interception(struct vcpu_svm
*svm
)
4471 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
4472 return nop_interception(svm
);
4475 static int mwait_interception(struct vcpu_svm
*svm
)
4477 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
4478 return nop_interception(svm
);
4481 enum avic_ipi_failure_cause
{
4482 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
4483 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
4484 AVIC_IPI_FAILURE_INVALID_TARGET
,
4485 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
4488 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
4490 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
4491 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
4492 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
4493 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
4494 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4496 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
4499 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
4501 * AVIC hardware handles the generation of
4502 * IPIs when the specified Message Type is Fixed
4503 * (also known as fixed delivery mode) and
4504 * the Trigger Mode is edge-triggered. The hardware
4505 * also supports self and broadcast delivery modes
4506 * specified via the Destination Shorthand(DSH)
4507 * field of the ICRL. Logical and physical APIC ID
4508 * formats are supported. All other IPI types cause
4509 * a #VMEXIT, which needs to emulated.
4511 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
4512 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
4514 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
4515 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4518 * Update ICR high and low, then emulate sending IPI,
4519 * which is handled when writing APIC_ICR.
4521 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
4522 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
4525 case AVIC_IPI_FAILURE_INVALID_TARGET
:
4526 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
4527 index
, svm
->vcpu
.vcpu_id
, icrh
, icrl
);
4529 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
4530 WARN_ONCE(1, "Invalid backing page\n");
4533 pr_err("Unknown IPI interception\n");
4539 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
4541 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4543 u32
*logical_apic_id_table
;
4544 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
4549 if (flat
) { /* flat */
4550 index
= ffs(dlid
) - 1;
4553 } else { /* cluster */
4554 int cluster
= (dlid
& 0xf0) >> 4;
4555 int apic
= ffs(dlid
& 0x0f) - 1;
4557 if ((apic
< 0) || (apic
> 7) ||
4560 index
= (cluster
<< 2) + apic
;
4563 logical_apic_id_table
= (u32
*) page_address(kvm_svm
->avic_logical_id_table_page
);
4565 return &logical_apic_id_table
[index
];
4568 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
4572 u32
*entry
, new_entry
;
4574 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
4575 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
4579 new_entry
= READ_ONCE(*entry
);
4580 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
4581 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
4583 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4585 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4586 WRITE_ONCE(*entry
, new_entry
);
4591 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
4594 struct vcpu_svm
*svm
= to_svm(vcpu
);
4595 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
4600 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
4601 if (ret
&& svm
->ldr_reg
) {
4602 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
4610 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
4613 struct vcpu_svm
*svm
= to_svm(vcpu
);
4614 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
4615 u32 id
= (apic_id_reg
>> 24) & 0xff;
4617 if (vcpu
->vcpu_id
== id
)
4620 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
4621 new = avic_get_physical_id_entry(vcpu
, id
);
4625 /* We need to move physical_id_entry to new offset */
4628 to_svm(vcpu
)->avic_physical_id_cache
= new;
4631 * Also update the guest physical APIC ID in the logical
4632 * APIC ID table entry if already setup the LDR.
4635 avic_handle_ldr_update(vcpu
);
4640 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
4642 struct vcpu_svm
*svm
= to_svm(vcpu
);
4643 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4644 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
4645 u32 mod
= (dfr
>> 28) & 0xf;
4648 * We assume that all local APICs are using the same type.
4649 * If this changes, we need to flush the AVIC logical
4652 if (kvm_svm
->ldr_mode
== mod
)
4655 clear_page(page_address(kvm_svm
->avic_logical_id_table_page
));
4656 kvm_svm
->ldr_mode
= mod
;
4659 avic_handle_ldr_update(vcpu
);
4663 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4665 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4666 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4667 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4671 if (avic_handle_apic_id_update(&svm
->vcpu
))
4675 if (avic_handle_ldr_update(&svm
->vcpu
))
4679 avic_handle_dfr_update(&svm
->vcpu
);
4685 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4690 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4719 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4722 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4723 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4724 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4725 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4726 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4727 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4728 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4730 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4731 trap
, write
, vector
);
4734 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4735 ret
= avic_unaccel_trap_write(svm
);
4737 /* Handling Fault */
4738 ret
= (kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4744 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4745 [SVM_EXIT_READ_CR0
] = cr_interception
,
4746 [SVM_EXIT_READ_CR3
] = cr_interception
,
4747 [SVM_EXIT_READ_CR4
] = cr_interception
,
4748 [SVM_EXIT_READ_CR8
] = cr_interception
,
4749 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4750 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4751 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4752 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4753 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4754 [SVM_EXIT_READ_DR0
] = dr_interception
,
4755 [SVM_EXIT_READ_DR1
] = dr_interception
,
4756 [SVM_EXIT_READ_DR2
] = dr_interception
,
4757 [SVM_EXIT_READ_DR3
] = dr_interception
,
4758 [SVM_EXIT_READ_DR4
] = dr_interception
,
4759 [SVM_EXIT_READ_DR5
] = dr_interception
,
4760 [SVM_EXIT_READ_DR6
] = dr_interception
,
4761 [SVM_EXIT_READ_DR7
] = dr_interception
,
4762 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4763 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4764 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4765 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4766 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4767 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4768 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4769 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4770 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4771 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4772 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4773 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4774 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4775 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4776 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
4777 [SVM_EXIT_INTR
] = intr_interception
,
4778 [SVM_EXIT_NMI
] = nmi_interception
,
4779 [SVM_EXIT_SMI
] = nop_on_interception
,
4780 [SVM_EXIT_INIT
] = nop_on_interception
,
4781 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4782 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4783 [SVM_EXIT_CPUID
] = cpuid_interception
,
4784 [SVM_EXIT_IRET
] = iret_interception
,
4785 [SVM_EXIT_INVD
] = emulate_on_interception
,
4786 [SVM_EXIT_PAUSE
] = pause_interception
,
4787 [SVM_EXIT_HLT
] = halt_interception
,
4788 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4789 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4790 [SVM_EXIT_IOIO
] = io_interception
,
4791 [SVM_EXIT_MSR
] = msr_interception
,
4792 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4793 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4794 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4795 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4796 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4797 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4798 [SVM_EXIT_STGI
] = stgi_interception
,
4799 [SVM_EXIT_CLGI
] = clgi_interception
,
4800 [SVM_EXIT_SKINIT
] = skinit_interception
,
4801 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4802 [SVM_EXIT_MONITOR
] = monitor_interception
,
4803 [SVM_EXIT_MWAIT
] = mwait_interception
,
4804 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4805 [SVM_EXIT_NPF
] = npf_interception
,
4806 [SVM_EXIT_RSM
] = rsm_interception
,
4807 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4808 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4811 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4813 struct vcpu_svm
*svm
= to_svm(vcpu
);
4814 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4815 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4817 pr_err("VMCB Control Area:\n");
4818 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4819 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4820 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4821 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4822 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4823 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4824 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4825 pr_err("%-20s%d\n", "pause filter threshold:",
4826 control
->pause_filter_thresh
);
4827 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4828 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4829 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4830 pr_err("%-20s%d\n", "asid:", control
->asid
);
4831 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4832 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4833 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4834 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4835 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4836 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4837 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4838 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4839 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4840 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4841 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4842 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4843 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4844 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4845 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4846 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4847 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4848 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4849 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4850 pr_err("VMCB State Save Area:\n");
4851 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853 save
->es
.selector
, save
->es
.attrib
,
4854 save
->es
.limit
, save
->es
.base
);
4855 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4857 save
->cs
.selector
, save
->cs
.attrib
,
4858 save
->cs
.limit
, save
->cs
.base
);
4859 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4861 save
->ss
.selector
, save
->ss
.attrib
,
4862 save
->ss
.limit
, save
->ss
.base
);
4863 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4865 save
->ds
.selector
, save
->ds
.attrib
,
4866 save
->ds
.limit
, save
->ds
.base
);
4867 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4869 save
->fs
.selector
, save
->fs
.attrib
,
4870 save
->fs
.limit
, save
->fs
.base
);
4871 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4873 save
->gs
.selector
, save
->gs
.attrib
,
4874 save
->gs
.limit
, save
->gs
.base
);
4875 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4877 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4878 save
->gdtr
.limit
, save
->gdtr
.base
);
4879 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4881 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4882 save
->ldtr
.limit
, save
->ldtr
.base
);
4883 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4885 save
->idtr
.selector
, save
->idtr
.attrib
,
4886 save
->idtr
.limit
, save
->idtr
.base
);
4887 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4889 save
->tr
.selector
, save
->tr
.attrib
,
4890 save
->tr
.limit
, save
->tr
.base
);
4891 pr_err("cpl: %d efer: %016llx\n",
4892 save
->cpl
, save
->efer
);
4893 pr_err("%-15s %016llx %-13s %016llx\n",
4894 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4895 pr_err("%-15s %016llx %-13s %016llx\n",
4896 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4897 pr_err("%-15s %016llx %-13s %016llx\n",
4898 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4899 pr_err("%-15s %016llx %-13s %016llx\n",
4900 "rip:", save
->rip
, "rflags:", save
->rflags
);
4901 pr_err("%-15s %016llx %-13s %016llx\n",
4902 "rsp:", save
->rsp
, "rax:", save
->rax
);
4903 pr_err("%-15s %016llx %-13s %016llx\n",
4904 "star:", save
->star
, "lstar:", save
->lstar
);
4905 pr_err("%-15s %016llx %-13s %016llx\n",
4906 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4907 pr_err("%-15s %016llx %-13s %016llx\n",
4908 "kernel_gs_base:", save
->kernel_gs_base
,
4909 "sysenter_cs:", save
->sysenter_cs
);
4910 pr_err("%-15s %016llx %-13s %016llx\n",
4911 "sysenter_esp:", save
->sysenter_esp
,
4912 "sysenter_eip:", save
->sysenter_eip
);
4913 pr_err("%-15s %016llx %-13s %016llx\n",
4914 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4915 pr_err("%-15s %016llx %-13s %016llx\n",
4916 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4917 pr_err("%-15s %016llx %-13s %016llx\n",
4918 "excp_from:", save
->last_excp_from
,
4919 "excp_to:", save
->last_excp_to
);
4922 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4924 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4926 *info1
= control
->exit_info_1
;
4927 *info2
= control
->exit_info_2
;
4930 static int handle_exit(struct kvm_vcpu
*vcpu
)
4932 struct vcpu_svm
*svm
= to_svm(vcpu
);
4933 struct kvm_run
*kvm_run
= vcpu
->run
;
4934 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4936 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4938 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4939 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4941 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4943 if (unlikely(svm
->nested
.exit_required
)) {
4944 nested_svm_vmexit(svm
);
4945 svm
->nested
.exit_required
= false;
4950 if (is_guest_mode(vcpu
)) {
4953 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4954 svm
->vmcb
->control
.exit_info_1
,
4955 svm
->vmcb
->control
.exit_info_2
,
4956 svm
->vmcb
->control
.exit_int_info
,
4957 svm
->vmcb
->control
.exit_int_info_err
,
4960 vmexit
= nested_svm_exit_special(svm
);
4962 if (vmexit
== NESTED_EXIT_CONTINUE
)
4963 vmexit
= nested_svm_exit_handled(svm
);
4965 if (vmexit
== NESTED_EXIT_DONE
)
4969 svm_complete_interrupts(svm
);
4971 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4972 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4973 kvm_run
->fail_entry
.hardware_entry_failure_reason
4974 = svm
->vmcb
->control
.exit_code
;
4975 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4980 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4981 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4982 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4983 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4984 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4986 __func__
, svm
->vmcb
->control
.exit_int_info
,
4989 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4990 || !svm_exit_handlers
[exit_code
]) {
4991 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4992 kvm_queue_exception(vcpu
, UD_VECTOR
);
4996 return svm_exit_handlers
[exit_code
](svm
);
4999 static void reload_tss(struct kvm_vcpu
*vcpu
)
5001 int cpu
= raw_smp_processor_id();
5003 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5004 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
5008 static void pre_sev_run(struct vcpu_svm
*svm
, int cpu
)
5010 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5011 int asid
= sev_get_asid(svm
->vcpu
.kvm
);
5013 /* Assign the asid allocated with this SEV guest */
5014 svm
->vmcb
->control
.asid
= asid
;
5019 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5020 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5022 if (sd
->sev_vmcbs
[asid
] == svm
->vmcb
&&
5023 svm
->last_cpu
== cpu
)
5026 svm
->last_cpu
= cpu
;
5027 sd
->sev_vmcbs
[asid
] = svm
->vmcb
;
5028 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5029 mark_dirty(svm
->vmcb
, VMCB_ASID
);
5032 static void pre_svm_run(struct vcpu_svm
*svm
)
5034 int cpu
= raw_smp_processor_id();
5036 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5038 if (sev_guest(svm
->vcpu
.kvm
))
5039 return pre_sev_run(svm
, cpu
);
5041 /* FIXME: handle wraparound of asid_generation */
5042 if (svm
->asid_generation
!= sd
->asid_generation
)
5046 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
5048 struct vcpu_svm
*svm
= to_svm(vcpu
);
5050 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
5051 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
5052 set_intercept(svm
, INTERCEPT_IRET
);
5053 ++vcpu
->stat
.nmi_injections
;
5056 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
5058 struct vmcb_control_area
*control
;
5060 /* The following fields are ignored when AVIC is enabled */
5061 control
= &svm
->vmcb
->control
;
5062 control
->int_vector
= irq
;
5063 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
5064 control
->int_ctl
|= V_IRQ_MASK
|
5065 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
5066 mark_dirty(svm
->vmcb
, VMCB_INTR
);
5069 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
5071 struct vcpu_svm
*svm
= to_svm(vcpu
);
5073 BUG_ON(!(gif_set(svm
)));
5075 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
5076 ++vcpu
->stat
.irq_injections
;
5078 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
5079 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
5082 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
5084 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
5087 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5089 struct vcpu_svm
*svm
= to_svm(vcpu
);
5091 if (svm_nested_virtualize_tpr(vcpu
) ||
5092 kvm_vcpu_apicv_active(vcpu
))
5095 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5101 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5104 static void svm_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
5109 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5111 return avic
&& irqchip_split(vcpu
->kvm
);
5114 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
5118 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
5122 /* Note: Currently only used by Hyper-V. */
5123 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5125 struct vcpu_svm
*svm
= to_svm(vcpu
);
5126 struct vmcb
*vmcb
= svm
->vmcb
;
5128 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
5131 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
5132 mark_dirty(vmcb
, VMCB_INTR
);
5135 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
5140 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
5142 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
5143 smp_mb__after_atomic();
5145 if (avic_vcpu_is_running(vcpu
))
5146 wrmsrl(SVM_AVIC_DOORBELL
,
5147 kvm_cpu_get_apicid(vcpu
->cpu
));
5149 kvm_vcpu_wake_up(vcpu
);
5152 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5154 unsigned long flags
;
5155 struct amd_svm_iommu_ir
*cur
;
5157 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5158 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
5159 if (cur
->data
!= pi
->ir_data
)
5161 list_del(&cur
->node
);
5165 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5168 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5171 unsigned long flags
;
5172 struct amd_svm_iommu_ir
*ir
;
5175 * In some cases, the existing irte is updaed and re-set,
5176 * so we need to check here if it's already been * added
5179 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
5180 struct kvm
*kvm
= svm
->vcpu
.kvm
;
5181 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
5182 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
5183 struct vcpu_svm
*prev_svm
;
5190 prev_svm
= to_svm(prev_vcpu
);
5191 svm_ir_list_del(prev_svm
, pi
);
5195 * Allocating new amd_iommu_pi_data, which will get
5196 * add to the per-vcpu ir_list.
5198 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
5203 ir
->data
= pi
->ir_data
;
5205 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5206 list_add(&ir
->node
, &svm
->ir_list
);
5207 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5214 * The HW cannot support posting multicast/broadcast
5215 * interrupts to a vCPU. So, we still use legacy interrupt
5216 * remapping for these kind of interrupts.
5218 * For lowest-priority interrupts, we only support
5219 * those with single CPU as the destination, e.g. user
5220 * configures the interrupts via /proc/irq or uses
5221 * irqbalance to make the interrupts single-CPU.
5224 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
5225 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
5227 struct kvm_lapic_irq irq
;
5228 struct kvm_vcpu
*vcpu
= NULL
;
5230 kvm_set_msi_irq(kvm
, e
, &irq
);
5232 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
5233 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5234 __func__
, irq
.vector
);
5238 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
5240 *svm
= to_svm(vcpu
);
5241 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
5242 vcpu_info
->vector
= irq
.vector
;
5248 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5251 * @host_irq: host irq of the interrupt
5252 * @guest_irq: gsi of the interrupt
5253 * @set: set or unset PI
5254 * returns 0 on success, < 0 on failure
5256 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
5257 uint32_t guest_irq
, bool set
)
5259 struct kvm_kernel_irq_routing_entry
*e
;
5260 struct kvm_irq_routing_table
*irq_rt
;
5261 int idx
, ret
= -EINVAL
;
5263 if (!kvm_arch_has_assigned_device(kvm
) ||
5264 !irq_remapping_cap(IRQ_POSTING_CAP
))
5267 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5268 __func__
, host_irq
, guest_irq
, set
);
5270 idx
= srcu_read_lock(&kvm
->irq_srcu
);
5271 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
5272 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
5274 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
5275 struct vcpu_data vcpu_info
;
5276 struct vcpu_svm
*svm
= NULL
;
5278 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
5282 * Here, we setup with legacy mode in the following cases:
5283 * 1. When cannot target interrupt to a specific vcpu.
5284 * 2. Unsetting posted interrupt.
5285 * 3. APIC virtialization is disabled for the vcpu.
5287 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
5288 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
5289 struct amd_iommu_pi_data pi
;
5291 /* Try to enable guest_mode in IRTE */
5292 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
5294 pi
.ga_tag
= AVIC_GATAG(to_kvm_svm(kvm
)->avic_vm_id
,
5296 pi
.is_guest_mode
= true;
5297 pi
.vcpu_data
= &vcpu_info
;
5298 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5301 * Here, we successfully setting up vcpu affinity in
5302 * IOMMU guest mode. Now, we need to store the posted
5303 * interrupt information in a per-vcpu ir_list so that
5304 * we can reference to them directly when we update vcpu
5305 * scheduling information in IOMMU irte.
5307 if (!ret
&& pi
.is_guest_mode
)
5308 svm_ir_list_add(svm
, &pi
);
5310 /* Use legacy mode in IRTE */
5311 struct amd_iommu_pi_data pi
;
5314 * Here, pi is used to:
5315 * - Tell IOMMU to use legacy mode for this interrupt.
5316 * - Retrieve ga_tag of prior interrupt remapping data.
5318 pi
.is_guest_mode
= false;
5319 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5322 * Check if the posted interrupt was previously
5323 * setup with the guest_mode by checking if the ga_tag
5324 * was cached. If so, we need to clean up the per-vcpu
5327 if (!ret
&& pi
.prev_ga_tag
) {
5328 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
5329 struct kvm_vcpu
*vcpu
;
5331 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
5333 svm_ir_list_del(to_svm(vcpu
), &pi
);
5338 trace_kvm_pi_irte_update(host_irq
, svm
->vcpu
.vcpu_id
,
5339 e
->gsi
, vcpu_info
.vector
,
5340 vcpu_info
.pi_desc_addr
, set
);
5344 pr_err("%s: failed to update PI IRTE\n", __func__
);
5351 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
5355 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
5357 struct vcpu_svm
*svm
= to_svm(vcpu
);
5358 struct vmcb
*vmcb
= svm
->vmcb
;
5360 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
5361 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5362 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
5367 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5369 struct vcpu_svm
*svm
= to_svm(vcpu
);
5371 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5374 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5376 struct vcpu_svm
*svm
= to_svm(vcpu
);
5379 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
5380 set_intercept(svm
, INTERCEPT_IRET
);
5382 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
5383 clr_intercept(svm
, INTERCEPT_IRET
);
5387 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5389 struct vcpu_svm
*svm
= to_svm(vcpu
);
5390 struct vmcb
*vmcb
= svm
->vmcb
;
5393 if (!gif_set(svm
) ||
5394 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
5397 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
5399 if (is_guest_mode(vcpu
))
5400 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
5405 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5407 struct vcpu_svm
*svm
= to_svm(vcpu
);
5409 if (kvm_vcpu_apicv_active(vcpu
))
5413 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5414 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5415 * get that intercept, this function will be called again though and
5416 * we'll get the vintr intercept. However, if the vGIF feature is
5417 * enabled, the STGI interception will not occur. Enable the irq
5418 * window under the assumption that the hardware will set the GIF.
5420 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
5422 svm_inject_irq(svm
, 0x0);
5426 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5428 struct vcpu_svm
*svm
= to_svm(vcpu
);
5430 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
5432 return; /* IRET will cause a vm exit */
5434 if (!gif_set(svm
)) {
5435 if (vgif_enabled(svm
))
5436 set_intercept(svm
, INTERCEPT_STGI
);
5437 return; /* STGI will cause a vm exit */
5440 if (svm
->nested
.exit_required
)
5441 return; /* we're not going to run the guest yet */
5444 * Something prevents NMI from been injected. Single step over possible
5445 * problem (IRET or exception injection or interrupt shadow)
5447 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
5448 svm
->nmi_singlestep
= true;
5449 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
5452 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5457 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
5462 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
5464 struct vcpu_svm
*svm
= to_svm(vcpu
);
5466 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
5467 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5469 svm
->asid_generation
--;
5472 static void svm_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t gva
)
5474 struct vcpu_svm
*svm
= to_svm(vcpu
);
5476 invlpga(gva
, svm
->vmcb
->control
.asid
);
5479 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
5483 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
5485 struct vcpu_svm
*svm
= to_svm(vcpu
);
5487 if (svm_nested_virtualize_tpr(vcpu
))
5490 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
5491 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
5492 kvm_set_cr8(vcpu
, cr8
);
5496 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
5498 struct vcpu_svm
*svm
= to_svm(vcpu
);
5501 if (svm_nested_virtualize_tpr(vcpu
) ||
5502 kvm_vcpu_apicv_active(vcpu
))
5505 cr8
= kvm_get_cr8(vcpu
);
5506 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
5507 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
5510 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
5514 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
5515 unsigned int3_injected
= svm
->int3_injected
;
5517 svm
->int3_injected
= 0;
5520 * If we've made progress since setting HF_IRET_MASK, we've
5521 * executed an IRET and can allow NMI injection.
5523 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
5524 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
5525 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
5526 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5529 svm
->vcpu
.arch
.nmi_injected
= false;
5530 kvm_clear_exception_queue(&svm
->vcpu
);
5531 kvm_clear_interrupt_queue(&svm
->vcpu
);
5533 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
5536 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5538 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
5539 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
5542 case SVM_EXITINTINFO_TYPE_NMI
:
5543 svm
->vcpu
.arch
.nmi_injected
= true;
5545 case SVM_EXITINTINFO_TYPE_EXEPT
:
5547 * In case of software exceptions, do not reinject the vector,
5548 * but re-execute the instruction instead. Rewind RIP first
5549 * if we emulated INT3 before.
5551 if (kvm_exception_is_soft(vector
)) {
5552 if (vector
== BP_VECTOR
&& int3_injected
&&
5553 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
5554 kvm_rip_write(&svm
->vcpu
,
5555 kvm_rip_read(&svm
->vcpu
) -
5559 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
5560 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
5561 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
5564 kvm_requeue_exception(&svm
->vcpu
, vector
);
5566 case SVM_EXITINTINFO_TYPE_INTR
:
5567 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
5574 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
5576 struct vcpu_svm
*svm
= to_svm(vcpu
);
5577 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
5579 control
->exit_int_info
= control
->event_inj
;
5580 control
->exit_int_info_err
= control
->event_inj_err
;
5581 control
->event_inj
= 0;
5582 svm_complete_interrupts(svm
);
5585 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
5587 struct vcpu_svm
*svm
= to_svm(vcpu
);
5589 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5590 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5591 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5594 * A vmexit emulation is required before the vcpu can be executed
5597 if (unlikely(svm
->nested
.exit_required
))
5601 * Disable singlestep if we're injecting an interrupt/exception.
5602 * We don't want our modified rflags to be pushed on the stack where
5603 * we might not be able to easily reset them if we disabled NMI
5606 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
5608 * Event injection happens before external interrupts cause a
5609 * vmexit and interrupts are disabled here, so smp_send_reschedule
5610 * is enough to force an immediate vmexit.
5612 disable_nmi_singlestep(svm
);
5613 smp_send_reschedule(vcpu
->cpu
);
5618 sync_lapic_to_cr8(vcpu
);
5620 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
5625 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5626 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5627 * is no need to worry about the conditional branch over the wrmsr
5628 * being speculatively taken.
5630 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5635 "push %%" _ASM_BP
"; \n\t"
5636 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
5637 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
5638 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
5639 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
5640 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
5641 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
5642 #ifdef CONFIG_X86_64
5643 "mov %c[r8](%[svm]), %%r8 \n\t"
5644 "mov %c[r9](%[svm]), %%r9 \n\t"
5645 "mov %c[r10](%[svm]), %%r10 \n\t"
5646 "mov %c[r11](%[svm]), %%r11 \n\t"
5647 "mov %c[r12](%[svm]), %%r12 \n\t"
5648 "mov %c[r13](%[svm]), %%r13 \n\t"
5649 "mov %c[r14](%[svm]), %%r14 \n\t"
5650 "mov %c[r15](%[svm]), %%r15 \n\t"
5653 /* Enter guest mode */
5654 "push %%" _ASM_AX
" \n\t"
5655 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
5656 __ex("vmload %%" _ASM_AX
) "\n\t"
5657 __ex("vmrun %%" _ASM_AX
) "\n\t"
5658 __ex("vmsave %%" _ASM_AX
) "\n\t"
5659 "pop %%" _ASM_AX
" \n\t"
5661 /* Save guest registers, load host registers */
5662 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
5663 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
5664 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
5665 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
5666 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
5667 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
5668 #ifdef CONFIG_X86_64
5669 "mov %%r8, %c[r8](%[svm]) \n\t"
5670 "mov %%r9, %c[r9](%[svm]) \n\t"
5671 "mov %%r10, %c[r10](%[svm]) \n\t"
5672 "mov %%r11, %c[r11](%[svm]) \n\t"
5673 "mov %%r12, %c[r12](%[svm]) \n\t"
5674 "mov %%r13, %c[r13](%[svm]) \n\t"
5675 "mov %%r14, %c[r14](%[svm]) \n\t"
5676 "mov %%r15, %c[r15](%[svm]) \n\t"
5678 * Clear host registers marked as clobbered to prevent
5681 "xor %%r8d, %%r8d \n\t"
5682 "xor %%r9d, %%r9d \n\t"
5683 "xor %%r10d, %%r10d \n\t"
5684 "xor %%r11d, %%r11d \n\t"
5685 "xor %%r12d, %%r12d \n\t"
5686 "xor %%r13d, %%r13d \n\t"
5687 "xor %%r14d, %%r14d \n\t"
5688 "xor %%r15d, %%r15d \n\t"
5690 "xor %%ebx, %%ebx \n\t"
5691 "xor %%ecx, %%ecx \n\t"
5692 "xor %%edx, %%edx \n\t"
5693 "xor %%esi, %%esi \n\t"
5694 "xor %%edi, %%edi \n\t"
5698 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
5699 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5700 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5701 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5702 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5703 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5704 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
5705 #ifdef CONFIG_X86_64
5706 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5707 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5708 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5709 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5710 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5711 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5712 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5713 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
5716 #ifdef CONFIG_X86_64
5717 , "rbx", "rcx", "rdx", "rsi", "rdi"
5718 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5720 , "ebx", "ecx", "edx", "esi", "edi"
5724 /* Eliminate branch target predictions from guest mode */
5727 #ifdef CONFIG_X86_64
5728 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5730 loadsegment(fs
, svm
->host
.fs
);
5731 #ifndef CONFIG_X86_32_LAZY_GS
5732 loadsegment(gs
, svm
->host
.gs
);
5737 * We do not use IBRS in the kernel. If this vCPU has used the
5738 * SPEC_CTRL MSR it may have left it on; save the value and
5739 * turn it off. This is much more efficient than blindly adding
5740 * it to the atomic save/restore list. Especially as the former
5741 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5743 * For non-nested case:
5744 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5748 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5751 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
5752 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
5756 local_irq_disable();
5758 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5760 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5761 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5762 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5763 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5765 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5766 kvm_before_interrupt(&svm
->vcpu
);
5770 /* Any pending NMI will happen here */
5772 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5773 kvm_after_interrupt(&svm
->vcpu
);
5775 sync_cr8_to_lapic(vcpu
);
5779 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5781 /* if exit due to PF check for async PF */
5782 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5783 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5786 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5787 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5791 * We need to handle MC intercepts here before the vcpu has a chance to
5792 * change the physical cpu
5794 if (unlikely(svm
->vmcb
->control
.exit_code
==
5795 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5796 svm_handle_mce(svm
);
5798 mark_all_clean(svm
->vmcb
);
5800 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5802 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5804 struct vcpu_svm
*svm
= to_svm(vcpu
);
5806 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5807 mark_dirty(svm
->vmcb
, VMCB_CR
);
5810 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5812 struct vcpu_svm
*svm
= to_svm(vcpu
);
5814 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5815 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5817 /* Also sync guest cr3 here in case we live migrate */
5818 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5819 mark_dirty(svm
->vmcb
, VMCB_CR
);
5822 static int is_disabled(void)
5826 rdmsrl(MSR_VM_CR
, vm_cr
);
5827 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5834 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5837 * Patch in the VMMCALL instruction:
5839 hypercall
[0] = 0x0f;
5840 hypercall
[1] = 0x01;
5841 hypercall
[2] = 0xd9;
5844 static void svm_check_processor_compat(void *rtn
)
5849 static bool svm_cpu_has_accelerated_tpr(void)
5854 static bool svm_has_emulated_msr(int index
)
5857 case MSR_IA32_MCG_EXT_CTL
:
5866 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5871 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5873 struct vcpu_svm
*svm
= to_svm(vcpu
);
5875 /* Update nrips enabled cache */
5876 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5878 if (!kvm_vcpu_apicv_active(vcpu
))
5881 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5884 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5889 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5893 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5896 entry
->eax
= 1; /* SVM revision 1 */
5897 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5898 ASID emulation to nested SVM */
5899 entry
->ecx
= 0; /* Reserved */
5900 entry
->edx
= 0; /* Per default do not support any
5901 additional features */
5903 /* Support next_rip if host supports it */
5904 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5905 entry
->edx
|= SVM_FEATURE_NRIP
;
5907 /* Support NPT for the guest if enabled */
5909 entry
->edx
|= SVM_FEATURE_NPT
;
5913 /* Support memory encryption cpuid if host supports it */
5914 if (boot_cpu_has(X86_FEATURE_SEV
))
5915 cpuid(0x8000001f, &entry
->eax
, &entry
->ebx
,
5916 &entry
->ecx
, &entry
->edx
);
5921 static int svm_get_lpage_level(void)
5923 return PT_PDPE_LEVEL
;
5926 static bool svm_rdtscp_supported(void)
5928 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5931 static bool svm_invpcid_supported(void)
5936 static bool svm_mpx_supported(void)
5941 static bool svm_xsaves_supported(void)
5946 static bool svm_umip_emulated(void)
5951 static bool svm_pt_supported(void)
5956 static bool svm_has_wbinvd_exit(void)
5961 #define PRE_EX(exit) { .exit_code = (exit), \
5962 .stage = X86_ICPT_PRE_EXCEPT, }
5963 #define POST_EX(exit) { .exit_code = (exit), \
5964 .stage = X86_ICPT_POST_EXCEPT, }
5965 #define POST_MEM(exit) { .exit_code = (exit), \
5966 .stage = X86_ICPT_POST_MEMACCESS, }
5968 static const struct __x86_intercept
{
5970 enum x86_intercept_stage stage
;
5971 } x86_intercept_map
[] = {
5972 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5973 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5974 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5975 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5976 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5977 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5978 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5979 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5980 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5981 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5982 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5983 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5984 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5985 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5986 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5987 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5988 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5989 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5990 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5991 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5992 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5993 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5994 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5995 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5996 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5997 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5998 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5999 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
6000 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
6001 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
6002 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
6003 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
6004 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
6005 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
6006 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
6007 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
6008 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
6009 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
6010 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
6011 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
6012 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
6013 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
6014 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
6015 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
6016 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
6017 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
6024 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
6025 struct x86_instruction_info
*info
,
6026 enum x86_intercept_stage stage
)
6028 struct vcpu_svm
*svm
= to_svm(vcpu
);
6029 int vmexit
, ret
= X86EMUL_CONTINUE
;
6030 struct __x86_intercept icpt_info
;
6031 struct vmcb
*vmcb
= svm
->vmcb
;
6033 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
6036 icpt_info
= x86_intercept_map
[info
->intercept
];
6038 if (stage
!= icpt_info
.stage
)
6041 switch (icpt_info
.exit_code
) {
6042 case SVM_EXIT_READ_CR0
:
6043 if (info
->intercept
== x86_intercept_cr_read
)
6044 icpt_info
.exit_code
+= info
->modrm_reg
;
6046 case SVM_EXIT_WRITE_CR0
: {
6047 unsigned long cr0
, val
;
6050 if (info
->intercept
== x86_intercept_cr_write
)
6051 icpt_info
.exit_code
+= info
->modrm_reg
;
6053 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
6054 info
->intercept
== x86_intercept_clts
)
6057 intercept
= svm
->nested
.intercept
;
6059 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
6062 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
6063 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
6065 if (info
->intercept
== x86_intercept_lmsw
) {
6068 /* lmsw can't clear PE - catch this here */
6069 if (cr0
& X86_CR0_PE
)
6074 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
6078 case SVM_EXIT_READ_DR0
:
6079 case SVM_EXIT_WRITE_DR0
:
6080 icpt_info
.exit_code
+= info
->modrm_reg
;
6083 if (info
->intercept
== x86_intercept_wrmsr
)
6084 vmcb
->control
.exit_info_1
= 1;
6086 vmcb
->control
.exit_info_1
= 0;
6088 case SVM_EXIT_PAUSE
:
6090 * We get this for NOP only, but pause
6091 * is rep not, check this here
6093 if (info
->rep_prefix
!= REPE_PREFIX
)
6096 case SVM_EXIT_IOIO
: {
6100 if (info
->intercept
== x86_intercept_in
||
6101 info
->intercept
== x86_intercept_ins
) {
6102 exit_info
= ((info
->src_val
& 0xffff) << 16) |
6104 bytes
= info
->dst_bytes
;
6106 exit_info
= (info
->dst_val
& 0xffff) << 16;
6107 bytes
= info
->src_bytes
;
6110 if (info
->intercept
== x86_intercept_outs
||
6111 info
->intercept
== x86_intercept_ins
)
6112 exit_info
|= SVM_IOIO_STR_MASK
;
6114 if (info
->rep_prefix
)
6115 exit_info
|= SVM_IOIO_REP_MASK
;
6117 bytes
= min(bytes
, 4u);
6119 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
6121 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
6123 vmcb
->control
.exit_info_1
= exit_info
;
6124 vmcb
->control
.exit_info_2
= info
->next_rip
;
6132 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6133 if (static_cpu_has(X86_FEATURE_NRIPS
))
6134 vmcb
->control
.next_rip
= info
->next_rip
;
6135 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
6136 vmexit
= nested_svm_exit_handled(svm
);
6138 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
6145 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
6149 * We must have an instruction with interrupts enabled, so
6150 * the timer interrupt isn't delayed by the interrupt shadow.
6153 local_irq_disable();
6156 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
6158 if (pause_filter_thresh
)
6159 shrink_ple_window(vcpu
);
6162 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
6164 if (avic_handle_apic_id_update(vcpu
) != 0)
6166 if (avic_handle_dfr_update(vcpu
) != 0)
6168 avic_handle_ldr_update(vcpu
);
6171 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
6173 /* [63:9] are reserved. */
6174 vcpu
->arch
.mcg_cap
&= 0x1ff;
6177 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
6179 struct vcpu_svm
*svm
= to_svm(vcpu
);
6181 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6185 if (is_guest_mode(&svm
->vcpu
) &&
6186 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
6187 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6188 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
6189 svm
->nested
.exit_required
= true;
6196 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
6198 struct vcpu_svm
*svm
= to_svm(vcpu
);
6201 if (is_guest_mode(vcpu
)) {
6202 /* FED8h - SVM Guest */
6203 put_smstate(u64
, smstate
, 0x7ed8, 1);
6204 /* FEE0h - SVM Guest VMCB Physical Address */
6205 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
6207 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
6208 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
6209 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
6211 ret
= nested_svm_vmexit(svm
);
6218 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
6220 struct vcpu_svm
*svm
= to_svm(vcpu
);
6221 struct vmcb
*nested_vmcb
;
6229 ret
= kvm_vcpu_read_guest(vcpu
, smbase
+ 0xfed8, &svm_state_save
,
6230 sizeof(svm_state_save
));
6234 if (svm_state_save
.guest
) {
6235 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
6236 nested_vmcb
= nested_svm_map(svm
, svm_state_save
.vmcb
, &page
);
6238 enter_svm_guest_mode(svm
, svm_state_save
.vmcb
, nested_vmcb
, page
);
6241 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
6246 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
6248 struct vcpu_svm
*svm
= to_svm(vcpu
);
6250 if (!gif_set(svm
)) {
6251 if (vgif_enabled(svm
))
6252 set_intercept(svm
, INTERCEPT_STGI
);
6253 /* STGI will cause a vm exit */
6259 static int sev_asid_new(void)
6264 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6266 pos
= find_next_zero_bit(sev_asid_bitmap
, max_sev_asid
, min_sev_asid
- 1);
6267 if (pos
>= max_sev_asid
)
6270 set_bit(pos
, sev_asid_bitmap
);
6274 static int sev_guest_init(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6276 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6280 if (unlikely(sev
->active
))
6283 asid
= sev_asid_new();
6287 ret
= sev_platform_init(&argp
->error
);
6293 INIT_LIST_HEAD(&sev
->regions_list
);
6298 __sev_asid_free(asid
);
6302 static int sev_bind_asid(struct kvm
*kvm
, unsigned int handle
, int *error
)
6304 struct sev_data_activate
*data
;
6305 int asid
= sev_get_asid(kvm
);
6308 wbinvd_on_all_cpus();
6310 ret
= sev_guest_df_flush(error
);
6314 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6318 /* activate ASID on the given handle */
6319 data
->handle
= handle
;
6321 ret
= sev_guest_activate(data
, error
);
6327 static int __sev_issue_cmd(int fd
, int id
, void *data
, int *error
)
6336 ret
= sev_issue_cmd_external_user(f
.file
, id
, data
, error
);
6342 static int sev_issue_cmd(struct kvm
*kvm
, int id
, void *data
, int *error
)
6344 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6346 return __sev_issue_cmd(sev
->fd
, id
, data
, error
);
6349 static int sev_launch_start(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6351 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6352 struct sev_data_launch_start
*start
;
6353 struct kvm_sev_launch_start params
;
6354 void *dh_blob
, *session_blob
;
6355 int *error
= &argp
->error
;
6358 if (!sev_guest(kvm
))
6361 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6364 start
= kzalloc(sizeof(*start
), GFP_KERNEL
);
6369 if (params
.dh_uaddr
) {
6370 dh_blob
= psp_copy_user_blob(params
.dh_uaddr
, params
.dh_len
);
6371 if (IS_ERR(dh_blob
)) {
6372 ret
= PTR_ERR(dh_blob
);
6376 start
->dh_cert_address
= __sme_set(__pa(dh_blob
));
6377 start
->dh_cert_len
= params
.dh_len
;
6380 session_blob
= NULL
;
6381 if (params
.session_uaddr
) {
6382 session_blob
= psp_copy_user_blob(params
.session_uaddr
, params
.session_len
);
6383 if (IS_ERR(session_blob
)) {
6384 ret
= PTR_ERR(session_blob
);
6388 start
->session_address
= __sme_set(__pa(session_blob
));
6389 start
->session_len
= params
.session_len
;
6392 start
->handle
= params
.handle
;
6393 start
->policy
= params
.policy
;
6395 /* create memory encryption context */
6396 ret
= __sev_issue_cmd(argp
->sev_fd
, SEV_CMD_LAUNCH_START
, start
, error
);
6398 goto e_free_session
;
6400 /* Bind ASID to this guest */
6401 ret
= sev_bind_asid(kvm
, start
->handle
, error
);
6403 goto e_free_session
;
6405 /* return handle to userspace */
6406 params
.handle
= start
->handle
;
6407 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
))) {
6408 sev_unbind_asid(kvm
, start
->handle
);
6410 goto e_free_session
;
6413 sev
->handle
= start
->handle
;
6414 sev
->fd
= argp
->sev_fd
;
6417 kfree(session_blob
);
6425 static int get_num_contig_pages(int idx
, struct page
**inpages
,
6426 unsigned long npages
)
6428 unsigned long paddr
, next_paddr
;
6429 int i
= idx
+ 1, pages
= 1;
6431 /* find the number of contiguous pages starting from idx */
6432 paddr
= __sme_page_pa(inpages
[idx
]);
6433 while (i
< npages
) {
6434 next_paddr
= __sme_page_pa(inpages
[i
++]);
6435 if ((paddr
+ PAGE_SIZE
) == next_paddr
) {
6446 static int sev_launch_update_data(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6448 unsigned long vaddr
, vaddr_end
, next_vaddr
, npages
, size
;
6449 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6450 struct kvm_sev_launch_update_data params
;
6451 struct sev_data_launch_update_data
*data
;
6452 struct page
**inpages
;
6455 if (!sev_guest(kvm
))
6458 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6461 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6465 vaddr
= params
.uaddr
;
6467 vaddr_end
= vaddr
+ size
;
6469 /* Lock the user memory. */
6470 inpages
= sev_pin_memory(kvm
, vaddr
, size
, &npages
, 1);
6477 * The LAUNCH_UPDATE command will perform in-place encryption of the
6478 * memory content (i.e it will write the same memory region with C=1).
6479 * It's possible that the cache may contain the data with C=0, i.e.,
6480 * unencrypted so invalidate it first.
6482 sev_clflush_pages(inpages
, npages
);
6484 for (i
= 0; vaddr
< vaddr_end
; vaddr
= next_vaddr
, i
+= pages
) {
6488 * If the user buffer is not page-aligned, calculate the offset
6491 offset
= vaddr
& (PAGE_SIZE
- 1);
6493 /* Calculate the number of pages that can be encrypted in one go. */
6494 pages
= get_num_contig_pages(i
, inpages
, npages
);
6496 len
= min_t(size_t, ((pages
* PAGE_SIZE
) - offset
), size
);
6498 data
->handle
= sev
->handle
;
6500 data
->address
= __sme_page_pa(inpages
[i
]) + offset
;
6501 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_DATA
, data
, &argp
->error
);
6506 next_vaddr
= vaddr
+ len
;
6510 /* content of memory is updated, mark pages dirty */
6511 for (i
= 0; i
< npages
; i
++) {
6512 set_page_dirty_lock(inpages
[i
]);
6513 mark_page_accessed(inpages
[i
]);
6515 /* unlock the user pages */
6516 sev_unpin_memory(kvm
, inpages
, npages
);
6522 static int sev_launch_measure(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6524 void __user
*measure
= (void __user
*)(uintptr_t)argp
->data
;
6525 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6526 struct sev_data_launch_measure
*data
;
6527 struct kvm_sev_launch_measure params
;
6528 void __user
*p
= NULL
;
6532 if (!sev_guest(kvm
))
6535 if (copy_from_user(¶ms
, measure
, sizeof(params
)))
6538 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6542 /* User wants to query the blob length */
6546 p
= (void __user
*)(uintptr_t)params
.uaddr
;
6548 if (params
.len
> SEV_FW_BLOB_MAX_SIZE
) {
6554 blob
= kmalloc(params
.len
, GFP_KERNEL
);
6558 data
->address
= __psp_pa(blob
);
6559 data
->len
= params
.len
;
6563 data
->handle
= sev
->handle
;
6564 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_MEASURE
, data
, &argp
->error
);
6567 * If we query the session length, FW responded with expected data.
6576 if (copy_to_user(p
, blob
, params
.len
))
6581 params
.len
= data
->len
;
6582 if (copy_to_user(measure
, ¶ms
, sizeof(params
)))
6591 static int sev_launch_finish(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6593 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6594 struct sev_data_launch_finish
*data
;
6597 if (!sev_guest(kvm
))
6600 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6604 data
->handle
= sev
->handle
;
6605 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_FINISH
, data
, &argp
->error
);
6611 static int sev_guest_status(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6613 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6614 struct kvm_sev_guest_status params
;
6615 struct sev_data_guest_status
*data
;
6618 if (!sev_guest(kvm
))
6621 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6625 data
->handle
= sev
->handle
;
6626 ret
= sev_issue_cmd(kvm
, SEV_CMD_GUEST_STATUS
, data
, &argp
->error
);
6630 params
.policy
= data
->policy
;
6631 params
.state
= data
->state
;
6632 params
.handle
= data
->handle
;
6634 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
)))
6641 static int __sev_issue_dbg_cmd(struct kvm
*kvm
, unsigned long src
,
6642 unsigned long dst
, int size
,
6643 int *error
, bool enc
)
6645 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6646 struct sev_data_dbg
*data
;
6649 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6653 data
->handle
= sev
->handle
;
6654 data
->dst_addr
= dst
;
6655 data
->src_addr
= src
;
6658 ret
= sev_issue_cmd(kvm
,
6659 enc
? SEV_CMD_DBG_ENCRYPT
: SEV_CMD_DBG_DECRYPT
,
6665 static int __sev_dbg_decrypt(struct kvm
*kvm
, unsigned long src_paddr
,
6666 unsigned long dst_paddr
, int sz
, int *err
)
6671 * Its safe to read more than we are asked, caller should ensure that
6672 * destination has enough space.
6674 src_paddr
= round_down(src_paddr
, 16);
6675 offset
= src_paddr
& 15;
6676 sz
= round_up(sz
+ offset
, 16);
6678 return __sev_issue_dbg_cmd(kvm
, src_paddr
, dst_paddr
, sz
, err
, false);
6681 static int __sev_dbg_decrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6682 unsigned long __user dst_uaddr
,
6683 unsigned long dst_paddr
,
6686 struct page
*tpage
= NULL
;
6689 /* if inputs are not 16-byte then use intermediate buffer */
6690 if (!IS_ALIGNED(dst_paddr
, 16) ||
6691 !IS_ALIGNED(paddr
, 16) ||
6692 !IS_ALIGNED(size
, 16)) {
6693 tpage
= (void *)alloc_page(GFP_KERNEL
);
6697 dst_paddr
= __sme_page_pa(tpage
);
6700 ret
= __sev_dbg_decrypt(kvm
, paddr
, dst_paddr
, size
, err
);
6705 offset
= paddr
& 15;
6706 if (copy_to_user((void __user
*)(uintptr_t)dst_uaddr
,
6707 page_address(tpage
) + offset
, size
))
6718 static int __sev_dbg_encrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6719 unsigned long __user vaddr
,
6720 unsigned long dst_paddr
,
6721 unsigned long __user dst_vaddr
,
6722 int size
, int *error
)
6724 struct page
*src_tpage
= NULL
;
6725 struct page
*dst_tpage
= NULL
;
6726 int ret
, len
= size
;
6728 /* If source buffer is not aligned then use an intermediate buffer */
6729 if (!IS_ALIGNED(vaddr
, 16)) {
6730 src_tpage
= alloc_page(GFP_KERNEL
);
6734 if (copy_from_user(page_address(src_tpage
),
6735 (void __user
*)(uintptr_t)vaddr
, size
)) {
6736 __free_page(src_tpage
);
6740 paddr
= __sme_page_pa(src_tpage
);
6744 * If destination buffer or length is not aligned then do read-modify-write:
6745 * - decrypt destination in an intermediate buffer
6746 * - copy the source buffer in an intermediate buffer
6747 * - use the intermediate buffer as source buffer
6749 if (!IS_ALIGNED(dst_vaddr
, 16) || !IS_ALIGNED(size
, 16)) {
6752 dst_tpage
= alloc_page(GFP_KERNEL
);
6758 ret
= __sev_dbg_decrypt(kvm
, dst_paddr
,
6759 __sme_page_pa(dst_tpage
), size
, error
);
6764 * If source is kernel buffer then use memcpy() otherwise
6767 dst_offset
= dst_paddr
& 15;
6770 memcpy(page_address(dst_tpage
) + dst_offset
,
6771 page_address(src_tpage
), size
);
6773 if (copy_from_user(page_address(dst_tpage
) + dst_offset
,
6774 (void __user
*)(uintptr_t)vaddr
, size
)) {
6780 paddr
= __sme_page_pa(dst_tpage
);
6781 dst_paddr
= round_down(dst_paddr
, 16);
6782 len
= round_up(size
, 16);
6785 ret
= __sev_issue_dbg_cmd(kvm
, paddr
, dst_paddr
, len
, error
, true);
6789 __free_page(src_tpage
);
6791 __free_page(dst_tpage
);
6795 static int sev_dbg_crypt(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
, bool dec
)
6797 unsigned long vaddr
, vaddr_end
, next_vaddr
;
6798 unsigned long dst_vaddr
;
6799 struct page
**src_p
, **dst_p
;
6800 struct kvm_sev_dbg debug
;
6804 if (!sev_guest(kvm
))
6807 if (copy_from_user(&debug
, (void __user
*)(uintptr_t)argp
->data
, sizeof(debug
)))
6810 vaddr
= debug
.src_uaddr
;
6812 vaddr_end
= vaddr
+ size
;
6813 dst_vaddr
= debug
.dst_uaddr
;
6815 for (; vaddr
< vaddr_end
; vaddr
= next_vaddr
) {
6816 int len
, s_off
, d_off
;
6818 /* lock userspace source and destination page */
6819 src_p
= sev_pin_memory(kvm
, vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 0);
6823 dst_p
= sev_pin_memory(kvm
, dst_vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 1);
6825 sev_unpin_memory(kvm
, src_p
, n
);
6830 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6831 * memory content (i.e it will write the same memory region with C=1).
6832 * It's possible that the cache may contain the data with C=0, i.e.,
6833 * unencrypted so invalidate it first.
6835 sev_clflush_pages(src_p
, 1);
6836 sev_clflush_pages(dst_p
, 1);
6839 * Since user buffer may not be page aligned, calculate the
6840 * offset within the page.
6842 s_off
= vaddr
& ~PAGE_MASK
;
6843 d_off
= dst_vaddr
& ~PAGE_MASK
;
6844 len
= min_t(size_t, (PAGE_SIZE
- s_off
), size
);
6847 ret
= __sev_dbg_decrypt_user(kvm
,
6848 __sme_page_pa(src_p
[0]) + s_off
,
6850 __sme_page_pa(dst_p
[0]) + d_off
,
6853 ret
= __sev_dbg_encrypt_user(kvm
,
6854 __sme_page_pa(src_p
[0]) + s_off
,
6856 __sme_page_pa(dst_p
[0]) + d_off
,
6860 sev_unpin_memory(kvm
, src_p
, 1);
6861 sev_unpin_memory(kvm
, dst_p
, 1);
6866 next_vaddr
= vaddr
+ len
;
6867 dst_vaddr
= dst_vaddr
+ len
;
6874 static int sev_launch_secret(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6876 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6877 struct sev_data_launch_secret
*data
;
6878 struct kvm_sev_launch_secret params
;
6879 struct page
**pages
;
6884 if (!sev_guest(kvm
))
6887 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6890 pages
= sev_pin_memory(kvm
, params
.guest_uaddr
, params
.guest_len
, &n
, 1);
6895 * The secret must be copied into contiguous memory region, lets verify
6896 * that userspace memory pages are contiguous before we issue command.
6898 if (get_num_contig_pages(0, pages
, n
) != n
) {
6900 goto e_unpin_memory
;
6904 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6906 goto e_unpin_memory
;
6908 offset
= params
.guest_uaddr
& (PAGE_SIZE
- 1);
6909 data
->guest_address
= __sme_page_pa(pages
[0]) + offset
;
6910 data
->guest_len
= params
.guest_len
;
6912 blob
= psp_copy_user_blob(params
.trans_uaddr
, params
.trans_len
);
6914 ret
= PTR_ERR(blob
);
6918 data
->trans_address
= __psp_pa(blob
);
6919 data
->trans_len
= params
.trans_len
;
6921 hdr
= psp_copy_user_blob(params
.hdr_uaddr
, params
.hdr_len
);
6926 data
->hdr_address
= __psp_pa(hdr
);
6927 data
->hdr_len
= params
.hdr_len
;
6929 data
->handle
= sev
->handle
;
6930 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_SECRET
, data
, &argp
->error
);
6939 sev_unpin_memory(kvm
, pages
, n
);
6943 static int svm_mem_enc_op(struct kvm
*kvm
, void __user
*argp
)
6945 struct kvm_sev_cmd sev_cmd
;
6948 if (!svm_sev_enabled())
6951 if (copy_from_user(&sev_cmd
, argp
, sizeof(struct kvm_sev_cmd
)))
6954 mutex_lock(&kvm
->lock
);
6956 switch (sev_cmd
.id
) {
6958 r
= sev_guest_init(kvm
, &sev_cmd
);
6960 case KVM_SEV_LAUNCH_START
:
6961 r
= sev_launch_start(kvm
, &sev_cmd
);
6963 case KVM_SEV_LAUNCH_UPDATE_DATA
:
6964 r
= sev_launch_update_data(kvm
, &sev_cmd
);
6966 case KVM_SEV_LAUNCH_MEASURE
:
6967 r
= sev_launch_measure(kvm
, &sev_cmd
);
6969 case KVM_SEV_LAUNCH_FINISH
:
6970 r
= sev_launch_finish(kvm
, &sev_cmd
);
6972 case KVM_SEV_GUEST_STATUS
:
6973 r
= sev_guest_status(kvm
, &sev_cmd
);
6975 case KVM_SEV_DBG_DECRYPT
:
6976 r
= sev_dbg_crypt(kvm
, &sev_cmd
, true);
6978 case KVM_SEV_DBG_ENCRYPT
:
6979 r
= sev_dbg_crypt(kvm
, &sev_cmd
, false);
6981 case KVM_SEV_LAUNCH_SECRET
:
6982 r
= sev_launch_secret(kvm
, &sev_cmd
);
6989 if (copy_to_user(argp
, &sev_cmd
, sizeof(struct kvm_sev_cmd
)))
6993 mutex_unlock(&kvm
->lock
);
6997 static int svm_register_enc_region(struct kvm
*kvm
,
6998 struct kvm_enc_region
*range
)
7000 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
7001 struct enc_region
*region
;
7004 if (!sev_guest(kvm
))
7007 if (range
->addr
> ULONG_MAX
|| range
->size
> ULONG_MAX
)
7010 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
7014 region
->pages
= sev_pin_memory(kvm
, range
->addr
, range
->size
, ®ion
->npages
, 1);
7015 if (!region
->pages
) {
7021 * The guest may change the memory encryption attribute from C=0 -> C=1
7022 * or vice versa for this memory range. Lets make sure caches are
7023 * flushed to ensure that guest data gets written into memory with
7026 sev_clflush_pages(region
->pages
, region
->npages
);
7028 region
->uaddr
= range
->addr
;
7029 region
->size
= range
->size
;
7031 mutex_lock(&kvm
->lock
);
7032 list_add_tail(®ion
->list
, &sev
->regions_list
);
7033 mutex_unlock(&kvm
->lock
);
7042 static struct enc_region
*
7043 find_enc_region(struct kvm
*kvm
, struct kvm_enc_region
*range
)
7045 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
7046 struct list_head
*head
= &sev
->regions_list
;
7047 struct enc_region
*i
;
7049 list_for_each_entry(i
, head
, list
) {
7050 if (i
->uaddr
== range
->addr
&&
7051 i
->size
== range
->size
)
7059 static int svm_unregister_enc_region(struct kvm
*kvm
,
7060 struct kvm_enc_region
*range
)
7062 struct enc_region
*region
;
7065 mutex_lock(&kvm
->lock
);
7067 if (!sev_guest(kvm
)) {
7072 region
= find_enc_region(kvm
, range
);
7078 __unregister_enc_region_locked(kvm
, region
);
7080 mutex_unlock(&kvm
->lock
);
7084 mutex_unlock(&kvm
->lock
);
7088 static uint16_t nested_get_evmcs_version(struct kvm_vcpu
*vcpu
)
7094 static int nested_enable_evmcs(struct kvm_vcpu
*vcpu
,
7095 uint16_t *vmcs_version
)
7097 /* Intel-only feature */
7101 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
7102 .cpu_has_kvm_support
= has_svm
,
7103 .disabled_by_bios
= is_disabled
,
7104 .hardware_setup
= svm_hardware_setup
,
7105 .hardware_unsetup
= svm_hardware_unsetup
,
7106 .check_processor_compatibility
= svm_check_processor_compat
,
7107 .hardware_enable
= svm_hardware_enable
,
7108 .hardware_disable
= svm_hardware_disable
,
7109 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
7110 .has_emulated_msr
= svm_has_emulated_msr
,
7112 .vcpu_create
= svm_create_vcpu
,
7113 .vcpu_free
= svm_free_vcpu
,
7114 .vcpu_reset
= svm_vcpu_reset
,
7116 .vm_alloc
= svm_vm_alloc
,
7117 .vm_free
= svm_vm_free
,
7118 .vm_init
= avic_vm_init
,
7119 .vm_destroy
= svm_vm_destroy
,
7121 .prepare_guest_switch
= svm_prepare_guest_switch
,
7122 .vcpu_load
= svm_vcpu_load
,
7123 .vcpu_put
= svm_vcpu_put
,
7124 .vcpu_blocking
= svm_vcpu_blocking
,
7125 .vcpu_unblocking
= svm_vcpu_unblocking
,
7127 .update_bp_intercept
= update_bp_intercept
,
7128 .get_msr_feature
= svm_get_msr_feature
,
7129 .get_msr
= svm_get_msr
,
7130 .set_msr
= svm_set_msr
,
7131 .get_segment_base
= svm_get_segment_base
,
7132 .get_segment
= svm_get_segment
,
7133 .set_segment
= svm_set_segment
,
7134 .get_cpl
= svm_get_cpl
,
7135 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
7136 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
7137 .decache_cr3
= svm_decache_cr3
,
7138 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
7139 .set_cr0
= svm_set_cr0
,
7140 .set_cr3
= svm_set_cr3
,
7141 .set_cr4
= svm_set_cr4
,
7142 .set_efer
= svm_set_efer
,
7143 .get_idt
= svm_get_idt
,
7144 .set_idt
= svm_set_idt
,
7145 .get_gdt
= svm_get_gdt
,
7146 .set_gdt
= svm_set_gdt
,
7147 .get_dr6
= svm_get_dr6
,
7148 .set_dr6
= svm_set_dr6
,
7149 .set_dr7
= svm_set_dr7
,
7150 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
7151 .cache_reg
= svm_cache_reg
,
7152 .get_rflags
= svm_get_rflags
,
7153 .set_rflags
= svm_set_rflags
,
7155 .tlb_flush
= svm_flush_tlb
,
7156 .tlb_flush_gva
= svm_flush_tlb_gva
,
7158 .run
= svm_vcpu_run
,
7159 .handle_exit
= handle_exit
,
7160 .skip_emulated_instruction
= skip_emulated_instruction
,
7161 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
7162 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
7163 .patch_hypercall
= svm_patch_hypercall
,
7164 .set_irq
= svm_set_irq
,
7165 .set_nmi
= svm_inject_nmi
,
7166 .queue_exception
= svm_queue_exception
,
7167 .cancel_injection
= svm_cancel_injection
,
7168 .interrupt_allowed
= svm_interrupt_allowed
,
7169 .nmi_allowed
= svm_nmi_allowed
,
7170 .get_nmi_mask
= svm_get_nmi_mask
,
7171 .set_nmi_mask
= svm_set_nmi_mask
,
7172 .enable_nmi_window
= enable_nmi_window
,
7173 .enable_irq_window
= enable_irq_window
,
7174 .update_cr8_intercept
= update_cr8_intercept
,
7175 .set_virtual_apic_mode
= svm_set_virtual_apic_mode
,
7176 .get_enable_apicv
= svm_get_enable_apicv
,
7177 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
7178 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
7179 .hwapic_irr_update
= svm_hwapic_irr_update
,
7180 .hwapic_isr_update
= svm_hwapic_isr_update
,
7181 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
7182 .apicv_post_state_restore
= avic_post_state_restore
,
7184 .set_tss_addr
= svm_set_tss_addr
,
7185 .set_identity_map_addr
= svm_set_identity_map_addr
,
7186 .get_tdp_level
= get_npt_level
,
7187 .get_mt_mask
= svm_get_mt_mask
,
7189 .get_exit_info
= svm_get_exit_info
,
7191 .get_lpage_level
= svm_get_lpage_level
,
7193 .cpuid_update
= svm_cpuid_update
,
7195 .rdtscp_supported
= svm_rdtscp_supported
,
7196 .invpcid_supported
= svm_invpcid_supported
,
7197 .mpx_supported
= svm_mpx_supported
,
7198 .xsaves_supported
= svm_xsaves_supported
,
7199 .umip_emulated
= svm_umip_emulated
,
7200 .pt_supported
= svm_pt_supported
,
7202 .set_supported_cpuid
= svm_set_supported_cpuid
,
7204 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
7206 .read_l1_tsc_offset
= svm_read_l1_tsc_offset
,
7207 .write_l1_tsc_offset
= svm_write_l1_tsc_offset
,
7209 .set_tdp_cr3
= set_tdp_cr3
,
7211 .check_intercept
= svm_check_intercept
,
7212 .handle_external_intr
= svm_handle_external_intr
,
7214 .request_immediate_exit
= __kvm_request_immediate_exit
,
7216 .sched_in
= svm_sched_in
,
7218 .pmu_ops
= &amd_pmu_ops
,
7219 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
7220 .update_pi_irte
= svm_update_pi_irte
,
7221 .setup_mce
= svm_setup_mce
,
7223 .smi_allowed
= svm_smi_allowed
,
7224 .pre_enter_smm
= svm_pre_enter_smm
,
7225 .pre_leave_smm
= svm_pre_leave_smm
,
7226 .enable_smi_window
= enable_smi_window
,
7228 .mem_enc_op
= svm_mem_enc_op
,
7229 .mem_enc_reg_region
= svm_register_enc_region
,
7230 .mem_enc_unreg_region
= svm_unregister_enc_region
,
7232 .nested_enable_evmcs
= nested_enable_evmcs
,
7233 .nested_get_evmcs_version
= nested_get_evmcs_version
,
7236 static int __init
svm_init(void)
7238 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
7239 __alignof__(struct vcpu_svm
), THIS_MODULE
);
7242 static void __exit
svm_exit(void)
7247 module_init(svm_init
)
7248 module_exit(svm_exit
)