2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
41 #include <asm/virtext.h>
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
49 static const struct x86_cpu_id svm_cpu_id
[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
53 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
81 static bool erratum_383_found __read_mostly
;
83 static const u32 host_save_user_msrs
[] = {
85 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
88 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
91 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
101 /* These are the merged vectors */
104 /* gpa pointers to the real vectors */
108 /* A VMEXIT is required but not yet emulated */
111 /* cache for intercepts of the guest */
114 u32 intercept_exceptions
;
117 /* Nested Paging related state */
121 #define MSRPM_OFFSETS 16
122 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
125 * Set osvw_len to higher value when updated Revision Guides
126 * are published and we know what the new status bits are
128 static uint64_t osvw_len
= 4, osvw_status
;
131 struct kvm_vcpu vcpu
;
133 unsigned long vmcb_pa
;
134 struct svm_cpu_data
*svm_data
;
135 uint64_t asid_generation
;
136 uint64_t sysenter_esp
;
137 uint64_t sysenter_eip
;
141 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
153 struct nested_state nested
;
157 unsigned int3_injected
;
158 unsigned long int3_rip
;
163 /* cached guest cpuid flags for faster access */
164 bool nrips_enabled
: 1;
167 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
168 #define TSC_RATIO_DEFAULT 0x0100000000ULL
170 #define MSR_INVALID 0xffffffffU
172 static const struct svm_direct_access_msrs
{
173 u32 index
; /* Index of the MSR */
174 bool always
; /* True if intercept is always on */
175 } direct_access_msrs
[] = {
176 { .index
= MSR_STAR
, .always
= true },
177 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
179 { .index
= MSR_GS_BASE
, .always
= true },
180 { .index
= MSR_FS_BASE
, .always
= true },
181 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
182 { .index
= MSR_LSTAR
, .always
= true },
183 { .index
= MSR_CSTAR
, .always
= true },
184 { .index
= MSR_SYSCALL_MASK
, .always
= true },
186 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
187 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
188 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
189 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
190 { .index
= MSR_INVALID
, .always
= false },
193 /* enable NPT for AMD64 and X86 with PAE */
194 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
195 static bool npt_enabled
= true;
197 static bool npt_enabled
;
200 /* allow nested paging (virtualized MMU) for all guests */
201 static int npt
= true;
202 module_param(npt
, int, S_IRUGO
);
204 /* allow nested virtualization in KVM/SVM */
205 static int nested
= true;
206 module_param(nested
, int, S_IRUGO
);
208 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
209 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
210 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
212 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
213 static int nested_svm_intercept(struct vcpu_svm
*svm
);
214 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
215 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
216 bool has_error_code
, u32 error_code
);
217 static u64
__scale_tsc(u64 ratio
, u64 tsc
);
220 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
221 pause filter count */
222 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
223 VMCB_ASID
, /* ASID */
224 VMCB_INTR
, /* int_ctl, int_vector */
225 VMCB_NPT
, /* npt_en, nCR3, gPAT */
226 VMCB_CR
, /* CR0, CR3, CR4, EFER */
227 VMCB_DR
, /* DR6, DR7 */
228 VMCB_DT
, /* GDT, IDT */
229 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
230 VMCB_CR2
, /* CR2 only */
231 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
235 /* TPR and CR2 are always written before VMRUN */
236 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
238 static inline void mark_all_dirty(struct vmcb
*vmcb
)
240 vmcb
->control
.clean
= 0;
243 static inline void mark_all_clean(struct vmcb
*vmcb
)
245 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
246 & ~VMCB_ALWAYS_DIRTY_MASK
;
249 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
251 vmcb
->control
.clean
&= ~(1 << bit
);
254 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
256 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
259 static void recalc_intercepts(struct vcpu_svm
*svm
)
261 struct vmcb_control_area
*c
, *h
;
262 struct nested_state
*g
;
264 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
266 if (!is_guest_mode(&svm
->vcpu
))
269 c
= &svm
->vmcb
->control
;
270 h
= &svm
->nested
.hsave
->control
;
273 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
274 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
275 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
276 c
->intercept
= h
->intercept
| g
->intercept
;
279 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
281 if (is_guest_mode(&svm
->vcpu
))
282 return svm
->nested
.hsave
;
287 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
289 struct vmcb
*vmcb
= get_host_vmcb(svm
);
291 vmcb
->control
.intercept_cr
|= (1U << bit
);
293 recalc_intercepts(svm
);
296 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
298 struct vmcb
*vmcb
= get_host_vmcb(svm
);
300 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
302 recalc_intercepts(svm
);
305 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
307 struct vmcb
*vmcb
= get_host_vmcb(svm
);
309 return vmcb
->control
.intercept_cr
& (1U << bit
);
312 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
314 struct vmcb
*vmcb
= get_host_vmcb(svm
);
316 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
317 | (1 << INTERCEPT_DR1_READ
)
318 | (1 << INTERCEPT_DR2_READ
)
319 | (1 << INTERCEPT_DR3_READ
)
320 | (1 << INTERCEPT_DR4_READ
)
321 | (1 << INTERCEPT_DR5_READ
)
322 | (1 << INTERCEPT_DR6_READ
)
323 | (1 << INTERCEPT_DR7_READ
)
324 | (1 << INTERCEPT_DR0_WRITE
)
325 | (1 << INTERCEPT_DR1_WRITE
)
326 | (1 << INTERCEPT_DR2_WRITE
)
327 | (1 << INTERCEPT_DR3_WRITE
)
328 | (1 << INTERCEPT_DR4_WRITE
)
329 | (1 << INTERCEPT_DR5_WRITE
)
330 | (1 << INTERCEPT_DR6_WRITE
)
331 | (1 << INTERCEPT_DR7_WRITE
);
333 recalc_intercepts(svm
);
336 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
338 struct vmcb
*vmcb
= get_host_vmcb(svm
);
340 vmcb
->control
.intercept_dr
= 0;
342 recalc_intercepts(svm
);
345 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
347 struct vmcb
*vmcb
= get_host_vmcb(svm
);
349 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
351 recalc_intercepts(svm
);
354 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
356 struct vmcb
*vmcb
= get_host_vmcb(svm
);
358 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
360 recalc_intercepts(svm
);
363 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
365 struct vmcb
*vmcb
= get_host_vmcb(svm
);
367 vmcb
->control
.intercept
|= (1ULL << bit
);
369 recalc_intercepts(svm
);
372 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
374 struct vmcb
*vmcb
= get_host_vmcb(svm
);
376 vmcb
->control
.intercept
&= ~(1ULL << bit
);
378 recalc_intercepts(svm
);
381 static inline void enable_gif(struct vcpu_svm
*svm
)
383 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
386 static inline void disable_gif(struct vcpu_svm
*svm
)
388 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
391 static inline bool gif_set(struct vcpu_svm
*svm
)
393 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
396 static unsigned long iopm_base
;
398 struct kvm_ldttss_desc
{
401 unsigned base1
:8, type
:5, dpl
:2, p
:1;
402 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
405 } __attribute__((packed
));
407 struct svm_cpu_data
{
413 struct kvm_ldttss_desc
*tss_desc
;
415 struct page
*save_area
;
418 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
420 struct svm_init_data
{
425 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
427 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
428 #define MSRS_RANGE_SIZE 2048
429 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
431 static u32
svm_msrpm_offset(u32 msr
)
436 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
437 if (msr
< msrpm_ranges
[i
] ||
438 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
441 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
442 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
444 /* Now we have the u8 offset - but need the u32 offset */
448 /* MSR not in any range */
452 #define MAX_INST_SIZE 15
454 static inline void clgi(void)
456 asm volatile (__ex(SVM_CLGI
));
459 static inline void stgi(void)
461 asm volatile (__ex(SVM_STGI
));
464 static inline void invlpga(unsigned long addr
, u32 asid
)
466 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
469 static int get_npt_level(void)
472 return PT64_ROOT_LEVEL
;
474 return PT32E_ROOT_LEVEL
;
478 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
480 vcpu
->arch
.efer
= efer
;
481 if (!npt_enabled
&& !(efer
& EFER_LMA
))
484 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
485 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
488 static int is_external_interrupt(u32 info
)
490 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
491 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
494 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
496 struct vcpu_svm
*svm
= to_svm(vcpu
);
499 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
500 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
504 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
506 struct vcpu_svm
*svm
= to_svm(vcpu
);
509 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
511 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
515 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
517 struct vcpu_svm
*svm
= to_svm(vcpu
);
519 if (svm
->vmcb
->control
.next_rip
!= 0) {
520 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
521 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
524 if (!svm
->next_rip
) {
525 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
527 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
530 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
531 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
532 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
534 kvm_rip_write(vcpu
, svm
->next_rip
);
535 svm_set_interrupt_shadow(vcpu
, 0);
538 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
539 bool has_error_code
, u32 error_code
,
542 struct vcpu_svm
*svm
= to_svm(vcpu
);
545 * If we are within a nested VM we'd better #VMEXIT and let the guest
546 * handle the exception
549 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
552 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
553 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
556 * For guest debugging where we have to reinject #BP if some
557 * INT3 is guest-owned:
558 * Emulate nRIP by moving RIP forward. Will fail if injection
559 * raises a fault that is not intercepted. Still better than
560 * failing in all cases.
562 skip_emulated_instruction(&svm
->vcpu
);
563 rip
= kvm_rip_read(&svm
->vcpu
);
564 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
565 svm
->int3_injected
= rip
- old_rip
;
568 svm
->vmcb
->control
.event_inj
= nr
570 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
571 | SVM_EVTINJ_TYPE_EXEPT
;
572 svm
->vmcb
->control
.event_inj_err
= error_code
;
575 static void svm_init_erratum_383(void)
581 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
584 /* Use _safe variants to not break nested virtualization */
585 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
591 low
= lower_32_bits(val
);
592 high
= upper_32_bits(val
);
594 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
596 erratum_383_found
= true;
599 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
602 * Guests should see errata 400 and 415 as fixed (assuming that
603 * HLT and IO instructions are intercepted).
605 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
606 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
609 * By increasing VCPU's osvw.length to 3 we are telling the guest that
610 * all osvw.status bits inside that length, including bit 0 (which is
611 * reserved for erratum 298), are valid. However, if host processor's
612 * osvw_len is 0 then osvw_status[0] carries no information. We need to
613 * be conservative here and therefore we tell the guest that erratum 298
614 * is present (because we really don't know).
616 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
617 vcpu
->arch
.osvw
.status
|= 1;
620 static int has_svm(void)
624 if (!cpu_has_svm(&msg
)) {
625 printk(KERN_INFO
"has_svm: %s\n", msg
);
632 static void svm_hardware_disable(void)
634 /* Make sure we clean up behind us */
635 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
636 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
640 amd_pmu_disable_virt();
643 static int svm_hardware_enable(void)
646 struct svm_cpu_data
*sd
;
648 struct desc_ptr gdt_descr
;
649 struct desc_struct
*gdt
;
650 int me
= raw_smp_processor_id();
652 rdmsrl(MSR_EFER
, efer
);
653 if (efer
& EFER_SVME
)
657 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
660 sd
= per_cpu(svm_data
, me
);
662 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
666 sd
->asid_generation
= 1;
667 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
668 sd
->next_asid
= sd
->max_asid
+ 1;
670 native_store_gdt(&gdt_descr
);
671 gdt
= (struct desc_struct
*)gdt_descr
.address
;
672 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
674 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
676 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
678 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
679 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
680 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
687 * Note that it is possible to have a system with mixed processor
688 * revisions and therefore different OSVW bits. If bits are not the same
689 * on different processors then choose the worst case (i.e. if erratum
690 * is present on one processor and not on another then assume that the
691 * erratum is present everywhere).
693 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
694 uint64_t len
, status
= 0;
697 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
699 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
703 osvw_status
= osvw_len
= 0;
707 osvw_status
|= status
;
708 osvw_status
&= (1ULL << osvw_len
) - 1;
711 osvw_status
= osvw_len
= 0;
713 svm_init_erratum_383();
715 amd_pmu_enable_virt();
720 static void svm_cpu_uninit(int cpu
)
722 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
727 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
728 __free_page(sd
->save_area
);
732 static int svm_cpu_init(int cpu
)
734 struct svm_cpu_data
*sd
;
737 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
741 sd
->save_area
= alloc_page(GFP_KERNEL
);
746 per_cpu(svm_data
, cpu
) = sd
;
756 static bool valid_msr_intercept(u32 index
)
760 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
761 if (direct_access_msrs
[i
].index
== index
)
767 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
770 u8 bit_read
, bit_write
;
775 * If this warning triggers extend the direct_access_msrs list at the
776 * beginning of the file
778 WARN_ON(!valid_msr_intercept(msr
));
780 offset
= svm_msrpm_offset(msr
);
781 bit_read
= 2 * (msr
& 0x0f);
782 bit_write
= 2 * (msr
& 0x0f) + 1;
785 BUG_ON(offset
== MSR_INVALID
);
787 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
788 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
793 static void svm_vcpu_init_msrpm(u32
*msrpm
)
797 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
799 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
800 if (!direct_access_msrs
[i
].always
)
803 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
807 static void add_msr_offset(u32 offset
)
811 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
813 /* Offset already in list? */
814 if (msrpm_offsets
[i
] == offset
)
817 /* Slot used by another offset? */
818 if (msrpm_offsets
[i
] != MSR_INVALID
)
821 /* Add offset to list */
822 msrpm_offsets
[i
] = offset
;
828 * If this BUG triggers the msrpm_offsets table has an overflow. Just
829 * increase MSRPM_OFFSETS in this case.
834 static void init_msrpm_offsets(void)
838 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
840 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
843 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
844 BUG_ON(offset
== MSR_INVALID
);
846 add_msr_offset(offset
);
850 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
852 u32
*msrpm
= svm
->msrpm
;
854 svm
->vmcb
->control
.lbr_ctl
= 1;
855 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
856 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
857 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
858 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
861 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
863 u32
*msrpm
= svm
->msrpm
;
865 svm
->vmcb
->control
.lbr_ctl
= 0;
866 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
867 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
868 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
869 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
872 static __init
int svm_hardware_setup(void)
875 struct page
*iopm_pages
;
879 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
884 iopm_va
= page_address(iopm_pages
);
885 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
886 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
888 init_msrpm_offsets();
890 if (boot_cpu_has(X86_FEATURE_NX
))
891 kvm_enable_efer_bits(EFER_NX
);
893 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
894 kvm_enable_efer_bits(EFER_FFXSR
);
896 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
899 kvm_has_tsc_control
= true;
902 * Make sure the user can only configure tsc_khz values that
903 * fit into a signed integer.
904 * A min value is not calculated needed because it will always
905 * be 1 on all machines and a value of 0 is used to disable
906 * tsc-scaling for the vcpu.
908 max
= min(0x7fffffffULL
, __scale_tsc(tsc_khz
, TSC_RATIO_MAX
));
910 kvm_max_guest_tsc_khz
= max
;
914 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
915 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
918 for_each_possible_cpu(cpu
) {
919 r
= svm_cpu_init(cpu
);
924 if (!boot_cpu_has(X86_FEATURE_NPT
))
927 if (npt_enabled
&& !npt
) {
928 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
933 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
941 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
946 static __exit
void svm_hardware_unsetup(void)
950 for_each_possible_cpu(cpu
)
953 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
957 static void init_seg(struct vmcb_seg
*seg
)
960 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
961 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
966 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
969 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
974 static u64
__scale_tsc(u64 ratio
, u64 tsc
)
976 u64 mult
, frac
, _tsc
;
979 frac
= ratio
& ((1ULL << 32) - 1);
983 _tsc
+= (tsc
>> 32) * frac
;
984 _tsc
+= ((tsc
& ((1ULL << 32) - 1)) * frac
) >> 32;
989 static u64
svm_scale_tsc(struct kvm_vcpu
*vcpu
, u64 tsc
)
991 struct vcpu_svm
*svm
= to_svm(vcpu
);
994 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
995 _tsc
= __scale_tsc(svm
->tsc_ratio
, tsc
);
1000 static void svm_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1002 struct vcpu_svm
*svm
= to_svm(vcpu
);
1006 /* Guest TSC same frequency as host TSC? */
1008 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1012 /* TSC scaling supported? */
1013 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1014 if (user_tsc_khz
> tsc_khz
) {
1015 vcpu
->arch
.tsc_catchup
= 1;
1016 vcpu
->arch
.tsc_always_catchup
= 1;
1018 WARN(1, "user requested TSC rate below hardware speed\n");
1024 /* TSC scaling required - calculate ratio */
1026 do_div(ratio
, tsc_khz
);
1028 if (ratio
== 0 || ratio
& TSC_RATIO_RSVD
) {
1029 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1033 svm
->tsc_ratio
= ratio
;
1036 static u64
svm_read_tsc_offset(struct kvm_vcpu
*vcpu
)
1038 struct vcpu_svm
*svm
= to_svm(vcpu
);
1040 return svm
->vmcb
->control
.tsc_offset
;
1043 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1045 struct vcpu_svm
*svm
= to_svm(vcpu
);
1046 u64 g_tsc_offset
= 0;
1048 if (is_guest_mode(vcpu
)) {
1049 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1050 svm
->nested
.hsave
->control
.tsc_offset
;
1051 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1053 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1054 svm
->vmcb
->control
.tsc_offset
,
1057 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1059 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1062 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1064 struct vcpu_svm
*svm
= to_svm(vcpu
);
1067 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
1068 WARN_ON(adjustment
< 0);
1069 adjustment
= svm_scale_tsc(vcpu
, (u64
)adjustment
);
1072 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
1073 if (is_guest_mode(vcpu
))
1074 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
1076 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1077 svm
->vmcb
->control
.tsc_offset
- adjustment
,
1078 svm
->vmcb
->control
.tsc_offset
);
1080 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1083 static u64
svm_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1087 tsc
= svm_scale_tsc(vcpu
, rdtsc());
1089 return target_tsc
- tsc
;
1092 static void init_vmcb(struct vcpu_svm
*svm
)
1094 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1095 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1097 svm
->vcpu
.fpu_active
= 1;
1098 svm
->vcpu
.arch
.hflags
= 0;
1100 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1101 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1102 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1103 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1104 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1105 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1106 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1108 set_dr_intercepts(svm
);
1110 set_exception_intercept(svm
, PF_VECTOR
);
1111 set_exception_intercept(svm
, UD_VECTOR
);
1112 set_exception_intercept(svm
, MC_VECTOR
);
1114 set_intercept(svm
, INTERCEPT_INTR
);
1115 set_intercept(svm
, INTERCEPT_NMI
);
1116 set_intercept(svm
, INTERCEPT_SMI
);
1117 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1118 set_intercept(svm
, INTERCEPT_RDPMC
);
1119 set_intercept(svm
, INTERCEPT_CPUID
);
1120 set_intercept(svm
, INTERCEPT_INVD
);
1121 set_intercept(svm
, INTERCEPT_HLT
);
1122 set_intercept(svm
, INTERCEPT_INVLPG
);
1123 set_intercept(svm
, INTERCEPT_INVLPGA
);
1124 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1125 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1126 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1127 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1128 set_intercept(svm
, INTERCEPT_VMRUN
);
1129 set_intercept(svm
, INTERCEPT_VMMCALL
);
1130 set_intercept(svm
, INTERCEPT_VMLOAD
);
1131 set_intercept(svm
, INTERCEPT_VMSAVE
);
1132 set_intercept(svm
, INTERCEPT_STGI
);
1133 set_intercept(svm
, INTERCEPT_CLGI
);
1134 set_intercept(svm
, INTERCEPT_SKINIT
);
1135 set_intercept(svm
, INTERCEPT_WBINVD
);
1136 set_intercept(svm
, INTERCEPT_MONITOR
);
1137 set_intercept(svm
, INTERCEPT_MWAIT
);
1138 set_intercept(svm
, INTERCEPT_XSETBV
);
1140 control
->iopm_base_pa
= iopm_base
;
1141 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1142 control
->int_ctl
= V_INTR_MASKING_MASK
;
1144 init_seg(&save
->es
);
1145 init_seg(&save
->ss
);
1146 init_seg(&save
->ds
);
1147 init_seg(&save
->fs
);
1148 init_seg(&save
->gs
);
1150 save
->cs
.selector
= 0xf000;
1151 save
->cs
.base
= 0xffff0000;
1152 /* Executable/Readable Code Segment */
1153 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1154 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1155 save
->cs
.limit
= 0xffff;
1157 save
->gdtr
.limit
= 0xffff;
1158 save
->idtr
.limit
= 0xffff;
1160 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1161 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1163 svm_set_efer(&svm
->vcpu
, 0);
1164 save
->dr6
= 0xffff0ff0;
1165 kvm_set_rflags(&svm
->vcpu
, 2);
1166 save
->rip
= 0x0000fff0;
1167 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1170 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1171 * It also updates the guest-visible cr0 value.
1173 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1174 kvm_mmu_reset_context(&svm
->vcpu
);
1176 save
->cr4
= X86_CR4_PAE
;
1180 /* Setup VMCB for Nested Paging */
1181 control
->nested_ctl
= 1;
1182 clr_intercept(svm
, INTERCEPT_INVLPG
);
1183 clr_exception_intercept(svm
, PF_VECTOR
);
1184 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1185 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1186 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1190 svm
->asid_generation
= 0;
1192 svm
->nested
.vmcb
= 0;
1193 svm
->vcpu
.arch
.hflags
= 0;
1195 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1196 control
->pause_filter_count
= 3000;
1197 set_intercept(svm
, INTERCEPT_PAUSE
);
1200 mark_all_dirty(svm
->vmcb
);
1205 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1207 struct vcpu_svm
*svm
= to_svm(vcpu
);
1212 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1213 MSR_IA32_APICBASE_ENABLE
;
1214 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1215 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1219 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
);
1220 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1223 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1225 struct vcpu_svm
*svm
;
1227 struct page
*msrpm_pages
;
1228 struct page
*hsave_page
;
1229 struct page
*nested_msrpm_pages
;
1232 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1238 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1240 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1245 page
= alloc_page(GFP_KERNEL
);
1249 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1253 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1254 if (!nested_msrpm_pages
)
1257 hsave_page
= alloc_page(GFP_KERNEL
);
1261 svm
->nested
.hsave
= page_address(hsave_page
);
1263 svm
->msrpm
= page_address(msrpm_pages
);
1264 svm_vcpu_init_msrpm(svm
->msrpm
);
1266 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1267 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1269 svm
->vmcb
= page_address(page
);
1270 clear_page(svm
->vmcb
);
1271 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1272 svm
->asid_generation
= 0;
1275 svm_init_osvw(&svm
->vcpu
);
1280 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1282 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1286 kvm_vcpu_uninit(&svm
->vcpu
);
1288 kmem_cache_free(kvm_vcpu_cache
, svm
);
1290 return ERR_PTR(err
);
1293 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1295 struct vcpu_svm
*svm
= to_svm(vcpu
);
1297 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1298 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1299 __free_page(virt_to_page(svm
->nested
.hsave
));
1300 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1301 kvm_vcpu_uninit(vcpu
);
1302 kmem_cache_free(kvm_vcpu_cache
, svm
);
1305 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1307 struct vcpu_svm
*svm
= to_svm(vcpu
);
1310 if (unlikely(cpu
!= vcpu
->cpu
)) {
1311 svm
->asid_generation
= 0;
1312 mark_all_dirty(svm
->vmcb
);
1315 #ifdef CONFIG_X86_64
1316 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1318 savesegment(fs
, svm
->host
.fs
);
1319 savesegment(gs
, svm
->host
.gs
);
1320 svm
->host
.ldt
= kvm_read_ldt();
1322 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1323 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1325 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
) &&
1326 svm
->tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1327 __this_cpu_write(current_tsc_ratio
, svm
->tsc_ratio
);
1328 wrmsrl(MSR_AMD64_TSC_RATIO
, svm
->tsc_ratio
);
1332 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1334 struct vcpu_svm
*svm
= to_svm(vcpu
);
1337 ++vcpu
->stat
.host_state_reload
;
1338 kvm_load_ldt(svm
->host
.ldt
);
1339 #ifdef CONFIG_X86_64
1340 loadsegment(fs
, svm
->host
.fs
);
1341 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1342 load_gs_index(svm
->host
.gs
);
1344 #ifdef CONFIG_X86_32_LAZY_GS
1345 loadsegment(gs
, svm
->host
.gs
);
1348 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1349 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1352 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1354 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1357 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1360 * Any change of EFLAGS.VM is accompained by a reload of SS
1361 * (caused by either a task switch or an inter-privilege IRET),
1362 * so we do not need to update the CPL here.
1364 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1367 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1370 case VCPU_EXREG_PDPTR
:
1371 BUG_ON(!npt_enabled
);
1372 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1379 static void svm_set_vintr(struct vcpu_svm
*svm
)
1381 set_intercept(svm
, INTERCEPT_VINTR
);
1384 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1386 clr_intercept(svm
, INTERCEPT_VINTR
);
1389 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1391 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1394 case VCPU_SREG_CS
: return &save
->cs
;
1395 case VCPU_SREG_DS
: return &save
->ds
;
1396 case VCPU_SREG_ES
: return &save
->es
;
1397 case VCPU_SREG_FS
: return &save
->fs
;
1398 case VCPU_SREG_GS
: return &save
->gs
;
1399 case VCPU_SREG_SS
: return &save
->ss
;
1400 case VCPU_SREG_TR
: return &save
->tr
;
1401 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1407 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1409 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1414 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1415 struct kvm_segment
*var
, int seg
)
1417 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1419 var
->base
= s
->base
;
1420 var
->limit
= s
->limit
;
1421 var
->selector
= s
->selector
;
1422 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1423 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1424 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1425 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1426 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1427 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1428 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1431 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1432 * However, the SVM spec states that the G bit is not observed by the
1433 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1434 * So let's synthesize a legal G bit for all segments, this helps
1435 * running KVM nested. It also helps cross-vendor migration, because
1436 * Intel's vmentry has a check on the 'G' bit.
1438 var
->g
= s
->limit
> 0xfffff;
1441 * AMD's VMCB does not have an explicit unusable field, so emulate it
1442 * for cross vendor migration purposes by "not present"
1444 var
->unusable
= !var
->present
|| (var
->type
== 0);
1449 * Work around a bug where the busy flag in the tr selector
1459 * The accessed bit must always be set in the segment
1460 * descriptor cache, although it can be cleared in the
1461 * descriptor, the cached bit always remains at 1. Since
1462 * Intel has a check on this, set it here to support
1463 * cross-vendor migration.
1470 * On AMD CPUs sometimes the DB bit in the segment
1471 * descriptor is left as 1, although the whole segment has
1472 * been made unusable. Clear it here to pass an Intel VMX
1473 * entry check when cross vendor migrating.
1477 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1482 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1484 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1489 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1491 struct vcpu_svm
*svm
= to_svm(vcpu
);
1493 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1494 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1497 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1499 struct vcpu_svm
*svm
= to_svm(vcpu
);
1501 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1502 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1503 mark_dirty(svm
->vmcb
, VMCB_DT
);
1506 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1508 struct vcpu_svm
*svm
= to_svm(vcpu
);
1510 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1511 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1514 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1516 struct vcpu_svm
*svm
= to_svm(vcpu
);
1518 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1519 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1520 mark_dirty(svm
->vmcb
, VMCB_DT
);
1523 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1527 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1531 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1535 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1537 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1538 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1540 if (!svm
->vcpu
.fpu_active
)
1541 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1543 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1544 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1546 mark_dirty(svm
->vmcb
, VMCB_CR
);
1548 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1549 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1550 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1552 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1553 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1557 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1559 struct vcpu_svm
*svm
= to_svm(vcpu
);
1561 #ifdef CONFIG_X86_64
1562 if (vcpu
->arch
.efer
& EFER_LME
) {
1563 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1564 vcpu
->arch
.efer
|= EFER_LMA
;
1565 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1568 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1569 vcpu
->arch
.efer
&= ~EFER_LMA
;
1570 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1574 vcpu
->arch
.cr0
= cr0
;
1577 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1579 if (!vcpu
->fpu_active
)
1582 * re-enable caching here because the QEMU bios
1583 * does not do it - this results in some delay at
1586 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
1587 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1588 svm
->vmcb
->save
.cr0
= cr0
;
1589 mark_dirty(svm
->vmcb
, VMCB_CR
);
1590 update_cr0_intercept(svm
);
1593 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1595 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
1596 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1598 if (cr4
& X86_CR4_VMXE
)
1601 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1602 svm_flush_tlb(vcpu
);
1604 vcpu
->arch
.cr4
= cr4
;
1607 cr4
|= host_cr4_mce
;
1608 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1609 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1613 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1614 struct kvm_segment
*var
, int seg
)
1616 struct vcpu_svm
*svm
= to_svm(vcpu
);
1617 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1619 s
->base
= var
->base
;
1620 s
->limit
= var
->limit
;
1621 s
->selector
= var
->selector
;
1625 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1626 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1627 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1628 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1629 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1630 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1631 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1632 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1636 * This is always accurate, except if SYSRET returned to a segment
1637 * with SS.DPL != 3. Intel does not have this quirk, and always
1638 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1639 * would entail passing the CPL to userspace and back.
1641 if (seg
== VCPU_SREG_SS
)
1642 svm
->vmcb
->save
.cpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1644 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1647 static void update_db_bp_intercept(struct kvm_vcpu
*vcpu
)
1649 struct vcpu_svm
*svm
= to_svm(vcpu
);
1651 clr_exception_intercept(svm
, DB_VECTOR
);
1652 clr_exception_intercept(svm
, BP_VECTOR
);
1654 if (svm
->nmi_singlestep
)
1655 set_exception_intercept(svm
, DB_VECTOR
);
1657 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1658 if (vcpu
->guest_debug
&
1659 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1660 set_exception_intercept(svm
, DB_VECTOR
);
1661 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1662 set_exception_intercept(svm
, BP_VECTOR
);
1664 vcpu
->guest_debug
= 0;
1667 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1669 if (sd
->next_asid
> sd
->max_asid
) {
1670 ++sd
->asid_generation
;
1672 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1675 svm
->asid_generation
= sd
->asid_generation
;
1676 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1678 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1681 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
1683 return to_svm(vcpu
)->vmcb
->save
.dr6
;
1686 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
1688 struct vcpu_svm
*svm
= to_svm(vcpu
);
1690 svm
->vmcb
->save
.dr6
= value
;
1691 mark_dirty(svm
->vmcb
, VMCB_DR
);
1694 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
1696 struct vcpu_svm
*svm
= to_svm(vcpu
);
1698 get_debugreg(vcpu
->arch
.db
[0], 0);
1699 get_debugreg(vcpu
->arch
.db
[1], 1);
1700 get_debugreg(vcpu
->arch
.db
[2], 2);
1701 get_debugreg(vcpu
->arch
.db
[3], 3);
1702 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
1703 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
1705 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
1706 set_dr_intercepts(svm
);
1709 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1711 struct vcpu_svm
*svm
= to_svm(vcpu
);
1713 svm
->vmcb
->save
.dr7
= value
;
1714 mark_dirty(svm
->vmcb
, VMCB_DR
);
1717 static int pf_interception(struct vcpu_svm
*svm
)
1719 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1723 switch (svm
->apf_reason
) {
1725 error_code
= svm
->vmcb
->control
.exit_info_1
;
1727 trace_kvm_page_fault(fault_address
, error_code
);
1728 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1729 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1730 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1731 svm
->vmcb
->control
.insn_bytes
,
1732 svm
->vmcb
->control
.insn_len
);
1734 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1735 svm
->apf_reason
= 0;
1736 local_irq_disable();
1737 kvm_async_pf_task_wait(fault_address
);
1740 case KVM_PV_REASON_PAGE_READY
:
1741 svm
->apf_reason
= 0;
1742 local_irq_disable();
1743 kvm_async_pf_task_wake(fault_address
);
1750 static int db_interception(struct vcpu_svm
*svm
)
1752 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1754 if (!(svm
->vcpu
.guest_debug
&
1755 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1756 !svm
->nmi_singlestep
) {
1757 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1761 if (svm
->nmi_singlestep
) {
1762 svm
->nmi_singlestep
= false;
1763 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1764 svm
->vmcb
->save
.rflags
&=
1765 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1766 update_db_bp_intercept(&svm
->vcpu
);
1769 if (svm
->vcpu
.guest_debug
&
1770 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1771 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1772 kvm_run
->debug
.arch
.pc
=
1773 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1774 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1781 static int bp_interception(struct vcpu_svm
*svm
)
1783 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1785 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1786 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1787 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1791 static int ud_interception(struct vcpu_svm
*svm
)
1795 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1796 if (er
!= EMULATE_DONE
)
1797 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1801 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1803 struct vcpu_svm
*svm
= to_svm(vcpu
);
1805 clr_exception_intercept(svm
, NM_VECTOR
);
1807 svm
->vcpu
.fpu_active
= 1;
1808 update_cr0_intercept(svm
);
1811 static int nm_interception(struct vcpu_svm
*svm
)
1813 svm_fpu_activate(&svm
->vcpu
);
1817 static bool is_erratum_383(void)
1822 if (!erratum_383_found
)
1825 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1829 /* Bit 62 may or may not be set for this mce */
1830 value
&= ~(1ULL << 62);
1832 if (value
!= 0xb600000000010015ULL
)
1835 /* Clear MCi_STATUS registers */
1836 for (i
= 0; i
< 6; ++i
)
1837 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1839 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1843 value
&= ~(1ULL << 2);
1844 low
= lower_32_bits(value
);
1845 high
= upper_32_bits(value
);
1847 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1850 /* Flush tlb to evict multi-match entries */
1856 static void svm_handle_mce(struct vcpu_svm
*svm
)
1858 if (is_erratum_383()) {
1860 * Erratum 383 triggered. Guest state is corrupt so kill the
1863 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1865 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1871 * On an #MC intercept the MCE handler is not called automatically in
1872 * the host. So do it by hand here.
1876 /* not sure if we ever come back to this point */
1881 static int mc_interception(struct vcpu_svm
*svm
)
1886 static int shutdown_interception(struct vcpu_svm
*svm
)
1888 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1891 * VMCB is undefined after a SHUTDOWN intercept
1892 * so reinitialize it.
1894 clear_page(svm
->vmcb
);
1897 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1901 static int io_interception(struct vcpu_svm
*svm
)
1903 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1904 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1905 int size
, in
, string
;
1908 ++svm
->vcpu
.stat
.io_exits
;
1909 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1910 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1912 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
1914 port
= io_info
>> 16;
1915 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1916 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1917 skip_emulated_instruction(&svm
->vcpu
);
1919 return kvm_fast_pio_out(vcpu
, size
, port
);
1922 static int nmi_interception(struct vcpu_svm
*svm
)
1927 static int intr_interception(struct vcpu_svm
*svm
)
1929 ++svm
->vcpu
.stat
.irq_exits
;
1933 static int nop_on_interception(struct vcpu_svm
*svm
)
1938 static int halt_interception(struct vcpu_svm
*svm
)
1940 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1941 return kvm_emulate_halt(&svm
->vcpu
);
1944 static int vmmcall_interception(struct vcpu_svm
*svm
)
1946 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1947 kvm_emulate_hypercall(&svm
->vcpu
);
1951 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1953 struct vcpu_svm
*svm
= to_svm(vcpu
);
1955 return svm
->nested
.nested_cr3
;
1958 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
1960 struct vcpu_svm
*svm
= to_svm(vcpu
);
1961 u64 cr3
= svm
->nested
.nested_cr3
;
1965 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(cr3
), &pdpte
,
1966 offset_in_page(cr3
) + index
* 8, 8);
1972 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1975 struct vcpu_svm
*svm
= to_svm(vcpu
);
1977 svm
->vmcb
->control
.nested_cr3
= root
;
1978 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1979 svm_flush_tlb(vcpu
);
1982 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1983 struct x86_exception
*fault
)
1985 struct vcpu_svm
*svm
= to_svm(vcpu
);
1987 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
1989 * TODO: track the cause of the nested page fault, and
1990 * correctly fill in the high bits of exit_info_1.
1992 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1993 svm
->vmcb
->control
.exit_code_hi
= 0;
1994 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
1995 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1998 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
1999 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2002 * The present bit is always zero for page structure faults on real
2005 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2006 svm
->vmcb
->control
.exit_info_1
&= ~1;
2008 nested_svm_vmexit(svm
);
2011 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2013 WARN_ON(mmu_is_nested(vcpu
));
2014 kvm_init_shadow_mmu(vcpu
);
2015 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2016 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2017 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2018 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2019 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
2020 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2021 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2024 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2026 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2029 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2031 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
2032 || !is_paging(&svm
->vcpu
)) {
2033 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2037 if (svm
->vmcb
->save
.cpl
) {
2038 kvm_inject_gp(&svm
->vcpu
, 0);
2045 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2046 bool has_error_code
, u32 error_code
)
2050 if (!is_guest_mode(&svm
->vcpu
))
2053 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2054 svm
->vmcb
->control
.exit_code_hi
= 0;
2055 svm
->vmcb
->control
.exit_info_1
= error_code
;
2056 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2058 vmexit
= nested_svm_intercept(svm
);
2059 if (vmexit
== NESTED_EXIT_DONE
)
2060 svm
->nested
.exit_required
= true;
2065 /* This function returns true if it is save to enable the irq window */
2066 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2068 if (!is_guest_mode(&svm
->vcpu
))
2071 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2074 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2078 * if vmexit was already requested (by intercepted exception
2079 * for instance) do not overwrite it with "external interrupt"
2082 if (svm
->nested
.exit_required
)
2085 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2086 svm
->vmcb
->control
.exit_info_1
= 0;
2087 svm
->vmcb
->control
.exit_info_2
= 0;
2089 if (svm
->nested
.intercept
& 1ULL) {
2091 * The #vmexit can't be emulated here directly because this
2092 * code path runs with irqs and preemption disabled. A
2093 * #vmexit emulation might sleep. Only signal request for
2096 svm
->nested
.exit_required
= true;
2097 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2104 /* This function returns true if it is save to enable the nmi window */
2105 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2107 if (!is_guest_mode(&svm
->vcpu
))
2110 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2113 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2114 svm
->nested
.exit_required
= true;
2119 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2125 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2126 if (is_error_page(page
))
2134 kvm_inject_gp(&svm
->vcpu
, 0);
2139 static void nested_svm_unmap(struct page
*page
)
2142 kvm_release_page_dirty(page
);
2145 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2147 unsigned port
, size
, iopm_len
;
2152 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2153 return NESTED_EXIT_HOST
;
2155 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2156 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2157 SVM_IOIO_SIZE_SHIFT
;
2158 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2159 start_bit
= port
% 8;
2160 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2161 mask
= (0xf >> (4 - size
)) << start_bit
;
2164 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2165 return NESTED_EXIT_DONE
;
2167 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2170 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2172 u32 offset
, msr
, value
;
2175 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2176 return NESTED_EXIT_HOST
;
2178 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2179 offset
= svm_msrpm_offset(msr
);
2180 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2181 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2183 if (offset
== MSR_INVALID
)
2184 return NESTED_EXIT_DONE
;
2186 /* Offset is in 32 bit units but need in 8 bit units */
2189 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2190 return NESTED_EXIT_DONE
;
2192 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2195 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2197 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2199 switch (exit_code
) {
2202 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2203 return NESTED_EXIT_HOST
;
2205 /* For now we are always handling NPFs when using them */
2207 return NESTED_EXIT_HOST
;
2209 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2210 /* When we're shadowing, trap PFs, but not async PF */
2211 if (!npt_enabled
&& svm
->apf_reason
== 0)
2212 return NESTED_EXIT_HOST
;
2214 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2215 nm_interception(svm
);
2221 return NESTED_EXIT_CONTINUE
;
2225 * If this function returns true, this #vmexit was already handled
2227 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2229 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2230 int vmexit
= NESTED_EXIT_HOST
;
2232 switch (exit_code
) {
2234 vmexit
= nested_svm_exit_handled_msr(svm
);
2237 vmexit
= nested_svm_intercept_ioio(svm
);
2239 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2240 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2241 if (svm
->nested
.intercept_cr
& bit
)
2242 vmexit
= NESTED_EXIT_DONE
;
2245 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2246 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2247 if (svm
->nested
.intercept_dr
& bit
)
2248 vmexit
= NESTED_EXIT_DONE
;
2251 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2252 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2253 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2254 vmexit
= NESTED_EXIT_DONE
;
2255 /* async page fault always cause vmexit */
2256 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2257 svm
->apf_reason
!= 0)
2258 vmexit
= NESTED_EXIT_DONE
;
2261 case SVM_EXIT_ERR
: {
2262 vmexit
= NESTED_EXIT_DONE
;
2266 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2267 if (svm
->nested
.intercept
& exit_bits
)
2268 vmexit
= NESTED_EXIT_DONE
;
2275 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2279 vmexit
= nested_svm_intercept(svm
);
2281 if (vmexit
== NESTED_EXIT_DONE
)
2282 nested_svm_vmexit(svm
);
2287 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2289 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2290 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2292 dst
->intercept_cr
= from
->intercept_cr
;
2293 dst
->intercept_dr
= from
->intercept_dr
;
2294 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2295 dst
->intercept
= from
->intercept
;
2296 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2297 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2298 dst
->tsc_offset
= from
->tsc_offset
;
2299 dst
->asid
= from
->asid
;
2300 dst
->tlb_ctl
= from
->tlb_ctl
;
2301 dst
->int_ctl
= from
->int_ctl
;
2302 dst
->int_vector
= from
->int_vector
;
2303 dst
->int_state
= from
->int_state
;
2304 dst
->exit_code
= from
->exit_code
;
2305 dst
->exit_code_hi
= from
->exit_code_hi
;
2306 dst
->exit_info_1
= from
->exit_info_1
;
2307 dst
->exit_info_2
= from
->exit_info_2
;
2308 dst
->exit_int_info
= from
->exit_int_info
;
2309 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2310 dst
->nested_ctl
= from
->nested_ctl
;
2311 dst
->event_inj
= from
->event_inj
;
2312 dst
->event_inj_err
= from
->event_inj_err
;
2313 dst
->nested_cr3
= from
->nested_cr3
;
2314 dst
->lbr_ctl
= from
->lbr_ctl
;
2317 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2319 struct vmcb
*nested_vmcb
;
2320 struct vmcb
*hsave
= svm
->nested
.hsave
;
2321 struct vmcb
*vmcb
= svm
->vmcb
;
2324 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2325 vmcb
->control
.exit_info_1
,
2326 vmcb
->control
.exit_info_2
,
2327 vmcb
->control
.exit_int_info
,
2328 vmcb
->control
.exit_int_info_err
,
2331 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2335 /* Exit Guest-Mode */
2336 leave_guest_mode(&svm
->vcpu
);
2337 svm
->nested
.vmcb
= 0;
2339 /* Give the current vmcb to the guest */
2342 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2343 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2344 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2345 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2346 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2347 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2348 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2349 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2350 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2351 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2352 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2353 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2354 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2355 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2356 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2357 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2358 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2359 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2361 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2362 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2363 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2364 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2365 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2366 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2367 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2368 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2369 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2371 if (svm
->nrips_enabled
)
2372 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2375 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2376 * to make sure that we do not lose injected events. So check event_inj
2377 * here and copy it to exit_int_info if it is valid.
2378 * Exit_int_info and event_inj can't be both valid because the case
2379 * below only happens on a VMRUN instruction intercept which has
2380 * no valid exit_int_info set.
2382 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2383 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2385 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2386 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2389 nested_vmcb
->control
.tlb_ctl
= 0;
2390 nested_vmcb
->control
.event_inj
= 0;
2391 nested_vmcb
->control
.event_inj_err
= 0;
2393 /* We always set V_INTR_MASKING and remember the old value in hflags */
2394 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2395 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2397 /* Restore the original control entries */
2398 copy_vmcb_control_area(vmcb
, hsave
);
2400 kvm_clear_exception_queue(&svm
->vcpu
);
2401 kvm_clear_interrupt_queue(&svm
->vcpu
);
2403 svm
->nested
.nested_cr3
= 0;
2405 /* Restore selected save entries */
2406 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2407 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2408 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2409 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2410 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2411 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2412 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2413 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2414 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2415 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2417 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2418 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2420 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2422 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2423 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2424 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2425 svm
->vmcb
->save
.dr7
= 0;
2426 svm
->vmcb
->save
.cpl
= 0;
2427 svm
->vmcb
->control
.exit_int_info
= 0;
2429 mark_all_dirty(svm
->vmcb
);
2431 nested_svm_unmap(page
);
2433 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2434 kvm_mmu_reset_context(&svm
->vcpu
);
2435 kvm_mmu_load(&svm
->vcpu
);
2440 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2443 * This function merges the msr permission bitmaps of kvm and the
2444 * nested vmcb. It is optimized in that it only merges the parts where
2445 * the kvm msr permission bitmap may contain zero bits
2449 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2452 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2456 if (msrpm_offsets
[i
] == 0xffffffff)
2459 p
= msrpm_offsets
[i
];
2460 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2462 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2465 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2468 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2473 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2475 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2478 if (vmcb
->control
.asid
== 0)
2481 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2487 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2489 struct vmcb
*nested_vmcb
;
2490 struct vmcb
*hsave
= svm
->nested
.hsave
;
2491 struct vmcb
*vmcb
= svm
->vmcb
;
2495 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2497 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2501 if (!nested_vmcb_checks(nested_vmcb
)) {
2502 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2503 nested_vmcb
->control
.exit_code_hi
= 0;
2504 nested_vmcb
->control
.exit_info_1
= 0;
2505 nested_vmcb
->control
.exit_info_2
= 0;
2507 nested_svm_unmap(page
);
2512 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2513 nested_vmcb
->save
.rip
,
2514 nested_vmcb
->control
.int_ctl
,
2515 nested_vmcb
->control
.event_inj
,
2516 nested_vmcb
->control
.nested_ctl
);
2518 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2519 nested_vmcb
->control
.intercept_cr
>> 16,
2520 nested_vmcb
->control
.intercept_exceptions
,
2521 nested_vmcb
->control
.intercept
);
2523 /* Clear internal status */
2524 kvm_clear_exception_queue(&svm
->vcpu
);
2525 kvm_clear_interrupt_queue(&svm
->vcpu
);
2528 * Save the old vmcb, so we don't need to pick what we save, but can
2529 * restore everything when a VMEXIT occurs
2531 hsave
->save
.es
= vmcb
->save
.es
;
2532 hsave
->save
.cs
= vmcb
->save
.cs
;
2533 hsave
->save
.ss
= vmcb
->save
.ss
;
2534 hsave
->save
.ds
= vmcb
->save
.ds
;
2535 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2536 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2537 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2538 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2539 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2540 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2541 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2542 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2543 hsave
->save
.rax
= vmcb
->save
.rax
;
2545 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2547 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2549 copy_vmcb_control_area(hsave
, vmcb
);
2551 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2552 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2554 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2556 if (nested_vmcb
->control
.nested_ctl
) {
2557 kvm_mmu_unload(&svm
->vcpu
);
2558 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2559 nested_svm_init_mmu_context(&svm
->vcpu
);
2562 /* Load the nested guest state */
2563 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2564 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2565 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2566 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2567 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2568 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2569 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2570 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2571 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2572 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2574 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2575 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2577 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2579 /* Guest paging mode is active - reset mmu */
2580 kvm_mmu_reset_context(&svm
->vcpu
);
2582 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2583 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2584 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2585 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2587 /* In case we don't even reach vcpu_run, the fields are not updated */
2588 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2589 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2590 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2591 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2592 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2593 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2595 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2596 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2598 /* cache intercepts */
2599 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2600 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2601 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2602 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2604 svm_flush_tlb(&svm
->vcpu
);
2605 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2606 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2607 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2609 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2611 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2612 /* We only want the cr8 intercept bits of the guest */
2613 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2614 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2617 /* We don't want to see VMMCALLs from a nested guest */
2618 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2620 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2621 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2622 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2623 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2624 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2625 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2627 nested_svm_unmap(page
);
2629 /* Enter Guest-Mode */
2630 enter_guest_mode(&svm
->vcpu
);
2633 * Merge guest and host intercepts - must be called with vcpu in
2634 * guest-mode to take affect here
2636 recalc_intercepts(svm
);
2638 svm
->nested
.vmcb
= vmcb_gpa
;
2642 mark_all_dirty(svm
->vmcb
);
2647 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2649 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2650 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2651 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2652 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2653 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2654 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2655 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2656 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2657 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2658 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2659 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2660 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2663 static int vmload_interception(struct vcpu_svm
*svm
)
2665 struct vmcb
*nested_vmcb
;
2668 if (nested_svm_check_permissions(svm
))
2671 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2675 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2676 skip_emulated_instruction(&svm
->vcpu
);
2678 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2679 nested_svm_unmap(page
);
2684 static int vmsave_interception(struct vcpu_svm
*svm
)
2686 struct vmcb
*nested_vmcb
;
2689 if (nested_svm_check_permissions(svm
))
2692 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2696 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2697 skip_emulated_instruction(&svm
->vcpu
);
2699 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2700 nested_svm_unmap(page
);
2705 static int vmrun_interception(struct vcpu_svm
*svm
)
2707 if (nested_svm_check_permissions(svm
))
2710 /* Save rip after vmrun instruction */
2711 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2713 if (!nested_svm_vmrun(svm
))
2716 if (!nested_svm_vmrun_msrpm(svm
))
2723 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2724 svm
->vmcb
->control
.exit_code_hi
= 0;
2725 svm
->vmcb
->control
.exit_info_1
= 0;
2726 svm
->vmcb
->control
.exit_info_2
= 0;
2728 nested_svm_vmexit(svm
);
2733 static int stgi_interception(struct vcpu_svm
*svm
)
2735 if (nested_svm_check_permissions(svm
))
2738 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2739 skip_emulated_instruction(&svm
->vcpu
);
2740 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2747 static int clgi_interception(struct vcpu_svm
*svm
)
2749 if (nested_svm_check_permissions(svm
))
2752 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2753 skip_emulated_instruction(&svm
->vcpu
);
2757 /* After a CLGI no interrupts should come */
2758 svm_clear_vintr(svm
);
2759 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2761 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2766 static int invlpga_interception(struct vcpu_svm
*svm
)
2768 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2770 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
2771 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2773 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2774 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2776 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2777 skip_emulated_instruction(&svm
->vcpu
);
2781 static int skinit_interception(struct vcpu_svm
*svm
)
2783 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
2785 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2789 static int wbinvd_interception(struct vcpu_svm
*svm
)
2791 kvm_emulate_wbinvd(&svm
->vcpu
);
2795 static int xsetbv_interception(struct vcpu_svm
*svm
)
2797 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2798 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2800 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2801 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2802 skip_emulated_instruction(&svm
->vcpu
);
2808 static int task_switch_interception(struct vcpu_svm
*svm
)
2812 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2813 SVM_EXITINTINFO_TYPE_MASK
;
2814 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2816 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2818 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2819 bool has_error_code
= false;
2822 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2824 if (svm
->vmcb
->control
.exit_info_2
&
2825 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2826 reason
= TASK_SWITCH_IRET
;
2827 else if (svm
->vmcb
->control
.exit_info_2
&
2828 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2829 reason
= TASK_SWITCH_JMP
;
2831 reason
= TASK_SWITCH_GATE
;
2833 reason
= TASK_SWITCH_CALL
;
2835 if (reason
== TASK_SWITCH_GATE
) {
2837 case SVM_EXITINTINFO_TYPE_NMI
:
2838 svm
->vcpu
.arch
.nmi_injected
= false;
2840 case SVM_EXITINTINFO_TYPE_EXEPT
:
2841 if (svm
->vmcb
->control
.exit_info_2
&
2842 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2843 has_error_code
= true;
2845 (u32
)svm
->vmcb
->control
.exit_info_2
;
2847 kvm_clear_exception_queue(&svm
->vcpu
);
2849 case SVM_EXITINTINFO_TYPE_INTR
:
2850 kvm_clear_interrupt_queue(&svm
->vcpu
);
2857 if (reason
!= TASK_SWITCH_GATE
||
2858 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2859 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2860 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2861 skip_emulated_instruction(&svm
->vcpu
);
2863 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
2866 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
2867 has_error_code
, error_code
) == EMULATE_FAIL
) {
2868 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2869 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2870 svm
->vcpu
.run
->internal
.ndata
= 0;
2876 static int cpuid_interception(struct vcpu_svm
*svm
)
2878 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2879 kvm_emulate_cpuid(&svm
->vcpu
);
2883 static int iret_interception(struct vcpu_svm
*svm
)
2885 ++svm
->vcpu
.stat
.nmi_window_exits
;
2886 clr_intercept(svm
, INTERCEPT_IRET
);
2887 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2888 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2889 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2893 static int invlpg_interception(struct vcpu_svm
*svm
)
2895 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2896 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2898 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2899 skip_emulated_instruction(&svm
->vcpu
);
2903 static int emulate_on_interception(struct vcpu_svm
*svm
)
2905 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2908 static int rdpmc_interception(struct vcpu_svm
*svm
)
2912 if (!static_cpu_has(X86_FEATURE_NRIPS
))
2913 return emulate_on_interception(svm
);
2915 err
= kvm_rdpmc(&svm
->vcpu
);
2916 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2921 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
2924 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
2928 intercept
= svm
->nested
.intercept
;
2930 if (!is_guest_mode(&svm
->vcpu
) ||
2931 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
2934 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2935 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2938 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2939 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2945 #define CR_VALID (1ULL << 63)
2947 static int cr_interception(struct vcpu_svm
*svm
)
2953 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2954 return emulate_on_interception(svm
);
2956 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2957 return emulate_on_interception(svm
);
2959 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2960 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
2961 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
2963 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2966 if (cr
>= 16) { /* mov to cr */
2968 val
= kvm_register_read(&svm
->vcpu
, reg
);
2971 if (!check_selective_cr0_intercepted(svm
, val
))
2972 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2978 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2981 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2984 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2987 WARN(1, "unhandled write to CR%d", cr
);
2988 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2991 } else { /* mov from cr */
2994 val
= kvm_read_cr0(&svm
->vcpu
);
2997 val
= svm
->vcpu
.arch
.cr2
;
3000 val
= kvm_read_cr3(&svm
->vcpu
);
3003 val
= kvm_read_cr4(&svm
->vcpu
);
3006 val
= kvm_get_cr8(&svm
->vcpu
);
3009 WARN(1, "unhandled read from CR%d", cr
);
3010 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3013 kvm_register_write(&svm
->vcpu
, reg
, val
);
3015 kvm_complete_insn_gp(&svm
->vcpu
, err
);
3020 static int dr_interception(struct vcpu_svm
*svm
)
3025 if (svm
->vcpu
.guest_debug
== 0) {
3027 * No more DR vmexits; force a reload of the debug registers
3028 * and reenter on this instruction. The next vmexit will
3029 * retrieve the full state of the debug registers.
3031 clr_dr_intercepts(svm
);
3032 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3036 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3037 return emulate_on_interception(svm
);
3039 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3040 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3042 if (dr
>= 16) { /* mov to DRn */
3043 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3045 val
= kvm_register_read(&svm
->vcpu
, reg
);
3046 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3048 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3050 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3051 kvm_register_write(&svm
->vcpu
, reg
, val
);
3054 skip_emulated_instruction(&svm
->vcpu
);
3059 static int cr8_write_interception(struct vcpu_svm
*svm
)
3061 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3064 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3065 /* instruction emulation calls kvm_set_cr8() */
3066 r
= cr_interception(svm
);
3067 if (lapic_in_kernel(&svm
->vcpu
))
3069 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3071 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3075 static u64
svm_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
3077 struct vmcb
*vmcb
= get_host_vmcb(to_svm(vcpu
));
3078 return vmcb
->control
.tsc_offset
+
3079 svm_scale_tsc(vcpu
, host_tsc
);
3082 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3084 struct vcpu_svm
*svm
= to_svm(vcpu
);
3086 switch (msr_info
->index
) {
3087 case MSR_IA32_TSC
: {
3088 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
3089 svm_scale_tsc(vcpu
, rdtsc());
3094 msr_info
->data
= svm
->vmcb
->save
.star
;
3096 #ifdef CONFIG_X86_64
3098 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3101 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3103 case MSR_KERNEL_GS_BASE
:
3104 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3106 case MSR_SYSCALL_MASK
:
3107 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3110 case MSR_IA32_SYSENTER_CS
:
3111 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3113 case MSR_IA32_SYSENTER_EIP
:
3114 msr_info
->data
= svm
->sysenter_eip
;
3116 case MSR_IA32_SYSENTER_ESP
:
3117 msr_info
->data
= svm
->sysenter_esp
;
3120 * Nobody will change the following 5 values in the VMCB so we can
3121 * safely return them on rdmsr. They will always be 0 until LBRV is
3124 case MSR_IA32_DEBUGCTLMSR
:
3125 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3127 case MSR_IA32_LASTBRANCHFROMIP
:
3128 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3130 case MSR_IA32_LASTBRANCHTOIP
:
3131 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3133 case MSR_IA32_LASTINTFROMIP
:
3134 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3136 case MSR_IA32_LASTINTTOIP
:
3137 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3139 case MSR_VM_HSAVE_PA
:
3140 msr_info
->data
= svm
->nested
.hsave_msr
;
3143 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3145 case MSR_IA32_UCODE_REV
:
3146 msr_info
->data
= 0x01000065;
3149 return kvm_get_msr_common(vcpu
, msr_info
);
3154 static int rdmsr_interception(struct vcpu_svm
*svm
)
3156 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3157 struct msr_data msr_info
;
3159 msr_info
.index
= ecx
;
3160 msr_info
.host_initiated
= false;
3161 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3162 trace_kvm_msr_read_ex(ecx
);
3163 kvm_inject_gp(&svm
->vcpu
, 0);
3165 trace_kvm_msr_read(ecx
, msr_info
.data
);
3167 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3168 msr_info
.data
& 0xffffffff);
3169 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3170 msr_info
.data
>> 32);
3171 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3172 skip_emulated_instruction(&svm
->vcpu
);
3177 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3179 struct vcpu_svm
*svm
= to_svm(vcpu
);
3180 int svm_dis
, chg_mask
;
3182 if (data
& ~SVM_VM_CR_VALID_MASK
)
3185 chg_mask
= SVM_VM_CR_VALID_MASK
;
3187 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3188 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3190 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3191 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3193 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3195 /* check for svm_disable while efer.svme is set */
3196 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3202 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3204 struct vcpu_svm
*svm
= to_svm(vcpu
);
3206 u32 ecx
= msr
->index
;
3207 u64 data
= msr
->data
;
3210 kvm_write_tsc(vcpu
, msr
);
3213 svm
->vmcb
->save
.star
= data
;
3215 #ifdef CONFIG_X86_64
3217 svm
->vmcb
->save
.lstar
= data
;
3220 svm
->vmcb
->save
.cstar
= data
;
3222 case MSR_KERNEL_GS_BASE
:
3223 svm
->vmcb
->save
.kernel_gs_base
= data
;
3225 case MSR_SYSCALL_MASK
:
3226 svm
->vmcb
->save
.sfmask
= data
;
3229 case MSR_IA32_SYSENTER_CS
:
3230 svm
->vmcb
->save
.sysenter_cs
= data
;
3232 case MSR_IA32_SYSENTER_EIP
:
3233 svm
->sysenter_eip
= data
;
3234 svm
->vmcb
->save
.sysenter_eip
= data
;
3236 case MSR_IA32_SYSENTER_ESP
:
3237 svm
->sysenter_esp
= data
;
3238 svm
->vmcb
->save
.sysenter_esp
= data
;
3240 case MSR_IA32_DEBUGCTLMSR
:
3241 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3242 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3246 if (data
& DEBUGCTL_RESERVED_BITS
)
3249 svm
->vmcb
->save
.dbgctl
= data
;
3250 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3251 if (data
& (1ULL<<0))
3252 svm_enable_lbrv(svm
);
3254 svm_disable_lbrv(svm
);
3256 case MSR_VM_HSAVE_PA
:
3257 svm
->nested
.hsave_msr
= data
;
3260 return svm_set_vm_cr(vcpu
, data
);
3262 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3265 return kvm_set_msr_common(vcpu
, msr
);
3270 static int wrmsr_interception(struct vcpu_svm
*svm
)
3272 struct msr_data msr
;
3273 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3274 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3278 msr
.host_initiated
= false;
3280 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3281 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3282 trace_kvm_msr_write_ex(ecx
, data
);
3283 kvm_inject_gp(&svm
->vcpu
, 0);
3285 trace_kvm_msr_write(ecx
, data
);
3286 skip_emulated_instruction(&svm
->vcpu
);
3291 static int msr_interception(struct vcpu_svm
*svm
)
3293 if (svm
->vmcb
->control
.exit_info_1
)
3294 return wrmsr_interception(svm
);
3296 return rdmsr_interception(svm
);
3299 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3301 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3302 svm_clear_vintr(svm
);
3303 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3304 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3305 ++svm
->vcpu
.stat
.irq_window_exits
;
3309 static int pause_interception(struct vcpu_svm
*svm
)
3311 kvm_vcpu_on_spin(&(svm
->vcpu
));
3315 static int nop_interception(struct vcpu_svm
*svm
)
3317 skip_emulated_instruction(&(svm
->vcpu
));
3321 static int monitor_interception(struct vcpu_svm
*svm
)
3323 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3324 return nop_interception(svm
);
3327 static int mwait_interception(struct vcpu_svm
*svm
)
3329 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3330 return nop_interception(svm
);
3333 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3334 [SVM_EXIT_READ_CR0
] = cr_interception
,
3335 [SVM_EXIT_READ_CR3
] = cr_interception
,
3336 [SVM_EXIT_READ_CR4
] = cr_interception
,
3337 [SVM_EXIT_READ_CR8
] = cr_interception
,
3338 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
3339 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3340 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3341 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3342 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3343 [SVM_EXIT_READ_DR0
] = dr_interception
,
3344 [SVM_EXIT_READ_DR1
] = dr_interception
,
3345 [SVM_EXIT_READ_DR2
] = dr_interception
,
3346 [SVM_EXIT_READ_DR3
] = dr_interception
,
3347 [SVM_EXIT_READ_DR4
] = dr_interception
,
3348 [SVM_EXIT_READ_DR5
] = dr_interception
,
3349 [SVM_EXIT_READ_DR6
] = dr_interception
,
3350 [SVM_EXIT_READ_DR7
] = dr_interception
,
3351 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3352 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3353 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3354 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3355 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3356 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3357 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3358 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3359 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3360 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3361 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3362 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3363 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3364 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3365 [SVM_EXIT_INTR
] = intr_interception
,
3366 [SVM_EXIT_NMI
] = nmi_interception
,
3367 [SVM_EXIT_SMI
] = nop_on_interception
,
3368 [SVM_EXIT_INIT
] = nop_on_interception
,
3369 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3370 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3371 [SVM_EXIT_CPUID
] = cpuid_interception
,
3372 [SVM_EXIT_IRET
] = iret_interception
,
3373 [SVM_EXIT_INVD
] = emulate_on_interception
,
3374 [SVM_EXIT_PAUSE
] = pause_interception
,
3375 [SVM_EXIT_HLT
] = halt_interception
,
3376 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3377 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3378 [SVM_EXIT_IOIO
] = io_interception
,
3379 [SVM_EXIT_MSR
] = msr_interception
,
3380 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3381 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3382 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3383 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3384 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3385 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3386 [SVM_EXIT_STGI
] = stgi_interception
,
3387 [SVM_EXIT_CLGI
] = clgi_interception
,
3388 [SVM_EXIT_SKINIT
] = skinit_interception
,
3389 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
3390 [SVM_EXIT_MONITOR
] = monitor_interception
,
3391 [SVM_EXIT_MWAIT
] = mwait_interception
,
3392 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3393 [SVM_EXIT_NPF
] = pf_interception
,
3394 [SVM_EXIT_RSM
] = emulate_on_interception
,
3397 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3399 struct vcpu_svm
*svm
= to_svm(vcpu
);
3400 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3401 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3403 pr_err("VMCB Control Area:\n");
3404 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
3405 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
3406 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
3407 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
3408 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
3409 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
3410 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3411 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3412 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3413 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3414 pr_err("%-20s%d\n", "asid:", control
->asid
);
3415 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3416 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3417 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3418 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3419 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3420 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3421 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3422 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3423 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3424 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3425 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3426 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3427 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3428 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
3429 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3430 pr_err("VMCB State Save Area:\n");
3431 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3433 save
->es
.selector
, save
->es
.attrib
,
3434 save
->es
.limit
, save
->es
.base
);
3435 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3437 save
->cs
.selector
, save
->cs
.attrib
,
3438 save
->cs
.limit
, save
->cs
.base
);
3439 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3441 save
->ss
.selector
, save
->ss
.attrib
,
3442 save
->ss
.limit
, save
->ss
.base
);
3443 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3445 save
->ds
.selector
, save
->ds
.attrib
,
3446 save
->ds
.limit
, save
->ds
.base
);
3447 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3449 save
->fs
.selector
, save
->fs
.attrib
,
3450 save
->fs
.limit
, save
->fs
.base
);
3451 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3453 save
->gs
.selector
, save
->gs
.attrib
,
3454 save
->gs
.limit
, save
->gs
.base
);
3455 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3457 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3458 save
->gdtr
.limit
, save
->gdtr
.base
);
3459 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3461 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3462 save
->ldtr
.limit
, save
->ldtr
.base
);
3463 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3465 save
->idtr
.selector
, save
->idtr
.attrib
,
3466 save
->idtr
.limit
, save
->idtr
.base
);
3467 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3469 save
->tr
.selector
, save
->tr
.attrib
,
3470 save
->tr
.limit
, save
->tr
.base
);
3471 pr_err("cpl: %d efer: %016llx\n",
3472 save
->cpl
, save
->efer
);
3473 pr_err("%-15s %016llx %-13s %016llx\n",
3474 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3475 pr_err("%-15s %016llx %-13s %016llx\n",
3476 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3477 pr_err("%-15s %016llx %-13s %016llx\n",
3478 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3479 pr_err("%-15s %016llx %-13s %016llx\n",
3480 "rip:", save
->rip
, "rflags:", save
->rflags
);
3481 pr_err("%-15s %016llx %-13s %016llx\n",
3482 "rsp:", save
->rsp
, "rax:", save
->rax
);
3483 pr_err("%-15s %016llx %-13s %016llx\n",
3484 "star:", save
->star
, "lstar:", save
->lstar
);
3485 pr_err("%-15s %016llx %-13s %016llx\n",
3486 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3487 pr_err("%-15s %016llx %-13s %016llx\n",
3488 "kernel_gs_base:", save
->kernel_gs_base
,
3489 "sysenter_cs:", save
->sysenter_cs
);
3490 pr_err("%-15s %016llx %-13s %016llx\n",
3491 "sysenter_esp:", save
->sysenter_esp
,
3492 "sysenter_eip:", save
->sysenter_eip
);
3493 pr_err("%-15s %016llx %-13s %016llx\n",
3494 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3495 pr_err("%-15s %016llx %-13s %016llx\n",
3496 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3497 pr_err("%-15s %016llx %-13s %016llx\n",
3498 "excp_from:", save
->last_excp_from
,
3499 "excp_to:", save
->last_excp_to
);
3502 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3504 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3506 *info1
= control
->exit_info_1
;
3507 *info2
= control
->exit_info_2
;
3510 static int handle_exit(struct kvm_vcpu
*vcpu
)
3512 struct vcpu_svm
*svm
= to_svm(vcpu
);
3513 struct kvm_run
*kvm_run
= vcpu
->run
;
3514 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3516 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3517 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3519 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3521 if (unlikely(svm
->nested
.exit_required
)) {
3522 nested_svm_vmexit(svm
);
3523 svm
->nested
.exit_required
= false;
3528 if (is_guest_mode(vcpu
)) {
3531 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3532 svm
->vmcb
->control
.exit_info_1
,
3533 svm
->vmcb
->control
.exit_info_2
,
3534 svm
->vmcb
->control
.exit_int_info
,
3535 svm
->vmcb
->control
.exit_int_info_err
,
3538 vmexit
= nested_svm_exit_special(svm
);
3540 if (vmexit
== NESTED_EXIT_CONTINUE
)
3541 vmexit
= nested_svm_exit_handled(svm
);
3543 if (vmexit
== NESTED_EXIT_DONE
)
3547 svm_complete_interrupts(svm
);
3549 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3550 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3551 kvm_run
->fail_entry
.hardware_entry_failure_reason
3552 = svm
->vmcb
->control
.exit_code
;
3553 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3558 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3559 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3560 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3561 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3562 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
3564 __func__
, svm
->vmcb
->control
.exit_int_info
,
3567 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3568 || !svm_exit_handlers
[exit_code
]) {
3569 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
3570 kvm_queue_exception(vcpu
, UD_VECTOR
);
3574 return svm_exit_handlers
[exit_code
](svm
);
3577 static void reload_tss(struct kvm_vcpu
*vcpu
)
3579 int cpu
= raw_smp_processor_id();
3581 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3582 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3586 static void pre_svm_run(struct vcpu_svm
*svm
)
3588 int cpu
= raw_smp_processor_id();
3590 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3592 /* FIXME: handle wraparound of asid_generation */
3593 if (svm
->asid_generation
!= sd
->asid_generation
)
3597 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3599 struct vcpu_svm
*svm
= to_svm(vcpu
);
3601 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3602 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3603 set_intercept(svm
, INTERCEPT_IRET
);
3604 ++vcpu
->stat
.nmi_injections
;
3607 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3609 struct vmcb_control_area
*control
;
3611 control
= &svm
->vmcb
->control
;
3612 control
->int_vector
= irq
;
3613 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3614 control
->int_ctl
|= V_IRQ_MASK
|
3615 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3616 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3619 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3621 struct vcpu_svm
*svm
= to_svm(vcpu
);
3623 BUG_ON(!(gif_set(svm
)));
3625 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3626 ++vcpu
->stat
.irq_injections
;
3628 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3629 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3632 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3634 struct vcpu_svm
*svm
= to_svm(vcpu
);
3636 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3639 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3645 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3648 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
3653 static int svm_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
3658 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
3663 static void svm_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
3668 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3670 struct vcpu_svm
*svm
= to_svm(vcpu
);
3671 struct vmcb
*vmcb
= svm
->vmcb
;
3673 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3674 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3675 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3680 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3682 struct vcpu_svm
*svm
= to_svm(vcpu
);
3684 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3687 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3689 struct vcpu_svm
*svm
= to_svm(vcpu
);
3692 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3693 set_intercept(svm
, INTERCEPT_IRET
);
3695 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3696 clr_intercept(svm
, INTERCEPT_IRET
);
3700 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3702 struct vcpu_svm
*svm
= to_svm(vcpu
);
3703 struct vmcb
*vmcb
= svm
->vmcb
;
3706 if (!gif_set(svm
) ||
3707 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3710 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
3712 if (is_guest_mode(vcpu
))
3713 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3718 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3720 struct vcpu_svm
*svm
= to_svm(vcpu
);
3723 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3724 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3725 * get that intercept, this function will be called again though and
3726 * we'll get the vintr intercept.
3728 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3730 svm_inject_irq(svm
, 0x0);
3734 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3736 struct vcpu_svm
*svm
= to_svm(vcpu
);
3738 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3740 return; /* IRET will cause a vm exit */
3743 * Something prevents NMI from been injected. Single step over possible
3744 * problem (IRET or exception injection or interrupt shadow)
3746 svm
->nmi_singlestep
= true;
3747 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3748 update_db_bp_intercept(vcpu
);
3751 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3756 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3758 struct vcpu_svm
*svm
= to_svm(vcpu
);
3760 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3761 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3763 svm
->asid_generation
--;
3766 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3770 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3772 struct vcpu_svm
*svm
= to_svm(vcpu
);
3774 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3777 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3778 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3779 kvm_set_cr8(vcpu
, cr8
);
3783 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3785 struct vcpu_svm
*svm
= to_svm(vcpu
);
3788 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3791 cr8
= kvm_get_cr8(vcpu
);
3792 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3793 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3796 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3800 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3801 unsigned int3_injected
= svm
->int3_injected
;
3803 svm
->int3_injected
= 0;
3806 * If we've made progress since setting HF_IRET_MASK, we've
3807 * executed an IRET and can allow NMI injection.
3809 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3810 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
3811 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3812 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3815 svm
->vcpu
.arch
.nmi_injected
= false;
3816 kvm_clear_exception_queue(&svm
->vcpu
);
3817 kvm_clear_interrupt_queue(&svm
->vcpu
);
3819 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3822 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3824 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3825 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3828 case SVM_EXITINTINFO_TYPE_NMI
:
3829 svm
->vcpu
.arch
.nmi_injected
= true;
3831 case SVM_EXITINTINFO_TYPE_EXEPT
:
3833 * In case of software exceptions, do not reinject the vector,
3834 * but re-execute the instruction instead. Rewind RIP first
3835 * if we emulated INT3 before.
3837 if (kvm_exception_is_soft(vector
)) {
3838 if (vector
== BP_VECTOR
&& int3_injected
&&
3839 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3840 kvm_rip_write(&svm
->vcpu
,
3841 kvm_rip_read(&svm
->vcpu
) -
3845 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3846 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3847 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3850 kvm_requeue_exception(&svm
->vcpu
, vector
);
3852 case SVM_EXITINTINFO_TYPE_INTR
:
3853 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3860 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3862 struct vcpu_svm
*svm
= to_svm(vcpu
);
3863 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3865 control
->exit_int_info
= control
->event_inj
;
3866 control
->exit_int_info_err
= control
->event_inj_err
;
3867 control
->event_inj
= 0;
3868 svm_complete_interrupts(svm
);
3871 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3873 struct vcpu_svm
*svm
= to_svm(vcpu
);
3875 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3876 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3877 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3880 * A vmexit emulation is required before the vcpu can be executed
3883 if (unlikely(svm
->nested
.exit_required
))
3888 sync_lapic_to_cr8(vcpu
);
3890 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3897 "push %%" _ASM_BP
"; \n\t"
3898 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
3899 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
3900 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
3901 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
3902 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
3903 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
3904 #ifdef CONFIG_X86_64
3905 "mov %c[r8](%[svm]), %%r8 \n\t"
3906 "mov %c[r9](%[svm]), %%r9 \n\t"
3907 "mov %c[r10](%[svm]), %%r10 \n\t"
3908 "mov %c[r11](%[svm]), %%r11 \n\t"
3909 "mov %c[r12](%[svm]), %%r12 \n\t"
3910 "mov %c[r13](%[svm]), %%r13 \n\t"
3911 "mov %c[r14](%[svm]), %%r14 \n\t"
3912 "mov %c[r15](%[svm]), %%r15 \n\t"
3915 /* Enter guest mode */
3916 "push %%" _ASM_AX
" \n\t"
3917 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
3918 __ex(SVM_VMLOAD
) "\n\t"
3919 __ex(SVM_VMRUN
) "\n\t"
3920 __ex(SVM_VMSAVE
) "\n\t"
3921 "pop %%" _ASM_AX
" \n\t"
3923 /* Save guest registers, load host registers */
3924 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
3925 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
3926 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
3927 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
3928 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
3929 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
3930 #ifdef CONFIG_X86_64
3931 "mov %%r8, %c[r8](%[svm]) \n\t"
3932 "mov %%r9, %c[r9](%[svm]) \n\t"
3933 "mov %%r10, %c[r10](%[svm]) \n\t"
3934 "mov %%r11, %c[r11](%[svm]) \n\t"
3935 "mov %%r12, %c[r12](%[svm]) \n\t"
3936 "mov %%r13, %c[r13](%[svm]) \n\t"
3937 "mov %%r14, %c[r14](%[svm]) \n\t"
3938 "mov %%r15, %c[r15](%[svm]) \n\t"
3943 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3944 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3945 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3946 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3947 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3948 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3949 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3950 #ifdef CONFIG_X86_64
3951 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3952 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3953 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3954 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3955 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3956 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3957 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3958 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3961 #ifdef CONFIG_X86_64
3962 , "rbx", "rcx", "rdx", "rsi", "rdi"
3963 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3965 , "ebx", "ecx", "edx", "esi", "edi"
3969 #ifdef CONFIG_X86_64
3970 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3972 loadsegment(fs
, svm
->host
.fs
);
3973 #ifndef CONFIG_X86_32_LAZY_GS
3974 loadsegment(gs
, svm
->host
.gs
);
3980 local_irq_disable();
3982 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3983 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3984 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3985 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3987 trace_kvm_exit(svm
->vmcb
->control
.exit_code
, vcpu
, KVM_ISA_SVM
);
3989 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3990 kvm_before_handle_nmi(&svm
->vcpu
);
3994 /* Any pending NMI will happen here */
3996 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3997 kvm_after_handle_nmi(&svm
->vcpu
);
3999 sync_cr8_to_lapic(vcpu
);
4003 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
4005 /* if exit due to PF check for async PF */
4006 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
4007 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
4010 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
4011 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
4015 * We need to handle MC intercepts here before the vcpu has a chance to
4016 * change the physical cpu
4018 if (unlikely(svm
->vmcb
->control
.exit_code
==
4019 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
4020 svm_handle_mce(svm
);
4022 mark_all_clean(svm
->vmcb
);
4025 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4027 struct vcpu_svm
*svm
= to_svm(vcpu
);
4029 svm
->vmcb
->save
.cr3
= root
;
4030 mark_dirty(svm
->vmcb
, VMCB_CR
);
4031 svm_flush_tlb(vcpu
);
4034 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
4036 struct vcpu_svm
*svm
= to_svm(vcpu
);
4038 svm
->vmcb
->control
.nested_cr3
= root
;
4039 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4041 /* Also sync guest cr3 here in case we live migrate */
4042 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
4043 mark_dirty(svm
->vmcb
, VMCB_CR
);
4045 svm_flush_tlb(vcpu
);
4048 static int is_disabled(void)
4052 rdmsrl(MSR_VM_CR
, vm_cr
);
4053 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
4060 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4063 * Patch in the VMMCALL instruction:
4065 hypercall
[0] = 0x0f;
4066 hypercall
[1] = 0x01;
4067 hypercall
[2] = 0xd9;
4070 static void svm_check_processor_compat(void *rtn
)
4075 static bool svm_cpu_has_accelerated_tpr(void)
4080 static bool svm_has_high_real_mode_segbase(void)
4085 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4090 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
4092 struct vcpu_svm
*svm
= to_svm(vcpu
);
4094 /* Update nrips enabled cache */
4095 svm
->nrips_enabled
= !!guest_cpuid_has_nrips(&svm
->vcpu
);
4098 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4103 entry
->ecx
|= (1 << 2); /* Set SVM bit */
4106 entry
->eax
= 1; /* SVM revision 1 */
4107 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
4108 ASID emulation to nested SVM */
4109 entry
->ecx
= 0; /* Reserved */
4110 entry
->edx
= 0; /* Per default do not support any
4111 additional features */
4113 /* Support next_rip if host supports it */
4114 if (boot_cpu_has(X86_FEATURE_NRIPS
))
4115 entry
->edx
|= SVM_FEATURE_NRIP
;
4117 /* Support NPT for the guest if enabled */
4119 entry
->edx
|= SVM_FEATURE_NPT
;
4125 static int svm_get_lpage_level(void)
4127 return PT_PDPE_LEVEL
;
4130 static bool svm_rdtscp_supported(void)
4135 static bool svm_invpcid_supported(void)
4140 static bool svm_mpx_supported(void)
4145 static bool svm_xsaves_supported(void)
4150 static bool svm_has_wbinvd_exit(void)
4155 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
4157 struct vcpu_svm
*svm
= to_svm(vcpu
);
4159 set_exception_intercept(svm
, NM_VECTOR
);
4160 update_cr0_intercept(svm
);
4163 #define PRE_EX(exit) { .exit_code = (exit), \
4164 .stage = X86_ICPT_PRE_EXCEPT, }
4165 #define POST_EX(exit) { .exit_code = (exit), \
4166 .stage = X86_ICPT_POST_EXCEPT, }
4167 #define POST_MEM(exit) { .exit_code = (exit), \
4168 .stage = X86_ICPT_POST_MEMACCESS, }
4170 static const struct __x86_intercept
{
4172 enum x86_intercept_stage stage
;
4173 } x86_intercept_map
[] = {
4174 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4175 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4176 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4177 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4178 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4179 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4180 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4181 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4182 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4183 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4184 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4185 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4186 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4187 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4188 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4189 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4190 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4191 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4192 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4193 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4194 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4195 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4196 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4197 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4198 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4199 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4200 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4201 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4202 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4203 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4204 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4205 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4206 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4207 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4208 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4209 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4210 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4211 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4212 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4213 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4214 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4215 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4216 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4217 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4218 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4219 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4226 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4227 struct x86_instruction_info
*info
,
4228 enum x86_intercept_stage stage
)
4230 struct vcpu_svm
*svm
= to_svm(vcpu
);
4231 int vmexit
, ret
= X86EMUL_CONTINUE
;
4232 struct __x86_intercept icpt_info
;
4233 struct vmcb
*vmcb
= svm
->vmcb
;
4235 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4238 icpt_info
= x86_intercept_map
[info
->intercept
];
4240 if (stage
!= icpt_info
.stage
)
4243 switch (icpt_info
.exit_code
) {
4244 case SVM_EXIT_READ_CR0
:
4245 if (info
->intercept
== x86_intercept_cr_read
)
4246 icpt_info
.exit_code
+= info
->modrm_reg
;
4248 case SVM_EXIT_WRITE_CR0
: {
4249 unsigned long cr0
, val
;
4252 if (info
->intercept
== x86_intercept_cr_write
)
4253 icpt_info
.exit_code
+= info
->modrm_reg
;
4255 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
4256 info
->intercept
== x86_intercept_clts
)
4259 intercept
= svm
->nested
.intercept
;
4261 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
4264 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4265 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4267 if (info
->intercept
== x86_intercept_lmsw
) {
4270 /* lmsw can't clear PE - catch this here */
4271 if (cr0
& X86_CR0_PE
)
4276 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4280 case SVM_EXIT_READ_DR0
:
4281 case SVM_EXIT_WRITE_DR0
:
4282 icpt_info
.exit_code
+= info
->modrm_reg
;
4285 if (info
->intercept
== x86_intercept_wrmsr
)
4286 vmcb
->control
.exit_info_1
= 1;
4288 vmcb
->control
.exit_info_1
= 0;
4290 case SVM_EXIT_PAUSE
:
4292 * We get this for NOP only, but pause
4293 * is rep not, check this here
4295 if (info
->rep_prefix
!= REPE_PREFIX
)
4297 case SVM_EXIT_IOIO
: {
4301 if (info
->intercept
== x86_intercept_in
||
4302 info
->intercept
== x86_intercept_ins
) {
4303 exit_info
= ((info
->src_val
& 0xffff) << 16) |
4305 bytes
= info
->dst_bytes
;
4307 exit_info
= (info
->dst_val
& 0xffff) << 16;
4308 bytes
= info
->src_bytes
;
4311 if (info
->intercept
== x86_intercept_outs
||
4312 info
->intercept
== x86_intercept_ins
)
4313 exit_info
|= SVM_IOIO_STR_MASK
;
4315 if (info
->rep_prefix
)
4316 exit_info
|= SVM_IOIO_REP_MASK
;
4318 bytes
= min(bytes
, 4u);
4320 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4322 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4324 vmcb
->control
.exit_info_1
= exit_info
;
4325 vmcb
->control
.exit_info_2
= info
->next_rip
;
4333 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4334 if (static_cpu_has(X86_FEATURE_NRIPS
))
4335 vmcb
->control
.next_rip
= info
->next_rip
;
4336 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4337 vmexit
= nested_svm_exit_handled(svm
);
4339 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4346 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
4351 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
4355 static struct kvm_x86_ops svm_x86_ops
= {
4356 .cpu_has_kvm_support
= has_svm
,
4357 .disabled_by_bios
= is_disabled
,
4358 .hardware_setup
= svm_hardware_setup
,
4359 .hardware_unsetup
= svm_hardware_unsetup
,
4360 .check_processor_compatibility
= svm_check_processor_compat
,
4361 .hardware_enable
= svm_hardware_enable
,
4362 .hardware_disable
= svm_hardware_disable
,
4363 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4364 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
4366 .vcpu_create
= svm_create_vcpu
,
4367 .vcpu_free
= svm_free_vcpu
,
4368 .vcpu_reset
= svm_vcpu_reset
,
4370 .prepare_guest_switch
= svm_prepare_guest_switch
,
4371 .vcpu_load
= svm_vcpu_load
,
4372 .vcpu_put
= svm_vcpu_put
,
4374 .update_db_bp_intercept
= update_db_bp_intercept
,
4375 .get_msr
= svm_get_msr
,
4376 .set_msr
= svm_set_msr
,
4377 .get_segment_base
= svm_get_segment_base
,
4378 .get_segment
= svm_get_segment
,
4379 .set_segment
= svm_set_segment
,
4380 .get_cpl
= svm_get_cpl
,
4381 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4382 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
4383 .decache_cr3
= svm_decache_cr3
,
4384 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
4385 .set_cr0
= svm_set_cr0
,
4386 .set_cr3
= svm_set_cr3
,
4387 .set_cr4
= svm_set_cr4
,
4388 .set_efer
= svm_set_efer
,
4389 .get_idt
= svm_get_idt
,
4390 .set_idt
= svm_set_idt
,
4391 .get_gdt
= svm_get_gdt
,
4392 .set_gdt
= svm_set_gdt
,
4393 .get_dr6
= svm_get_dr6
,
4394 .set_dr6
= svm_set_dr6
,
4395 .set_dr7
= svm_set_dr7
,
4396 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
4397 .cache_reg
= svm_cache_reg
,
4398 .get_rflags
= svm_get_rflags
,
4399 .set_rflags
= svm_set_rflags
,
4400 .fpu_activate
= svm_fpu_activate
,
4401 .fpu_deactivate
= svm_fpu_deactivate
,
4403 .tlb_flush
= svm_flush_tlb
,
4405 .run
= svm_vcpu_run
,
4406 .handle_exit
= handle_exit
,
4407 .skip_emulated_instruction
= skip_emulated_instruction
,
4408 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4409 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4410 .patch_hypercall
= svm_patch_hypercall
,
4411 .set_irq
= svm_set_irq
,
4412 .set_nmi
= svm_inject_nmi
,
4413 .queue_exception
= svm_queue_exception
,
4414 .cancel_injection
= svm_cancel_injection
,
4415 .interrupt_allowed
= svm_interrupt_allowed
,
4416 .nmi_allowed
= svm_nmi_allowed
,
4417 .get_nmi_mask
= svm_get_nmi_mask
,
4418 .set_nmi_mask
= svm_set_nmi_mask
,
4419 .enable_nmi_window
= enable_nmi_window
,
4420 .enable_irq_window
= enable_irq_window
,
4421 .update_cr8_intercept
= update_cr8_intercept
,
4422 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
4423 .cpu_uses_apicv
= svm_cpu_uses_apicv
,
4424 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
4425 .sync_pir_to_irr
= svm_sync_pir_to_irr
,
4427 .set_tss_addr
= svm_set_tss_addr
,
4428 .get_tdp_level
= get_npt_level
,
4429 .get_mt_mask
= svm_get_mt_mask
,
4431 .get_exit_info
= svm_get_exit_info
,
4433 .get_lpage_level
= svm_get_lpage_level
,
4435 .cpuid_update
= svm_cpuid_update
,
4437 .rdtscp_supported
= svm_rdtscp_supported
,
4438 .invpcid_supported
= svm_invpcid_supported
,
4439 .mpx_supported
= svm_mpx_supported
,
4440 .xsaves_supported
= svm_xsaves_supported
,
4442 .set_supported_cpuid
= svm_set_supported_cpuid
,
4444 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4446 .set_tsc_khz
= svm_set_tsc_khz
,
4447 .read_tsc_offset
= svm_read_tsc_offset
,
4448 .write_tsc_offset
= svm_write_tsc_offset
,
4449 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
4450 .compute_tsc_offset
= svm_compute_tsc_offset
,
4451 .read_l1_tsc
= svm_read_l1_tsc
,
4453 .set_tdp_cr3
= set_tdp_cr3
,
4455 .check_intercept
= svm_check_intercept
,
4456 .handle_external_intr
= svm_handle_external_intr
,
4458 .sched_in
= svm_sched_in
,
4460 .pmu_ops
= &amd_pmu_ops
,
4463 static int __init
svm_init(void)
4465 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
4466 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4469 static void __exit
svm_exit(void)
4474 module_init(svm_init
)
4475 module_exit(svm_exit
)